1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ESWIN SATA PHY driver 4 * 5 * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd.. 6 * All rights reserved. 7 * 8 * Authors: Yulin Lu <luyulin@eswincomputing.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regmap.h> 20 #include <linux/reset.h> 21 22 #define SATA_AXI_LP_CTRL 0x08 23 #define SATA_MPLL_CTRL 0x20 24 #define SATA_P0_PHY_STAT 0x24 25 #define SATA_PHY_CTRL0 0x28 26 #define SATA_PHY_CTRL1 0x2c 27 #define SATA_REF_CTRL 0x34 28 #define SATA_REF_CTRL1 0x38 29 #define SATA_LOS_IDEN 0x3c 30 31 #define SATA_CLK_RST_SOURCE_PHY BIT(0) 32 #define SATA_P0_PHY_TX_AMPLITUDE_GEN1_MASK GENMASK(6, 0) 33 #define SATA_P0_PHY_TX_AMPLITUDE_GEN1_DEFAULT 0x42 34 #define SATA_P0_PHY_TX_AMPLITUDE_GEN2_MASK GENMASK(14, 8) 35 #define SATA_P0_PHY_TX_AMPLITUDE_GEN2_DEFAULT 0x46 36 #define SATA_P0_PHY_TX_AMPLITUDE_GEN3_MASK GENMASK(22, 16) 37 #define SATA_P0_PHY_TX_AMPLITUDE_GEN3_DEFAULT 0x73 38 #define SATA_P0_PHY_TX_PREEMPH_GEN1_MASK GENMASK(5, 0) 39 #define SATA_P0_PHY_TX_PREEMPH_GEN1_DEFAULT 0x5 40 #define SATA_P0_PHY_TX_PREEMPH_GEN2_MASK GENMASK(13, 8) 41 #define SATA_P0_PHY_TX_PREEMPH_GEN2_DEFAULT 0x5 42 #define SATA_P0_PHY_TX_PREEMPH_GEN3_MASK GENMASK(21, 16) 43 #define SATA_P0_PHY_TX_PREEMPH_GEN3_DEFAULT 0x23 44 #define SATA_LOS_LEVEL_MASK GENMASK(4, 0) 45 #define SATA_LOS_BIAS_MASK GENMASK(18, 16) 46 #define SATA_M_CSYSREQ BIT(0) 47 #define SATA_S_CSYSREQ BIT(16) 48 #define SATA_REF_REPEATCLK_EN BIT(0) 49 #define SATA_REF_USE_PAD BIT(20) 50 #define SATA_MPLL_MULTIPLIER_MASK GENMASK(22, 16) 51 #define SATA_P0_PHY_READY BIT(0) 52 53 #define PLL_LOCK_SLEEP_US 10 54 #define PLL_LOCK_TIMEOUT_US 1000 55 56 struct eic7700_sata_phy { 57 u32 tx_amplitude_tuning_val[3]; 58 u32 tx_preemph_tuning_val[3]; 59 struct reset_control *rst; 60 struct regmap *regmap; 61 struct clk *clk; 62 struct phy *phy; 63 }; 64 65 static const struct regmap_config eic7700_sata_phy_regmap_config = { 66 .reg_bits = 32, 67 .val_bits = 32, 68 .reg_stride = 4, 69 .max_register = SATA_LOS_IDEN, 70 }; 71 72 static int wait_for_phy_ready(struct regmap *regmap, u32 reg, u32 checkbit, 73 u32 status) 74 { 75 u32 val; 76 int ret; 77 78 ret = regmap_read_poll_timeout(regmap, reg, val, 79 (val & checkbit) == status, 80 PLL_LOCK_SLEEP_US, PLL_LOCK_TIMEOUT_US); 81 82 return ret; 83 } 84 85 static int eic7700_sata_phy_init(struct phy *phy) 86 { 87 struct eic7700_sata_phy *sata_phy = phy_get_drvdata(phy); 88 u32 val; 89 int ret; 90 91 ret = clk_prepare_enable(sata_phy->clk); 92 if (ret) 93 return ret; 94 95 regmap_write(sata_phy->regmap, SATA_REF_CTRL1, SATA_CLK_RST_SOURCE_PHY); 96 97 val = FIELD_PREP(SATA_P0_PHY_TX_AMPLITUDE_GEN1_MASK, 98 sata_phy->tx_amplitude_tuning_val[0]) | 99 FIELD_PREP(SATA_P0_PHY_TX_AMPLITUDE_GEN2_MASK, 100 sata_phy->tx_amplitude_tuning_val[1]) | 101 FIELD_PREP(SATA_P0_PHY_TX_AMPLITUDE_GEN3_MASK, 102 sata_phy->tx_amplitude_tuning_val[2]); 103 regmap_write(sata_phy->regmap, SATA_PHY_CTRL0, val); 104 105 val = FIELD_PREP(SATA_P0_PHY_TX_PREEMPH_GEN1_MASK, 106 sata_phy->tx_preemph_tuning_val[0]) | 107 FIELD_PREP(SATA_P0_PHY_TX_PREEMPH_GEN2_MASK, 108 sata_phy->tx_preemph_tuning_val[1]) | 109 FIELD_PREP(SATA_P0_PHY_TX_PREEMPH_GEN3_MASK, 110 sata_phy->tx_preemph_tuning_val[2]); 111 regmap_write(sata_phy->regmap, SATA_PHY_CTRL1, val); 112 113 val = FIELD_PREP(SATA_LOS_LEVEL_MASK, 0x9) | 114 FIELD_PREP(SATA_LOS_BIAS_MASK, 0x2); 115 regmap_write(sata_phy->regmap, SATA_LOS_IDEN, val); 116 117 val = SATA_M_CSYSREQ | SATA_S_CSYSREQ; 118 regmap_write(sata_phy->regmap, SATA_AXI_LP_CTRL, val); 119 120 val = SATA_REF_REPEATCLK_EN | SATA_REF_USE_PAD; 121 regmap_write(sata_phy->regmap, SATA_REF_CTRL, val); 122 123 val = FIELD_PREP(SATA_MPLL_MULTIPLIER_MASK, 0x3c); 124 regmap_write(sata_phy->regmap, SATA_MPLL_CTRL, val); 125 126 usleep_range(15, 20); 127 128 ret = reset_control_deassert(sata_phy->rst); 129 if (ret) 130 goto disable_clk; 131 132 ret = wait_for_phy_ready(sata_phy->regmap, SATA_P0_PHY_STAT, 133 SATA_P0_PHY_READY, 1); 134 if (ret < 0) { 135 dev_err(&sata_phy->phy->dev, "PHY READY check failed\n"); 136 goto disable_clk; 137 } 138 139 return 0; 140 141 disable_clk: 142 clk_disable_unprepare(sata_phy->clk); 143 return ret; 144 } 145 146 static int eic7700_sata_phy_exit(struct phy *phy) 147 { 148 struct eic7700_sata_phy *sata_phy = phy_get_drvdata(phy); 149 int ret; 150 151 ret = reset_control_assert(sata_phy->rst); 152 if (ret) 153 return ret; 154 155 clk_disable_unprepare(sata_phy->clk); 156 157 return 0; 158 } 159 160 static const struct phy_ops eic7700_sata_phy_ops = { 161 .init = eic7700_sata_phy_init, 162 .exit = eic7700_sata_phy_exit, 163 .owner = THIS_MODULE, 164 }; 165 166 static void eic7700_get_tuning_param(struct device_node *np, 167 struct eic7700_sata_phy *sata_phy) 168 { 169 if (of_property_read_u32_array 170 (np, "eswin,tx-amplitude-tuning", 171 sata_phy->tx_amplitude_tuning_val, 172 ARRAY_SIZE(sata_phy->tx_amplitude_tuning_val))) { 173 sata_phy->tx_amplitude_tuning_val[0] = 174 SATA_P0_PHY_TX_AMPLITUDE_GEN1_DEFAULT; 175 sata_phy->tx_amplitude_tuning_val[1] = 176 SATA_P0_PHY_TX_AMPLITUDE_GEN2_DEFAULT; 177 sata_phy->tx_amplitude_tuning_val[2] = 178 SATA_P0_PHY_TX_AMPLITUDE_GEN3_DEFAULT; 179 } 180 181 if (of_property_read_u32_array 182 (np, "eswin,tx-preemph-tuning", 183 sata_phy->tx_preemph_tuning_val, 184 ARRAY_SIZE(sata_phy->tx_preemph_tuning_val))) { 185 sata_phy->tx_preemph_tuning_val[0] = 186 SATA_P0_PHY_TX_PREEMPH_GEN1_DEFAULT; 187 sata_phy->tx_preemph_tuning_val[1] = 188 SATA_P0_PHY_TX_PREEMPH_GEN2_DEFAULT; 189 sata_phy->tx_preemph_tuning_val[2] = 190 SATA_P0_PHY_TX_PREEMPH_GEN3_DEFAULT; 191 } 192 } 193 194 static int eic7700_sata_phy_probe(struct platform_device *pdev) 195 { 196 struct eic7700_sata_phy *sata_phy; 197 struct phy_provider *phy_provider; 198 struct device *dev = &pdev->dev; 199 struct device_node *np = dev->of_node; 200 struct resource *res; 201 void __iomem *regs; 202 203 sata_phy = devm_kzalloc(dev, sizeof(*sata_phy), GFP_KERNEL); 204 if (!sata_phy) 205 return -ENOMEM; 206 207 /* 208 * Map the I/O resource with platform_get_resource and devm_ioremap 209 * instead of the devm_platform_ioremap_resource API, because the 210 * address region of the SATA-PHY falls into the region of the HSP 211 * clock & reset that has already been obtained by the HSP 212 * clock-and-reset driver. 213 */ 214 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 215 if (!res) 216 return -ENOENT; 217 218 regs = devm_ioremap(dev, res->start, resource_size(res)); 219 if (IS_ERR(regs)) 220 return PTR_ERR(regs); 221 222 sata_phy->regmap = devm_regmap_init_mmio 223 (dev, regs, &eic7700_sata_phy_regmap_config); 224 if (IS_ERR(sata_phy->regmap)) 225 return dev_err_probe(dev, PTR_ERR(sata_phy->regmap), 226 "failed to init regmap\n"); 227 228 dev_set_drvdata(dev, sata_phy); 229 230 eic7700_get_tuning_param(np, sata_phy); 231 232 sata_phy->clk = devm_clk_get(dev, "phy"); 233 if (IS_ERR(sata_phy->clk)) 234 return PTR_ERR(sata_phy->clk); 235 236 sata_phy->rst = devm_reset_control_array_get_exclusive(dev); 237 if (IS_ERR(sata_phy->rst)) 238 return dev_err_probe(dev, PTR_ERR(sata_phy->rst), 239 "failed to get reset control\n"); 240 241 sata_phy->phy = devm_phy_create(dev, NULL, &eic7700_sata_phy_ops); 242 if (IS_ERR(sata_phy->phy)) 243 return dev_err_probe(dev, PTR_ERR(sata_phy->phy), 244 "failed to create PHY\n"); 245 246 phy_set_drvdata(sata_phy->phy, sata_phy); 247 248 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 249 if (IS_ERR(phy_provider)) 250 return dev_err_probe(dev, PTR_ERR(phy_provider), 251 "failed to register PHY provider\n"); 252 253 return 0; 254 } 255 256 static const struct of_device_id eic7700_sata_phy_of_match[] = { 257 { .compatible = "eswin,eic7700-sata-phy" }, 258 { }, 259 }; 260 MODULE_DEVICE_TABLE(of, eic7700_sata_phy_of_match); 261 262 static struct platform_driver eic7700_sata_phy_driver = { 263 .probe = eic7700_sata_phy_probe, 264 .driver = { 265 .of_match_table = eic7700_sata_phy_of_match, 266 .name = "eic7700-sata-phy", 267 } 268 }; 269 module_platform_driver(eic7700_sata_phy_driver); 270 271 MODULE_DESCRIPTION("SATA PHY driver for the ESWIN EIC7700 SoC"); 272 MODULE_AUTHOR("Yulin Lu <luyulin@eswincomputing.com>"); 273 MODULE_LICENSE("GPL"); 274