1# SPDX-License-Identifier: GPL-2.0-only 2# 3# PHY 4# 5 6menu "PHY Subsystem" 7 8config GENERIC_PHY 9 bool "PHY Core" 10 help 11 Generic PHY support. 12 13 This framework is designed to provide a generic interface for PHY 14 devices present in the kernel. This layer will have the generic 15 API by which phy drivers can create PHY using the phy framework and 16 phy users can obtain reference to the PHY. All the users of this 17 framework should select this config. 18 19config GENERIC_PHY_MIPI_DPHY 20 bool 21 select GENERIC_PHY 22 help 23 Generic MIPI D-PHY support. 24 25 Provides a number of helpers a core functions for MIPI D-PHY 26 drivers to us. 27 28config PHY_LPC18XX_USB_OTG 29 tristate "NXP LPC18xx/43xx SoC USB OTG PHY driver" 30 depends on OF && (ARCH_LPC18XX || COMPILE_TEST) 31 depends on MFD_SYSCON 32 select GENERIC_PHY 33 help 34 Enable this to support NXP LPC18xx/43xx internal USB OTG PHY. 35 36 This driver is need for USB0 support on LPC18xx/43xx and takes 37 care of enabling and clock setup. 38 39config PHY_PISTACHIO_USB 40 tristate "IMG Pistachio USB2.0 PHY driver" 41 depends on MIPS || COMPILE_TEST 42 select GENERIC_PHY 43 help 44 Enable this to support the USB2.0 PHY on the IMG Pistachio SoC. 45 46config PHY_XGENE 47 tristate "APM X-Gene 15Gbps PHY support" 48 depends on HAS_IOMEM && OF && (ARCH_XGENE || COMPILE_TEST) 49 select GENERIC_PHY 50 help 51 This option enables support for APM X-Gene SoC multi-purpose PHY. 52 53config USB_LGM_PHY 54 tristate "INTEL Lightning Mountain USB PHY Driver" 55 depends on USB_SUPPORT 56 depends on X86 || COMPILE_TEST 57 select USB_PHY 58 select REGULATOR 59 select REGULATOR_FIXED_VOLTAGE 60 help 61 Enable this to support Intel DWC3 PHY USB phy. This driver provides 62 interface to interact with USB GEN-II and USB 3.x PHY that is part 63 of the Intel network SOC. 64 65config PHY_CAN_TRANSCEIVER 66 tristate "CAN transceiver PHY" 67 select GENERIC_PHY 68 select MULTIPLEXER 69 help 70 This option enables support for CAN transceivers as a PHY. This 71 driver provides function for putting the transceivers in various 72 functional modes using gpios and sets the attribute max link 73 rate, for CAN drivers. 74 75config PHY_AIROHA_PCIE 76 tristate "Airoha PCIe-PHY Driver" 77 depends on ARCH_AIROHA || COMPILE_TEST 78 depends on OF 79 select GENERIC_PHY 80 help 81 Say Y here to add support for Airoha PCIe PHY driver. 82 This driver create the basic PHY instance and provides initialize 83 callback for PCIe GEN3 port. 84 85source "drivers/phy/allwinner/Kconfig" 86source "drivers/phy/amlogic/Kconfig" 87source "drivers/phy/broadcom/Kconfig" 88source "drivers/phy/cadence/Kconfig" 89source "drivers/phy/freescale/Kconfig" 90source "drivers/phy/hisilicon/Kconfig" 91source "drivers/phy/ingenic/Kconfig" 92source "drivers/phy/lantiq/Kconfig" 93source "drivers/phy/marvell/Kconfig" 94source "drivers/phy/mediatek/Kconfig" 95source "drivers/phy/microchip/Kconfig" 96source "drivers/phy/motorola/Kconfig" 97source "drivers/phy/mscc/Kconfig" 98source "drivers/phy/qualcomm/Kconfig" 99source "drivers/phy/ralink/Kconfig" 100source "drivers/phy/realtek/Kconfig" 101source "drivers/phy/renesas/Kconfig" 102source "drivers/phy/rockchip/Kconfig" 103source "drivers/phy/samsung/Kconfig" 104source "drivers/phy/socionext/Kconfig" 105source "drivers/phy/st/Kconfig" 106source "drivers/phy/starfive/Kconfig" 107source "drivers/phy/sunplus/Kconfig" 108source "drivers/phy/tegra/Kconfig" 109source "drivers/phy/ti/Kconfig" 110source "drivers/phy/intel/Kconfig" 111source "drivers/phy/xilinx/Kconfig" 112 113endmenu 114