1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Aardvark PCIe controller, used on Marvell Armada 4 * 3700. 5 * 6 * Copyright (C) 2016 Marvell 7 * 8 * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com> 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/interrupt.h> 13 #include <linux/irq.h> 14 #include <linux/irqdomain.h> 15 #include <linux/kernel.h> 16 #include <linux/pci.h> 17 #include <linux/init.h> 18 #include <linux/platform_device.h> 19 #include <linux/of_address.h> 20 #include <linux/of_pci.h> 21 22 #include "../pci.h" 23 #include "../pci-bridge-emul.h" 24 25 /* PCIe core registers */ 26 #define PCIE_CORE_DEV_ID_REG 0x0 27 #define PCIE_CORE_CMD_STATUS_REG 0x4 28 #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0) 29 #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1) 30 #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2) 31 #define PCIE_CORE_DEV_REV_REG 0x8 32 #define PCIE_CORE_PCIEXP_CAP 0xc0 33 #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8 34 #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4) 35 #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5 36 #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11) 37 #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12 38 #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2 39 #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0 40 #define PCIE_CORE_LINK_L0S_ENTRY BIT(0) 41 #define PCIE_CORE_LINK_TRAINING BIT(5) 42 #define PCIE_CORE_LINK_WIDTH_SHIFT 20 43 #define PCIE_CORE_ERR_CAPCTL_REG 0x118 44 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5) 45 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6) 46 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7) 47 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8) 48 #define PCIE_CORE_INT_A_ASSERT_ENABLE 1 49 #define PCIE_CORE_INT_B_ASSERT_ENABLE 2 50 #define PCIE_CORE_INT_C_ASSERT_ENABLE 3 51 #define PCIE_CORE_INT_D_ASSERT_ENABLE 4 52 /* PIO registers base address and register offsets */ 53 #define PIO_BASE_ADDR 0x4000 54 #define PIO_CTRL (PIO_BASE_ADDR + 0x0) 55 #define PIO_CTRL_TYPE_MASK GENMASK(3, 0) 56 #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24) 57 #define PIO_STAT (PIO_BASE_ADDR + 0x4) 58 #define PIO_COMPLETION_STATUS_SHIFT 7 59 #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7) 60 #define PIO_COMPLETION_STATUS_OK 0 61 #define PIO_COMPLETION_STATUS_UR 1 62 #define PIO_COMPLETION_STATUS_CRS 2 63 #define PIO_COMPLETION_STATUS_CA 4 64 #define PIO_NON_POSTED_REQ BIT(0) 65 #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8) 66 #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc) 67 #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10) 68 #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14) 69 #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18) 70 #define PIO_START (PIO_BASE_ADDR + 0x1c) 71 #define PIO_ISR (PIO_BASE_ADDR + 0x20) 72 #define PIO_ISRM (PIO_BASE_ADDR + 0x24) 73 74 /* Aardvark Control registers */ 75 #define CONTROL_BASE_ADDR 0x4800 76 #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0) 77 #define PCIE_GEN_SEL_MSK 0x3 78 #define PCIE_GEN_SEL_SHIFT 0x0 79 #define SPEED_GEN_1 0 80 #define SPEED_GEN_2 1 81 #define SPEED_GEN_3 2 82 #define IS_RC_MSK 1 83 #define IS_RC_SHIFT 2 84 #define LANE_CNT_MSK 0x18 85 #define LANE_CNT_SHIFT 0x3 86 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT) 87 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT) 88 #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT) 89 #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT) 90 #define LINK_TRAINING_EN BIT(6) 91 #define LEGACY_INTA BIT(28) 92 #define LEGACY_INTB BIT(29) 93 #define LEGACY_INTC BIT(30) 94 #define LEGACY_INTD BIT(31) 95 #define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4) 96 #define HOT_RESET_GEN BIT(0) 97 #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8) 98 #define PCIE_CORE_CTRL2_RESERVED 0x7 99 #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4) 100 #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5) 101 #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6) 102 #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10) 103 #define PCIE_MSG_LOG_REG (CONTROL_BASE_ADDR + 0x30) 104 #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40) 105 #define PCIE_MSG_PM_PME_MASK BIT(7) 106 #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44) 107 #define PCIE_ISR0_MSI_INT_PENDING BIT(24) 108 #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val)) 109 #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val)) 110 #define PCIE_ISR0_ALL_MASK GENMASK(26, 0) 111 #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48) 112 #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C) 113 #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4) 114 #define PCIE_ISR1_FLUSH BIT(5) 115 #define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val)) 116 #define PCIE_ISR1_ALL_MASK GENMASK(11, 4) 117 #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50) 118 #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54) 119 #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58) 120 #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C) 121 #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C) 122 123 /* LMI registers base address and register offsets */ 124 #define LMI_BASE_ADDR 0x6000 125 #define CFG_REG (LMI_BASE_ADDR + 0x0) 126 #define LTSSM_SHIFT 24 127 #define LTSSM_MASK 0x3f 128 #define LTSSM_L0 0x10 129 #define RC_BAR_CONFIG 0x300 130 131 /* PCIe core controller registers */ 132 #define CTRL_CORE_BASE_ADDR 0x18000 133 #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0) 134 #define CTRL_MODE_SHIFT 0x0 135 #define CTRL_MODE_MASK 0x1 136 #define PCIE_CORE_MODE_DIRECT 0x0 137 #define PCIE_CORE_MODE_COMMAND 0x1 138 139 /* PCIe Central Interrupts Registers */ 140 #define CENTRAL_INT_BASE_ADDR 0x1b000 141 #define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0) 142 #define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4) 143 #define PCIE_IRQ_CMDQ_INT BIT(0) 144 #define PCIE_IRQ_MSI_STATUS_INT BIT(1) 145 #define PCIE_IRQ_CMD_SENT_DONE BIT(3) 146 #define PCIE_IRQ_DMA_INT BIT(4) 147 #define PCIE_IRQ_IB_DXFERDONE BIT(5) 148 #define PCIE_IRQ_OB_DXFERDONE BIT(6) 149 #define PCIE_IRQ_OB_RXFERDONE BIT(7) 150 #define PCIE_IRQ_COMPQ_INT BIT(12) 151 #define PCIE_IRQ_DIR_RD_DDR_DET BIT(13) 152 #define PCIE_IRQ_DIR_WR_DDR_DET BIT(14) 153 #define PCIE_IRQ_CORE_INT BIT(16) 154 #define PCIE_IRQ_CORE_INT_PIO BIT(17) 155 #define PCIE_IRQ_DPMU_INT BIT(18) 156 #define PCIE_IRQ_PCIE_MIS_INT BIT(19) 157 #define PCIE_IRQ_MSI_INT1_DET BIT(20) 158 #define PCIE_IRQ_MSI_INT2_DET BIT(21) 159 #define PCIE_IRQ_RC_DBELL_DET BIT(22) 160 #define PCIE_IRQ_EP_STATUS BIT(23) 161 #define PCIE_IRQ_ALL_MASK 0xfff0fb 162 #define PCIE_IRQ_ENABLE_INTS_MASK PCIE_IRQ_CORE_INT 163 164 /* Transaction types */ 165 #define PCIE_CONFIG_RD_TYPE0 0x8 166 #define PCIE_CONFIG_RD_TYPE1 0x9 167 #define PCIE_CONFIG_WR_TYPE0 0xa 168 #define PCIE_CONFIG_WR_TYPE1 0xb 169 170 #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20) 171 #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15) 172 #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12) 173 #define PCIE_CONF_REG(reg) ((reg) & 0xffc) 174 #define PCIE_CONF_ADDR(bus, devfn, where) \ 175 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \ 176 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where)) 177 178 #define PIO_TIMEOUT_MS 1 179 180 #define LINK_WAIT_MAX_RETRIES 10 181 #define LINK_WAIT_USLEEP_MIN 90000 182 #define LINK_WAIT_USLEEP_MAX 100000 183 184 #define MSI_IRQ_NUM 32 185 186 struct advk_pcie { 187 struct platform_device *pdev; 188 void __iomem *base; 189 struct list_head resources; 190 struct irq_domain *irq_domain; 191 struct irq_chip irq_chip; 192 struct irq_domain *msi_domain; 193 struct irq_domain *msi_inner_domain; 194 struct irq_chip msi_bottom_irq_chip; 195 struct irq_chip msi_irq_chip; 196 struct msi_domain_info msi_domain_info; 197 DECLARE_BITMAP(msi_used, MSI_IRQ_NUM); 198 struct mutex msi_used_lock; 199 u16 msi_msg; 200 int root_bus_nr; 201 struct pci_bridge_emul bridge; 202 }; 203 204 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) 205 { 206 writel(val, pcie->base + reg); 207 } 208 209 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) 210 { 211 return readl(pcie->base + reg); 212 } 213 214 static int advk_pcie_link_up(struct advk_pcie *pcie) 215 { 216 u32 val, ltssm_state; 217 218 val = advk_readl(pcie, CFG_REG); 219 ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK; 220 return ltssm_state >= LTSSM_L0; 221 } 222 223 static int advk_pcie_wait_for_link(struct advk_pcie *pcie) 224 { 225 struct device *dev = &pcie->pdev->dev; 226 int retries; 227 228 /* check if the link is up or not */ 229 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { 230 if (advk_pcie_link_up(pcie)) { 231 dev_info(dev, "link up\n"); 232 return 0; 233 } 234 235 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); 236 } 237 238 dev_err(dev, "link never came up\n"); 239 return -ETIMEDOUT; 240 } 241 242 static void advk_pcie_setup_hw(struct advk_pcie *pcie) 243 { 244 u32 reg; 245 246 /* Set to Direct mode */ 247 reg = advk_readl(pcie, CTRL_CONFIG_REG); 248 reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT); 249 reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT); 250 advk_writel(pcie, reg, CTRL_CONFIG_REG); 251 252 /* Set PCI global control register to RC mode */ 253 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 254 reg |= (IS_RC_MSK << IS_RC_SHIFT); 255 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 256 257 /* Set Advanced Error Capabilities and Control PF0 register */ 258 reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX | 259 PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN | 260 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK | 261 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV; 262 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG); 263 264 /* Set PCIe Device Control and Status 1 PF0 register */ 265 reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE | 266 (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) | 267 PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE | 268 (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ << 269 PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT); 270 advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG); 271 272 /* Program PCIe Control 2 to disable strict ordering */ 273 reg = PCIE_CORE_CTRL2_RESERVED | 274 PCIE_CORE_CTRL2_TD_ENABLE; 275 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); 276 277 /* Set GEN2 */ 278 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 279 reg &= ~PCIE_GEN_SEL_MSK; 280 reg |= SPEED_GEN_2; 281 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 282 283 /* Set lane X1 */ 284 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 285 reg &= ~LANE_CNT_MSK; 286 reg |= LANE_COUNT_1; 287 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 288 289 /* Enable link training */ 290 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); 291 reg |= LINK_TRAINING_EN; 292 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); 293 294 /* Enable MSI */ 295 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); 296 reg |= PCIE_CORE_CTRL2_MSI_ENABLE; 297 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); 298 299 /* Clear all interrupts */ 300 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG); 301 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); 302 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); 303 304 /* Disable All ISR0/1 Sources */ 305 reg = PCIE_ISR0_ALL_MASK; 306 reg &= ~PCIE_ISR0_MSI_INT_PENDING; 307 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); 308 309 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); 310 311 /* Unmask all MSI's */ 312 advk_writel(pcie, 0, PCIE_MSI_MASK_REG); 313 314 /* Enable summary interrupt for GIC SPI source */ 315 reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK); 316 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG); 317 318 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); 319 reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE; 320 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); 321 322 /* Bypass the address window mapping for PIO */ 323 reg = advk_readl(pcie, PIO_CTRL); 324 reg |= PIO_CTRL_ADDR_WIN_DISABLE; 325 advk_writel(pcie, reg, PIO_CTRL); 326 327 /* Start link training */ 328 reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG); 329 reg |= PCIE_CORE_LINK_TRAINING; 330 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); 331 332 advk_pcie_wait_for_link(pcie); 333 334 reg = PCIE_CORE_LINK_L0S_ENTRY | 335 (1 << PCIE_CORE_LINK_WIDTH_SHIFT); 336 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); 337 338 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); 339 reg |= PCIE_CORE_CMD_MEM_ACCESS_EN | 340 PCIE_CORE_CMD_IO_ACCESS_EN | 341 PCIE_CORE_CMD_MEM_IO_REQ_EN; 342 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); 343 } 344 345 static void advk_pcie_check_pio_status(struct advk_pcie *pcie) 346 { 347 struct device *dev = &pcie->pdev->dev; 348 u32 reg; 349 unsigned int status; 350 char *strcomp_status, *str_posted; 351 352 reg = advk_readl(pcie, PIO_STAT); 353 status = (reg & PIO_COMPLETION_STATUS_MASK) >> 354 PIO_COMPLETION_STATUS_SHIFT; 355 356 if (!status) 357 return; 358 359 switch (status) { 360 case PIO_COMPLETION_STATUS_UR: 361 strcomp_status = "UR"; 362 break; 363 case PIO_COMPLETION_STATUS_CRS: 364 strcomp_status = "CRS"; 365 break; 366 case PIO_COMPLETION_STATUS_CA: 367 strcomp_status = "CA"; 368 break; 369 default: 370 strcomp_status = "Unknown"; 371 break; 372 } 373 374 if (reg & PIO_NON_POSTED_REQ) 375 str_posted = "Non-posted"; 376 else 377 str_posted = "Posted"; 378 379 dev_err(dev, "%s PIO Response Status: %s, %#x @ %#x\n", 380 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); 381 } 382 383 static int advk_pcie_wait_pio(struct advk_pcie *pcie) 384 { 385 struct device *dev = &pcie->pdev->dev; 386 unsigned long timeout; 387 388 timeout = jiffies + msecs_to_jiffies(PIO_TIMEOUT_MS); 389 390 while (time_before(jiffies, timeout)) { 391 u32 start, isr; 392 393 start = advk_readl(pcie, PIO_START); 394 isr = advk_readl(pcie, PIO_ISR); 395 if (!start && isr) 396 return 0; 397 } 398 399 dev_err(dev, "config read/write timed out\n"); 400 return -ETIMEDOUT; 401 } 402 403 404 static pci_bridge_emul_read_status_t 405 advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge, 406 int reg, u32 *value) 407 { 408 struct advk_pcie *pcie = bridge->data; 409 410 411 switch (reg) { 412 case PCI_EXP_SLTCTL: 413 *value = PCI_EXP_SLTSTA_PDS << 16; 414 return PCI_BRIDGE_EMUL_HANDLED; 415 416 case PCI_EXP_RTCTL: { 417 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG); 418 *value = (val & PCIE_MSG_PM_PME_MASK) ? PCI_EXP_RTCTL_PMEIE : 0; 419 return PCI_BRIDGE_EMUL_HANDLED; 420 } 421 422 case PCI_EXP_RTSTA: { 423 u32 isr0 = advk_readl(pcie, PCIE_ISR0_REG); 424 u32 msglog = advk_readl(pcie, PCIE_MSG_LOG_REG); 425 *value = (isr0 & PCIE_MSG_PM_PME_MASK) << 16 | (msglog >> 16); 426 return PCI_BRIDGE_EMUL_HANDLED; 427 } 428 429 case PCI_CAP_LIST_ID: 430 case PCI_EXP_DEVCAP: 431 case PCI_EXP_DEVCTL: 432 case PCI_EXP_LNKCAP: 433 case PCI_EXP_LNKCTL: 434 *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); 435 return PCI_BRIDGE_EMUL_HANDLED; 436 default: 437 return PCI_BRIDGE_EMUL_NOT_HANDLED; 438 } 439 440 } 441 442 static void 443 advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge, 444 int reg, u32 old, u32 new, u32 mask) 445 { 446 struct advk_pcie *pcie = bridge->data; 447 448 switch (reg) { 449 case PCI_EXP_DEVCTL: 450 case PCI_EXP_LNKCTL: 451 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); 452 break; 453 454 case PCI_EXP_RTCTL: 455 new = (new & PCI_EXP_RTCTL_PMEIE) << 3; 456 advk_writel(pcie, new, PCIE_ISR0_MASK_REG); 457 break; 458 459 case PCI_EXP_RTSTA: 460 new = (new & PCI_EXP_RTSTA_PME) >> 9; 461 advk_writel(pcie, new, PCIE_ISR0_REG); 462 break; 463 464 default: 465 break; 466 } 467 } 468 469 static struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = { 470 .read_pcie = advk_pci_bridge_emul_pcie_conf_read, 471 .write_pcie = advk_pci_bridge_emul_pcie_conf_write, 472 }; 473 474 /* 475 * Initialize the configuration space of the PCI-to-PCI bridge 476 * associated with the given PCIe interface. 477 */ 478 static void advk_sw_pci_bridge_init(struct advk_pcie *pcie) 479 { 480 struct pci_bridge_emul *bridge = &pcie->bridge; 481 482 bridge->conf.vendor = advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff; 483 bridge->conf.device = advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16; 484 bridge->conf.class_revision = 485 advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff; 486 487 /* Support 32 bits I/O addressing */ 488 bridge->conf.iobase = PCI_IO_RANGE_TYPE_32; 489 bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32; 490 491 /* Support 64 bits memory pref */ 492 bridge->conf.pref_mem_base = PCI_PREF_RANGE_TYPE_64; 493 bridge->conf.pref_mem_limit = PCI_PREF_RANGE_TYPE_64; 494 495 /* Support interrupt A for MSI feature */ 496 bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE; 497 498 bridge->has_pcie = true; 499 bridge->data = pcie; 500 bridge->ops = &advk_pci_bridge_emul_ops; 501 502 pci_bridge_emul_init(bridge, 0); 503 504 } 505 506 static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus, 507 int devfn) 508 { 509 if ((bus->number == pcie->root_bus_nr) && PCI_SLOT(devfn) != 0) 510 return false; 511 512 return true; 513 } 514 515 static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn, 516 int where, int size, u32 *val) 517 { 518 struct advk_pcie *pcie = bus->sysdata; 519 u32 reg; 520 int ret; 521 522 if (!advk_pcie_valid_device(pcie, bus, devfn)) { 523 *val = 0xffffffff; 524 return PCIBIOS_DEVICE_NOT_FOUND; 525 } 526 527 if (bus->number == pcie->root_bus_nr) 528 return pci_bridge_emul_conf_read(&pcie->bridge, where, 529 size, val); 530 531 /* Start PIO */ 532 advk_writel(pcie, 0, PIO_START); 533 advk_writel(pcie, 1, PIO_ISR); 534 535 /* Program the control register */ 536 reg = advk_readl(pcie, PIO_CTRL); 537 reg &= ~PIO_CTRL_TYPE_MASK; 538 if (bus->primary == pcie->root_bus_nr) 539 reg |= PCIE_CONFIG_RD_TYPE0; 540 else 541 reg |= PCIE_CONFIG_RD_TYPE1; 542 advk_writel(pcie, reg, PIO_CTRL); 543 544 /* Program the address registers */ 545 reg = PCIE_CONF_ADDR(bus->number, devfn, where); 546 advk_writel(pcie, reg, PIO_ADDR_LS); 547 advk_writel(pcie, 0, PIO_ADDR_MS); 548 549 /* Program the data strobe */ 550 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB); 551 552 /* Start the transfer */ 553 advk_writel(pcie, 1, PIO_START); 554 555 ret = advk_pcie_wait_pio(pcie); 556 if (ret < 0) 557 return PCIBIOS_SET_FAILED; 558 559 advk_pcie_check_pio_status(pcie); 560 561 /* Get the read result */ 562 *val = advk_readl(pcie, PIO_RD_DATA); 563 if (size == 1) 564 *val = (*val >> (8 * (where & 3))) & 0xff; 565 else if (size == 2) 566 *val = (*val >> (8 * (where & 3))) & 0xffff; 567 568 return PCIBIOS_SUCCESSFUL; 569 } 570 571 static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn, 572 int where, int size, u32 val) 573 { 574 struct advk_pcie *pcie = bus->sysdata; 575 u32 reg; 576 u32 data_strobe = 0x0; 577 int offset; 578 int ret; 579 580 if (!advk_pcie_valid_device(pcie, bus, devfn)) 581 return PCIBIOS_DEVICE_NOT_FOUND; 582 583 if (bus->number == pcie->root_bus_nr) 584 return pci_bridge_emul_conf_write(&pcie->bridge, where, 585 size, val); 586 587 if (where % size) 588 return PCIBIOS_SET_FAILED; 589 590 /* Start PIO */ 591 advk_writel(pcie, 0, PIO_START); 592 advk_writel(pcie, 1, PIO_ISR); 593 594 /* Program the control register */ 595 reg = advk_readl(pcie, PIO_CTRL); 596 reg &= ~PIO_CTRL_TYPE_MASK; 597 if (bus->primary == pcie->root_bus_nr) 598 reg |= PCIE_CONFIG_WR_TYPE0; 599 else 600 reg |= PCIE_CONFIG_WR_TYPE1; 601 advk_writel(pcie, reg, PIO_CTRL); 602 603 /* Program the address registers */ 604 reg = PCIE_CONF_ADDR(bus->number, devfn, where); 605 advk_writel(pcie, reg, PIO_ADDR_LS); 606 advk_writel(pcie, 0, PIO_ADDR_MS); 607 608 /* Calculate the write strobe */ 609 offset = where & 0x3; 610 reg = val << (8 * offset); 611 data_strobe = GENMASK(size - 1, 0) << offset; 612 613 /* Program the data register */ 614 advk_writel(pcie, reg, PIO_WR_DATA); 615 616 /* Program the data strobe */ 617 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB); 618 619 /* Start the transfer */ 620 advk_writel(pcie, 1, PIO_START); 621 622 ret = advk_pcie_wait_pio(pcie); 623 if (ret < 0) 624 return PCIBIOS_SET_FAILED; 625 626 advk_pcie_check_pio_status(pcie); 627 628 return PCIBIOS_SUCCESSFUL; 629 } 630 631 static struct pci_ops advk_pcie_ops = { 632 .read = advk_pcie_rd_conf, 633 .write = advk_pcie_wr_conf, 634 }; 635 636 static void advk_msi_irq_compose_msi_msg(struct irq_data *data, 637 struct msi_msg *msg) 638 { 639 struct advk_pcie *pcie = irq_data_get_irq_chip_data(data); 640 phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg); 641 642 msg->address_lo = lower_32_bits(msi_msg); 643 msg->address_hi = upper_32_bits(msi_msg); 644 msg->data = data->irq; 645 } 646 647 static int advk_msi_set_affinity(struct irq_data *irq_data, 648 const struct cpumask *mask, bool force) 649 { 650 return -EINVAL; 651 } 652 653 static int advk_msi_irq_domain_alloc(struct irq_domain *domain, 654 unsigned int virq, 655 unsigned int nr_irqs, void *args) 656 { 657 struct advk_pcie *pcie = domain->host_data; 658 int hwirq, i; 659 660 mutex_lock(&pcie->msi_used_lock); 661 hwirq = bitmap_find_next_zero_area(pcie->msi_used, MSI_IRQ_NUM, 662 0, nr_irqs, 0); 663 if (hwirq >= MSI_IRQ_NUM) { 664 mutex_unlock(&pcie->msi_used_lock); 665 return -ENOSPC; 666 } 667 668 bitmap_set(pcie->msi_used, hwirq, nr_irqs); 669 mutex_unlock(&pcie->msi_used_lock); 670 671 for (i = 0; i < nr_irqs; i++) 672 irq_domain_set_info(domain, virq + i, hwirq + i, 673 &pcie->msi_bottom_irq_chip, 674 domain->host_data, handle_simple_irq, 675 NULL, NULL); 676 677 return hwirq; 678 } 679 680 static void advk_msi_irq_domain_free(struct irq_domain *domain, 681 unsigned int virq, unsigned int nr_irqs) 682 { 683 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 684 struct advk_pcie *pcie = domain->host_data; 685 686 mutex_lock(&pcie->msi_used_lock); 687 bitmap_clear(pcie->msi_used, d->hwirq, nr_irqs); 688 mutex_unlock(&pcie->msi_used_lock); 689 } 690 691 static const struct irq_domain_ops advk_msi_domain_ops = { 692 .alloc = advk_msi_irq_domain_alloc, 693 .free = advk_msi_irq_domain_free, 694 }; 695 696 static void advk_pcie_irq_mask(struct irq_data *d) 697 { 698 struct advk_pcie *pcie = d->domain->host_data; 699 irq_hw_number_t hwirq = irqd_to_hwirq(d); 700 u32 mask; 701 702 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); 703 mask |= PCIE_ISR1_INTX_ASSERT(hwirq); 704 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); 705 } 706 707 static void advk_pcie_irq_unmask(struct irq_data *d) 708 { 709 struct advk_pcie *pcie = d->domain->host_data; 710 irq_hw_number_t hwirq = irqd_to_hwirq(d); 711 u32 mask; 712 713 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); 714 mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq); 715 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); 716 } 717 718 static int advk_pcie_irq_map(struct irq_domain *h, 719 unsigned int virq, irq_hw_number_t hwirq) 720 { 721 struct advk_pcie *pcie = h->host_data; 722 723 advk_pcie_irq_mask(irq_get_irq_data(virq)); 724 irq_set_status_flags(virq, IRQ_LEVEL); 725 irq_set_chip_and_handler(virq, &pcie->irq_chip, 726 handle_level_irq); 727 irq_set_chip_data(virq, pcie); 728 729 return 0; 730 } 731 732 static const struct irq_domain_ops advk_pcie_irq_domain_ops = { 733 .map = advk_pcie_irq_map, 734 .xlate = irq_domain_xlate_onecell, 735 }; 736 737 static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) 738 { 739 struct device *dev = &pcie->pdev->dev; 740 struct device_node *node = dev->of_node; 741 struct irq_chip *bottom_ic, *msi_ic; 742 struct msi_domain_info *msi_di; 743 phys_addr_t msi_msg_phys; 744 745 mutex_init(&pcie->msi_used_lock); 746 747 bottom_ic = &pcie->msi_bottom_irq_chip; 748 749 bottom_ic->name = "MSI"; 750 bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg; 751 bottom_ic->irq_set_affinity = advk_msi_set_affinity; 752 753 msi_ic = &pcie->msi_irq_chip; 754 msi_ic->name = "advk-MSI"; 755 756 msi_di = &pcie->msi_domain_info; 757 msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 758 MSI_FLAG_MULTI_PCI_MSI; 759 msi_di->chip = msi_ic; 760 761 msi_msg_phys = virt_to_phys(&pcie->msi_msg); 762 763 advk_writel(pcie, lower_32_bits(msi_msg_phys), 764 PCIE_MSI_ADDR_LOW_REG); 765 advk_writel(pcie, upper_32_bits(msi_msg_phys), 766 PCIE_MSI_ADDR_HIGH_REG); 767 768 pcie->msi_inner_domain = 769 irq_domain_add_linear(NULL, MSI_IRQ_NUM, 770 &advk_msi_domain_ops, pcie); 771 if (!pcie->msi_inner_domain) 772 return -ENOMEM; 773 774 pcie->msi_domain = 775 pci_msi_create_irq_domain(of_node_to_fwnode(node), 776 msi_di, pcie->msi_inner_domain); 777 if (!pcie->msi_domain) { 778 irq_domain_remove(pcie->msi_inner_domain); 779 return -ENOMEM; 780 } 781 782 return 0; 783 } 784 785 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie) 786 { 787 irq_domain_remove(pcie->msi_domain); 788 irq_domain_remove(pcie->msi_inner_domain); 789 } 790 791 static int advk_pcie_init_irq_domain(struct advk_pcie *pcie) 792 { 793 struct device *dev = &pcie->pdev->dev; 794 struct device_node *node = dev->of_node; 795 struct device_node *pcie_intc_node; 796 struct irq_chip *irq_chip; 797 int ret = 0; 798 799 pcie_intc_node = of_get_next_child(node, NULL); 800 if (!pcie_intc_node) { 801 dev_err(dev, "No PCIe Intc node found\n"); 802 return -ENODEV; 803 } 804 805 irq_chip = &pcie->irq_chip; 806 807 irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq", 808 dev_name(dev)); 809 if (!irq_chip->name) { 810 ret = -ENOMEM; 811 goto out_put_node; 812 } 813 814 irq_chip->irq_mask = advk_pcie_irq_mask; 815 irq_chip->irq_mask_ack = advk_pcie_irq_mask; 816 irq_chip->irq_unmask = advk_pcie_irq_unmask; 817 818 pcie->irq_domain = 819 irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, 820 &advk_pcie_irq_domain_ops, pcie); 821 if (!pcie->irq_domain) { 822 dev_err(dev, "Failed to get a INTx IRQ domain\n"); 823 ret = -ENOMEM; 824 goto out_put_node; 825 } 826 827 out_put_node: 828 of_node_put(pcie_intc_node); 829 return ret; 830 } 831 832 static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie) 833 { 834 irq_domain_remove(pcie->irq_domain); 835 } 836 837 static void advk_pcie_handle_msi(struct advk_pcie *pcie) 838 { 839 u32 msi_val, msi_mask, msi_status, msi_idx; 840 u16 msi_data; 841 842 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); 843 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG); 844 msi_status = msi_val & ~msi_mask; 845 846 for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) { 847 if (!(BIT(msi_idx) & msi_status)) 848 continue; 849 850 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG); 851 msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & 0xFF; 852 generic_handle_irq(msi_data); 853 } 854 855 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING, 856 PCIE_ISR0_REG); 857 } 858 859 static void advk_pcie_handle_int(struct advk_pcie *pcie) 860 { 861 u32 isr0_val, isr0_mask, isr0_status; 862 u32 isr1_val, isr1_mask, isr1_status; 863 int i, virq; 864 865 isr0_val = advk_readl(pcie, PCIE_ISR0_REG); 866 isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG); 867 isr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK); 868 869 isr1_val = advk_readl(pcie, PCIE_ISR1_REG); 870 isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); 871 isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK); 872 873 if (!isr0_status && !isr1_status) { 874 advk_writel(pcie, isr0_val, PCIE_ISR0_REG); 875 advk_writel(pcie, isr1_val, PCIE_ISR1_REG); 876 return; 877 } 878 879 /* Process MSI interrupts */ 880 if (isr0_status & PCIE_ISR0_MSI_INT_PENDING) 881 advk_pcie_handle_msi(pcie); 882 883 /* Process legacy interrupts */ 884 for (i = 0; i < PCI_NUM_INTX; i++) { 885 if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i))) 886 continue; 887 888 advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i), 889 PCIE_ISR1_REG); 890 891 virq = irq_find_mapping(pcie->irq_domain, i); 892 generic_handle_irq(virq); 893 } 894 } 895 896 static irqreturn_t advk_pcie_irq_handler(int irq, void *arg) 897 { 898 struct advk_pcie *pcie = arg; 899 u32 status; 900 901 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG); 902 if (!(status & PCIE_IRQ_CORE_INT)) 903 return IRQ_NONE; 904 905 advk_pcie_handle_int(pcie); 906 907 /* Clear interrupt */ 908 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG); 909 910 return IRQ_HANDLED; 911 } 912 913 static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie) 914 { 915 int err, res_valid = 0; 916 struct device *dev = &pcie->pdev->dev; 917 struct resource_entry *win, *tmp; 918 resource_size_t iobase; 919 920 INIT_LIST_HEAD(&pcie->resources); 921 922 err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, 923 &pcie->resources, &iobase); 924 if (err) 925 return err; 926 927 err = devm_request_pci_bus_resources(dev, &pcie->resources); 928 if (err) 929 goto out_release_res; 930 931 resource_list_for_each_entry_safe(win, tmp, &pcie->resources) { 932 struct resource *res = win->res; 933 934 switch (resource_type(res)) { 935 case IORESOURCE_IO: 936 err = devm_pci_remap_iospace(dev, res, iobase); 937 if (err) { 938 dev_warn(dev, "error %d: failed to map resource %pR\n", 939 err, res); 940 resource_list_destroy_entry(win); 941 } 942 break; 943 case IORESOURCE_MEM: 944 res_valid |= !(res->flags & IORESOURCE_PREFETCH); 945 break; 946 case IORESOURCE_BUS: 947 pcie->root_bus_nr = res->start; 948 break; 949 } 950 } 951 952 if (!res_valid) { 953 dev_err(dev, "non-prefetchable memory resource required\n"); 954 err = -EINVAL; 955 goto out_release_res; 956 } 957 958 return 0; 959 960 out_release_res: 961 pci_free_resource_list(&pcie->resources); 962 return err; 963 } 964 965 static int advk_pcie_probe(struct platform_device *pdev) 966 { 967 struct device *dev = &pdev->dev; 968 struct advk_pcie *pcie; 969 struct resource *res; 970 struct pci_host_bridge *bridge; 971 int ret, irq; 972 973 bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie)); 974 if (!bridge) 975 return -ENOMEM; 976 977 pcie = pci_host_bridge_priv(bridge); 978 pcie->pdev = pdev; 979 980 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 981 pcie->base = devm_ioremap_resource(dev, res); 982 if (IS_ERR(pcie->base)) 983 return PTR_ERR(pcie->base); 984 985 irq = platform_get_irq(pdev, 0); 986 ret = devm_request_irq(dev, irq, advk_pcie_irq_handler, 987 IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie", 988 pcie); 989 if (ret) { 990 dev_err(dev, "Failed to register interrupt\n"); 991 return ret; 992 } 993 994 ret = advk_pcie_parse_request_of_pci_ranges(pcie); 995 if (ret) { 996 dev_err(dev, "Failed to parse resources\n"); 997 return ret; 998 } 999 1000 advk_pcie_setup_hw(pcie); 1001 1002 advk_sw_pci_bridge_init(pcie); 1003 1004 ret = advk_pcie_init_irq_domain(pcie); 1005 if (ret) { 1006 dev_err(dev, "Failed to initialize irq\n"); 1007 return ret; 1008 } 1009 1010 ret = advk_pcie_init_msi_irq_domain(pcie); 1011 if (ret) { 1012 dev_err(dev, "Failed to initialize irq\n"); 1013 advk_pcie_remove_irq_domain(pcie); 1014 return ret; 1015 } 1016 1017 list_splice_init(&pcie->resources, &bridge->windows); 1018 bridge->dev.parent = dev; 1019 bridge->sysdata = pcie; 1020 bridge->busnr = 0; 1021 bridge->ops = &advk_pcie_ops; 1022 bridge->map_irq = of_irq_parse_and_map_pci; 1023 bridge->swizzle_irq = pci_common_swizzle; 1024 1025 ret = pci_host_probe(bridge); 1026 if (ret < 0) { 1027 advk_pcie_remove_msi_irq_domain(pcie); 1028 advk_pcie_remove_irq_domain(pcie); 1029 return ret; 1030 } 1031 1032 return 0; 1033 } 1034 1035 static const struct of_device_id advk_pcie_of_match_table[] = { 1036 { .compatible = "marvell,armada-3700-pcie", }, 1037 {}, 1038 }; 1039 1040 static struct platform_driver advk_pcie_driver = { 1041 .driver = { 1042 .name = "advk-pcie", 1043 .of_match_table = advk_pcie_of_match_table, 1044 /* Driver unloading/unbinding currently not supported */ 1045 .suppress_bind_attrs = true, 1046 }, 1047 .probe = advk_pcie_probe, 1048 }; 1049 builtin_platform_driver(advk_pcie_driver); 1050