1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SpacemiT K1 PCIe host driver 4 * 5 * Copyright (C) 2025 by RISCstar Solutions Corporation. All rights reserved. 6 * Copyright (c) 2023, spacemit Corporation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/device.h> 12 #include <linux/err.h> 13 #include <linux/gfp.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/phy/phy.h> 17 #include <linux/platform_device.h> 18 #include <linux/regmap.h> 19 #include <linux/reset.h> 20 #include <linux/types.h> 21 22 #include "pcie-designware.h" 23 24 #define PCI_VENDOR_ID_SPACEMIT 0x201f 25 #define PCI_DEVICE_ID_SPACEMIT_K1 0x0001 26 27 /* Offsets and field definitions for link management registers */ 28 #define K1_PHY_AHB_IRQ_EN 0x0000 29 #define PCIE_INTERRUPT_EN BIT(0) 30 31 #define K1_PHY_AHB_LINK_STS 0x0004 32 #define SMLH_LINK_UP BIT(1) 33 #define RDLH_LINK_UP BIT(12) 34 35 #define INTR_ENABLE 0x0014 36 #define MSI_CTRL_INT BIT(11) 37 38 /* Some controls require APMU regmap access */ 39 #define SYSCON_APMU "spacemit,apmu" 40 41 /* Offsets and field definitions for APMU registers */ 42 #define PCIE_CLK_RESET_CONTROL 0x0000 43 #define LTSSM_EN BIT(6) 44 #define PCIE_AUX_PWR_DET BIT(9) 45 #define PCIE_RC_PERST BIT(12) /* 1: assert PERST# */ 46 #define APP_HOLD_PHY_RST BIT(30) 47 #define DEVICE_TYPE_RC BIT(31) /* 0: endpoint; 1: RC */ 48 49 #define PCIE_CONTROL_LOGIC 0x0004 50 #define PCIE_SOFT_RESET BIT(0) 51 52 struct k1_pcie { 53 struct dw_pcie pci; 54 struct phy *phy; 55 void __iomem *link; 56 struct regmap *pmu; /* Errors ignored; MMIO-backed regmap */ 57 u32 pmu_off; 58 }; 59 60 #define to_k1_pcie(dw_pcie) \ 61 platform_get_drvdata(to_platform_device((dw_pcie)->dev)) 62 63 static void k1_pcie_toggle_soft_reset(struct k1_pcie *k1) 64 { 65 u32 offset; 66 u32 val; 67 68 /* 69 * Write, then read back to guarantee it has reached the device 70 * before we start the delay. 71 */ 72 offset = k1->pmu_off + PCIE_CONTROL_LOGIC; 73 regmap_set_bits(k1->pmu, offset, PCIE_SOFT_RESET); 74 regmap_read(k1->pmu, offset, &val); 75 76 mdelay(2); 77 78 regmap_clear_bits(k1->pmu, offset, PCIE_SOFT_RESET); 79 } 80 81 /* Enable app clocks, deassert resets */ 82 static int k1_pcie_enable_resources(struct k1_pcie *k1) 83 { 84 struct dw_pcie *pci = &k1->pci; 85 int ret; 86 87 ret = clk_bulk_prepare_enable(ARRAY_SIZE(pci->app_clks), pci->app_clks); 88 if (ret) 89 return ret; 90 91 ret = reset_control_bulk_deassert(ARRAY_SIZE(pci->app_rsts), 92 pci->app_rsts); 93 if (ret) 94 goto err_disable_clks; 95 96 return 0; 97 98 err_disable_clks: 99 clk_bulk_disable_unprepare(ARRAY_SIZE(pci->app_clks), pci->app_clks); 100 101 return ret; 102 } 103 104 /* Assert resets, disable app clocks */ 105 static void k1_pcie_disable_resources(struct k1_pcie *k1) 106 { 107 struct dw_pcie *pci = &k1->pci; 108 109 reset_control_bulk_assert(ARRAY_SIZE(pci->app_rsts), pci->app_rsts); 110 clk_bulk_disable_unprepare(ARRAY_SIZE(pci->app_clks), pci->app_clks); 111 } 112 113 /* FIXME: Disable ASPM L1 to avoid errors reported on some NVMe drives */ 114 static void k1_pcie_disable_aspm_l1(struct k1_pcie *k1) 115 { 116 struct dw_pcie *pci = &k1->pci; 117 u8 offset; 118 u32 val; 119 120 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 121 offset += PCI_EXP_LNKCAP; 122 123 dw_pcie_dbi_ro_wr_en(pci); 124 val = dw_pcie_readl_dbi(pci, offset); 125 val &= ~PCI_EXP_LNKCAP_ASPM_L1; 126 dw_pcie_writel_dbi(pci, offset, val); 127 dw_pcie_dbi_ro_wr_dis(pci); 128 } 129 130 static int k1_pcie_init(struct dw_pcie_rp *pp) 131 { 132 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 133 struct k1_pcie *k1 = to_k1_pcie(pci); 134 u32 reset_ctrl; 135 u32 val; 136 int ret; 137 138 k1_pcie_toggle_soft_reset(k1); 139 140 ret = k1_pcie_enable_resources(k1); 141 if (ret) 142 return ret; 143 144 /* Set the PCI vendor and device ID */ 145 dw_pcie_dbi_ro_wr_en(pci); 146 dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, PCI_VENDOR_ID_SPACEMIT); 147 dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, PCI_DEVICE_ID_SPACEMIT_K1); 148 dw_pcie_dbi_ro_wr_dis(pci); 149 150 /* 151 * Start by asserting fundamental reset (drive PERST# low). The 152 * PCI CEM spec says that PERST# should be deasserted at least 153 * 100ms after the power becomes stable, so we'll insert that 154 * delay first. Write, then read it back to guarantee the write 155 * reaches the device before we start the delay. 156 */ 157 reset_ctrl = k1->pmu_off + PCIE_CLK_RESET_CONTROL; 158 regmap_set_bits(k1->pmu, reset_ctrl, PCIE_RC_PERST); 159 regmap_read(k1->pmu, reset_ctrl, &val); 160 mdelay(PCIE_T_PVPERL_MS); 161 162 /* 163 * Put the controller in root complex mode, and indicate that 164 * Vaux (3.3v) is present. 165 */ 166 regmap_set_bits(k1->pmu, reset_ctrl, DEVICE_TYPE_RC | PCIE_AUX_PWR_DET); 167 168 ret = phy_init(k1->phy); 169 if (ret) { 170 k1_pcie_disable_resources(k1); 171 172 return ret; 173 } 174 175 /* Deassert fundamental reset (drive PERST# high) */ 176 regmap_clear_bits(k1->pmu, reset_ctrl, PCIE_RC_PERST); 177 178 /* Finally, as a workaround, disable ASPM L1 */ 179 k1_pcie_disable_aspm_l1(k1); 180 181 return 0; 182 } 183 184 static void k1_pcie_deinit(struct dw_pcie_rp *pp) 185 { 186 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 187 struct k1_pcie *k1 = to_k1_pcie(pci); 188 189 /* Assert fundamental reset (drive PERST# low) */ 190 regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL, 191 PCIE_RC_PERST); 192 193 phy_exit(k1->phy); 194 195 k1_pcie_disable_resources(k1); 196 } 197 198 static const struct dw_pcie_host_ops k1_pcie_host_ops = { 199 .init = k1_pcie_init, 200 .deinit = k1_pcie_deinit, 201 }; 202 203 static bool k1_pcie_link_up(struct dw_pcie *pci) 204 { 205 struct k1_pcie *k1 = to_k1_pcie(pci); 206 u32 val; 207 208 val = readl_relaxed(k1->link + K1_PHY_AHB_LINK_STS); 209 210 return (val & RDLH_LINK_UP) && (val & SMLH_LINK_UP); 211 } 212 213 static int k1_pcie_start_link(struct dw_pcie *pci) 214 { 215 struct k1_pcie *k1 = to_k1_pcie(pci); 216 u32 val; 217 218 /* Stop holding the PHY in reset, and enable link training */ 219 regmap_update_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL, 220 APP_HOLD_PHY_RST | LTSSM_EN, LTSSM_EN); 221 222 /* Enable the MSI interrupt */ 223 writel_relaxed(MSI_CTRL_INT, k1->link + INTR_ENABLE); 224 225 /* Top-level interrupt enable */ 226 val = readl_relaxed(k1->link + K1_PHY_AHB_IRQ_EN); 227 val |= PCIE_INTERRUPT_EN; 228 writel_relaxed(val, k1->link + K1_PHY_AHB_IRQ_EN); 229 230 return 0; 231 } 232 233 static void k1_pcie_stop_link(struct dw_pcie *pci) 234 { 235 struct k1_pcie *k1 = to_k1_pcie(pci); 236 u32 val; 237 238 /* Disable interrupts */ 239 val = readl_relaxed(k1->link + K1_PHY_AHB_IRQ_EN); 240 val &= ~PCIE_INTERRUPT_EN; 241 writel_relaxed(val, k1->link + K1_PHY_AHB_IRQ_EN); 242 243 writel_relaxed(0, k1->link + INTR_ENABLE); 244 245 /* Disable the link and hold the PHY in reset */ 246 regmap_update_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL, 247 APP_HOLD_PHY_RST | LTSSM_EN, APP_HOLD_PHY_RST); 248 } 249 250 static const struct dw_pcie_ops k1_pcie_ops = { 251 .link_up = k1_pcie_link_up, 252 .start_link = k1_pcie_start_link, 253 .stop_link = k1_pcie_stop_link, 254 }; 255 256 static int k1_pcie_parse_port(struct k1_pcie *k1) 257 { 258 struct device *dev = k1->pci.dev; 259 struct device_node *root_port; 260 struct phy *phy; 261 262 /* We assume only one root port */ 263 root_port = of_get_next_available_child(dev_of_node(dev), NULL); 264 if (!root_port) 265 return -EINVAL; 266 267 phy = devm_of_phy_get(dev, root_port, NULL); 268 269 of_node_put(root_port); 270 271 if (IS_ERR(phy)) 272 return PTR_ERR(phy); 273 274 k1->phy = phy; 275 276 return 0; 277 } 278 279 static int k1_pcie_probe(struct platform_device *pdev) 280 { 281 struct device *dev = &pdev->dev; 282 struct k1_pcie *k1; 283 int ret; 284 285 k1 = devm_kzalloc(dev, sizeof(*k1), GFP_KERNEL); 286 if (!k1) 287 return -ENOMEM; 288 289 k1->pmu = syscon_regmap_lookup_by_phandle_args(dev_of_node(dev), 290 SYSCON_APMU, 1, 291 &k1->pmu_off); 292 if (IS_ERR(k1->pmu)) 293 return dev_err_probe(dev, PTR_ERR(k1->pmu), 294 "failed to lookup PMU registers\n"); 295 296 k1->link = devm_platform_ioremap_resource_byname(pdev, "link"); 297 if (IS_ERR(k1->link)) 298 return dev_err_probe(dev, PTR_ERR(k1->link), 299 "failed to map \"link\" registers\n"); 300 301 k1->pci.dev = dev; 302 k1->pci.ops = &k1_pcie_ops; 303 k1->pci.pp.num_vectors = MAX_MSI_IRQS; 304 dw_pcie_cap_set(&k1->pci, REQ_RES); 305 306 k1->pci.pp.ops = &k1_pcie_host_ops; 307 308 /* Hold the PHY in reset until we start the link */ 309 regmap_set_bits(k1->pmu, k1->pmu_off + PCIE_CLK_RESET_CONTROL, 310 APP_HOLD_PHY_RST); 311 312 ret = devm_regulator_get_enable(dev, "vpcie3v3"); 313 if (ret) 314 return dev_err_probe(dev, ret, 315 "failed to get \"vpcie3v3\" supply\n"); 316 317 pm_runtime_set_active(dev); 318 pm_runtime_no_callbacks(dev); 319 devm_pm_runtime_enable(dev); 320 321 platform_set_drvdata(pdev, k1); 322 323 ret = k1_pcie_parse_port(k1); 324 if (ret) 325 return dev_err_probe(dev, ret, "failed to parse root port\n"); 326 327 ret = dw_pcie_host_init(&k1->pci.pp); 328 if (ret) 329 return dev_err_probe(dev, ret, "failed to initialize host\n"); 330 331 return 0; 332 } 333 334 static void k1_pcie_remove(struct platform_device *pdev) 335 { 336 struct k1_pcie *k1 = platform_get_drvdata(pdev); 337 338 dw_pcie_host_deinit(&k1->pci.pp); 339 } 340 341 static const struct of_device_id k1_pcie_of_match_table[] = { 342 { .compatible = "spacemit,k1-pcie", }, 343 { } 344 }; 345 346 static struct platform_driver k1_pcie_driver = { 347 .probe = k1_pcie_probe, 348 .remove = k1_pcie_remove, 349 .driver = { 350 .name = "spacemit-k1-pcie", 351 .of_match_table = k1_pcie_of_match_table, 352 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 353 }, 354 }; 355 module_platform_driver(k1_pcie_driver); 356 MODULE_LICENSE("GPL"); 357 MODULE_DESCRIPTION("SpacemiT K1 PCIe host driver"); 358