1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * PCIe host controller driver for Freescale i.MX6 SoCs 4 * 5 * Copyright (C) 2013 Kosagi 6 * https://www.kosagi.com 7 * 8 * Author: Sean Cross <xobs@kosagi.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/gpio.h> 15 #include <linux/kernel.h> 16 #include <linux/mfd/syscon.h> 17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_gpio.h> 22 #include <linux/of_address.h> 23 #include <linux/pci.h> 24 #include <linux/platform_device.h> 25 #include <linux/regmap.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/resource.h> 28 #include <linux/signal.h> 29 #include <linux/types.h> 30 #include <linux/interrupt.h> 31 #include <linux/reset.h> 32 #include <linux/phy/phy.h> 33 #include <linux/pm_domain.h> 34 #include <linux/pm_runtime.h> 35 36 #include "pcie-designware.h" 37 38 #define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9) 39 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10) 40 #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11) 41 #define IMX8MQ_GPR_PCIE_VREG_BYPASS BIT(12) 42 #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8) 43 #define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000 44 45 #define IMX95_PCIE_PHY_GEN_CTRL 0x0 46 #define IMX95_PCIE_REF_USE_PAD BIT(17) 47 48 #define IMX95_PCIE_SS_RW_REG_0 0xf0 49 #define IMX95_PCIE_REF_CLKEN BIT(23) 50 #define IMX95_PCIE_PHY_CR_PARA_SEL BIT(9) 51 52 #define IMX95_PE0_GEN_CTRL_1 0x1050 53 #define IMX95_PCIE_DEVICE_TYPE GENMASK(3, 0) 54 55 #define IMX95_PE0_GEN_CTRL_3 0x1058 56 #define IMX95_PCIE_LTSSM_EN BIT(0) 57 58 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev) 59 60 enum imx6_pcie_variants { 61 IMX6Q, 62 IMX6SX, 63 IMX6QP, 64 IMX7D, 65 IMX8MQ, 66 IMX8MM, 67 IMX8MP, 68 IMX95, 69 IMX8MQ_EP, 70 IMX8MM_EP, 71 IMX8MP_EP, 72 IMX95_EP, 73 }; 74 75 #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) 76 #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) 77 #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) 78 #define IMX6_PCIE_FLAG_HAS_PHYDRV BIT(3) 79 #define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(4) 80 #define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(5) 81 #define IMX6_PCIE_FLAG_HAS_SERDES BIT(6) 82 #define IMX6_PCIE_FLAG_SUPPORT_64BIT BIT(7) 83 84 #define imx6_check_flag(pci, val) (pci->drvdata->flags & val) 85 86 #define IMX6_PCIE_MAX_CLKS 6 87 88 #define IMX6_PCIE_MAX_INSTANCES 2 89 90 struct imx6_pcie; 91 92 struct imx6_pcie_drvdata { 93 enum imx6_pcie_variants variant; 94 enum dw_pcie_device_mode mode; 95 u32 flags; 96 int dbi_length; 97 const char *gpr; 98 const char * const *clk_names; 99 const u32 clks_cnt; 100 const u32 ltssm_off; 101 const u32 ltssm_mask; 102 const u32 mode_off[IMX6_PCIE_MAX_INSTANCES]; 103 const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES]; 104 const struct pci_epc_features *epc_features; 105 int (*init_phy)(struct imx6_pcie *pcie); 106 }; 107 108 struct imx6_pcie { 109 struct dw_pcie *pci; 110 int reset_gpio; 111 bool gpio_active_high; 112 bool link_is_up; 113 struct clk_bulk_data clks[IMX6_PCIE_MAX_CLKS]; 114 struct regmap *iomuxc_gpr; 115 u16 msi_ctrl; 116 u32 controller_id; 117 struct reset_control *pciephy_reset; 118 struct reset_control *apps_reset; 119 struct reset_control *turnoff_reset; 120 u32 tx_deemph_gen1; 121 u32 tx_deemph_gen2_3p5db; 122 u32 tx_deemph_gen2_6db; 123 u32 tx_swing_full; 124 u32 tx_swing_low; 125 struct regulator *vpcie; 126 struct regulator *vph; 127 void __iomem *phy_base; 128 129 /* power domain for pcie */ 130 struct device *pd_pcie; 131 /* power domain for pcie phy */ 132 struct device *pd_pcie_phy; 133 struct phy *phy; 134 const struct imx6_pcie_drvdata *drvdata; 135 }; 136 137 /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */ 138 #define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200 139 #define PHY_PLL_LOCK_WAIT_TIMEOUT (2000 * PHY_PLL_LOCK_WAIT_USLEEP_MAX) 140 141 /* PCIe Port Logic registers (memory-mapped) */ 142 #define PL_OFFSET 0x700 143 144 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114) 145 #define PCIE_PHY_CTRL_DATA(x) FIELD_PREP(GENMASK(15, 0), (x)) 146 #define PCIE_PHY_CTRL_CAP_ADR BIT(16) 147 #define PCIE_PHY_CTRL_CAP_DAT BIT(17) 148 #define PCIE_PHY_CTRL_WR BIT(18) 149 #define PCIE_PHY_CTRL_RD BIT(19) 150 151 #define PCIE_PHY_STAT (PL_OFFSET + 0x110) 152 #define PCIE_PHY_STAT_ACK BIT(16) 153 154 /* PHY registers (not memory-mapped) */ 155 #define PCIE_PHY_ATEOVRD 0x10 156 #define PCIE_PHY_ATEOVRD_EN BIT(2) 157 #define PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT 0 158 #define PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK 0x1 159 160 #define PCIE_PHY_MPLL_OVRD_IN_LO 0x11 161 #define PCIE_PHY_MPLL_MULTIPLIER_SHIFT 2 162 #define PCIE_PHY_MPLL_MULTIPLIER_MASK 0x7f 163 #define PCIE_PHY_MPLL_MULTIPLIER_OVRD BIT(9) 164 165 #define PCIE_PHY_RX_ASIC_OUT 0x100D 166 #define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0) 167 168 /* iMX7 PCIe PHY registers */ 169 #define PCIE_PHY_CMN_REG4 0x14 170 /* These are probably the bits that *aren't* DCC_FB_EN */ 171 #define PCIE_PHY_CMN_REG4_DCC_FB_EN 0x29 172 173 #define PCIE_PHY_CMN_REG15 0x54 174 #define PCIE_PHY_CMN_REG15_DLY_4 BIT(2) 175 #define PCIE_PHY_CMN_REG15_PLL_PD BIT(5) 176 #define PCIE_PHY_CMN_REG15_OVRD_PLL_PD BIT(7) 177 178 #define PCIE_PHY_CMN_REG24 0x90 179 #define PCIE_PHY_CMN_REG24_RX_EQ BIT(6) 180 #define PCIE_PHY_CMN_REG24_RX_EQ_SEL BIT(3) 181 182 #define PCIE_PHY_CMN_REG26 0x98 183 #define PCIE_PHY_CMN_REG26_ATT_MODE 0xBC 184 185 #define PHY_RX_OVRD_IN_LO 0x1005 186 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5) 187 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3) 188 189 static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie) 190 { 191 WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ && 192 imx6_pcie->drvdata->variant != IMX8MQ_EP && 193 imx6_pcie->drvdata->variant != IMX8MM && 194 imx6_pcie->drvdata->variant != IMX8MM_EP && 195 imx6_pcie->drvdata->variant != IMX8MP && 196 imx6_pcie->drvdata->variant != IMX8MP_EP); 197 return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; 198 } 199 200 static int imx95_pcie_init_phy(struct imx6_pcie *imx6_pcie) 201 { 202 regmap_update_bits(imx6_pcie->iomuxc_gpr, 203 IMX95_PCIE_SS_RW_REG_0, 204 IMX95_PCIE_PHY_CR_PARA_SEL, 205 IMX95_PCIE_PHY_CR_PARA_SEL); 206 207 regmap_update_bits(imx6_pcie->iomuxc_gpr, 208 IMX95_PCIE_PHY_GEN_CTRL, 209 IMX95_PCIE_REF_USE_PAD, 0); 210 regmap_update_bits(imx6_pcie->iomuxc_gpr, 211 IMX95_PCIE_SS_RW_REG_0, 212 IMX95_PCIE_REF_CLKEN, 213 IMX95_PCIE_REF_CLKEN); 214 215 return 0; 216 } 217 218 static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) 219 { 220 const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; 221 unsigned int mask, val, mode, id; 222 223 if (drvdata->mode == DW_PCIE_EP_TYPE) 224 mode = PCI_EXP_TYPE_ENDPOINT; 225 else 226 mode = PCI_EXP_TYPE_ROOT_PORT; 227 228 id = imx6_pcie->controller_id; 229 230 /* If mode_mask[id] is zero, means each controller have its individual gpr */ 231 if (!drvdata->mode_mask[id]) 232 id = 0; 233 234 mask = drvdata->mode_mask[id]; 235 val = mode << (ffs(mask) - 1); 236 237 regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val); 238 } 239 240 static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val) 241 { 242 struct dw_pcie *pci = imx6_pcie->pci; 243 bool val; 244 u32 max_iterations = 10; 245 u32 wait_counter = 0; 246 247 do { 248 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT) & 249 PCIE_PHY_STAT_ACK; 250 wait_counter++; 251 252 if (val == exp_val) 253 return 0; 254 255 udelay(1); 256 } while (wait_counter < max_iterations); 257 258 return -ETIMEDOUT; 259 } 260 261 static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr) 262 { 263 struct dw_pcie *pci = imx6_pcie->pci; 264 u32 val; 265 int ret; 266 267 val = PCIE_PHY_CTRL_DATA(addr); 268 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 269 270 val |= PCIE_PHY_CTRL_CAP_ADR; 271 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 272 273 ret = pcie_phy_poll_ack(imx6_pcie, true); 274 if (ret) 275 return ret; 276 277 val = PCIE_PHY_CTRL_DATA(addr); 278 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); 279 280 return pcie_phy_poll_ack(imx6_pcie, false); 281 } 282 283 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ 284 static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data) 285 { 286 struct dw_pcie *pci = imx6_pcie->pci; 287 u32 phy_ctl; 288 int ret; 289 290 ret = pcie_phy_wait_ack(imx6_pcie, addr); 291 if (ret) 292 return ret; 293 294 /* assert Read signal */ 295 phy_ctl = PCIE_PHY_CTRL_RD; 296 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl); 297 298 ret = pcie_phy_poll_ack(imx6_pcie, true); 299 if (ret) 300 return ret; 301 302 *data = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT); 303 304 /* deassert Read signal */ 305 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00); 306 307 return pcie_phy_poll_ack(imx6_pcie, false); 308 } 309 310 static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) 311 { 312 struct dw_pcie *pci = imx6_pcie->pci; 313 u32 var; 314 int ret; 315 316 /* write addr */ 317 /* cap addr */ 318 ret = pcie_phy_wait_ack(imx6_pcie, addr); 319 if (ret) 320 return ret; 321 322 var = PCIE_PHY_CTRL_DATA(data); 323 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 324 325 /* capture data */ 326 var |= PCIE_PHY_CTRL_CAP_DAT; 327 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 328 329 ret = pcie_phy_poll_ack(imx6_pcie, true); 330 if (ret) 331 return ret; 332 333 /* deassert cap data */ 334 var = PCIE_PHY_CTRL_DATA(data); 335 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 336 337 /* wait for ack de-assertion */ 338 ret = pcie_phy_poll_ack(imx6_pcie, false); 339 if (ret) 340 return ret; 341 342 /* assert wr signal */ 343 var = PCIE_PHY_CTRL_WR; 344 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 345 346 /* wait for ack */ 347 ret = pcie_phy_poll_ack(imx6_pcie, true); 348 if (ret) 349 return ret; 350 351 /* deassert wr signal */ 352 var = PCIE_PHY_CTRL_DATA(data); 353 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); 354 355 /* wait for ack de-assertion */ 356 ret = pcie_phy_poll_ack(imx6_pcie, false); 357 if (ret) 358 return ret; 359 360 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0); 361 362 return 0; 363 } 364 365 static int imx8mq_pcie_init_phy(struct imx6_pcie *imx6_pcie) 366 { 367 /* TODO: Currently this code assumes external oscillator is being used */ 368 regmap_update_bits(imx6_pcie->iomuxc_gpr, 369 imx6_pcie_grp_offset(imx6_pcie), 370 IMX8MQ_GPR_PCIE_REF_USE_PAD, 371 IMX8MQ_GPR_PCIE_REF_USE_PAD); 372 /* 373 * Regarding the datasheet, the PCIE_VPH is suggested to be 1.8V. If the PCIE_VPH is 374 * supplied by 3.3V, the VREG_BYPASS should be cleared to zero. 375 */ 376 if (imx6_pcie->vph && regulator_get_voltage(imx6_pcie->vph) > 3000000) 377 regmap_update_bits(imx6_pcie->iomuxc_gpr, 378 imx6_pcie_grp_offset(imx6_pcie), 379 IMX8MQ_GPR_PCIE_VREG_BYPASS, 380 0); 381 382 return 0; 383 } 384 385 static int imx7d_pcie_init_phy(struct imx6_pcie *imx6_pcie) 386 { 387 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0); 388 389 return 0; 390 } 391 392 static int imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) 393 { 394 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 395 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); 396 397 /* configure constant input signal to the pcie ctrl and phy */ 398 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 399 IMX6Q_GPR12_LOS_LEVEL, 9 << 4); 400 401 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 402 IMX6Q_GPR8_TX_DEEMPH_GEN1, 403 imx6_pcie->tx_deemph_gen1 << 0); 404 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 405 IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 406 imx6_pcie->tx_deemph_gen2_3p5db << 6); 407 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 408 IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 409 imx6_pcie->tx_deemph_gen2_6db << 12); 410 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 411 IMX6Q_GPR8_TX_SWING_FULL, 412 imx6_pcie->tx_swing_full << 18); 413 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, 414 IMX6Q_GPR8_TX_SWING_LOW, 415 imx6_pcie->tx_swing_low << 25); 416 return 0; 417 } 418 419 static int imx6sx_pcie_init_phy(struct imx6_pcie *imx6_pcie) 420 { 421 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 422 IMX6SX_GPR12_PCIE_RX_EQ_MASK, IMX6SX_GPR12_PCIE_RX_EQ_2); 423 424 return imx6_pcie_init_phy(imx6_pcie); 425 } 426 427 static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) 428 { 429 u32 val; 430 struct device *dev = imx6_pcie->pci->dev; 431 432 if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr, 433 IOMUXC_GPR22, val, 434 val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED, 435 PHY_PLL_LOCK_WAIT_USLEEP_MAX, 436 PHY_PLL_LOCK_WAIT_TIMEOUT)) 437 dev_err(dev, "PCIe PLL lock timeout\n"); 438 } 439 440 static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie) 441 { 442 unsigned long phy_rate = 0; 443 int mult, div; 444 u16 val; 445 int i; 446 447 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) 448 return 0; 449 450 for (i = 0; i < imx6_pcie->drvdata->clks_cnt; i++) 451 if (strncmp(imx6_pcie->clks[i].id, "pcie_phy", 8) == 0) 452 phy_rate = clk_get_rate(imx6_pcie->clks[i].clk); 453 454 switch (phy_rate) { 455 case 125000000: 456 /* 457 * The default settings of the MPLL are for a 125MHz input 458 * clock, so no need to reconfigure anything in that case. 459 */ 460 return 0; 461 case 100000000: 462 mult = 25; 463 div = 0; 464 break; 465 case 200000000: 466 mult = 25; 467 div = 1; 468 break; 469 default: 470 dev_err(imx6_pcie->pci->dev, 471 "Unsupported PHY reference clock rate %lu\n", phy_rate); 472 return -EINVAL; 473 } 474 475 pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val); 476 val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK << 477 PCIE_PHY_MPLL_MULTIPLIER_SHIFT); 478 val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT; 479 val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD; 480 pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val); 481 482 pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val); 483 val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK << 484 PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT); 485 val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT; 486 val |= PCIE_PHY_ATEOVRD_EN; 487 pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val); 488 489 return 0; 490 } 491 492 static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie) 493 { 494 u16 tmp; 495 496 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) 497 return; 498 499 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); 500 tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | 501 PHY_RX_OVRD_IN_LO_RX_PLL_EN); 502 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); 503 504 usleep_range(2000, 3000); 505 506 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); 507 tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | 508 PHY_RX_OVRD_IN_LO_RX_PLL_EN); 509 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); 510 } 511 512 #ifdef CONFIG_ARM 513 /* Added for PCI abort handling */ 514 static int imx6q_pcie_abort_handler(unsigned long addr, 515 unsigned int fsr, struct pt_regs *regs) 516 { 517 unsigned long pc = instruction_pointer(regs); 518 unsigned long instr = *(unsigned long *)pc; 519 int reg = (instr >> 12) & 15; 520 521 /* 522 * If the instruction being executed was a read, 523 * make it look like it read all-ones. 524 */ 525 if ((instr & 0x0c100000) == 0x04100000) { 526 unsigned long val; 527 528 if (instr & 0x00400000) 529 val = 255; 530 else 531 val = -1; 532 533 regs->uregs[reg] = val; 534 regs->ARM_pc += 4; 535 return 0; 536 } 537 538 if ((instr & 0x0e100090) == 0x00100090) { 539 regs->uregs[reg] = -1; 540 regs->ARM_pc += 4; 541 return 0; 542 } 543 544 return 1; 545 } 546 #endif 547 548 static int imx6_pcie_attach_pd(struct device *dev) 549 { 550 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 551 struct device_link *link; 552 553 /* Do nothing when in a single power domain */ 554 if (dev->pm_domain) 555 return 0; 556 557 imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie"); 558 if (IS_ERR(imx6_pcie->pd_pcie)) 559 return PTR_ERR(imx6_pcie->pd_pcie); 560 /* Do nothing when power domain missing */ 561 if (!imx6_pcie->pd_pcie) 562 return 0; 563 link = device_link_add(dev, imx6_pcie->pd_pcie, 564 DL_FLAG_STATELESS | 565 DL_FLAG_PM_RUNTIME | 566 DL_FLAG_RPM_ACTIVE); 567 if (!link) { 568 dev_err(dev, "Failed to add device_link to pcie pd.\n"); 569 return -EINVAL; 570 } 571 572 imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy"); 573 if (IS_ERR(imx6_pcie->pd_pcie_phy)) 574 return PTR_ERR(imx6_pcie->pd_pcie_phy); 575 576 link = device_link_add(dev, imx6_pcie->pd_pcie_phy, 577 DL_FLAG_STATELESS | 578 DL_FLAG_PM_RUNTIME | 579 DL_FLAG_RPM_ACTIVE); 580 if (!link) { 581 dev_err(dev, "Failed to add device_link to pcie_phy pd.\n"); 582 return -EINVAL; 583 } 584 585 return 0; 586 } 587 588 static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) 589 { 590 unsigned int offset; 591 int ret = 0; 592 593 switch (imx6_pcie->drvdata->variant) { 594 case IMX6SX: 595 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 596 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0); 597 break; 598 case IMX6QP: 599 case IMX6Q: 600 /* power up core phy and enable ref clock */ 601 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 602 IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); 603 /* 604 * the async reset input need ref clock to sync internally, 605 * when the ref clock comes after reset, internal synced 606 * reset time is too short, cannot meet the requirement. 607 * add one ~10us delay here. 608 */ 609 usleep_range(10, 100); 610 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 611 IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); 612 break; 613 case IMX7D: 614 case IMX95: 615 case IMX95_EP: 616 break; 617 case IMX8MM: 618 case IMX8MM_EP: 619 case IMX8MQ: 620 case IMX8MQ_EP: 621 case IMX8MP: 622 case IMX8MP_EP: 623 offset = imx6_pcie_grp_offset(imx6_pcie); 624 /* 625 * Set the over ride low and enabled 626 * make sure that REF_CLK is turned on. 627 */ 628 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, 629 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, 630 0); 631 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, 632 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, 633 IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN); 634 break; 635 } 636 637 return ret; 638 } 639 640 static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie) 641 { 642 switch (imx6_pcie->drvdata->variant) { 643 case IMX6QP: 644 case IMX6Q: 645 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 646 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0); 647 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 648 IMX6Q_GPR1_PCIE_TEST_PD, 649 IMX6Q_GPR1_PCIE_TEST_PD); 650 break; 651 case IMX7D: 652 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 653 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 654 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); 655 break; 656 default: 657 break; 658 } 659 } 660 661 static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie) 662 { 663 struct dw_pcie *pci = imx6_pcie->pci; 664 struct device *dev = pci->dev; 665 int ret; 666 667 ret = clk_bulk_prepare_enable(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); 668 if (ret) 669 return ret; 670 671 ret = imx6_pcie_enable_ref_clk(imx6_pcie); 672 if (ret) { 673 dev_err(dev, "unable to enable pcie ref clock\n"); 674 goto err_ref_clk; 675 } 676 677 /* allow the clocks to stabilize */ 678 usleep_range(200, 500); 679 return 0; 680 681 err_ref_clk: 682 clk_bulk_disable_unprepare(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); 683 684 return ret; 685 } 686 687 static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) 688 { 689 imx6_pcie_disable_ref_clk(imx6_pcie); 690 clk_bulk_disable_unprepare(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); 691 } 692 693 static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) 694 { 695 reset_control_assert(imx6_pcie->pciephy_reset); 696 reset_control_assert(imx6_pcie->apps_reset); 697 698 switch (imx6_pcie->drvdata->variant) { 699 case IMX6SX: 700 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 701 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 702 IMX6SX_GPR12_PCIE_TEST_POWERDOWN); 703 /* Force PCIe PHY reset */ 704 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, 705 IMX6SX_GPR5_PCIE_BTNRST_RESET, 706 IMX6SX_GPR5_PCIE_BTNRST_RESET); 707 break; 708 case IMX6QP: 709 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 710 IMX6Q_GPR1_PCIE_SW_RST, 711 IMX6Q_GPR1_PCIE_SW_RST); 712 break; 713 case IMX6Q: 714 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 715 IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); 716 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 717 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); 718 break; 719 default: 720 break; 721 } 722 723 /* Some boards don't have PCIe reset GPIO. */ 724 if (gpio_is_valid(imx6_pcie->reset_gpio)) 725 gpio_set_value_cansleep(imx6_pcie->reset_gpio, 726 imx6_pcie->gpio_active_high); 727 } 728 729 static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) 730 { 731 struct dw_pcie *pci = imx6_pcie->pci; 732 struct device *dev = pci->dev; 733 734 reset_control_deassert(imx6_pcie->pciephy_reset); 735 736 switch (imx6_pcie->drvdata->variant) { 737 case IMX7D: 738 /* Workaround for ERR010728, failure of PCI-e PLL VCO to 739 * oscillate, especially when cold. This turns off "Duty-cycle 740 * Corrector" and other mysterious undocumented things. 741 */ 742 if (likely(imx6_pcie->phy_base)) { 743 /* De-assert DCC_FB_EN */ 744 writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, 745 imx6_pcie->phy_base + PCIE_PHY_CMN_REG4); 746 /* Assert RX_EQS and RX_EQS_SEL */ 747 writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL 748 | PCIE_PHY_CMN_REG24_RX_EQ, 749 imx6_pcie->phy_base + PCIE_PHY_CMN_REG24); 750 /* Assert ATT_MODE */ 751 writel(PCIE_PHY_CMN_REG26_ATT_MODE, 752 imx6_pcie->phy_base + PCIE_PHY_CMN_REG26); 753 } else { 754 dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); 755 } 756 757 imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie); 758 break; 759 case IMX6SX: 760 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, 761 IMX6SX_GPR5_PCIE_BTNRST_RESET, 0); 762 break; 763 case IMX6QP: 764 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, 765 IMX6Q_GPR1_PCIE_SW_RST, 0); 766 767 usleep_range(200, 500); 768 break; 769 default: 770 break; 771 } 772 773 /* Some boards don't have PCIe reset GPIO. */ 774 if (gpio_is_valid(imx6_pcie->reset_gpio)) { 775 msleep(100); 776 gpio_set_value_cansleep(imx6_pcie->reset_gpio, 777 !imx6_pcie->gpio_active_high); 778 /* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */ 779 msleep(100); 780 } 781 782 return 0; 783 } 784 785 static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie) 786 { 787 struct dw_pcie *pci = imx6_pcie->pci; 788 struct device *dev = pci->dev; 789 u32 tmp; 790 unsigned int retries; 791 792 for (retries = 0; retries < 200; retries++) { 793 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 794 /* Test if the speed change finished. */ 795 if (!(tmp & PORT_LOGIC_SPEED_CHANGE)) 796 return 0; 797 usleep_range(100, 1000); 798 } 799 800 dev_err(dev, "Speed change timeout\n"); 801 return -ETIMEDOUT; 802 } 803 804 static void imx6_pcie_ltssm_enable(struct device *dev) 805 { 806 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 807 const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; 808 809 if (drvdata->ltssm_mask) 810 regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, 811 drvdata->ltssm_mask); 812 813 reset_control_deassert(imx6_pcie->apps_reset); 814 } 815 816 static void imx6_pcie_ltssm_disable(struct device *dev) 817 { 818 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 819 const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; 820 821 if (drvdata->ltssm_mask) 822 regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->ltssm_off, 823 drvdata->ltssm_mask, 0); 824 825 reset_control_assert(imx6_pcie->apps_reset); 826 } 827 828 static int imx6_pcie_start_link(struct dw_pcie *pci) 829 { 830 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 831 struct device *dev = pci->dev; 832 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 833 u32 tmp; 834 int ret; 835 836 /* 837 * Force Gen1 operation when starting the link. In case the link is 838 * started in Gen2 mode, there is a possibility the devices on the 839 * bus will not be detected at all. This happens with PCIe switches. 840 */ 841 dw_pcie_dbi_ro_wr_en(pci); 842 tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 843 tmp &= ~PCI_EXP_LNKCAP_SLS; 844 tmp |= PCI_EXP_LNKCAP_SLS_2_5GB; 845 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); 846 dw_pcie_dbi_ro_wr_dis(pci); 847 848 /* Start LTSSM. */ 849 imx6_pcie_ltssm_enable(dev); 850 851 ret = dw_pcie_wait_for_link(pci); 852 if (ret) 853 goto err_reset_phy; 854 855 if (pci->link_gen > 1) { 856 /* Allow faster modes after the link is up */ 857 dw_pcie_dbi_ro_wr_en(pci); 858 tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); 859 tmp &= ~PCI_EXP_LNKCAP_SLS; 860 tmp |= pci->link_gen; 861 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp); 862 863 /* 864 * Start Directed Speed Change so the best possible 865 * speed both link partners support can be negotiated. 866 */ 867 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); 868 tmp |= PORT_LOGIC_SPEED_CHANGE; 869 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); 870 dw_pcie_dbi_ro_wr_dis(pci); 871 872 if (imx6_pcie->drvdata->flags & 873 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE) { 874 /* 875 * On i.MX7, DIRECT_SPEED_CHANGE behaves differently 876 * from i.MX6 family when no link speed transition 877 * occurs and we go Gen1 -> yep, Gen1. The difference 878 * is that, in such case, it will not be cleared by HW 879 * which will cause the following code to report false 880 * failure. 881 */ 882 883 ret = imx6_pcie_wait_for_speed_change(imx6_pcie); 884 if (ret) { 885 dev_err(dev, "Failed to bring link up!\n"); 886 goto err_reset_phy; 887 } 888 } 889 890 /* Make sure link training is finished as well! */ 891 ret = dw_pcie_wait_for_link(pci); 892 if (ret) 893 goto err_reset_phy; 894 } else { 895 dev_info(dev, "Link: Only Gen1 is enabled\n"); 896 } 897 898 imx6_pcie->link_is_up = true; 899 tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); 900 dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS); 901 return 0; 902 903 err_reset_phy: 904 imx6_pcie->link_is_up = false; 905 dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", 906 dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0), 907 dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1)); 908 imx6_pcie_reset_phy(imx6_pcie); 909 return 0; 910 } 911 912 static void imx6_pcie_stop_link(struct dw_pcie *pci) 913 { 914 struct device *dev = pci->dev; 915 916 /* Turn off PCIe LTSSM */ 917 imx6_pcie_ltssm_disable(dev); 918 } 919 920 static int imx6_pcie_host_init(struct dw_pcie_rp *pp) 921 { 922 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 923 struct device *dev = pci->dev; 924 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 925 int ret; 926 927 if (imx6_pcie->vpcie) { 928 ret = regulator_enable(imx6_pcie->vpcie); 929 if (ret) { 930 dev_err(dev, "failed to enable vpcie regulator: %d\n", 931 ret); 932 return ret; 933 } 934 } 935 936 imx6_pcie_assert_core_reset(imx6_pcie); 937 938 if (imx6_pcie->drvdata->init_phy) 939 imx6_pcie->drvdata->init_phy(imx6_pcie); 940 941 imx6_pcie_configure_type(imx6_pcie); 942 943 ret = imx6_pcie_clk_enable(imx6_pcie); 944 if (ret) { 945 dev_err(dev, "unable to enable pcie clocks: %d\n", ret); 946 goto err_reg_disable; 947 } 948 949 if (imx6_pcie->phy) { 950 ret = phy_init(imx6_pcie->phy); 951 if (ret) { 952 dev_err(dev, "pcie PHY power up failed\n"); 953 goto err_clk_disable; 954 } 955 } 956 957 if (imx6_pcie->phy) { 958 ret = phy_power_on(imx6_pcie->phy); 959 if (ret) { 960 dev_err(dev, "waiting for PHY ready timeout!\n"); 961 goto err_phy_off; 962 } 963 } 964 965 ret = imx6_pcie_deassert_core_reset(imx6_pcie); 966 if (ret < 0) { 967 dev_err(dev, "pcie deassert core reset failed: %d\n", ret); 968 goto err_phy_off; 969 } 970 971 imx6_setup_phy_mpll(imx6_pcie); 972 973 return 0; 974 975 err_phy_off: 976 if (imx6_pcie->phy) 977 phy_exit(imx6_pcie->phy); 978 err_clk_disable: 979 imx6_pcie_clk_disable(imx6_pcie); 980 err_reg_disable: 981 if (imx6_pcie->vpcie) 982 regulator_disable(imx6_pcie->vpcie); 983 return ret; 984 } 985 986 static void imx6_pcie_host_exit(struct dw_pcie_rp *pp) 987 { 988 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 989 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 990 991 if (imx6_pcie->phy) { 992 if (phy_power_off(imx6_pcie->phy)) 993 dev_err(pci->dev, "unable to power off PHY\n"); 994 phy_exit(imx6_pcie->phy); 995 } 996 imx6_pcie_clk_disable(imx6_pcie); 997 998 if (imx6_pcie->vpcie) 999 regulator_disable(imx6_pcie->vpcie); 1000 } 1001 1002 static const struct dw_pcie_host_ops imx6_pcie_host_ops = { 1003 .init = imx6_pcie_host_init, 1004 .deinit = imx6_pcie_host_exit, 1005 }; 1006 1007 static const struct dw_pcie_ops dw_pcie_ops = { 1008 .start_link = imx6_pcie_start_link, 1009 .stop_link = imx6_pcie_stop_link, 1010 }; 1011 1012 static void imx6_pcie_ep_init(struct dw_pcie_ep *ep) 1013 { 1014 enum pci_barno bar; 1015 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 1016 1017 for (bar = BAR_0; bar <= BAR_5; bar++) 1018 dw_pcie_ep_reset_bar(pci, bar); 1019 } 1020 1021 static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, 1022 unsigned int type, u16 interrupt_num) 1023 { 1024 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 1025 1026 switch (type) { 1027 case PCI_IRQ_INTX: 1028 return dw_pcie_ep_raise_intx_irq(ep, func_no); 1029 case PCI_IRQ_MSI: 1030 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); 1031 case PCI_IRQ_MSIX: 1032 return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num); 1033 default: 1034 dev_err(pci->dev, "UNKNOWN IRQ type\n"); 1035 return -EINVAL; 1036 } 1037 1038 return 0; 1039 } 1040 1041 static const struct pci_epc_features imx8m_pcie_epc_features = { 1042 .linkup_notifier = false, 1043 .msi_capable = true, 1044 .msix_capable = false, 1045 .bar[BAR_1] = { .type = BAR_RESERVED, }, 1046 .bar[BAR_3] = { .type = BAR_RESERVED, }, 1047 .align = SZ_64K, 1048 }; 1049 1050 /* 1051 * BAR# | Default BAR enable | Default BAR Type | Default BAR Size | BAR Sizing Scheme 1052 * ================================================================================================ 1053 * BAR0 | Enable | 64-bit | 1 MB | Programmable Size 1054 * BAR1 | Disable | 32-bit | 64 KB | Fixed Size 1055 * BAR1 should be disabled if BAR0 is 64bit. 1056 * BAR2 | Enable | 32-bit | 1 MB | Programmable Size 1057 * BAR3 | Enable | 32-bit | 64 KB | Programmable Size 1058 * BAR4 | Enable | 32-bit | 1M | Programmable Size 1059 * BAR5 | Enable | 32-bit | 64 KB | Programmable Size 1060 */ 1061 static const struct pci_epc_features imx95_pcie_epc_features = { 1062 .msi_capable = true, 1063 .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_64K, }, 1064 .align = SZ_4K, 1065 }; 1066 1067 static const struct pci_epc_features* 1068 imx6_pcie_ep_get_features(struct dw_pcie_ep *ep) 1069 { 1070 struct dw_pcie *pci = to_dw_pcie_from_ep(ep); 1071 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 1072 1073 return imx6_pcie->drvdata->epc_features; 1074 } 1075 1076 static const struct dw_pcie_ep_ops pcie_ep_ops = { 1077 .init = imx6_pcie_ep_init, 1078 .raise_irq = imx6_pcie_ep_raise_irq, 1079 .get_features = imx6_pcie_ep_get_features, 1080 }; 1081 1082 static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, 1083 struct platform_device *pdev) 1084 { 1085 int ret; 1086 unsigned int pcie_dbi2_offset; 1087 struct dw_pcie_ep *ep; 1088 struct dw_pcie *pci = imx6_pcie->pci; 1089 struct dw_pcie_rp *pp = &pci->pp; 1090 struct device *dev = pci->dev; 1091 1092 imx6_pcie_host_init(pp); 1093 ep = &pci->ep; 1094 ep->ops = &pcie_ep_ops; 1095 1096 switch (imx6_pcie->drvdata->variant) { 1097 case IMX8MQ_EP: 1098 case IMX8MM_EP: 1099 case IMX8MP_EP: 1100 pcie_dbi2_offset = SZ_1M; 1101 break; 1102 default: 1103 pcie_dbi2_offset = SZ_4K; 1104 break; 1105 } 1106 1107 pci->dbi_base2 = pci->dbi_base + pcie_dbi2_offset; 1108 1109 /* 1110 * FIXME: Ideally, dbi2 base address should come from DT. But since only IMX95 is defining 1111 * "dbi2" in DT, "dbi_base2" is set to NULL here for that platform alone so that the DWC 1112 * core code can fetch that from DT. But once all platform DTs were fixed, this and the 1113 * above "dbi_base2" setting should be removed. 1114 */ 1115 if (device_property_match_string(dev, "reg-names", "dbi2") >= 0) 1116 pci->dbi_base2 = NULL; 1117 1118 if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT)) 1119 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); 1120 1121 ret = dw_pcie_ep_init(ep); 1122 if (ret) { 1123 dev_err(dev, "failed to initialize endpoint\n"); 1124 return ret; 1125 } 1126 1127 ret = dw_pcie_ep_init_registers(ep); 1128 if (ret) { 1129 dev_err(dev, "Failed to initialize DWC endpoint registers\n"); 1130 dw_pcie_ep_deinit(ep); 1131 return ret; 1132 } 1133 1134 dw_pcie_ep_init_notify(ep); 1135 1136 /* Start LTSSM. */ 1137 imx6_pcie_ltssm_enable(dev); 1138 1139 return 0; 1140 } 1141 1142 static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie) 1143 { 1144 struct device *dev = imx6_pcie->pci->dev; 1145 1146 /* Some variants have a turnoff reset in DT */ 1147 if (imx6_pcie->turnoff_reset) { 1148 reset_control_assert(imx6_pcie->turnoff_reset); 1149 reset_control_deassert(imx6_pcie->turnoff_reset); 1150 goto pm_turnoff_sleep; 1151 } 1152 1153 /* Others poke directly at IOMUXC registers */ 1154 switch (imx6_pcie->drvdata->variant) { 1155 case IMX6SX: 1156 case IMX6QP: 1157 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 1158 IMX6SX_GPR12_PCIE_PM_TURN_OFF, 1159 IMX6SX_GPR12_PCIE_PM_TURN_OFF); 1160 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, 1161 IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0); 1162 break; 1163 default: 1164 dev_err(dev, "PME_Turn_Off not implemented\n"); 1165 return; 1166 } 1167 1168 /* 1169 * Components with an upstream port must respond to 1170 * PME_Turn_Off with PME_TO_Ack but we can't check. 1171 * 1172 * The standard recommends a 1-10ms timeout after which to 1173 * proceed anyway as if acks were received. 1174 */ 1175 pm_turnoff_sleep: 1176 usleep_range(1000, 10000); 1177 } 1178 1179 static void imx6_pcie_msi_save_restore(struct imx6_pcie *imx6_pcie, bool save) 1180 { 1181 u8 offset; 1182 u16 val; 1183 struct dw_pcie *pci = imx6_pcie->pci; 1184 1185 if (pci_msi_enabled()) { 1186 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); 1187 if (save) { 1188 val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS); 1189 imx6_pcie->msi_ctrl = val; 1190 } else { 1191 dw_pcie_dbi_ro_wr_en(pci); 1192 val = imx6_pcie->msi_ctrl; 1193 dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val); 1194 dw_pcie_dbi_ro_wr_dis(pci); 1195 } 1196 } 1197 } 1198 1199 static int imx6_pcie_suspend_noirq(struct device *dev) 1200 { 1201 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 1202 struct dw_pcie_rp *pp = &imx6_pcie->pci->pp; 1203 1204 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) 1205 return 0; 1206 1207 imx6_pcie_msi_save_restore(imx6_pcie, true); 1208 imx6_pcie_pm_turnoff(imx6_pcie); 1209 imx6_pcie_stop_link(imx6_pcie->pci); 1210 imx6_pcie_host_exit(pp); 1211 1212 return 0; 1213 } 1214 1215 static int imx6_pcie_resume_noirq(struct device *dev) 1216 { 1217 int ret; 1218 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); 1219 struct dw_pcie_rp *pp = &imx6_pcie->pci->pp; 1220 1221 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) 1222 return 0; 1223 1224 ret = imx6_pcie_host_init(pp); 1225 if (ret) 1226 return ret; 1227 imx6_pcie_msi_save_restore(imx6_pcie, false); 1228 dw_pcie_setup_rc(pp); 1229 1230 if (imx6_pcie->link_is_up) 1231 imx6_pcie_start_link(imx6_pcie->pci); 1232 1233 return 0; 1234 } 1235 1236 static const struct dev_pm_ops imx6_pcie_pm_ops = { 1237 NOIRQ_SYSTEM_SLEEP_PM_OPS(imx6_pcie_suspend_noirq, 1238 imx6_pcie_resume_noirq) 1239 }; 1240 1241 static int imx6_pcie_probe(struct platform_device *pdev) 1242 { 1243 struct device *dev = &pdev->dev; 1244 struct dw_pcie *pci; 1245 struct imx6_pcie *imx6_pcie; 1246 struct device_node *np; 1247 struct resource *dbi_base; 1248 struct device_node *node = dev->of_node; 1249 int ret; 1250 u16 val; 1251 int i; 1252 1253 imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL); 1254 if (!imx6_pcie) 1255 return -ENOMEM; 1256 1257 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 1258 if (!pci) 1259 return -ENOMEM; 1260 1261 pci->dev = dev; 1262 pci->ops = &dw_pcie_ops; 1263 pci->pp.ops = &imx6_pcie_host_ops; 1264 1265 imx6_pcie->pci = pci; 1266 imx6_pcie->drvdata = of_device_get_match_data(dev); 1267 1268 /* Find the PHY if one is defined, only imx7d uses it */ 1269 np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); 1270 if (np) { 1271 struct resource res; 1272 1273 ret = of_address_to_resource(np, 0, &res); 1274 if (ret) { 1275 dev_err(dev, "Unable to map PCIe PHY\n"); 1276 return ret; 1277 } 1278 imx6_pcie->phy_base = devm_ioremap_resource(dev, &res); 1279 if (IS_ERR(imx6_pcie->phy_base)) 1280 return PTR_ERR(imx6_pcie->phy_base); 1281 } 1282 1283 pci->dbi_base = devm_platform_get_and_ioremap_resource(pdev, 0, &dbi_base); 1284 if (IS_ERR(pci->dbi_base)) 1285 return PTR_ERR(pci->dbi_base); 1286 1287 /* Fetch GPIOs */ 1288 imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0); 1289 imx6_pcie->gpio_active_high = of_property_read_bool(node, 1290 "reset-gpio-active-high"); 1291 if (gpio_is_valid(imx6_pcie->reset_gpio)) { 1292 ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio, 1293 imx6_pcie->gpio_active_high ? 1294 GPIOF_OUT_INIT_HIGH : 1295 GPIOF_OUT_INIT_LOW, 1296 "PCIe reset"); 1297 if (ret) { 1298 dev_err(dev, "unable to get reset gpio\n"); 1299 return ret; 1300 } 1301 } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) { 1302 return imx6_pcie->reset_gpio; 1303 } 1304 1305 if (imx6_pcie->drvdata->clks_cnt >= IMX6_PCIE_MAX_CLKS) 1306 return dev_err_probe(dev, -ENOMEM, "clks_cnt is too big\n"); 1307 1308 for (i = 0; i < imx6_pcie->drvdata->clks_cnt; i++) 1309 imx6_pcie->clks[i].id = imx6_pcie->drvdata->clk_names[i]; 1310 1311 /* Fetch clocks */ 1312 ret = devm_clk_bulk_get(dev, imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); 1313 if (ret) 1314 return ret; 1315 1316 if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHYDRV)) { 1317 imx6_pcie->phy = devm_phy_get(dev, "pcie-phy"); 1318 if (IS_ERR(imx6_pcie->phy)) 1319 return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy), 1320 "failed to get pcie phy\n"); 1321 } 1322 1323 if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_APP_RESET)) { 1324 imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps"); 1325 if (IS_ERR(imx6_pcie->apps_reset)) 1326 return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset), 1327 "failed to get pcie apps reset control\n"); 1328 } 1329 1330 if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHY_RESET)) { 1331 imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy"); 1332 if (IS_ERR(imx6_pcie->pciephy_reset)) 1333 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pciephy_reset), 1334 "Failed to get PCIEPHY reset control\n"); 1335 } 1336 1337 switch (imx6_pcie->drvdata->variant) { 1338 case IMX8MQ: 1339 case IMX8MQ_EP: 1340 case IMX7D: 1341 if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) 1342 imx6_pcie->controller_id = 1; 1343 break; 1344 default: 1345 break; 1346 } 1347 1348 /* Grab turnoff reset */ 1349 imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff"); 1350 if (IS_ERR(imx6_pcie->turnoff_reset)) { 1351 dev_err(dev, "Failed to get TURNOFF reset control\n"); 1352 return PTR_ERR(imx6_pcie->turnoff_reset); 1353 } 1354 1355 if (imx6_pcie->drvdata->gpr) { 1356 /* Grab GPR config register range */ 1357 imx6_pcie->iomuxc_gpr = 1358 syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr); 1359 if (IS_ERR(imx6_pcie->iomuxc_gpr)) 1360 return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr), 1361 "unable to find iomuxc registers\n"); 1362 } 1363 1364 if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_SERDES)) { 1365 void __iomem *off = devm_platform_ioremap_resource_byname(pdev, "app"); 1366 1367 if (IS_ERR(off)) 1368 return dev_err_probe(dev, PTR_ERR(off), 1369 "unable to find serdes registers\n"); 1370 1371 static const struct regmap_config regmap_config = { 1372 .reg_bits = 32, 1373 .val_bits = 32, 1374 .reg_stride = 4, 1375 }; 1376 1377 imx6_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, ®map_config); 1378 if (IS_ERR(imx6_pcie->iomuxc_gpr)) 1379 return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr), 1380 "unable to find iomuxc registers\n"); 1381 } 1382 1383 /* Grab PCIe PHY Tx Settings */ 1384 if (of_property_read_u32(node, "fsl,tx-deemph-gen1", 1385 &imx6_pcie->tx_deemph_gen1)) 1386 imx6_pcie->tx_deemph_gen1 = 0; 1387 1388 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db", 1389 &imx6_pcie->tx_deemph_gen2_3p5db)) 1390 imx6_pcie->tx_deemph_gen2_3p5db = 0; 1391 1392 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db", 1393 &imx6_pcie->tx_deemph_gen2_6db)) 1394 imx6_pcie->tx_deemph_gen2_6db = 20; 1395 1396 if (of_property_read_u32(node, "fsl,tx-swing-full", 1397 &imx6_pcie->tx_swing_full)) 1398 imx6_pcie->tx_swing_full = 127; 1399 1400 if (of_property_read_u32(node, "fsl,tx-swing-low", 1401 &imx6_pcie->tx_swing_low)) 1402 imx6_pcie->tx_swing_low = 127; 1403 1404 /* Limit link speed */ 1405 pci->link_gen = 1; 1406 of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen); 1407 1408 imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie"); 1409 if (IS_ERR(imx6_pcie->vpcie)) { 1410 if (PTR_ERR(imx6_pcie->vpcie) != -ENODEV) 1411 return PTR_ERR(imx6_pcie->vpcie); 1412 imx6_pcie->vpcie = NULL; 1413 } 1414 1415 imx6_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph"); 1416 if (IS_ERR(imx6_pcie->vph)) { 1417 if (PTR_ERR(imx6_pcie->vph) != -ENODEV) 1418 return PTR_ERR(imx6_pcie->vph); 1419 imx6_pcie->vph = NULL; 1420 } 1421 1422 platform_set_drvdata(pdev, imx6_pcie); 1423 1424 ret = imx6_pcie_attach_pd(dev); 1425 if (ret) 1426 return ret; 1427 1428 if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE) { 1429 ret = imx6_add_pcie_ep(imx6_pcie, pdev); 1430 if (ret < 0) 1431 return ret; 1432 } else { 1433 ret = dw_pcie_host_init(&pci->pp); 1434 if (ret < 0) 1435 return ret; 1436 1437 if (pci_msi_enabled()) { 1438 u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); 1439 1440 val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS); 1441 val |= PCI_MSI_FLAGS_ENABLE; 1442 dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val); 1443 } 1444 } 1445 1446 return 0; 1447 } 1448 1449 static void imx6_pcie_shutdown(struct platform_device *pdev) 1450 { 1451 struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev); 1452 1453 /* bring down link, so bootloader gets clean state in case of reboot */ 1454 imx6_pcie_assert_core_reset(imx6_pcie); 1455 } 1456 1457 static const char * const imx6q_clks[] = {"pcie_bus", "pcie", "pcie_phy"}; 1458 static const char * const imx8mm_clks[] = {"pcie_bus", "pcie", "pcie_aux"}; 1459 static const char * const imx8mq_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"}; 1460 static const char * const imx6sx_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"}; 1461 1462 static const struct imx6_pcie_drvdata drvdata[] = { 1463 [IMX6Q] = { 1464 .variant = IMX6Q, 1465 .flags = IMX6_PCIE_FLAG_IMX6_PHY | 1466 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE, 1467 .dbi_length = 0x200, 1468 .gpr = "fsl,imx6q-iomuxc-gpr", 1469 .clk_names = imx6q_clks, 1470 .clks_cnt = ARRAY_SIZE(imx6q_clks), 1471 .ltssm_off = IOMUXC_GPR12, 1472 .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, 1473 .mode_off[0] = IOMUXC_GPR12, 1474 .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1475 .init_phy = imx6_pcie_init_phy, 1476 }, 1477 [IMX6SX] = { 1478 .variant = IMX6SX, 1479 .flags = IMX6_PCIE_FLAG_IMX6_PHY | 1480 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | 1481 IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, 1482 .gpr = "fsl,imx6q-iomuxc-gpr", 1483 .clk_names = imx6sx_clks, 1484 .clks_cnt = ARRAY_SIZE(imx6sx_clks), 1485 .ltssm_off = IOMUXC_GPR12, 1486 .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, 1487 .mode_off[0] = IOMUXC_GPR12, 1488 .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1489 .init_phy = imx6sx_pcie_init_phy, 1490 }, 1491 [IMX6QP] = { 1492 .variant = IMX6QP, 1493 .flags = IMX6_PCIE_FLAG_IMX6_PHY | 1494 IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | 1495 IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, 1496 .dbi_length = 0x200, 1497 .gpr = "fsl,imx6q-iomuxc-gpr", 1498 .clk_names = imx6q_clks, 1499 .clks_cnt = ARRAY_SIZE(imx6q_clks), 1500 .ltssm_off = IOMUXC_GPR12, 1501 .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, 1502 .mode_off[0] = IOMUXC_GPR12, 1503 .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1504 .init_phy = imx6_pcie_init_phy, 1505 }, 1506 [IMX7D] = { 1507 .variant = IMX7D, 1508 .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | 1509 IMX6_PCIE_FLAG_HAS_APP_RESET | 1510 IMX6_PCIE_FLAG_HAS_PHY_RESET, 1511 .gpr = "fsl,imx7d-iomuxc-gpr", 1512 .clk_names = imx6q_clks, 1513 .clks_cnt = ARRAY_SIZE(imx6q_clks), 1514 .mode_off[0] = IOMUXC_GPR12, 1515 .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1516 .init_phy = imx7d_pcie_init_phy, 1517 }, 1518 [IMX8MQ] = { 1519 .variant = IMX8MQ, 1520 .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | 1521 IMX6_PCIE_FLAG_HAS_PHY_RESET, 1522 .gpr = "fsl,imx8mq-iomuxc-gpr", 1523 .clk_names = imx8mq_clks, 1524 .clks_cnt = ARRAY_SIZE(imx8mq_clks), 1525 .mode_off[0] = IOMUXC_GPR12, 1526 .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1527 .mode_off[1] = IOMUXC_GPR12, 1528 .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, 1529 .init_phy = imx8mq_pcie_init_phy, 1530 }, 1531 [IMX8MM] = { 1532 .variant = IMX8MM, 1533 .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | 1534 IMX6_PCIE_FLAG_HAS_PHYDRV | 1535 IMX6_PCIE_FLAG_HAS_APP_RESET, 1536 .gpr = "fsl,imx8mm-iomuxc-gpr", 1537 .clk_names = imx8mm_clks, 1538 .clks_cnt = ARRAY_SIZE(imx8mm_clks), 1539 .mode_off[0] = IOMUXC_GPR12, 1540 .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1541 }, 1542 [IMX8MP] = { 1543 .variant = IMX8MP, 1544 .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | 1545 IMX6_PCIE_FLAG_HAS_PHYDRV | 1546 IMX6_PCIE_FLAG_HAS_APP_RESET, 1547 .gpr = "fsl,imx8mp-iomuxc-gpr", 1548 .clk_names = imx8mm_clks, 1549 .clks_cnt = ARRAY_SIZE(imx8mm_clks), 1550 .mode_off[0] = IOMUXC_GPR12, 1551 .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1552 }, 1553 [IMX95] = { 1554 .variant = IMX95, 1555 .flags = IMX6_PCIE_FLAG_HAS_SERDES, 1556 .clk_names = imx8mq_clks, 1557 .clks_cnt = ARRAY_SIZE(imx8mq_clks), 1558 .ltssm_off = IMX95_PE0_GEN_CTRL_3, 1559 .ltssm_mask = IMX95_PCIE_LTSSM_EN, 1560 .mode_off[0] = IMX95_PE0_GEN_CTRL_1, 1561 .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE, 1562 .init_phy = imx95_pcie_init_phy, 1563 }, 1564 [IMX8MQ_EP] = { 1565 .variant = IMX8MQ_EP, 1566 .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | 1567 IMX6_PCIE_FLAG_HAS_PHY_RESET, 1568 .mode = DW_PCIE_EP_TYPE, 1569 .gpr = "fsl,imx8mq-iomuxc-gpr", 1570 .clk_names = imx8mq_clks, 1571 .clks_cnt = ARRAY_SIZE(imx8mq_clks), 1572 .mode_off[0] = IOMUXC_GPR12, 1573 .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1574 .mode_off[1] = IOMUXC_GPR12, 1575 .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, 1576 .epc_features = &imx8m_pcie_epc_features, 1577 .init_phy = imx8mq_pcie_init_phy, 1578 }, 1579 [IMX8MM_EP] = { 1580 .variant = IMX8MM_EP, 1581 .flags = IMX6_PCIE_FLAG_HAS_PHYDRV, 1582 .mode = DW_PCIE_EP_TYPE, 1583 .gpr = "fsl,imx8mm-iomuxc-gpr", 1584 .clk_names = imx8mm_clks, 1585 .clks_cnt = ARRAY_SIZE(imx8mm_clks), 1586 .mode_off[0] = IOMUXC_GPR12, 1587 .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1588 .epc_features = &imx8m_pcie_epc_features, 1589 }, 1590 [IMX8MP_EP] = { 1591 .variant = IMX8MP_EP, 1592 .flags = IMX6_PCIE_FLAG_HAS_PHYDRV, 1593 .mode = DW_PCIE_EP_TYPE, 1594 .gpr = "fsl,imx8mp-iomuxc-gpr", 1595 .clk_names = imx8mm_clks, 1596 .clks_cnt = ARRAY_SIZE(imx8mm_clks), 1597 .mode_off[0] = IOMUXC_GPR12, 1598 .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, 1599 .epc_features = &imx8m_pcie_epc_features, 1600 }, 1601 [IMX95_EP] = { 1602 .variant = IMX95_EP, 1603 .flags = IMX6_PCIE_FLAG_HAS_SERDES | 1604 IMX6_PCIE_FLAG_SUPPORT_64BIT, 1605 .clk_names = imx8mq_clks, 1606 .clks_cnt = ARRAY_SIZE(imx8mq_clks), 1607 .ltssm_off = IMX95_PE0_GEN_CTRL_3, 1608 .ltssm_mask = IMX95_PCIE_LTSSM_EN, 1609 .mode_off[0] = IMX95_PE0_GEN_CTRL_1, 1610 .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE, 1611 .init_phy = imx95_pcie_init_phy, 1612 .epc_features = &imx95_pcie_epc_features, 1613 .mode = DW_PCIE_EP_TYPE, 1614 }, 1615 }; 1616 1617 static const struct of_device_id imx6_pcie_of_match[] = { 1618 { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], }, 1619 { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], }, 1620 { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], }, 1621 { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], }, 1622 { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], }, 1623 { .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], }, 1624 { .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], }, 1625 { .compatible = "fsl,imx95-pcie", .data = &drvdata[IMX95], }, 1626 { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], }, 1627 { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], }, 1628 { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], }, 1629 { .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], }, 1630 {}, 1631 }; 1632 1633 static struct platform_driver imx6_pcie_driver = { 1634 .driver = { 1635 .name = "imx6q-pcie", 1636 .of_match_table = imx6_pcie_of_match, 1637 .suppress_bind_attrs = true, 1638 .pm = &imx6_pcie_pm_ops, 1639 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1640 }, 1641 .probe = imx6_pcie_probe, 1642 .shutdown = imx6_pcie_shutdown, 1643 }; 1644 1645 static void imx6_pcie_quirk(struct pci_dev *dev) 1646 { 1647 struct pci_bus *bus = dev->bus; 1648 struct dw_pcie_rp *pp = bus->sysdata; 1649 1650 /* Bus parent is the PCI bridge, its parent is this platform driver */ 1651 if (!bus->dev.parent || !bus->dev.parent->parent) 1652 return; 1653 1654 /* Make sure we only quirk devices associated with this driver */ 1655 if (bus->dev.parent->parent->driver != &imx6_pcie_driver.driver) 1656 return; 1657 1658 if (pci_is_root_bus(bus)) { 1659 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 1660 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); 1661 1662 /* 1663 * Limit config length to avoid the kernel reading beyond 1664 * the register set and causing an abort on i.MX 6Quad 1665 */ 1666 if (imx6_pcie->drvdata->dbi_length) { 1667 dev->cfg_size = imx6_pcie->drvdata->dbi_length; 1668 dev_info(&dev->dev, "Limiting cfg_size to %d\n", 1669 dev->cfg_size); 1670 } 1671 } 1672 } 1673 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, 0xabcd, 1674 PCI_CLASS_BRIDGE_PCI, 8, imx6_pcie_quirk); 1675 1676 static int __init imx6_pcie_init(void) 1677 { 1678 #ifdef CONFIG_ARM 1679 struct device_node *np; 1680 1681 np = of_find_matching_node(NULL, imx6_pcie_of_match); 1682 if (!np) 1683 return -ENODEV; 1684 of_node_put(np); 1685 1686 /* 1687 * Since probe() can be deferred we need to make sure that 1688 * hook_fault_code is not called after __init memory is freed 1689 * by kernel and since imx6q_pcie_abort_handler() is a no-op, 1690 * we can install the handler here without risking it 1691 * accessing some uninitialized driver state. 1692 */ 1693 hook_fault_code(8, imx6q_pcie_abort_handler, SIGBUS, 0, 1694 "external abort on non-linefetch"); 1695 #endif 1696 1697 return platform_driver_register(&imx6_pcie_driver); 1698 } 1699 device_initcall(imx6_pcie_init); 1700