1*6e0832faSShawn Lin# SPDX-License-Identifier: GPL-2.0 2*6e0832faSShawn Lin 3*6e0832faSShawn Linmenu "DesignWare PCI Core Support" 4*6e0832faSShawn Lin depends on PCI 5*6e0832faSShawn Lin 6*6e0832faSShawn Linconfig PCIE_DW 7*6e0832faSShawn Lin bool 8*6e0832faSShawn Lin 9*6e0832faSShawn Linconfig PCIE_DW_HOST 10*6e0832faSShawn Lin bool 11*6e0832faSShawn Lin depends on PCI_MSI_IRQ_DOMAIN 12*6e0832faSShawn Lin select PCIE_DW 13*6e0832faSShawn Lin 14*6e0832faSShawn Linconfig PCIE_DW_EP 15*6e0832faSShawn Lin bool 16*6e0832faSShawn Lin depends on PCI_ENDPOINT 17*6e0832faSShawn Lin select PCIE_DW 18*6e0832faSShawn Lin 19*6e0832faSShawn Linconfig PCI_DRA7XX 20*6e0832faSShawn Lin bool 21*6e0832faSShawn Lin 22*6e0832faSShawn Linconfig PCI_DRA7XX_HOST 23*6e0832faSShawn Lin bool "TI DRA7xx PCIe controller Host Mode" 24*6e0832faSShawn Lin depends on SOC_DRA7XX || COMPILE_TEST 25*6e0832faSShawn Lin depends on PCI_MSI_IRQ_DOMAIN 26*6e0832faSShawn Lin depends on OF && HAS_IOMEM && TI_PIPE3 27*6e0832faSShawn Lin select PCIE_DW_HOST 28*6e0832faSShawn Lin select PCI_DRA7XX 29*6e0832faSShawn Lin default y 30*6e0832faSShawn Lin help 31*6e0832faSShawn Lin Enables support for the PCIe controller in the DRA7xx SoC to work in 32*6e0832faSShawn Lin host mode. There are two instances of PCIe controller in DRA7xx. 33*6e0832faSShawn Lin This controller can work either as EP or RC. In order to enable 34*6e0832faSShawn Lin host-specific features PCI_DRA7XX_HOST must be selected and in order 35*6e0832faSShawn Lin to enable device-specific features PCI_DRA7XX_EP must be selected. 36*6e0832faSShawn Lin This uses the DesignWare core. 37*6e0832faSShawn Lin 38*6e0832faSShawn Linconfig PCI_DRA7XX_EP 39*6e0832faSShawn Lin bool "TI DRA7xx PCIe controller Endpoint Mode" 40*6e0832faSShawn Lin depends on SOC_DRA7XX || COMPILE_TEST 41*6e0832faSShawn Lin depends on PCI_ENDPOINT 42*6e0832faSShawn Lin depends on OF && HAS_IOMEM && TI_PIPE3 43*6e0832faSShawn Lin select PCIE_DW_EP 44*6e0832faSShawn Lin select PCI_DRA7XX 45*6e0832faSShawn Lin help 46*6e0832faSShawn Lin Enables support for the PCIe controller in the DRA7xx SoC to work in 47*6e0832faSShawn Lin endpoint mode. There are two instances of PCIe controller in DRA7xx. 48*6e0832faSShawn Lin This controller can work either as EP or RC. In order to enable 49*6e0832faSShawn Lin host-specific features PCI_DRA7XX_HOST must be selected and in order 50*6e0832faSShawn Lin to enable device-specific features PCI_DRA7XX_EP must be selected. 51*6e0832faSShawn Lin This uses the DesignWare core. 52*6e0832faSShawn Lin 53*6e0832faSShawn Linconfig PCIE_DW_PLAT 54*6e0832faSShawn Lin bool 55*6e0832faSShawn Lin 56*6e0832faSShawn Linconfig PCIE_DW_PLAT_HOST 57*6e0832faSShawn Lin bool "Platform bus based DesignWare PCIe Controller - Host mode" 58*6e0832faSShawn Lin depends on PCI && PCI_MSI_IRQ_DOMAIN 59*6e0832faSShawn Lin select PCIE_DW_HOST 60*6e0832faSShawn Lin select PCIE_DW_PLAT 61*6e0832faSShawn Lin default y 62*6e0832faSShawn Lin help 63*6e0832faSShawn Lin Enables support for the PCIe controller in the Designware IP to 64*6e0832faSShawn Lin work in host mode. There are two instances of PCIe controller in 65*6e0832faSShawn Lin Designware IP. 66*6e0832faSShawn Lin This controller can work either as EP or RC. In order to enable 67*6e0832faSShawn Lin host-specific features PCIE_DW_PLAT_HOST must be selected and in 68*6e0832faSShawn Lin order to enable device-specific features PCI_DW_PLAT_EP must be 69*6e0832faSShawn Lin selected. 70*6e0832faSShawn Lin 71*6e0832faSShawn Linconfig PCIE_DW_PLAT_EP 72*6e0832faSShawn Lin bool "Platform bus based DesignWare PCIe Controller - Endpoint mode" 73*6e0832faSShawn Lin depends on PCI && PCI_MSI_IRQ_DOMAIN 74*6e0832faSShawn Lin depends on PCI_ENDPOINT 75*6e0832faSShawn Lin select PCIE_DW_EP 76*6e0832faSShawn Lin select PCIE_DW_PLAT 77*6e0832faSShawn Lin help 78*6e0832faSShawn Lin Enables support for the PCIe controller in the Designware IP to 79*6e0832faSShawn Lin work in endpoint mode. There are two instances of PCIe controller 80*6e0832faSShawn Lin in Designware IP. 81*6e0832faSShawn Lin This controller can work either as EP or RC. In order to enable 82*6e0832faSShawn Lin host-specific features PCIE_DW_PLAT_HOST must be selected and in 83*6e0832faSShawn Lin order to enable device-specific features PCI_DW_PLAT_EP must be 84*6e0832faSShawn Lin selected. 85*6e0832faSShawn Lin 86*6e0832faSShawn Linconfig PCI_EXYNOS 87*6e0832faSShawn Lin bool "Samsung Exynos PCIe controller" 88*6e0832faSShawn Lin depends on SOC_EXYNOS5440 || COMPILE_TEST 89*6e0832faSShawn Lin depends on PCI_MSI_IRQ_DOMAIN 90*6e0832faSShawn Lin select PCIE_DW_HOST 91*6e0832faSShawn Lin 92*6e0832faSShawn Linconfig PCI_IMX6 93*6e0832faSShawn Lin bool "Freescale i.MX6 PCIe controller" 94*6e0832faSShawn Lin depends on SOC_IMX6Q || (ARM && COMPILE_TEST) 95*6e0832faSShawn Lin depends on PCI_MSI_IRQ_DOMAIN 96*6e0832faSShawn Lin select PCIE_DW_HOST 97*6e0832faSShawn Lin 98*6e0832faSShawn Linconfig PCIE_SPEAR13XX 99*6e0832faSShawn Lin bool "STMicroelectronics SPEAr PCIe controller" 100*6e0832faSShawn Lin depends on ARCH_SPEAR13XX || COMPILE_TEST 101*6e0832faSShawn Lin depends on PCI_MSI_IRQ_DOMAIN 102*6e0832faSShawn Lin select PCIE_DW_HOST 103*6e0832faSShawn Lin help 104*6e0832faSShawn Lin Say Y here if you want PCIe support on SPEAr13XX SoCs. 105*6e0832faSShawn Lin 106*6e0832faSShawn Linconfig PCI_KEYSTONE 107*6e0832faSShawn Lin bool "TI Keystone PCIe controller" 108*6e0832faSShawn Lin depends on ARCH_KEYSTONE || (ARM && COMPILE_TEST) 109*6e0832faSShawn Lin depends on PCI_MSI_IRQ_DOMAIN 110*6e0832faSShawn Lin select PCIE_DW_HOST 111*6e0832faSShawn Lin help 112*6e0832faSShawn Lin Say Y here if you want to enable PCI controller support on Keystone 113*6e0832faSShawn Lin SoCs. The PCI controller on Keystone is based on DesignWare hardware 114*6e0832faSShawn Lin and therefore the driver re-uses the DesignWare core functions to 115*6e0832faSShawn Lin implement the driver. 116*6e0832faSShawn Lin 117*6e0832faSShawn Linconfig PCI_LAYERSCAPE 118*6e0832faSShawn Lin bool "Freescale Layerscape PCIe controller" 119*6e0832faSShawn Lin depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST) 120*6e0832faSShawn Lin depends on PCI_MSI_IRQ_DOMAIN 121*6e0832faSShawn Lin select MFD_SYSCON 122*6e0832faSShawn Lin select PCIE_DW_HOST 123*6e0832faSShawn Lin help 124*6e0832faSShawn Lin Say Y here if you want PCIe controller support on Layerscape SoCs. 125*6e0832faSShawn Lin 126*6e0832faSShawn Linconfig PCI_HISI 127*6e0832faSShawn Lin depends on OF && (ARM64 || COMPILE_TEST) 128*6e0832faSShawn Lin bool "HiSilicon Hip05 and Hip06 SoCs PCIe controllers" 129*6e0832faSShawn Lin depends on PCI_MSI_IRQ_DOMAIN 130*6e0832faSShawn Lin select PCIE_DW_HOST 131*6e0832faSShawn Lin select PCI_HOST_COMMON 132*6e0832faSShawn Lin help 133*6e0832faSShawn Lin Say Y here if you want PCIe controller support on HiSilicon 134*6e0832faSShawn Lin Hip05 and Hip06 SoCs 135*6e0832faSShawn Lin 136*6e0832faSShawn Linconfig PCIE_QCOM 137*6e0832faSShawn Lin bool "Qualcomm PCIe controller" 138*6e0832faSShawn Lin depends on OF && (ARCH_QCOM || COMPILE_TEST) 139*6e0832faSShawn Lin depends on PCI_MSI_IRQ_DOMAIN 140*6e0832faSShawn Lin select PCIE_DW_HOST 141*6e0832faSShawn Lin help 142*6e0832faSShawn Lin Say Y here to enable PCIe controller support on Qualcomm SoCs. The 143*6e0832faSShawn Lin PCIe controller uses the DesignWare core plus Qualcomm-specific 144*6e0832faSShawn Lin hardware wrappers. 145*6e0832faSShawn Lin 146*6e0832faSShawn Linconfig PCIE_ARMADA_8K 147*6e0832faSShawn Lin bool "Marvell Armada-8K PCIe controller" 148*6e0832faSShawn Lin depends on ARCH_MVEBU || COMPILE_TEST 149*6e0832faSShawn Lin depends on PCI_MSI_IRQ_DOMAIN 150*6e0832faSShawn Lin select PCIE_DW_HOST 151*6e0832faSShawn Lin help 152*6e0832faSShawn Lin Say Y here if you want to enable PCIe controller support on 153*6e0832faSShawn Lin Armada-8K SoCs. The PCIe controller on Armada-8K is based on 154*6e0832faSShawn Lin DesignWare hardware and therefore the driver re-uses the 155*6e0832faSShawn Lin DesignWare core functions to implement the driver. 156*6e0832faSShawn Lin 157*6e0832faSShawn Linconfig PCIE_ARTPEC6 158*6e0832faSShawn Lin bool 159*6e0832faSShawn Lin 160*6e0832faSShawn Linconfig PCIE_ARTPEC6_HOST 161*6e0832faSShawn Lin bool "Axis ARTPEC-6 PCIe controller Host Mode" 162*6e0832faSShawn Lin depends on MACH_ARTPEC6 || COMPILE_TEST 163*6e0832faSShawn Lin depends on PCI_MSI_IRQ_DOMAIN 164*6e0832faSShawn Lin select PCIE_DW_HOST 165*6e0832faSShawn Lin select PCIE_ARTPEC6 166*6e0832faSShawn Lin help 167*6e0832faSShawn Lin Enables support for the PCIe controller in the ARTPEC-6 SoC to work in 168*6e0832faSShawn Lin host mode. This uses the DesignWare core. 169*6e0832faSShawn Lin 170*6e0832faSShawn Linconfig PCIE_ARTPEC6_EP 171*6e0832faSShawn Lin bool "Axis ARTPEC-6 PCIe controller Endpoint Mode" 172*6e0832faSShawn Lin depends on MACH_ARTPEC6 || COMPILE_TEST 173*6e0832faSShawn Lin depends on PCI_ENDPOINT 174*6e0832faSShawn Lin select PCIE_DW_EP 175*6e0832faSShawn Lin select PCIE_ARTPEC6 176*6e0832faSShawn Lin help 177*6e0832faSShawn Lin Enables support for the PCIe controller in the ARTPEC-6 SoC to work in 178*6e0832faSShawn Lin endpoint mode. This uses the DesignWare core. 179*6e0832faSShawn Lin 180*6e0832faSShawn Linconfig PCIE_KIRIN 181*6e0832faSShawn Lin depends on OF && (ARM64 || COMPILE_TEST) 182*6e0832faSShawn Lin bool "HiSilicon Kirin series SoCs PCIe controllers" 183*6e0832faSShawn Lin depends on PCI_MSI_IRQ_DOMAIN 184*6e0832faSShawn Lin select PCIE_DW_HOST 185*6e0832faSShawn Lin help 186*6e0832faSShawn Lin Say Y here if you want PCIe controller support 187*6e0832faSShawn Lin on HiSilicon Kirin series SoCs. 188*6e0832faSShawn Lin 189*6e0832faSShawn Linconfig PCIE_HISI_STB 190*6e0832faSShawn Lin bool "HiSilicon STB SoCs PCIe controllers" 191*6e0832faSShawn Lin depends on ARCH_HISI || COMPILE_TEST 192*6e0832faSShawn Lin depends on PCI_MSI_IRQ_DOMAIN 193*6e0832faSShawn Lin select PCIE_DW_HOST 194*6e0832faSShawn Lin help 195*6e0832faSShawn Lin Say Y here if you want PCIe controller support on HiSilicon STB SoCs 196*6e0832faSShawn Lin 197*6e0832faSShawn Linendmenu 198