1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2024 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "debug.h" 7 #include "mac.h" 8 #include "phy.h" 9 #include "reg.h" 10 #include "rtw8852b_common.h" 11 #include "sar.h" 12 #include "util.h" 13 14 static const struct rtw89_reg3_def rtw8852bx_pmac_ht20_mcs7_tbl[] = { 15 {0x4580, 0x0000ffff, 0x0}, 16 {0x4580, 0xffff0000, 0x0}, 17 {0x4584, 0x0000ffff, 0x0}, 18 {0x4584, 0xffff0000, 0x0}, 19 {0x4580, 0x0000ffff, 0x1}, 20 {0x4578, 0x00ffffff, 0x2018b}, 21 {0x4570, 0x03ffffff, 0x7}, 22 {0x4574, 0x03ffffff, 0x32407}, 23 {0x45b8, 0x00000010, 0x0}, 24 {0x45b8, 0x00000100, 0x0}, 25 {0x45b8, 0x00000080, 0x0}, 26 {0x45b8, 0x00000008, 0x0}, 27 {0x45a0, 0x0000ff00, 0x0}, 28 {0x45a0, 0xff000000, 0x1}, 29 {0x45a4, 0x0000ff00, 0x2}, 30 {0x45a4, 0xff000000, 0x3}, 31 {0x45b8, 0x00000020, 0x0}, 32 {0x4568, 0xe0000000, 0x0}, 33 {0x45b8, 0x00000002, 0x1}, 34 {0x456c, 0xe0000000, 0x0}, 35 {0x45b4, 0x00006000, 0x0}, 36 {0x45b4, 0x00001800, 0x1}, 37 {0x45b8, 0x00000040, 0x0}, 38 {0x45b8, 0x00000004, 0x0}, 39 {0x45b8, 0x00000200, 0x0}, 40 {0x4598, 0xf8000000, 0x0}, 41 {0x45b8, 0x00100000, 0x0}, 42 {0x45a8, 0x00000fc0, 0x0}, 43 {0x45b8, 0x00200000, 0x0}, 44 {0x45b0, 0x00000038, 0x0}, 45 {0x45b0, 0x000001c0, 0x0}, 46 {0x45a0, 0x000000ff, 0x0}, 47 {0x45b8, 0x00400000, 0x0}, 48 {0x4590, 0x000007ff, 0x0}, 49 {0x45b0, 0x00000e00, 0x0}, 50 {0x45ac, 0x0000001f, 0x0}, 51 {0x45b8, 0x00800000, 0x0}, 52 {0x45a8, 0x0003f000, 0x0}, 53 {0x45b8, 0x01000000, 0x0}, 54 {0x45b0, 0x00007000, 0x0}, 55 {0x45b0, 0x00038000, 0x0}, 56 {0x45a0, 0x00ff0000, 0x0}, 57 {0x45b8, 0x02000000, 0x0}, 58 {0x4590, 0x003ff800, 0x0}, 59 {0x45b0, 0x001c0000, 0x0}, 60 {0x45ac, 0x000003e0, 0x0}, 61 {0x45b8, 0x04000000, 0x0}, 62 {0x45a8, 0x00fc0000, 0x0}, 63 {0x45b8, 0x08000000, 0x0}, 64 {0x45b0, 0x00e00000, 0x0}, 65 {0x45b0, 0x07000000, 0x0}, 66 {0x45a4, 0x000000ff, 0x0}, 67 {0x45b8, 0x10000000, 0x0}, 68 {0x4594, 0x000007ff, 0x0}, 69 {0x45b0, 0x38000000, 0x0}, 70 {0x45ac, 0x00007c00, 0x0}, 71 {0x45b8, 0x20000000, 0x0}, 72 {0x45a8, 0x3f000000, 0x0}, 73 {0x45b8, 0x40000000, 0x0}, 74 {0x45b4, 0x00000007, 0x0}, 75 {0x45b4, 0x00000038, 0x0}, 76 {0x45a4, 0x00ff0000, 0x0}, 77 {0x45b8, 0x80000000, 0x0}, 78 {0x4594, 0x003ff800, 0x0}, 79 {0x45b4, 0x000001c0, 0x0}, 80 {0x4598, 0xf8000000, 0x0}, 81 {0x45b8, 0x00100000, 0x0}, 82 {0x45a8, 0x00000fc0, 0x7}, 83 {0x45b8, 0x00200000, 0x0}, 84 {0x45b0, 0x00000038, 0x0}, 85 {0x45b0, 0x000001c0, 0x0}, 86 {0x45a0, 0x000000ff, 0x0}, 87 {0x45b4, 0x06000000, 0x0}, 88 {0x45b0, 0x00000007, 0x0}, 89 {0x45b8, 0x00080000, 0x0}, 90 {0x45a8, 0x0000003f, 0x0}, 91 {0x457c, 0xffe00000, 0x1}, 92 {0x4530, 0xffffffff, 0x0}, 93 {0x4588, 0x00003fff, 0x0}, 94 {0x4598, 0x000001ff, 0x0}, 95 {0x4534, 0xffffffff, 0x0}, 96 {0x4538, 0xffffffff, 0x0}, 97 {0x453c, 0xffffffff, 0x0}, 98 {0x4588, 0x0fffc000, 0x0}, 99 {0x4598, 0x0003fe00, 0x0}, 100 {0x4540, 0xffffffff, 0x0}, 101 {0x4544, 0xffffffff, 0x0}, 102 {0x4548, 0xffffffff, 0x0}, 103 {0x458c, 0x00003fff, 0x0}, 104 {0x4598, 0x07fc0000, 0x0}, 105 {0x454c, 0xffffffff, 0x0}, 106 {0x4550, 0xffffffff, 0x0}, 107 {0x4554, 0xffffffff, 0x0}, 108 {0x458c, 0x0fffc000, 0x0}, 109 {0x459c, 0x000001ff, 0x0}, 110 {0x4558, 0xffffffff, 0x0}, 111 {0x455c, 0xffffffff, 0x0}, 112 {0x4530, 0xffffffff, 0x4e790001}, 113 {0x4588, 0x00003fff, 0x0}, 114 {0x4598, 0x000001ff, 0x1}, 115 {0x4534, 0xffffffff, 0x0}, 116 {0x4538, 0xffffffff, 0x4b}, 117 {0x45ac, 0x38000000, 0x7}, 118 {0x4588, 0xf0000000, 0x0}, 119 {0x459c, 0x7e000000, 0x0}, 120 {0x45b8, 0x00040000, 0x0}, 121 {0x45b8, 0x00020000, 0x0}, 122 {0x4590, 0xffc00000, 0x0}, 123 {0x45b8, 0x00004000, 0x0}, 124 {0x4578, 0xff000000, 0x0}, 125 {0x45b8, 0x00000400, 0x0}, 126 {0x45b8, 0x00000800, 0x0}, 127 {0x45b8, 0x00001000, 0x0}, 128 {0x45b8, 0x00002000, 0x0}, 129 {0x45b4, 0x00018000, 0x0}, 130 {0x45ac, 0x07800000, 0x0}, 131 {0x45b4, 0x00000600, 0x2}, 132 {0x459c, 0x0001fe00, 0x80}, 133 {0x45ac, 0x00078000, 0x3}, 134 {0x459c, 0x01fe0000, 0x1}, 135 }; 136 137 static const struct rtw89_reg3_def rtw8852bx_btc_preagc_en_defs[] = { 138 {0x46D0, GENMASK(1, 0), 0x3}, 139 {0x4790, GENMASK(1, 0), 0x3}, 140 {0x4AD4, GENMASK(31, 0), 0xf}, 141 {0x4AE0, GENMASK(31, 0), 0xf}, 142 {0x4688, GENMASK(31, 24), 0x80}, 143 {0x476C, GENMASK(31, 24), 0x80}, 144 {0x4694, GENMASK(7, 0), 0x80}, 145 {0x4694, GENMASK(15, 8), 0x80}, 146 {0x4778, GENMASK(7, 0), 0x80}, 147 {0x4778, GENMASK(15, 8), 0x80}, 148 {0x4AE4, GENMASK(23, 0), 0x780D1E}, 149 {0x4AEC, GENMASK(23, 0), 0x780D1E}, 150 {0x469C, GENMASK(31, 26), 0x34}, 151 {0x49F0, GENMASK(31, 26), 0x34}, 152 }; 153 154 static DECLARE_PHY_REG3_TBL(rtw8852bx_btc_preagc_en_defs); 155 156 static const struct rtw89_reg3_def rtw8852bx_btc_preagc_dis_defs[] = { 157 {0x46D0, GENMASK(1, 0), 0x0}, 158 {0x4790, GENMASK(1, 0), 0x0}, 159 {0x4AD4, GENMASK(31, 0), 0x60}, 160 {0x4AE0, GENMASK(31, 0), 0x60}, 161 {0x4688, GENMASK(31, 24), 0x1a}, 162 {0x476C, GENMASK(31, 24), 0x1a}, 163 {0x4694, GENMASK(7, 0), 0x2a}, 164 {0x4694, GENMASK(15, 8), 0x2a}, 165 {0x4778, GENMASK(7, 0), 0x2a}, 166 {0x4778, GENMASK(15, 8), 0x2a}, 167 {0x4AE4, GENMASK(23, 0), 0x79E99E}, 168 {0x4AEC, GENMASK(23, 0), 0x79E99E}, 169 {0x469C, GENMASK(31, 26), 0x26}, 170 {0x49F0, GENMASK(31, 26), 0x26}, 171 }; 172 173 static DECLARE_PHY_REG3_TBL(rtw8852bx_btc_preagc_dis_defs); 174 175 static void rtw8852be_efuse_parsing(struct rtw89_efuse *efuse, 176 struct rtw8852bx_efuse *map) 177 { 178 ether_addr_copy(efuse->addr, map->e.mac_addr); 179 efuse->rfe_type = map->rfe_type; 180 efuse->xtal_cap = map->xtal_k; 181 } 182 183 static void rtw8852bx_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 184 struct rtw8852bx_efuse *map) 185 { 186 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 187 struct rtw8852bx_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; 188 u8 i, j; 189 190 tssi->thermal[RF_PATH_A] = map->path_a_therm; 191 tssi->thermal[RF_PATH_B] = map->path_b_therm; 192 193 for (i = 0; i < RF_PATH_NUM_8852BX; i++) { 194 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 195 sizeof(ofst[i]->cck_tssi)); 196 197 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 198 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 199 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 200 i, j, tssi->tssi_cck[i][j]); 201 202 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 203 sizeof(ofst[i]->bw40_tssi)); 204 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 205 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 206 207 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 208 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 209 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 210 i, j, tssi->tssi_mcs[i][j]); 211 } 212 } 213 214 static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low) 215 { 216 if (high) 217 *high = sign_extend32(FIELD_GET(GENMASK(7, 4), data), 3); 218 if (low) 219 *low = sign_extend32(FIELD_GET(GENMASK(3, 0), data), 3); 220 221 return data != 0xff; 222 } 223 224 static void rtw8852bx_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev, 225 struct rtw8852bx_efuse *map) 226 { 227 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 228 bool valid = false; 229 230 valid |= _decode_efuse_gain(map->rx_gain_2g_cck, 231 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK], 232 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK]); 233 valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm, 234 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM], 235 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM]); 236 valid |= _decode_efuse_gain(map->rx_gain_5g_low, 237 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW], 238 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW]); 239 valid |= _decode_efuse_gain(map->rx_gain_5g_mid, 240 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID], 241 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID]); 242 valid |= _decode_efuse_gain(map->rx_gain_5g_high, 243 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH], 244 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH]); 245 246 gain->offset_valid = valid; 247 } 248 249 static int __rtw8852bx_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map, 250 enum rtw89_efuse_block block) 251 { 252 struct rtw89_efuse *efuse = &rtwdev->efuse; 253 struct rtw8852bx_efuse *map; 254 255 map = (struct rtw8852bx_efuse *)log_map; 256 257 efuse->country_code[0] = map->country_code[0]; 258 efuse->country_code[1] = map->country_code[1]; 259 rtw8852bx_efuse_parsing_tssi(rtwdev, map); 260 rtw8852bx_efuse_parsing_gain_offset(rtwdev, map); 261 262 switch (rtwdev->hci.type) { 263 case RTW89_HCI_TYPE_PCIE: 264 rtw8852be_efuse_parsing(efuse, map); 265 break; 266 default: 267 return -EOPNOTSUPP; 268 } 269 270 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 271 272 return 0; 273 } 274 275 static void rtw8852bx_phycap_parsing_power_cal(struct rtw89_dev *rtwdev, u8 *phycap_map) 276 { 277 #define PWR_K_CHK_OFFSET 0x5E9 278 #define PWR_K_CHK_VALUE 0xAA 279 u32 offset = PWR_K_CHK_OFFSET - rtwdev->chip->phycap_addr; 280 281 if (phycap_map[offset] == PWR_K_CHK_VALUE) 282 rtwdev->efuse.power_k_valid = true; 283 } 284 285 static void rtw8852bx_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 286 { 287 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 288 static const u32 tssi_trim_addr[RF_PATH_NUM_8852BX] = {0x5D6, 0x5AB}; 289 u32 addr = rtwdev->chip->phycap_addr; 290 bool pg = false; 291 u32 ofst; 292 u8 i, j; 293 294 for (i = 0; i < RF_PATH_NUM_8852BX; i++) { 295 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 296 /* addrs are in decreasing order */ 297 ofst = tssi_trim_addr[i] - addr - j; 298 tssi->tssi_trim[i][j] = phycap_map[ofst]; 299 300 if (phycap_map[ofst] != 0xff) 301 pg = true; 302 } 303 } 304 305 if (!pg) { 306 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 307 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 308 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 309 } 310 311 for (i = 0; i < RF_PATH_NUM_8852BX; i++) 312 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 313 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 314 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 315 i, j, tssi->tssi_trim[i][j], 316 tssi_trim_addr[i] - j); 317 } 318 319 static void rtw8852bx_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 320 u8 *phycap_map) 321 { 322 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 323 static const u32 thm_trim_addr[RF_PATH_NUM_8852BX] = {0x5DF, 0x5DC}; 324 u32 addr = rtwdev->chip->phycap_addr; 325 u8 i; 326 327 for (i = 0; i < RF_PATH_NUM_8852BX; i++) { 328 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 329 330 rtw89_debug(rtwdev, RTW89_DBG_RFK, 331 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 332 i, info->thermal_trim[i]); 333 334 if (info->thermal_trim[i] != 0xff) 335 info->pg_thermal_trim = true; 336 } 337 } 338 339 static void rtw8852bx_thermal_trim(struct rtw89_dev *rtwdev) 340 { 341 #define __thm_setting(raw) \ 342 ({ \ 343 u8 __v = (raw); \ 344 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 345 }) 346 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 347 u8 i, val; 348 349 if (!info->pg_thermal_trim) { 350 rtw89_debug(rtwdev, RTW89_DBG_RFK, 351 "[THERMAL][TRIM] no PG, do nothing\n"); 352 353 return; 354 } 355 356 for (i = 0; i < RF_PATH_NUM_8852BX; i++) { 357 val = __thm_setting(info->thermal_trim[i]); 358 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 359 360 rtw89_debug(rtwdev, RTW89_DBG_RFK, 361 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 362 i, val); 363 } 364 #undef __thm_setting 365 } 366 367 static void rtw8852bx_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 368 u8 *phycap_map) 369 { 370 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 371 static const u32 pabias_trim_addr[RF_PATH_NUM_8852BX] = {0x5DE, 0x5DB}; 372 u32 addr = rtwdev->chip->phycap_addr; 373 u8 i; 374 375 for (i = 0; i < RF_PATH_NUM_8852BX; i++) { 376 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 377 378 rtw89_debug(rtwdev, RTW89_DBG_RFK, 379 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 380 i, info->pa_bias_trim[i]); 381 382 if (info->pa_bias_trim[i] != 0xff) 383 info->pg_pa_bias_trim = true; 384 } 385 } 386 387 static void rtw8852bx_pa_bias_trim(struct rtw89_dev *rtwdev) 388 { 389 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 390 u8 pabias_2g, pabias_5g; 391 u8 i; 392 393 if (!info->pg_pa_bias_trim) { 394 rtw89_debug(rtwdev, RTW89_DBG_RFK, 395 "[PA_BIAS][TRIM] no PG, do nothing\n"); 396 397 return; 398 } 399 400 for (i = 0; i < RF_PATH_NUM_8852BX; i++) { 401 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); 402 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); 403 404 rtw89_debug(rtwdev, RTW89_DBG_RFK, 405 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 406 i, pabias_2g, pabias_5g); 407 408 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 409 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 410 } 411 } 412 413 static void rtw8852bx_phycap_parsing_gain_comp(struct rtw89_dev *rtwdev, u8 *phycap_map) 414 { 415 static const u32 comp_addrs[][RTW89_SUBBAND_2GHZ_5GHZ_NR] = { 416 {0x5BB, 0x5BA, 0, 0x5B9, 0x5B8}, 417 {0x590, 0x58F, 0, 0x58E, 0x58D}, 418 }; 419 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 420 u32 phycap_addr = rtwdev->chip->phycap_addr; 421 bool valid = false; 422 int path, i; 423 u8 data; 424 425 for (path = 0; path < 2; path++) 426 for (i = 0; i < RTW89_SUBBAND_2GHZ_5GHZ_NR; i++) { 427 if (comp_addrs[path][i] == 0) 428 continue; 429 430 data = phycap_map[comp_addrs[path][i] - phycap_addr]; 431 valid |= _decode_efuse_gain(data, NULL, 432 &gain->comp[path][i]); 433 } 434 435 gain->comp_valid = valid; 436 } 437 438 static int __rtw8852bx_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 439 { 440 rtw8852bx_phycap_parsing_power_cal(rtwdev, phycap_map); 441 rtw8852bx_phycap_parsing_tssi(rtwdev, phycap_map); 442 rtw8852bx_phycap_parsing_thermal_trim(rtwdev, phycap_map); 443 rtw8852bx_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 444 rtw8852bx_phycap_parsing_gain_comp(rtwdev, phycap_map); 445 446 return 0; 447 } 448 449 static void __rtw8852bx_power_trim(struct rtw89_dev *rtwdev) 450 { 451 rtw8852bx_thermal_trim(rtwdev); 452 rtw8852bx_pa_bias_trim(rtwdev); 453 } 454 455 static void __rtw8852bx_set_channel_mac(struct rtw89_dev *rtwdev, 456 const struct rtw89_chan *chan, 457 u8 mac_idx) 458 { 459 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx); 460 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 461 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx); 462 u8 txsc20 = 0, txsc40 = 0; 463 464 switch (chan->band_width) { 465 case RTW89_CHANNEL_WIDTH_80: 466 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_40); 467 fallthrough; 468 case RTW89_CHANNEL_WIDTH_40: 469 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_20); 470 break; 471 default: 472 break; 473 } 474 475 switch (chan->band_width) { 476 case RTW89_CHANNEL_WIDTH_80: 477 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1)); 478 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4)); 479 break; 480 case RTW89_CHANNEL_WIDTH_40: 481 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0)); 482 rtw89_write32(rtwdev, sub_carr, txsc20); 483 break; 484 case RTW89_CHANNEL_WIDTH_20: 485 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK); 486 rtw89_write32(rtwdev, sub_carr, 0); 487 break; 488 default: 489 break; 490 } 491 492 if (chan->channel > 14) { 493 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE); 494 rtw89_write8_set(rtwdev, chk_rate, 495 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 496 } else { 497 rtw89_write8_set(rtwdev, chk_rate, B_AX_BAND_MODE); 498 rtw89_write8_clr(rtwdev, chk_rate, 499 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 500 } 501 } 502 503 static const u32 rtw8852bx_sco_barker_threshold[14] = { 504 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6, 505 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4 506 }; 507 508 static const u32 rtw8852bx_sco_cck_threshold[14] = { 509 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724, 510 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed 511 }; 512 513 static void rtw8852bx_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 primary_ch) 514 { 515 u8 ch_element = primary_ch - 1; 516 517 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH, 518 rtw8852bx_sco_barker_threshold[ch_element]); 519 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH, 520 rtw8852bx_sco_cck_threshold[ch_element]); 521 } 522 523 static u8 rtw8852bx_sco_mapping(u8 central_ch) 524 { 525 if (central_ch == 1) 526 return 109; 527 else if (central_ch >= 2 && central_ch <= 6) 528 return 108; 529 else if (central_ch >= 7 && central_ch <= 10) 530 return 107; 531 else if (central_ch >= 11 && central_ch <= 14) 532 return 106; 533 else if (central_ch == 36 || central_ch == 38) 534 return 51; 535 else if (central_ch >= 40 && central_ch <= 58) 536 return 50; 537 else if (central_ch >= 60 && central_ch <= 64) 538 return 49; 539 else if (central_ch == 100 || central_ch == 102) 540 return 48; 541 else if (central_ch >= 104 && central_ch <= 126) 542 return 47; 543 else if (central_ch >= 128 && central_ch <= 151) 544 return 46; 545 else if (central_ch >= 153 && central_ch <= 177) 546 return 45; 547 else 548 return 0; 549 } 550 551 struct rtw8852bx_bb_gain { 552 u32 gain_g[BB_PATH_NUM_8852BX]; 553 u32 gain_a[BB_PATH_NUM_8852BX]; 554 u32 gain_mask; 555 }; 556 557 static const struct rtw8852bx_bb_gain bb_gain_lna[LNA_GAIN_NUM] = { 558 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 559 .gain_mask = 0x00ff0000 }, 560 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 561 .gain_mask = 0xff000000 }, 562 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 563 .gain_mask = 0x000000ff }, 564 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 565 .gain_mask = 0x0000ff00 }, 566 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 567 .gain_mask = 0x00ff0000 }, 568 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 569 .gain_mask = 0xff000000 }, 570 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 571 .gain_mask = 0x000000ff }, 572 }; 573 574 static const struct rtw8852bx_bb_gain bb_gain_tia[TIA_GAIN_NUM] = { 575 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 576 .gain_mask = 0x00ff0000 }, 577 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 578 .gain_mask = 0xff000000 }, 579 }; 580 581 static void rtw8852bx_set_gain_error(struct rtw89_dev *rtwdev, 582 enum rtw89_subband subband, 583 enum rtw89_rf_path path) 584 { 585 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 586 u8 gain_band = rtw89_subband_to_bb_gain_band(subband); 587 s32 val; 588 u32 reg; 589 u32 mask; 590 int i; 591 592 for (i = 0; i < LNA_GAIN_NUM; i++) { 593 if (subband == RTW89_CH_2G) 594 reg = bb_gain_lna[i].gain_g[path]; 595 else 596 reg = bb_gain_lna[i].gain_a[path]; 597 598 mask = bb_gain_lna[i].gain_mask; 599 val = gain->lna_gain[gain_band][path][i]; 600 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 601 } 602 603 for (i = 0; i < TIA_GAIN_NUM; i++) { 604 if (subband == RTW89_CH_2G) 605 reg = bb_gain_tia[i].gain_g[path]; 606 else 607 reg = bb_gain_tia[i].gain_a[path]; 608 609 mask = bb_gain_tia[i].gain_mask; 610 val = gain->tia_gain[gain_band][path][i]; 611 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 612 } 613 } 614 615 static void rtw8852bt_ext_loss_avg_update(struct rtw89_dev *rtwdev, 616 s8 ext_loss_a, s8 ext_loss_b) 617 { 618 s8 ext_loss_avg; 619 u64 linear; 620 u8 pwrofst; 621 622 if (ext_loss_a == ext_loss_b) { 623 ext_loss_avg = ext_loss_a; 624 } else { 625 linear = rtw89_db_to_linear(abs(ext_loss_a - ext_loss_b)) + 1; 626 linear /= 2; 627 ext_loss_avg = rtw89_linear_to_db(linear); 628 ext_loss_avg += min(ext_loss_a, ext_loss_b); 629 } 630 631 pwrofst = max(DIV_ROUND_CLOSEST(ext_loss_avg, 4) + 16, EDCCA_PWROFST_DEFAULT); 632 633 rtw89_phy_write32_mask(rtwdev, R_PWOFST, B_PWOFST, pwrofst); 634 } 635 636 static void rtw8852bx_set_gain_offset(struct rtw89_dev *rtwdev, 637 enum rtw89_subband subband, 638 enum rtw89_phy_idx phy_idx) 639 { 640 static const u32 gain_err_addr[2] = {R_P0_AGC_RSVD, R_P1_AGC_RSVD}; 641 static const u32 rssi_ofst_addr[2] = {R_PATH0_G_TIA1_LNA6_OP1DB_V1, 642 R_PATH1_G_TIA1_LNA6_OP1DB_V1}; 643 struct rtw89_hal *hal = &rtwdev->hal; 644 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain; 645 enum rtw89_gain_offset gain_ofdm_band; 646 s8 ext_loss_a = 0, ext_loss_b = 0; 647 s32 offset_a, offset_b; 648 s32 offset_ofdm, offset_cck; 649 s32 tmp; 650 u8 path; 651 652 if (!efuse_gain->comp_valid) 653 goto next; 654 655 for (path = RF_PATH_A; path < BB_PATH_NUM_8852BX; path++) { 656 tmp = efuse_gain->comp[path][subband]; 657 tmp = clamp_t(s32, tmp << 2, S8_MIN, S8_MAX); 658 rtw89_phy_write32_mask(rtwdev, gain_err_addr[path], MASKBYTE0, tmp); 659 } 660 661 next: 662 if (!efuse_gain->offset_valid) 663 goto ext_loss; 664 665 gain_ofdm_band = rtw89_subband_to_gain_offset_band_of_ofdm(subband); 666 667 offset_a = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band]; 668 offset_b = -efuse_gain->offset[RF_PATH_B][gain_ofdm_band]; 669 670 tmp = -((offset_a << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2)); 671 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); 672 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_A], B_PATH0_R_G_OFST_MASK, tmp); 673 674 tmp = -((offset_b << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2)); 675 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); 676 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_B], B_PATH0_R_G_OFST_MASK, tmp); 677 678 if (hal->antenna_rx == RF_B) { 679 offset_ofdm = -efuse_gain->offset[RF_PATH_B][gain_ofdm_band]; 680 offset_cck = -efuse_gain->offset[RF_PATH_B][0]; 681 } else { 682 offset_ofdm = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band]; 683 offset_cck = -efuse_gain->offset[RF_PATH_A][0]; 684 } 685 686 tmp = (offset_ofdm << 4) + efuse_gain->offset_base[RTW89_PHY_0]; 687 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); 688 rtw89_phy_write32_idx(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx); 689 690 tmp = (offset_ofdm << 4) + efuse_gain->rssi_base[RTW89_PHY_0]; 691 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX); 692 rtw89_phy_write32_idx(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx); 693 694 if (subband == RTW89_CH_2G) { 695 tmp = (offset_cck << 3) + (efuse_gain->offset_base[RTW89_PHY_0] >> 1); 696 tmp = clamp_t(s32, tmp, S8_MIN >> 1, S8_MAX >> 1); 697 rtw89_phy_write32_mask(rtwdev, R_RX_RPL_OFST, 698 B_RX_RPL_OFST_CCK_MASK, tmp); 699 } 700 701 ext_loss_a = (offset_a << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2); 702 ext_loss_b = (offset_b << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2); 703 704 ext_loss: 705 if (rtwdev->chip->chip_id == RTL8852BT) 706 rtw8852bt_ext_loss_avg_update(rtwdev, ext_loss_a, ext_loss_b); 707 } 708 709 static 710 void rtw8852bx_set_rxsc_rpl_comp(struct rtw89_dev *rtwdev, enum rtw89_subband subband) 711 { 712 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 713 u8 band = rtw89_subband_to_bb_gain_band(subband); 714 u32 val; 715 716 val = u32_encode_bits((gain->rpl_ofst_20[band][RF_PATH_A] + 717 gain->rpl_ofst_20[band][RF_PATH_B]) >> 1, B_P0_RPL1_20_MASK) | 718 u32_encode_bits((gain->rpl_ofst_40[band][RF_PATH_A][0] + 719 gain->rpl_ofst_40[band][RF_PATH_B][0]) >> 1, B_P0_RPL1_40_MASK) | 720 u32_encode_bits((gain->rpl_ofst_40[band][RF_PATH_A][1] + 721 gain->rpl_ofst_40[band][RF_PATH_B][1]) >> 1, B_P0_RPL1_41_MASK); 722 val >>= B_P0_RPL1_SHIFT; 723 rtw89_phy_write32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_MASK, val); 724 rtw89_phy_write32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_MASK, val); 725 726 val = u32_encode_bits((gain->rpl_ofst_40[band][RF_PATH_A][2] + 727 gain->rpl_ofst_40[band][RF_PATH_B][2]) >> 1, B_P0_RTL2_42_MASK) | 728 u32_encode_bits((gain->rpl_ofst_80[band][RF_PATH_A][0] + 729 gain->rpl_ofst_80[band][RF_PATH_B][0]) >> 1, B_P0_RTL2_80_MASK) | 730 u32_encode_bits((gain->rpl_ofst_80[band][RF_PATH_A][1] + 731 gain->rpl_ofst_80[band][RF_PATH_B][1]) >> 1, B_P0_RTL2_81_MASK) | 732 u32_encode_bits((gain->rpl_ofst_80[band][RF_PATH_A][10] + 733 gain->rpl_ofst_80[band][RF_PATH_B][10]) >> 1, B_P0_RTL2_8A_MASK); 734 rtw89_phy_write32(rtwdev, R_P0_RPL2, val); 735 rtw89_phy_write32(rtwdev, R_P1_RPL2, val); 736 737 val = u32_encode_bits((gain->rpl_ofst_80[band][RF_PATH_A][2] + 738 gain->rpl_ofst_80[band][RF_PATH_B][2]) >> 1, B_P0_RTL3_82_MASK) | 739 u32_encode_bits((gain->rpl_ofst_80[band][RF_PATH_A][3] + 740 gain->rpl_ofst_80[band][RF_PATH_B][3]) >> 1, B_P0_RTL3_83_MASK) | 741 u32_encode_bits((gain->rpl_ofst_80[band][RF_PATH_A][4] + 742 gain->rpl_ofst_80[band][RF_PATH_B][4]) >> 1, B_P0_RTL3_84_MASK) | 743 u32_encode_bits((gain->rpl_ofst_80[band][RF_PATH_A][9] + 744 gain->rpl_ofst_80[band][RF_PATH_B][9]) >> 1, B_P0_RTL3_89_MASK); 745 rtw89_phy_write32(rtwdev, R_P0_RPL3, val); 746 rtw89_phy_write32(rtwdev, R_P1_RPL3, val); 747 } 748 749 static void rtw8852bx_ctrl_ch(struct rtw89_dev *rtwdev, 750 const struct rtw89_chan *chan, 751 enum rtw89_phy_idx phy_idx) 752 { 753 u8 central_ch = chan->channel; 754 u8 subband = chan->subband_type; 755 u8 sco_comp; 756 bool is_2g = central_ch <= 14; 757 758 /* Path A */ 759 if (is_2g) 760 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 761 B_PATH0_BAND_SEL_MSK_V1, 1, phy_idx); 762 else 763 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 764 B_PATH0_BAND_SEL_MSK_V1, 0, phy_idx); 765 766 /* Path B */ 767 if (is_2g) 768 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 769 B_PATH1_BAND_SEL_MSK_V1, 1, phy_idx); 770 else 771 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 772 B_PATH1_BAND_SEL_MSK_V1, 0, phy_idx); 773 774 /* SCO compensate FC setting */ 775 sco_comp = rtw8852bx_sco_mapping(central_ch); 776 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_INV, sco_comp, phy_idx); 777 778 if (chan->band_type == RTW89_BAND_6G) 779 return; 780 781 /* CCK parameters */ 782 if (central_ch == 14) { 783 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3b13ff); 784 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x1c42de); 785 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfdb0ad); 786 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xf60f6e); 787 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xfd8f92); 788 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011); 789 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c); 790 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xfff00a); 791 } else { 792 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3d23ff); 793 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x29b354); 794 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8); 795 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xfdb053); 796 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xf86f9a); 797 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0xfaef92); 798 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0xfe5fcc); 799 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xffdff5); 800 } 801 802 rtw8852bx_set_gain_error(rtwdev, subband, RF_PATH_A); 803 rtw8852bx_set_gain_error(rtwdev, subband, RF_PATH_B); 804 rtw8852bx_set_gain_offset(rtwdev, subband, phy_idx); 805 rtw8852bx_set_rxsc_rpl_comp(rtwdev, subband); 806 } 807 808 static void rtw8852b_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) 809 { 810 static const u32 adc_sel[2] = {0xC0EC, 0xC1EC}; 811 static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4}; 812 813 switch (bw) { 814 case RTW89_CHANNEL_WIDTH_5: 815 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); 816 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); 817 break; 818 case RTW89_CHANNEL_WIDTH_10: 819 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); 820 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); 821 break; 822 case RTW89_CHANNEL_WIDTH_20: 823 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 824 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 825 break; 826 case RTW89_CHANNEL_WIDTH_40: 827 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 828 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 829 break; 830 case RTW89_CHANNEL_WIDTH_80: 831 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 832 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 833 break; 834 default: 835 rtw89_warn(rtwdev, "Fail to set ADC\n"); 836 } 837 } 838 839 static 840 void rtw8852bt_adc_cfg(struct rtw89_dev *rtwdev, u8 bw, u8 path) 841 { 842 static const u32 rck_reset_count[2] = {0xC0E8, 0xC1E8}; 843 static const u32 adc_op5_bw_sel[2] = {0xC0D8, 0xC1D8}; 844 static const u32 adc_sample_td[2] = {0xC0D4, 0xC1D4}; 845 static const u32 adc_rst_cycle[2] = {0xC0EC, 0xC1EC}; 846 static const u32 decim_filter[2] = {0xC0EC, 0xC1EC}; 847 static const u32 rck_offset[2] = {0xC0C4, 0xC1C4}; 848 static const u32 rx_adc_clk[2] = {0x12A0, 0x32A0}; 849 static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4}; 850 static const u32 idac2_1[2] = {0xC0D4, 0xC1D4}; 851 static const u32 idac2[2] = {0xC0D4, 0xC1D4}; 852 static const u32 upd_clk_adc = {0x704}; 853 854 if (rtwdev->chip->chip_id != RTL8852BT) 855 return; 856 857 rtw89_phy_write32_mask(rtwdev, idac2[path], B_P0_CFCH_CTL, 0x8); 858 rtw89_phy_write32_mask(rtwdev, rck_reset_count[path], B_ADCMOD_LP, 0x9); 859 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], B_WDADC_SEL, 0x2); 860 rtw89_phy_write32_mask(rtwdev, rx_adc_clk[path], B_P0_RXCK_ADJ, 0x49); 861 rtw89_phy_write32_mask(rtwdev, decim_filter[path], B_DCIM_FR, 0x0); 862 863 switch (bw) { 864 case RTW89_CHANNEL_WIDTH_5: 865 case RTW89_CHANNEL_WIDTH_10: 866 case RTW89_CHANNEL_WIDTH_20: 867 case RTW89_CHANNEL_WIDTH_40: 868 rtw89_phy_write32_mask(rtwdev, idac2_1[path], B_P0_CFCH_EN, 0x2); 869 rtw89_phy_write32_mask(rtwdev, adc_sample_td[path], B_P0_CFCH_BW0, 0x3); 870 rtw89_phy_write32_mask(rtwdev, adc_op5_bw_sel[path], B_P0_CFCH_BW1, 0xf); 871 rtw89_phy_write32_mask(rtwdev, rck_offset[path], B_DRCK_MUL, 0x0); 872 /* Tx TSSI ADC update */ 873 rtw89_phy_write32_mask(rtwdev, upd_clk_adc, B_RSTB_ASYNC_BW80, 0); 874 875 if (rtwdev->efuse.rfe_type >= 51) 876 rtw89_phy_write32_mask(rtwdev, adc_rst_cycle[path], B_DCIM_RC, 0x2); 877 else 878 rtw89_phy_write32_mask(rtwdev, adc_rst_cycle[path], B_DCIM_RC, 0x3); 879 break; 880 case RTW89_CHANNEL_WIDTH_80: 881 rtw89_phy_write32_mask(rtwdev, idac2_1[path], B_P0_CFCH_EN, 0x2); 882 rtw89_phy_write32_mask(rtwdev, adc_sample_td[path], B_P0_CFCH_BW0, 0x2); 883 rtw89_phy_write32_mask(rtwdev, adc_op5_bw_sel[path], B_P0_CFCH_BW1, 0x8); 884 rtw89_phy_write32_mask(rtwdev, rck_offset[path], B_DRCK_MUL, 0x0); 885 rtw89_phy_write32_mask(rtwdev, adc_rst_cycle[path], B_DCIM_RC, 0x3); 886 /* Tx TSSI ADC update */ 887 rtw89_phy_write32_mask(rtwdev, upd_clk_adc, B_RSTB_ASYNC_BW80, 1); 888 break; 889 case RTW89_CHANNEL_WIDTH_160: 890 rtw89_phy_write32_mask(rtwdev, idac2_1[path], B_P0_CFCH_EN, 0x0); 891 rtw89_phy_write32_mask(rtwdev, adc_sample_td[path], B_P0_CFCH_BW0, 0x2); 892 rtw89_phy_write32_mask(rtwdev, adc_op5_bw_sel[path], B_P0_CFCH_BW1, 0x4); 893 rtw89_phy_write32_mask(rtwdev, rck_offset[path], B_DRCK_MUL, 0x6); 894 rtw89_phy_write32_mask(rtwdev, adc_rst_cycle[path], B_DCIM_RC, 0x3); 895 /* Tx TSSI ADC update */ 896 rtw89_phy_write32_mask(rtwdev, upd_clk_adc, B_RSTB_ASYNC_BW80, 2); 897 break; 898 default: 899 rtw89_warn(rtwdev, "Fail to set ADC\n"); 900 break; 901 } 902 } 903 904 static void rtw8852bx_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 905 enum rtw89_phy_idx phy_idx) 906 { 907 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 908 u32 rx_path_0; 909 910 rx_path_0 = rtw89_phy_read32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, phy_idx); 911 912 switch (bw) { 913 case RTW89_CHANNEL_WIDTH_5: 914 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx); 915 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x1, phy_idx); 916 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx); 917 918 /*Set RF mode at 3 */ 919 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, 920 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 921 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, 922 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 923 if (chip_id == RTL8852BT) { 924 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 925 B_PATH0_BAND_NRBW_EN_V1, 0x0, phy_idx); 926 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 927 B_PATH1_BAND_NRBW_EN_V1, 0x0, phy_idx); 928 } 929 break; 930 case RTW89_CHANNEL_WIDTH_10: 931 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx); 932 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x2, phy_idx); 933 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx); 934 935 /*Set RF mode at 3 */ 936 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, 937 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 938 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, 939 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 940 if (chip_id == RTL8852BT) { 941 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 942 B_PATH0_BAND_NRBW_EN_V1, 0x0, phy_idx); 943 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 944 B_PATH1_BAND_NRBW_EN_V1, 0x0, phy_idx); 945 } 946 break; 947 case RTW89_CHANNEL_WIDTH_20: 948 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx); 949 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx); 950 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx); 951 952 /*Set RF mode at 3 */ 953 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, 954 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 955 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, 956 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 957 if (chip_id == RTL8852BT) { 958 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 959 B_PATH0_BAND_NRBW_EN_V1, 0x1, phy_idx); 960 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 961 B_PATH1_BAND_NRBW_EN_V1, 0x1, phy_idx); 962 } 963 break; 964 case RTW89_CHANNEL_WIDTH_40: 965 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x1, phy_idx); 966 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx); 967 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 968 pri_ch, phy_idx); 969 970 /*Set RF mode at 3 */ 971 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, 972 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 973 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, 974 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 975 /*CCK primary channel */ 976 if (pri_ch == RTW89_SC_20_UPPER) 977 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1); 978 else 979 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0); 980 981 break; 982 case RTW89_CHANNEL_WIDTH_80: 983 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x2, phy_idx); 984 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx); 985 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 986 pri_ch, phy_idx); 987 988 /*Set RF mode at 3 */ 989 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, 990 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 991 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, 992 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx); 993 break; 994 default: 995 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 996 pri_ch); 997 } 998 999 if (chip_id == RTL8852B) { 1000 rtw8852b_bw_setting(rtwdev, bw, RF_PATH_A); 1001 rtw8852b_bw_setting(rtwdev, bw, RF_PATH_B); 1002 } else if (chip_id == RTL8852BT) { 1003 rtw8852bt_adc_cfg(rtwdev, bw, RF_PATH_A); 1004 rtw8852bt_adc_cfg(rtwdev, bw, RF_PATH_B); 1005 } 1006 1007 if (rx_path_0 == 0x1) 1008 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX, 1009 B_P1_RFMODE_ORI_RX_ALL, 0x111, phy_idx); 1010 else if (rx_path_0 == 0x2) 1011 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX, 1012 B_P0_RFMODE_ORI_RX_ALL, 0x111, phy_idx); 1013 } 1014 1015 static void rtw8852bx_ctrl_cck_en(struct rtw89_dev *rtwdev, bool cck_en) 1016 { 1017 if (cck_en) { 1018 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1); 1019 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0); 1020 } else { 1021 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0); 1022 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1); 1023 } 1024 } 1025 1026 static void rtw8852bx_5m_mask(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, 1027 enum rtw89_phy_idx phy_idx) 1028 { 1029 u8 pri_ch = chan->pri_ch_idx; 1030 bool mask_5m_low; 1031 bool mask_5m_en; 1032 1033 switch (chan->band_width) { 1034 case RTW89_CHANNEL_WIDTH_40: 1035 /* Prich=1: Mask 5M High, Prich=2: Mask 5M Low */ 1036 mask_5m_en = true; 1037 mask_5m_low = pri_ch == RTW89_SC_20_LOWER; 1038 break; 1039 case RTW89_CHANNEL_WIDTH_80: 1040 /* Prich=3: Mask 5M High, Prich=4: Mask 5M Low, Else: Disable */ 1041 mask_5m_en = pri_ch == RTW89_SC_20_UPMOST || 1042 pri_ch == RTW89_SC_20_LOWEST; 1043 mask_5m_low = pri_ch == RTW89_SC_20_LOWEST; 1044 break; 1045 default: 1046 mask_5m_en = false; 1047 break; 1048 } 1049 1050 if (!mask_5m_en) { 1051 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x0); 1052 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x0); 1053 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1, 1054 B_ASSIGN_SBD_OPT_EN_V1, 0x0, phy_idx); 1055 return; 1056 } 1057 1058 if (mask_5m_low) { 1059 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x4); 1060 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1); 1061 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x0); 1062 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x1); 1063 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_TH, 0x4); 1064 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x1); 1065 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB2, 0x0); 1066 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB0, 0x1); 1067 } else { 1068 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x4); 1069 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1); 1070 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x1); 1071 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x0); 1072 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_TH, 0x4); 1073 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x1); 1074 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB2, 0x1); 1075 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB0, 0x0); 1076 } 1077 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1, 1078 B_ASSIGN_SBD_OPT_EN_V1, 0x1, phy_idx); 1079 } 1080 1081 static void __rtw8852bx_bb_reset_all(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 1082 { 1083 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1084 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1085 fsleep(1); 1086 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx); 1087 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx); 1088 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1089 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1090 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx); 1091 } 1092 1093 static void rtw8852bx_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1094 enum rtw89_phy_idx phy_idx) 1095 { 1096 u32 addr; 1097 1098 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1099 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1100 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1101 } 1102 1103 static void __rtw8852bx_bb_sethw(struct rtw89_dev *rtwdev) 1104 { 1105 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 1106 1107 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP); 1108 rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP); 1109 1110 rtw8852bx_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1111 1112 /* read these registers after loading BB parameters */ 1113 gain->offset_base[RTW89_PHY_0] = 1114 rtw89_phy_read32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK); 1115 gain->rssi_base[RTW89_PHY_0] = 1116 rtw89_phy_read32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK); 1117 } 1118 1119 static void rtw8852bx_bb_set_pop(struct rtw89_dev *rtwdev) 1120 { 1121 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) 1122 rtw89_phy_write32_clr(rtwdev, R_PKT_CTRL, B_PKT_POP_EN); 1123 } 1124 1125 static u32 rtw8852bt_spur_freq(struct rtw89_dev *rtwdev, 1126 const struct rtw89_chan *chan) 1127 { 1128 u8 center_chan = chan->channel; 1129 1130 switch (chan->band_type) { 1131 case RTW89_BAND_5G: 1132 if (center_chan == 151 || center_chan == 153 || 1133 center_chan == 155 || center_chan == 163) 1134 return 5760; 1135 break; 1136 default: 1137 break; 1138 } 1139 1140 return 0; 1141 } 1142 1143 #define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */ 1144 #define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */ 1145 #define MAX_TONE_NUM 2048 1146 1147 static void rtw8852bt_set_csi_tone_idx(struct rtw89_dev *rtwdev, 1148 const struct rtw89_chan *chan, 1149 enum rtw89_phy_idx phy_idx) 1150 { 1151 s32 freq_diff, csi_idx, csi_tone_idx; 1152 u32 spur_freq; 1153 1154 spur_freq = rtw8852bt_spur_freq(rtwdev, chan); 1155 if (spur_freq == 0) { 1156 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN, 1157 0, phy_idx); 1158 return; 1159 } 1160 1161 freq_diff = (spur_freq - chan->freq) * 1000000; 1162 csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125); 1163 s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx); 1164 1165 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_V1, B_SEG0CSI_IDX, 1166 csi_tone_idx, phy_idx); 1167 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN, 1, phy_idx); 1168 } 1169 1170 static 1171 void __rtw8852bx_set_channel_bb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, 1172 enum rtw89_phy_idx phy_idx) 1173 { 1174 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1175 bool cck_en = chan->channel <= 14; 1176 u8 pri_ch_idx = chan->pri_ch_idx; 1177 u8 band = chan->band_type, chan_idx; 1178 1179 if (cck_en) 1180 rtw8852bx_ctrl_sco_cck(rtwdev, chan->primary_channel); 1181 1182 rtw8852bx_ctrl_ch(rtwdev, chan, phy_idx); 1183 rtw8852bx_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx); 1184 rtw8852bx_ctrl_cck_en(rtwdev, cck_en); 1185 if (chip_id == RTL8852BT) 1186 rtw8852bt_set_csi_tone_idx(rtwdev, chan, phy_idx); 1187 if (chip_id == RTL8852B && chan->band_type == RTW89_BAND_5G) { 1188 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 1189 B_PATH0_BT_SHARE_V1, 0x0); 1190 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 1191 B_PATH0_BTG_PATH_V1, 0x0); 1192 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 1193 B_PATH1_BT_SHARE_V1, 0x0); 1194 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 1195 B_PATH1_BTG_PATH_V1, 0x0); 1196 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0); 1197 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0); 1198 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1, 1199 B_BT_DYN_DC_EST_EN_MSK, 0x0); 1200 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0); 1201 } 1202 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band); 1203 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx); 1204 rtw8852bx_5m_mask(rtwdev, chan, phy_idx); 1205 rtw8852bx_bb_set_pop(rtwdev); 1206 __rtw8852bx_bb_reset_all(rtwdev, phy_idx); 1207 } 1208 1209 static u32 rtw8852bx_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, 1210 enum rtw89_phy_idx phy_idx, 1211 s16 ref, u16 pwr_ofst_decrease) 1212 { 1213 const u16 tssi_16dbm_cw = 0x12c; 1214 const u8 base_cw_0db = 0x27; 1215 s16 pwr_s10_3; 1216 s16 rf_pwr_cw; 1217 u16 bb_pwr_cw; 1218 u32 pwr_cw; 1219 u32 tssi_ofst_cw; 1220 1221 pwr_s10_3 = (ref << 1) + (s16)(base_cw_0db << 3) - pwr_ofst_decrease; 1222 bb_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(2, 0)); 1223 rf_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(8, 3)); 1224 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); 1225 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; 1226 1227 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)) - 1228 pwr_ofst_decrease; 1229 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1230 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", 1231 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); 1232 1233 return u32_encode_bits(tssi_ofst_cw, B_DPD_TSSI_CW) | 1234 u32_encode_bits(pwr_cw, B_DPD_PWR_CW) | 1235 u32_encode_bits(ref, B_DPD_REF); 1236 } 1237 1238 /* @pwr_ofst (unit: 1/8 dBm): power of path A minus power of path B */ 1239 static void rtw8852bx_set_txpwr_ref(struct rtw89_dev *rtwdev, 1240 enum rtw89_phy_idx phy_idx, s16 pwr_ofst) 1241 { 1242 static const u32 addr[RF_PATH_NUM_8852BX] = {0x5800, 0x7800}; 1243 const u32 mask = B_DPD_TSSI_CW | B_DPD_PWR_CW | B_DPD_REF; 1244 u16 ofst_dec[RF_PATH_NUM_8852BX]; 1245 const u8 ofst_ofdm = 0x4; 1246 const u8 ofst_cck = 0x8; 1247 const s16 ref_ofdm = 0; 1248 const s16 ref_cck = 0; 1249 u32 val; 1250 u8 i; 1251 1252 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); 1253 1254 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, 1255 B_AX_PWR_REF, 0x0); 1256 1257 ofst_dec[RF_PATH_A] = pwr_ofst > 0 ? 0 : abs(pwr_ofst); 1258 ofst_dec[RF_PATH_B] = pwr_ofst > 0 ? pwr_ofst : 0; 1259 1260 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); 1261 for (i = 0; i < RF_PATH_NUM_8852BX; i++) { 1262 val = rtw8852bx_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm, ofst_dec[i]); 1263 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, phy_idx); 1264 } 1265 1266 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); 1267 for (i = 0; i < RF_PATH_NUM_8852BX; i++) { 1268 val = rtw8852bx_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck, ofst_dec[i]); 1269 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, phy_idx); 1270 } 1271 } 1272 1273 static void rtw8852bx_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev, 1274 const struct rtw89_chan *chan, 1275 u8 tx_shape_idx, 1276 enum rtw89_phy_idx phy_idx) 1277 { 1278 #define __DFIR_CFG_ADDR(i) (R_TXFIR0 + ((i) << 2)) 1279 #define __DFIR_CFG_MASK 0xffffffff 1280 #define __DFIR_CFG_NR 8 1281 #define __DECL_DFIR_PARAM(_name, _val...) \ 1282 static const u32 param_ ## _name[] = {_val}; \ 1283 static_assert(ARRAY_SIZE(param_ ## _name) == __DFIR_CFG_NR) 1284 1285 __DECL_DFIR_PARAM(flat, 1286 0x023D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053, 1287 0x00F86F9A, 0x06FAEF92, 0x00FE5FCC, 0x00FFDFF5); 1288 __DECL_DFIR_PARAM(sharp, 1289 0x023D83FF, 0x002C636A, 0x0013F204, 0x00008090, 1290 0x00F87FB0, 0x06F99F83, 0x00FDBFBA, 0x00003FF5); 1291 __DECL_DFIR_PARAM(sharp_14, 1292 0x023B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E, 1293 0x00FD8F92, 0x0602D011, 0x0001C02C, 0x00FFF00A); 1294 u8 ch = chan->channel; 1295 const u32 *param; 1296 u32 addr; 1297 int i; 1298 1299 if (ch > 14) { 1300 rtw89_warn(rtwdev, 1301 "set tx shape dfir by unknown ch: %d on 2G\n", ch); 1302 return; 1303 } 1304 1305 if (ch == 14) 1306 param = param_sharp_14; 1307 else 1308 param = tx_shape_idx == 0 ? param_flat : param_sharp; 1309 1310 for (i = 0; i < __DFIR_CFG_NR; i++) { 1311 addr = __DFIR_CFG_ADDR(i); 1312 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1313 "set tx shape dfir: 0x%x: 0x%x\n", addr, param[i]); 1314 rtw89_phy_write32_idx(rtwdev, addr, __DFIR_CFG_MASK, param[i], 1315 phy_idx); 1316 } 1317 1318 #undef __DECL_DFIR_PARAM 1319 #undef __DFIR_CFG_NR 1320 #undef __DFIR_CFG_MASK 1321 #undef __DECL_CFG_ADDR 1322 } 1323 1324 static void rtw8852bx_set_tx_shape(struct rtw89_dev *rtwdev, 1325 const struct rtw89_chan *chan, 1326 enum rtw89_phy_idx phy_idx) 1327 { 1328 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 1329 u8 band = chan->band_type; 1330 u8 regd = rtw89_regd_get(rtwdev, band); 1331 u8 tx_shape_cck = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_CCK][regd]; 1332 u8 tx_shape_ofdm = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_OFDM][regd]; 1333 1334 if (band == RTW89_BAND_2G) 1335 rtw8852bx_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx); 1336 1337 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG, 1338 tx_shape_ofdm); 1339 } 1340 1341 static s16 rtw8852bx_get_txpwr_sar_diff(struct rtw89_dev *rtwdev, 1342 const struct rtw89_chan *chan) 1343 { 1344 struct rtw89_sar_parm sar_parm = { 1345 .center_freq = chan->freq, 1346 .force_path = true, 1347 }; 1348 s16 sar_bb_a, sar_bb_b; 1349 s8 sar_mac; 1350 1351 sar_parm.path = RF_PATH_A; 1352 sar_mac = rtw89_query_sar(rtwdev, &sar_parm); 1353 sar_bb_a = rtw89_phy_txpwr_mac_to_bb(rtwdev, sar_mac); 1354 1355 sar_parm.path = RF_PATH_B; 1356 sar_mac = rtw89_query_sar(rtwdev, &sar_parm); 1357 sar_bb_b = rtw89_phy_txpwr_mac_to_bb(rtwdev, sar_mac); 1358 1359 return sar_bb_a - sar_bb_b; 1360 } 1361 1362 static void rtw8852bx_set_txpwr_diff(struct rtw89_dev *rtwdev, 1363 const struct rtw89_chan *chan, 1364 enum rtw89_phy_idx phy_idx) 1365 { 1366 s16 pwr_ofst; 1367 1368 pwr_ofst = rtw89_phy_ant_gain_pwr_offset(rtwdev, chan); 1369 pwr_ofst += rtw8852bx_get_txpwr_sar_diff(rtwdev, chan); 1370 rtw8852bx_set_txpwr_ref(rtwdev, phy_idx, pwr_ofst); 1371 } 1372 1373 static void __rtw8852bx_set_txpwr(struct rtw89_dev *rtwdev, 1374 const struct rtw89_chan *chan, 1375 enum rtw89_phy_idx phy_idx) 1376 { 1377 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx); 1378 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx); 1379 rtw8852bx_set_tx_shape(rtwdev, chan, phy_idx); 1380 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx); 1381 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx); 1382 rtw8852bx_set_txpwr_diff(rtwdev, chan, phy_idx); 1383 } 1384 1385 static void __rtw8852bx_set_txpwr_ctrl(struct rtw89_dev *rtwdev, 1386 enum rtw89_phy_idx phy_idx) 1387 { 1388 rtw8852bx_set_txpwr_ref(rtwdev, phy_idx, 0); 1389 } 1390 1391 static 1392 void __rtw8852bx_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1393 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 1394 { 1395 u32 reg; 1396 1397 if (pw_ofst < -16 || pw_ofst > 15) { 1398 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst); 1399 return; 1400 } 1401 1402 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx); 1403 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN); 1404 1405 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx); 1406 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst); 1407 1408 pw_ofst = max_t(s8, pw_ofst - 3, -16); 1409 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx); 1410 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, pw_ofst); 1411 } 1412 1413 static int 1414 __rtw8852bx_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 1415 { 1416 int ret; 1417 1418 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); 1419 if (ret) 1420 return ret; 1421 1422 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000); 1423 if (ret) 1424 return ret; 1425 1426 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); 1427 if (ret) 1428 return ret; 1429 1430 rtw8852bx_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ? 1431 RTW89_MAC_1 : RTW89_MAC_0); 1432 1433 return 0; 1434 } 1435 1436 static 1437 void __rtw8852bx_bb_set_plcp_tx(struct rtw89_dev *rtwdev) 1438 { 1439 const struct rtw89_reg3_def *def = rtw8852bx_pmac_ht20_mcs7_tbl; 1440 u8 i; 1441 1442 for (i = 0; i < ARRAY_SIZE(rtw8852bx_pmac_ht20_mcs7_tbl); i++, def++) 1443 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data); 1444 } 1445 1446 static void rtw8852bx_stop_pmac_tx(struct rtw89_dev *rtwdev, 1447 struct rtw8852bx_bb_pmac_info *tx_info, 1448 enum rtw89_phy_idx idx) 1449 { 1450 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx"); 1451 if (tx_info->mode == CONT_TX) 1452 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0, idx); 1453 else if (tx_info->mode == PKTS_TX) 1454 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0, idx); 1455 } 1456 1457 static void rtw8852bx_start_pmac_tx(struct rtw89_dev *rtwdev, 1458 struct rtw8852bx_bb_pmac_info *tx_info, 1459 enum rtw89_phy_idx idx) 1460 { 1461 enum rtw8852bx_pmac_mode mode = tx_info->mode; 1462 u32 pkt_cnt = tx_info->tx_cnt; 1463 u16 period = tx_info->period; 1464 1465 if (mode == CONT_TX && !tx_info->is_cck) { 1466 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1, idx); 1467 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start"); 1468 } else if (mode == PKTS_TX) { 1469 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1, idx); 1470 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, 1471 B_PMAC_TX_PRD_MSK, period, idx); 1472 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK, 1473 pkt_cnt, idx); 1474 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start"); 1475 } 1476 1477 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx); 1478 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx); 1479 } 1480 1481 static 1482 void rtw8852bx_bb_set_pmac_tx(struct rtw89_dev *rtwdev, 1483 struct rtw8852bx_bb_pmac_info *tx_info, 1484 enum rtw89_phy_idx idx, const struct rtw89_chan *chan) 1485 { 1486 if (!tx_info->en_pmac_tx) { 1487 rtw8852bx_stop_pmac_tx(rtwdev, tx_info, idx); 1488 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx); 1489 if (chan->band_type == RTW89_BAND_2G) 1490 rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS); 1491 return; 1492 } 1493 1494 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable"); 1495 1496 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx); 1497 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx); 1498 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f, idx); 1499 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx); 1500 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx); 1501 rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS); 1502 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx); 1503 1504 rtw8852bx_start_pmac_tx(rtwdev, tx_info, idx); 1505 } 1506 1507 static 1508 void __rtw8852bx_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable, 1509 u16 tx_cnt, u16 period, u16 tx_time, 1510 enum rtw89_phy_idx idx, const struct rtw89_chan *chan) 1511 { 1512 struct rtw8852bx_bb_pmac_info tx_info = {0}; 1513 1514 tx_info.en_pmac_tx = enable; 1515 tx_info.is_cck = 0; 1516 tx_info.mode = PKTS_TX; 1517 tx_info.tx_cnt = tx_cnt; 1518 tx_info.period = period; 1519 tx_info.tx_time = tx_time; 1520 1521 rtw8852bx_bb_set_pmac_tx(rtwdev, &tx_info, idx, chan); 1522 } 1523 1524 static 1525 void __rtw8852bx_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm, 1526 enum rtw89_phy_idx idx) 1527 { 1528 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm); 1529 1530 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx); 1531 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx); 1532 } 1533 1534 static 1535 void __rtw8852bx_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path) 1536 { 1537 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0); 1538 1539 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path); 1540 1541 if (tx_path == RF_PATH_A) { 1542 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 1); 1543 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0); 1544 } else if (tx_path == RF_PATH_B) { 1545 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2); 1546 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0); 1547 } else if (tx_path == RF_PATH_AB) { 1548 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 3); 1549 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4); 1550 } else { 1551 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path"); 1552 } 1553 } 1554 1555 static 1556 void __rtw8852bx_bb_tx_mode_switch(struct rtw89_dev *rtwdev, 1557 enum rtw89_phy_idx idx, u8 mode) 1558 { 1559 if (mode != 0) 1560 return; 1561 1562 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch"); 1563 1564 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx); 1565 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx); 1566 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx); 1567 rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx); 1568 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx); 1569 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx); 1570 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx); 1571 } 1572 1573 static 1574 void __rtw8852bx_bb_backup_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx, 1575 struct rtw8852bx_bb_tssi_bak *bak) 1576 { 1577 s32 tmp; 1578 1579 bak->tx_path = rtw89_phy_read32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, idx); 1580 bak->rx_path = rtw89_phy_read32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, idx); 1581 bak->p0_rfmode = rtw89_phy_read32_idx(rtwdev, R_P0_RFMODE, MASKDWORD, idx); 1582 bak->p0_rfmode_ftm = rtw89_phy_read32_idx(rtwdev, R_P0_RFMODE_FTM_RX, MASKDWORD, idx); 1583 bak->p1_rfmode = rtw89_phy_read32_idx(rtwdev, R_P1_RFMODE, MASKDWORD, idx); 1584 bak->p1_rfmode_ftm = rtw89_phy_read32_idx(rtwdev, R_P1_RFMODE_FTM_RX, MASKDWORD, idx); 1585 tmp = rtw89_phy_read32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, idx); 1586 bak->tx_pwr = sign_extend32(tmp, 8); 1587 } 1588 1589 static 1590 void __rtw8852bx_bb_restore_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx, 1591 const struct rtw8852bx_bb_tssi_bak *bak) 1592 { 1593 rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, bak->tx_path, idx); 1594 if (bak->tx_path == RF_AB) 1595 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0x4); 1596 else 1597 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0x0); 1598 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, bak->rx_path, idx); 1599 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx); 1600 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE, MASKDWORD, bak->p0_rfmode, idx); 1601 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_FTM_RX, MASKDWORD, bak->p0_rfmode_ftm, idx); 1602 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE, MASKDWORD, bak->p1_rfmode, idx); 1603 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_FTM_RX, MASKDWORD, bak->p1_rfmode_ftm, idx); 1604 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, bak->tx_pwr, idx); 1605 } 1606 1607 static void __rtw8852bx_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 1608 enum rtw89_phy_idx phy_idx) 1609 { 1610 rtw89_phy_write_reg3_tbl(rtwdev, en ? &rtw8852bx_btc_preagc_en_defs_tbl : 1611 &rtw8852bx_btc_preagc_dis_defs_tbl); 1612 } 1613 1614 static void __rtw8852bx_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 1615 enum rtw89_phy_idx phy_idx) 1616 { 1617 if (en) { 1618 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 1619 B_PATH0_BT_SHARE_V1, 0x1); 1620 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 1621 B_PATH0_BTG_PATH_V1, 0x0); 1622 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 1623 B_PATH1_G_LNA6_OP1DB_V1, 0x20); 1624 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 1625 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x30); 1626 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 1627 B_PATH1_BT_SHARE_V1, 0x1); 1628 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 1629 B_PATH1_BTG_PATH_V1, 0x1); 1630 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 1631 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x1); 1632 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x2); 1633 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1, 1634 B_BT_DYN_DC_EST_EN_MSK, 0x1); 1635 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x1); 1636 } else { 1637 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 1638 B_PATH0_BT_SHARE_V1, 0x0); 1639 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 1640 B_PATH0_BTG_PATH_V1, 0x0); 1641 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 1642 B_PATH1_G_LNA6_OP1DB_V1, 0x1a); 1643 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 1644 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a); 1645 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 1646 B_PATH1_BT_SHARE_V1, 0x0); 1647 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 1648 B_PATH1_BTG_PATH_V1, 0x0); 1649 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xc); 1650 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0); 1651 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0); 1652 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1, 1653 B_BT_DYN_DC_EST_EN_MSK, 0x1); 1654 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0); 1655 } 1656 } 1657 1658 static 1659 void __rtw8852bx_bb_ctrl_rx_path(struct rtw89_dev *rtwdev, 1660 enum rtw89_rf_path_bit rx_path, 1661 const struct rtw89_chan *chan) 1662 { 1663 u32 rst_mask0; 1664 u32 rst_mask1; 1665 1666 if (rx_path == RF_A) { 1667 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 1); 1668 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 1); 1669 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 1); 1670 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); 1671 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); 1672 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4); 1673 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 1674 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 1675 } else if (rx_path == RF_B) { 1676 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 2); 1677 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 2); 1678 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 2); 1679 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); 1680 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); 1681 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4); 1682 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 1683 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 1684 } else if (rx_path == RF_AB) { 1685 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 3); 1686 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 3); 1687 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 3); 1688 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1); 1689 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1); 1690 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4); 1691 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1); 1692 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1); 1693 } 1694 1695 rtw8852bx_set_gain_offset(rtwdev, chan->subband_type, RTW89_PHY_0); 1696 1697 if (chan->band_type == RTW89_BAND_2G && 1698 (rx_path == RF_B || rx_path == RF_AB)) 1699 rtw8852bx_ctrl_btg_bt_rx(rtwdev, true, RTW89_PHY_0); 1700 else 1701 rtw8852bx_ctrl_btg_bt_rx(rtwdev, false, RTW89_PHY_0); 1702 1703 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 1704 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; 1705 if (rx_path == RF_A) { 1706 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 1707 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 1708 } else { 1709 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); 1710 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); 1711 } 1712 } 1713 1714 static void rtw8852bx_bb_ctrl_rf_mode_rx_path(struct rtw89_dev *rtwdev, 1715 enum rtw89_rf_path_bit rx_path) 1716 { 1717 if (rx_path == RF_A) { 1718 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, 1719 B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1233312); 1720 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX, 1721 B_P0_RFMODE_FTM_RX, 0x333); 1722 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, 1723 B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1111111); 1724 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX, 1725 B_P1_RFMODE_FTM_RX, 0x111); 1726 } else if (rx_path == RF_B) { 1727 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, 1728 B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1111111); 1729 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX, 1730 B_P0_RFMODE_FTM_RX, 0x111); 1731 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, 1732 B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1233312); 1733 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX, 1734 B_P1_RFMODE_FTM_RX, 0x333); 1735 } else if (rx_path == RF_AB) { 1736 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, 1737 B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1233312); 1738 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX, 1739 B_P0_RFMODE_FTM_RX, 0x333); 1740 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, 1741 B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1233312); 1742 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX, 1743 B_P1_RFMODE_FTM_RX, 0x333); 1744 } 1745 } 1746 1747 static void __rtw8852bx_bb_cfg_txrx_path(struct rtw89_dev *rtwdev) 1748 { 1749 struct rtw89_hal *hal = &rtwdev->hal; 1750 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 1751 enum rtw89_rf_path_bit rx_path = hal->antenna_rx ? hal->antenna_rx : RF_AB; 1752 1753 rtw8852bx_bb_ctrl_rx_path(rtwdev, rx_path, chan); 1754 rtw8852bx_bb_ctrl_rf_mode_rx_path(rtwdev, rx_path); 1755 1756 if (rtwdev->hal.rx_nss == 1) { 1757 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); 1758 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); 1759 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 1760 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 1761 } else { 1762 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1); 1763 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1); 1764 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1); 1765 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1); 1766 } 1767 1768 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0); 1769 } 1770 1771 static u8 __rtw8852bx_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 1772 { 1773 if (rtwdev->is_tssi_mode[rf_path]) { 1774 u32 addr = 0x1c10 + (rf_path << 13); 1775 1776 return rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000); 1777 } 1778 1779 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1780 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); 1781 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1782 1783 fsleep(200); 1784 1785 return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); 1786 } 1787 1788 static 1789 void rtw8852bx_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 1790 { 1791 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000); 1792 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group); 1793 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val); 1794 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0); 1795 } 1796 1797 static void __rtw8852bx_btc_init_cfg(struct rtw89_dev *rtwdev) 1798 { 1799 struct rtw89_btc *btc = &rtwdev->btc; 1800 const struct rtw89_chip_info *chip = rtwdev->chip; 1801 const struct rtw89_mac_ax_coex coex_params = { 1802 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 1803 .direction = RTW89_MAC_AX_COEX_INNER, 1804 }; 1805 1806 /* PTA init */ 1807 rtw89_mac_coex_init(rtwdev, &coex_params); 1808 1809 /* set WL Tx response = Hi-Pri */ 1810 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 1811 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 1812 1813 /* set rf gnt debug off */ 1814 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, RFREG_MASK, 0x0); 1815 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0); 1816 1817 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ 1818 if (btc->ant_type == BTC_ANT_SHARED) { 1819 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); 1820 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); 1821 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */ 1822 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); 1823 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_TX_GROUP, 0x55f); 1824 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ 1825 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); 1826 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); 1827 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); 1828 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_TX_GROUP, 0x5ff); 1829 } 1830 1831 if (rtwdev->chip->chip_id == RTL8852BT) { 1832 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_RX_GROUP, 0x5df); 1833 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_RX_GROUP, 0x5df); 1834 } 1835 1836 /* set PTA break table */ 1837 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM); 1838 1839 /* enable BT counter 0xda40[16,2] = 2b'11 */ 1840 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN); 1841 btc->cx.wl.status.map.init_ok = true; 1842 } 1843 1844 static 1845 void __rtw8852bx_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 1846 { 1847 u32 bitmap; 1848 u32 reg; 1849 1850 switch (map) { 1851 case BTC_PRI_MASK_TX_RESP: 1852 reg = R_BTC_BT_COEX_MSK_TABLE; 1853 bitmap = B_BTC_PRI_MASK_TX_RESP_V1; 1854 break; 1855 case BTC_PRI_MASK_BEACON: 1856 reg = R_AX_WL_PRI_MSK; 1857 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ; 1858 break; 1859 case BTC_PRI_MASK_RX_CCK: 1860 reg = R_BTC_BT_COEX_MSK_TABLE; 1861 bitmap = B_BTC_PRI_MASK_RXCCK_V1; 1862 break; 1863 default: 1864 return; 1865 } 1866 1867 if (state) 1868 rtw89_write32_set(rtwdev, reg, bitmap); 1869 else 1870 rtw89_write32_clr(rtwdev, reg, bitmap); 1871 } 1872 1873 static 1874 s8 __rtw8852bx_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 1875 { 1876 /* +6 for compensate offset */ 1877 return clamp_t(s8, val + 6, -100, 0) + 100; 1878 } 1879 1880 static 1881 void __rtw8852bx_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 1882 { 1883 /* Feature move to firmware */ 1884 } 1885 1886 static void __rtw8852bx_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 1887 { 1888 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); 1889 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 1890 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x31); 1891 1892 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ 1893 if (state) 1894 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x179); 1895 else 1896 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x20); 1897 1898 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 1899 } 1900 1901 static void rtw8852bx_btc_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level) 1902 { 1903 switch (level) { 1904 case 0: /* default */ 1905 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 1906 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); 1907 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 1908 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 1909 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 1910 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 1911 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 1912 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 1913 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 1914 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 1915 break; 1916 case 1: /* Fix LNA2=5 */ 1917 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 1918 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); 1919 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 1920 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 1921 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 1922 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 1923 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 1924 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 1925 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 1926 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 1927 break; 1928 } 1929 } 1930 1931 static void __rtw8852bx_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) 1932 { 1933 struct rtw89_btc *btc = &rtwdev->btc; 1934 1935 switch (level) { 1936 case 0: /* original */ 1937 default: 1938 rtw8852bx_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0); 1939 btc->dm.wl_lna2 = 0; 1940 break; 1941 case 1: /* for FDD free-run */ 1942 rtw8852bx_ctrl_nbtg_bt_tx(rtwdev, true, RTW89_PHY_0); 1943 btc->dm.wl_lna2 = 0; 1944 break; 1945 case 2: /* for BTG Co-Rx*/ 1946 rtw8852bx_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0); 1947 btc->dm.wl_lna2 = 1; 1948 break; 1949 } 1950 1951 rtw8852bx_btc_set_wl_lna2(rtwdev, btc->dm.wl_lna2); 1952 } 1953 1954 static void rtw8852bx_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, 1955 struct rtw89_rx_phy_ppdu *phy_ppdu, 1956 struct ieee80211_rx_status *status) 1957 { 1958 u16 chan = phy_ppdu->chan_idx; 1959 enum nl80211_band band; 1960 u8 ch; 1961 1962 if (chan == 0) 1963 return; 1964 1965 rtw89_decode_chan_idx(rtwdev, chan, &ch, &band); 1966 status->freq = ieee80211_channel_to_frequency(ch, band); 1967 status->band = band; 1968 } 1969 1970 static void __rtw8852bx_query_ppdu(struct rtw89_dev *rtwdev, 1971 struct rtw89_rx_phy_ppdu *phy_ppdu, 1972 struct ieee80211_rx_status *status) 1973 { 1974 u8 path; 1975 u8 *rx_power = phy_ppdu->rssi; 1976 1977 if (!status->signal) 1978 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], 1979 rx_power[RF_PATH_B])); 1980 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 1981 status->chains |= BIT(path); 1982 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]); 1983 } 1984 if (phy_ppdu->valid) 1985 rtw8852bx_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); 1986 } 1987 1988 static void __rtw8852bx_convert_rpl_to_rssi(struct rtw89_dev *rtwdev, 1989 struct rtw89_rx_phy_ppdu *phy_ppdu) 1990 { 1991 u8 delta = phy_ppdu->rpl_avg - phy_ppdu->rssi_avg; 1992 u8 *rssi = phy_ppdu->rssi; 1993 u8 i; 1994 1995 for (i = 0; i < RF_PATH_NUM_8852BX; i++) 1996 rssi[i] += delta; 1997 1998 phy_ppdu->rssi_avg = phy_ppdu->rpl_avg; 1999 } 2000 2001 static int __rtw8852bx_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 2002 { 2003 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2004 u32 val32; 2005 int ret; 2006 2007 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 2008 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2009 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x1); 2010 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2011 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2012 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2013 2014 if (chip_id == RTL8852BT) { 2015 val32 = rtw89_read32(rtwdev, R_AX_AFE_OFF_CTRL1); 2016 val32 = u32_replace_bits(val32, 0x1, B_AX_S0_LDO_VSEL_F_MASK); 2017 val32 = u32_replace_bits(val32, 0x1, B_AX_S1_LDO_VSEL_F_MASK); 2018 rtw89_write32(rtwdev, R_AX_AFE_OFF_CTRL1, val32); 2019 } 2020 2021 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xC7, 2022 FULL_BIT_MASK); 2023 if (ret) 2024 return ret; 2025 2026 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xC7, 2027 FULL_BIT_MASK); 2028 if (ret) 2029 return ret; 2030 2031 rtw89_write8(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_XYN_CYCLE); 2032 2033 return 0; 2034 } 2035 2036 static int __rtw8852bx_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 2037 { 2038 u8 wl_rfc_s0; 2039 u8 wl_rfc_s1; 2040 int ret; 2041 2042 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2043 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 2044 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2045 2046 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, &wl_rfc_s0); 2047 if (ret) 2048 return ret; 2049 wl_rfc_s0 &= ~XTAL_SI_RF00S_EN; 2050 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, wl_rfc_s0, 2051 FULL_BIT_MASK); 2052 if (ret) 2053 return ret; 2054 2055 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, &wl_rfc_s1); 2056 if (ret) 2057 return ret; 2058 wl_rfc_s1 &= ~XTAL_SI_RF10S_EN; 2059 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, wl_rfc_s1, 2060 FULL_BIT_MASK); 2061 return ret; 2062 } 2063 2064 const struct rtw8852bx_info rtw8852bx_info = { 2065 .mac_enable_bb_rf = __rtw8852bx_mac_enable_bb_rf, 2066 .mac_disable_bb_rf = __rtw8852bx_mac_disable_bb_rf, 2067 .bb_sethw = __rtw8852bx_bb_sethw, 2068 .bb_reset_all = __rtw8852bx_bb_reset_all, 2069 .bb_cfg_txrx_path = __rtw8852bx_bb_cfg_txrx_path, 2070 .bb_cfg_tx_path = __rtw8852bx_bb_cfg_tx_path, 2071 .bb_ctrl_rx_path = __rtw8852bx_bb_ctrl_rx_path, 2072 .bb_set_plcp_tx = __rtw8852bx_bb_set_plcp_tx, 2073 .bb_set_power = __rtw8852bx_bb_set_power, 2074 .bb_set_pmac_pkt_tx = __rtw8852bx_bb_set_pmac_pkt_tx, 2075 .bb_backup_tssi = __rtw8852bx_bb_backup_tssi, 2076 .bb_restore_tssi = __rtw8852bx_bb_restore_tssi, 2077 .bb_tx_mode_switch = __rtw8852bx_bb_tx_mode_switch, 2078 .set_channel_mac = __rtw8852bx_set_channel_mac, 2079 .set_channel_bb = __rtw8852bx_set_channel_bb, 2080 .ctrl_nbtg_bt_tx = __rtw8852bx_ctrl_nbtg_bt_tx, 2081 .ctrl_btg_bt_rx = __rtw8852bx_ctrl_btg_bt_rx, 2082 .query_ppdu = __rtw8852bx_query_ppdu, 2083 .convert_rpl_to_rssi = __rtw8852bx_convert_rpl_to_rssi, 2084 .read_efuse = __rtw8852bx_read_efuse, 2085 .read_phycap = __rtw8852bx_read_phycap, 2086 .power_trim = __rtw8852bx_power_trim, 2087 .set_txpwr = __rtw8852bx_set_txpwr, 2088 .set_txpwr_ctrl = __rtw8852bx_set_txpwr_ctrl, 2089 .init_txpwr_unit = __rtw8852bx_init_txpwr_unit, 2090 .set_txpwr_ul_tb_offset = __rtw8852bx_set_txpwr_ul_tb_offset, 2091 .get_thermal = __rtw8852bx_get_thermal, 2092 .adc_cfg = rtw8852bt_adc_cfg, 2093 .btc_init_cfg = __rtw8852bx_btc_init_cfg, 2094 .btc_set_wl_pri = __rtw8852bx_btc_set_wl_pri, 2095 .btc_get_bt_rssi = __rtw8852bx_btc_get_bt_rssi, 2096 .btc_update_bt_cnt = __rtw8852bx_btc_update_bt_cnt, 2097 .btc_wl_s1_standby = __rtw8852bx_btc_wl_s1_standby, 2098 .btc_set_wl_rx_gain = __rtw8852bx_btc_set_wl_rx_gain, 2099 }; 2100 EXPORT_SYMBOL(rtw8852bx_info); 2101 2102 MODULE_AUTHOR("Realtek Corporation"); 2103 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852B common routines"); 2104 MODULE_LICENSE("Dual BSD/GPL"); 2105