1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2024 Realtek Corporation
3 */
4
5 #include "coex.h"
6 #include "debug.h"
7 #include "mac.h"
8 #include "phy.h"
9 #include "reg.h"
10 #include "rtw8852b_common.h"
11 #include "util.h"
12
13 static const struct rtw89_reg3_def rtw8852bx_pmac_ht20_mcs7_tbl[] = {
14 {0x4580, 0x0000ffff, 0x0},
15 {0x4580, 0xffff0000, 0x0},
16 {0x4584, 0x0000ffff, 0x0},
17 {0x4584, 0xffff0000, 0x0},
18 {0x4580, 0x0000ffff, 0x1},
19 {0x4578, 0x00ffffff, 0x2018b},
20 {0x4570, 0x03ffffff, 0x7},
21 {0x4574, 0x03ffffff, 0x32407},
22 {0x45b8, 0x00000010, 0x0},
23 {0x45b8, 0x00000100, 0x0},
24 {0x45b8, 0x00000080, 0x0},
25 {0x45b8, 0x00000008, 0x0},
26 {0x45a0, 0x0000ff00, 0x0},
27 {0x45a0, 0xff000000, 0x1},
28 {0x45a4, 0x0000ff00, 0x2},
29 {0x45a4, 0xff000000, 0x3},
30 {0x45b8, 0x00000020, 0x0},
31 {0x4568, 0xe0000000, 0x0},
32 {0x45b8, 0x00000002, 0x1},
33 {0x456c, 0xe0000000, 0x0},
34 {0x45b4, 0x00006000, 0x0},
35 {0x45b4, 0x00001800, 0x1},
36 {0x45b8, 0x00000040, 0x0},
37 {0x45b8, 0x00000004, 0x0},
38 {0x45b8, 0x00000200, 0x0},
39 {0x4598, 0xf8000000, 0x0},
40 {0x45b8, 0x00100000, 0x0},
41 {0x45a8, 0x00000fc0, 0x0},
42 {0x45b8, 0x00200000, 0x0},
43 {0x45b0, 0x00000038, 0x0},
44 {0x45b0, 0x000001c0, 0x0},
45 {0x45a0, 0x000000ff, 0x0},
46 {0x45b8, 0x00400000, 0x0},
47 {0x4590, 0x000007ff, 0x0},
48 {0x45b0, 0x00000e00, 0x0},
49 {0x45ac, 0x0000001f, 0x0},
50 {0x45b8, 0x00800000, 0x0},
51 {0x45a8, 0x0003f000, 0x0},
52 {0x45b8, 0x01000000, 0x0},
53 {0x45b0, 0x00007000, 0x0},
54 {0x45b0, 0x00038000, 0x0},
55 {0x45a0, 0x00ff0000, 0x0},
56 {0x45b8, 0x02000000, 0x0},
57 {0x4590, 0x003ff800, 0x0},
58 {0x45b0, 0x001c0000, 0x0},
59 {0x45ac, 0x000003e0, 0x0},
60 {0x45b8, 0x04000000, 0x0},
61 {0x45a8, 0x00fc0000, 0x0},
62 {0x45b8, 0x08000000, 0x0},
63 {0x45b0, 0x00e00000, 0x0},
64 {0x45b0, 0x07000000, 0x0},
65 {0x45a4, 0x000000ff, 0x0},
66 {0x45b8, 0x10000000, 0x0},
67 {0x4594, 0x000007ff, 0x0},
68 {0x45b0, 0x38000000, 0x0},
69 {0x45ac, 0x00007c00, 0x0},
70 {0x45b8, 0x20000000, 0x0},
71 {0x45a8, 0x3f000000, 0x0},
72 {0x45b8, 0x40000000, 0x0},
73 {0x45b4, 0x00000007, 0x0},
74 {0x45b4, 0x00000038, 0x0},
75 {0x45a4, 0x00ff0000, 0x0},
76 {0x45b8, 0x80000000, 0x0},
77 {0x4594, 0x003ff800, 0x0},
78 {0x45b4, 0x000001c0, 0x0},
79 {0x4598, 0xf8000000, 0x0},
80 {0x45b8, 0x00100000, 0x0},
81 {0x45a8, 0x00000fc0, 0x7},
82 {0x45b8, 0x00200000, 0x0},
83 {0x45b0, 0x00000038, 0x0},
84 {0x45b0, 0x000001c0, 0x0},
85 {0x45a0, 0x000000ff, 0x0},
86 {0x45b4, 0x06000000, 0x0},
87 {0x45b0, 0x00000007, 0x0},
88 {0x45b8, 0x00080000, 0x0},
89 {0x45a8, 0x0000003f, 0x0},
90 {0x457c, 0xffe00000, 0x1},
91 {0x4530, 0xffffffff, 0x0},
92 {0x4588, 0x00003fff, 0x0},
93 {0x4598, 0x000001ff, 0x0},
94 {0x4534, 0xffffffff, 0x0},
95 {0x4538, 0xffffffff, 0x0},
96 {0x453c, 0xffffffff, 0x0},
97 {0x4588, 0x0fffc000, 0x0},
98 {0x4598, 0x0003fe00, 0x0},
99 {0x4540, 0xffffffff, 0x0},
100 {0x4544, 0xffffffff, 0x0},
101 {0x4548, 0xffffffff, 0x0},
102 {0x458c, 0x00003fff, 0x0},
103 {0x4598, 0x07fc0000, 0x0},
104 {0x454c, 0xffffffff, 0x0},
105 {0x4550, 0xffffffff, 0x0},
106 {0x4554, 0xffffffff, 0x0},
107 {0x458c, 0x0fffc000, 0x0},
108 {0x459c, 0x000001ff, 0x0},
109 {0x4558, 0xffffffff, 0x0},
110 {0x455c, 0xffffffff, 0x0},
111 {0x4530, 0xffffffff, 0x4e790001},
112 {0x4588, 0x00003fff, 0x0},
113 {0x4598, 0x000001ff, 0x1},
114 {0x4534, 0xffffffff, 0x0},
115 {0x4538, 0xffffffff, 0x4b},
116 {0x45ac, 0x38000000, 0x7},
117 {0x4588, 0xf0000000, 0x0},
118 {0x459c, 0x7e000000, 0x0},
119 {0x45b8, 0x00040000, 0x0},
120 {0x45b8, 0x00020000, 0x0},
121 {0x4590, 0xffc00000, 0x0},
122 {0x45b8, 0x00004000, 0x0},
123 {0x4578, 0xff000000, 0x0},
124 {0x45b8, 0x00000400, 0x0},
125 {0x45b8, 0x00000800, 0x0},
126 {0x45b8, 0x00001000, 0x0},
127 {0x45b8, 0x00002000, 0x0},
128 {0x45b4, 0x00018000, 0x0},
129 {0x45ac, 0x07800000, 0x0},
130 {0x45b4, 0x00000600, 0x2},
131 {0x459c, 0x0001fe00, 0x80},
132 {0x45ac, 0x00078000, 0x3},
133 {0x459c, 0x01fe0000, 0x1},
134 };
135
136 static const struct rtw89_reg3_def rtw8852bx_btc_preagc_en_defs[] = {
137 {0x46D0, GENMASK(1, 0), 0x3},
138 {0x4790, GENMASK(1, 0), 0x3},
139 {0x4AD4, GENMASK(31, 0), 0xf},
140 {0x4AE0, GENMASK(31, 0), 0xf},
141 {0x4688, GENMASK(31, 24), 0x80},
142 {0x476C, GENMASK(31, 24), 0x80},
143 {0x4694, GENMASK(7, 0), 0x80},
144 {0x4694, GENMASK(15, 8), 0x80},
145 {0x4778, GENMASK(7, 0), 0x80},
146 {0x4778, GENMASK(15, 8), 0x80},
147 {0x4AE4, GENMASK(23, 0), 0x780D1E},
148 {0x4AEC, GENMASK(23, 0), 0x780D1E},
149 {0x469C, GENMASK(31, 26), 0x34},
150 {0x49F0, GENMASK(31, 26), 0x34},
151 };
152
153 static DECLARE_PHY_REG3_TBL(rtw8852bx_btc_preagc_en_defs);
154
155 static const struct rtw89_reg3_def rtw8852bx_btc_preagc_dis_defs[] = {
156 {0x46D0, GENMASK(1, 0), 0x0},
157 {0x4790, GENMASK(1, 0), 0x0},
158 {0x4AD4, GENMASK(31, 0), 0x60},
159 {0x4AE0, GENMASK(31, 0), 0x60},
160 {0x4688, GENMASK(31, 24), 0x1a},
161 {0x476C, GENMASK(31, 24), 0x1a},
162 {0x4694, GENMASK(7, 0), 0x2a},
163 {0x4694, GENMASK(15, 8), 0x2a},
164 {0x4778, GENMASK(7, 0), 0x2a},
165 {0x4778, GENMASK(15, 8), 0x2a},
166 {0x4AE4, GENMASK(23, 0), 0x79E99E},
167 {0x4AEC, GENMASK(23, 0), 0x79E99E},
168 {0x469C, GENMASK(31, 26), 0x26},
169 {0x49F0, GENMASK(31, 26), 0x26},
170 };
171
172 static DECLARE_PHY_REG3_TBL(rtw8852bx_btc_preagc_dis_defs);
173
rtw8852be_efuse_parsing(struct rtw89_efuse * efuse,struct rtw8852bx_efuse * map)174 static void rtw8852be_efuse_parsing(struct rtw89_efuse *efuse,
175 struct rtw8852bx_efuse *map)
176 {
177 ether_addr_copy(efuse->addr, map->e.mac_addr);
178 efuse->rfe_type = map->rfe_type;
179 efuse->xtal_cap = map->xtal_k;
180 }
181
rtw8852bx_efuse_parsing_tssi(struct rtw89_dev * rtwdev,struct rtw8852bx_efuse * map)182 static void rtw8852bx_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
183 struct rtw8852bx_efuse *map)
184 {
185 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
186 struct rtw8852bx_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi};
187 u8 i, j;
188
189 tssi->thermal[RF_PATH_A] = map->path_a_therm;
190 tssi->thermal[RF_PATH_B] = map->path_b_therm;
191
192 for (i = 0; i < RF_PATH_NUM_8852BX; i++) {
193 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
194 sizeof(ofst[i]->cck_tssi));
195
196 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
197 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
198 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
199 i, j, tssi->tssi_cck[i][j]);
200
201 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
202 sizeof(ofst[i]->bw40_tssi));
203 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
204 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
205
206 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
207 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
208 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
209 i, j, tssi->tssi_mcs[i][j]);
210 }
211 }
212
_decode_efuse_gain(u8 data,s8 * high,s8 * low)213 static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low)
214 {
215 if (high)
216 *high = sign_extend32(FIELD_GET(GENMASK(7, 4), data), 3);
217 if (low)
218 *low = sign_extend32(FIELD_GET(GENMASK(3, 0), data), 3);
219
220 return data != 0xff;
221 }
222
rtw8852bx_efuse_parsing_gain_offset(struct rtw89_dev * rtwdev,struct rtw8852bx_efuse * map)223 static void rtw8852bx_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev,
224 struct rtw8852bx_efuse *map)
225 {
226 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
227 bool valid = false;
228
229 valid |= _decode_efuse_gain(map->rx_gain_2g_cck,
230 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK],
231 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK]);
232 valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm,
233 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM],
234 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM]);
235 valid |= _decode_efuse_gain(map->rx_gain_5g_low,
236 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW],
237 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW]);
238 valid |= _decode_efuse_gain(map->rx_gain_5g_mid,
239 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID],
240 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID]);
241 valid |= _decode_efuse_gain(map->rx_gain_5g_high,
242 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH],
243 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH]);
244
245 gain->offset_valid = valid;
246 }
247
__rtw8852bx_read_efuse(struct rtw89_dev * rtwdev,u8 * log_map,enum rtw89_efuse_block block)248 static int __rtw8852bx_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map,
249 enum rtw89_efuse_block block)
250 {
251 struct rtw89_efuse *efuse = &rtwdev->efuse;
252 struct rtw8852bx_efuse *map;
253
254 map = (struct rtw8852bx_efuse *)log_map;
255
256 efuse->country_code[0] = map->country_code[0];
257 efuse->country_code[1] = map->country_code[1];
258 rtw8852bx_efuse_parsing_tssi(rtwdev, map);
259 rtw8852bx_efuse_parsing_gain_offset(rtwdev, map);
260
261 switch (rtwdev->hci.type) {
262 case RTW89_HCI_TYPE_PCIE:
263 rtw8852be_efuse_parsing(efuse, map);
264 break;
265 default:
266 return -EOPNOTSUPP;
267 }
268
269 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
270
271 return 0;
272 }
273
rtw8852bx_phycap_parsing_power_cal(struct rtw89_dev * rtwdev,u8 * phycap_map)274 static void rtw8852bx_phycap_parsing_power_cal(struct rtw89_dev *rtwdev, u8 *phycap_map)
275 {
276 #define PWR_K_CHK_OFFSET 0x5E9
277 #define PWR_K_CHK_VALUE 0xAA
278 u32 offset = PWR_K_CHK_OFFSET - rtwdev->chip->phycap_addr;
279
280 if (phycap_map[offset] == PWR_K_CHK_VALUE)
281 rtwdev->efuse.power_k_valid = true;
282 }
283
rtw8852bx_phycap_parsing_tssi(struct rtw89_dev * rtwdev,u8 * phycap_map)284 static void rtw8852bx_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
285 {
286 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
287 static const u32 tssi_trim_addr[RF_PATH_NUM_8852BX] = {0x5D6, 0x5AB};
288 u32 addr = rtwdev->chip->phycap_addr;
289 bool pg = false;
290 u32 ofst;
291 u8 i, j;
292
293 for (i = 0; i < RF_PATH_NUM_8852BX; i++) {
294 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) {
295 /* addrs are in decreasing order */
296 ofst = tssi_trim_addr[i] - addr - j;
297 tssi->tssi_trim[i][j] = phycap_map[ofst];
298
299 if (phycap_map[ofst] != 0xff)
300 pg = true;
301 }
302 }
303
304 if (!pg) {
305 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim));
306 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
307 "[TSSI][TRIM] no PG, set all trim info to 0\n");
308 }
309
310 for (i = 0; i < RF_PATH_NUM_8852BX; i++)
311 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++)
312 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
313 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
314 i, j, tssi->tssi_trim[i][j],
315 tssi_trim_addr[i] - j);
316 }
317
rtw8852bx_phycap_parsing_thermal_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)318 static void rtw8852bx_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
319 u8 *phycap_map)
320 {
321 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
322 static const u32 thm_trim_addr[RF_PATH_NUM_8852BX] = {0x5DF, 0x5DC};
323 u32 addr = rtwdev->chip->phycap_addr;
324 u8 i;
325
326 for (i = 0; i < RF_PATH_NUM_8852BX; i++) {
327 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr];
328
329 rtw89_debug(rtwdev, RTW89_DBG_RFK,
330 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
331 i, info->thermal_trim[i]);
332
333 if (info->thermal_trim[i] != 0xff)
334 info->pg_thermal_trim = true;
335 }
336 }
337
rtw8852bx_thermal_trim(struct rtw89_dev * rtwdev)338 static void rtw8852bx_thermal_trim(struct rtw89_dev *rtwdev)
339 {
340 #define __thm_setting(raw) \
341 ({ \
342 u8 __v = (raw); \
343 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \
344 })
345 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
346 u8 i, val;
347
348 if (!info->pg_thermal_trim) {
349 rtw89_debug(rtwdev, RTW89_DBG_RFK,
350 "[THERMAL][TRIM] no PG, do nothing\n");
351
352 return;
353 }
354
355 for (i = 0; i < RF_PATH_NUM_8852BX; i++) {
356 val = __thm_setting(info->thermal_trim[i]);
357 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
358
359 rtw89_debug(rtwdev, RTW89_DBG_RFK,
360 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
361 i, val);
362 }
363 #undef __thm_setting
364 }
365
rtw8852bx_phycap_parsing_pa_bias_trim(struct rtw89_dev * rtwdev,u8 * phycap_map)366 static void rtw8852bx_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
367 u8 *phycap_map)
368 {
369 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
370 static const u32 pabias_trim_addr[RF_PATH_NUM_8852BX] = {0x5DE, 0x5DB};
371 u32 addr = rtwdev->chip->phycap_addr;
372 u8 i;
373
374 for (i = 0; i < RF_PATH_NUM_8852BX; i++) {
375 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
376
377 rtw89_debug(rtwdev, RTW89_DBG_RFK,
378 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
379 i, info->pa_bias_trim[i]);
380
381 if (info->pa_bias_trim[i] != 0xff)
382 info->pg_pa_bias_trim = true;
383 }
384 }
385
rtw8852bx_pa_bias_trim(struct rtw89_dev * rtwdev)386 static void rtw8852bx_pa_bias_trim(struct rtw89_dev *rtwdev)
387 {
388 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
389 u8 pabias_2g, pabias_5g;
390 u8 i;
391
392 if (!info->pg_pa_bias_trim) {
393 rtw89_debug(rtwdev, RTW89_DBG_RFK,
394 "[PA_BIAS][TRIM] no PG, do nothing\n");
395
396 return;
397 }
398
399 for (i = 0; i < RF_PATH_NUM_8852BX; i++) {
400 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);
401 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]);
402
403 rtw89_debug(rtwdev, RTW89_DBG_RFK,
404 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
405 i, pabias_2g, pabias_5g);
406
407 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
408 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
409 }
410 }
411
rtw8852bx_phycap_parsing_gain_comp(struct rtw89_dev * rtwdev,u8 * phycap_map)412 static void rtw8852bx_phycap_parsing_gain_comp(struct rtw89_dev *rtwdev, u8 *phycap_map)
413 {
414 static const u32 comp_addrs[][RTW89_SUBBAND_2GHZ_5GHZ_NR] = {
415 {0x5BB, 0x5BA, 0, 0x5B9, 0x5B8},
416 {0x590, 0x58F, 0, 0x58E, 0x58D},
417 };
418 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
419 u32 phycap_addr = rtwdev->chip->phycap_addr;
420 bool valid = false;
421 int path, i;
422 u8 data;
423
424 for (path = 0; path < 2; path++)
425 for (i = 0; i < RTW89_SUBBAND_2GHZ_5GHZ_NR; i++) {
426 if (comp_addrs[path][i] == 0)
427 continue;
428
429 data = phycap_map[comp_addrs[path][i] - phycap_addr];
430 valid |= _decode_efuse_gain(data, NULL,
431 &gain->comp[path][i]);
432 }
433
434 gain->comp_valid = valid;
435 }
436
__rtw8852bx_read_phycap(struct rtw89_dev * rtwdev,u8 * phycap_map)437 static int __rtw8852bx_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
438 {
439 rtw8852bx_phycap_parsing_power_cal(rtwdev, phycap_map);
440 rtw8852bx_phycap_parsing_tssi(rtwdev, phycap_map);
441 rtw8852bx_phycap_parsing_thermal_trim(rtwdev, phycap_map);
442 rtw8852bx_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
443 rtw8852bx_phycap_parsing_gain_comp(rtwdev, phycap_map);
444
445 return 0;
446 }
447
__rtw8852bx_power_trim(struct rtw89_dev * rtwdev)448 static void __rtw8852bx_power_trim(struct rtw89_dev *rtwdev)
449 {
450 rtw8852bx_thermal_trim(rtwdev);
451 rtw8852bx_pa_bias_trim(rtwdev);
452 }
453
__rtw8852bx_set_channel_mac(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,u8 mac_idx)454 static void __rtw8852bx_set_channel_mac(struct rtw89_dev *rtwdev,
455 const struct rtw89_chan *chan,
456 u8 mac_idx)
457 {
458 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx);
459 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
460 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx);
461 u8 txsc20 = 0, txsc40 = 0;
462
463 switch (chan->band_width) {
464 case RTW89_CHANNEL_WIDTH_80:
465 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_40);
466 fallthrough;
467 case RTW89_CHANNEL_WIDTH_40:
468 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_20);
469 break;
470 default:
471 break;
472 }
473
474 switch (chan->band_width) {
475 case RTW89_CHANNEL_WIDTH_80:
476 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1));
477 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4));
478 break;
479 case RTW89_CHANNEL_WIDTH_40:
480 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0));
481 rtw89_write32(rtwdev, sub_carr, txsc20);
482 break;
483 case RTW89_CHANNEL_WIDTH_20:
484 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK);
485 rtw89_write32(rtwdev, sub_carr, 0);
486 break;
487 default:
488 break;
489 }
490
491 if (chan->channel > 14) {
492 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE);
493 rtw89_write8_set(rtwdev, chk_rate,
494 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
495 } else {
496 rtw89_write8_set(rtwdev, chk_rate, B_AX_BAND_MODE);
497 rtw89_write8_clr(rtwdev, chk_rate,
498 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
499 }
500 }
501
502 static const u32 rtw8852bx_sco_barker_threshold[14] = {
503 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6,
504 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4
505 };
506
507 static const u32 rtw8852bx_sco_cck_threshold[14] = {
508 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724,
509 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed
510 };
511
rtw8852bx_ctrl_sco_cck(struct rtw89_dev * rtwdev,u8 primary_ch)512 static void rtw8852bx_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 primary_ch)
513 {
514 u8 ch_element = primary_ch - 1;
515
516 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH,
517 rtw8852bx_sco_barker_threshold[ch_element]);
518 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH,
519 rtw8852bx_sco_cck_threshold[ch_element]);
520 }
521
rtw8852bx_sco_mapping(u8 central_ch)522 static u8 rtw8852bx_sco_mapping(u8 central_ch)
523 {
524 if (central_ch == 1)
525 return 109;
526 else if (central_ch >= 2 && central_ch <= 6)
527 return 108;
528 else if (central_ch >= 7 && central_ch <= 10)
529 return 107;
530 else if (central_ch >= 11 && central_ch <= 14)
531 return 106;
532 else if (central_ch == 36 || central_ch == 38)
533 return 51;
534 else if (central_ch >= 40 && central_ch <= 58)
535 return 50;
536 else if (central_ch >= 60 && central_ch <= 64)
537 return 49;
538 else if (central_ch == 100 || central_ch == 102)
539 return 48;
540 else if (central_ch >= 104 && central_ch <= 126)
541 return 47;
542 else if (central_ch >= 128 && central_ch <= 151)
543 return 46;
544 else if (central_ch >= 153 && central_ch <= 177)
545 return 45;
546 else
547 return 0;
548 }
549
550 struct rtw8852bx_bb_gain {
551 u32 gain_g[BB_PATH_NUM_8852BX];
552 u32 gain_a[BB_PATH_NUM_8852BX];
553 u32 gain_mask;
554 };
555
556 static const struct rtw8852bx_bb_gain bb_gain_lna[LNA_GAIN_NUM] = {
557 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740},
558 .gain_mask = 0x00ff0000 },
559 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740},
560 .gain_mask = 0xff000000 },
561 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
562 .gain_mask = 0x000000ff },
563 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
564 .gain_mask = 0x0000ff00 },
565 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
566 .gain_mask = 0x00ff0000 },
567 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
568 .gain_mask = 0xff000000 },
569 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748},
570 .gain_mask = 0x000000ff },
571 };
572
573 static const struct rtw8852bx_bb_gain bb_gain_tia[TIA_GAIN_NUM] = {
574 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748},
575 .gain_mask = 0x00ff0000 },
576 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748},
577 .gain_mask = 0xff000000 },
578 };
579
rtw8852bx_set_gain_error(struct rtw89_dev * rtwdev,enum rtw89_subband subband,enum rtw89_rf_path path)580 static void rtw8852bx_set_gain_error(struct rtw89_dev *rtwdev,
581 enum rtw89_subband subband,
582 enum rtw89_rf_path path)
583 {
584 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
585 u8 gain_band = rtw89_subband_to_bb_gain_band(subband);
586 s32 val;
587 u32 reg;
588 u32 mask;
589 int i;
590
591 for (i = 0; i < LNA_GAIN_NUM; i++) {
592 if (subband == RTW89_CH_2G)
593 reg = bb_gain_lna[i].gain_g[path];
594 else
595 reg = bb_gain_lna[i].gain_a[path];
596
597 mask = bb_gain_lna[i].gain_mask;
598 val = gain->lna_gain[gain_band][path][i];
599 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
600 }
601
602 for (i = 0; i < TIA_GAIN_NUM; i++) {
603 if (subband == RTW89_CH_2G)
604 reg = bb_gain_tia[i].gain_g[path];
605 else
606 reg = bb_gain_tia[i].gain_a[path];
607
608 mask = bb_gain_tia[i].gain_mask;
609 val = gain->tia_gain[gain_band][path][i];
610 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
611 }
612 }
613
rtw8852bt_ext_loss_avg_update(struct rtw89_dev * rtwdev,s8 ext_loss_a,s8 ext_loss_b)614 static void rtw8852bt_ext_loss_avg_update(struct rtw89_dev *rtwdev,
615 s8 ext_loss_a, s8 ext_loss_b)
616 {
617 s8 ext_loss_avg;
618 u64 linear;
619 u8 pwrofst;
620
621 if (ext_loss_a == ext_loss_b) {
622 ext_loss_avg = ext_loss_a;
623 } else {
624 linear = rtw89_db_2_linear(abs(ext_loss_a - ext_loss_b)) + 1;
625 linear = DIV_ROUND_CLOSEST_ULL(linear / 2, 1 << RTW89_LINEAR_FRAC_BITS);
626 ext_loss_avg = rtw89_linear_2_db(linear);
627 ext_loss_avg += min(ext_loss_a, ext_loss_b);
628 }
629
630 pwrofst = max(DIV_ROUND_CLOSEST(ext_loss_avg, 4) + 16, EDCCA_PWROFST_DEFAULT);
631
632 rtw89_phy_write32_mask(rtwdev, R_PWOFST, B_PWOFST, pwrofst);
633 }
634
rtw8852bx_set_gain_offset(struct rtw89_dev * rtwdev,enum rtw89_subband subband,enum rtw89_phy_idx phy_idx)635 static void rtw8852bx_set_gain_offset(struct rtw89_dev *rtwdev,
636 enum rtw89_subband subband,
637 enum rtw89_phy_idx phy_idx)
638 {
639 static const u32 gain_err_addr[2] = {R_P0_AGC_RSVD, R_P1_AGC_RSVD};
640 static const u32 rssi_ofst_addr[2] = {R_PATH0_G_TIA1_LNA6_OP1DB_V1,
641 R_PATH1_G_TIA1_LNA6_OP1DB_V1};
642 struct rtw89_hal *hal = &rtwdev->hal;
643 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain;
644 enum rtw89_gain_offset gain_ofdm_band;
645 s8 ext_loss_a = 0, ext_loss_b = 0;
646 s32 offset_a, offset_b;
647 s32 offset_ofdm, offset_cck;
648 s32 tmp;
649 u8 path;
650
651 if (!efuse_gain->comp_valid)
652 goto next;
653
654 for (path = RF_PATH_A; path < BB_PATH_NUM_8852BX; path++) {
655 tmp = efuse_gain->comp[path][subband];
656 tmp = clamp_t(s32, tmp << 2, S8_MIN, S8_MAX);
657 rtw89_phy_write32_mask(rtwdev, gain_err_addr[path], MASKBYTE0, tmp);
658 }
659
660 next:
661 if (!efuse_gain->offset_valid)
662 goto ext_loss;
663
664 gain_ofdm_band = rtw89_subband_to_gain_offset_band_of_ofdm(subband);
665
666 offset_a = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band];
667 offset_b = -efuse_gain->offset[RF_PATH_B][gain_ofdm_band];
668
669 tmp = -((offset_a << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2));
670 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
671 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_A], B_PATH0_R_G_OFST_MASK, tmp);
672
673 tmp = -((offset_b << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2));
674 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
675 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_B], B_PATH0_R_G_OFST_MASK, tmp);
676
677 if (hal->antenna_rx == RF_B) {
678 offset_ofdm = -efuse_gain->offset[RF_PATH_B][gain_ofdm_band];
679 offset_cck = -efuse_gain->offset[RF_PATH_B][0];
680 } else {
681 offset_ofdm = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band];
682 offset_cck = -efuse_gain->offset[RF_PATH_A][0];
683 }
684
685 tmp = (offset_ofdm << 4) + efuse_gain->offset_base[RTW89_PHY_0];
686 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
687 rtw89_phy_write32_idx(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
688
689 tmp = (offset_ofdm << 4) + efuse_gain->rssi_base[RTW89_PHY_0];
690 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
691 rtw89_phy_write32_idx(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
692
693 if (subband == RTW89_CH_2G) {
694 tmp = (offset_cck << 3) + (efuse_gain->offset_base[RTW89_PHY_0] >> 1);
695 tmp = clamp_t(s32, tmp, S8_MIN >> 1, S8_MAX >> 1);
696 rtw89_phy_write32_mask(rtwdev, R_RX_RPL_OFST,
697 B_RX_RPL_OFST_CCK_MASK, tmp);
698 }
699
700 ext_loss_a = (offset_a << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2);
701 ext_loss_b = (offset_b << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2);
702
703 ext_loss:
704 if (rtwdev->chip->chip_id == RTL8852BT)
705 rtw8852bt_ext_loss_avg_update(rtwdev, ext_loss_a, ext_loss_b);
706 }
707
708 static
rtw8852bx_set_rxsc_rpl_comp(struct rtw89_dev * rtwdev,enum rtw89_subband subband)709 void rtw8852bx_set_rxsc_rpl_comp(struct rtw89_dev *rtwdev, enum rtw89_subband subband)
710 {
711 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
712 u8 band = rtw89_subband_to_bb_gain_band(subband);
713 u32 val;
714
715 val = u32_encode_bits((gain->rpl_ofst_20[band][RF_PATH_A] +
716 gain->rpl_ofst_20[band][RF_PATH_B]) >> 1, B_P0_RPL1_20_MASK) |
717 u32_encode_bits((gain->rpl_ofst_40[band][RF_PATH_A][0] +
718 gain->rpl_ofst_40[band][RF_PATH_B][0]) >> 1, B_P0_RPL1_40_MASK) |
719 u32_encode_bits((gain->rpl_ofst_40[band][RF_PATH_A][1] +
720 gain->rpl_ofst_40[band][RF_PATH_B][1]) >> 1, B_P0_RPL1_41_MASK);
721 val >>= B_P0_RPL1_SHIFT;
722 rtw89_phy_write32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_MASK, val);
723 rtw89_phy_write32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_MASK, val);
724
725 val = u32_encode_bits((gain->rpl_ofst_40[band][RF_PATH_A][2] +
726 gain->rpl_ofst_40[band][RF_PATH_B][2]) >> 1, B_P0_RTL2_42_MASK) |
727 u32_encode_bits((gain->rpl_ofst_80[band][RF_PATH_A][0] +
728 gain->rpl_ofst_80[band][RF_PATH_B][0]) >> 1, B_P0_RTL2_80_MASK) |
729 u32_encode_bits((gain->rpl_ofst_80[band][RF_PATH_A][1] +
730 gain->rpl_ofst_80[band][RF_PATH_B][1]) >> 1, B_P0_RTL2_81_MASK) |
731 u32_encode_bits((gain->rpl_ofst_80[band][RF_PATH_A][10] +
732 gain->rpl_ofst_80[band][RF_PATH_B][10]) >> 1, B_P0_RTL2_8A_MASK);
733 rtw89_phy_write32(rtwdev, R_P0_RPL2, val);
734 rtw89_phy_write32(rtwdev, R_P1_RPL2, val);
735
736 val = u32_encode_bits((gain->rpl_ofst_80[band][RF_PATH_A][2] +
737 gain->rpl_ofst_80[band][RF_PATH_B][2]) >> 1, B_P0_RTL3_82_MASK) |
738 u32_encode_bits((gain->rpl_ofst_80[band][RF_PATH_A][3] +
739 gain->rpl_ofst_80[band][RF_PATH_B][3]) >> 1, B_P0_RTL3_83_MASK) |
740 u32_encode_bits((gain->rpl_ofst_80[band][RF_PATH_A][4] +
741 gain->rpl_ofst_80[band][RF_PATH_B][4]) >> 1, B_P0_RTL3_84_MASK) |
742 u32_encode_bits((gain->rpl_ofst_80[band][RF_PATH_A][9] +
743 gain->rpl_ofst_80[band][RF_PATH_B][9]) >> 1, B_P0_RTL3_89_MASK);
744 rtw89_phy_write32(rtwdev, R_P0_RPL3, val);
745 rtw89_phy_write32(rtwdev, R_P1_RPL3, val);
746 }
747
rtw8852bx_ctrl_ch(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)748 static void rtw8852bx_ctrl_ch(struct rtw89_dev *rtwdev,
749 const struct rtw89_chan *chan,
750 enum rtw89_phy_idx phy_idx)
751 {
752 u8 central_ch = chan->channel;
753 u8 subband = chan->subband_type;
754 u8 sco_comp;
755 bool is_2g = central_ch <= 14;
756
757 /* Path A */
758 if (is_2g)
759 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
760 B_PATH0_BAND_SEL_MSK_V1, 1, phy_idx);
761 else
762 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
763 B_PATH0_BAND_SEL_MSK_V1, 0, phy_idx);
764
765 /* Path B */
766 if (is_2g)
767 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1,
768 B_PATH1_BAND_SEL_MSK_V1, 1, phy_idx);
769 else
770 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1,
771 B_PATH1_BAND_SEL_MSK_V1, 0, phy_idx);
772
773 /* SCO compensate FC setting */
774 sco_comp = rtw8852bx_sco_mapping(central_ch);
775 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_INV, sco_comp, phy_idx);
776
777 if (chan->band_type == RTW89_BAND_6G)
778 return;
779
780 /* CCK parameters */
781 if (central_ch == 14) {
782 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3b13ff);
783 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x1c42de);
784 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfdb0ad);
785 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xf60f6e);
786 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xfd8f92);
787 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011);
788 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c);
789 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xfff00a);
790 } else {
791 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3d23ff);
792 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x29b354);
793 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8);
794 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xfdb053);
795 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xf86f9a);
796 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0xfaef92);
797 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0xfe5fcc);
798 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xffdff5);
799 }
800
801 rtw8852bx_set_gain_error(rtwdev, subband, RF_PATH_A);
802 rtw8852bx_set_gain_error(rtwdev, subband, RF_PATH_B);
803 rtw8852bx_set_gain_offset(rtwdev, subband, phy_idx);
804 rtw8852bx_set_rxsc_rpl_comp(rtwdev, subband);
805 }
806
rtw8852b_bw_setting(struct rtw89_dev * rtwdev,u8 bw,u8 path)807 static void rtw8852b_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path)
808 {
809 static const u32 adc_sel[2] = {0xC0EC, 0xC1EC};
810 static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4};
811
812 switch (bw) {
813 case RTW89_CHANNEL_WIDTH_5:
814 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1);
815 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0);
816 break;
817 case RTW89_CHANNEL_WIDTH_10:
818 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2);
819 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1);
820 break;
821 case RTW89_CHANNEL_WIDTH_20:
822 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
823 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
824 break;
825 case RTW89_CHANNEL_WIDTH_40:
826 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
827 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
828 break;
829 case RTW89_CHANNEL_WIDTH_80:
830 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
831 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
832 break;
833 default:
834 rtw89_warn(rtwdev, "Fail to set ADC\n");
835 }
836 }
837
838 static
rtw8852bt_adc_cfg(struct rtw89_dev * rtwdev,u8 bw,u8 path)839 void rtw8852bt_adc_cfg(struct rtw89_dev *rtwdev, u8 bw, u8 path)
840 {
841 static const u32 rck_reset_count[2] = {0xC0E8, 0xC1E8};
842 static const u32 adc_op5_bw_sel[2] = {0xC0D8, 0xC1D8};
843 static const u32 adc_sample_td[2] = {0xC0D4, 0xC1D4};
844 static const u32 adc_rst_cycle[2] = {0xC0EC, 0xC1EC};
845 static const u32 decim_filter[2] = {0xC0EC, 0xC1EC};
846 static const u32 rck_offset[2] = {0xC0C4, 0xC1C4};
847 static const u32 rx_adc_clk[2] = {0x12A0, 0x32A0};
848 static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4};
849 static const u32 idac2_1[2] = {0xC0D4, 0xC1D4};
850 static const u32 idac2[2] = {0xC0D4, 0xC1D4};
851 static const u32 upd_clk_adc = {0x704};
852
853 if (rtwdev->chip->chip_id != RTL8852BT)
854 return;
855
856 rtw89_phy_write32_mask(rtwdev, idac2[path], B_P0_CFCH_CTL, 0x8);
857 rtw89_phy_write32_mask(rtwdev, rck_reset_count[path], B_ADCMOD_LP, 0x9);
858 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], B_WDADC_SEL, 0x2);
859 rtw89_phy_write32_mask(rtwdev, rx_adc_clk[path], B_P0_RXCK_ADJ, 0x49);
860 rtw89_phy_write32_mask(rtwdev, decim_filter[path], B_DCIM_FR, 0x0);
861
862 switch (bw) {
863 case RTW89_CHANNEL_WIDTH_5:
864 case RTW89_CHANNEL_WIDTH_10:
865 case RTW89_CHANNEL_WIDTH_20:
866 case RTW89_CHANNEL_WIDTH_40:
867 rtw89_phy_write32_mask(rtwdev, idac2_1[path], B_P0_CFCH_EN, 0x2);
868 rtw89_phy_write32_mask(rtwdev, adc_sample_td[path], B_P0_CFCH_BW0, 0x3);
869 rtw89_phy_write32_mask(rtwdev, adc_op5_bw_sel[path], B_P0_CFCH_BW1, 0xf);
870 rtw89_phy_write32_mask(rtwdev, rck_offset[path], B_DRCK_MUL, 0x0);
871 /* Tx TSSI ADC update */
872 rtw89_phy_write32_mask(rtwdev, upd_clk_adc, B_RSTB_ASYNC_BW80, 0);
873
874 if (rtwdev->efuse.rfe_type >= 51)
875 rtw89_phy_write32_mask(rtwdev, adc_rst_cycle[path], B_DCIM_RC, 0x2);
876 else
877 rtw89_phy_write32_mask(rtwdev, adc_rst_cycle[path], B_DCIM_RC, 0x3);
878 break;
879 case RTW89_CHANNEL_WIDTH_80:
880 rtw89_phy_write32_mask(rtwdev, idac2_1[path], B_P0_CFCH_EN, 0x2);
881 rtw89_phy_write32_mask(rtwdev, adc_sample_td[path], B_P0_CFCH_BW0, 0x2);
882 rtw89_phy_write32_mask(rtwdev, adc_op5_bw_sel[path], B_P0_CFCH_BW1, 0x8);
883 rtw89_phy_write32_mask(rtwdev, rck_offset[path], B_DRCK_MUL, 0x0);
884 rtw89_phy_write32_mask(rtwdev, adc_rst_cycle[path], B_DCIM_RC, 0x3);
885 /* Tx TSSI ADC update */
886 rtw89_phy_write32_mask(rtwdev, upd_clk_adc, B_RSTB_ASYNC_BW80, 1);
887 break;
888 case RTW89_CHANNEL_WIDTH_160:
889 rtw89_phy_write32_mask(rtwdev, idac2_1[path], B_P0_CFCH_EN, 0x0);
890 rtw89_phy_write32_mask(rtwdev, adc_sample_td[path], B_P0_CFCH_BW0, 0x2);
891 rtw89_phy_write32_mask(rtwdev, adc_op5_bw_sel[path], B_P0_CFCH_BW1, 0x4);
892 rtw89_phy_write32_mask(rtwdev, rck_offset[path], B_DRCK_MUL, 0x6);
893 rtw89_phy_write32_mask(rtwdev, adc_rst_cycle[path], B_DCIM_RC, 0x3);
894 /* Tx TSSI ADC update */
895 rtw89_phy_write32_mask(rtwdev, upd_clk_adc, B_RSTB_ASYNC_BW80, 2);
896 break;
897 default:
898 rtw89_warn(rtwdev, "Fail to set ADC\n");
899 break;
900 }
901 }
902
rtw8852bx_ctrl_bw(struct rtw89_dev * rtwdev,u8 pri_ch,u8 bw,enum rtw89_phy_idx phy_idx)903 static void rtw8852bx_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
904 enum rtw89_phy_idx phy_idx)
905 {
906 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
907 u32 rx_path_0;
908 u32 val;
909
910 rx_path_0 = rtw89_phy_read32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, phy_idx);
911
912 switch (bw) {
913 case RTW89_CHANNEL_WIDTH_5:
914 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
915 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x1, phy_idx);
916 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
917
918 /*Set RF mode at 3 */
919 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
920 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
921 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
922 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
923 if (chip_id == RTL8852BT) {
924 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
925 B_PATH0_BAND_NRBW_EN_V1, 0x0, phy_idx);
926 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1,
927 B_PATH1_BAND_NRBW_EN_V1, 0x0, phy_idx);
928 }
929 break;
930 case RTW89_CHANNEL_WIDTH_10:
931 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
932 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x2, phy_idx);
933 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
934
935 /*Set RF mode at 3 */
936 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
937 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
938 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
939 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
940 if (chip_id == RTL8852BT) {
941 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
942 B_PATH0_BAND_NRBW_EN_V1, 0x0, phy_idx);
943 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1,
944 B_PATH1_BAND_NRBW_EN_V1, 0x0, phy_idx);
945 }
946 break;
947 case RTW89_CHANNEL_WIDTH_20:
948 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
949 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
950 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
951
952 /*Set RF mode at 3 */
953 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
954 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
955 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
956 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
957 if (chip_id == RTL8852BT) {
958 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
959 B_PATH0_BAND_NRBW_EN_V1, 0x1, phy_idx);
960 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1,
961 B_PATH1_BAND_NRBW_EN_V1, 0x1, phy_idx);
962 }
963 break;
964 case RTW89_CHANNEL_WIDTH_40:
965 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x1, phy_idx);
966 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
967 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH,
968 pri_ch, phy_idx);
969
970 /*Set RF mode at 3 */
971 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
972 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
973 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
974 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
975 /*CCK primary channel */
976 if (pri_ch == RTW89_SC_20_UPPER)
977 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1);
978 else
979 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0);
980
981 break;
982 case RTW89_CHANNEL_WIDTH_80:
983 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x2, phy_idx);
984 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
985 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH,
986 pri_ch, phy_idx);
987
988 /*Set RF mode at A */
989 val = chip_id == RTL8852BT ? 0x333 : 0xaaa;
990 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
991 B_P0_RFMODE_ORI_RX_ALL, val, phy_idx);
992 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
993 B_P1_RFMODE_ORI_RX_ALL, val, phy_idx);
994 break;
995 default:
996 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
997 pri_ch);
998 }
999
1000 if (chip_id == RTL8852B) {
1001 rtw8852b_bw_setting(rtwdev, bw, RF_PATH_A);
1002 rtw8852b_bw_setting(rtwdev, bw, RF_PATH_B);
1003 } else if (chip_id == RTL8852BT) {
1004 rtw8852bt_adc_cfg(rtwdev, bw, RF_PATH_A);
1005 rtw8852bt_adc_cfg(rtwdev, bw, RF_PATH_B);
1006 }
1007
1008 if (rx_path_0 == 0x1)
1009 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
1010 B_P1_RFMODE_ORI_RX_ALL, 0x111, phy_idx);
1011 else if (rx_path_0 == 0x2)
1012 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
1013 B_P0_RFMODE_ORI_RX_ALL, 0x111, phy_idx);
1014 }
1015
rtw8852bx_ctrl_cck_en(struct rtw89_dev * rtwdev,bool cck_en)1016 static void rtw8852bx_ctrl_cck_en(struct rtw89_dev *rtwdev, bool cck_en)
1017 {
1018 if (cck_en) {
1019 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1);
1020 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0);
1021 } else {
1022 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0);
1023 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1);
1024 }
1025 }
1026
rtw8852bx_5m_mask(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1027 static void rtw8852bx_5m_mask(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
1028 enum rtw89_phy_idx phy_idx)
1029 {
1030 u8 pri_ch = chan->pri_ch_idx;
1031 bool mask_5m_low;
1032 bool mask_5m_en;
1033
1034 switch (chan->band_width) {
1035 case RTW89_CHANNEL_WIDTH_40:
1036 /* Prich=1: Mask 5M High, Prich=2: Mask 5M Low */
1037 mask_5m_en = true;
1038 mask_5m_low = pri_ch == RTW89_SC_20_LOWER;
1039 break;
1040 case RTW89_CHANNEL_WIDTH_80:
1041 /* Prich=3: Mask 5M High, Prich=4: Mask 5M Low, Else: Disable */
1042 mask_5m_en = pri_ch == RTW89_SC_20_UPMOST ||
1043 pri_ch == RTW89_SC_20_LOWEST;
1044 mask_5m_low = pri_ch == RTW89_SC_20_LOWEST;
1045 break;
1046 default:
1047 mask_5m_en = false;
1048 break;
1049 }
1050
1051 if (!mask_5m_en) {
1052 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x0);
1053 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x0);
1054 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1,
1055 B_ASSIGN_SBD_OPT_EN_V1, 0x0, phy_idx);
1056 return;
1057 }
1058
1059 if (mask_5m_low) {
1060 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x4);
1061 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1);
1062 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x0);
1063 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x1);
1064 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_TH, 0x4);
1065 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x1);
1066 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB2, 0x0);
1067 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB0, 0x1);
1068 } else {
1069 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x4);
1070 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1);
1071 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x1);
1072 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x0);
1073 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_TH, 0x4);
1074 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x1);
1075 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB2, 0x1);
1076 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB0, 0x0);
1077 }
1078 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1,
1079 B_ASSIGN_SBD_OPT_EN_V1, 0x1, phy_idx);
1080 }
1081
__rtw8852bx_bb_reset_all(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1082 static void __rtw8852bx_bb_reset_all(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1083 {
1084 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1085 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1086 fsleep(1);
1087 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1088 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
1089 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1090 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1091 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1092 }
1093
rtw8852bx_bb_macid_ctrl_init(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1094 static void rtw8852bx_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
1095 enum rtw89_phy_idx phy_idx)
1096 {
1097 u32 addr;
1098
1099 for (addr = R_AX_PWR_MACID_LMT_TABLE0;
1100 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4)
1101 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
1102 }
1103
__rtw8852bx_bb_sethw(struct rtw89_dev * rtwdev)1104 static void __rtw8852bx_bb_sethw(struct rtw89_dev *rtwdev)
1105 {
1106 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1107
1108 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP);
1109 rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP);
1110
1111 rtw8852bx_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
1112
1113 /* read these registers after loading BB parameters */
1114 gain->offset_base[RTW89_PHY_0] =
1115 rtw89_phy_read32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK);
1116 gain->rssi_base[RTW89_PHY_0] =
1117 rtw89_phy_read32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK);
1118 }
1119
rtw8852bx_bb_set_pop(struct rtw89_dev * rtwdev)1120 static void rtw8852bx_bb_set_pop(struct rtw89_dev *rtwdev)
1121 {
1122 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)
1123 rtw89_phy_write32_clr(rtwdev, R_PKT_CTRL, B_PKT_POP_EN);
1124 }
1125
rtw8852bt_spur_freq(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)1126 static u32 rtw8852bt_spur_freq(struct rtw89_dev *rtwdev,
1127 const struct rtw89_chan *chan)
1128 {
1129 u8 center_chan = chan->channel;
1130
1131 switch (chan->band_type) {
1132 case RTW89_BAND_5G:
1133 if (center_chan == 151 || center_chan == 153 ||
1134 center_chan == 155 || center_chan == 163)
1135 return 5760;
1136 break;
1137 default:
1138 break;
1139 }
1140
1141 return 0;
1142 }
1143
1144 #define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */
1145 #define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */
1146 #define MAX_TONE_NUM 2048
1147
rtw8852bt_set_csi_tone_idx(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1148 static void rtw8852bt_set_csi_tone_idx(struct rtw89_dev *rtwdev,
1149 const struct rtw89_chan *chan,
1150 enum rtw89_phy_idx phy_idx)
1151 {
1152 s32 freq_diff, csi_idx, csi_tone_idx;
1153 u32 spur_freq;
1154
1155 spur_freq = rtw8852bt_spur_freq(rtwdev, chan);
1156 if (spur_freq == 0) {
1157 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN,
1158 0, phy_idx);
1159 return;
1160 }
1161
1162 freq_diff = (spur_freq - chan->freq) * 1000000;
1163 csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125);
1164 s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx);
1165
1166 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_V1, B_SEG0CSI_IDX,
1167 csi_tone_idx, phy_idx);
1168 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN, 1, phy_idx);
1169 }
1170
1171 static
__rtw8852bx_set_channel_bb(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1172 void __rtw8852bx_set_channel_bb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
1173 enum rtw89_phy_idx phy_idx)
1174 {
1175 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
1176 bool cck_en = chan->channel <= 14;
1177 u8 pri_ch_idx = chan->pri_ch_idx;
1178 u8 band = chan->band_type, chan_idx;
1179
1180 if (cck_en)
1181 rtw8852bx_ctrl_sco_cck(rtwdev, chan->primary_channel);
1182
1183 rtw8852bx_ctrl_ch(rtwdev, chan, phy_idx);
1184 rtw8852bx_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx);
1185 rtw8852bx_ctrl_cck_en(rtwdev, cck_en);
1186 if (chip_id == RTL8852BT)
1187 rtw8852bt_set_csi_tone_idx(rtwdev, chan, phy_idx);
1188 if (chip_id == RTL8852B && chan->band_type == RTW89_BAND_5G) {
1189 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1190 B_PATH0_BT_SHARE_V1, 0x0);
1191 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1192 B_PATH0_BTG_PATH_V1, 0x0);
1193 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1,
1194 B_PATH1_BT_SHARE_V1, 0x0);
1195 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1,
1196 B_PATH1_BTG_PATH_V1, 0x0);
1197 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
1198 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
1199 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1200 B_BT_DYN_DC_EST_EN_MSK, 0x0);
1201 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
1202 }
1203 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band);
1204 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx);
1205 rtw8852bx_5m_mask(rtwdev, chan, phy_idx);
1206 rtw8852bx_bb_set_pop(rtwdev);
1207 __rtw8852bx_bb_reset_all(rtwdev, phy_idx);
1208 }
1209
rtw8852bx_bb_cal_txpwr_ref(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,s16 ref)1210 static u32 rtw8852bx_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
1211 enum rtw89_phy_idx phy_idx, s16 ref)
1212 {
1213 const u16 tssi_16dbm_cw = 0x12c;
1214 const u8 base_cw_0db = 0x27;
1215 const s8 ofst_int = 0;
1216 s16 pwr_s10_3;
1217 s16 rf_pwr_cw;
1218 u16 bb_pwr_cw;
1219 u32 pwr_cw;
1220 u32 tssi_ofst_cw;
1221
1222 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3);
1223 bb_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(2, 0));
1224 rf_pwr_cw = u16_get_bits(pwr_s10_3, GENMASK(8, 3));
1225 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63);
1226 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw;
1227
1228 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3));
1229 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1230 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n",
1231 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw);
1232
1233 return u32_encode_bits(tssi_ofst_cw, B_DPD_TSSI_CW) |
1234 u32_encode_bits(pwr_cw, B_DPD_PWR_CW) |
1235 u32_encode_bits(ref, B_DPD_REF);
1236 }
1237
rtw8852bx_set_txpwr_ref(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1238 static void rtw8852bx_set_txpwr_ref(struct rtw89_dev *rtwdev,
1239 enum rtw89_phy_idx phy_idx)
1240 {
1241 static const u32 addr[RF_PATH_NUM_8852BX] = {0x5800, 0x7800};
1242 const u32 mask = B_DPD_TSSI_CW | B_DPD_PWR_CW | B_DPD_REF;
1243 const u8 ofst_ofdm = 0x4;
1244 const u8 ofst_cck = 0x8;
1245 const s16 ref_ofdm = 0;
1246 const s16 ref_cck = 0;
1247 u32 val;
1248 u8 i;
1249
1250 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
1251
1252 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
1253 B_AX_PWR_REF, 0x0);
1254
1255 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n");
1256 val = rtw8852bx_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm);
1257
1258 for (i = 0; i < RF_PATH_NUM_8852BX; i++)
1259 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val,
1260 phy_idx);
1261
1262 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n");
1263 val = rtw8852bx_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck);
1264
1265 for (i = 0; i < RF_PATH_NUM_8852BX; i++)
1266 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val,
1267 phy_idx);
1268 }
1269
rtw8852bx_bb_set_tx_shape_dfir(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,u8 tx_shape_idx,enum rtw89_phy_idx phy_idx)1270 static void rtw8852bx_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev,
1271 const struct rtw89_chan *chan,
1272 u8 tx_shape_idx,
1273 enum rtw89_phy_idx phy_idx)
1274 {
1275 #define __DFIR_CFG_ADDR(i) (R_TXFIR0 + ((i) << 2))
1276 #define __DFIR_CFG_MASK 0xffffffff
1277 #define __DFIR_CFG_NR 8
1278 #define __DECL_DFIR_PARAM(_name, _val...) \
1279 static const u32 param_ ## _name[] = {_val}; \
1280 static_assert(ARRAY_SIZE(param_ ## _name) == __DFIR_CFG_NR)
1281
1282 __DECL_DFIR_PARAM(flat,
1283 0x023D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053,
1284 0x00F86F9A, 0x06FAEF92, 0x00FE5FCC, 0x00FFDFF5);
1285 __DECL_DFIR_PARAM(sharp,
1286 0x023D83FF, 0x002C636A, 0x0013F204, 0x00008090,
1287 0x00F87FB0, 0x06F99F83, 0x00FDBFBA, 0x00003FF5);
1288 __DECL_DFIR_PARAM(sharp_14,
1289 0x023B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E,
1290 0x00FD8F92, 0x0602D011, 0x0001C02C, 0x00FFF00A);
1291 u8 ch = chan->channel;
1292 const u32 *param;
1293 u32 addr;
1294 int i;
1295
1296 if (ch > 14) {
1297 rtw89_warn(rtwdev,
1298 "set tx shape dfir by unknown ch: %d on 2G\n", ch);
1299 return;
1300 }
1301
1302 if (ch == 14)
1303 param = param_sharp_14;
1304 else
1305 param = tx_shape_idx == 0 ? param_flat : param_sharp;
1306
1307 for (i = 0; i < __DFIR_CFG_NR; i++) {
1308 addr = __DFIR_CFG_ADDR(i);
1309 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1310 "set tx shape dfir: 0x%x: 0x%x\n", addr, param[i]);
1311 rtw89_phy_write32_idx(rtwdev, addr, __DFIR_CFG_MASK, param[i],
1312 phy_idx);
1313 }
1314
1315 #undef __DECL_DFIR_PARAM
1316 #undef __DFIR_CFG_NR
1317 #undef __DFIR_CFG_MASK
1318 #undef __DECL_CFG_ADDR
1319 }
1320
rtw8852bx_set_tx_shape(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1321 static void rtw8852bx_set_tx_shape(struct rtw89_dev *rtwdev,
1322 const struct rtw89_chan *chan,
1323 enum rtw89_phy_idx phy_idx)
1324 {
1325 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
1326 u8 band = chan->band_type;
1327 u8 regd = rtw89_regd_get(rtwdev, band);
1328 u8 tx_shape_cck = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_CCK][regd];
1329 u8 tx_shape_ofdm = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_OFDM][regd];
1330
1331 if (band == RTW89_BAND_2G)
1332 rtw8852bx_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx);
1333
1334 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG,
1335 tx_shape_ofdm);
1336 }
1337
__rtw8852bx_set_txpwr(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1338 static void __rtw8852bx_set_txpwr(struct rtw89_dev *rtwdev,
1339 const struct rtw89_chan *chan,
1340 enum rtw89_phy_idx phy_idx)
1341 {
1342 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
1343 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
1344 rtw8852bx_set_tx_shape(rtwdev, chan, phy_idx);
1345 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
1346 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
1347 }
1348
__rtw8852bx_set_txpwr_ctrl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1349 static void __rtw8852bx_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
1350 enum rtw89_phy_idx phy_idx)
1351 {
1352 rtw8852bx_set_txpwr_ref(rtwdev, phy_idx);
1353 }
1354
1355 static
__rtw8852bx_set_txpwr_ul_tb_offset(struct rtw89_dev * rtwdev,s8 pw_ofst,enum rtw89_mac_idx mac_idx)1356 void __rtw8852bx_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
1357 s8 pw_ofst, enum rtw89_mac_idx mac_idx)
1358 {
1359 u32 reg;
1360
1361 if (pw_ofst < -16 || pw_ofst > 15) {
1362 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst);
1363 return;
1364 }
1365
1366 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx);
1367 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN);
1368
1369 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx);
1370 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst);
1371
1372 pw_ofst = max_t(s8, pw_ofst - 3, -16);
1373 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx);
1374 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, pw_ofst);
1375 }
1376
1377 static int
__rtw8852bx_init_txpwr_unit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1378 __rtw8852bx_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1379 {
1380 int ret;
1381
1382 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
1383 if (ret)
1384 return ret;
1385
1386 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000);
1387 if (ret)
1388 return ret;
1389
1390 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
1391 if (ret)
1392 return ret;
1393
1394 rtw8852bx_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ?
1395 RTW89_MAC_1 : RTW89_MAC_0);
1396
1397 return 0;
1398 }
1399
1400 static
__rtw8852bx_bb_set_plcp_tx(struct rtw89_dev * rtwdev)1401 void __rtw8852bx_bb_set_plcp_tx(struct rtw89_dev *rtwdev)
1402 {
1403 const struct rtw89_reg3_def *def = rtw8852bx_pmac_ht20_mcs7_tbl;
1404 u8 i;
1405
1406 for (i = 0; i < ARRAY_SIZE(rtw8852bx_pmac_ht20_mcs7_tbl); i++, def++)
1407 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data);
1408 }
1409
rtw8852bx_stop_pmac_tx(struct rtw89_dev * rtwdev,struct rtw8852bx_bb_pmac_info * tx_info,enum rtw89_phy_idx idx)1410 static void rtw8852bx_stop_pmac_tx(struct rtw89_dev *rtwdev,
1411 struct rtw8852bx_bb_pmac_info *tx_info,
1412 enum rtw89_phy_idx idx)
1413 {
1414 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx");
1415 if (tx_info->mode == CONT_TX)
1416 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0, idx);
1417 else if (tx_info->mode == PKTS_TX)
1418 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0, idx);
1419 }
1420
rtw8852bx_start_pmac_tx(struct rtw89_dev * rtwdev,struct rtw8852bx_bb_pmac_info * tx_info,enum rtw89_phy_idx idx)1421 static void rtw8852bx_start_pmac_tx(struct rtw89_dev *rtwdev,
1422 struct rtw8852bx_bb_pmac_info *tx_info,
1423 enum rtw89_phy_idx idx)
1424 {
1425 enum rtw8852bx_pmac_mode mode = tx_info->mode;
1426 u32 pkt_cnt = tx_info->tx_cnt;
1427 u16 period = tx_info->period;
1428
1429 if (mode == CONT_TX && !tx_info->is_cck) {
1430 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1, idx);
1431 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start");
1432 } else if (mode == PKTS_TX) {
1433 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1, idx);
1434 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD,
1435 B_PMAC_TX_PRD_MSK, period, idx);
1436 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK,
1437 pkt_cnt, idx);
1438 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start");
1439 }
1440
1441 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx);
1442 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx);
1443 }
1444
1445 static
rtw8852bx_bb_set_pmac_tx(struct rtw89_dev * rtwdev,struct rtw8852bx_bb_pmac_info * tx_info,enum rtw89_phy_idx idx,const struct rtw89_chan * chan)1446 void rtw8852bx_bb_set_pmac_tx(struct rtw89_dev *rtwdev,
1447 struct rtw8852bx_bb_pmac_info *tx_info,
1448 enum rtw89_phy_idx idx, const struct rtw89_chan *chan)
1449 {
1450 if (!tx_info->en_pmac_tx) {
1451 rtw8852bx_stop_pmac_tx(rtwdev, tx_info, idx);
1452 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx);
1453 if (chan->band_type == RTW89_BAND_2G)
1454 rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS);
1455 return;
1456 }
1457
1458 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable");
1459
1460 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx);
1461 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx);
1462 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f, idx);
1463 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx);
1464 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx);
1465 rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS);
1466 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx);
1467
1468 rtw8852bx_start_pmac_tx(rtwdev, tx_info, idx);
1469 }
1470
1471 static
__rtw8852bx_bb_set_pmac_pkt_tx(struct rtw89_dev * rtwdev,u8 enable,u16 tx_cnt,u16 period,u16 tx_time,enum rtw89_phy_idx idx,const struct rtw89_chan * chan)1472 void __rtw8852bx_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable,
1473 u16 tx_cnt, u16 period, u16 tx_time,
1474 enum rtw89_phy_idx idx, const struct rtw89_chan *chan)
1475 {
1476 struct rtw8852bx_bb_pmac_info tx_info = {0};
1477
1478 tx_info.en_pmac_tx = enable;
1479 tx_info.is_cck = 0;
1480 tx_info.mode = PKTS_TX;
1481 tx_info.tx_cnt = tx_cnt;
1482 tx_info.period = period;
1483 tx_info.tx_time = tx_time;
1484
1485 rtw8852bx_bb_set_pmac_tx(rtwdev, &tx_info, idx, chan);
1486 }
1487
1488 static
__rtw8852bx_bb_set_power(struct rtw89_dev * rtwdev,s16 pwr_dbm,enum rtw89_phy_idx idx)1489 void __rtw8852bx_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm,
1490 enum rtw89_phy_idx idx)
1491 {
1492 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm);
1493
1494 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx);
1495 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx);
1496 }
1497
1498 static
__rtw8852bx_bb_cfg_tx_path(struct rtw89_dev * rtwdev,u8 tx_path)1499 void __rtw8852bx_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path)
1500 {
1501 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0);
1502
1503 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path);
1504
1505 if (tx_path == RF_PATH_A) {
1506 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 1);
1507 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0);
1508 } else if (tx_path == RF_PATH_B) {
1509 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2);
1510 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0);
1511 } else if (tx_path == RF_PATH_AB) {
1512 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 3);
1513 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4);
1514 } else {
1515 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path");
1516 }
1517 }
1518
1519 static
__rtw8852bx_bb_tx_mode_switch(struct rtw89_dev * rtwdev,enum rtw89_phy_idx idx,u8 mode)1520 void __rtw8852bx_bb_tx_mode_switch(struct rtw89_dev *rtwdev,
1521 enum rtw89_phy_idx idx, u8 mode)
1522 {
1523 if (mode != 0)
1524 return;
1525
1526 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch");
1527
1528 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx);
1529 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx);
1530 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx);
1531 rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx);
1532 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx);
1533 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx);
1534 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx);
1535 }
1536
1537 static
__rtw8852bx_bb_backup_tssi(struct rtw89_dev * rtwdev,enum rtw89_phy_idx idx,struct rtw8852bx_bb_tssi_bak * bak)1538 void __rtw8852bx_bb_backup_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx,
1539 struct rtw8852bx_bb_tssi_bak *bak)
1540 {
1541 s32 tmp;
1542
1543 bak->tx_path = rtw89_phy_read32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, idx);
1544 bak->rx_path = rtw89_phy_read32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, idx);
1545 bak->p0_rfmode = rtw89_phy_read32_idx(rtwdev, R_P0_RFMODE, MASKDWORD, idx);
1546 bak->p0_rfmode_ftm = rtw89_phy_read32_idx(rtwdev, R_P0_RFMODE_FTM_RX, MASKDWORD, idx);
1547 bak->p1_rfmode = rtw89_phy_read32_idx(rtwdev, R_P1_RFMODE, MASKDWORD, idx);
1548 bak->p1_rfmode_ftm = rtw89_phy_read32_idx(rtwdev, R_P1_RFMODE_FTM_RX, MASKDWORD, idx);
1549 tmp = rtw89_phy_read32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, idx);
1550 bak->tx_pwr = sign_extend32(tmp, 8);
1551 }
1552
1553 static
__rtw8852bx_bb_restore_tssi(struct rtw89_dev * rtwdev,enum rtw89_phy_idx idx,const struct rtw8852bx_bb_tssi_bak * bak)1554 void __rtw8852bx_bb_restore_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx,
1555 const struct rtw8852bx_bb_tssi_bak *bak)
1556 {
1557 rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, bak->tx_path, idx);
1558 if (bak->tx_path == RF_AB)
1559 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0x4);
1560 else
1561 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0x0);
1562 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, bak->rx_path, idx);
1563 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx);
1564 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE, MASKDWORD, bak->p0_rfmode, idx);
1565 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_FTM_RX, MASKDWORD, bak->p0_rfmode_ftm, idx);
1566 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE, MASKDWORD, bak->p1_rfmode, idx);
1567 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_FTM_RX, MASKDWORD, bak->p1_rfmode_ftm, idx);
1568 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, bak->tx_pwr, idx);
1569 }
1570
__rtw8852bx_ctrl_nbtg_bt_tx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)1571 static void __rtw8852bx_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
1572 enum rtw89_phy_idx phy_idx)
1573 {
1574 rtw89_phy_write_reg3_tbl(rtwdev, en ? &rtw8852bx_btc_preagc_en_defs_tbl :
1575 &rtw8852bx_btc_preagc_dis_defs_tbl);
1576 }
1577
__rtw8852bx_ctrl_btg_bt_rx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)1578 static void __rtw8852bx_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
1579 enum rtw89_phy_idx phy_idx)
1580 {
1581 if (en) {
1582 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1583 B_PATH0_BT_SHARE_V1, 0x1);
1584 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1585 B_PATH0_BTG_PATH_V1, 0x0);
1586 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
1587 B_PATH1_G_LNA6_OP1DB_V1, 0x20);
1588 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
1589 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x30);
1590 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1,
1591 B_PATH1_BT_SHARE_V1, 0x1);
1592 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1,
1593 B_PATH1_BTG_PATH_V1, 0x1);
1594 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);
1595 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x1);
1596 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x2);
1597 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1598 B_BT_DYN_DC_EST_EN_MSK, 0x1);
1599 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x1);
1600 } else {
1601 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1602 B_PATH0_BT_SHARE_V1, 0x0);
1603 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1604 B_PATH0_BTG_PATH_V1, 0x0);
1605 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
1606 B_PATH1_G_LNA6_OP1DB_V1, 0x1a);
1607 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
1608 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a);
1609 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1,
1610 B_PATH1_BT_SHARE_V1, 0x0);
1611 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1,
1612 B_PATH1_BTG_PATH_V1, 0x0);
1613 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xc);
1614 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
1615 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
1616 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1617 B_BT_DYN_DC_EST_EN_MSK, 0x1);
1618 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
1619 }
1620 }
1621
1622 static
__rtw8852bx_bb_ctrl_rx_path(struct rtw89_dev * rtwdev,enum rtw89_rf_path_bit rx_path,const struct rtw89_chan * chan)1623 void __rtw8852bx_bb_ctrl_rx_path(struct rtw89_dev *rtwdev,
1624 enum rtw89_rf_path_bit rx_path,
1625 const struct rtw89_chan *chan)
1626 {
1627 u32 rst_mask0;
1628 u32 rst_mask1;
1629
1630 if (rx_path == RF_A) {
1631 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 1);
1632 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 1);
1633 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 1);
1634 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
1635 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
1636 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4);
1637 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
1638 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
1639 } else if (rx_path == RF_B) {
1640 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 2);
1641 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 2);
1642 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 2);
1643 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
1644 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
1645 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4);
1646 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
1647 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
1648 } else if (rx_path == RF_AB) {
1649 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 3);
1650 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 3);
1651 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 3);
1652 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1);
1653 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1);
1654 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4);
1655 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1);
1656 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1);
1657 }
1658
1659 rtw8852bx_set_gain_offset(rtwdev, chan->subband_type, RTW89_PHY_0);
1660
1661 if (chan->band_type == RTW89_BAND_2G &&
1662 (rx_path == RF_B || rx_path == RF_AB))
1663 rtw8852bx_ctrl_btg_bt_rx(rtwdev, true, RTW89_PHY_0);
1664 else
1665 rtw8852bx_ctrl_btg_bt_rx(rtwdev, false, RTW89_PHY_0);
1666
1667 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI;
1668 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI;
1669 if (rx_path == RF_A) {
1670 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1);
1671 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3);
1672 } else {
1673 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1);
1674 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3);
1675 }
1676 }
1677
rtw8852bx_bb_ctrl_rf_mode_rx_path(struct rtw89_dev * rtwdev,enum rtw89_rf_path_bit rx_path)1678 static void rtw8852bx_bb_ctrl_rf_mode_rx_path(struct rtw89_dev *rtwdev,
1679 enum rtw89_rf_path_bit rx_path)
1680 {
1681 if (rx_path == RF_A) {
1682 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE,
1683 B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1233312);
1684 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX,
1685 B_P0_RFMODE_FTM_RX, 0x333);
1686 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE,
1687 B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1111111);
1688 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX,
1689 B_P1_RFMODE_FTM_RX, 0x111);
1690 } else if (rx_path == RF_B) {
1691 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE,
1692 B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1111111);
1693 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX,
1694 B_P0_RFMODE_FTM_RX, 0x111);
1695 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE,
1696 B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1233312);
1697 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX,
1698 B_P1_RFMODE_FTM_RX, 0x333);
1699 } else if (rx_path == RF_AB) {
1700 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE,
1701 B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1233312);
1702 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX,
1703 B_P0_RFMODE_FTM_RX, 0x333);
1704 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE,
1705 B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1233312);
1706 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX,
1707 B_P1_RFMODE_FTM_RX, 0x333);
1708 }
1709 }
1710
__rtw8852bx_bb_cfg_txrx_path(struct rtw89_dev * rtwdev)1711 static void __rtw8852bx_bb_cfg_txrx_path(struct rtw89_dev *rtwdev)
1712 {
1713 struct rtw89_hal *hal = &rtwdev->hal;
1714 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
1715 enum rtw89_rf_path_bit rx_path = hal->antenna_rx ? hal->antenna_rx : RF_AB;
1716
1717 rtw8852bx_bb_ctrl_rx_path(rtwdev, rx_path, chan);
1718 rtw8852bx_bb_ctrl_rf_mode_rx_path(rtwdev, rx_path);
1719
1720 if (rtwdev->hal.rx_nss == 1) {
1721 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
1722 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
1723 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
1724 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
1725 } else {
1726 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1);
1727 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1);
1728 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1);
1729 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1);
1730 }
1731
1732 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0);
1733 }
1734
__rtw8852bx_get_thermal(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path)1735 static u8 __rtw8852bx_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
1736 {
1737 if (rtwdev->is_tssi_mode[rf_path]) {
1738 u32 addr = 0x1c10 + (rf_path << 13);
1739
1740 return rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000);
1741 }
1742
1743 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1744 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
1745 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1746
1747 fsleep(200);
1748
1749 return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
1750 }
1751
1752 static
rtw8852bx_set_trx_mask(struct rtw89_dev * rtwdev,u8 path,u8 group,u32 val)1753 void rtw8852bx_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
1754 {
1755 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000);
1756 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group);
1757 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
1758 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0);
1759 }
1760
__rtw8852bx_btc_init_cfg(struct rtw89_dev * rtwdev)1761 static void __rtw8852bx_btc_init_cfg(struct rtw89_dev *rtwdev)
1762 {
1763 struct rtw89_btc *btc = &rtwdev->btc;
1764 const struct rtw89_chip_info *chip = rtwdev->chip;
1765 const struct rtw89_mac_ax_coex coex_params = {
1766 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE,
1767 .direction = RTW89_MAC_AX_COEX_INNER,
1768 };
1769
1770 /* PTA init */
1771 rtw89_mac_coex_init(rtwdev, &coex_params);
1772
1773 /* set WL Tx response = Hi-Pri */
1774 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
1775 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
1776
1777 /* set rf gnt debug off */
1778 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, RFREG_MASK, 0x0);
1779 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0);
1780
1781 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */
1782 if (btc->ant_type == BTC_ANT_SHARED) {
1783 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff);
1784 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff);
1785 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */
1786 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff);
1787 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_TX_GROUP, 0x55f);
1788 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */
1789 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_SS_GROUP, 0x5df);
1790 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_SS_GROUP, 0x5df);
1791 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff);
1792 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_TX_GROUP, 0x5ff);
1793 }
1794
1795 if (rtwdev->chip->chip_id == RTL8852BT) {
1796 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_RX_GROUP, 0x5df);
1797 rtw8852bx_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_RX_GROUP, 0x5df);
1798 }
1799
1800 /* set PTA break table */
1801 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM);
1802
1803 /* enable BT counter 0xda40[16,2] = 2b'11 */
1804 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN);
1805 btc->cx.wl.status.map.init_ok = true;
1806 }
1807
1808 static
__rtw8852bx_btc_set_wl_pri(struct rtw89_dev * rtwdev,u8 map,bool state)1809 void __rtw8852bx_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
1810 {
1811 u32 bitmap;
1812 u32 reg;
1813
1814 switch (map) {
1815 case BTC_PRI_MASK_TX_RESP:
1816 reg = R_BTC_BT_COEX_MSK_TABLE;
1817 bitmap = B_BTC_PRI_MASK_TX_RESP_V1;
1818 break;
1819 case BTC_PRI_MASK_BEACON:
1820 reg = R_AX_WL_PRI_MSK;
1821 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ;
1822 break;
1823 case BTC_PRI_MASK_RX_CCK:
1824 reg = R_BTC_BT_COEX_MSK_TABLE;
1825 bitmap = B_BTC_PRI_MASK_RXCCK_V1;
1826 break;
1827 default:
1828 return;
1829 }
1830
1831 if (state)
1832 rtw89_write32_set(rtwdev, reg, bitmap);
1833 else
1834 rtw89_write32_clr(rtwdev, reg, bitmap);
1835 }
1836
1837 static
__rtw8852bx_btc_get_bt_rssi(struct rtw89_dev * rtwdev,s8 val)1838 s8 __rtw8852bx_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
1839 {
1840 /* +6 for compensate offset */
1841 return clamp_t(s8, val + 6, -100, 0) + 100;
1842 }
1843
1844 static
__rtw8852bx_btc_update_bt_cnt(struct rtw89_dev * rtwdev)1845 void __rtw8852bx_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
1846 {
1847 /* Feature move to firmware */
1848 }
1849
__rtw8852bx_btc_wl_s1_standby(struct rtw89_dev * rtwdev,bool state)1850 static void __rtw8852bx_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
1851 {
1852 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000);
1853 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
1854 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x31);
1855
1856 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */
1857 if (state)
1858 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x179);
1859 else
1860 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x20);
1861
1862 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
1863 }
1864
rtw8852bx_btc_set_wl_lna2(struct rtw89_dev * rtwdev,u8 level)1865 static void rtw8852bx_btc_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level)
1866 {
1867 switch (level) {
1868 case 0: /* default */
1869 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000);
1870 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0);
1871 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
1872 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
1873 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17);
1874 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2);
1875 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
1876 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3);
1877 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17);
1878 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
1879 break;
1880 case 1: /* Fix LNA2=5 */
1881 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000);
1882 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0);
1883 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
1884 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
1885 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5);
1886 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2);
1887 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
1888 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3);
1889 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5);
1890 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
1891 break;
1892 }
1893 }
1894
__rtw8852bx_btc_set_wl_rx_gain(struct rtw89_dev * rtwdev,u32 level)1895 static void __rtw8852bx_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
1896 {
1897 struct rtw89_btc *btc = &rtwdev->btc;
1898
1899 switch (level) {
1900 case 0: /* original */
1901 default:
1902 rtw8852bx_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0);
1903 btc->dm.wl_lna2 = 0;
1904 break;
1905 case 1: /* for FDD free-run */
1906 rtw8852bx_ctrl_nbtg_bt_tx(rtwdev, true, RTW89_PHY_0);
1907 btc->dm.wl_lna2 = 0;
1908 break;
1909 case 2: /* for BTG Co-Rx*/
1910 rtw8852bx_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0);
1911 btc->dm.wl_lna2 = 1;
1912 break;
1913 }
1914
1915 rtw8852bx_btc_set_wl_lna2(rtwdev, btc->dm.wl_lna2);
1916 }
1917
rtw8852bx_fill_freq_with_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)1918 static void rtw8852bx_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
1919 struct rtw89_rx_phy_ppdu *phy_ppdu,
1920 struct ieee80211_rx_status *status)
1921 {
1922 u16 chan = phy_ppdu->chan_idx;
1923 enum nl80211_band band;
1924 u8 ch;
1925
1926 if (chan == 0)
1927 return;
1928
1929 rtw89_decode_chan_idx(rtwdev, chan, &ch, &band);
1930 status->freq = ieee80211_channel_to_frequency(ch, band);
1931 status->band = band;
1932 }
1933
__rtw8852bx_query_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)1934 static void __rtw8852bx_query_ppdu(struct rtw89_dev *rtwdev,
1935 struct rtw89_rx_phy_ppdu *phy_ppdu,
1936 struct ieee80211_rx_status *status)
1937 {
1938 u8 path;
1939 u8 *rx_power = phy_ppdu->rssi;
1940
1941 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], rx_power[RF_PATH_B]));
1942 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
1943 status->chains |= BIT(path);
1944 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]);
1945 }
1946 if (phy_ppdu->valid)
1947 rtw8852bx_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
1948 }
1949
__rtw8852bx_convert_rpl_to_rssi(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)1950 static void __rtw8852bx_convert_rpl_to_rssi(struct rtw89_dev *rtwdev,
1951 struct rtw89_rx_phy_ppdu *phy_ppdu)
1952 {
1953 u8 delta = phy_ppdu->rpl_avg - phy_ppdu->rssi_avg;
1954 u8 *rssi = phy_ppdu->rssi;
1955 u8 i;
1956
1957 for (i = 0; i < RF_PATH_NUM_8852BX; i++)
1958 rssi[i] += delta;
1959
1960 phy_ppdu->rssi_avg = phy_ppdu->rpl_avg;
1961 }
1962
__rtw8852bx_mac_enable_bb_rf(struct rtw89_dev * rtwdev)1963 static int __rtw8852bx_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
1964 {
1965 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
1966 u32 val32;
1967 int ret;
1968
1969 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,
1970 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
1971 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x1);
1972 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
1973 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
1974 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
1975
1976 if (chip_id == RTL8852BT) {
1977 val32 = rtw89_read32(rtwdev, R_AX_AFE_OFF_CTRL1);
1978 val32 = u32_replace_bits(val32, 0x1, B_AX_S0_LDO_VSEL_F_MASK);
1979 val32 = u32_replace_bits(val32, 0x1, B_AX_S1_LDO_VSEL_F_MASK);
1980 rtw89_write32(rtwdev, R_AX_AFE_OFF_CTRL1, val32);
1981 }
1982
1983 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xC7,
1984 FULL_BIT_MASK);
1985 if (ret)
1986 return ret;
1987
1988 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xC7,
1989 FULL_BIT_MASK);
1990 if (ret)
1991 return ret;
1992
1993 rtw89_write8(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_XYN_CYCLE);
1994
1995 return 0;
1996 }
1997
__rtw8852bx_mac_disable_bb_rf(struct rtw89_dev * rtwdev)1998 static int __rtw8852bx_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
1999 {
2000 u8 wl_rfc_s0;
2001 u8 wl_rfc_s1;
2002 int ret;
2003
2004 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2005 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,
2006 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
2007
2008 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, &wl_rfc_s0);
2009 if (ret)
2010 return ret;
2011 wl_rfc_s0 &= ~XTAL_SI_RF00S_EN;
2012 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, wl_rfc_s0,
2013 FULL_BIT_MASK);
2014 if (ret)
2015 return ret;
2016
2017 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, &wl_rfc_s1);
2018 if (ret)
2019 return ret;
2020 wl_rfc_s1 &= ~XTAL_SI_RF10S_EN;
2021 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, wl_rfc_s1,
2022 FULL_BIT_MASK);
2023 return ret;
2024 }
2025
2026 const struct rtw8852bx_info rtw8852bx_info = {
2027 .mac_enable_bb_rf = __rtw8852bx_mac_enable_bb_rf,
2028 .mac_disable_bb_rf = __rtw8852bx_mac_disable_bb_rf,
2029 .bb_sethw = __rtw8852bx_bb_sethw,
2030 .bb_reset_all = __rtw8852bx_bb_reset_all,
2031 .bb_cfg_txrx_path = __rtw8852bx_bb_cfg_txrx_path,
2032 .bb_cfg_tx_path = __rtw8852bx_bb_cfg_tx_path,
2033 .bb_ctrl_rx_path = __rtw8852bx_bb_ctrl_rx_path,
2034 .bb_set_plcp_tx = __rtw8852bx_bb_set_plcp_tx,
2035 .bb_set_power = __rtw8852bx_bb_set_power,
2036 .bb_set_pmac_pkt_tx = __rtw8852bx_bb_set_pmac_pkt_tx,
2037 .bb_backup_tssi = __rtw8852bx_bb_backup_tssi,
2038 .bb_restore_tssi = __rtw8852bx_bb_restore_tssi,
2039 .bb_tx_mode_switch = __rtw8852bx_bb_tx_mode_switch,
2040 .set_channel_mac = __rtw8852bx_set_channel_mac,
2041 .set_channel_bb = __rtw8852bx_set_channel_bb,
2042 .ctrl_nbtg_bt_tx = __rtw8852bx_ctrl_nbtg_bt_tx,
2043 .ctrl_btg_bt_rx = __rtw8852bx_ctrl_btg_bt_rx,
2044 .query_ppdu = __rtw8852bx_query_ppdu,
2045 .convert_rpl_to_rssi = __rtw8852bx_convert_rpl_to_rssi,
2046 .read_efuse = __rtw8852bx_read_efuse,
2047 .read_phycap = __rtw8852bx_read_phycap,
2048 .power_trim = __rtw8852bx_power_trim,
2049 .set_txpwr = __rtw8852bx_set_txpwr,
2050 .set_txpwr_ctrl = __rtw8852bx_set_txpwr_ctrl,
2051 .init_txpwr_unit = __rtw8852bx_init_txpwr_unit,
2052 .set_txpwr_ul_tb_offset = __rtw8852bx_set_txpwr_ul_tb_offset,
2053 .get_thermal = __rtw8852bx_get_thermal,
2054 .adc_cfg = rtw8852bt_adc_cfg,
2055 .btc_init_cfg = __rtw8852bx_btc_init_cfg,
2056 .btc_set_wl_pri = __rtw8852bx_btc_set_wl_pri,
2057 .btc_get_bt_rssi = __rtw8852bx_btc_get_bt_rssi,
2058 .btc_update_bt_cnt = __rtw8852bx_btc_update_bt_cnt,
2059 .btc_wl_s1_standby = __rtw8852bx_btc_wl_s1_standby,
2060 .btc_set_wl_rx_gain = __rtw8852bx_btc_set_wl_rx_gain,
2061 };
2062 EXPORT_SYMBOL(rtw8852bx_info);
2063
2064 MODULE_AUTHOR("Realtek Corporation");
2065 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852B common routines");
2066 MODULE_LICENSE("Dual BSD/GPL");
2067