1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2005-2014, 2018-2026 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2015-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/devcoredump.h> 8 #include "iwl-drv.h" 9 #include "runtime.h" 10 #include "dbg.h" 11 #include "debugfs.h" 12 #include "iwl-io.h" 13 #include "iwl-prph.h" 14 #include "iwl-csr.h" 15 #include "iwl-fh.h" 16 17 /** 18 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump 19 * 20 * @fwrt_ptr: pointer to the buffer coming from fwrt 21 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the 22 * transport's data. 23 * @fwrt_len: length of the valid data in fwrt_ptr 24 */ 25 struct iwl_fw_dump_ptrs { 26 struct iwl_trans_dump_data *trans_ptr; 27 void *fwrt_ptr; 28 u32 fwrt_len; 29 }; 30 31 #define RADIO_REG_MAX_READ 0x2ad 32 static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt, 33 struct iwl_fw_error_dump_data **dump_data) 34 { 35 u8 *pos = (void *)(*dump_data)->data; 36 int i; 37 38 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n"); 39 40 if (!iwl_trans_grab_nic_access(fwrt->trans)) 41 return; 42 43 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG); 44 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ); 45 46 for (i = 0; i < RADIO_REG_MAX_READ; i++) { 47 u32 rd_cmd = RADIO_RSP_RD_CMD; 48 49 rd_cmd |= i << RADIO_RSP_ADDR_POS; 50 iwl_trans_write_prph(fwrt->trans, RSP_RADIO_CMD, rd_cmd); 51 *pos = (u8)iwl_trans_read_prph(fwrt->trans, RSP_RADIO_RDDAT); 52 53 pos++; 54 } 55 56 *dump_data = iwl_fw_error_next_data(*dump_data); 57 58 iwl_trans_release_nic_access(fwrt->trans); 59 } 60 61 static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt, 62 struct iwl_fw_error_dump_data **dump_data, 63 int size, u32 offset, int fifo_num) 64 { 65 struct iwl_fw_error_dump_fifo *fifo_hdr; 66 u32 *fifo_data; 67 u32 fifo_len; 68 int i; 69 70 fifo_hdr = (void *)(*dump_data)->data; 71 fifo_data = (void *)fifo_hdr->data; 72 fifo_len = size; 73 74 /* No need to try to read the data if the length is 0 */ 75 if (fifo_len == 0) 76 return; 77 78 /* Add a TLV for the RXF */ 79 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF); 80 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 81 82 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 83 fifo_hdr->available_bytes = 84 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 85 RXF_RD_D_SPACE + offset)); 86 fifo_hdr->wr_ptr = 87 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 88 RXF_RD_WR_PTR + offset)); 89 fifo_hdr->rd_ptr = 90 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 91 RXF_RD_RD_PTR + offset)); 92 fifo_hdr->fence_ptr = 93 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 94 RXF_RD_FENCE_PTR + offset)); 95 fifo_hdr->fence_mode = 96 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 97 RXF_SET_FENCE_MODE + offset)); 98 99 /* Lock fence */ 100 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1); 101 /* Set fence pointer to the same place like WR pointer */ 102 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1); 103 /* Set fence offset */ 104 iwl_trans_write_prph(fwrt->trans, 105 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0); 106 107 /* Read FIFO */ 108 fifo_len /= sizeof(u32); /* Size in DWORDS */ 109 for (i = 0; i < fifo_len; i++) 110 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 111 RXF_FIFO_RD_FENCE_INC + 112 offset); 113 *dump_data = iwl_fw_error_next_data(*dump_data); 114 } 115 116 static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt, 117 struct iwl_fw_error_dump_data **dump_data, 118 int size, u32 offset, int fifo_num) 119 { 120 struct iwl_fw_error_dump_fifo *fifo_hdr; 121 u32 *fifo_data; 122 u32 fifo_len; 123 int i; 124 125 fifo_hdr = (void *)(*dump_data)->data; 126 fifo_data = (void *)fifo_hdr->data; 127 fifo_len = size; 128 129 /* No need to try to read the data if the length is 0 */ 130 if (fifo_len == 0) 131 return; 132 133 /* Add a TLV for the FIFO */ 134 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF); 135 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 136 137 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 138 fifo_hdr->available_bytes = 139 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 140 TXF_FIFO_ITEM_CNT + offset)); 141 fifo_hdr->wr_ptr = 142 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 143 TXF_WR_PTR + offset)); 144 fifo_hdr->rd_ptr = 145 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 146 TXF_RD_PTR + offset)); 147 fifo_hdr->fence_ptr = 148 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 149 TXF_FENCE_PTR + offset)); 150 fifo_hdr->fence_mode = 151 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 152 TXF_LOCK_FENCE + offset)); 153 154 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 155 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset, 156 TXF_WR_PTR + offset); 157 158 /* Dummy-read to advance the read pointer to the head */ 159 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset); 160 161 /* Read FIFO */ 162 for (i = 0; i < fifo_len / sizeof(u32); i++) 163 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 164 TXF_READ_MODIFY_DATA + 165 offset); 166 167 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 168 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 169 fifo_data, fifo_len); 170 171 *dump_data = iwl_fw_error_next_data(*dump_data); 172 } 173 174 static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt, 175 struct iwl_fw_error_dump_data **dump_data) 176 { 177 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 178 179 IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n"); 180 181 if (!iwl_trans_grab_nic_access(fwrt->trans)) 182 return; 183 184 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) { 185 /* Pull RXF1 */ 186 iwl_fwrt_dump_rxf(fwrt, dump_data, 187 cfg->lmac[0].rxfifo1_size, 0, 0); 188 /* Pull RXF2 */ 189 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size, 190 RXF_DIFF_FROM_PREV + 191 fwrt->trans->mac_cfg->umac_prph_offset, 1); 192 /* Pull LMAC2 RXF1 */ 193 if (fwrt->smem_cfg.num_lmacs > 1) 194 iwl_fwrt_dump_rxf(fwrt, dump_data, 195 cfg->lmac[1].rxfifo1_size, 196 LMAC2_PRPH_OFFSET, 2); 197 } 198 199 iwl_trans_release_nic_access(fwrt->trans); 200 } 201 202 static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt, 203 struct iwl_fw_error_dump_data **dump_data) 204 { 205 struct iwl_fw_error_dump_fifo *fifo_hdr; 206 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 207 u32 *fifo_data; 208 u32 fifo_len; 209 int i, j; 210 211 IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n"); 212 213 if (!iwl_trans_grab_nic_access(fwrt->trans)) 214 return; 215 216 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) { 217 /* Pull TXF data from LMAC1 */ 218 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) { 219 /* Mark the number of TXF we're pulling now */ 220 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i); 221 iwl_fwrt_dump_txf(fwrt, dump_data, 222 cfg->lmac[0].txfifo_size[i], 0, i); 223 } 224 225 /* Pull TXF data from LMAC2 */ 226 if (fwrt->smem_cfg.num_lmacs > 1) { 227 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; 228 i++) { 229 /* Mark the number of TXF we're pulling now */ 230 iwl_trans_write_prph(fwrt->trans, 231 TXF_LARC_NUM + 232 LMAC2_PRPH_OFFSET, i); 233 iwl_fwrt_dump_txf(fwrt, dump_data, 234 cfg->lmac[1].txfifo_size[i], 235 LMAC2_PRPH_OFFSET, 236 i + cfg->num_txfifo_entries); 237 } 238 } 239 } 240 241 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 242 fw_has_capa(&fwrt->fw->ucode_capa, 243 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) { 244 /* Pull UMAC internal TXF data from all TXFs */ 245 for (i = 0; 246 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size); 247 i++) { 248 fifo_hdr = (void *)(*dump_data)->data; 249 fifo_data = (void *)fifo_hdr->data; 250 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i]; 251 252 /* No need to try to read the data if the length is 0 */ 253 if (fifo_len == 0) 254 continue; 255 256 /* Add a TLV for the internal FIFOs */ 257 (*dump_data)->type = 258 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF); 259 (*dump_data)->len = 260 cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 261 262 fifo_hdr->fifo_num = cpu_to_le32(i); 263 264 /* Mark the number of TXF we're pulling now */ 265 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i + 266 fwrt->smem_cfg.num_txfifo_entries); 267 268 fifo_hdr->available_bytes = 269 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 270 TXF_CPU2_FIFO_ITEM_CNT)); 271 fifo_hdr->wr_ptr = 272 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 273 TXF_CPU2_WR_PTR)); 274 fifo_hdr->rd_ptr = 275 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 276 TXF_CPU2_RD_PTR)); 277 fifo_hdr->fence_ptr = 278 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 279 TXF_CPU2_FENCE_PTR)); 280 fifo_hdr->fence_mode = 281 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 282 TXF_CPU2_LOCK_FENCE)); 283 284 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */ 285 iwl_trans_write_prph(fwrt->trans, 286 TXF_CPU2_READ_MODIFY_ADDR, 287 TXF_CPU2_WR_PTR); 288 289 /* Dummy-read to advance the read pointer to head */ 290 iwl_trans_read_prph(fwrt->trans, 291 TXF_CPU2_READ_MODIFY_DATA); 292 293 /* Read FIFO */ 294 fifo_len /= sizeof(u32); /* Size in DWORDS */ 295 for (j = 0; j < fifo_len; j++) 296 fifo_data[j] = 297 iwl_trans_read_prph(fwrt->trans, 298 TXF_CPU2_READ_MODIFY_DATA); 299 *dump_data = iwl_fw_error_next_data(*dump_data); 300 } 301 } 302 303 iwl_trans_release_nic_access(fwrt->trans); 304 } 305 306 struct iwl_prph_range { 307 u32 start, end; 308 }; 309 310 static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = { 311 { .start = 0x00a00000, .end = 0x00a00000 }, 312 { .start = 0x00a0000c, .end = 0x00a00024 }, 313 { .start = 0x00a0002c, .end = 0x00a0003c }, 314 { .start = 0x00a00410, .end = 0x00a00418 }, 315 { .start = 0x00a00420, .end = 0x00a00420 }, 316 { .start = 0x00a00428, .end = 0x00a00428 }, 317 { .start = 0x00a00430, .end = 0x00a0043c }, 318 { .start = 0x00a00444, .end = 0x00a00444 }, 319 { .start = 0x00a004c0, .end = 0x00a004cc }, 320 { .start = 0x00a004d8, .end = 0x00a004d8 }, 321 { .start = 0x00a004e0, .end = 0x00a004f0 }, 322 { .start = 0x00a00840, .end = 0x00a00840 }, 323 { .start = 0x00a00850, .end = 0x00a00858 }, 324 { .start = 0x00a01004, .end = 0x00a01008 }, 325 { .start = 0x00a01010, .end = 0x00a01010 }, 326 { .start = 0x00a01018, .end = 0x00a01018 }, 327 { .start = 0x00a01024, .end = 0x00a01024 }, 328 { .start = 0x00a0102c, .end = 0x00a01034 }, 329 { .start = 0x00a0103c, .end = 0x00a01040 }, 330 { .start = 0x00a01048, .end = 0x00a01094 }, 331 { .start = 0x00a01c00, .end = 0x00a01c20 }, 332 { .start = 0x00a01c58, .end = 0x00a01c58 }, 333 { .start = 0x00a01c7c, .end = 0x00a01c7c }, 334 { .start = 0x00a01c28, .end = 0x00a01c54 }, 335 { .start = 0x00a01c5c, .end = 0x00a01c5c }, 336 { .start = 0x00a01c60, .end = 0x00a01cdc }, 337 { .start = 0x00a01ce0, .end = 0x00a01d0c }, 338 { .start = 0x00a01d18, .end = 0x00a01d20 }, 339 { .start = 0x00a01d2c, .end = 0x00a01d30 }, 340 { .start = 0x00a01d40, .end = 0x00a01d5c }, 341 { .start = 0x00a01d80, .end = 0x00a01d80 }, 342 { .start = 0x00a01d98, .end = 0x00a01d9c }, 343 { .start = 0x00a01da8, .end = 0x00a01da8 }, 344 { .start = 0x00a01db8, .end = 0x00a01df4 }, 345 { .start = 0x00a01dc0, .end = 0x00a01dfc }, 346 { .start = 0x00a01e00, .end = 0x00a01e2c }, 347 { .start = 0x00a01e40, .end = 0x00a01e60 }, 348 { .start = 0x00a01e68, .end = 0x00a01e6c }, 349 { .start = 0x00a01e74, .end = 0x00a01e74 }, 350 { .start = 0x00a01e84, .end = 0x00a01e90 }, 351 { .start = 0x00a01e9c, .end = 0x00a01ec4 }, 352 { .start = 0x00a01ed0, .end = 0x00a01ee0 }, 353 { .start = 0x00a01f00, .end = 0x00a01f1c }, 354 { .start = 0x00a01f44, .end = 0x00a01ffc }, 355 { .start = 0x00a02000, .end = 0x00a02048 }, 356 { .start = 0x00a02068, .end = 0x00a020f0 }, 357 { .start = 0x00a02100, .end = 0x00a02118 }, 358 { .start = 0x00a02140, .end = 0x00a0214c }, 359 { .start = 0x00a02168, .end = 0x00a0218c }, 360 { .start = 0x00a021c0, .end = 0x00a021c0 }, 361 { .start = 0x00a02400, .end = 0x00a02410 }, 362 { .start = 0x00a02418, .end = 0x00a02420 }, 363 { .start = 0x00a02428, .end = 0x00a0242c }, 364 { .start = 0x00a02434, .end = 0x00a02434 }, 365 { .start = 0x00a02440, .end = 0x00a02460 }, 366 { .start = 0x00a02468, .end = 0x00a024b0 }, 367 { .start = 0x00a024c8, .end = 0x00a024cc }, 368 { .start = 0x00a02500, .end = 0x00a02504 }, 369 { .start = 0x00a0250c, .end = 0x00a02510 }, 370 { .start = 0x00a02540, .end = 0x00a02554 }, 371 { .start = 0x00a02580, .end = 0x00a025f4 }, 372 { .start = 0x00a02600, .end = 0x00a0260c }, 373 { .start = 0x00a02648, .end = 0x00a02650 }, 374 { .start = 0x00a02680, .end = 0x00a02680 }, 375 { .start = 0x00a026c0, .end = 0x00a026d0 }, 376 { .start = 0x00a02700, .end = 0x00a0270c }, 377 { .start = 0x00a02804, .end = 0x00a02804 }, 378 { .start = 0x00a02818, .end = 0x00a0281c }, 379 { .start = 0x00a02c00, .end = 0x00a02db4 }, 380 { .start = 0x00a02df4, .end = 0x00a02fb0 }, 381 { .start = 0x00a03000, .end = 0x00a03014 }, 382 { .start = 0x00a0301c, .end = 0x00a0302c }, 383 { .start = 0x00a03034, .end = 0x00a03038 }, 384 { .start = 0x00a03040, .end = 0x00a03048 }, 385 { .start = 0x00a03060, .end = 0x00a03068 }, 386 { .start = 0x00a03070, .end = 0x00a03074 }, 387 { .start = 0x00a0307c, .end = 0x00a0307c }, 388 { .start = 0x00a03080, .end = 0x00a03084 }, 389 { .start = 0x00a0308c, .end = 0x00a03090 }, 390 { .start = 0x00a03098, .end = 0x00a03098 }, 391 { .start = 0x00a030a0, .end = 0x00a030a0 }, 392 { .start = 0x00a030a8, .end = 0x00a030b4 }, 393 { .start = 0x00a030bc, .end = 0x00a030bc }, 394 { .start = 0x00a030c0, .end = 0x00a0312c }, 395 { .start = 0x00a03c00, .end = 0x00a03c5c }, 396 { .start = 0x00a04400, .end = 0x00a04454 }, 397 { .start = 0x00a04460, .end = 0x00a04474 }, 398 { .start = 0x00a044c0, .end = 0x00a044ec }, 399 { .start = 0x00a04500, .end = 0x00a04504 }, 400 { .start = 0x00a04510, .end = 0x00a04538 }, 401 { .start = 0x00a04540, .end = 0x00a04548 }, 402 { .start = 0x00a04560, .end = 0x00a0457c }, 403 { .start = 0x00a04590, .end = 0x00a04598 }, 404 { .start = 0x00a045c0, .end = 0x00a045f4 }, 405 }; 406 407 static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = { 408 { .start = 0x00a05c00, .end = 0x00a05c18 }, 409 { .start = 0x00a05400, .end = 0x00a056e8 }, 410 { .start = 0x00a08000, .end = 0x00a098bc }, 411 { .start = 0x00a02400, .end = 0x00a02758 }, 412 { .start = 0x00a04764, .end = 0x00a0476c }, 413 { .start = 0x00a04770, .end = 0x00a04774 }, 414 { .start = 0x00a04620, .end = 0x00a04624 }, 415 }; 416 417 static const struct iwl_prph_range iwl_prph_dump_addr_22000[] = { 418 { .start = 0x00a00000, .end = 0x00a00000 }, 419 { .start = 0x00a0000c, .end = 0x00a00024 }, 420 { .start = 0x00a0002c, .end = 0x00a00034 }, 421 { .start = 0x00a0003c, .end = 0x00a0003c }, 422 { .start = 0x00a00410, .end = 0x00a00418 }, 423 { .start = 0x00a00420, .end = 0x00a00420 }, 424 { .start = 0x00a00428, .end = 0x00a00428 }, 425 { .start = 0x00a00430, .end = 0x00a0043c }, 426 { .start = 0x00a00444, .end = 0x00a00444 }, 427 { .start = 0x00a00840, .end = 0x00a00840 }, 428 { .start = 0x00a00850, .end = 0x00a00858 }, 429 { .start = 0x00a01004, .end = 0x00a01008 }, 430 { .start = 0x00a01010, .end = 0x00a01010 }, 431 { .start = 0x00a01018, .end = 0x00a01018 }, 432 { .start = 0x00a01024, .end = 0x00a01024 }, 433 { .start = 0x00a0102c, .end = 0x00a01034 }, 434 { .start = 0x00a0103c, .end = 0x00a01040 }, 435 { .start = 0x00a01048, .end = 0x00a01050 }, 436 { .start = 0x00a01058, .end = 0x00a01058 }, 437 { .start = 0x00a01060, .end = 0x00a01070 }, 438 { .start = 0x00a0108c, .end = 0x00a0108c }, 439 { .start = 0x00a01c20, .end = 0x00a01c28 }, 440 { .start = 0x00a01d10, .end = 0x00a01d10 }, 441 { .start = 0x00a01e28, .end = 0x00a01e2c }, 442 { .start = 0x00a01e60, .end = 0x00a01e60 }, 443 { .start = 0x00a01e80, .end = 0x00a01e80 }, 444 { .start = 0x00a01ea0, .end = 0x00a01ea0 }, 445 { .start = 0x00a02000, .end = 0x00a0201c }, 446 { .start = 0x00a02024, .end = 0x00a02024 }, 447 { .start = 0x00a02040, .end = 0x00a02048 }, 448 { .start = 0x00a020c0, .end = 0x00a020e0 }, 449 { .start = 0x00a02400, .end = 0x00a02404 }, 450 { .start = 0x00a0240c, .end = 0x00a02414 }, 451 { .start = 0x00a0241c, .end = 0x00a0243c }, 452 { .start = 0x00a02448, .end = 0x00a024bc }, 453 { .start = 0x00a024c4, .end = 0x00a024cc }, 454 { .start = 0x00a02508, .end = 0x00a02508 }, 455 { .start = 0x00a02510, .end = 0x00a02514 }, 456 { .start = 0x00a0251c, .end = 0x00a0251c }, 457 { .start = 0x00a0252c, .end = 0x00a0255c }, 458 { .start = 0x00a02564, .end = 0x00a025a0 }, 459 { .start = 0x00a025a8, .end = 0x00a025b4 }, 460 { .start = 0x00a025c0, .end = 0x00a025c0 }, 461 { .start = 0x00a025e8, .end = 0x00a025f4 }, 462 { .start = 0x00a02c08, .end = 0x00a02c18 }, 463 { .start = 0x00a02c2c, .end = 0x00a02c38 }, 464 { .start = 0x00a02c68, .end = 0x00a02c78 }, 465 { .start = 0x00a03000, .end = 0x00a03000 }, 466 { .start = 0x00a03010, .end = 0x00a03014 }, 467 { .start = 0x00a0301c, .end = 0x00a0302c }, 468 { .start = 0x00a03034, .end = 0x00a03038 }, 469 { .start = 0x00a03040, .end = 0x00a03044 }, 470 { .start = 0x00a03060, .end = 0x00a03068 }, 471 { .start = 0x00a03070, .end = 0x00a03070 }, 472 { .start = 0x00a0307c, .end = 0x00a03084 }, 473 { .start = 0x00a0308c, .end = 0x00a03090 }, 474 { .start = 0x00a03098, .end = 0x00a03098 }, 475 { .start = 0x00a030a0, .end = 0x00a030a0 }, 476 { .start = 0x00a030a8, .end = 0x00a030b4 }, 477 { .start = 0x00a030bc, .end = 0x00a030c0 }, 478 { .start = 0x00a030c8, .end = 0x00a030f4 }, 479 { .start = 0x00a03100, .end = 0x00a0312c }, 480 { .start = 0x00a03c00, .end = 0x00a03c5c }, 481 { .start = 0x00a04400, .end = 0x00a04454 }, 482 { .start = 0x00a04460, .end = 0x00a04474 }, 483 { .start = 0x00a044c0, .end = 0x00a044ec }, 484 { .start = 0x00a04500, .end = 0x00a04504 }, 485 { .start = 0x00a04510, .end = 0x00a04538 }, 486 { .start = 0x00a04540, .end = 0x00a04548 }, 487 { .start = 0x00a04560, .end = 0x00a04560 }, 488 { .start = 0x00a04570, .end = 0x00a0457c }, 489 { .start = 0x00a04590, .end = 0x00a04590 }, 490 { .start = 0x00a04598, .end = 0x00a04598 }, 491 { .start = 0x00a045c0, .end = 0x00a045f4 }, 492 { .start = 0x00a05c18, .end = 0x00a05c1c }, 493 { .start = 0x00a0c000, .end = 0x00a0c018 }, 494 { .start = 0x00a0c020, .end = 0x00a0c028 }, 495 { .start = 0x00a0c038, .end = 0x00a0c094 }, 496 { .start = 0x00a0c0c0, .end = 0x00a0c104 }, 497 { .start = 0x00a0c10c, .end = 0x00a0c118 }, 498 { .start = 0x00a0c150, .end = 0x00a0c174 }, 499 { .start = 0x00a0c17c, .end = 0x00a0c188 }, 500 { .start = 0x00a0c190, .end = 0x00a0c198 }, 501 { .start = 0x00a0c1a0, .end = 0x00a0c1a8 }, 502 { .start = 0x00a0c1b0, .end = 0x00a0c1b8 }, 503 }; 504 505 static const struct iwl_prph_range iwl_prph_dump_addr_ax210[] = { 506 { .start = 0x00d03c00, .end = 0x00d03c64 }, 507 { .start = 0x00d05c18, .end = 0x00d05c1c }, 508 { .start = 0x00d0c000, .end = 0x00d0c174 }, 509 }; 510 511 static void iwl_read_prph_block(struct iwl_trans *trans, u32 start, 512 u32 len_bytes, __le32 *data) 513 { 514 u32 i; 515 516 for (i = 0; i < len_bytes; i += 4) 517 *data++ = cpu_to_le32(iwl_trans_read_prph(trans, start + i)); 518 } 519 520 static void iwl_dump_prph(struct iwl_fw_runtime *fwrt, 521 const struct iwl_prph_range *iwl_prph_dump_addr, 522 u32 range_len, void *ptr) 523 { 524 struct iwl_fw_error_dump_prph *prph; 525 struct iwl_trans *trans = fwrt->trans; 526 struct iwl_fw_error_dump_data **data = 527 (struct iwl_fw_error_dump_data **)ptr; 528 u32 i; 529 530 if (!data) 531 return; 532 533 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n"); 534 535 if (!iwl_trans_grab_nic_access(trans)) 536 return; 537 538 for (i = 0; i < range_len; i++) { 539 /* The range includes both boundaries */ 540 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - 541 iwl_prph_dump_addr[i].start + 4; 542 543 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH); 544 (*data)->len = cpu_to_le32(sizeof(*prph) + 545 num_bytes_in_chunk); 546 prph = (void *)(*data)->data; 547 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start); 548 549 iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start, 550 /* our range is inclusive, hence + 4 */ 551 iwl_prph_dump_addr[i].end - 552 iwl_prph_dump_addr[i].start + 4, 553 (void *)prph->data); 554 555 *data = iwl_fw_error_next_data(*data); 556 } 557 558 iwl_trans_release_nic_access(trans); 559 } 560 561 static void iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt, 562 const struct iwl_prph_range *iwl_prph_dump_addr, 563 u32 range_len, void *ptr) 564 { 565 u32 *prph_len = (u32 *)ptr; 566 int i, num_bytes_in_chunk; 567 568 if (!prph_len) 569 return; 570 571 for (i = 0; i < range_len; i++) { 572 /* The range includes both boundaries */ 573 num_bytes_in_chunk = 574 iwl_prph_dump_addr[i].end - 575 iwl_prph_dump_addr[i].start + 4; 576 577 *prph_len += sizeof(struct iwl_fw_error_dump_data) + 578 sizeof(struct iwl_fw_error_dump_prph) + 579 num_bytes_in_chunk; 580 } 581 } 582 583 static void iwl_fw_prph_handler(struct iwl_fw_runtime *fwrt, void *ptr, 584 void (*handler)(struct iwl_fw_runtime *, 585 const struct iwl_prph_range *, 586 u32, void *)) 587 { 588 u32 range_len; 589 590 if (fwrt->trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 591 range_len = ARRAY_SIZE(iwl_prph_dump_addr_ax210); 592 handler(fwrt, iwl_prph_dump_addr_ax210, range_len, ptr); 593 } else if (fwrt->trans->mac_cfg->device_family >= 594 IWL_DEVICE_FAMILY_22000) { 595 range_len = ARRAY_SIZE(iwl_prph_dump_addr_22000); 596 handler(fwrt, iwl_prph_dump_addr_22000, range_len, ptr); 597 } else { 598 range_len = ARRAY_SIZE(iwl_prph_dump_addr_comm); 599 handler(fwrt, iwl_prph_dump_addr_comm, range_len, ptr); 600 601 if (fwrt->trans->mac_cfg->mq_rx_supported) { 602 range_len = ARRAY_SIZE(iwl_prph_dump_addr_9000); 603 handler(fwrt, iwl_prph_dump_addr_9000, range_len, ptr); 604 } 605 } 606 } 607 608 static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt, 609 struct iwl_fw_error_dump_data **dump_data, 610 u32 len, u32 ofs, u32 type) 611 { 612 struct iwl_fw_error_dump_mem *dump_mem; 613 614 if (!len) 615 return; 616 617 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 618 (*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem)); 619 dump_mem = (void *)(*dump_data)->data; 620 dump_mem->type = cpu_to_le32(type); 621 dump_mem->offset = cpu_to_le32(ofs); 622 iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len); 623 *dump_data = iwl_fw_error_next_data(*dump_data); 624 625 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 626 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, ofs, 627 dump_mem->data, len); 628 629 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type); 630 } 631 632 #define ADD_LEN(len, item_len, const_len) \ 633 do {size_t item = item_len; len += (!!item) * const_len + item; } \ 634 while (0) 635 636 static int iwl_fw_rxf_len(struct iwl_fw_runtime *fwrt, 637 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 638 { 639 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 640 sizeof(struct iwl_fw_error_dump_fifo); 641 u32 fifo_len = 0; 642 int i; 643 644 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) 645 return 0; 646 647 /* Count RXF2 size */ 648 ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len); 649 650 /* Count RXF1 sizes */ 651 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 652 mem_cfg->num_lmacs = MAX_NUM_LMAC; 653 654 for (i = 0; i < mem_cfg->num_lmacs; i++) 655 ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len); 656 657 return fifo_len; 658 } 659 660 static int iwl_fw_txf_len(struct iwl_fw_runtime *fwrt, 661 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 662 { 663 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 664 sizeof(struct iwl_fw_error_dump_fifo); 665 u32 fifo_len = 0; 666 int i; 667 668 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) 669 goto dump_internal_txf; 670 671 /* Count TXF sizes */ 672 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 673 mem_cfg->num_lmacs = MAX_NUM_LMAC; 674 675 for (i = 0; i < mem_cfg->num_lmacs; i++) { 676 int j; 677 678 for (j = 0; j < mem_cfg->num_txfifo_entries; j++) 679 ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j], 680 hdr_len); 681 } 682 683 dump_internal_txf: 684 if (!(iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 685 fw_has_capa(&fwrt->fw->ucode_capa, 686 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))) 687 goto out; 688 689 for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++) 690 ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len); 691 692 out: 693 return fifo_len; 694 } 695 696 static void iwl_dump_paging(struct iwl_fw_runtime *fwrt, 697 struct iwl_fw_error_dump_data **data) 698 { 699 int i; 700 701 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n"); 702 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) { 703 struct iwl_fw_error_dump_paging *paging; 704 struct page *pages = 705 fwrt->fw_paging_db[i].fw_paging_block; 706 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys; 707 708 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 709 (*data)->len = cpu_to_le32(sizeof(*paging) + 710 PAGING_BLOCK_SIZE); 711 paging = (void *)(*data)->data; 712 paging->index = cpu_to_le32(i); 713 dma_sync_single_for_cpu(fwrt->trans->dev, addr, 714 PAGING_BLOCK_SIZE, 715 DMA_BIDIRECTIONAL); 716 memcpy(paging->data, page_address(pages), 717 PAGING_BLOCK_SIZE); 718 dma_sync_single_for_device(fwrt->trans->dev, addr, 719 PAGING_BLOCK_SIZE, 720 DMA_BIDIRECTIONAL); 721 (*data) = iwl_fw_error_next_data(*data); 722 723 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 724 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, 725 fwrt->fw_paging_db[i].fw_offs, 726 paging->data, 727 PAGING_BLOCK_SIZE); 728 } 729 } 730 731 static struct iwl_fw_error_dump_file * 732 iwl_fw_error_dump_file(struct iwl_fw_runtime *fwrt, 733 struct iwl_fw_dump_ptrs *fw_error_dump, 734 struct iwl_fwrt_dump_data *data) 735 { 736 struct iwl_fw_error_dump_file *dump_file; 737 struct iwl_fw_error_dump_data *dump_data; 738 struct iwl_fw_error_dump_info *dump_info; 739 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg; 740 struct iwl_fw_error_dump_trigger_desc *dump_trig; 741 u32 sram_len, sram_ofs; 742 const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv; 743 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg; 744 u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0; 745 u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->mac_cfg->base->smem_len; 746 u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ? 747 0 : fwrt->trans->cfg->dccm2_len; 748 int i; 749 750 /* SRAM - include stack CCM if driver knows the values for it */ 751 if (!fwrt->trans->cfg->dccm_offset || 752 !fwrt->trans->cfg->dccm_len) { 753 const struct fw_img *img; 754 755 if (fwrt->cur_fw_img >= IWL_UCODE_TYPE_MAX) 756 return NULL; 757 img = &fwrt->fw->img[fwrt->cur_fw_img]; 758 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset; 759 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len; 760 } else { 761 sram_ofs = fwrt->trans->cfg->dccm_offset; 762 sram_len = fwrt->trans->cfg->dccm_len; 763 } 764 765 /* reading RXF/TXF sizes */ 766 if (iwl_trans_is_fw_error(fwrt->trans)) { 767 fifo_len = iwl_fw_rxf_len(fwrt, mem_cfg); 768 fifo_len += iwl_fw_txf_len(fwrt, mem_cfg); 769 770 /* Make room for PRPH registers */ 771 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_PRPH)) 772 iwl_fw_prph_handler(fwrt, &prph_len, 773 iwl_fw_get_prph_len); 774 775 if (fwrt->trans->mac_cfg->device_family == 776 IWL_DEVICE_FAMILY_7000 && 777 iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RADIO_REG)) 778 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ; 779 } 780 781 file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len; 782 783 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) 784 file_len += sizeof(*dump_data) + sizeof(*dump_info); 785 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) 786 file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg); 787 788 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 789 size_t hdr_len = sizeof(*dump_data) + 790 sizeof(struct iwl_fw_error_dump_mem); 791 792 /* Dump SRAM only if no mem_tlvs */ 793 if (!fwrt->fw->dbg.n_mem_tlv) 794 ADD_LEN(file_len, sram_len, hdr_len); 795 796 /* Make room for all mem types that exist */ 797 ADD_LEN(file_len, smem_len, hdr_len); 798 ADD_LEN(file_len, sram2_len, hdr_len); 799 800 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) 801 ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len); 802 } 803 804 /* Make room for fw's virtual image pages, if it exists */ 805 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 806 file_len += fwrt->num_of_paging_blk * 807 (sizeof(*dump_data) + 808 sizeof(struct iwl_fw_error_dump_paging) + 809 PAGING_BLOCK_SIZE); 810 811 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 812 file_len += sizeof(*dump_data) + 813 fwrt->trans->mac_cfg->base->d3_debug_data_length * 2; 814 } 815 816 /* If we only want a monitor dump, reset the file length */ 817 if (data->monitor_only) { 818 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 + 819 sizeof(*dump_info) + sizeof(*dump_smem_cfg); 820 } 821 822 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 823 data->desc) 824 file_len += sizeof(*dump_data) + sizeof(*dump_trig) + 825 data->desc->len; 826 827 dump_file = vzalloc(file_len); 828 if (!dump_file) 829 return NULL; 830 831 fw_error_dump->fwrt_ptr = dump_file; 832 833 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER); 834 dump_data = (void *)dump_file->data; 835 836 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) { 837 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO); 838 dump_data->len = cpu_to_le32(sizeof(*dump_info)); 839 dump_info = (void *)dump_data->data; 840 dump_info->hw_type = 841 cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->info.hw_rev)); 842 dump_info->hw_step = 843 cpu_to_le32(fwrt->trans->info.hw_rev_step); 844 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable, 845 sizeof(dump_info->fw_human_readable)); 846 strscpy_pad(dump_info->dev_human_readable, 847 fwrt->trans->info.name, 848 sizeof(dump_info->dev_human_readable)); 849 strscpy_pad(dump_info->bus_human_readable, fwrt->dev->bus->name, 850 sizeof(dump_info->bus_human_readable)); 851 dump_info->num_of_lmacs = fwrt->smem_cfg.num_lmacs; 852 dump_info->lmac_err_id[0] = 853 cpu_to_le32(fwrt->dump.lmac_err_id[0]); 854 if (fwrt->smem_cfg.num_lmacs > 1) 855 dump_info->lmac_err_id[1] = 856 cpu_to_le32(fwrt->dump.lmac_err_id[1]); 857 dump_info->umac_err_id = cpu_to_le32(fwrt->dump.umac_err_id); 858 859 dump_data = iwl_fw_error_next_data(dump_data); 860 } 861 862 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) { 863 /* Dump shared memory configuration */ 864 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG); 865 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg)); 866 dump_smem_cfg = (void *)dump_data->data; 867 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs); 868 dump_smem_cfg->num_txfifo_entries = 869 cpu_to_le32(mem_cfg->num_txfifo_entries); 870 for (i = 0; i < MAX_NUM_LMAC; i++) { 871 int j; 872 u32 *txf_size = mem_cfg->lmac[i].txfifo_size; 873 874 for (j = 0; j < TX_FIFO_MAX_NUM; j++) 875 dump_smem_cfg->lmac[i].txfifo_size[j] = 876 cpu_to_le32(txf_size[j]); 877 dump_smem_cfg->lmac[i].rxfifo1_size = 878 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size); 879 } 880 dump_smem_cfg->rxfifo2_size = 881 cpu_to_le32(mem_cfg->rxfifo2_size); 882 dump_smem_cfg->internal_txfifo_addr = 883 cpu_to_le32(mem_cfg->internal_txfifo_addr); 884 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) { 885 dump_smem_cfg->internal_txfifo_size[i] = 886 cpu_to_le32(mem_cfg->internal_txfifo_size[i]); 887 } 888 889 dump_data = iwl_fw_error_next_data(dump_data); 890 } 891 892 /* We only dump the FIFOs if the FW is in error state */ 893 if (fifo_len) { 894 iwl_fw_dump_rxf(fwrt, &dump_data); 895 iwl_fw_dump_txf(fwrt, &dump_data); 896 } 897 898 if (radio_len) 899 iwl_read_radio_regs(fwrt, &dump_data); 900 901 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 902 data->desc) { 903 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO); 904 dump_data->len = cpu_to_le32(sizeof(*dump_trig) + 905 data->desc->len); 906 dump_trig = (void *)dump_data->data; 907 memcpy(dump_trig, &data->desc->trig_desc, 908 sizeof(*dump_trig) + data->desc->len); 909 910 dump_data = iwl_fw_error_next_data(dump_data); 911 } 912 913 /* In case we only want monitor dump, skip to dump transport data */ 914 if (data->monitor_only) 915 goto out; 916 917 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 918 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem = 919 fwrt->fw->dbg.mem_tlv; 920 921 if (!fwrt->fw->dbg.n_mem_tlv) 922 iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs, 923 IWL_FW_ERROR_DUMP_MEM_SRAM); 924 925 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) { 926 u32 len = le32_to_cpu(fw_dbg_mem[i].len); 927 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs); 928 929 iwl_fw_dump_mem(fwrt, &dump_data, len, ofs, 930 le32_to_cpu(fw_dbg_mem[i].data_type)); 931 } 932 933 iwl_fw_dump_mem(fwrt, &dump_data, smem_len, 934 fwrt->trans->mac_cfg->base->smem_offset, 935 IWL_FW_ERROR_DUMP_MEM_SMEM); 936 937 iwl_fw_dump_mem(fwrt, &dump_data, sram2_len, 938 fwrt->trans->cfg->dccm2_offset, 939 IWL_FW_ERROR_DUMP_MEM_SRAM); 940 } 941 942 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 943 u32 addr = fwrt->trans->mac_cfg->base->d3_debug_data_base_addr; 944 size_t data_size = fwrt->trans->mac_cfg->base->d3_debug_data_length; 945 946 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA); 947 dump_data->len = cpu_to_le32(data_size * 2); 948 949 memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size); 950 951 kfree(fwrt->dump.d3_debug_data); 952 fwrt->dump.d3_debug_data = NULL; 953 954 iwl_trans_read_mem_bytes(fwrt->trans, addr, 955 dump_data->data + data_size, 956 data_size); 957 958 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 959 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, addr, 960 dump_data->data + data_size, 961 data_size); 962 963 dump_data = iwl_fw_error_next_data(dump_data); 964 } 965 966 /* Dump fw's virtual image */ 967 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 968 iwl_dump_paging(fwrt, &dump_data); 969 970 if (prph_len) 971 iwl_fw_prph_handler(fwrt, &dump_data, iwl_dump_prph); 972 973 out: 974 dump_file->file_len = cpu_to_le32(file_len); 975 return dump_file; 976 } 977 978 void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt, 979 struct iwl_fwrt_dump_data *dump_data) 980 { 981 struct iwl_fw_dump_ptrs fw_error_dump = {}; 982 struct iwl_fw_error_dump_file *dump_file; 983 struct scatterlist *sg_dump_data; 984 u32 file_len; 985 u32 dump_mask = fwrt->fw->dbg.dump_mask; 986 987 dump_file = iwl_fw_error_dump_file(fwrt, &fw_error_dump, dump_data); 988 if (!dump_file) 989 return; 990 991 if (dump_data->monitor_only) 992 dump_mask &= BIT(IWL_FW_ERROR_DUMP_FW_MONITOR); 993 994 fw_error_dump.trans_ptr = iwl_trans_dump_data(fwrt->trans, dump_mask, 995 fwrt->sanitize_ops, 996 fwrt->sanitize_ctx); 997 file_len = le32_to_cpu(dump_file->file_len); 998 fw_error_dump.fwrt_len = file_len; 999 1000 if (fw_error_dump.trans_ptr) { 1001 file_len += fw_error_dump.trans_ptr->len; 1002 dump_file->file_len = cpu_to_le32(file_len); 1003 } 1004 1005 sg_dump_data = iwl_fw_dbg_alloc_sgtable(file_len); 1006 if (sg_dump_data) { 1007 sg_pcopy_from_buffer(sg_dump_data, 1008 sg_nents(sg_dump_data), 1009 fw_error_dump.fwrt_ptr, 1010 fw_error_dump.fwrt_len, 0); 1011 if (fw_error_dump.trans_ptr) 1012 sg_pcopy_from_buffer(sg_dump_data, 1013 sg_nents(sg_dump_data), 1014 fw_error_dump.trans_ptr->data, 1015 fw_error_dump.trans_ptr->len, 1016 fw_error_dump.fwrt_len); 1017 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 1018 GFP_KERNEL); 1019 } 1020 vfree(fw_error_dump.fwrt_ptr); 1021 vfree(fw_error_dump.trans_ptr); 1022 } 1023