1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2024-2025 Intel Corporation 4 */ 5 #include <linux/module.h> 6 #include <linux/stringify.h> 7 #include "iwl-config.h" 8 #include "iwl-prph.h" 9 #include "fw/api/txq.h" 10 11 /* Highest firmware core release supported */ 12 #define IWL_DR_UCODE_CORE_MAX 101 13 14 /* Lowest firmware API version supported */ 15 #define IWL_DR_UCODE_API_MIN 100 16 17 /* Memory offsets and lengths */ 18 #define IWL_DR_SMEM_OFFSET 0x400000 19 #define IWL_DR_SMEM_LEN 0xD0000 20 21 #define IWL_DR_A_PE_A_FW_PRE "iwlwifi-dr-a0-pe-a0" 22 23 static const struct iwl_family_base_params iwl_dr_base = { 24 .num_of_queues = 512, 25 .max_tfd_queue_size = 65536, 26 .shadow_ram_support = true, 27 .led_compensation = 57, 28 .wd_timeout = IWL_LONG_WD_TIMEOUT, 29 .max_event_log_size = 512, 30 .shadow_reg_enable = true, 31 .pcie_l1_allowed = true, 32 .smem_offset = IWL_DR_SMEM_OFFSET, 33 .smem_len = IWL_DR_SMEM_LEN, 34 .apmg_not_supported = true, 35 .mac_addr_from_csr = 0x30, 36 .d3_debug_data_base_addr = 0x401000, 37 .d3_debug_data_length = 60 * 1024, 38 .mon_smem_regs = { 39 .write_ptr = { 40 .addr = LDBG_M2S_BUF_WPTR, 41 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, 42 }, 43 .cycle_cnt = { 44 .addr = LDBG_M2S_BUF_WRAP_CNT, 45 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, 46 }, 47 }, 48 .min_txq_size = 128, 49 .gp2_reg_addr = 0xd02c68, 50 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT, 51 .mon_dram_regs = { 52 .write_ptr = { 53 .addr = DBGC_CUR_DBGBUF_STATUS, 54 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, 55 }, 56 .cycle_cnt = { 57 .addr = DBGC_DBGBUF_WRAP_AROUND, 58 .mask = 0xffffffff, 59 }, 60 .cur_frag = { 61 .addr = DBGC_CUR_DBGBUF_STATUS, 62 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, 63 }, 64 }, 65 .mon_dbgi_regs = { 66 .write_ptr = { 67 .addr = DBGI_SRAM_FIFO_POINTERS, 68 .mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK, 69 }, 70 }, 71 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 72 .ucode_api_max = ENCODE_CORE_AS_API(IWL_DR_UCODE_CORE_MAX), 73 .ucode_api_min = IWL_DR_UCODE_API_MIN, 74 }; 75 76 const struct iwl_mac_cfg iwl_dr_mac_cfg = { 77 .device_family = IWL_DEVICE_FAMILY_DR, 78 .base = &iwl_dr_base, 79 .mq_rx_supported = true, 80 .gen2 = true, 81 .integrated = true, 82 .umac_prph_offset = 0x300000, 83 .xtal_latency = 12000, 84 .low_latency_xtal = true, 85 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 86 }; 87 88 IWL_CORE_FW(IWL_DR_A_PE_A_FW_PRE, IWL_DR_UCODE_CORE_MAX); 89 90