1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2024-2025 Intel Corporation 4 */ 5 #include <linux/module.h> 6 #include <linux/stringify.h> 7 #include "iwl-config.h" 8 #include "iwl-prph.h" 9 #include "fw/api/txq.h" 10 11 /* Highest firmware API version supported */ 12 #define IWL_DR_UCODE_API_MAX 98 13 14 /* Lowest firmware API version supported */ 15 #define IWL_DR_UCODE_API_MIN 96 16 17 /* NVM versions */ 18 #define IWL_DR_NVM_VERSION 0x0a1d 19 20 /* Memory offsets and lengths */ 21 #define IWL_DR_DCCM_OFFSET 0x800000 /* LMAC1 */ 22 #define IWL_DR_DCCM_LEN 0x10000 /* LMAC1 */ 23 #define IWL_DR_DCCM2_OFFSET 0x880000 24 #define IWL_DR_DCCM2_LEN 0x8000 25 #define IWL_DR_SMEM_OFFSET 0x400000 26 #define IWL_DR_SMEM_LEN 0xD0000 27 28 #define IWL_DR_A_PE_A_FW_PRE "iwlwifi-dr-a0-pe-a0" 29 #define IWL_BR_A_PET_A_FW_PRE "iwlwifi-br-a0-petc-a0" 30 #define IWL_BR_A_PE_A_FW_PRE "iwlwifi-br-a0-pe-a0" 31 32 #define IWL_DR_A_PE_A_FW_MODULE_FIRMWARE(api) \ 33 IWL_DR_A_PE_A_FW_PRE "-" __stringify(api) ".ucode" 34 #define IWL_BR_A_PET_A_FW_MODULE_FIRMWARE(api) \ 35 IWL_BR_A_PET_A_FW_PRE "-" __stringify(api) ".ucode" 36 #define IWL_BR_A_PE_A_FW_MODULE_FIRMWARE(api) \ 37 IWL_BR_A_PE_A_FW_PRE "-" __stringify(api) ".ucode" 38 39 static const struct iwl_base_params iwl_dr_base_params = { 40 .eeprom_size = OTP_LOW_IMAGE_SIZE_32K, 41 .num_of_queues = 512, 42 .max_tfd_queue_size = 65536, 43 .shadow_ram_support = true, 44 .led_compensation = 57, 45 .wd_timeout = IWL_LONG_WD_TIMEOUT, 46 .max_event_log_size = 512, 47 .shadow_reg_enable = true, 48 .pcie_l1_allowed = true, 49 }; 50 51 #define IWL_DEVICE_DR_COMMON \ 52 .ucode_api_max = IWL_DR_UCODE_API_MAX, \ 53 .ucode_api_min = IWL_DR_UCODE_API_MIN, \ 54 .led_mode = IWL_LED_RF_STATE, \ 55 .nvm_hw_section_num = 10, \ 56 .non_shared_ant = ANT_B, \ 57 .dccm_offset = IWL_DR_DCCM_OFFSET, \ 58 .dccm_len = IWL_DR_DCCM_LEN, \ 59 .dccm2_offset = IWL_DR_DCCM2_OFFSET, \ 60 .dccm2_len = IWL_DR_DCCM2_LEN, \ 61 .smem_offset = IWL_DR_SMEM_OFFSET, \ 62 .smem_len = IWL_DR_SMEM_LEN, \ 63 .apmg_not_supported = true, \ 64 .trans.mq_rx_supported = true, \ 65 .vht_mu_mimo_supported = true, \ 66 .mac_addr_from_csr = 0x30, \ 67 .nvm_ver = IWL_DR_NVM_VERSION, \ 68 .trans.rf_id = true, \ 69 .trans.gen2 = true, \ 70 .nvm_type = IWL_NVM_EXT, \ 71 .dbgc_supported = true, \ 72 .min_umac_error_event_table = 0xD0000, \ 73 .d3_debug_data_base_addr = 0x401000, \ 74 .d3_debug_data_length = 60 * 1024, \ 75 .mon_smem_regs = { \ 76 .write_ptr = { \ 77 .addr = LDBG_M2S_BUF_WPTR, \ 78 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, \ 79 }, \ 80 .cycle_cnt = { \ 81 .addr = LDBG_M2S_BUF_WRAP_CNT, \ 82 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, \ 83 }, \ 84 }, \ 85 .trans.umac_prph_offset = 0x300000, \ 86 .trans.device_family = IWL_DEVICE_FAMILY_DR, \ 87 .trans.base_params = &iwl_dr_base_params, \ 88 .min_txq_size = 128, \ 89 .gp2_reg_addr = 0xd02c68, \ 90 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT, \ 91 .mon_dram_regs = { \ 92 .write_ptr = { \ 93 .addr = DBGC_CUR_DBGBUF_STATUS, \ 94 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, \ 95 }, \ 96 .cycle_cnt = { \ 97 .addr = DBGC_DBGBUF_WRAP_AROUND, \ 98 .mask = 0xffffffff, \ 99 }, \ 100 .cur_frag = { \ 101 .addr = DBGC_CUR_DBGBUF_STATUS, \ 102 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, \ 103 }, \ 104 }, \ 105 .mon_dbgi_regs = { \ 106 .write_ptr = { \ 107 .addr = DBGI_SRAM_FIFO_POINTERS, \ 108 .mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK, \ 109 }, \ 110 } 111 112 #define IWL_DEVICE_DR \ 113 IWL_DEVICE_DR_COMMON, \ 114 .uhb_supported = true, \ 115 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, \ 116 .num_rbds = IWL_NUM_RBDS_DR_EHT, \ 117 .ht_params = &iwl_bz_ht_params 118 119 /* 120 * This size was picked according to 8 MSDUs inside 512 A-MSDUs in an 121 * A-MPDU, with additional overhead to account for processing time. 122 */ 123 #define IWL_NUM_RBDS_DR_EHT (512 * 16) 124 125 const struct iwl_cfg_trans_params iwl_dr_trans_cfg = { 126 .device_family = IWL_DEVICE_FAMILY_DR, 127 .base_params = &iwl_dr_base_params, 128 .mq_rx_supported = true, 129 .rf_id = true, 130 .gen2 = true, 131 .integrated = true, 132 .umac_prph_offset = 0x300000, 133 .xtal_latency = 12000, 134 .low_latency_xtal = true, 135 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 136 }; 137 138 const char iwl_dr_name[] = "Intel(R) TBD Dr device"; 139 140 const struct iwl_cfg iwl_cfg_dr = { 141 .fw_name_mac = "dr", 142 IWL_DEVICE_DR, 143 }; 144 145 const struct iwl_cfg_trans_params iwl_br_trans_cfg = { 146 .device_family = IWL_DEVICE_FAMILY_DR, 147 .base_params = &iwl_dr_base_params, 148 .mq_rx_supported = true, 149 .rf_id = true, 150 .gen2 = true, 151 .umac_prph_offset = 0x300000, 152 .xtal_latency = 12000, 153 .low_latency_xtal = true, 154 }; 155 156 const char iwl_br_name[] = "Intel(R) TBD Br device"; 157 158 const struct iwl_cfg iwl_cfg_br = { 159 .fw_name_mac = "br", 160 IWL_DEVICE_DR, 161 }; 162 163 MODULE_FIRMWARE(IWL_DR_A_PE_A_FW_MODULE_FIRMWARE(IWL_DR_UCODE_API_MAX)); 164 MODULE_FIRMWARE(IWL_BR_A_PET_A_FW_MODULE_FIRMWARE(IWL_DR_UCODE_API_MAX)); 165 MODULE_FIRMWARE(IWL_BR_A_PE_A_FW_MODULE_FIRMWARE(IWL_DR_UCODE_API_MAX)); 166