1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2024-2025 Intel Corporation 4 */ 5 #include <linux/module.h> 6 #include <linux/stringify.h> 7 #include "iwl-config.h" 8 #include "iwl-prph.h" 9 #include "fw/api/txq.h" 10 11 /* Highest firmware core release supported */ 12 #define IWL_DR_UCODE_CORE_MAX 99 13 14 /* Lowest firmware API version supported */ 15 #define IWL_DR_UCODE_API_MIN 100 16 17 /* Memory offsets and lengths */ 18 #define IWL_DR_SMEM_OFFSET 0x400000 19 #define IWL_DR_SMEM_LEN 0xD0000 20 21 #define IWL_DR_A_PE_A_FW_PRE "iwlwifi-dr-a0-pe-a0" 22 23 static const struct iwl_family_base_params iwl_dr_base = { 24 .num_of_queues = 512, 25 .max_tfd_queue_size = 65536, 26 .shadow_ram_support = true, 27 .led_compensation = 57, 28 .wd_timeout = IWL_LONG_WD_TIMEOUT, 29 .max_event_log_size = 512, 30 .shadow_reg_enable = true, 31 .pcie_l1_allowed = true, 32 .smem_offset = IWL_DR_SMEM_OFFSET, 33 .smem_len = IWL_DR_SMEM_LEN, 34 .apmg_not_supported = true, 35 .mac_addr_from_csr = 0x30, 36 .min_umac_error_event_table = 0xD0000, 37 .d3_debug_data_base_addr = 0x401000, 38 .d3_debug_data_length = 60 * 1024, 39 .mon_smem_regs = { 40 .write_ptr = { 41 .addr = LDBG_M2S_BUF_WPTR, 42 .mask = LDBG_M2S_BUF_WPTR_VAL_MSK, 43 }, 44 .cycle_cnt = { 45 .addr = LDBG_M2S_BUF_WRAP_CNT, 46 .mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK, 47 }, 48 }, 49 .min_txq_size = 128, 50 .gp2_reg_addr = 0xd02c68, 51 .min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT, 52 .mon_dram_regs = { 53 .write_ptr = { 54 .addr = DBGC_CUR_DBGBUF_STATUS, 55 .mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK, 56 }, 57 .cycle_cnt = { 58 .addr = DBGC_DBGBUF_WRAP_AROUND, 59 .mask = 0xffffffff, 60 }, 61 .cur_frag = { 62 .addr = DBGC_CUR_DBGBUF_STATUS, 63 .mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK, 64 }, 65 }, 66 .mon_dbgi_regs = { 67 .write_ptr = { 68 .addr = DBGI_SRAM_FIFO_POINTERS, 69 .mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK, 70 }, 71 }, 72 .features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM, 73 .ucode_api_max = ENCODE_CORE_AS_API(IWL_DR_UCODE_CORE_MAX), 74 .ucode_api_min = IWL_DR_UCODE_API_MIN, 75 }; 76 77 const struct iwl_mac_cfg iwl_dr_mac_cfg = { 78 .device_family = IWL_DEVICE_FAMILY_DR, 79 .base = &iwl_dr_base, 80 .mq_rx_supported = true, 81 .gen2 = true, 82 .integrated = true, 83 .umac_prph_offset = 0x300000, 84 .xtal_latency = 12000, 85 .low_latency_xtal = true, 86 .ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US, 87 }; 88 89 IWL_CORE_FW(IWL_DR_A_PE_A_FW_PRE, IWL_DR_UCODE_CORE_MAX); 90 91