1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/dma-mapping.h> 18 #include "ath9k.h" 19 #include "ar9003_mac.h" 20 21 #define BITS_PER_BYTE 8 22 #define OFDM_PLCP_BITS 22 23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) 24 #define L_STF 8 25 #define L_LTF 8 26 #define L_SIG 4 27 #define HT_SIG 8 28 #define HT_STF 4 29 #define HT_LTF(_ns) (4 * (_ns)) 30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ 31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ 32 #define TIME_SYMBOLS(t) ((t) >> 2) 33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18) 34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) 35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) 36 37 /* Shifts in ar5008_phy.c and ar9003_phy.c are equal for all revisions */ 38 #define ATH9K_PWRTBL_11NA_OFDM_SHIFT 0 39 #define ATH9K_PWRTBL_11NG_OFDM_SHIFT 4 40 #define ATH9K_PWRTBL_11NA_HT_SHIFT 8 41 #define ATH9K_PWRTBL_11NG_HT_SHIFT 12 42 43 44 static u16 bits_per_symbol[][2] = { 45 /* 20MHz 40MHz */ 46 { 26, 54 }, /* 0: BPSK */ 47 { 52, 108 }, /* 1: QPSK 1/2 */ 48 { 78, 162 }, /* 2: QPSK 3/4 */ 49 { 104, 216 }, /* 3: 16-QAM 1/2 */ 50 { 156, 324 }, /* 4: 16-QAM 3/4 */ 51 { 208, 432 }, /* 5: 64-QAM 2/3 */ 52 { 234, 486 }, /* 6: 64-QAM 3/4 */ 53 { 260, 540 }, /* 7: 64-QAM 5/6 */ 54 }; 55 56 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, 57 struct ath_atx_tid *tid, struct sk_buff *skb); 58 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, 59 int tx_flags, struct ath_txq *txq, 60 struct ieee80211_sta *sta); 61 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 62 struct ath_txq *txq, struct list_head *bf_q, 63 struct ieee80211_sta *sta, 64 struct ath_tx_status *ts, int txok); 65 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 66 struct list_head *head, bool internal); 67 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, 68 struct ath_tx_status *ts, int nframes, int nbad, 69 int txok); 70 static void ath_tx_update_baw(struct ath_atx_tid *tid, struct ath_buf *bf); 71 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, 72 struct ath_txq *txq, 73 struct ath_atx_tid *tid, 74 struct sk_buff *skb); 75 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb, 76 struct ath_tx_control *txctl); 77 78 enum { 79 MCS_HT20, 80 MCS_HT20_SGI, 81 MCS_HT40, 82 MCS_HT40_SGI, 83 }; 84 85 /*********************/ 86 /* Aggregation logic */ 87 /*********************/ 88 89 static void ath_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb) 90 { 91 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 92 struct ieee80211_sta *sta = info->status.status_driver_data[0]; 93 94 if (info->flags & (IEEE80211_TX_CTL_REQ_TX_STATUS | 95 IEEE80211_TX_STATUS_EOSP)) { 96 ieee80211_tx_status_skb(hw, skb); 97 return; 98 } 99 100 if (sta) 101 ieee80211_tx_status_noskb(hw, sta, info); 102 103 dev_kfree_skb(skb); 104 } 105 106 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq) 107 __releases(&txq->axq_lock) 108 { 109 struct ieee80211_hw *hw = sc->hw; 110 struct sk_buff_head q; 111 struct sk_buff *skb; 112 113 __skb_queue_head_init(&q); 114 skb_queue_splice_init(&txq->complete_q, &q); 115 spin_unlock_bh(&txq->axq_lock); 116 117 while ((skb = __skb_dequeue(&q))) 118 ath_tx_status(hw, skb); 119 } 120 121 void ath_tx_queue_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 122 { 123 struct ieee80211_txq *queue = 124 container_of((void *)tid, struct ieee80211_txq, drv_priv); 125 126 ieee80211_schedule_txq(sc->hw, queue); 127 } 128 129 void ath9k_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *queue) 130 { 131 struct ath_softc *sc = hw->priv; 132 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 133 struct ath_atx_tid *tid = (struct ath_atx_tid *) queue->drv_priv; 134 struct ath_txq *txq = tid->txq; 135 136 ath_dbg(common, QUEUE, "Waking TX queue: %pM (%d)\n", 137 queue->sta ? queue->sta->addr : queue->vif->addr, 138 tid->tidno); 139 140 ath_txq_lock(sc, txq); 141 ath_txq_schedule(sc, txq); 142 ath_txq_unlock(sc, txq); 143 } 144 145 static struct ath_frame_info *get_frame_info(struct sk_buff *skb) 146 { 147 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 148 BUILD_BUG_ON(sizeof(struct ath_frame_info) > 149 sizeof(tx_info->status.status_driver_data)); 150 return (struct ath_frame_info *) &tx_info->status.status_driver_data[0]; 151 } 152 153 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno) 154 { 155 if (!tid->an->sta) 156 return; 157 158 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno, 159 seqno << IEEE80211_SEQ_SEQ_SHIFT); 160 } 161 162 static bool ath_merge_ratetbl(struct ieee80211_sta *sta, struct ath_buf *bf, 163 struct ieee80211_tx_info *tx_info) 164 { 165 struct ieee80211_sta_rates *ratetbl; 166 u8 i; 167 168 if (!sta) 169 return false; 170 171 ratetbl = rcu_dereference(sta->rates); 172 if (!ratetbl) 173 return false; 174 175 if (tx_info->control.rates[0].idx < 0 || 176 tx_info->control.rates[0].count == 0) 177 { 178 i = 0; 179 } else { 180 bf->rates[0] = tx_info->control.rates[0]; 181 i = 1; 182 } 183 184 for ( ; i < IEEE80211_TX_MAX_RATES; i++) { 185 bf->rates[i].idx = ratetbl->rate[i].idx; 186 bf->rates[i].flags = ratetbl->rate[i].flags; 187 if (tx_info->control.use_rts) 188 bf->rates[i].count = ratetbl->rate[i].count_rts; 189 else if (tx_info->control.use_cts_prot) 190 bf->rates[i].count = ratetbl->rate[i].count_cts; 191 else 192 bf->rates[i].count = ratetbl->rate[i].count; 193 } 194 195 return true; 196 } 197 198 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta, 199 struct ath_buf *bf) 200 { 201 struct ieee80211_tx_info *tx_info; 202 203 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 204 205 if (!ath_merge_ratetbl(sta, bf, tx_info)) 206 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates, 207 ARRAY_SIZE(bf->rates)); 208 } 209 210 static void ath_txq_skb_done(struct ath_softc *sc, struct sk_buff *skb) 211 { 212 struct ath_frame_info *fi = get_frame_info(skb); 213 struct ath_txq *txq; 214 int q = fi->txq; 215 216 if (q < 0) 217 return; 218 219 txq = sc->tx.txq_map[q]; 220 if (WARN_ON(--txq->pending_frames < 0)) 221 txq->pending_frames = 0; 222 223 } 224 225 static struct ath_atx_tid * 226 ath_get_skb_tid(struct ath_node *an, struct sk_buff *skb) 227 { 228 u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK; 229 return ATH_AN_2_TID(an, tidno); 230 } 231 232 static int 233 ath_tid_pull(struct ath_atx_tid *tid, struct sk_buff **skbuf) 234 { 235 struct ieee80211_txq *txq = container_of((void*)tid, struct ieee80211_txq, drv_priv); 236 struct ath_softc *sc = tid->an->sc; 237 struct ieee80211_hw *hw = sc->hw; 238 struct ath_tx_control txctl = { 239 .txq = tid->txq, 240 .sta = tid->an->sta, 241 }; 242 struct sk_buff *skb; 243 struct ath_frame_info *fi; 244 int q, ret; 245 246 skb = ieee80211_tx_dequeue(hw, txq); 247 if (!skb) 248 return -ENOENT; 249 250 ret = ath_tx_prepare(hw, skb, &txctl); 251 if (ret) { 252 ieee80211_free_txskb(hw, skb); 253 return ret; 254 } 255 256 q = skb_get_queue_mapping(skb); 257 if (tid->txq == sc->tx.txq_map[q]) { 258 fi = get_frame_info(skb); 259 fi->txq = q; 260 ++tid->txq->pending_frames; 261 } 262 263 *skbuf = skb; 264 return 0; 265 } 266 267 static int ath_tid_dequeue(struct ath_atx_tid *tid, 268 struct sk_buff **skb) 269 { 270 int ret = 0; 271 *skb = __skb_dequeue(&tid->retry_q); 272 if (!*skb) 273 ret = ath_tid_pull(tid, skb); 274 275 return ret; 276 } 277 278 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 279 { 280 struct ath_txq *txq = tid->txq; 281 struct sk_buff *skb; 282 struct ath_buf *bf; 283 struct list_head bf_head; 284 struct ath_tx_status ts; 285 struct ath_frame_info *fi; 286 bool sendbar = false; 287 288 INIT_LIST_HEAD(&bf_head); 289 290 memset(&ts, 0, sizeof(ts)); 291 292 while ((skb = __skb_dequeue(&tid->retry_q))) { 293 fi = get_frame_info(skb); 294 bf = fi->bf; 295 if (!bf) { 296 ath_txq_skb_done(sc, skb); 297 ieee80211_free_txskb(sc->hw, skb); 298 continue; 299 } 300 301 if (fi->baw_tracked) { 302 ath_tx_update_baw(tid, bf); 303 sendbar = true; 304 } 305 306 list_add_tail(&bf->list, &bf_head); 307 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0); 308 } 309 310 if (sendbar) { 311 ath_txq_unlock(sc, txq); 312 ath_send_bar(tid, tid->seq_start); 313 ath_txq_lock(sc, txq); 314 } 315 } 316 317 static void ath_tx_update_baw(struct ath_atx_tid *tid, struct ath_buf *bf) 318 { 319 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 320 u16 seqno = bf->bf_state.seqno; 321 int index, cindex; 322 323 if (!fi->baw_tracked) 324 return; 325 326 index = ATH_BA_INDEX(tid->seq_start, seqno); 327 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 328 329 __clear_bit(cindex, tid->tx_buf); 330 331 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) { 332 INCR(tid->seq_start, IEEE80211_SEQ_MAX); 333 INCR(tid->baw_head, ATH_TID_MAX_BUFS); 334 if (tid->bar_index >= 0) 335 tid->bar_index--; 336 } 337 } 338 339 static void ath_tx_addto_baw(struct ath_atx_tid *tid, struct ath_buf *bf) 340 { 341 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 342 u16 seqno = bf->bf_state.seqno; 343 int index, cindex; 344 345 if (fi->baw_tracked) 346 return; 347 348 index = ATH_BA_INDEX(tid->seq_start, seqno); 349 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 350 __set_bit(cindex, tid->tx_buf); 351 fi->baw_tracked = 1; 352 353 if (index >= ((tid->baw_tail - tid->baw_head) & 354 (ATH_TID_MAX_BUFS - 1))) { 355 tid->baw_tail = cindex; 356 INCR(tid->baw_tail, ATH_TID_MAX_BUFS); 357 } 358 } 359 360 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq, 361 struct ath_atx_tid *tid) 362 363 { 364 struct sk_buff *skb; 365 struct ath_buf *bf; 366 struct list_head bf_head; 367 struct ath_tx_status ts; 368 struct ath_frame_info *fi; 369 370 memset(&ts, 0, sizeof(ts)); 371 INIT_LIST_HEAD(&bf_head); 372 373 while (ath_tid_dequeue(tid, &skb) == 0) { 374 fi = get_frame_info(skb); 375 bf = fi->bf; 376 377 if (!bf) { 378 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq, NULL); 379 continue; 380 } 381 382 list_add_tail(&bf->list, &bf_head); 383 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0); 384 } 385 } 386 387 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq, 388 struct sk_buff *skb, int count) 389 { 390 struct ath_frame_info *fi = get_frame_info(skb); 391 struct ath_buf *bf = fi->bf; 392 struct ieee80211_hdr *hdr; 393 int prev = fi->retries; 394 395 TX_STAT_INC(sc, txq->axq_qnum, a_retries); 396 fi->retries += count; 397 398 if (prev > 0) 399 return; 400 401 hdr = (struct ieee80211_hdr *)skb->data; 402 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); 403 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, 404 sizeof(*hdr), DMA_TO_DEVICE); 405 } 406 407 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) 408 { 409 struct ath_buf *bf = NULL; 410 411 spin_lock_bh(&sc->tx.txbuflock); 412 413 if (unlikely(list_empty(&sc->tx.txbuf))) { 414 spin_unlock_bh(&sc->tx.txbuflock); 415 return NULL; 416 } 417 418 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); 419 list_del(&bf->list); 420 421 spin_unlock_bh(&sc->tx.txbuflock); 422 423 return bf; 424 } 425 426 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf) 427 { 428 spin_lock_bh(&sc->tx.txbuflock); 429 list_add_tail(&bf->list, &sc->tx.txbuf); 430 spin_unlock_bh(&sc->tx.txbuflock); 431 } 432 433 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf) 434 { 435 struct ath_buf *tbf; 436 437 tbf = ath_tx_get_buffer(sc); 438 if (WARN_ON(!tbf)) 439 return NULL; 440 441 ATH_TXBUF_RESET(tbf); 442 443 tbf->bf_mpdu = bf->bf_mpdu; 444 tbf->bf_buf_addr = bf->bf_buf_addr; 445 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len); 446 tbf->bf_state = bf->bf_state; 447 tbf->bf_state.stale = false; 448 449 return tbf; 450 } 451 452 static void ath_tx_count_frames(struct ath_buf *bf, struct ath_tx_status *ts, 453 int txok, int *nframes, int *nbad) 454 { 455 u16 seq_st = 0; 456 u32 ba[WME_BA_BMP_SIZE >> 5]; 457 int ba_index; 458 int isaggr = 0; 459 460 *nbad = 0; 461 *nframes = 0; 462 463 isaggr = bf_isaggr(bf); 464 memset(ba, 0, WME_BA_BMP_SIZE >> 3); 465 466 if (isaggr) { 467 seq_st = ts->ts_seqnum; 468 memcpy(ba, &ts->ba, WME_BA_BMP_SIZE >> 3); 469 } 470 471 while (bf) { 472 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno); 473 474 (*nframes)++; 475 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) 476 (*nbad)++; 477 478 bf = bf->bf_next; 479 } 480 } 481 482 483 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, 484 struct ath_buf *bf, struct list_head *bf_q, 485 struct ieee80211_sta *sta, 486 struct ath_atx_tid *tid, 487 struct ath_tx_status *ts, int txok) 488 { 489 struct ath_node *an = NULL; 490 struct sk_buff *skb; 491 struct ieee80211_tx_info *tx_info; 492 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; 493 struct list_head bf_head; 494 struct sk_buff_head bf_pending; 495 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first; 496 u32 ba[WME_BA_BMP_SIZE >> 5]; 497 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0; 498 bool rc_update = true, isba; 499 struct ieee80211_tx_rate rates[4]; 500 struct ath_frame_info *fi; 501 int nframes; 502 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH); 503 int i, retries; 504 int bar_index = -1; 505 506 skb = bf->bf_mpdu; 507 tx_info = IEEE80211_SKB_CB(skb); 508 509 memcpy(rates, bf->rates, sizeof(rates)); 510 511 retries = ts->ts_longretry + 1; 512 for (i = 0; i < ts->ts_rateindex; i++) 513 retries += rates[i].count; 514 515 if (!sta) { 516 INIT_LIST_HEAD(&bf_head); 517 while (bf) { 518 bf_next = bf->bf_next; 519 520 if (!bf->bf_state.stale || bf_next != NULL) 521 list_move_tail(&bf->list, &bf_head); 522 523 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, ts, 0); 524 525 bf = bf_next; 526 } 527 return; 528 } 529 530 an = (struct ath_node *)sta->drv_priv; 531 seq_first = tid->seq_start; 532 isba = ts->ts_flags & ATH9K_TX_BA; 533 534 /* 535 * The hardware occasionally sends a tx status for the wrong TID. 536 * In this case, the BA status cannot be considered valid and all 537 * subframes need to be retransmitted 538 * 539 * Only BlockAcks have a TID and therefore normal Acks cannot be 540 * checked 541 */ 542 if (isba && tid->tidno != ts->tid) 543 txok = false; 544 545 isaggr = bf_isaggr(bf); 546 memset(ba, 0, WME_BA_BMP_SIZE >> 3); 547 548 if (isaggr && txok) { 549 if (ts->ts_flags & ATH9K_TX_BA) { 550 seq_st = ts->ts_seqnum; 551 memcpy(ba, &ts->ba, WME_BA_BMP_SIZE >> 3); 552 } else { 553 /* 554 * AR5416 can become deaf/mute when BA 555 * issue happens. Chip needs to be reset. 556 * But AP code may have synchronization issues 557 * when perform internal reset in this routine. 558 * Only enable reset in STA mode for now. 559 */ 560 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) 561 needreset = 1; 562 } 563 } 564 565 __skb_queue_head_init(&bf_pending); 566 567 ath_tx_count_frames(bf, ts, txok, &nframes, &nbad); 568 while (bf) { 569 u16 seqno = bf->bf_state.seqno; 570 571 txfail = txpending = sendbar = 0; 572 bf_next = bf->bf_next; 573 574 skb = bf->bf_mpdu; 575 tx_info = IEEE80211_SKB_CB(skb); 576 fi = get_frame_info(skb); 577 578 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) || 579 !tid->active) { 580 /* 581 * Outside of the current BlockAck window, 582 * maybe part of a previous session 583 */ 584 txfail = 1; 585 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) { 586 /* transmit completion, subframe is 587 * acked by block ack */ 588 acked_cnt++; 589 } else if (!isaggr && txok) { 590 /* transmit completion */ 591 acked_cnt++; 592 } else if (flush) { 593 txpending = 1; 594 } else if (fi->retries < ATH_MAX_SW_RETRIES) { 595 if (txok || !an->sleeping) 596 ath_tx_set_retry(sc, txq, bf->bf_mpdu, 597 retries); 598 599 txpending = 1; 600 } else { 601 txfail = 1; 602 txfail_cnt++; 603 bar_index = max_t(int, bar_index, 604 ATH_BA_INDEX(seq_first, seqno)); 605 } 606 607 /* 608 * Make sure the last desc is reclaimed if it 609 * not a holding desc. 610 */ 611 INIT_LIST_HEAD(&bf_head); 612 if (bf_next != NULL || !bf_last->bf_state.stale) 613 list_move_tail(&bf->list, &bf_head); 614 615 if (!txpending) { 616 /* 617 * complete the acked-ones/xretried ones; update 618 * block-ack window 619 */ 620 ath_tx_update_baw(tid, bf); 621 622 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) { 623 memcpy(tx_info->control.rates, rates, sizeof(rates)); 624 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok); 625 rc_update = false; 626 if (bf == bf->bf_lastbf) 627 ath_dynack_sample_tx_ts(sc->sc_ah, 628 bf->bf_mpdu, 629 ts, sta); 630 } 631 632 ath_tx_complete_buf(sc, bf, txq, &bf_head, sta, ts, 633 !txfail); 634 } else { 635 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) { 636 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP; 637 ieee80211_sta_eosp(sta); 638 } 639 /* retry the un-acked ones */ 640 if (bf->bf_next == NULL && bf_last->bf_state.stale) { 641 struct ath_buf *tbf; 642 643 tbf = ath_clone_txbuf(sc, bf_last); 644 /* 645 * Update tx baw and complete the 646 * frame with failed status if we 647 * run out of tx buf. 648 */ 649 if (!tbf) { 650 ath_tx_update_baw(tid, bf); 651 652 ath_tx_complete_buf(sc, bf, txq, 653 &bf_head, NULL, ts, 654 0); 655 bar_index = max_t(int, bar_index, 656 ATH_BA_INDEX(seq_first, seqno)); 657 break; 658 } 659 660 fi->bf = tbf; 661 } 662 663 /* 664 * Put this buffer to the temporary pending 665 * queue to retain ordering 666 */ 667 __skb_queue_tail(&bf_pending, skb); 668 } 669 670 bf = bf_next; 671 } 672 673 /* prepend un-acked frames to the beginning of the pending frame queue */ 674 if (!skb_queue_empty(&bf_pending)) { 675 if (an->sleeping) 676 ieee80211_sta_set_buffered(sta, tid->tidno, true); 677 678 skb_queue_splice_tail(&bf_pending, &tid->retry_q); 679 if (!an->sleeping) { 680 ath_tx_queue_tid(sc, tid); 681 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY)) 682 tid->clear_ps_filter = true; 683 } 684 } 685 686 if (bar_index >= 0) { 687 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index); 688 689 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq)) 690 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq); 691 692 ath_txq_unlock(sc, txq); 693 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1)); 694 ath_txq_lock(sc, txq); 695 } 696 697 if (needreset) 698 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR); 699 } 700 701 static bool bf_is_ampdu_not_probing(struct ath_buf *bf) 702 { 703 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu); 704 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE); 705 } 706 707 static void ath_tx_count_airtime(struct ath_softc *sc, 708 struct ieee80211_sta *sta, 709 struct ath_buf *bf, 710 struct ath_tx_status *ts, 711 u8 tid) 712 { 713 u32 airtime = 0; 714 int i; 715 716 airtime += ts->duration * (ts->ts_longretry + 1); 717 for(i = 0; i < ts->ts_rateindex; i++) { 718 int rate_dur = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc, i); 719 airtime += rate_dur * bf->rates[i].count; 720 } 721 722 ieee80211_sta_register_airtime(sta, tid, airtime, 0); 723 } 724 725 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq, 726 struct ath_tx_status *ts, struct ath_buf *bf, 727 struct list_head *bf_head) 728 { 729 struct ieee80211_hw *hw = sc->hw; 730 struct ieee80211_tx_info *info; 731 struct ieee80211_sta *sta; 732 struct ieee80211_hdr *hdr; 733 struct ath_atx_tid *tid = NULL; 734 bool txok, flush; 735 736 txok = !(ts->ts_status & ATH9K_TXERR_MASK); 737 flush = !!(ts->ts_status & ATH9K_TX_FLUSH); 738 txq->axq_tx_inprogress = false; 739 740 txq->axq_depth--; 741 if (bf_is_ampdu_not_probing(bf)) 742 txq->axq_ampdu_depth--; 743 744 ts->duration = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc, 745 ts->ts_rateindex); 746 747 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data; 748 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2); 749 if (sta) { 750 struct ath_node *an = (struct ath_node *)sta->drv_priv; 751 tid = ath_get_skb_tid(an, bf->bf_mpdu); 752 ath_tx_count_airtime(sc, sta, bf, ts, tid->tidno); 753 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY)) 754 tid->clear_ps_filter = true; 755 } 756 757 if (!bf_isampdu(bf)) { 758 if (!flush) { 759 info = IEEE80211_SKB_CB(bf->bf_mpdu); 760 memcpy(info->control.rates, bf->rates, 761 sizeof(info->control.rates)); 762 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok); 763 ath_dynack_sample_tx_ts(sc->sc_ah, bf->bf_mpdu, ts, 764 sta); 765 } 766 ath_tx_complete_buf(sc, bf, txq, bf_head, sta, ts, txok); 767 } else 768 ath_tx_complete_aggr(sc, txq, bf, bf_head, sta, tid, ts, txok); 769 770 if (!flush) 771 ath_txq_schedule(sc, txq); 772 } 773 774 static bool ath_lookup_legacy(struct ath_buf *bf) 775 { 776 struct sk_buff *skb; 777 struct ieee80211_tx_info *tx_info; 778 struct ieee80211_tx_rate *rates; 779 int i; 780 781 skb = bf->bf_mpdu; 782 tx_info = IEEE80211_SKB_CB(skb); 783 rates = tx_info->control.rates; 784 785 for (i = 0; i < 4; i++) { 786 if (!rates[i].count || rates[i].idx < 0) 787 break; 788 789 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) 790 return true; 791 } 792 793 return false; 794 } 795 796 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, 797 struct ath_atx_tid *tid) 798 { 799 struct sk_buff *skb; 800 struct ieee80211_tx_info *tx_info; 801 struct ieee80211_tx_rate *rates; 802 u32 max_4ms_framelen, frmlen; 803 u16 aggr_limit, bt_aggr_limit, legacy = 0; 804 int q = tid->txq->mac80211_qnum; 805 int i; 806 807 skb = bf->bf_mpdu; 808 tx_info = IEEE80211_SKB_CB(skb); 809 rates = bf->rates; 810 811 /* 812 * Find the lowest frame length among the rate series that will have a 813 * 4ms (or TXOP limited) transmit duration. 814 */ 815 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; 816 817 for (i = 0; i < 4; i++) { 818 int modeidx; 819 820 if (!rates[i].count) 821 continue; 822 823 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) { 824 legacy = 1; 825 break; 826 } 827 828 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 829 modeidx = MCS_HT40; 830 else 831 modeidx = MCS_HT20; 832 833 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) 834 modeidx++; 835 836 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx]; 837 max_4ms_framelen = min(max_4ms_framelen, frmlen); 838 } 839 840 /* 841 * limit aggregate size by the minimum rate if rate selected is 842 * not a probe rate, if rate selected is a probe rate then 843 * avoid aggregation of this packet. 844 */ 845 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) 846 return 0; 847 848 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX); 849 850 /* 851 * Override the default aggregation limit for BTCOEX. 852 */ 853 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen); 854 if (bt_aggr_limit) 855 aggr_limit = bt_aggr_limit; 856 857 if (tid->an->maxampdu) 858 aggr_limit = min(aggr_limit, tid->an->maxampdu); 859 860 return aggr_limit; 861 } 862 863 /* 864 * Returns the number of delimiters to be added to 865 * meet the minimum required mpdudensity. 866 */ 867 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, 868 struct ath_buf *bf, u16 frmlen, 869 bool first_subfrm) 870 { 871 #define FIRST_DESC_NDELIMS 60 872 u32 nsymbits, nsymbols; 873 u16 minlen; 874 u8 flags, rix; 875 int width, streams, half_gi, ndelim, mindelim; 876 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 877 878 /* Select standard number of delimiters based on frame length alone */ 879 ndelim = ATH_AGGR_GET_NDELIM(frmlen); 880 881 /* 882 * If encryption enabled, hardware requires some more padding between 883 * subframes. 884 * TODO - this could be improved to be dependent on the rate. 885 * The hardware can keep up at lower rates, but not higher rates 886 */ 887 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) && 888 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) 889 ndelim += ATH_AGGR_ENCRYPTDELIM; 890 891 /* 892 * Add delimiter when using RTS/CTS with aggregation 893 * and non enterprise AR9003 card 894 */ 895 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) && 896 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE)) 897 ndelim = max(ndelim, FIRST_DESC_NDELIMS); 898 899 /* 900 * Convert desired mpdu density from microeconds to bytes based 901 * on highest rate in rate series (i.e. first rate) to determine 902 * required minimum length for subframe. Take into account 903 * whether high rate is 20 or 40Mhz and half or full GI. 904 * 905 * If there is no mpdu density restriction, no further calculation 906 * is needed. 907 */ 908 909 if (tid->an->mpdudensity == 0) 910 return ndelim; 911 912 rix = bf->rates[0].idx; 913 flags = bf->rates[0].flags; 914 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; 915 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; 916 917 if (half_gi) 918 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity); 919 else 920 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity); 921 922 if (nsymbols == 0) 923 nsymbols = 1; 924 925 streams = HT_RC_2_STREAMS(rix); 926 nsymbits = bits_per_symbol[rix % 8][width] * streams; 927 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; 928 929 if (frmlen < minlen) { 930 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; 931 ndelim = max(mindelim, ndelim); 932 } 933 934 return ndelim; 935 } 936 937 static int 938 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq, 939 struct ath_atx_tid *tid, struct ath_buf **buf) 940 { 941 struct ieee80211_tx_info *tx_info; 942 struct ath_frame_info *fi; 943 struct ath_buf *bf; 944 struct sk_buff *skb, *first_skb = NULL; 945 u16 seqno; 946 int ret; 947 948 while (1) { 949 ret = ath_tid_dequeue(tid, &skb); 950 if (ret < 0) 951 return ret; 952 953 fi = get_frame_info(skb); 954 bf = fi->bf; 955 if (!fi->bf) 956 bf = ath_tx_setup_buffer(sc, txq, tid, skb); 957 else 958 bf->bf_state.stale = false; 959 960 if (!bf) { 961 ath_txq_skb_done(sc, skb); 962 ieee80211_free_txskb(sc->hw, skb); 963 continue; 964 } 965 966 bf->bf_next = NULL; 967 bf->bf_lastbf = bf; 968 969 tx_info = IEEE80211_SKB_CB(skb); 970 tx_info->flags &= ~(IEEE80211_TX_CTL_CLEAR_PS_FILT | 971 IEEE80211_TX_STATUS_EOSP); 972 973 /* 974 * No aggregation session is running, but there may be frames 975 * from a previous session or a failed attempt in the queue. 976 * Send them out as normal data frames 977 */ 978 if (!tid->active) 979 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU; 980 981 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) { 982 bf->bf_state.bf_type = 0; 983 break; 984 } 985 986 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR; 987 seqno = bf->bf_state.seqno; 988 989 /* do not step over block-ack window */ 990 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) { 991 __skb_queue_tail(&tid->retry_q, skb); 992 993 /* If there are other skbs in the retry q, they are 994 * probably within the BAW, so loop immediately to get 995 * one of them. Otherwise the queue can get stuck. */ 996 if (!skb_queue_is_first(&tid->retry_q, skb) && 997 !WARN_ON(skb == first_skb)) { 998 if(!first_skb) /* infinite loop prevention */ 999 first_skb = skb; 1000 continue; 1001 } 1002 return -EINPROGRESS; 1003 } 1004 1005 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) { 1006 struct ath_tx_status ts = {}; 1007 struct list_head bf_head; 1008 1009 INIT_LIST_HEAD(&bf_head); 1010 list_add(&bf->list, &bf_head); 1011 ath_tx_update_baw(tid, bf); 1012 ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0); 1013 continue; 1014 } 1015 1016 if (bf_isampdu(bf)) 1017 ath_tx_addto_baw(tid, bf); 1018 1019 break; 1020 } 1021 1022 *buf = bf; 1023 return 0; 1024 } 1025 1026 static int 1027 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq, 1028 struct ath_atx_tid *tid, struct list_head *bf_q, 1029 struct ath_buf *bf_first) 1030 { 1031 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) 1032 struct ath_buf *bf = bf_first, *bf_prev = NULL; 1033 int nframes = 0, ndelim, ret; 1034 u16 aggr_limit = 0, al = 0, bpad = 0, 1035 al_delta, h_baw = tid->baw_size / 2; 1036 struct ieee80211_tx_info *tx_info; 1037 struct ath_frame_info *fi; 1038 struct sk_buff *skb; 1039 1040 1041 bf = bf_first; 1042 aggr_limit = ath_lookup_rate(sc, bf, tid); 1043 1044 while (bf) 1045 { 1046 skb = bf->bf_mpdu; 1047 fi = get_frame_info(skb); 1048 1049 /* do not exceed aggregation limit */ 1050 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen; 1051 if (nframes) { 1052 if (aggr_limit < al + bpad + al_delta || 1053 ath_lookup_legacy(bf) || nframes >= h_baw) 1054 goto stop; 1055 1056 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 1057 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) || 1058 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) 1059 goto stop; 1060 } 1061 1062 /* add padding for previous frame to aggregation length */ 1063 al += bpad + al_delta; 1064 1065 /* 1066 * Get the delimiters needed to meet the MPDU 1067 * density for this node. 1068 */ 1069 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen, 1070 !nframes); 1071 bpad = PADBYTES(al_delta) + (ndelim << 2); 1072 1073 nframes++; 1074 bf->bf_next = NULL; 1075 1076 /* link buffers of this frame to the aggregate */ 1077 bf->bf_state.ndelim = ndelim; 1078 1079 list_add_tail(&bf->list, bf_q); 1080 if (bf_prev) 1081 bf_prev->bf_next = bf; 1082 1083 bf_prev = bf; 1084 1085 ret = ath_tx_get_tid_subframe(sc, txq, tid, &bf); 1086 if (ret < 0) 1087 break; 1088 } 1089 goto finish; 1090 stop: 1091 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu); 1092 finish: 1093 bf = bf_first; 1094 bf->bf_lastbf = bf_prev; 1095 1096 if (bf == bf_prev) { 1097 al = get_frame_info(bf->bf_mpdu)->framelen; 1098 bf->bf_state.bf_type = BUF_AMPDU; 1099 } else { 1100 TX_STAT_INC(sc, txq->axq_qnum, a_aggr); 1101 } 1102 1103 return al; 1104 #undef PADBYTES 1105 } 1106 1107 /* 1108 * rix - rate index 1109 * pktlen - total bytes (delims + data + fcs + pads + pad delims) 1110 * width - 0 for 20 MHz, 1 for 40 MHz 1111 * half_gi - to use 4us v/s 3.6 us for symbol time 1112 */ 1113 u32 ath_pkt_duration(u8 rix, int pktlen, int width, 1114 int half_gi, bool shortPreamble) 1115 { 1116 u32 nbits, nsymbits, duration, nsymbols; 1117 int streams; 1118 1119 /* find number of symbols: PLCP + data */ 1120 streams = HT_RC_2_STREAMS(rix); 1121 nbits = (pktlen << 3) + OFDM_PLCP_BITS; 1122 nsymbits = bits_per_symbol[rix % 8][width] * streams; 1123 nsymbols = (nbits + nsymbits - 1) / nsymbits; 1124 1125 if (!half_gi) 1126 duration = SYMBOL_TIME(nsymbols); 1127 else 1128 duration = SYMBOL_TIME_HALFGI(nsymbols); 1129 1130 /* addup duration for legacy/ht training and signal fields */ 1131 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); 1132 1133 return duration; 1134 } 1135 1136 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi) 1137 { 1138 int streams = HT_RC_2_STREAMS(mcs); 1139 int symbols, bits; 1140 int bytes = 0; 1141 1142 usec -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); 1143 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec); 1144 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams; 1145 bits -= OFDM_PLCP_BITS; 1146 bytes = bits / 8; 1147 if (bytes > 65532) 1148 bytes = 65532; 1149 1150 return bytes; 1151 } 1152 1153 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop) 1154 { 1155 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi; 1156 int mcs; 1157 1158 /* 4ms is the default (and maximum) duration */ 1159 if (!txop || txop > 4096) 1160 txop = 4096; 1161 1162 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20]; 1163 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI]; 1164 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40]; 1165 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI]; 1166 for (mcs = 0; mcs < 32; mcs++) { 1167 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false); 1168 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true); 1169 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false); 1170 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true); 1171 } 1172 } 1173 1174 static u8 ath_get_rate_txpower(struct ath_softc *sc, struct ath_buf *bf, 1175 u8 rateidx, bool is_40, bool is_cck, bool is_mcs) 1176 { 1177 u8 max_power; 1178 struct sk_buff *skb; 1179 struct ath_frame_info *fi; 1180 struct ieee80211_tx_info *info; 1181 struct ath_hw *ah = sc->sc_ah; 1182 bool is_2ghz, is_5ghz, use_stbc; 1183 1184 if (sc->tx99_state || !ah->tpc_enabled) 1185 return MAX_RATE_POWER; 1186 1187 skb = bf->bf_mpdu; 1188 fi = get_frame_info(skb); 1189 info = IEEE80211_SKB_CB(skb); 1190 1191 is_2ghz = info->band == NL80211_BAND_2GHZ; 1192 is_5ghz = info->band == NL80211_BAND_5GHZ; 1193 use_stbc = is_mcs && rateidx < 8 && (info->flags & 1194 IEEE80211_TX_CTL_STBC); 1195 1196 if (is_mcs) 1197 rateidx += is_5ghz ? ATH9K_PWRTBL_11NA_HT_SHIFT 1198 : ATH9K_PWRTBL_11NG_HT_SHIFT; 1199 else if (is_2ghz && !is_cck) 1200 rateidx += ATH9K_PWRTBL_11NG_OFDM_SHIFT; 1201 else 1202 rateidx += ATH9K_PWRTBL_11NA_OFDM_SHIFT; 1203 1204 if (!AR_SREV_9300_20_OR_LATER(ah)) { 1205 int txpower = fi->tx_power; 1206 1207 if (is_40) { 1208 u8 power_ht40delta; 1209 struct ar5416_eeprom_def *eep = &ah->eeprom.def; 1210 u16 eeprom_rev = ah->eep_ops->get_eeprom_rev(ah); 1211 1212 if (eeprom_rev >= AR5416_EEP_MINOR_VER_2) { 1213 struct modal_eep_header *pmodal; 1214 1215 pmodal = &eep->modalHeader[is_2ghz]; 1216 power_ht40delta = pmodal->ht40PowerIncForPdadc; 1217 } else { 1218 power_ht40delta = 2; 1219 } 1220 txpower += power_ht40delta; 1221 } 1222 1223 if (AR_SREV_9287(ah) || AR_SREV_9285(ah) || 1224 AR_SREV_9271(ah)) { 1225 txpower -= 2 * AR9287_PWR_TABLE_OFFSET_DB; 1226 } else if (AR_SREV_9280_20_OR_LATER(ah)) { 1227 s8 power_offset; 1228 1229 power_offset = ah->eep_ops->get_eeprom(ah, 1230 EEP_PWR_TABLE_OFFSET); 1231 txpower -= 2 * power_offset; 1232 } 1233 1234 if (OLC_FOR_AR9280_20_LATER(ah) && is_cck) 1235 txpower -= 2; 1236 1237 txpower = max(txpower, 0); 1238 max_power = min_t(u8, ah->tx_power[rateidx], txpower); 1239 1240 /* XXX: clamp minimum TX power at 1 for AR9160 since if 1241 * max_power is set to 0, frames are transmitted at max 1242 * TX power 1243 */ 1244 if (!max_power && !AR_SREV_9280_20_OR_LATER(ah)) 1245 max_power = 1; 1246 } else if (!bf->bf_state.bfs_paprd) { 1247 if (use_stbc) 1248 max_power = min_t(u8, ah->tx_power_stbc[rateidx], 1249 fi->tx_power); 1250 else 1251 max_power = min_t(u8, ah->tx_power[rateidx], 1252 fi->tx_power); 1253 } else { 1254 max_power = ah->paprd_training_power; 1255 } 1256 1257 return max_power; 1258 } 1259 1260 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, 1261 struct ath_tx_info *info, int len, bool rts) 1262 { 1263 struct ath_hw *ah = sc->sc_ah; 1264 struct ath_common *common = ath9k_hw_common(ah); 1265 struct sk_buff *skb; 1266 struct ieee80211_tx_info *tx_info; 1267 struct ieee80211_tx_rate *rates; 1268 const struct ieee80211_rate *rate; 1269 struct ieee80211_hdr *hdr; 1270 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 1271 u32 rts_thresh = sc->hw->wiphy->rts_threshold; 1272 int i; 1273 u8 rix = 0; 1274 1275 skb = bf->bf_mpdu; 1276 tx_info = IEEE80211_SKB_CB(skb); 1277 rates = bf->rates; 1278 hdr = (struct ieee80211_hdr *)skb->data; 1279 1280 /* set dur_update_en for l-sig computation except for PS-Poll frames */ 1281 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control); 1282 info->rtscts_rate = fi->rtscts_rate; 1283 1284 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) { 1285 bool is_40, is_sgi, is_sp, is_cck; 1286 int phy; 1287 1288 if (!rates[i].count || (rates[i].idx < 0)) 1289 break; 1290 1291 rix = rates[i].idx; 1292 info->rates[i].Tries = rates[i].count; 1293 1294 /* 1295 * Handle RTS threshold for unaggregated HT frames. 1296 */ 1297 if (bf_isampdu(bf) && !bf_isaggr(bf) && 1298 (rates[i].flags & IEEE80211_TX_RC_MCS) && 1299 unlikely(rts_thresh != (u32) -1)) { 1300 if (!rts_thresh || (len > rts_thresh)) 1301 rts = true; 1302 } 1303 1304 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) { 1305 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; 1306 info->flags |= ATH9K_TXDESC_RTSENA; 1307 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 1308 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; 1309 info->flags |= ATH9K_TXDESC_CTSENA; 1310 } 1311 1312 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 1313 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040; 1314 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) 1315 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI; 1316 1317 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI); 1318 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH); 1319 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE); 1320 1321 if (rates[i].flags & IEEE80211_TX_RC_MCS) { 1322 /* MCS rates */ 1323 info->rates[i].Rate = rix | 0x80; 1324 info->rates[i].ChSel = ath_txchainmask_reduction(sc, 1325 ah->txchainmask, info->rates[i].Rate); 1326 info->rates[i].PktDuration = ath_pkt_duration(rix, len, 1327 is_40, is_sgi, is_sp); 1328 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC)) 1329 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC; 1330 if (rix >= 8 && fi->dyn_smps) { 1331 info->rates[i].RateFlags |= 1332 ATH9K_RATESERIES_RTS_CTS; 1333 info->flags |= ATH9K_TXDESC_CTSENA; 1334 } 1335 1336 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, 1337 is_40, false, true); 1338 continue; 1339 } 1340 1341 /* legacy rates */ 1342 rate = &common->sbands[tx_info->band].bitrates[rates[i].idx]; 1343 if ((tx_info->band == NL80211_BAND_2GHZ) && 1344 !(rate->flags & IEEE80211_RATE_ERP_G)) 1345 phy = WLAN_RC_PHY_CCK; 1346 else 1347 phy = WLAN_RC_PHY_OFDM; 1348 1349 info->rates[i].Rate = rate->hw_value; 1350 if (rate->hw_value_short) { 1351 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 1352 info->rates[i].Rate |= rate->hw_value_short; 1353 } else { 1354 is_sp = false; 1355 } 1356 1357 if (bf->bf_state.bfs_paprd) 1358 info->rates[i].ChSel = ah->txchainmask; 1359 else 1360 info->rates[i].ChSel = ath_txchainmask_reduction(sc, 1361 ah->txchainmask, info->rates[i].Rate); 1362 1363 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah, 1364 phy, rate->bitrate * 100, len, rix, is_sp); 1365 1366 is_cck = IS_CCK_RATE(info->rates[i].Rate); 1367 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, false, 1368 is_cck, false); 1369 } 1370 1371 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ 1372 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit)) 1373 info->flags &= ~ATH9K_TXDESC_RTSENA; 1374 1375 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */ 1376 if (info->flags & ATH9K_TXDESC_RTSENA) 1377 info->flags &= ~ATH9K_TXDESC_CTSENA; 1378 } 1379 1380 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) 1381 { 1382 struct ieee80211_hdr *hdr; 1383 enum ath9k_pkt_type htype; 1384 __le16 fc; 1385 1386 hdr = (struct ieee80211_hdr *)skb->data; 1387 fc = hdr->frame_control; 1388 1389 if (ieee80211_is_beacon(fc)) 1390 htype = ATH9K_PKT_TYPE_BEACON; 1391 else if (ieee80211_is_probe_resp(fc)) 1392 htype = ATH9K_PKT_TYPE_PROBE_RESP; 1393 else if (ieee80211_is_atim(fc)) 1394 htype = ATH9K_PKT_TYPE_ATIM; 1395 else if (ieee80211_is_pspoll(fc)) 1396 htype = ATH9K_PKT_TYPE_PSPOLL; 1397 else 1398 htype = ATH9K_PKT_TYPE_NORMAL; 1399 1400 return htype; 1401 } 1402 1403 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf, 1404 struct ath_txq *txq, int len) 1405 { 1406 struct ath_hw *ah = sc->sc_ah; 1407 struct ath_buf *bf_first = NULL; 1408 struct ath_tx_info info; 1409 u32 rts_thresh = sc->hw->wiphy->rts_threshold; 1410 bool rts = false; 1411 1412 memset(&info, 0, sizeof(info)); 1413 info.is_first = true; 1414 info.is_last = true; 1415 info.qcu = txq->axq_qnum; 1416 1417 while (bf) { 1418 struct sk_buff *skb = bf->bf_mpdu; 1419 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1420 struct ath_frame_info *fi = get_frame_info(skb); 1421 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR); 1422 1423 info.type = get_hw_packet_type(skb); 1424 if (bf->bf_next) 1425 info.link = bf->bf_next->bf_daddr; 1426 else 1427 info.link = (sc->tx99_state) ? bf->bf_daddr : 0; 1428 1429 if (!bf_first) { 1430 bf_first = bf; 1431 1432 if (!sc->tx99_state) 1433 info.flags = ATH9K_TXDESC_INTREQ; 1434 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) || 1435 txq == sc->tx.uapsdq) 1436 info.flags |= ATH9K_TXDESC_CLRDMASK; 1437 1438 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) 1439 info.flags |= ATH9K_TXDESC_NOACK; 1440 if (tx_info->flags & IEEE80211_TX_CTL_LDPC) 1441 info.flags |= ATH9K_TXDESC_LDPC; 1442 1443 if (bf->bf_state.bfs_paprd) 1444 info.flags |= (u32) bf->bf_state.bfs_paprd << 1445 ATH9K_TXDESC_PAPRD_S; 1446 1447 /* 1448 * mac80211 doesn't handle RTS threshold for HT because 1449 * the decision has to be taken based on AMPDU length 1450 * and aggregation is done entirely inside ath9k. 1451 * Set the RTS/CTS flag for the first subframe based 1452 * on the threshold. 1453 */ 1454 if (aggr && (bf == bf_first) && 1455 unlikely(rts_thresh != (u32) -1)) { 1456 /* 1457 * "len" is the size of the entire AMPDU. 1458 */ 1459 if (!rts_thresh || (len > rts_thresh)) 1460 rts = true; 1461 } 1462 1463 if (!aggr) 1464 len = fi->framelen; 1465 1466 ath_buf_set_rate(sc, bf, &info, len, rts); 1467 } 1468 1469 info.buf_addr[0] = bf->bf_buf_addr; 1470 info.buf_len[0] = skb->len; 1471 info.pkt_len = fi->framelen; 1472 info.keyix = fi->keyix; 1473 info.keytype = fi->keytype; 1474 1475 if (aggr) { 1476 if (bf == bf_first) 1477 info.aggr = AGGR_BUF_FIRST; 1478 else if (bf == bf_first->bf_lastbf) 1479 info.aggr = AGGR_BUF_LAST; 1480 else 1481 info.aggr = AGGR_BUF_MIDDLE; 1482 1483 info.ndelim = bf->bf_state.ndelim; 1484 info.aggr_len = len; 1485 } 1486 1487 if (bf == bf_first->bf_lastbf) 1488 bf_first = NULL; 1489 1490 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info); 1491 bf = bf->bf_next; 1492 } 1493 } 1494 1495 static void 1496 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq, 1497 struct ath_atx_tid *tid, struct list_head *bf_q, 1498 struct ath_buf *bf_first) 1499 { 1500 struct ath_buf *bf = bf_first, *bf_prev = NULL; 1501 int nframes = 0, ret; 1502 1503 do { 1504 struct ieee80211_tx_info *tx_info; 1505 1506 nframes++; 1507 list_add_tail(&bf->list, bf_q); 1508 if (bf_prev) 1509 bf_prev->bf_next = bf; 1510 bf_prev = bf; 1511 1512 if (nframes >= 2) 1513 break; 1514 1515 ret = ath_tx_get_tid_subframe(sc, txq, tid, &bf); 1516 if (ret < 0) 1517 break; 1518 1519 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 1520 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { 1521 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu); 1522 break; 1523 } 1524 1525 ath_set_rates(tid->an->vif, tid->an->sta, bf); 1526 } while (1); 1527 } 1528 1529 static int ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, 1530 struct ath_atx_tid *tid) 1531 { 1532 struct ath_buf *bf = NULL; 1533 struct ieee80211_tx_info *tx_info; 1534 struct list_head bf_q; 1535 int aggr_len = 0, ret; 1536 bool aggr; 1537 1538 INIT_LIST_HEAD(&bf_q); 1539 1540 ret = ath_tx_get_tid_subframe(sc, txq, tid, &bf); 1541 if (ret < 0) 1542 return ret; 1543 1544 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 1545 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU); 1546 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) || 1547 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) { 1548 __skb_queue_tail(&tid->retry_q, bf->bf_mpdu); 1549 return -EBUSY; 1550 } 1551 1552 ath_set_rates(tid->an->vif, tid->an->sta, bf); 1553 if (aggr) 1554 aggr_len = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf); 1555 else 1556 ath_tx_form_burst(sc, txq, tid, &bf_q, bf); 1557 1558 if (list_empty(&bf_q)) 1559 return -EAGAIN; 1560 1561 if (tid->clear_ps_filter || tid->an->no_ps_filter) { 1562 tid->clear_ps_filter = false; 1563 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; 1564 } 1565 1566 ath_tx_fill_desc(sc, bf, txq, aggr_len); 1567 ath_tx_txqaddbuf(sc, txq, &bf_q, false); 1568 return 0; 1569 } 1570 1571 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, 1572 u16 tid, u16 *ssn) 1573 { 1574 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1575 struct ath_atx_tid *txtid; 1576 struct ath_txq *txq; 1577 struct ath_node *an; 1578 u8 density; 1579 1580 ath_dbg(common, XMIT, "%s called\n", __func__); 1581 1582 an = (struct ath_node *)sta->drv_priv; 1583 txtid = ATH_AN_2_TID(an, tid); 1584 txq = txtid->txq; 1585 1586 ath_txq_lock(sc, txq); 1587 1588 /* update ampdu factor/density, they may have changed. This may happen 1589 * in HT IBSS when a beacon with HT-info is received after the station 1590 * has already been added. 1591 */ 1592 if (sta->deflink.ht_cap.ht_supported) { 1593 an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + 1594 sta->deflink.ht_cap.ampdu_factor)) - 1; 1595 density = ath9k_parse_mpdudensity(sta->deflink.ht_cap.ampdu_density); 1596 an->mpdudensity = density; 1597 } 1598 1599 txtid->active = true; 1600 *ssn = txtid->seq_start = txtid->seq_next; 1601 txtid->bar_index = -1; 1602 1603 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf)); 1604 txtid->baw_head = txtid->baw_tail = 0; 1605 1606 ath_txq_unlock_complete(sc, txq); 1607 1608 return 0; 1609 } 1610 1611 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) 1612 { 1613 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1614 struct ath_node *an = (struct ath_node *)sta->drv_priv; 1615 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); 1616 struct ath_txq *txq = txtid->txq; 1617 1618 ath_dbg(common, XMIT, "%s called\n", __func__); 1619 1620 ath_txq_lock(sc, txq); 1621 txtid->active = false; 1622 ath_tx_flush_tid(sc, txtid); 1623 ath_txq_unlock_complete(sc, txq); 1624 } 1625 1626 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc, 1627 struct ath_node *an) 1628 { 1629 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1630 struct ath_atx_tid *tid; 1631 int tidno; 1632 1633 ath_dbg(common, XMIT, "%s called\n", __func__); 1634 1635 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) { 1636 tid = ath_node_to_tid(an, tidno); 1637 1638 if (!skb_queue_empty(&tid->retry_q)) 1639 ieee80211_sta_set_buffered(sta, tid->tidno, true); 1640 1641 } 1642 } 1643 1644 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an) 1645 { 1646 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1647 struct ath_atx_tid *tid; 1648 struct ath_txq *txq; 1649 int tidno; 1650 1651 ath_dbg(common, XMIT, "%s called\n", __func__); 1652 1653 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) { 1654 tid = ath_node_to_tid(an, tidno); 1655 txq = tid->txq; 1656 1657 ath_txq_lock(sc, txq); 1658 tid->clear_ps_filter = true; 1659 if (!skb_queue_empty(&tid->retry_q)) { 1660 ath_tx_queue_tid(sc, tid); 1661 ath_txq_schedule(sc, txq); 1662 } 1663 ath_txq_unlock_complete(sc, txq); 1664 1665 } 1666 } 1667 1668 1669 static void 1670 ath9k_set_moredata(struct ath_softc *sc, struct ath_buf *bf, bool val) 1671 { 1672 struct ieee80211_hdr *hdr; 1673 __le16 mask, mask_val; 1674 1675 mask = cpu_to_le16(IEEE80211_FCTL_MOREDATA); 1676 1677 if (val) 1678 mask_val = mask; 1679 else 1680 mask_val = 0; 1681 1682 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data; 1683 if ((hdr->frame_control & mask) != mask_val) { 1684 hdr->frame_control = (hdr->frame_control & ~mask) | mask_val; 1685 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, 1686 sizeof(*hdr), DMA_TO_DEVICE); 1687 } 1688 } 1689 1690 void ath9k_release_buffered_frames(struct ieee80211_hw *hw, 1691 struct ieee80211_sta *sta, 1692 u16 tids, int nframes, 1693 enum ieee80211_frame_release_type reason, 1694 bool more_data) 1695 { 1696 struct ath_softc *sc = hw->priv; 1697 struct ath_node *an = (struct ath_node *)sta->drv_priv; 1698 struct ath_txq *txq = sc->tx.uapsdq; 1699 struct ieee80211_tx_info *info; 1700 struct list_head bf_q; 1701 struct ath_buf *bf_tail = NULL, *bf = NULL; 1702 int i, ret; 1703 1704 INIT_LIST_HEAD(&bf_q); 1705 for (i = 0; tids && nframes; i++, tids >>= 1) { 1706 struct ath_atx_tid *tid; 1707 1708 if (!(tids & 1)) 1709 continue; 1710 1711 tid = ATH_AN_2_TID(an, i); 1712 1713 ath_txq_lock(sc, tid->txq); 1714 while (nframes > 0) { 1715 ret = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, 1716 tid, &bf); 1717 if (ret < 0) 1718 break; 1719 1720 ath9k_set_moredata(sc, bf, true); 1721 list_add_tail(&bf->list, &bf_q); 1722 ath_set_rates(tid->an->vif, tid->an->sta, bf); 1723 if (bf_isampdu(bf)) 1724 bf->bf_state.bf_type &= ~BUF_AGGR; 1725 if (bf_tail) 1726 bf_tail->bf_next = bf; 1727 1728 bf_tail = bf; 1729 nframes--; 1730 TX_STAT_INC(sc, txq->axq_qnum, a_queued_hw); 1731 1732 if (an->sta && skb_queue_empty(&tid->retry_q)) 1733 ieee80211_sta_set_buffered(an->sta, i, false); 1734 } 1735 ath_txq_unlock_complete(sc, tid->txq); 1736 } 1737 1738 if (list_empty(&bf_q)) 1739 return; 1740 1741 if (!more_data) 1742 ath9k_set_moredata(sc, bf_tail, false); 1743 1744 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu); 1745 info->flags |= IEEE80211_TX_STATUS_EOSP; 1746 1747 bf = list_first_entry(&bf_q, struct ath_buf, list); 1748 ath_txq_lock(sc, txq); 1749 ath_tx_fill_desc(sc, bf, txq, 0); 1750 ath_tx_txqaddbuf(sc, txq, &bf_q, false); 1751 ath_txq_unlock(sc, txq); 1752 } 1753 1754 /********************/ 1755 /* Queue Management */ 1756 /********************/ 1757 1758 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 1759 { 1760 struct ath_hw *ah = sc->sc_ah; 1761 struct ath9k_tx_queue_info qi; 1762 static const int subtype_txq_to_hwq[] = { 1763 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE, 1764 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK, 1765 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI, 1766 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO, 1767 }; 1768 int axq_qnum, i; 1769 1770 memset(&qi, 0, sizeof(qi)); 1771 qi.tqi_subtype = subtype_txq_to_hwq[subtype]; 1772 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; 1773 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; 1774 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; 1775 qi.tqi_physCompBuf = 0; 1776 1777 /* 1778 * Enable interrupts only for EOL and DESC conditions. 1779 * We mark tx descriptors to receive a DESC interrupt 1780 * when a tx queue gets deep; otherwise waiting for the 1781 * EOL to reap descriptors. Note that this is done to 1782 * reduce interrupt load and this only defers reaping 1783 * descriptors, never transmitting frames. Aside from 1784 * reducing interrupts this also permits more concurrency. 1785 * The only potential downside is if the tx queue backs 1786 * up in which case the top half of the kernel may backup 1787 * due to a lack of tx descriptors. 1788 * 1789 * The UAPSD queue is an exception, since we take a desc- 1790 * based intr on the EOSP frames. 1791 */ 1792 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1793 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE; 1794 } else { 1795 if (qtype == ATH9K_TX_QUEUE_UAPSD) 1796 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; 1797 else 1798 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | 1799 TXQ_FLAG_TXDESCINT_ENABLE; 1800 } 1801 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); 1802 if (axq_qnum == -1) { 1803 /* 1804 * NB: don't print a message, this happens 1805 * normally on parts with too few tx queues 1806 */ 1807 return NULL; 1808 } 1809 if (!ATH_TXQ_SETUP(sc, axq_qnum)) { 1810 struct ath_txq *txq = &sc->tx.txq[axq_qnum]; 1811 1812 txq->axq_qnum = axq_qnum; 1813 txq->mac80211_qnum = -1; 1814 txq->axq_link = NULL; 1815 __skb_queue_head_init(&txq->complete_q); 1816 INIT_LIST_HEAD(&txq->axq_q); 1817 spin_lock_init(&txq->axq_lock); 1818 txq->axq_depth = 0; 1819 txq->axq_ampdu_depth = 0; 1820 txq->axq_tx_inprogress = false; 1821 sc->tx.txqsetup |= 1<<axq_qnum; 1822 1823 txq->txq_headidx = txq->txq_tailidx = 0; 1824 for (i = 0; i < ATH_TXFIFO_DEPTH; i++) 1825 INIT_LIST_HEAD(&txq->txq_fifo[i]); 1826 } 1827 return &sc->tx.txq[axq_qnum]; 1828 } 1829 1830 int ath_txq_update(struct ath_softc *sc, int qnum, 1831 struct ath9k_tx_queue_info *qinfo) 1832 { 1833 struct ath_hw *ah = sc->sc_ah; 1834 int error = 0; 1835 struct ath9k_tx_queue_info qi; 1836 1837 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum); 1838 1839 ath9k_hw_get_txq_props(ah, qnum, &qi); 1840 qi.tqi_aifs = qinfo->tqi_aifs; 1841 qi.tqi_cwmin = qinfo->tqi_cwmin; 1842 qi.tqi_cwmax = qinfo->tqi_cwmax; 1843 qi.tqi_burstTime = qinfo->tqi_burstTime; 1844 qi.tqi_readyTime = qinfo->tqi_readyTime; 1845 1846 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { 1847 ath_err(ath9k_hw_common(sc->sc_ah), 1848 "Unable to update hardware queue %u!\n", qnum); 1849 error = -EIO; 1850 } else { 1851 ath9k_hw_resettxqueue(ah, qnum); 1852 } 1853 1854 return error; 1855 } 1856 1857 int ath_cabq_update(struct ath_softc *sc) 1858 { 1859 struct ath9k_tx_queue_info qi; 1860 struct ath_beacon_config *cur_conf = &sc->cur_chan->beacon; 1861 int qnum = sc->beacon.cabq->axq_qnum; 1862 1863 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); 1864 1865 qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) * 1866 ATH_CABQ_READY_TIME) / 100; 1867 ath_txq_update(sc, qnum, &qi); 1868 1869 return 0; 1870 } 1871 1872 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq, 1873 struct list_head *list) 1874 { 1875 struct ath_buf *bf, *lastbf; 1876 struct list_head bf_head; 1877 struct ath_tx_status ts; 1878 1879 memset(&ts, 0, sizeof(ts)); 1880 ts.ts_status = ATH9K_TX_FLUSH; 1881 INIT_LIST_HEAD(&bf_head); 1882 1883 while (!list_empty(list)) { 1884 bf = list_first_entry(list, struct ath_buf, list); 1885 1886 if (bf->bf_state.stale) { 1887 list_del(&bf->list); 1888 1889 ath_tx_return_buffer(sc, bf); 1890 continue; 1891 } 1892 1893 lastbf = bf->bf_lastbf; 1894 list_cut_position(&bf_head, list, &lastbf->list); 1895 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); 1896 } 1897 } 1898 1899 /* 1900 * Drain a given TX queue (could be Beacon or Data) 1901 * 1902 * This assumes output has been stopped and 1903 * we do not need to block ath_tx_tasklet. 1904 */ 1905 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq) 1906 { 1907 rcu_read_lock(); 1908 ath_txq_lock(sc, txq); 1909 1910 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1911 int idx = txq->txq_tailidx; 1912 1913 while (!list_empty(&txq->txq_fifo[idx])) { 1914 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]); 1915 1916 INCR(idx, ATH_TXFIFO_DEPTH); 1917 } 1918 txq->txq_tailidx = idx; 1919 } 1920 1921 txq->axq_link = NULL; 1922 txq->axq_tx_inprogress = false; 1923 ath_drain_txq_list(sc, txq, &txq->axq_q); 1924 1925 ath_txq_unlock_complete(sc, txq); 1926 rcu_read_unlock(); 1927 } 1928 1929 bool ath_drain_all_txq(struct ath_softc *sc) 1930 { 1931 struct ath_hw *ah = sc->sc_ah; 1932 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1933 struct ath_txq *txq; 1934 int i; 1935 u32 npend = 0; 1936 1937 if (test_bit(ATH_OP_INVALID, &common->op_flags)) 1938 return true; 1939 1940 ath9k_hw_abort_tx_dma(ah); 1941 1942 /* Check if any queue remains active */ 1943 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1944 if (!ATH_TXQ_SETUP(sc, i)) 1945 continue; 1946 1947 if (!sc->tx.txq[i].axq_depth) 1948 continue; 1949 1950 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum)) 1951 npend |= BIT(i); 1952 } 1953 1954 if (npend) { 1955 RESET_STAT_INC(sc, RESET_TX_DMA_ERROR); 1956 ath_dbg(common, RESET, 1957 "Failed to stop TX DMA, queues=0x%03x!\n", npend); 1958 } 1959 1960 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1961 if (!ATH_TXQ_SETUP(sc, i)) 1962 continue; 1963 1964 txq = &sc->tx.txq[i]; 1965 ath_draintxq(sc, txq); 1966 } 1967 1968 return !npend; 1969 } 1970 1971 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 1972 { 1973 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); 1974 sc->tx.txqsetup &= ~(1<<txq->axq_qnum); 1975 } 1976 1977 /* For each acq entry, for each tid, try to schedule packets 1978 * for transmit until ampdu_depth has reached min Q depth. 1979 */ 1980 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) 1981 { 1982 struct ieee80211_hw *hw = sc->hw; 1983 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1984 struct ieee80211_txq *queue; 1985 struct ath_atx_tid *tid; 1986 int ret; 1987 1988 if (txq->mac80211_qnum < 0) 1989 return; 1990 1991 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) 1992 return; 1993 1994 ieee80211_txq_schedule_start(hw, txq->mac80211_qnum); 1995 spin_lock_bh(&sc->chan_lock); 1996 rcu_read_lock(); 1997 1998 if (sc->cur_chan->stopped) 1999 goto out; 2000 2001 while ((queue = ieee80211_next_txq(hw, txq->mac80211_qnum))) { 2002 bool force; 2003 2004 tid = (struct ath_atx_tid *)queue->drv_priv; 2005 2006 ret = ath_tx_sched_aggr(sc, txq, tid); 2007 ath_dbg(common, QUEUE, "ath_tx_sched_aggr returned %d\n", ret); 2008 2009 force = !skb_queue_empty(&tid->retry_q); 2010 ieee80211_return_txq(hw, queue, force); 2011 } 2012 2013 out: 2014 rcu_read_unlock(); 2015 spin_unlock_bh(&sc->chan_lock); 2016 ieee80211_txq_schedule_end(hw, txq->mac80211_qnum); 2017 } 2018 2019 void ath_txq_schedule_all(struct ath_softc *sc) 2020 { 2021 struct ath_txq *txq; 2022 int i; 2023 2024 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 2025 txq = sc->tx.txq_map[i]; 2026 2027 spin_lock_bh(&txq->axq_lock); 2028 ath_txq_schedule(sc, txq); 2029 spin_unlock_bh(&txq->axq_lock); 2030 } 2031 } 2032 2033 /***********/ 2034 /* TX, DMA */ 2035 /***********/ 2036 2037 /* 2038 * Insert a chain of ath_buf (descriptors) on a txq and 2039 * assume the descriptors are already chained together by caller. 2040 */ 2041 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 2042 struct list_head *head, bool internal) 2043 { 2044 struct ath_hw *ah = sc->sc_ah; 2045 struct ath_common *common = ath9k_hw_common(ah); 2046 struct ath_buf *bf, *bf_last; 2047 bool puttxbuf = false; 2048 bool edma; 2049 2050 /* 2051 * Insert the frame on the outbound list and 2052 * pass it on to the hardware. 2053 */ 2054 2055 if (list_empty(head)) 2056 return; 2057 2058 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 2059 bf = list_first_entry(head, struct ath_buf, list); 2060 bf_last = list_entry(head->prev, struct ath_buf, list); 2061 2062 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n", 2063 txq->axq_qnum, txq->axq_depth); 2064 2065 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) { 2066 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]); 2067 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH); 2068 puttxbuf = true; 2069 } else { 2070 list_splice_tail_init(head, &txq->axq_q); 2071 2072 if (txq->axq_link) { 2073 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr); 2074 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n", 2075 txq->axq_qnum, txq->axq_link, 2076 ito64(bf->bf_daddr), bf->bf_desc); 2077 } else if (!edma) 2078 puttxbuf = true; 2079 2080 txq->axq_link = bf_last->bf_desc; 2081 } 2082 2083 if (puttxbuf) { 2084 TX_STAT_INC(sc, txq->axq_qnum, puttxbuf); 2085 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 2086 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n", 2087 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); 2088 } 2089 2090 if (!edma || sc->tx99_state) { 2091 TX_STAT_INC(sc, txq->axq_qnum, txstart); 2092 ath9k_hw_txstart(ah, txq->axq_qnum); 2093 } 2094 2095 if (!internal) { 2096 while (bf) { 2097 txq->axq_depth++; 2098 if (bf_is_ampdu_not_probing(bf)) 2099 txq->axq_ampdu_depth++; 2100 2101 bf_last = bf->bf_lastbf; 2102 bf = bf_last->bf_next; 2103 bf_last->bf_next = NULL; 2104 } 2105 } 2106 } 2107 2108 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, 2109 struct ath_atx_tid *tid, struct sk_buff *skb) 2110 { 2111 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2112 struct ath_frame_info *fi = get_frame_info(skb); 2113 struct list_head bf_head; 2114 struct ath_buf *bf = fi->bf; 2115 2116 INIT_LIST_HEAD(&bf_head); 2117 list_add_tail(&bf->list, &bf_head); 2118 bf->bf_state.bf_type = 0; 2119 if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) { 2120 bf->bf_state.bf_type = BUF_AMPDU; 2121 ath_tx_addto_baw(tid, bf); 2122 } 2123 2124 bf->bf_next = NULL; 2125 bf->bf_lastbf = bf; 2126 ath_tx_fill_desc(sc, bf, txq, fi->framelen); 2127 ath_tx_txqaddbuf(sc, txq, &bf_head, false); 2128 TX_STAT_INC(sc, txq->axq_qnum, queued); 2129 } 2130 2131 static void setup_frame_info(struct ieee80211_hw *hw, 2132 struct ieee80211_sta *sta, 2133 struct sk_buff *skb, 2134 int framelen) 2135 { 2136 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2137 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key; 2138 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2139 const struct ieee80211_rate *rate; 2140 struct ath_frame_info *fi = get_frame_info(skb); 2141 struct ath_node *an = NULL; 2142 enum ath9k_key_type keytype; 2143 bool short_preamble = false; 2144 u8 txpower; 2145 2146 /* 2147 * We check if Short Preamble is needed for the CTS rate by 2148 * checking the BSS's global flag. 2149 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. 2150 */ 2151 if (tx_info->control.vif && 2152 tx_info->control.vif->bss_conf.use_short_preamble) 2153 short_preamble = true; 2154 2155 rate = ieee80211_get_rts_cts_rate(hw, tx_info); 2156 keytype = ath9k_cmn_get_hw_crypto_keytype(skb); 2157 2158 if (sta) 2159 an = (struct ath_node *) sta->drv_priv; 2160 2161 if (tx_info->control.vif) { 2162 struct ieee80211_vif *vif = tx_info->control.vif; 2163 if (vif->bss_conf.txpower == INT_MIN) 2164 goto nonvifpower; 2165 txpower = 2 * vif->bss_conf.txpower; 2166 } else { 2167 struct ath_softc *sc; 2168 nonvifpower: 2169 sc = hw->priv; 2170 2171 txpower = sc->cur_chan->cur_txpower; 2172 } 2173 2174 memset(fi, 0, sizeof(*fi)); 2175 fi->txq = -1; 2176 if (hw_key) 2177 fi->keyix = hw_key->hw_key_idx; 2178 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0) 2179 fi->keyix = an->ps_key; 2180 else 2181 fi->keyix = ATH9K_TXKEYIX_INVALID; 2182 fi->dyn_smps = sta && sta->deflink.smps_mode == IEEE80211_SMPS_DYNAMIC; 2183 fi->keytype = keytype; 2184 fi->framelen = framelen; 2185 fi->tx_power = txpower; 2186 2187 if (!rate) 2188 return; 2189 fi->rtscts_rate = rate->hw_value; 2190 if (short_preamble) 2191 fi->rtscts_rate |= rate->hw_value_short; 2192 } 2193 2194 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate) 2195 { 2196 struct ath_hw *ah = sc->sc_ah; 2197 struct ath9k_channel *curchan = ah->curchan; 2198 2199 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) && 2200 (chainmask == 0x7) && (rate < 0x90)) 2201 return 0x3; 2202 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) && 2203 IS_CCK_RATE(rate)) 2204 return 0x2; 2205 else 2206 return chainmask; 2207 } 2208 2209 /* 2210 * Assign a descriptor (and sequence number if necessary, 2211 * and map buffer for DMA. Frees skb on error 2212 */ 2213 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, 2214 struct ath_txq *txq, 2215 struct ath_atx_tid *tid, 2216 struct sk_buff *skb) 2217 { 2218 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2219 struct ath_frame_info *fi = get_frame_info(skb); 2220 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2221 struct ath_buf *bf; 2222 int fragno; 2223 u16 seqno; 2224 2225 bf = ath_tx_get_buffer(sc); 2226 if (!bf) { 2227 ath_dbg(common, XMIT, "TX buffers are full\n"); 2228 return NULL; 2229 } 2230 2231 ATH_TXBUF_RESET(bf); 2232 2233 if (tid && ieee80211_is_data_present(hdr->frame_control)) { 2234 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG; 2235 seqno = tid->seq_next; 2236 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT); 2237 2238 if (fragno) 2239 hdr->seq_ctrl |= cpu_to_le16(fragno); 2240 2241 if (!ieee80211_has_morefrags(hdr->frame_control)) 2242 INCR(tid->seq_next, IEEE80211_SEQ_MAX); 2243 2244 bf->bf_state.seqno = seqno; 2245 } 2246 2247 bf->bf_mpdu = skb; 2248 2249 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, 2250 skb->len, DMA_TO_DEVICE); 2251 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) { 2252 bf->bf_mpdu = NULL; 2253 bf->bf_buf_addr = 0; 2254 ath_err(ath9k_hw_common(sc->sc_ah), 2255 "dma_mapping_error() on TX\n"); 2256 ath_tx_return_buffer(sc, bf); 2257 return NULL; 2258 } 2259 2260 fi->bf = bf; 2261 2262 return bf; 2263 } 2264 2265 void ath_assign_seq(struct ath_common *common, struct sk_buff *skb) 2266 { 2267 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 2268 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2269 struct ieee80211_vif *vif = info->control.vif; 2270 struct ath_vif *avp; 2271 2272 if (!(info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)) 2273 return; 2274 2275 if (!vif) 2276 return; 2277 2278 avp = (struct ath_vif *)vif->drv_priv; 2279 2280 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) 2281 avp->seq_no += 0x10; 2282 2283 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); 2284 hdr->seq_ctrl |= cpu_to_le16(avp->seq_no); 2285 } 2286 2287 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb, 2288 struct ath_tx_control *txctl) 2289 { 2290 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 2291 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2292 struct ieee80211_sta *sta = txctl->sta; 2293 struct ieee80211_vif *vif = info->control.vif; 2294 struct ath_vif *avp; 2295 struct ath_softc *sc = hw->priv; 2296 int frmlen = skb->len + FCS_LEN; 2297 int padpos, padsize; 2298 2299 /* NOTE: sta can be NULL according to net/mac80211.h */ 2300 if (sta) 2301 txctl->an = (struct ath_node *)sta->drv_priv; 2302 else if (vif && ieee80211_is_data(hdr->frame_control)) { 2303 avp = (void *)vif->drv_priv; 2304 txctl->an = &avp->mcast_node; 2305 } 2306 2307 if (info->control.hw_key) 2308 frmlen += info->control.hw_key->icv_len; 2309 2310 ath_assign_seq(ath9k_hw_common(sc->sc_ah), skb); 2311 2312 if ((vif && vif->type != NL80211_IFTYPE_AP && 2313 vif->type != NL80211_IFTYPE_AP_VLAN) || 2314 !ieee80211_is_data(hdr->frame_control)) 2315 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; 2316 2317 /* Add the padding after the header if this is not already done */ 2318 padpos = ieee80211_hdrlen(hdr->frame_control); 2319 padsize = padpos & 3; 2320 if (padsize && skb->len > padpos) { 2321 if (skb_headroom(skb) < padsize) 2322 return -ENOMEM; 2323 2324 skb_push(skb, padsize); 2325 memmove(skb->data, skb->data + padsize, padpos); 2326 } 2327 2328 setup_frame_info(hw, sta, skb, frmlen); 2329 return 0; 2330 } 2331 2332 2333 /* Upon failure caller should free skb */ 2334 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, 2335 struct ath_tx_control *txctl) 2336 { 2337 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 2338 struct ieee80211_sta *sta = txctl->sta; 2339 struct ieee80211_vif *vif = info->control.vif; 2340 struct ath_frame_info *fi = get_frame_info(skb); 2341 struct ath_softc *sc = hw->priv; 2342 struct ath_txq *txq = txctl->txq; 2343 struct ath_atx_tid *tid = NULL; 2344 struct ath_node *an = NULL; 2345 struct ath_buf *bf; 2346 bool ps_resp; 2347 int q, ret; 2348 2349 ps_resp = !!(info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE); 2350 2351 ret = ath_tx_prepare(hw, skb, txctl); 2352 if (ret) 2353 return ret; 2354 2355 /* 2356 * At this point, the vif, hw_key and sta pointers in the tx control 2357 * info are no longer valid (overwritten by the ath_frame_info data. 2358 */ 2359 2360 q = skb_get_queue_mapping(skb); 2361 2362 if (ps_resp) 2363 txq = sc->tx.uapsdq; 2364 2365 if (txctl->sta) { 2366 an = (struct ath_node *) sta->drv_priv; 2367 tid = ath_get_skb_tid(an, skb); 2368 } 2369 2370 ath_txq_lock(sc, txq); 2371 if (txq == sc->tx.txq_map[q]) { 2372 fi->txq = q; 2373 ++txq->pending_frames; 2374 } 2375 2376 bf = ath_tx_setup_buffer(sc, txq, tid, skb); 2377 if (!bf) { 2378 ath_txq_skb_done(sc, skb); 2379 if (txctl->paprd) 2380 dev_kfree_skb_any(skb); 2381 else 2382 ieee80211_free_txskb(sc->hw, skb); 2383 goto out; 2384 } 2385 2386 bf->bf_state.bfs_paprd = txctl->paprd; 2387 2388 if (txctl->paprd) 2389 bf->bf_state.bfs_paprd_timestamp = jiffies; 2390 2391 ath_set_rates(vif, sta, bf); 2392 ath_tx_send_normal(sc, txq, tid, skb); 2393 2394 out: 2395 ath_txq_unlock(sc, txq); 2396 2397 return 0; 2398 } 2399 2400 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 2401 struct sk_buff *skb) 2402 { 2403 struct ath_softc *sc = hw->priv; 2404 struct ath_tx_control txctl = { 2405 .txq = sc->beacon.cabq 2406 }; 2407 struct ath_tx_info info = {}; 2408 struct ath_buf *bf_tail = NULL; 2409 struct ath_buf *bf; 2410 LIST_HEAD(bf_q); 2411 int duration = 0; 2412 int max_duration; 2413 2414 max_duration = 2415 sc->cur_chan->beacon.beacon_interval * 1000 * 2416 sc->cur_chan->beacon.dtim_period / ATH_BCBUF; 2417 2418 do { 2419 struct ath_frame_info *fi = get_frame_info(skb); 2420 2421 if (ath_tx_prepare(hw, skb, &txctl)) 2422 break; 2423 2424 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb); 2425 if (!bf) 2426 break; 2427 2428 bf->bf_lastbf = bf; 2429 ath_set_rates(vif, NULL, bf); 2430 ath_buf_set_rate(sc, bf, &info, fi->framelen, false); 2431 duration += info.rates[0].PktDuration; 2432 if (bf_tail) 2433 bf_tail->bf_next = bf; 2434 2435 list_add_tail(&bf->list, &bf_q); 2436 bf_tail = bf; 2437 skb = NULL; 2438 2439 if (duration > max_duration) 2440 break; 2441 2442 skb = ieee80211_get_buffered_bc(hw, vif); 2443 } while(skb); 2444 2445 if (skb) 2446 ieee80211_free_txskb(hw, skb); 2447 2448 if (list_empty(&bf_q)) 2449 return; 2450 2451 bf = list_last_entry(&bf_q, struct ath_buf, list); 2452 ath9k_set_moredata(sc, bf, false); 2453 2454 bf = list_first_entry(&bf_q, struct ath_buf, list); 2455 ath_txq_lock(sc, txctl.txq); 2456 ath_tx_fill_desc(sc, bf, txctl.txq, 0); 2457 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false); 2458 TX_STAT_INC(sc, txctl.txq->axq_qnum, queued); 2459 ath_txq_unlock(sc, txctl.txq); 2460 } 2461 2462 /*****************/ 2463 /* TX Completion */ 2464 /*****************/ 2465 2466 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, 2467 int tx_flags, struct ath_txq *txq, 2468 struct ieee80211_sta *sta) 2469 { 2470 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2471 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2472 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; 2473 int padpos, padsize; 2474 unsigned long flags; 2475 2476 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb); 2477 2478 if (sc->sc_ah->caldata) 2479 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags); 2480 2481 if (!(tx_flags & ATH_TX_ERROR)) { 2482 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) 2483 tx_info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 2484 else 2485 tx_info->flags |= IEEE80211_TX_STAT_ACK; 2486 } 2487 2488 if (tx_info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) { 2489 padpos = ieee80211_hdrlen(hdr->frame_control); 2490 padsize = padpos & 3; 2491 if (padsize && skb->len>padpos+padsize) { 2492 /* 2493 * Remove MAC header padding before giving the frame back to 2494 * mac80211. 2495 */ 2496 memmove(skb->data + padsize, skb->data, padpos); 2497 skb_pull(skb, padsize); 2498 } 2499 } 2500 2501 spin_lock_irqsave(&sc->sc_pm_lock, flags); 2502 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) { 2503 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK; 2504 ath_dbg(common, PS, 2505 "Going back to sleep after having received TX status (0x%lx)\n", 2506 sc->ps_flags & (PS_WAIT_FOR_BEACON | 2507 PS_WAIT_FOR_CAB | 2508 PS_WAIT_FOR_PSPOLL_DATA | 2509 PS_WAIT_FOR_TX_ACK)); 2510 } 2511 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 2512 2513 ath_txq_skb_done(sc, skb); 2514 tx_info->status.status_driver_data[0] = sta; 2515 __skb_queue_tail(&txq->complete_q, skb); 2516 } 2517 2518 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 2519 struct ath_txq *txq, struct list_head *bf_q, 2520 struct ieee80211_sta *sta, 2521 struct ath_tx_status *ts, int txok) 2522 { 2523 struct sk_buff *skb = bf->bf_mpdu; 2524 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2525 unsigned long flags; 2526 int tx_flags = 0; 2527 2528 if (!txok) 2529 tx_flags |= ATH_TX_ERROR; 2530 2531 if (ts->ts_status & ATH9K_TXERR_FILT) 2532 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 2533 2534 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE); 2535 bf->bf_buf_addr = 0; 2536 if (sc->tx99_state) 2537 goto skip_tx_complete; 2538 2539 if (bf->bf_state.bfs_paprd) { 2540 if (time_after(jiffies, 2541 bf->bf_state.bfs_paprd_timestamp + 2542 msecs_to_jiffies(ATH_PAPRD_TIMEOUT))) 2543 dev_kfree_skb_any(skb); 2544 else 2545 complete(&sc->paprd_complete); 2546 } else { 2547 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags); 2548 ath_tx_complete(sc, skb, tx_flags, txq, sta); 2549 } 2550 skip_tx_complete: 2551 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't 2552 * accidentally reference it later. 2553 */ 2554 bf->bf_mpdu = NULL; 2555 2556 /* 2557 * Return the list of ath_buf of this mpdu to free queue 2558 */ 2559 spin_lock_irqsave(&sc->tx.txbuflock, flags); 2560 list_splice_tail_init(bf_q, &sc->tx.txbuf); 2561 spin_unlock_irqrestore(&sc->tx.txbuflock, flags); 2562 } 2563 2564 static void ath_clear_tx_status(struct ieee80211_tx_info *tx_info) 2565 { 2566 void *ptr = &tx_info->status; 2567 2568 memset(ptr + sizeof(tx_info->status.rates), 0, 2569 sizeof(tx_info->status) - 2570 sizeof(tx_info->status.rates) - 2571 sizeof(tx_info->status.status_driver_data)); 2572 } 2573 2574 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, 2575 struct ath_tx_status *ts, int nframes, int nbad, 2576 int txok) 2577 { 2578 struct sk_buff *skb = bf->bf_mpdu; 2579 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2580 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2581 struct ieee80211_hw *hw = sc->hw; 2582 struct ath_hw *ah = sc->sc_ah; 2583 u8 i, tx_rateindex; 2584 2585 ath_clear_tx_status(tx_info); 2586 2587 if (txok) 2588 tx_info->status.ack_signal = ts->ts_rssi; 2589 2590 tx_rateindex = ts->ts_rateindex; 2591 WARN_ON(tx_rateindex >= hw->max_rates); 2592 2593 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { 2594 tx_info->flags |= IEEE80211_TX_STAT_AMPDU; 2595 2596 BUG_ON(nbad > nframes); 2597 } 2598 tx_info->status.ampdu_len = nframes; 2599 tx_info->status.ampdu_ack_len = nframes - nbad; 2600 2601 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1; 2602 2603 for (i = tx_rateindex + 1; i < hw->max_rates; i++) { 2604 tx_info->status.rates[i].count = 0; 2605 tx_info->status.rates[i].idx = -1; 2606 } 2607 2608 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 && 2609 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) { 2610 /* 2611 * If an underrun error is seen assume it as an excessive 2612 * retry only if max frame trigger level has been reached 2613 * (2 KB for single stream, and 4 KB for dual stream). 2614 * Adjust the long retry as if the frame was tried 2615 * hw->max_rate_tries times to affect how rate control updates 2616 * PER for the failed rate. 2617 * In case of congestion on the bus penalizing this type of 2618 * underruns should help hardware actually transmit new frames 2619 * successfully by eventually preferring slower rates. 2620 * This itself should also alleviate congestion on the bus. 2621 */ 2622 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN | 2623 ATH9K_TX_DELIM_UNDERRUN)) && 2624 ieee80211_is_data(hdr->frame_control) && 2625 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level) 2626 tx_info->status.rates[tx_rateindex].count = 2627 hw->max_rate_tries; 2628 } 2629 } 2630 2631 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 2632 { 2633 struct ath_hw *ah = sc->sc_ah; 2634 struct ath_common *common = ath9k_hw_common(ah); 2635 struct ath_buf *bf, *lastbf, *bf_held = NULL; 2636 struct list_head bf_head; 2637 struct ath_desc *ds; 2638 struct ath_tx_status ts; 2639 int status; 2640 2641 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n", 2642 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), 2643 txq->axq_link); 2644 2645 ath_txq_lock(sc, txq); 2646 for (;;) { 2647 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) 2648 break; 2649 2650 if (list_empty(&txq->axq_q)) { 2651 txq->axq_link = NULL; 2652 ath_txq_schedule(sc, txq); 2653 break; 2654 } 2655 bf = list_first_entry(&txq->axq_q, struct ath_buf, list); 2656 2657 /* 2658 * There is a race condition that a BH gets scheduled 2659 * after sw writes TxE and before hw re-load the last 2660 * descriptor to get the newly chained one. 2661 * Software must keep the last DONE descriptor as a 2662 * holding descriptor - software does so by marking 2663 * it with the STALE flag. 2664 */ 2665 bf_held = NULL; 2666 if (bf->bf_state.stale) { 2667 bf_held = bf; 2668 if (list_is_last(&bf_held->list, &txq->axq_q)) 2669 break; 2670 2671 bf = list_entry(bf_held->list.next, struct ath_buf, 2672 list); 2673 } 2674 2675 lastbf = bf->bf_lastbf; 2676 ds = lastbf->bf_desc; 2677 2678 memset(&ts, 0, sizeof(ts)); 2679 status = ath9k_hw_txprocdesc(ah, ds, &ts); 2680 if (status == -EINPROGRESS) 2681 break; 2682 2683 TX_STAT_INC(sc, txq->axq_qnum, txprocdesc); 2684 2685 /* 2686 * Remove ath_buf's of the same transmit unit from txq, 2687 * however leave the last descriptor back as the holding 2688 * descriptor for hw. 2689 */ 2690 lastbf->bf_state.stale = true; 2691 INIT_LIST_HEAD(&bf_head); 2692 if (!list_is_singular(&lastbf->list)) 2693 list_cut_position(&bf_head, 2694 &txq->axq_q, lastbf->list.prev); 2695 2696 if (bf_held) { 2697 list_del(&bf_held->list); 2698 ath_tx_return_buffer(sc, bf_held); 2699 } 2700 2701 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); 2702 } 2703 ath_txq_unlock_complete(sc, txq); 2704 } 2705 2706 void ath_tx_tasklet(struct ath_softc *sc) 2707 { 2708 struct ath_hw *ah = sc->sc_ah; 2709 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs; 2710 int i; 2711 2712 rcu_read_lock(); 2713 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 2714 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) 2715 ath_tx_processq(sc, &sc->tx.txq[i]); 2716 } 2717 rcu_read_unlock(); 2718 } 2719 2720 void ath_tx_edma_tasklet(struct ath_softc *sc) 2721 { 2722 struct ath_tx_status ts; 2723 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2724 struct ath_hw *ah = sc->sc_ah; 2725 struct ath_txq *txq; 2726 struct ath_buf *bf, *lastbf; 2727 struct list_head bf_head; 2728 struct list_head *fifo_list; 2729 int status; 2730 2731 rcu_read_lock(); 2732 for (;;) { 2733 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) 2734 break; 2735 2736 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts); 2737 if (status == -EINPROGRESS) 2738 break; 2739 if (status == -EIO) { 2740 ath_dbg(common, XMIT, "Error processing tx status\n"); 2741 break; 2742 } 2743 2744 /* Process beacon completions separately */ 2745 if (ts.qid == sc->beacon.beaconq) { 2746 sc->beacon.tx_processed = true; 2747 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); 2748 2749 if (ath9k_is_chanctx_enabled()) { 2750 ath_chanctx_event(sc, NULL, 2751 ATH_CHANCTX_EVENT_BEACON_SENT); 2752 } 2753 2754 ath9k_csa_update(sc); 2755 continue; 2756 } 2757 2758 txq = &sc->tx.txq[ts.qid]; 2759 2760 ath_txq_lock(sc, txq); 2761 2762 TX_STAT_INC(sc, txq->axq_qnum, txprocdesc); 2763 2764 fifo_list = &txq->txq_fifo[txq->txq_tailidx]; 2765 if (list_empty(fifo_list)) { 2766 ath_txq_unlock(sc, txq); 2767 break; 2768 } 2769 2770 bf = list_first_entry(fifo_list, struct ath_buf, list); 2771 if (bf->bf_state.stale) { 2772 list_del(&bf->list); 2773 ath_tx_return_buffer(sc, bf); 2774 bf = list_first_entry(fifo_list, struct ath_buf, list); 2775 } 2776 2777 lastbf = bf->bf_lastbf; 2778 2779 INIT_LIST_HEAD(&bf_head); 2780 if (list_is_last(&lastbf->list, fifo_list)) { 2781 list_splice_tail_init(fifo_list, &bf_head); 2782 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH); 2783 2784 if (!list_empty(&txq->axq_q)) { 2785 struct list_head bf_q; 2786 2787 INIT_LIST_HEAD(&bf_q); 2788 txq->axq_link = NULL; 2789 list_splice_tail_init(&txq->axq_q, &bf_q); 2790 ath_tx_txqaddbuf(sc, txq, &bf_q, true); 2791 } 2792 } else { 2793 lastbf->bf_state.stale = true; 2794 if (bf != lastbf) 2795 list_cut_position(&bf_head, fifo_list, 2796 lastbf->list.prev); 2797 } 2798 2799 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); 2800 ath_txq_unlock_complete(sc, txq); 2801 } 2802 rcu_read_unlock(); 2803 } 2804 2805 /*****************/ 2806 /* Init, Cleanup */ 2807 /*****************/ 2808 2809 static int ath_txstatus_setup(struct ath_softc *sc, int size) 2810 { 2811 struct ath_descdma *dd = &sc->txsdma; 2812 u8 txs_len = sc->sc_ah->caps.txs_len; 2813 2814 dd->dd_desc_len = size * txs_len; 2815 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len, 2816 &dd->dd_desc_paddr, GFP_KERNEL); 2817 if (!dd->dd_desc) 2818 return -ENOMEM; 2819 2820 return 0; 2821 } 2822 2823 static int ath_tx_edma_init(struct ath_softc *sc) 2824 { 2825 int err; 2826 2827 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE); 2828 if (!err) 2829 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc, 2830 sc->txsdma.dd_desc_paddr, 2831 ATH_TXSTATUS_RING_SIZE); 2832 2833 return err; 2834 } 2835 2836 int ath_tx_init(struct ath_softc *sc, int nbufs) 2837 { 2838 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2839 int error = 0; 2840 2841 spin_lock_init(&sc->tx.txbuflock); 2842 2843 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, 2844 "tx", nbufs, 1, 1); 2845 if (error != 0) { 2846 ath_err(common, 2847 "Failed to allocate tx descriptors: %d\n", error); 2848 return error; 2849 } 2850 2851 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, 2852 "beacon", ATH_BCBUF, 1, 1); 2853 if (error != 0) { 2854 ath_err(common, 2855 "Failed to allocate beacon descriptors: %d\n", error); 2856 return error; 2857 } 2858 2859 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 2860 error = ath_tx_edma_init(sc); 2861 2862 return error; 2863 } 2864 2865 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) 2866 { 2867 struct ath_atx_tid *tid; 2868 int tidno, acno; 2869 2870 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) { 2871 tid = ath_node_to_tid(an, tidno); 2872 tid->an = an; 2873 tid->tidno = tidno; 2874 tid->seq_start = tid->seq_next = 0; 2875 tid->baw_size = WME_MAX_BA; 2876 tid->baw_head = tid->baw_tail = 0; 2877 tid->active = false; 2878 tid->clear_ps_filter = true; 2879 __skb_queue_head_init(&tid->retry_q); 2880 INIT_LIST_HEAD(&tid->list); 2881 acno = TID_TO_WME_AC(tidno); 2882 tid->txq = sc->tx.txq_map[acno]; 2883 2884 if (!an->sta) 2885 break; /* just one multicast ath_atx_tid */ 2886 } 2887 } 2888 2889 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) 2890 { 2891 struct ath_atx_tid *tid; 2892 struct ath_txq *txq; 2893 int tidno; 2894 2895 rcu_read_lock(); 2896 2897 for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) { 2898 tid = ath_node_to_tid(an, tidno); 2899 txq = tid->txq; 2900 2901 ath_txq_lock(sc, txq); 2902 2903 if (!list_empty(&tid->list)) 2904 list_del_init(&tid->list); 2905 2906 ath_tid_drain(sc, txq, tid); 2907 tid->active = false; 2908 2909 ath_txq_unlock(sc, txq); 2910 2911 if (!an->sta) 2912 break; /* just one multicast ath_atx_tid */ 2913 } 2914 2915 rcu_read_unlock(); 2916 } 2917 2918 #ifdef CONFIG_ATH9K_TX99 2919 2920 int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb, 2921 struct ath_tx_control *txctl) 2922 { 2923 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 2924 struct ath_frame_info *fi = get_frame_info(skb); 2925 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2926 struct ath_buf *bf; 2927 int padpos, padsize; 2928 2929 padpos = ieee80211_hdrlen(hdr->frame_control); 2930 padsize = padpos & 3; 2931 2932 if (padsize && skb->len > padpos) { 2933 if (skb_headroom(skb) < padsize) { 2934 ath_dbg(common, XMIT, 2935 "tx99 padding failed\n"); 2936 return -EINVAL; 2937 } 2938 2939 skb_push(skb, padsize); 2940 memmove(skb->data, skb->data + padsize, padpos); 2941 } 2942 2943 fi->keyix = ATH9K_TXKEYIX_INVALID; 2944 fi->framelen = skb->len + FCS_LEN; 2945 fi->keytype = ATH9K_KEY_TYPE_CLEAR; 2946 2947 bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb); 2948 if (!bf) { 2949 ath_dbg(common, XMIT, "tx99 buffer setup failed\n"); 2950 return -EINVAL; 2951 } 2952 2953 ath_set_rates(sc->tx99_vif, NULL, bf); 2954 2955 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr); 2956 ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum); 2957 2958 ath_tx_send_normal(sc, txctl->txq, NULL, skb); 2959 2960 return 0; 2961 } 2962 2963 #endif /* CONFIG_ATH9K_TX99 */ 2964