1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/dma-mapping.h> 18 #include "ath9k.h" 19 #include "ar9003_mac.h" 20 21 #define BITS_PER_BYTE 8 22 #define OFDM_PLCP_BITS 22 23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) 24 #define L_STF 8 25 #define L_LTF 8 26 #define L_SIG 4 27 #define HT_SIG 8 28 #define HT_STF 4 29 #define HT_LTF(_ns) (4 * (_ns)) 30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ 31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ 32 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) 33 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) 34 35 36 static u16 bits_per_symbol[][2] = { 37 /* 20MHz 40MHz */ 38 { 26, 54 }, /* 0: BPSK */ 39 { 52, 108 }, /* 1: QPSK 1/2 */ 40 { 78, 162 }, /* 2: QPSK 3/4 */ 41 { 104, 216 }, /* 3: 16-QAM 1/2 */ 42 { 156, 324 }, /* 4: 16-QAM 3/4 */ 43 { 208, 432 }, /* 5: 64-QAM 2/3 */ 44 { 234, 486 }, /* 6: 64-QAM 3/4 */ 45 { 260, 540 }, /* 7: 64-QAM 5/6 */ 46 }; 47 48 #define IS_HT_RATE(_rate) ((_rate) & 0x80) 49 50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, 51 struct ath_atx_tid *tid, struct sk_buff *skb); 52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, 53 int tx_flags, struct ath_txq *txq); 54 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 55 struct ath_txq *txq, struct list_head *bf_q, 56 struct ath_tx_status *ts, int txok); 57 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 58 struct list_head *head, bool internal); 59 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, 60 struct ath_tx_status *ts, int nframes, int nbad, 61 int txok); 62 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 63 int seqno); 64 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, 65 struct ath_txq *txq, 66 struct ath_atx_tid *tid, 67 struct sk_buff *skb); 68 69 enum { 70 MCS_HT20, 71 MCS_HT20_SGI, 72 MCS_HT40, 73 MCS_HT40_SGI, 74 }; 75 76 static int ath_max_4ms_framelen[4][32] = { 77 [MCS_HT20] = { 78 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172, 79 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280, 80 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532, 81 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532, 82 }, 83 [MCS_HT20_SGI] = { 84 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744, 85 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532, 86 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532, 87 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532, 88 }, 89 [MCS_HT40] = { 90 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532, 91 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532, 92 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532, 93 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532, 94 }, 95 [MCS_HT40_SGI] = { 96 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532, 97 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532, 98 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532, 99 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532, 100 } 101 }; 102 103 /*********************/ 104 /* Aggregation logic */ 105 /*********************/ 106 107 static void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq) 108 __acquires(&txq->axq_lock) 109 { 110 spin_lock_bh(&txq->axq_lock); 111 } 112 113 static void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq) 114 __releases(&txq->axq_lock) 115 { 116 spin_unlock_bh(&txq->axq_lock); 117 } 118 119 static void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq) 120 __releases(&txq->axq_lock) 121 { 122 struct sk_buff_head q; 123 struct sk_buff *skb; 124 125 __skb_queue_head_init(&q); 126 skb_queue_splice_init(&txq->complete_q, &q); 127 spin_unlock_bh(&txq->axq_lock); 128 129 while ((skb = __skb_dequeue(&q))) 130 ieee80211_tx_status(sc->hw, skb); 131 } 132 133 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid) 134 { 135 struct ath_atx_ac *ac = tid->ac; 136 137 if (tid->paused) 138 return; 139 140 if (tid->sched) 141 return; 142 143 tid->sched = true; 144 list_add_tail(&tid->list, &ac->tid_q); 145 146 if (ac->sched) 147 return; 148 149 ac->sched = true; 150 list_add_tail(&ac->list, &txq->axq_acq); 151 } 152 153 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 154 { 155 struct ath_txq *txq = tid->ac->txq; 156 157 WARN_ON(!tid->paused); 158 159 ath_txq_lock(sc, txq); 160 tid->paused = false; 161 162 if (skb_queue_empty(&tid->buf_q)) 163 goto unlock; 164 165 ath_tx_queue_tid(txq, tid); 166 ath_txq_schedule(sc, txq); 167 unlock: 168 ath_txq_unlock_complete(sc, txq); 169 } 170 171 static struct ath_frame_info *get_frame_info(struct sk_buff *skb) 172 { 173 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 174 BUILD_BUG_ON(sizeof(struct ath_frame_info) > 175 sizeof(tx_info->rate_driver_data)); 176 return (struct ath_frame_info *) &tx_info->rate_driver_data[0]; 177 } 178 179 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno) 180 { 181 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno, 182 seqno << IEEE80211_SEQ_SEQ_SHIFT); 183 } 184 185 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 186 { 187 struct ath_txq *txq = tid->ac->txq; 188 struct sk_buff *skb; 189 struct ath_buf *bf; 190 struct list_head bf_head; 191 struct ath_tx_status ts; 192 struct ath_frame_info *fi; 193 bool sendbar = false; 194 195 INIT_LIST_HEAD(&bf_head); 196 197 memset(&ts, 0, sizeof(ts)); 198 199 while ((skb = __skb_dequeue(&tid->buf_q))) { 200 fi = get_frame_info(skb); 201 bf = fi->bf; 202 203 if (bf && fi->retries) { 204 list_add_tail(&bf->list, &bf_head); 205 ath_tx_update_baw(sc, tid, bf->bf_state.seqno); 206 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0); 207 sendbar = true; 208 } else { 209 ath_tx_send_normal(sc, txq, NULL, skb); 210 } 211 } 212 213 if (tid->baw_head == tid->baw_tail) { 214 tid->state &= ~AGGR_ADDBA_COMPLETE; 215 tid->state &= ~AGGR_CLEANUP; 216 } 217 218 if (sendbar) { 219 ath_txq_unlock(sc, txq); 220 ath_send_bar(tid, tid->seq_start); 221 ath_txq_lock(sc, txq); 222 } 223 } 224 225 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 226 int seqno) 227 { 228 int index, cindex; 229 230 index = ATH_BA_INDEX(tid->seq_start, seqno); 231 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 232 233 __clear_bit(cindex, tid->tx_buf); 234 235 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) { 236 INCR(tid->seq_start, IEEE80211_SEQ_MAX); 237 INCR(tid->baw_head, ATH_TID_MAX_BUFS); 238 if (tid->bar_index >= 0) 239 tid->bar_index--; 240 } 241 } 242 243 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 244 u16 seqno) 245 { 246 int index, cindex; 247 248 index = ATH_BA_INDEX(tid->seq_start, seqno); 249 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 250 __set_bit(cindex, tid->tx_buf); 251 252 if (index >= ((tid->baw_tail - tid->baw_head) & 253 (ATH_TID_MAX_BUFS - 1))) { 254 tid->baw_tail = cindex; 255 INCR(tid->baw_tail, ATH_TID_MAX_BUFS); 256 } 257 } 258 259 /* 260 * TODO: For frame(s) that are in the retry state, we will reuse the 261 * sequence number(s) without setting the retry bit. The 262 * alternative is to give up on these and BAR the receiver's window 263 * forward. 264 */ 265 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq, 266 struct ath_atx_tid *tid) 267 268 { 269 struct sk_buff *skb; 270 struct ath_buf *bf; 271 struct list_head bf_head; 272 struct ath_tx_status ts; 273 struct ath_frame_info *fi; 274 275 memset(&ts, 0, sizeof(ts)); 276 INIT_LIST_HEAD(&bf_head); 277 278 while ((skb = __skb_dequeue(&tid->buf_q))) { 279 fi = get_frame_info(skb); 280 bf = fi->bf; 281 282 if (!bf) { 283 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq); 284 continue; 285 } 286 287 list_add_tail(&bf->list, &bf_head); 288 289 if (fi->retries) 290 ath_tx_update_baw(sc, tid, bf->bf_state.seqno); 291 292 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0); 293 } 294 295 tid->seq_next = tid->seq_start; 296 tid->baw_tail = tid->baw_head; 297 tid->bar_index = -1; 298 } 299 300 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq, 301 struct sk_buff *skb, int count) 302 { 303 struct ath_frame_info *fi = get_frame_info(skb); 304 struct ath_buf *bf = fi->bf; 305 struct ieee80211_hdr *hdr; 306 int prev = fi->retries; 307 308 TX_STAT_INC(txq->axq_qnum, a_retries); 309 fi->retries += count; 310 311 if (prev > 0) 312 return; 313 314 hdr = (struct ieee80211_hdr *)skb->data; 315 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); 316 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, 317 sizeof(*hdr), DMA_TO_DEVICE); 318 } 319 320 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) 321 { 322 struct ath_buf *bf = NULL; 323 324 spin_lock_bh(&sc->tx.txbuflock); 325 326 if (unlikely(list_empty(&sc->tx.txbuf))) { 327 spin_unlock_bh(&sc->tx.txbuflock); 328 return NULL; 329 } 330 331 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); 332 list_del(&bf->list); 333 334 spin_unlock_bh(&sc->tx.txbuflock); 335 336 return bf; 337 } 338 339 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf) 340 { 341 spin_lock_bh(&sc->tx.txbuflock); 342 list_add_tail(&bf->list, &sc->tx.txbuf); 343 spin_unlock_bh(&sc->tx.txbuflock); 344 } 345 346 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf) 347 { 348 struct ath_buf *tbf; 349 350 tbf = ath_tx_get_buffer(sc); 351 if (WARN_ON(!tbf)) 352 return NULL; 353 354 ATH_TXBUF_RESET(tbf); 355 356 tbf->bf_mpdu = bf->bf_mpdu; 357 tbf->bf_buf_addr = bf->bf_buf_addr; 358 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len); 359 tbf->bf_state = bf->bf_state; 360 361 return tbf; 362 } 363 364 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf, 365 struct ath_tx_status *ts, int txok, 366 int *nframes, int *nbad) 367 { 368 struct ath_frame_info *fi; 369 u16 seq_st = 0; 370 u32 ba[WME_BA_BMP_SIZE >> 5]; 371 int ba_index; 372 int isaggr = 0; 373 374 *nbad = 0; 375 *nframes = 0; 376 377 isaggr = bf_isaggr(bf); 378 if (isaggr) { 379 seq_st = ts->ts_seqnum; 380 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); 381 } 382 383 while (bf) { 384 fi = get_frame_info(bf->bf_mpdu); 385 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno); 386 387 (*nframes)++; 388 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) 389 (*nbad)++; 390 391 bf = bf->bf_next; 392 } 393 } 394 395 396 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, 397 struct ath_buf *bf, struct list_head *bf_q, 398 struct ath_tx_status *ts, int txok, bool retry) 399 { 400 struct ath_node *an = NULL; 401 struct sk_buff *skb; 402 struct ieee80211_sta *sta; 403 struct ieee80211_hw *hw = sc->hw; 404 struct ieee80211_hdr *hdr; 405 struct ieee80211_tx_info *tx_info; 406 struct ath_atx_tid *tid = NULL; 407 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; 408 struct list_head bf_head; 409 struct sk_buff_head bf_pending; 410 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first; 411 u32 ba[WME_BA_BMP_SIZE >> 5]; 412 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0; 413 bool rc_update = true; 414 struct ieee80211_tx_rate rates[4]; 415 struct ath_frame_info *fi; 416 int nframes; 417 u8 tidno; 418 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH); 419 int i, retries; 420 int bar_index = -1; 421 422 skb = bf->bf_mpdu; 423 hdr = (struct ieee80211_hdr *)skb->data; 424 425 tx_info = IEEE80211_SKB_CB(skb); 426 427 memcpy(rates, tx_info->control.rates, sizeof(rates)); 428 429 retries = ts->ts_longretry + 1; 430 for (i = 0; i < ts->ts_rateindex; i++) 431 retries += rates[i].count; 432 433 rcu_read_lock(); 434 435 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2); 436 if (!sta) { 437 rcu_read_unlock(); 438 439 INIT_LIST_HEAD(&bf_head); 440 while (bf) { 441 bf_next = bf->bf_next; 442 443 if (!bf->bf_stale || bf_next != NULL) 444 list_move_tail(&bf->list, &bf_head); 445 446 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0); 447 448 bf = bf_next; 449 } 450 return; 451 } 452 453 an = (struct ath_node *)sta->drv_priv; 454 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK; 455 tid = ATH_AN_2_TID(an, tidno); 456 seq_first = tid->seq_start; 457 458 /* 459 * The hardware occasionally sends a tx status for the wrong TID. 460 * In this case, the BA status cannot be considered valid and all 461 * subframes need to be retransmitted 462 */ 463 if (tidno != ts->tid) 464 txok = false; 465 466 isaggr = bf_isaggr(bf); 467 memset(ba, 0, WME_BA_BMP_SIZE >> 3); 468 469 if (isaggr && txok) { 470 if (ts->ts_flags & ATH9K_TX_BA) { 471 seq_st = ts->ts_seqnum; 472 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); 473 } else { 474 /* 475 * AR5416 can become deaf/mute when BA 476 * issue happens. Chip needs to be reset. 477 * But AP code may have sychronization issues 478 * when perform internal reset in this routine. 479 * Only enable reset in STA mode for now. 480 */ 481 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) 482 needreset = 1; 483 } 484 } 485 486 __skb_queue_head_init(&bf_pending); 487 488 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad); 489 while (bf) { 490 u16 seqno = bf->bf_state.seqno; 491 492 txfail = txpending = sendbar = 0; 493 bf_next = bf->bf_next; 494 495 skb = bf->bf_mpdu; 496 tx_info = IEEE80211_SKB_CB(skb); 497 fi = get_frame_info(skb); 498 499 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) { 500 /* transmit completion, subframe is 501 * acked by block ack */ 502 acked_cnt++; 503 } else if (!isaggr && txok) { 504 /* transmit completion */ 505 acked_cnt++; 506 } else if ((tid->state & AGGR_CLEANUP) || !retry) { 507 /* 508 * cleanup in progress, just fail 509 * the un-acked sub-frames 510 */ 511 txfail = 1; 512 } else if (flush) { 513 txpending = 1; 514 } else if (fi->retries < ATH_MAX_SW_RETRIES) { 515 if (txok || !an->sleeping) 516 ath_tx_set_retry(sc, txq, bf->bf_mpdu, 517 retries); 518 519 txpending = 1; 520 } else { 521 txfail = 1; 522 txfail_cnt++; 523 bar_index = max_t(int, bar_index, 524 ATH_BA_INDEX(seq_first, seqno)); 525 } 526 527 /* 528 * Make sure the last desc is reclaimed if it 529 * not a holding desc. 530 */ 531 INIT_LIST_HEAD(&bf_head); 532 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) || 533 bf_next != NULL || !bf_last->bf_stale) 534 list_move_tail(&bf->list, &bf_head); 535 536 if (!txpending || (tid->state & AGGR_CLEANUP)) { 537 /* 538 * complete the acked-ones/xretried ones; update 539 * block-ack window 540 */ 541 ath_tx_update_baw(sc, tid, seqno); 542 543 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) { 544 memcpy(tx_info->control.rates, rates, sizeof(rates)); 545 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok); 546 rc_update = false; 547 } 548 549 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 550 !txfail); 551 } else { 552 /* retry the un-acked ones */ 553 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 554 bf->bf_next == NULL && bf_last->bf_stale) { 555 struct ath_buf *tbf; 556 557 tbf = ath_clone_txbuf(sc, bf_last); 558 /* 559 * Update tx baw and complete the 560 * frame with failed status if we 561 * run out of tx buf. 562 */ 563 if (!tbf) { 564 ath_tx_update_baw(sc, tid, seqno); 565 566 ath_tx_complete_buf(sc, bf, txq, 567 &bf_head, ts, 0); 568 bar_index = max_t(int, bar_index, 569 ATH_BA_INDEX(seq_first, seqno)); 570 break; 571 } 572 573 fi->bf = tbf; 574 } 575 576 /* 577 * Put this buffer to the temporary pending 578 * queue to retain ordering 579 */ 580 __skb_queue_tail(&bf_pending, skb); 581 } 582 583 bf = bf_next; 584 } 585 586 /* prepend un-acked frames to the beginning of the pending frame queue */ 587 if (!skb_queue_empty(&bf_pending)) { 588 if (an->sleeping) 589 ieee80211_sta_set_buffered(sta, tid->tidno, true); 590 591 skb_queue_splice(&bf_pending, &tid->buf_q); 592 if (!an->sleeping) { 593 ath_tx_queue_tid(txq, tid); 594 595 if (ts->ts_status & ATH9K_TXERR_FILT) 596 tid->ac->clear_ps_filter = true; 597 } 598 } 599 600 if (bar_index >= 0) { 601 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index); 602 603 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq)) 604 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq); 605 606 ath_txq_unlock(sc, txq); 607 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1)); 608 ath_txq_lock(sc, txq); 609 } 610 611 if (tid->state & AGGR_CLEANUP) 612 ath_tx_flush_tid(sc, tid); 613 614 rcu_read_unlock(); 615 616 if (needreset) { 617 RESET_STAT_INC(sc, RESET_TYPE_TX_ERROR); 618 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 619 } 620 } 621 622 static bool ath_lookup_legacy(struct ath_buf *bf) 623 { 624 struct sk_buff *skb; 625 struct ieee80211_tx_info *tx_info; 626 struct ieee80211_tx_rate *rates; 627 int i; 628 629 skb = bf->bf_mpdu; 630 tx_info = IEEE80211_SKB_CB(skb); 631 rates = tx_info->control.rates; 632 633 for (i = 0; i < 4; i++) { 634 if (!rates[i].count || rates[i].idx < 0) 635 break; 636 637 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) 638 return true; 639 } 640 641 return false; 642 } 643 644 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, 645 struct ath_atx_tid *tid) 646 { 647 struct sk_buff *skb; 648 struct ieee80211_tx_info *tx_info; 649 struct ieee80211_tx_rate *rates; 650 struct ath_mci_profile *mci = &sc->btcoex.mci; 651 u32 max_4ms_framelen, frmlen; 652 u16 aggr_limit, legacy = 0; 653 int i; 654 655 skb = bf->bf_mpdu; 656 tx_info = IEEE80211_SKB_CB(skb); 657 rates = tx_info->control.rates; 658 659 /* 660 * Find the lowest frame length among the rate series that will have a 661 * 4ms transmit duration. 662 * TODO - TXOP limit needs to be considered. 663 */ 664 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; 665 666 for (i = 0; i < 4; i++) { 667 int modeidx; 668 669 if (!rates[i].count) 670 continue; 671 672 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) { 673 legacy = 1; 674 break; 675 } 676 677 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 678 modeidx = MCS_HT40; 679 else 680 modeidx = MCS_HT20; 681 682 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) 683 modeidx++; 684 685 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx]; 686 max_4ms_framelen = min(max_4ms_framelen, frmlen); 687 } 688 689 /* 690 * limit aggregate size by the minimum rate if rate selected is 691 * not a probe rate, if rate selected is a probe rate then 692 * avoid aggregation of this packet. 693 */ 694 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) 695 return 0; 696 697 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI) && mci->aggr_limit) 698 aggr_limit = (max_4ms_framelen * mci->aggr_limit) >> 4; 699 else if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED) 700 aggr_limit = min((max_4ms_framelen * 3) / 8, 701 (u32)ATH_AMPDU_LIMIT_MAX); 702 else 703 aggr_limit = min(max_4ms_framelen, 704 (u32)ATH_AMPDU_LIMIT_MAX); 705 706 /* 707 * h/w can accept aggregates up to 16 bit lengths (65535). 708 * The IE, however can hold up to 65536, which shows up here 709 * as zero. Ignore 65536 since we are constrained by hw. 710 */ 711 if (tid->an->maxampdu) 712 aggr_limit = min(aggr_limit, tid->an->maxampdu); 713 714 return aggr_limit; 715 } 716 717 /* 718 * Returns the number of delimiters to be added to 719 * meet the minimum required mpdudensity. 720 */ 721 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, 722 struct ath_buf *bf, u16 frmlen, 723 bool first_subfrm) 724 { 725 #define FIRST_DESC_NDELIMS 60 726 struct sk_buff *skb = bf->bf_mpdu; 727 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 728 u32 nsymbits, nsymbols; 729 u16 minlen; 730 u8 flags, rix; 731 int width, streams, half_gi, ndelim, mindelim; 732 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 733 734 /* Select standard number of delimiters based on frame length alone */ 735 ndelim = ATH_AGGR_GET_NDELIM(frmlen); 736 737 /* 738 * If encryption enabled, hardware requires some more padding between 739 * subframes. 740 * TODO - this could be improved to be dependent on the rate. 741 * The hardware can keep up at lower rates, but not higher rates 742 */ 743 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) && 744 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) 745 ndelim += ATH_AGGR_ENCRYPTDELIM; 746 747 /* 748 * Add delimiter when using RTS/CTS with aggregation 749 * and non enterprise AR9003 card 750 */ 751 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) && 752 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE)) 753 ndelim = max(ndelim, FIRST_DESC_NDELIMS); 754 755 /* 756 * Convert desired mpdu density from microeconds to bytes based 757 * on highest rate in rate series (i.e. first rate) to determine 758 * required minimum length for subframe. Take into account 759 * whether high rate is 20 or 40Mhz and half or full GI. 760 * 761 * If there is no mpdu density restriction, no further calculation 762 * is needed. 763 */ 764 765 if (tid->an->mpdudensity == 0) 766 return ndelim; 767 768 rix = tx_info->control.rates[0].idx; 769 flags = tx_info->control.rates[0].flags; 770 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; 771 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; 772 773 if (half_gi) 774 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity); 775 else 776 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity); 777 778 if (nsymbols == 0) 779 nsymbols = 1; 780 781 streams = HT_RC_2_STREAMS(rix); 782 nsymbits = bits_per_symbol[rix % 8][width] * streams; 783 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; 784 785 if (frmlen < minlen) { 786 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; 787 ndelim = max(mindelim, ndelim); 788 } 789 790 return ndelim; 791 } 792 793 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, 794 struct ath_txq *txq, 795 struct ath_atx_tid *tid, 796 struct list_head *bf_q, 797 int *aggr_len) 798 { 799 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) 800 struct ath_buf *bf, *bf_first = NULL, *bf_prev = NULL; 801 int rl = 0, nframes = 0, ndelim, prev_al = 0; 802 u16 aggr_limit = 0, al = 0, bpad = 0, 803 al_delta, h_baw = tid->baw_size / 2; 804 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE; 805 struct ieee80211_tx_info *tx_info; 806 struct ath_frame_info *fi; 807 struct sk_buff *skb; 808 u16 seqno; 809 810 do { 811 skb = skb_peek(&tid->buf_q); 812 fi = get_frame_info(skb); 813 bf = fi->bf; 814 if (!fi->bf) 815 bf = ath_tx_setup_buffer(sc, txq, tid, skb); 816 817 if (!bf) 818 continue; 819 820 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR; 821 seqno = bf->bf_state.seqno; 822 823 /* do not step over block-ack window */ 824 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) { 825 status = ATH_AGGR_BAW_CLOSED; 826 break; 827 } 828 829 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) { 830 struct ath_tx_status ts = {}; 831 struct list_head bf_head; 832 833 INIT_LIST_HEAD(&bf_head); 834 list_add(&bf->list, &bf_head); 835 __skb_unlink(skb, &tid->buf_q); 836 ath_tx_update_baw(sc, tid, seqno); 837 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0); 838 continue; 839 } 840 841 if (!bf_first) 842 bf_first = bf; 843 844 if (!rl) { 845 aggr_limit = ath_lookup_rate(sc, bf, tid); 846 rl = 1; 847 } 848 849 /* do not exceed aggregation limit */ 850 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen; 851 852 if (nframes && 853 ((aggr_limit < (al + bpad + al_delta + prev_al)) || 854 ath_lookup_legacy(bf))) { 855 status = ATH_AGGR_LIMITED; 856 break; 857 } 858 859 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 860 if (nframes && (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) 861 break; 862 863 /* do not exceed subframe limit */ 864 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) { 865 status = ATH_AGGR_LIMITED; 866 break; 867 } 868 869 /* add padding for previous frame to aggregation length */ 870 al += bpad + al_delta; 871 872 /* 873 * Get the delimiters needed to meet the MPDU 874 * density for this node. 875 */ 876 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen, 877 !nframes); 878 bpad = PADBYTES(al_delta) + (ndelim << 2); 879 880 nframes++; 881 bf->bf_next = NULL; 882 883 /* link buffers of this frame to the aggregate */ 884 if (!fi->retries) 885 ath_tx_addto_baw(sc, tid, seqno); 886 bf->bf_state.ndelim = ndelim; 887 888 __skb_unlink(skb, &tid->buf_q); 889 list_add_tail(&bf->list, bf_q); 890 if (bf_prev) 891 bf_prev->bf_next = bf; 892 893 bf_prev = bf; 894 895 } while (!skb_queue_empty(&tid->buf_q)); 896 897 *aggr_len = al; 898 899 return status; 900 #undef PADBYTES 901 } 902 903 /* 904 * rix - rate index 905 * pktlen - total bytes (delims + data + fcs + pads + pad delims) 906 * width - 0 for 20 MHz, 1 for 40 MHz 907 * half_gi - to use 4us v/s 3.6 us for symbol time 908 */ 909 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen, 910 int width, int half_gi, bool shortPreamble) 911 { 912 u32 nbits, nsymbits, duration, nsymbols; 913 int streams; 914 915 /* find number of symbols: PLCP + data */ 916 streams = HT_RC_2_STREAMS(rix); 917 nbits = (pktlen << 3) + OFDM_PLCP_BITS; 918 nsymbits = bits_per_symbol[rix % 8][width] * streams; 919 nsymbols = (nbits + nsymbits - 1) / nsymbits; 920 921 if (!half_gi) 922 duration = SYMBOL_TIME(nsymbols); 923 else 924 duration = SYMBOL_TIME_HALFGI(nsymbols); 925 926 /* addup duration for legacy/ht training and signal fields */ 927 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); 928 929 return duration; 930 } 931 932 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, 933 struct ath_tx_info *info, int len) 934 { 935 struct ath_hw *ah = sc->sc_ah; 936 struct sk_buff *skb; 937 struct ieee80211_tx_info *tx_info; 938 struct ieee80211_tx_rate *rates; 939 const struct ieee80211_rate *rate; 940 struct ieee80211_hdr *hdr; 941 int i; 942 u8 rix = 0; 943 944 skb = bf->bf_mpdu; 945 tx_info = IEEE80211_SKB_CB(skb); 946 rates = tx_info->control.rates; 947 hdr = (struct ieee80211_hdr *)skb->data; 948 949 /* set dur_update_en for l-sig computation except for PS-Poll frames */ 950 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control); 951 952 /* 953 * We check if Short Preamble is needed for the CTS rate by 954 * checking the BSS's global flag. 955 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. 956 */ 957 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info); 958 info->rtscts_rate = rate->hw_value; 959 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT) 960 info->rtscts_rate |= rate->hw_value_short; 961 962 for (i = 0; i < 4; i++) { 963 bool is_40, is_sgi, is_sp; 964 int phy; 965 966 if (!rates[i].count || (rates[i].idx < 0)) 967 continue; 968 969 rix = rates[i].idx; 970 info->rates[i].Tries = rates[i].count; 971 972 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) { 973 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; 974 info->flags |= ATH9K_TXDESC_RTSENA; 975 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 976 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; 977 info->flags |= ATH9K_TXDESC_CTSENA; 978 } 979 980 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 981 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040; 982 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) 983 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI; 984 985 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI); 986 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH); 987 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE); 988 989 if (rates[i].flags & IEEE80211_TX_RC_MCS) { 990 /* MCS rates */ 991 info->rates[i].Rate = rix | 0x80; 992 info->rates[i].ChSel = ath_txchainmask_reduction(sc, 993 ah->txchainmask, info->rates[i].Rate); 994 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len, 995 is_40, is_sgi, is_sp); 996 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC)) 997 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC; 998 continue; 999 } 1000 1001 /* legacy rates */ 1002 if ((tx_info->band == IEEE80211_BAND_2GHZ) && 1003 !(rate->flags & IEEE80211_RATE_ERP_G)) 1004 phy = WLAN_RC_PHY_CCK; 1005 else 1006 phy = WLAN_RC_PHY_OFDM; 1007 1008 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx]; 1009 info->rates[i].Rate = rate->hw_value; 1010 if (rate->hw_value_short) { 1011 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 1012 info->rates[i].Rate |= rate->hw_value_short; 1013 } else { 1014 is_sp = false; 1015 } 1016 1017 if (bf->bf_state.bfs_paprd) 1018 info->rates[i].ChSel = ah->txchainmask; 1019 else 1020 info->rates[i].ChSel = ath_txchainmask_reduction(sc, 1021 ah->txchainmask, info->rates[i].Rate); 1022 1023 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah, 1024 phy, rate->bitrate * 100, len, rix, is_sp); 1025 } 1026 1027 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ 1028 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit)) 1029 info->flags &= ~ATH9K_TXDESC_RTSENA; 1030 1031 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */ 1032 if (info->flags & ATH9K_TXDESC_RTSENA) 1033 info->flags &= ~ATH9K_TXDESC_CTSENA; 1034 } 1035 1036 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) 1037 { 1038 struct ieee80211_hdr *hdr; 1039 enum ath9k_pkt_type htype; 1040 __le16 fc; 1041 1042 hdr = (struct ieee80211_hdr *)skb->data; 1043 fc = hdr->frame_control; 1044 1045 if (ieee80211_is_beacon(fc)) 1046 htype = ATH9K_PKT_TYPE_BEACON; 1047 else if (ieee80211_is_probe_resp(fc)) 1048 htype = ATH9K_PKT_TYPE_PROBE_RESP; 1049 else if (ieee80211_is_atim(fc)) 1050 htype = ATH9K_PKT_TYPE_ATIM; 1051 else if (ieee80211_is_pspoll(fc)) 1052 htype = ATH9K_PKT_TYPE_PSPOLL; 1053 else 1054 htype = ATH9K_PKT_TYPE_NORMAL; 1055 1056 return htype; 1057 } 1058 1059 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf, 1060 struct ath_txq *txq, int len) 1061 { 1062 struct ath_hw *ah = sc->sc_ah; 1063 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 1064 struct ath_buf *bf_first = bf; 1065 struct ath_tx_info info; 1066 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR); 1067 1068 memset(&info, 0, sizeof(info)); 1069 info.is_first = true; 1070 info.is_last = true; 1071 info.txpower = MAX_RATE_POWER; 1072 info.qcu = txq->axq_qnum; 1073 1074 info.flags = ATH9K_TXDESC_INTREQ; 1075 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) 1076 info.flags |= ATH9K_TXDESC_NOACK; 1077 if (tx_info->flags & IEEE80211_TX_CTL_LDPC) 1078 info.flags |= ATH9K_TXDESC_LDPC; 1079 1080 ath_buf_set_rate(sc, bf, &info, len); 1081 1082 if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) 1083 info.flags |= ATH9K_TXDESC_CLRDMASK; 1084 1085 if (bf->bf_state.bfs_paprd) 1086 info.flags |= (u32) bf->bf_state.bfs_paprd << ATH9K_TXDESC_PAPRD_S; 1087 1088 1089 while (bf) { 1090 struct sk_buff *skb = bf->bf_mpdu; 1091 struct ath_frame_info *fi = get_frame_info(skb); 1092 1093 info.type = get_hw_packet_type(skb); 1094 if (bf->bf_next) 1095 info.link = bf->bf_next->bf_daddr; 1096 else 1097 info.link = 0; 1098 1099 info.buf_addr[0] = bf->bf_buf_addr; 1100 info.buf_len[0] = skb->len; 1101 info.pkt_len = fi->framelen; 1102 info.keyix = fi->keyix; 1103 info.keytype = fi->keytype; 1104 1105 if (aggr) { 1106 if (bf == bf_first) 1107 info.aggr = AGGR_BUF_FIRST; 1108 else if (!bf->bf_next) 1109 info.aggr = AGGR_BUF_LAST; 1110 else 1111 info.aggr = AGGR_BUF_MIDDLE; 1112 1113 info.ndelim = bf->bf_state.ndelim; 1114 info.aggr_len = len; 1115 } 1116 1117 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info); 1118 bf = bf->bf_next; 1119 } 1120 } 1121 1122 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, 1123 struct ath_atx_tid *tid) 1124 { 1125 struct ath_buf *bf; 1126 enum ATH_AGGR_STATUS status; 1127 struct ieee80211_tx_info *tx_info; 1128 struct list_head bf_q; 1129 int aggr_len; 1130 1131 do { 1132 if (skb_queue_empty(&tid->buf_q)) 1133 return; 1134 1135 INIT_LIST_HEAD(&bf_q); 1136 1137 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len); 1138 1139 /* 1140 * no frames picked up to be aggregated; 1141 * block-ack window is not open. 1142 */ 1143 if (list_empty(&bf_q)) 1144 break; 1145 1146 bf = list_first_entry(&bf_q, struct ath_buf, list); 1147 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list); 1148 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 1149 1150 if (tid->ac->clear_ps_filter) { 1151 tid->ac->clear_ps_filter = false; 1152 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; 1153 } else { 1154 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT; 1155 } 1156 1157 /* if only one frame, send as non-aggregate */ 1158 if (bf == bf->bf_lastbf) { 1159 aggr_len = get_frame_info(bf->bf_mpdu)->framelen; 1160 bf->bf_state.bf_type = BUF_AMPDU; 1161 } else { 1162 TX_STAT_INC(txq->axq_qnum, a_aggr); 1163 } 1164 1165 ath_tx_fill_desc(sc, bf, txq, aggr_len); 1166 ath_tx_txqaddbuf(sc, txq, &bf_q, false); 1167 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH && 1168 status != ATH_AGGR_BAW_CLOSED); 1169 } 1170 1171 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, 1172 u16 tid, u16 *ssn) 1173 { 1174 struct ath_atx_tid *txtid; 1175 struct ath_node *an; 1176 1177 an = (struct ath_node *)sta->drv_priv; 1178 txtid = ATH_AN_2_TID(an, tid); 1179 1180 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE)) 1181 return -EAGAIN; 1182 1183 txtid->state |= AGGR_ADDBA_PROGRESS; 1184 txtid->paused = true; 1185 *ssn = txtid->seq_start = txtid->seq_next; 1186 txtid->bar_index = -1; 1187 1188 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf)); 1189 txtid->baw_head = txtid->baw_tail = 0; 1190 1191 return 0; 1192 } 1193 1194 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) 1195 { 1196 struct ath_node *an = (struct ath_node *)sta->drv_priv; 1197 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); 1198 struct ath_txq *txq = txtid->ac->txq; 1199 1200 if (txtid->state & AGGR_CLEANUP) 1201 return; 1202 1203 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) { 1204 txtid->state &= ~AGGR_ADDBA_PROGRESS; 1205 return; 1206 } 1207 1208 ath_txq_lock(sc, txq); 1209 txtid->paused = true; 1210 1211 /* 1212 * If frames are still being transmitted for this TID, they will be 1213 * cleaned up during tx completion. To prevent race conditions, this 1214 * TID can only be reused after all in-progress subframes have been 1215 * completed. 1216 */ 1217 if (txtid->baw_head != txtid->baw_tail) 1218 txtid->state |= AGGR_CLEANUP; 1219 else 1220 txtid->state &= ~AGGR_ADDBA_COMPLETE; 1221 1222 ath_tx_flush_tid(sc, txtid); 1223 ath_txq_unlock_complete(sc, txq); 1224 } 1225 1226 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc, 1227 struct ath_node *an) 1228 { 1229 struct ath_atx_tid *tid; 1230 struct ath_atx_ac *ac; 1231 struct ath_txq *txq; 1232 bool buffered; 1233 int tidno; 1234 1235 for (tidno = 0, tid = &an->tid[tidno]; 1236 tidno < WME_NUM_TID; tidno++, tid++) { 1237 1238 if (!tid->sched) 1239 continue; 1240 1241 ac = tid->ac; 1242 txq = ac->txq; 1243 1244 ath_txq_lock(sc, txq); 1245 1246 buffered = !skb_queue_empty(&tid->buf_q); 1247 1248 tid->sched = false; 1249 list_del(&tid->list); 1250 1251 if (ac->sched) { 1252 ac->sched = false; 1253 list_del(&ac->list); 1254 } 1255 1256 ath_txq_unlock(sc, txq); 1257 1258 ieee80211_sta_set_buffered(sta, tidno, buffered); 1259 } 1260 } 1261 1262 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an) 1263 { 1264 struct ath_atx_tid *tid; 1265 struct ath_atx_ac *ac; 1266 struct ath_txq *txq; 1267 int tidno; 1268 1269 for (tidno = 0, tid = &an->tid[tidno]; 1270 tidno < WME_NUM_TID; tidno++, tid++) { 1271 1272 ac = tid->ac; 1273 txq = ac->txq; 1274 1275 ath_txq_lock(sc, txq); 1276 ac->clear_ps_filter = true; 1277 1278 if (!skb_queue_empty(&tid->buf_q) && !tid->paused) { 1279 ath_tx_queue_tid(txq, tid); 1280 ath_txq_schedule(sc, txq); 1281 } 1282 1283 ath_txq_unlock_complete(sc, txq); 1284 } 1285 } 1286 1287 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) 1288 { 1289 struct ath_atx_tid *txtid; 1290 struct ath_node *an; 1291 1292 an = (struct ath_node *)sta->drv_priv; 1293 1294 if (sc->sc_flags & SC_OP_TXAGGR) { 1295 txtid = ATH_AN_2_TID(an, tid); 1296 txtid->baw_size = 1297 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor; 1298 txtid->state |= AGGR_ADDBA_COMPLETE; 1299 txtid->state &= ~AGGR_ADDBA_PROGRESS; 1300 ath_tx_resume_tid(sc, txtid); 1301 } 1302 } 1303 1304 /********************/ 1305 /* Queue Management */ 1306 /********************/ 1307 1308 static void ath_txq_drain_pending_buffers(struct ath_softc *sc, 1309 struct ath_txq *txq) 1310 { 1311 struct ath_atx_ac *ac, *ac_tmp; 1312 struct ath_atx_tid *tid, *tid_tmp; 1313 1314 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) { 1315 list_del(&ac->list); 1316 ac->sched = false; 1317 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) { 1318 list_del(&tid->list); 1319 tid->sched = false; 1320 ath_tid_drain(sc, txq, tid); 1321 } 1322 } 1323 } 1324 1325 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 1326 { 1327 struct ath_hw *ah = sc->sc_ah; 1328 struct ath9k_tx_queue_info qi; 1329 static const int subtype_txq_to_hwq[] = { 1330 [WME_AC_BE] = ATH_TXQ_AC_BE, 1331 [WME_AC_BK] = ATH_TXQ_AC_BK, 1332 [WME_AC_VI] = ATH_TXQ_AC_VI, 1333 [WME_AC_VO] = ATH_TXQ_AC_VO, 1334 }; 1335 int axq_qnum, i; 1336 1337 memset(&qi, 0, sizeof(qi)); 1338 qi.tqi_subtype = subtype_txq_to_hwq[subtype]; 1339 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; 1340 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; 1341 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; 1342 qi.tqi_physCompBuf = 0; 1343 1344 /* 1345 * Enable interrupts only for EOL and DESC conditions. 1346 * We mark tx descriptors to receive a DESC interrupt 1347 * when a tx queue gets deep; otherwise waiting for the 1348 * EOL to reap descriptors. Note that this is done to 1349 * reduce interrupt load and this only defers reaping 1350 * descriptors, never transmitting frames. Aside from 1351 * reducing interrupts this also permits more concurrency. 1352 * The only potential downside is if the tx queue backs 1353 * up in which case the top half of the kernel may backup 1354 * due to a lack of tx descriptors. 1355 * 1356 * The UAPSD queue is an exception, since we take a desc- 1357 * based intr on the EOSP frames. 1358 */ 1359 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1360 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE | 1361 TXQ_FLAG_TXERRINT_ENABLE; 1362 } else { 1363 if (qtype == ATH9K_TX_QUEUE_UAPSD) 1364 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; 1365 else 1366 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | 1367 TXQ_FLAG_TXDESCINT_ENABLE; 1368 } 1369 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); 1370 if (axq_qnum == -1) { 1371 /* 1372 * NB: don't print a message, this happens 1373 * normally on parts with too few tx queues 1374 */ 1375 return NULL; 1376 } 1377 if (!ATH_TXQ_SETUP(sc, axq_qnum)) { 1378 struct ath_txq *txq = &sc->tx.txq[axq_qnum]; 1379 1380 txq->axq_qnum = axq_qnum; 1381 txq->mac80211_qnum = -1; 1382 txq->axq_link = NULL; 1383 __skb_queue_head_init(&txq->complete_q); 1384 INIT_LIST_HEAD(&txq->axq_q); 1385 INIT_LIST_HEAD(&txq->axq_acq); 1386 spin_lock_init(&txq->axq_lock); 1387 txq->axq_depth = 0; 1388 txq->axq_ampdu_depth = 0; 1389 txq->axq_tx_inprogress = false; 1390 sc->tx.txqsetup |= 1<<axq_qnum; 1391 1392 txq->txq_headidx = txq->txq_tailidx = 0; 1393 for (i = 0; i < ATH_TXFIFO_DEPTH; i++) 1394 INIT_LIST_HEAD(&txq->txq_fifo[i]); 1395 } 1396 return &sc->tx.txq[axq_qnum]; 1397 } 1398 1399 int ath_txq_update(struct ath_softc *sc, int qnum, 1400 struct ath9k_tx_queue_info *qinfo) 1401 { 1402 struct ath_hw *ah = sc->sc_ah; 1403 int error = 0; 1404 struct ath9k_tx_queue_info qi; 1405 1406 if (qnum == sc->beacon.beaconq) { 1407 /* 1408 * XXX: for beacon queue, we just save the parameter. 1409 * It will be picked up by ath_beaconq_config when 1410 * it's necessary. 1411 */ 1412 sc->beacon.beacon_qi = *qinfo; 1413 return 0; 1414 } 1415 1416 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum); 1417 1418 ath9k_hw_get_txq_props(ah, qnum, &qi); 1419 qi.tqi_aifs = qinfo->tqi_aifs; 1420 qi.tqi_cwmin = qinfo->tqi_cwmin; 1421 qi.tqi_cwmax = qinfo->tqi_cwmax; 1422 qi.tqi_burstTime = qinfo->tqi_burstTime; 1423 qi.tqi_readyTime = qinfo->tqi_readyTime; 1424 1425 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { 1426 ath_err(ath9k_hw_common(sc->sc_ah), 1427 "Unable to update hardware queue %u!\n", qnum); 1428 error = -EIO; 1429 } else { 1430 ath9k_hw_resettxqueue(ah, qnum); 1431 } 1432 1433 return error; 1434 } 1435 1436 int ath_cabq_update(struct ath_softc *sc) 1437 { 1438 struct ath9k_tx_queue_info qi; 1439 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf; 1440 int qnum = sc->beacon.cabq->axq_qnum; 1441 1442 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); 1443 /* 1444 * Ensure the readytime % is within the bounds. 1445 */ 1446 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND) 1447 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND; 1448 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND) 1449 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND; 1450 1451 qi.tqi_readyTime = (cur_conf->beacon_interval * 1452 sc->config.cabqReadytime) / 100; 1453 ath_txq_update(sc, qnum, &qi); 1454 1455 return 0; 1456 } 1457 1458 static bool bf_is_ampdu_not_probing(struct ath_buf *bf) 1459 { 1460 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu); 1461 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE); 1462 } 1463 1464 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq, 1465 struct list_head *list, bool retry_tx) 1466 { 1467 struct ath_buf *bf, *lastbf; 1468 struct list_head bf_head; 1469 struct ath_tx_status ts; 1470 1471 memset(&ts, 0, sizeof(ts)); 1472 ts.ts_status = ATH9K_TX_FLUSH; 1473 INIT_LIST_HEAD(&bf_head); 1474 1475 while (!list_empty(list)) { 1476 bf = list_first_entry(list, struct ath_buf, list); 1477 1478 if (bf->bf_stale) { 1479 list_del(&bf->list); 1480 1481 ath_tx_return_buffer(sc, bf); 1482 continue; 1483 } 1484 1485 lastbf = bf->bf_lastbf; 1486 list_cut_position(&bf_head, list, &lastbf->list); 1487 1488 txq->axq_depth--; 1489 if (bf_is_ampdu_not_probing(bf)) 1490 txq->axq_ampdu_depth--; 1491 1492 if (bf_isampdu(bf)) 1493 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0, 1494 retry_tx); 1495 else 1496 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0); 1497 } 1498 } 1499 1500 /* 1501 * Drain a given TX queue (could be Beacon or Data) 1502 * 1503 * This assumes output has been stopped and 1504 * we do not need to block ath_tx_tasklet. 1505 */ 1506 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx) 1507 { 1508 ath_txq_lock(sc, txq); 1509 1510 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1511 int idx = txq->txq_tailidx; 1512 1513 while (!list_empty(&txq->txq_fifo[idx])) { 1514 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx], 1515 retry_tx); 1516 1517 INCR(idx, ATH_TXFIFO_DEPTH); 1518 } 1519 txq->txq_tailidx = idx; 1520 } 1521 1522 txq->axq_link = NULL; 1523 txq->axq_tx_inprogress = false; 1524 ath_drain_txq_list(sc, txq, &txq->axq_q, retry_tx); 1525 1526 /* flush any pending frames if aggregation is enabled */ 1527 if ((sc->sc_flags & SC_OP_TXAGGR) && !retry_tx) 1528 ath_txq_drain_pending_buffers(sc, txq); 1529 1530 ath_txq_unlock_complete(sc, txq); 1531 } 1532 1533 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) 1534 { 1535 struct ath_hw *ah = sc->sc_ah; 1536 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1537 struct ath_txq *txq; 1538 int i; 1539 u32 npend = 0; 1540 1541 if (sc->sc_flags & SC_OP_INVALID) 1542 return true; 1543 1544 ath9k_hw_abort_tx_dma(ah); 1545 1546 /* Check if any queue remains active */ 1547 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1548 if (!ATH_TXQ_SETUP(sc, i)) 1549 continue; 1550 1551 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum)) 1552 npend |= BIT(i); 1553 } 1554 1555 if (npend) 1556 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend); 1557 1558 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1559 if (!ATH_TXQ_SETUP(sc, i)) 1560 continue; 1561 1562 /* 1563 * The caller will resume queues with ieee80211_wake_queues. 1564 * Mark the queue as not stopped to prevent ath_tx_complete 1565 * from waking the queue too early. 1566 */ 1567 txq = &sc->tx.txq[i]; 1568 txq->stopped = false; 1569 ath_draintxq(sc, txq, retry_tx); 1570 } 1571 1572 return !npend; 1573 } 1574 1575 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 1576 { 1577 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); 1578 sc->tx.txqsetup &= ~(1<<txq->axq_qnum); 1579 } 1580 1581 /* For each axq_acq entry, for each tid, try to schedule packets 1582 * for transmit until ampdu_depth has reached min Q depth. 1583 */ 1584 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) 1585 { 1586 struct ath_atx_ac *ac, *ac_tmp, *last_ac; 1587 struct ath_atx_tid *tid, *last_tid; 1588 1589 if (work_pending(&sc->hw_reset_work) || list_empty(&txq->axq_acq) || 1590 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) 1591 return; 1592 1593 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list); 1594 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list); 1595 1596 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) { 1597 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list); 1598 list_del(&ac->list); 1599 ac->sched = false; 1600 1601 while (!list_empty(&ac->tid_q)) { 1602 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, 1603 list); 1604 list_del(&tid->list); 1605 tid->sched = false; 1606 1607 if (tid->paused) 1608 continue; 1609 1610 ath_tx_sched_aggr(sc, txq, tid); 1611 1612 /* 1613 * add tid to round-robin queue if more frames 1614 * are pending for the tid 1615 */ 1616 if (!skb_queue_empty(&tid->buf_q)) 1617 ath_tx_queue_tid(txq, tid); 1618 1619 if (tid == last_tid || 1620 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) 1621 break; 1622 } 1623 1624 if (!list_empty(&ac->tid_q) && !ac->sched) { 1625 ac->sched = true; 1626 list_add_tail(&ac->list, &txq->axq_acq); 1627 } 1628 1629 if (ac == last_ac || 1630 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) 1631 return; 1632 } 1633 } 1634 1635 /***********/ 1636 /* TX, DMA */ 1637 /***********/ 1638 1639 /* 1640 * Insert a chain of ath_buf (descriptors) on a txq and 1641 * assume the descriptors are already chained together by caller. 1642 */ 1643 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 1644 struct list_head *head, bool internal) 1645 { 1646 struct ath_hw *ah = sc->sc_ah; 1647 struct ath_common *common = ath9k_hw_common(ah); 1648 struct ath_buf *bf, *bf_last; 1649 bool puttxbuf = false; 1650 bool edma; 1651 1652 /* 1653 * Insert the frame on the outbound list and 1654 * pass it on to the hardware. 1655 */ 1656 1657 if (list_empty(head)) 1658 return; 1659 1660 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 1661 bf = list_first_entry(head, struct ath_buf, list); 1662 bf_last = list_entry(head->prev, struct ath_buf, list); 1663 1664 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n", 1665 txq->axq_qnum, txq->axq_depth); 1666 1667 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) { 1668 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]); 1669 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH); 1670 puttxbuf = true; 1671 } else { 1672 list_splice_tail_init(head, &txq->axq_q); 1673 1674 if (txq->axq_link) { 1675 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr); 1676 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n", 1677 txq->axq_qnum, txq->axq_link, 1678 ito64(bf->bf_daddr), bf->bf_desc); 1679 } else if (!edma) 1680 puttxbuf = true; 1681 1682 txq->axq_link = bf_last->bf_desc; 1683 } 1684 1685 if (puttxbuf) { 1686 TX_STAT_INC(txq->axq_qnum, puttxbuf); 1687 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 1688 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n", 1689 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); 1690 } 1691 1692 if (!edma) { 1693 TX_STAT_INC(txq->axq_qnum, txstart); 1694 ath9k_hw_txstart(ah, txq->axq_qnum); 1695 } 1696 1697 if (!internal) { 1698 txq->axq_depth++; 1699 if (bf_is_ampdu_not_probing(bf)) 1700 txq->axq_ampdu_depth++; 1701 } 1702 } 1703 1704 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid, 1705 struct sk_buff *skb, struct ath_tx_control *txctl) 1706 { 1707 struct ath_frame_info *fi = get_frame_info(skb); 1708 struct list_head bf_head; 1709 struct ath_buf *bf; 1710 1711 /* 1712 * Do not queue to h/w when any of the following conditions is true: 1713 * - there are pending frames in software queue 1714 * - the TID is currently paused for ADDBA/BAR request 1715 * - seqno is not within block-ack window 1716 * - h/w queue depth exceeds low water mark 1717 */ 1718 if (!skb_queue_empty(&tid->buf_q) || tid->paused || 1719 !BAW_WITHIN(tid->seq_start, tid->baw_size, tid->seq_next) || 1720 txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) { 1721 /* 1722 * Add this frame to software queue for scheduling later 1723 * for aggregation. 1724 */ 1725 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw); 1726 __skb_queue_tail(&tid->buf_q, skb); 1727 if (!txctl->an || !txctl->an->sleeping) 1728 ath_tx_queue_tid(txctl->txq, tid); 1729 return; 1730 } 1731 1732 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb); 1733 if (!bf) 1734 return; 1735 1736 bf->bf_state.bf_type = BUF_AMPDU; 1737 INIT_LIST_HEAD(&bf_head); 1738 list_add(&bf->list, &bf_head); 1739 1740 /* Add sub-frame to BAW */ 1741 ath_tx_addto_baw(sc, tid, bf->bf_state.seqno); 1742 1743 /* Queue to h/w without aggregation */ 1744 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw); 1745 bf->bf_lastbf = bf; 1746 ath_tx_fill_desc(sc, bf, txctl->txq, fi->framelen); 1747 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false); 1748 } 1749 1750 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, 1751 struct ath_atx_tid *tid, struct sk_buff *skb) 1752 { 1753 struct ath_frame_info *fi = get_frame_info(skb); 1754 struct list_head bf_head; 1755 struct ath_buf *bf; 1756 1757 bf = fi->bf; 1758 if (!bf) 1759 bf = ath_tx_setup_buffer(sc, txq, tid, skb); 1760 1761 if (!bf) 1762 return; 1763 1764 INIT_LIST_HEAD(&bf_head); 1765 list_add_tail(&bf->list, &bf_head); 1766 bf->bf_state.bf_type = 0; 1767 1768 bf->bf_lastbf = bf; 1769 ath_tx_fill_desc(sc, bf, txq, fi->framelen); 1770 ath_tx_txqaddbuf(sc, txq, &bf_head, false); 1771 TX_STAT_INC(txq->axq_qnum, queued); 1772 } 1773 1774 static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb, 1775 int framelen) 1776 { 1777 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1778 struct ieee80211_sta *sta = tx_info->control.sta; 1779 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key; 1780 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1781 struct ath_frame_info *fi = get_frame_info(skb); 1782 struct ath_node *an = NULL; 1783 enum ath9k_key_type keytype; 1784 1785 keytype = ath9k_cmn_get_hw_crypto_keytype(skb); 1786 1787 if (sta) 1788 an = (struct ath_node *) sta->drv_priv; 1789 1790 memset(fi, 0, sizeof(*fi)); 1791 if (hw_key) 1792 fi->keyix = hw_key->hw_key_idx; 1793 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0) 1794 fi->keyix = an->ps_key; 1795 else 1796 fi->keyix = ATH9K_TXKEYIX_INVALID; 1797 fi->keytype = keytype; 1798 fi->framelen = framelen; 1799 } 1800 1801 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate) 1802 { 1803 struct ath_hw *ah = sc->sc_ah; 1804 struct ath9k_channel *curchan = ah->curchan; 1805 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && 1806 (curchan->channelFlags & CHANNEL_5GHZ) && 1807 (chainmask == 0x7) && (rate < 0x90)) 1808 return 0x3; 1809 else 1810 return chainmask; 1811 } 1812 1813 /* 1814 * Assign a descriptor (and sequence number if necessary, 1815 * and map buffer for DMA. Frees skb on error 1816 */ 1817 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, 1818 struct ath_txq *txq, 1819 struct ath_atx_tid *tid, 1820 struct sk_buff *skb) 1821 { 1822 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1823 struct ath_frame_info *fi = get_frame_info(skb); 1824 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1825 struct ath_buf *bf; 1826 u16 seqno; 1827 1828 bf = ath_tx_get_buffer(sc); 1829 if (!bf) { 1830 ath_dbg(common, XMIT, "TX buffers are full\n"); 1831 goto error; 1832 } 1833 1834 ATH_TXBUF_RESET(bf); 1835 1836 if (tid) { 1837 seqno = tid->seq_next; 1838 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT); 1839 INCR(tid->seq_next, IEEE80211_SEQ_MAX); 1840 bf->bf_state.seqno = seqno; 1841 } 1842 1843 bf->bf_mpdu = skb; 1844 1845 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, 1846 skb->len, DMA_TO_DEVICE); 1847 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) { 1848 bf->bf_mpdu = NULL; 1849 bf->bf_buf_addr = 0; 1850 ath_err(ath9k_hw_common(sc->sc_ah), 1851 "dma_mapping_error() on TX\n"); 1852 ath_tx_return_buffer(sc, bf); 1853 goto error; 1854 } 1855 1856 fi->bf = bf; 1857 1858 return bf; 1859 1860 error: 1861 dev_kfree_skb_any(skb); 1862 return NULL; 1863 } 1864 1865 /* FIXME: tx power */ 1866 static void ath_tx_start_dma(struct ath_softc *sc, struct sk_buff *skb, 1867 struct ath_tx_control *txctl) 1868 { 1869 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1870 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1871 struct ath_atx_tid *tid = NULL; 1872 struct ath_buf *bf; 1873 u8 tidno; 1874 1875 if ((sc->sc_flags & SC_OP_TXAGGR) && txctl->an && 1876 ieee80211_is_data_qos(hdr->frame_control)) { 1877 tidno = ieee80211_get_qos_ctl(hdr)[0] & 1878 IEEE80211_QOS_CTL_TID_MASK; 1879 tid = ATH_AN_2_TID(txctl->an, tidno); 1880 1881 WARN_ON(tid->ac->txq != txctl->txq); 1882 } 1883 1884 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) { 1885 /* 1886 * Try aggregation if it's a unicast data frame 1887 * and the destination is HT capable. 1888 */ 1889 ath_tx_send_ampdu(sc, tid, skb, txctl); 1890 } else { 1891 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb); 1892 if (!bf) 1893 return; 1894 1895 bf->bf_state.bfs_paprd = txctl->paprd; 1896 1897 if (txctl->paprd) 1898 bf->bf_state.bfs_paprd_timestamp = jiffies; 1899 1900 ath_tx_send_normal(sc, txctl->txq, tid, skb); 1901 } 1902 } 1903 1904 /* Upon failure caller should free skb */ 1905 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, 1906 struct ath_tx_control *txctl) 1907 { 1908 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 1909 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1910 struct ieee80211_sta *sta = info->control.sta; 1911 struct ieee80211_vif *vif = info->control.vif; 1912 struct ath_softc *sc = hw->priv; 1913 struct ath_txq *txq = txctl->txq; 1914 int padpos, padsize; 1915 int frmlen = skb->len + FCS_LEN; 1916 int q; 1917 1918 /* NOTE: sta can be NULL according to net/mac80211.h */ 1919 if (sta) 1920 txctl->an = (struct ath_node *)sta->drv_priv; 1921 1922 if (info->control.hw_key) 1923 frmlen += info->control.hw_key->icv_len; 1924 1925 /* 1926 * As a temporary workaround, assign seq# here; this will likely need 1927 * to be cleaned up to work better with Beacon transmission and virtual 1928 * BSSes. 1929 */ 1930 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { 1931 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) 1932 sc->tx.seq_no += 0x10; 1933 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); 1934 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); 1935 } 1936 1937 /* Add the padding after the header if this is not already done */ 1938 padpos = ath9k_cmn_padpos(hdr->frame_control); 1939 padsize = padpos & 3; 1940 if (padsize && skb->len > padpos) { 1941 if (skb_headroom(skb) < padsize) 1942 return -ENOMEM; 1943 1944 skb_push(skb, padsize); 1945 memmove(skb->data, skb->data + padsize, padpos); 1946 hdr = (struct ieee80211_hdr *) skb->data; 1947 } 1948 1949 if ((vif && vif->type != NL80211_IFTYPE_AP && 1950 vif->type != NL80211_IFTYPE_AP_VLAN) || 1951 !ieee80211_is_data(hdr->frame_control)) 1952 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; 1953 1954 setup_frame_info(hw, skb, frmlen); 1955 1956 /* 1957 * At this point, the vif, hw_key and sta pointers in the tx control 1958 * info are no longer valid (overwritten by the ath_frame_info data. 1959 */ 1960 1961 q = skb_get_queue_mapping(skb); 1962 1963 ath_txq_lock(sc, txq); 1964 if (txq == sc->tx.txq_map[q] && 1965 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) { 1966 ieee80211_stop_queue(sc->hw, q); 1967 txq->stopped = true; 1968 } 1969 1970 ath_tx_start_dma(sc, skb, txctl); 1971 1972 ath_txq_unlock(sc, txq); 1973 1974 return 0; 1975 } 1976 1977 /*****************/ 1978 /* TX Completion */ 1979 /*****************/ 1980 1981 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, 1982 int tx_flags, struct ath_txq *txq) 1983 { 1984 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1985 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1986 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; 1987 int q, padpos, padsize; 1988 1989 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb); 1990 1991 if (!(tx_flags & ATH_TX_ERROR)) 1992 /* Frame was ACKed */ 1993 tx_info->flags |= IEEE80211_TX_STAT_ACK; 1994 1995 padpos = ath9k_cmn_padpos(hdr->frame_control); 1996 padsize = padpos & 3; 1997 if (padsize && skb->len>padpos+padsize) { 1998 /* 1999 * Remove MAC header padding before giving the frame back to 2000 * mac80211. 2001 */ 2002 memmove(skb->data + padsize, skb->data, padpos); 2003 skb_pull(skb, padsize); 2004 } 2005 2006 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) { 2007 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK; 2008 ath_dbg(common, PS, 2009 "Going back to sleep after having received TX status (0x%lx)\n", 2010 sc->ps_flags & (PS_WAIT_FOR_BEACON | 2011 PS_WAIT_FOR_CAB | 2012 PS_WAIT_FOR_PSPOLL_DATA | 2013 PS_WAIT_FOR_TX_ACK)); 2014 } 2015 2016 q = skb_get_queue_mapping(skb); 2017 if (txq == sc->tx.txq_map[q]) { 2018 if (WARN_ON(--txq->pending_frames < 0)) 2019 txq->pending_frames = 0; 2020 2021 if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) { 2022 ieee80211_wake_queue(sc->hw, q); 2023 txq->stopped = false; 2024 } 2025 } 2026 2027 __skb_queue_tail(&txq->complete_q, skb); 2028 } 2029 2030 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 2031 struct ath_txq *txq, struct list_head *bf_q, 2032 struct ath_tx_status *ts, int txok) 2033 { 2034 struct sk_buff *skb = bf->bf_mpdu; 2035 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2036 unsigned long flags; 2037 int tx_flags = 0; 2038 2039 if (!txok) 2040 tx_flags |= ATH_TX_ERROR; 2041 2042 if (ts->ts_status & ATH9K_TXERR_FILT) 2043 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 2044 2045 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE); 2046 bf->bf_buf_addr = 0; 2047 2048 if (bf->bf_state.bfs_paprd) { 2049 if (time_after(jiffies, 2050 bf->bf_state.bfs_paprd_timestamp + 2051 msecs_to_jiffies(ATH_PAPRD_TIMEOUT))) 2052 dev_kfree_skb_any(skb); 2053 else 2054 complete(&sc->paprd_complete); 2055 } else { 2056 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags); 2057 ath_tx_complete(sc, skb, tx_flags, txq); 2058 } 2059 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't 2060 * accidentally reference it later. 2061 */ 2062 bf->bf_mpdu = NULL; 2063 2064 /* 2065 * Return the list of ath_buf of this mpdu to free queue 2066 */ 2067 spin_lock_irqsave(&sc->tx.txbuflock, flags); 2068 list_splice_tail_init(bf_q, &sc->tx.txbuf); 2069 spin_unlock_irqrestore(&sc->tx.txbuflock, flags); 2070 } 2071 2072 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, 2073 struct ath_tx_status *ts, int nframes, int nbad, 2074 int txok) 2075 { 2076 struct sk_buff *skb = bf->bf_mpdu; 2077 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2078 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2079 struct ieee80211_hw *hw = sc->hw; 2080 struct ath_hw *ah = sc->sc_ah; 2081 u8 i, tx_rateindex; 2082 2083 if (txok) 2084 tx_info->status.ack_signal = ts->ts_rssi; 2085 2086 tx_rateindex = ts->ts_rateindex; 2087 WARN_ON(tx_rateindex >= hw->max_rates); 2088 2089 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { 2090 tx_info->flags |= IEEE80211_TX_STAT_AMPDU; 2091 2092 BUG_ON(nbad > nframes); 2093 } 2094 tx_info->status.ampdu_len = nframes; 2095 tx_info->status.ampdu_ack_len = nframes - nbad; 2096 2097 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 && 2098 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) { 2099 /* 2100 * If an underrun error is seen assume it as an excessive 2101 * retry only if max frame trigger level has been reached 2102 * (2 KB for single stream, and 4 KB for dual stream). 2103 * Adjust the long retry as if the frame was tried 2104 * hw->max_rate_tries times to affect how rate control updates 2105 * PER for the failed rate. 2106 * In case of congestion on the bus penalizing this type of 2107 * underruns should help hardware actually transmit new frames 2108 * successfully by eventually preferring slower rates. 2109 * This itself should also alleviate congestion on the bus. 2110 */ 2111 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN | 2112 ATH9K_TX_DELIM_UNDERRUN)) && 2113 ieee80211_is_data(hdr->frame_control) && 2114 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level) 2115 tx_info->status.rates[tx_rateindex].count = 2116 hw->max_rate_tries; 2117 } 2118 2119 for (i = tx_rateindex + 1; i < hw->max_rates; i++) { 2120 tx_info->status.rates[i].count = 0; 2121 tx_info->status.rates[i].idx = -1; 2122 } 2123 2124 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1; 2125 } 2126 2127 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq, 2128 struct ath_tx_status *ts, struct ath_buf *bf, 2129 struct list_head *bf_head) 2130 { 2131 int txok; 2132 2133 txq->axq_depth--; 2134 txok = !(ts->ts_status & ATH9K_TXERR_MASK); 2135 txq->axq_tx_inprogress = false; 2136 if (bf_is_ampdu_not_probing(bf)) 2137 txq->axq_ampdu_depth--; 2138 2139 if (!bf_isampdu(bf)) { 2140 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok); 2141 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok); 2142 } else 2143 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok, true); 2144 2145 if (sc->sc_flags & SC_OP_TXAGGR) 2146 ath_txq_schedule(sc, txq); 2147 } 2148 2149 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 2150 { 2151 struct ath_hw *ah = sc->sc_ah; 2152 struct ath_common *common = ath9k_hw_common(ah); 2153 struct ath_buf *bf, *lastbf, *bf_held = NULL; 2154 struct list_head bf_head; 2155 struct ath_desc *ds; 2156 struct ath_tx_status ts; 2157 int status; 2158 2159 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n", 2160 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), 2161 txq->axq_link); 2162 2163 ath_txq_lock(sc, txq); 2164 for (;;) { 2165 if (work_pending(&sc->hw_reset_work)) 2166 break; 2167 2168 if (list_empty(&txq->axq_q)) { 2169 txq->axq_link = NULL; 2170 if (sc->sc_flags & SC_OP_TXAGGR) 2171 ath_txq_schedule(sc, txq); 2172 break; 2173 } 2174 bf = list_first_entry(&txq->axq_q, struct ath_buf, list); 2175 2176 /* 2177 * There is a race condition that a BH gets scheduled 2178 * after sw writes TxE and before hw re-load the last 2179 * descriptor to get the newly chained one. 2180 * Software must keep the last DONE descriptor as a 2181 * holding descriptor - software does so by marking 2182 * it with the STALE flag. 2183 */ 2184 bf_held = NULL; 2185 if (bf->bf_stale) { 2186 bf_held = bf; 2187 if (list_is_last(&bf_held->list, &txq->axq_q)) 2188 break; 2189 2190 bf = list_entry(bf_held->list.next, struct ath_buf, 2191 list); 2192 } 2193 2194 lastbf = bf->bf_lastbf; 2195 ds = lastbf->bf_desc; 2196 2197 memset(&ts, 0, sizeof(ts)); 2198 status = ath9k_hw_txprocdesc(ah, ds, &ts); 2199 if (status == -EINPROGRESS) 2200 break; 2201 2202 TX_STAT_INC(txq->axq_qnum, txprocdesc); 2203 2204 /* 2205 * Remove ath_buf's of the same transmit unit from txq, 2206 * however leave the last descriptor back as the holding 2207 * descriptor for hw. 2208 */ 2209 lastbf->bf_stale = true; 2210 INIT_LIST_HEAD(&bf_head); 2211 if (!list_is_singular(&lastbf->list)) 2212 list_cut_position(&bf_head, 2213 &txq->axq_q, lastbf->list.prev); 2214 2215 if (bf_held) { 2216 list_del(&bf_held->list); 2217 ath_tx_return_buffer(sc, bf_held); 2218 } 2219 2220 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); 2221 } 2222 ath_txq_unlock_complete(sc, txq); 2223 } 2224 2225 static void ath_tx_complete_poll_work(struct work_struct *work) 2226 { 2227 struct ath_softc *sc = container_of(work, struct ath_softc, 2228 tx_complete_work.work); 2229 struct ath_txq *txq; 2230 int i; 2231 bool needreset = false; 2232 #ifdef CONFIG_ATH9K_DEBUGFS 2233 sc->tx_complete_poll_work_seen++; 2234 #endif 2235 2236 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 2237 if (ATH_TXQ_SETUP(sc, i)) { 2238 txq = &sc->tx.txq[i]; 2239 ath_txq_lock(sc, txq); 2240 if (txq->axq_depth) { 2241 if (txq->axq_tx_inprogress) { 2242 needreset = true; 2243 ath_txq_unlock(sc, txq); 2244 break; 2245 } else { 2246 txq->axq_tx_inprogress = true; 2247 } 2248 } 2249 ath_txq_unlock_complete(sc, txq); 2250 } 2251 2252 if (needreset) { 2253 ath_dbg(ath9k_hw_common(sc->sc_ah), RESET, 2254 "tx hung, resetting the chip\n"); 2255 RESET_STAT_INC(sc, RESET_TYPE_TX_HANG); 2256 ieee80211_queue_work(sc->hw, &sc->hw_reset_work); 2257 } 2258 2259 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 2260 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT)); 2261 } 2262 2263 2264 2265 void ath_tx_tasklet(struct ath_softc *sc) 2266 { 2267 int i; 2268 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1); 2269 2270 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask); 2271 2272 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 2273 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) 2274 ath_tx_processq(sc, &sc->tx.txq[i]); 2275 } 2276 } 2277 2278 void ath_tx_edma_tasklet(struct ath_softc *sc) 2279 { 2280 struct ath_tx_status ts; 2281 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2282 struct ath_hw *ah = sc->sc_ah; 2283 struct ath_txq *txq; 2284 struct ath_buf *bf, *lastbf; 2285 struct list_head bf_head; 2286 int status; 2287 2288 for (;;) { 2289 if (work_pending(&sc->hw_reset_work)) 2290 break; 2291 2292 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts); 2293 if (status == -EINPROGRESS) 2294 break; 2295 if (status == -EIO) { 2296 ath_dbg(common, XMIT, "Error processing tx status\n"); 2297 break; 2298 } 2299 2300 /* Skip beacon completions */ 2301 if (ts.qid == sc->beacon.beaconq) 2302 continue; 2303 2304 txq = &sc->tx.txq[ts.qid]; 2305 2306 ath_txq_lock(sc, txq); 2307 2308 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) { 2309 ath_txq_unlock(sc, txq); 2310 return; 2311 } 2312 2313 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx], 2314 struct ath_buf, list); 2315 lastbf = bf->bf_lastbf; 2316 2317 INIT_LIST_HEAD(&bf_head); 2318 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx], 2319 &lastbf->list); 2320 2321 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) { 2322 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH); 2323 2324 if (!list_empty(&txq->axq_q)) { 2325 struct list_head bf_q; 2326 2327 INIT_LIST_HEAD(&bf_q); 2328 txq->axq_link = NULL; 2329 list_splice_tail_init(&txq->axq_q, &bf_q); 2330 ath_tx_txqaddbuf(sc, txq, &bf_q, true); 2331 } 2332 } 2333 2334 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); 2335 ath_txq_unlock_complete(sc, txq); 2336 } 2337 } 2338 2339 /*****************/ 2340 /* Init, Cleanup */ 2341 /*****************/ 2342 2343 static int ath_txstatus_setup(struct ath_softc *sc, int size) 2344 { 2345 struct ath_descdma *dd = &sc->txsdma; 2346 u8 txs_len = sc->sc_ah->caps.txs_len; 2347 2348 dd->dd_desc_len = size * txs_len; 2349 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len, 2350 &dd->dd_desc_paddr, GFP_KERNEL); 2351 if (!dd->dd_desc) 2352 return -ENOMEM; 2353 2354 return 0; 2355 } 2356 2357 static int ath_tx_edma_init(struct ath_softc *sc) 2358 { 2359 int err; 2360 2361 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE); 2362 if (!err) 2363 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc, 2364 sc->txsdma.dd_desc_paddr, 2365 ATH_TXSTATUS_RING_SIZE); 2366 2367 return err; 2368 } 2369 2370 static void ath_tx_edma_cleanup(struct ath_softc *sc) 2371 { 2372 struct ath_descdma *dd = &sc->txsdma; 2373 2374 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, 2375 dd->dd_desc_paddr); 2376 } 2377 2378 int ath_tx_init(struct ath_softc *sc, int nbufs) 2379 { 2380 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2381 int error = 0; 2382 2383 spin_lock_init(&sc->tx.txbuflock); 2384 2385 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, 2386 "tx", nbufs, 1, 1); 2387 if (error != 0) { 2388 ath_err(common, 2389 "Failed to allocate tx descriptors: %d\n", error); 2390 goto err; 2391 } 2392 2393 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, 2394 "beacon", ATH_BCBUF, 1, 1); 2395 if (error != 0) { 2396 ath_err(common, 2397 "Failed to allocate beacon descriptors: %d\n", error); 2398 goto err; 2399 } 2400 2401 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work); 2402 2403 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 2404 error = ath_tx_edma_init(sc); 2405 if (error) 2406 goto err; 2407 } 2408 2409 err: 2410 if (error != 0) 2411 ath_tx_cleanup(sc); 2412 2413 return error; 2414 } 2415 2416 void ath_tx_cleanup(struct ath_softc *sc) 2417 { 2418 if (sc->beacon.bdma.dd_desc_len != 0) 2419 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf); 2420 2421 if (sc->tx.txdma.dd_desc_len != 0) 2422 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf); 2423 2424 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 2425 ath_tx_edma_cleanup(sc); 2426 } 2427 2428 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) 2429 { 2430 struct ath_atx_tid *tid; 2431 struct ath_atx_ac *ac; 2432 int tidno, acno; 2433 2434 for (tidno = 0, tid = &an->tid[tidno]; 2435 tidno < WME_NUM_TID; 2436 tidno++, tid++) { 2437 tid->an = an; 2438 tid->tidno = tidno; 2439 tid->seq_start = tid->seq_next = 0; 2440 tid->baw_size = WME_MAX_BA; 2441 tid->baw_head = tid->baw_tail = 0; 2442 tid->sched = false; 2443 tid->paused = false; 2444 tid->state &= ~AGGR_CLEANUP; 2445 __skb_queue_head_init(&tid->buf_q); 2446 acno = TID_TO_WME_AC(tidno); 2447 tid->ac = &an->ac[acno]; 2448 tid->state &= ~AGGR_ADDBA_COMPLETE; 2449 tid->state &= ~AGGR_ADDBA_PROGRESS; 2450 } 2451 2452 for (acno = 0, ac = &an->ac[acno]; 2453 acno < WME_NUM_AC; acno++, ac++) { 2454 ac->sched = false; 2455 ac->txq = sc->tx.txq_map[acno]; 2456 INIT_LIST_HEAD(&ac->tid_q); 2457 } 2458 } 2459 2460 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) 2461 { 2462 struct ath_atx_ac *ac; 2463 struct ath_atx_tid *tid; 2464 struct ath_txq *txq; 2465 int tidno; 2466 2467 for (tidno = 0, tid = &an->tid[tidno]; 2468 tidno < WME_NUM_TID; tidno++, tid++) { 2469 2470 ac = tid->ac; 2471 txq = ac->txq; 2472 2473 ath_txq_lock(sc, txq); 2474 2475 if (tid->sched) { 2476 list_del(&tid->list); 2477 tid->sched = false; 2478 } 2479 2480 if (ac->sched) { 2481 list_del(&ac->list); 2482 tid->ac->sched = false; 2483 } 2484 2485 ath_tid_drain(sc, txq, tid); 2486 tid->state &= ~AGGR_ADDBA_COMPLETE; 2487 tid->state &= ~AGGR_CLEANUP; 2488 2489 ath_txq_unlock(sc, txq); 2490 } 2491 } 2492