1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <linux/dma-mapping.h> 18 #include "ath9k.h" 19 #include "ar9003_mac.h" 20 21 #define BITS_PER_BYTE 8 22 #define OFDM_PLCP_BITS 22 23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) 24 #define L_STF 8 25 #define L_LTF 8 26 #define L_SIG 4 27 #define HT_SIG 8 28 #define HT_STF 4 29 #define HT_LTF(_ns) (4 * (_ns)) 30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ 31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ 32 #define TIME_SYMBOLS(t) ((t) >> 2) 33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18) 34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) 35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) 36 37 38 static u16 bits_per_symbol[][2] = { 39 /* 20MHz 40MHz */ 40 { 26, 54 }, /* 0: BPSK */ 41 { 52, 108 }, /* 1: QPSK 1/2 */ 42 { 78, 162 }, /* 2: QPSK 3/4 */ 43 { 104, 216 }, /* 3: 16-QAM 1/2 */ 44 { 156, 324 }, /* 4: 16-QAM 3/4 */ 45 { 208, 432 }, /* 5: 64-QAM 2/3 */ 46 { 234, 486 }, /* 6: 64-QAM 3/4 */ 47 { 260, 540 }, /* 7: 64-QAM 5/6 */ 48 }; 49 50 #define IS_HT_RATE(_rate) ((_rate) & 0x80) 51 52 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, 53 struct ath_atx_tid *tid, struct sk_buff *skb); 54 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, 55 int tx_flags, struct ath_txq *txq); 56 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 57 struct ath_txq *txq, struct list_head *bf_q, 58 struct ath_tx_status *ts, int txok); 59 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 60 struct list_head *head, bool internal); 61 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, 62 struct ath_tx_status *ts, int nframes, int nbad, 63 int txok); 64 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 65 int seqno); 66 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, 67 struct ath_txq *txq, 68 struct ath_atx_tid *tid, 69 struct sk_buff *skb, 70 bool dequeue); 71 72 enum { 73 MCS_HT20, 74 MCS_HT20_SGI, 75 MCS_HT40, 76 MCS_HT40_SGI, 77 }; 78 79 /*********************/ 80 /* Aggregation logic */ 81 /*********************/ 82 83 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq) 84 __acquires(&txq->axq_lock) 85 { 86 spin_lock_bh(&txq->axq_lock); 87 } 88 89 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq) 90 __releases(&txq->axq_lock) 91 { 92 spin_unlock_bh(&txq->axq_lock); 93 } 94 95 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq) 96 __releases(&txq->axq_lock) 97 { 98 struct sk_buff_head q; 99 struct sk_buff *skb; 100 101 __skb_queue_head_init(&q); 102 skb_queue_splice_init(&txq->complete_q, &q); 103 spin_unlock_bh(&txq->axq_lock); 104 105 while ((skb = __skb_dequeue(&q))) 106 ieee80211_tx_status(sc->hw, skb); 107 } 108 109 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid) 110 { 111 struct ath_atx_ac *ac = tid->ac; 112 113 if (tid->paused) 114 return; 115 116 if (tid->sched) 117 return; 118 119 tid->sched = true; 120 list_add_tail(&tid->list, &ac->tid_q); 121 122 if (ac->sched) 123 return; 124 125 ac->sched = true; 126 list_add_tail(&ac->list, &txq->axq_acq); 127 } 128 129 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 130 { 131 struct ath_txq *txq = tid->ac->txq; 132 133 WARN_ON(!tid->paused); 134 135 ath_txq_lock(sc, txq); 136 tid->paused = false; 137 138 if (skb_queue_empty(&tid->buf_q)) 139 goto unlock; 140 141 ath_tx_queue_tid(txq, tid); 142 ath_txq_schedule(sc, txq); 143 unlock: 144 ath_txq_unlock_complete(sc, txq); 145 } 146 147 static struct ath_frame_info *get_frame_info(struct sk_buff *skb) 148 { 149 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 150 BUILD_BUG_ON(sizeof(struct ath_frame_info) > 151 sizeof(tx_info->rate_driver_data)); 152 return (struct ath_frame_info *) &tx_info->rate_driver_data[0]; 153 } 154 155 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno) 156 { 157 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno, 158 seqno << IEEE80211_SEQ_SEQ_SHIFT); 159 } 160 161 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 162 { 163 struct ath_txq *txq = tid->ac->txq; 164 struct sk_buff *skb; 165 struct ath_buf *bf; 166 struct list_head bf_head; 167 struct ath_tx_status ts; 168 struct ath_frame_info *fi; 169 bool sendbar = false; 170 171 INIT_LIST_HEAD(&bf_head); 172 173 memset(&ts, 0, sizeof(ts)); 174 175 while ((skb = __skb_dequeue(&tid->buf_q))) { 176 fi = get_frame_info(skb); 177 bf = fi->bf; 178 179 if (bf && fi->retries) { 180 list_add_tail(&bf->list, &bf_head); 181 ath_tx_update_baw(sc, tid, bf->bf_state.seqno); 182 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0); 183 sendbar = true; 184 } else { 185 ath_tx_send_normal(sc, txq, NULL, skb); 186 } 187 } 188 189 if (tid->baw_head == tid->baw_tail) { 190 tid->state &= ~AGGR_ADDBA_COMPLETE; 191 tid->state &= ~AGGR_CLEANUP; 192 } 193 194 if (sendbar) { 195 ath_txq_unlock(sc, txq); 196 ath_send_bar(tid, tid->seq_start); 197 ath_txq_lock(sc, txq); 198 } 199 } 200 201 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 202 int seqno) 203 { 204 int index, cindex; 205 206 index = ATH_BA_INDEX(tid->seq_start, seqno); 207 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 208 209 __clear_bit(cindex, tid->tx_buf); 210 211 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) { 212 INCR(tid->seq_start, IEEE80211_SEQ_MAX); 213 INCR(tid->baw_head, ATH_TID_MAX_BUFS); 214 if (tid->bar_index >= 0) 215 tid->bar_index--; 216 } 217 } 218 219 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 220 u16 seqno) 221 { 222 int index, cindex; 223 224 index = ATH_BA_INDEX(tid->seq_start, seqno); 225 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 226 __set_bit(cindex, tid->tx_buf); 227 228 if (index >= ((tid->baw_tail - tid->baw_head) & 229 (ATH_TID_MAX_BUFS - 1))) { 230 tid->baw_tail = cindex; 231 INCR(tid->baw_tail, ATH_TID_MAX_BUFS); 232 } 233 } 234 235 /* 236 * TODO: For frame(s) that are in the retry state, we will reuse the 237 * sequence number(s) without setting the retry bit. The 238 * alternative is to give up on these and BAR the receiver's window 239 * forward. 240 */ 241 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq, 242 struct ath_atx_tid *tid) 243 244 { 245 struct sk_buff *skb; 246 struct ath_buf *bf; 247 struct list_head bf_head; 248 struct ath_tx_status ts; 249 struct ath_frame_info *fi; 250 251 memset(&ts, 0, sizeof(ts)); 252 INIT_LIST_HEAD(&bf_head); 253 254 while ((skb = __skb_dequeue(&tid->buf_q))) { 255 fi = get_frame_info(skb); 256 bf = fi->bf; 257 258 if (!bf) { 259 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq); 260 continue; 261 } 262 263 list_add_tail(&bf->list, &bf_head); 264 265 if (fi->retries) 266 ath_tx_update_baw(sc, tid, bf->bf_state.seqno); 267 268 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0); 269 } 270 271 tid->seq_next = tid->seq_start; 272 tid->baw_tail = tid->baw_head; 273 tid->bar_index = -1; 274 } 275 276 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq, 277 struct sk_buff *skb, int count) 278 { 279 struct ath_frame_info *fi = get_frame_info(skb); 280 struct ath_buf *bf = fi->bf; 281 struct ieee80211_hdr *hdr; 282 int prev = fi->retries; 283 284 TX_STAT_INC(txq->axq_qnum, a_retries); 285 fi->retries += count; 286 287 if (prev > 0) 288 return; 289 290 hdr = (struct ieee80211_hdr *)skb->data; 291 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); 292 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, 293 sizeof(*hdr), DMA_TO_DEVICE); 294 } 295 296 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) 297 { 298 struct ath_buf *bf = NULL; 299 300 spin_lock_bh(&sc->tx.txbuflock); 301 302 if (unlikely(list_empty(&sc->tx.txbuf))) { 303 spin_unlock_bh(&sc->tx.txbuflock); 304 return NULL; 305 } 306 307 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); 308 list_del(&bf->list); 309 310 spin_unlock_bh(&sc->tx.txbuflock); 311 312 return bf; 313 } 314 315 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf) 316 { 317 spin_lock_bh(&sc->tx.txbuflock); 318 list_add_tail(&bf->list, &sc->tx.txbuf); 319 spin_unlock_bh(&sc->tx.txbuflock); 320 } 321 322 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf) 323 { 324 struct ath_buf *tbf; 325 326 tbf = ath_tx_get_buffer(sc); 327 if (WARN_ON(!tbf)) 328 return NULL; 329 330 ATH_TXBUF_RESET(tbf); 331 332 tbf->bf_mpdu = bf->bf_mpdu; 333 tbf->bf_buf_addr = bf->bf_buf_addr; 334 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len); 335 tbf->bf_state = bf->bf_state; 336 337 return tbf; 338 } 339 340 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf, 341 struct ath_tx_status *ts, int txok, 342 int *nframes, int *nbad) 343 { 344 struct ath_frame_info *fi; 345 u16 seq_st = 0; 346 u32 ba[WME_BA_BMP_SIZE >> 5]; 347 int ba_index; 348 int isaggr = 0; 349 350 *nbad = 0; 351 *nframes = 0; 352 353 isaggr = bf_isaggr(bf); 354 if (isaggr) { 355 seq_st = ts->ts_seqnum; 356 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); 357 } 358 359 while (bf) { 360 fi = get_frame_info(bf->bf_mpdu); 361 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno); 362 363 (*nframes)++; 364 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) 365 (*nbad)++; 366 367 bf = bf->bf_next; 368 } 369 } 370 371 372 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, 373 struct ath_buf *bf, struct list_head *bf_q, 374 struct ath_tx_status *ts, int txok, bool retry) 375 { 376 struct ath_node *an = NULL; 377 struct sk_buff *skb; 378 struct ieee80211_sta *sta; 379 struct ieee80211_hw *hw = sc->hw; 380 struct ieee80211_hdr *hdr; 381 struct ieee80211_tx_info *tx_info; 382 struct ath_atx_tid *tid = NULL; 383 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; 384 struct list_head bf_head; 385 struct sk_buff_head bf_pending; 386 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first; 387 u32 ba[WME_BA_BMP_SIZE >> 5]; 388 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0; 389 bool rc_update = true; 390 struct ieee80211_tx_rate rates[4]; 391 struct ath_frame_info *fi; 392 int nframes; 393 u8 tidno; 394 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH); 395 int i, retries; 396 int bar_index = -1; 397 398 skb = bf->bf_mpdu; 399 hdr = (struct ieee80211_hdr *)skb->data; 400 401 tx_info = IEEE80211_SKB_CB(skb); 402 403 memcpy(rates, tx_info->control.rates, sizeof(rates)); 404 405 retries = ts->ts_longretry + 1; 406 for (i = 0; i < ts->ts_rateindex; i++) 407 retries += rates[i].count; 408 409 rcu_read_lock(); 410 411 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2); 412 if (!sta) { 413 rcu_read_unlock(); 414 415 INIT_LIST_HEAD(&bf_head); 416 while (bf) { 417 bf_next = bf->bf_next; 418 419 if (!bf->bf_stale || bf_next != NULL) 420 list_move_tail(&bf->list, &bf_head); 421 422 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0); 423 424 bf = bf_next; 425 } 426 return; 427 } 428 429 an = (struct ath_node *)sta->drv_priv; 430 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK; 431 tid = ATH_AN_2_TID(an, tidno); 432 seq_first = tid->seq_start; 433 434 /* 435 * The hardware occasionally sends a tx status for the wrong TID. 436 * In this case, the BA status cannot be considered valid and all 437 * subframes need to be retransmitted 438 */ 439 if (tidno != ts->tid) 440 txok = false; 441 442 isaggr = bf_isaggr(bf); 443 memset(ba, 0, WME_BA_BMP_SIZE >> 3); 444 445 if (isaggr && txok) { 446 if (ts->ts_flags & ATH9K_TX_BA) { 447 seq_st = ts->ts_seqnum; 448 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); 449 } else { 450 /* 451 * AR5416 can become deaf/mute when BA 452 * issue happens. Chip needs to be reset. 453 * But AP code may have sychronization issues 454 * when perform internal reset in this routine. 455 * Only enable reset in STA mode for now. 456 */ 457 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) 458 needreset = 1; 459 } 460 } 461 462 __skb_queue_head_init(&bf_pending); 463 464 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad); 465 while (bf) { 466 u16 seqno = bf->bf_state.seqno; 467 468 txfail = txpending = sendbar = 0; 469 bf_next = bf->bf_next; 470 471 skb = bf->bf_mpdu; 472 tx_info = IEEE80211_SKB_CB(skb); 473 fi = get_frame_info(skb); 474 475 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) { 476 /* transmit completion, subframe is 477 * acked by block ack */ 478 acked_cnt++; 479 } else if (!isaggr && txok) { 480 /* transmit completion */ 481 acked_cnt++; 482 } else if ((tid->state & AGGR_CLEANUP) || !retry) { 483 /* 484 * cleanup in progress, just fail 485 * the un-acked sub-frames 486 */ 487 txfail = 1; 488 } else if (flush) { 489 txpending = 1; 490 } else if (fi->retries < ATH_MAX_SW_RETRIES) { 491 if (txok || !an->sleeping) 492 ath_tx_set_retry(sc, txq, bf->bf_mpdu, 493 retries); 494 495 txpending = 1; 496 } else { 497 txfail = 1; 498 txfail_cnt++; 499 bar_index = max_t(int, bar_index, 500 ATH_BA_INDEX(seq_first, seqno)); 501 } 502 503 /* 504 * Make sure the last desc is reclaimed if it 505 * not a holding desc. 506 */ 507 INIT_LIST_HEAD(&bf_head); 508 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) || 509 bf_next != NULL || !bf_last->bf_stale) 510 list_move_tail(&bf->list, &bf_head); 511 512 if (!txpending || (tid->state & AGGR_CLEANUP)) { 513 /* 514 * complete the acked-ones/xretried ones; update 515 * block-ack window 516 */ 517 ath_tx_update_baw(sc, tid, seqno); 518 519 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) { 520 memcpy(tx_info->control.rates, rates, sizeof(rates)); 521 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok); 522 rc_update = false; 523 } 524 525 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 526 !txfail); 527 } else { 528 /* retry the un-acked ones */ 529 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && 530 bf->bf_next == NULL && bf_last->bf_stale) { 531 struct ath_buf *tbf; 532 533 tbf = ath_clone_txbuf(sc, bf_last); 534 /* 535 * Update tx baw and complete the 536 * frame with failed status if we 537 * run out of tx buf. 538 */ 539 if (!tbf) { 540 ath_tx_update_baw(sc, tid, seqno); 541 542 ath_tx_complete_buf(sc, bf, txq, 543 &bf_head, ts, 0); 544 bar_index = max_t(int, bar_index, 545 ATH_BA_INDEX(seq_first, seqno)); 546 break; 547 } 548 549 fi->bf = tbf; 550 } 551 552 /* 553 * Put this buffer to the temporary pending 554 * queue to retain ordering 555 */ 556 __skb_queue_tail(&bf_pending, skb); 557 } 558 559 bf = bf_next; 560 } 561 562 /* prepend un-acked frames to the beginning of the pending frame queue */ 563 if (!skb_queue_empty(&bf_pending)) { 564 if (an->sleeping) 565 ieee80211_sta_set_buffered(sta, tid->tidno, true); 566 567 skb_queue_splice(&bf_pending, &tid->buf_q); 568 if (!an->sleeping) { 569 ath_tx_queue_tid(txq, tid); 570 571 if (ts->ts_status & ATH9K_TXERR_FILT) 572 tid->ac->clear_ps_filter = true; 573 } 574 } 575 576 if (bar_index >= 0) { 577 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index); 578 579 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq)) 580 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq); 581 582 ath_txq_unlock(sc, txq); 583 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1)); 584 ath_txq_lock(sc, txq); 585 } 586 587 if (tid->state & AGGR_CLEANUP) 588 ath_tx_flush_tid(sc, tid); 589 590 rcu_read_unlock(); 591 592 if (needreset) 593 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR); 594 } 595 596 static bool ath_lookup_legacy(struct ath_buf *bf) 597 { 598 struct sk_buff *skb; 599 struct ieee80211_tx_info *tx_info; 600 struct ieee80211_tx_rate *rates; 601 int i; 602 603 skb = bf->bf_mpdu; 604 tx_info = IEEE80211_SKB_CB(skb); 605 rates = tx_info->control.rates; 606 607 for (i = 0; i < 4; i++) { 608 if (!rates[i].count || rates[i].idx < 0) 609 break; 610 611 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) 612 return true; 613 } 614 615 return false; 616 } 617 618 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, 619 struct ath_atx_tid *tid) 620 { 621 struct sk_buff *skb; 622 struct ieee80211_tx_info *tx_info; 623 struct ieee80211_tx_rate *rates; 624 u32 max_4ms_framelen, frmlen; 625 u16 aggr_limit, bt_aggr_limit, legacy = 0; 626 int q = tid->ac->txq->mac80211_qnum; 627 int i; 628 629 skb = bf->bf_mpdu; 630 tx_info = IEEE80211_SKB_CB(skb); 631 rates = tx_info->control.rates; 632 633 /* 634 * Find the lowest frame length among the rate series that will have a 635 * 4ms (or TXOP limited) transmit duration. 636 */ 637 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; 638 639 for (i = 0; i < 4; i++) { 640 int modeidx; 641 642 if (!rates[i].count) 643 continue; 644 645 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) { 646 legacy = 1; 647 break; 648 } 649 650 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 651 modeidx = MCS_HT40; 652 else 653 modeidx = MCS_HT20; 654 655 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) 656 modeidx++; 657 658 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx]; 659 max_4ms_framelen = min(max_4ms_framelen, frmlen); 660 } 661 662 /* 663 * limit aggregate size by the minimum rate if rate selected is 664 * not a probe rate, if rate selected is a probe rate then 665 * avoid aggregation of this packet. 666 */ 667 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) 668 return 0; 669 670 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX); 671 672 /* 673 * Override the default aggregation limit for BTCOEX. 674 */ 675 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen); 676 if (bt_aggr_limit) 677 aggr_limit = bt_aggr_limit; 678 679 /* 680 * h/w can accept aggregates up to 16 bit lengths (65535). 681 * The IE, however can hold up to 65536, which shows up here 682 * as zero. Ignore 65536 since we are constrained by hw. 683 */ 684 if (tid->an->maxampdu) 685 aggr_limit = min(aggr_limit, tid->an->maxampdu); 686 687 return aggr_limit; 688 } 689 690 /* 691 * Returns the number of delimiters to be added to 692 * meet the minimum required mpdudensity. 693 */ 694 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, 695 struct ath_buf *bf, u16 frmlen, 696 bool first_subfrm) 697 { 698 #define FIRST_DESC_NDELIMS 60 699 struct sk_buff *skb = bf->bf_mpdu; 700 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 701 u32 nsymbits, nsymbols; 702 u16 minlen; 703 u8 flags, rix; 704 int width, streams, half_gi, ndelim, mindelim; 705 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 706 707 /* Select standard number of delimiters based on frame length alone */ 708 ndelim = ATH_AGGR_GET_NDELIM(frmlen); 709 710 /* 711 * If encryption enabled, hardware requires some more padding between 712 * subframes. 713 * TODO - this could be improved to be dependent on the rate. 714 * The hardware can keep up at lower rates, but not higher rates 715 */ 716 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) && 717 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) 718 ndelim += ATH_AGGR_ENCRYPTDELIM; 719 720 /* 721 * Add delimiter when using RTS/CTS with aggregation 722 * and non enterprise AR9003 card 723 */ 724 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) && 725 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE)) 726 ndelim = max(ndelim, FIRST_DESC_NDELIMS); 727 728 /* 729 * Convert desired mpdu density from microeconds to bytes based 730 * on highest rate in rate series (i.e. first rate) to determine 731 * required minimum length for subframe. Take into account 732 * whether high rate is 20 or 40Mhz and half or full GI. 733 * 734 * If there is no mpdu density restriction, no further calculation 735 * is needed. 736 */ 737 738 if (tid->an->mpdudensity == 0) 739 return ndelim; 740 741 rix = tx_info->control.rates[0].idx; 742 flags = tx_info->control.rates[0].flags; 743 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; 744 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; 745 746 if (half_gi) 747 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity); 748 else 749 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity); 750 751 if (nsymbols == 0) 752 nsymbols = 1; 753 754 streams = HT_RC_2_STREAMS(rix); 755 nsymbits = bits_per_symbol[rix % 8][width] * streams; 756 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; 757 758 if (frmlen < minlen) { 759 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; 760 ndelim = max(mindelim, ndelim); 761 } 762 763 return ndelim; 764 } 765 766 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, 767 struct ath_txq *txq, 768 struct ath_atx_tid *tid, 769 struct list_head *bf_q, 770 int *aggr_len) 771 { 772 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) 773 struct ath_buf *bf, *bf_first = NULL, *bf_prev = NULL; 774 int rl = 0, nframes = 0, ndelim, prev_al = 0; 775 u16 aggr_limit = 0, al = 0, bpad = 0, 776 al_delta, h_baw = tid->baw_size / 2; 777 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE; 778 struct ieee80211_tx_info *tx_info; 779 struct ath_frame_info *fi; 780 struct sk_buff *skb; 781 u16 seqno; 782 783 do { 784 skb = skb_peek(&tid->buf_q); 785 fi = get_frame_info(skb); 786 bf = fi->bf; 787 if (!fi->bf) 788 bf = ath_tx_setup_buffer(sc, txq, tid, skb, true); 789 790 if (!bf) 791 continue; 792 793 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR; 794 seqno = bf->bf_state.seqno; 795 796 /* do not step over block-ack window */ 797 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) { 798 status = ATH_AGGR_BAW_CLOSED; 799 break; 800 } 801 802 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) { 803 struct ath_tx_status ts = {}; 804 struct list_head bf_head; 805 806 INIT_LIST_HEAD(&bf_head); 807 list_add(&bf->list, &bf_head); 808 __skb_unlink(skb, &tid->buf_q); 809 ath_tx_update_baw(sc, tid, seqno); 810 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0); 811 continue; 812 } 813 814 if (!bf_first) 815 bf_first = bf; 816 817 if (!rl) { 818 aggr_limit = ath_lookup_rate(sc, bf, tid); 819 rl = 1; 820 } 821 822 /* do not exceed aggregation limit */ 823 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen; 824 825 if (nframes && 826 ((aggr_limit < (al + bpad + al_delta + prev_al)) || 827 ath_lookup_legacy(bf))) { 828 status = ATH_AGGR_LIMITED; 829 break; 830 } 831 832 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 833 if (nframes && (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) 834 break; 835 836 /* do not exceed subframe limit */ 837 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) { 838 status = ATH_AGGR_LIMITED; 839 break; 840 } 841 842 /* add padding for previous frame to aggregation length */ 843 al += bpad + al_delta; 844 845 /* 846 * Get the delimiters needed to meet the MPDU 847 * density for this node. 848 */ 849 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen, 850 !nframes); 851 bpad = PADBYTES(al_delta) + (ndelim << 2); 852 853 nframes++; 854 bf->bf_next = NULL; 855 856 /* link buffers of this frame to the aggregate */ 857 if (!fi->retries) 858 ath_tx_addto_baw(sc, tid, seqno); 859 bf->bf_state.ndelim = ndelim; 860 861 __skb_unlink(skb, &tid->buf_q); 862 list_add_tail(&bf->list, bf_q); 863 if (bf_prev) 864 bf_prev->bf_next = bf; 865 866 bf_prev = bf; 867 868 } while (!skb_queue_empty(&tid->buf_q)); 869 870 *aggr_len = al; 871 872 return status; 873 #undef PADBYTES 874 } 875 876 /* 877 * rix - rate index 878 * pktlen - total bytes (delims + data + fcs + pads + pad delims) 879 * width - 0 for 20 MHz, 1 for 40 MHz 880 * half_gi - to use 4us v/s 3.6 us for symbol time 881 */ 882 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen, 883 int width, int half_gi, bool shortPreamble) 884 { 885 u32 nbits, nsymbits, duration, nsymbols; 886 int streams; 887 888 /* find number of symbols: PLCP + data */ 889 streams = HT_RC_2_STREAMS(rix); 890 nbits = (pktlen << 3) + OFDM_PLCP_BITS; 891 nsymbits = bits_per_symbol[rix % 8][width] * streams; 892 nsymbols = (nbits + nsymbits - 1) / nsymbits; 893 894 if (!half_gi) 895 duration = SYMBOL_TIME(nsymbols); 896 else 897 duration = SYMBOL_TIME_HALFGI(nsymbols); 898 899 /* addup duration for legacy/ht training and signal fields */ 900 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); 901 902 return duration; 903 } 904 905 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi) 906 { 907 int streams = HT_RC_2_STREAMS(mcs); 908 int symbols, bits; 909 int bytes = 0; 910 911 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec); 912 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams; 913 bits -= OFDM_PLCP_BITS; 914 bytes = bits / 8; 915 bytes -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); 916 if (bytes > 65532) 917 bytes = 65532; 918 919 return bytes; 920 } 921 922 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop) 923 { 924 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi; 925 int mcs; 926 927 /* 4ms is the default (and maximum) duration */ 928 if (!txop || txop > 4096) 929 txop = 4096; 930 931 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20]; 932 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI]; 933 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40]; 934 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI]; 935 for (mcs = 0; mcs < 32; mcs++) { 936 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false); 937 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true); 938 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false); 939 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true); 940 } 941 } 942 943 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, 944 struct ath_tx_info *info, int len) 945 { 946 struct ath_hw *ah = sc->sc_ah; 947 struct sk_buff *skb; 948 struct ieee80211_tx_info *tx_info; 949 struct ieee80211_tx_rate *rates; 950 const struct ieee80211_rate *rate; 951 struct ieee80211_hdr *hdr; 952 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu); 953 int i; 954 u8 rix = 0; 955 956 skb = bf->bf_mpdu; 957 tx_info = IEEE80211_SKB_CB(skb); 958 rates = tx_info->control.rates; 959 hdr = (struct ieee80211_hdr *)skb->data; 960 961 /* set dur_update_en for l-sig computation except for PS-Poll frames */ 962 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control); 963 info->rtscts_rate = fi->rtscts_rate; 964 965 for (i = 0; i < 4; i++) { 966 bool is_40, is_sgi, is_sp; 967 int phy; 968 969 if (!rates[i].count || (rates[i].idx < 0)) 970 continue; 971 972 rix = rates[i].idx; 973 info->rates[i].Tries = rates[i].count; 974 975 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) { 976 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; 977 info->flags |= ATH9K_TXDESC_RTSENA; 978 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 979 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; 980 info->flags |= ATH9K_TXDESC_CTSENA; 981 } 982 983 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 984 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040; 985 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) 986 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI; 987 988 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI); 989 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH); 990 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE); 991 992 if (rates[i].flags & IEEE80211_TX_RC_MCS) { 993 /* MCS rates */ 994 info->rates[i].Rate = rix | 0x80; 995 info->rates[i].ChSel = ath_txchainmask_reduction(sc, 996 ah->txchainmask, info->rates[i].Rate); 997 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len, 998 is_40, is_sgi, is_sp); 999 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC)) 1000 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC; 1001 continue; 1002 } 1003 1004 /* legacy rates */ 1005 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx]; 1006 if ((tx_info->band == IEEE80211_BAND_2GHZ) && 1007 !(rate->flags & IEEE80211_RATE_ERP_G)) 1008 phy = WLAN_RC_PHY_CCK; 1009 else 1010 phy = WLAN_RC_PHY_OFDM; 1011 1012 info->rates[i].Rate = rate->hw_value; 1013 if (rate->hw_value_short) { 1014 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 1015 info->rates[i].Rate |= rate->hw_value_short; 1016 } else { 1017 is_sp = false; 1018 } 1019 1020 if (bf->bf_state.bfs_paprd) 1021 info->rates[i].ChSel = ah->txchainmask; 1022 else 1023 info->rates[i].ChSel = ath_txchainmask_reduction(sc, 1024 ah->txchainmask, info->rates[i].Rate); 1025 1026 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah, 1027 phy, rate->bitrate * 100, len, rix, is_sp); 1028 } 1029 1030 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ 1031 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit)) 1032 info->flags &= ~ATH9K_TXDESC_RTSENA; 1033 1034 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */ 1035 if (info->flags & ATH9K_TXDESC_RTSENA) 1036 info->flags &= ~ATH9K_TXDESC_CTSENA; 1037 } 1038 1039 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) 1040 { 1041 struct ieee80211_hdr *hdr; 1042 enum ath9k_pkt_type htype; 1043 __le16 fc; 1044 1045 hdr = (struct ieee80211_hdr *)skb->data; 1046 fc = hdr->frame_control; 1047 1048 if (ieee80211_is_beacon(fc)) 1049 htype = ATH9K_PKT_TYPE_BEACON; 1050 else if (ieee80211_is_probe_resp(fc)) 1051 htype = ATH9K_PKT_TYPE_PROBE_RESP; 1052 else if (ieee80211_is_atim(fc)) 1053 htype = ATH9K_PKT_TYPE_ATIM; 1054 else if (ieee80211_is_pspoll(fc)) 1055 htype = ATH9K_PKT_TYPE_PSPOLL; 1056 else 1057 htype = ATH9K_PKT_TYPE_NORMAL; 1058 1059 return htype; 1060 } 1061 1062 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf, 1063 struct ath_txq *txq, int len) 1064 { 1065 struct ath_hw *ah = sc->sc_ah; 1066 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 1067 struct ath_buf *bf_first = bf; 1068 struct ath_tx_info info; 1069 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR); 1070 1071 memset(&info, 0, sizeof(info)); 1072 info.is_first = true; 1073 info.is_last = true; 1074 info.txpower = MAX_RATE_POWER; 1075 info.qcu = txq->axq_qnum; 1076 1077 info.flags = ATH9K_TXDESC_INTREQ; 1078 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) 1079 info.flags |= ATH9K_TXDESC_NOACK; 1080 if (tx_info->flags & IEEE80211_TX_CTL_LDPC) 1081 info.flags |= ATH9K_TXDESC_LDPC; 1082 1083 ath_buf_set_rate(sc, bf, &info, len); 1084 1085 if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) 1086 info.flags |= ATH9K_TXDESC_CLRDMASK; 1087 1088 if (bf->bf_state.bfs_paprd) 1089 info.flags |= (u32) bf->bf_state.bfs_paprd << ATH9K_TXDESC_PAPRD_S; 1090 1091 1092 while (bf) { 1093 struct sk_buff *skb = bf->bf_mpdu; 1094 struct ath_frame_info *fi = get_frame_info(skb); 1095 1096 info.type = get_hw_packet_type(skb); 1097 if (bf->bf_next) 1098 info.link = bf->bf_next->bf_daddr; 1099 else 1100 info.link = 0; 1101 1102 info.buf_addr[0] = bf->bf_buf_addr; 1103 info.buf_len[0] = skb->len; 1104 info.pkt_len = fi->framelen; 1105 info.keyix = fi->keyix; 1106 info.keytype = fi->keytype; 1107 1108 if (aggr) { 1109 if (bf == bf_first) 1110 info.aggr = AGGR_BUF_FIRST; 1111 else if (!bf->bf_next) 1112 info.aggr = AGGR_BUF_LAST; 1113 else 1114 info.aggr = AGGR_BUF_MIDDLE; 1115 1116 info.ndelim = bf->bf_state.ndelim; 1117 info.aggr_len = len; 1118 } 1119 1120 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info); 1121 bf = bf->bf_next; 1122 } 1123 } 1124 1125 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, 1126 struct ath_atx_tid *tid) 1127 { 1128 struct ath_buf *bf; 1129 enum ATH_AGGR_STATUS status; 1130 struct ieee80211_tx_info *tx_info; 1131 struct list_head bf_q; 1132 int aggr_len; 1133 1134 do { 1135 if (skb_queue_empty(&tid->buf_q)) 1136 return; 1137 1138 INIT_LIST_HEAD(&bf_q); 1139 1140 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len); 1141 1142 /* 1143 * no frames picked up to be aggregated; 1144 * block-ack window is not open. 1145 */ 1146 if (list_empty(&bf_q)) 1147 break; 1148 1149 bf = list_first_entry(&bf_q, struct ath_buf, list); 1150 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list); 1151 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu); 1152 1153 if (tid->ac->clear_ps_filter) { 1154 tid->ac->clear_ps_filter = false; 1155 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; 1156 } else { 1157 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT; 1158 } 1159 1160 /* if only one frame, send as non-aggregate */ 1161 if (bf == bf->bf_lastbf) { 1162 aggr_len = get_frame_info(bf->bf_mpdu)->framelen; 1163 bf->bf_state.bf_type = BUF_AMPDU; 1164 } else { 1165 TX_STAT_INC(txq->axq_qnum, a_aggr); 1166 } 1167 1168 ath_tx_fill_desc(sc, bf, txq, aggr_len); 1169 ath_tx_txqaddbuf(sc, txq, &bf_q, false); 1170 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH && 1171 status != ATH_AGGR_BAW_CLOSED); 1172 } 1173 1174 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, 1175 u16 tid, u16 *ssn) 1176 { 1177 struct ath_atx_tid *txtid; 1178 struct ath_node *an; 1179 u8 density; 1180 1181 an = (struct ath_node *)sta->drv_priv; 1182 txtid = ATH_AN_2_TID(an, tid); 1183 1184 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE)) 1185 return -EAGAIN; 1186 1187 /* update ampdu factor/density, they may have changed. This may happen 1188 * in HT IBSS when a beacon with HT-info is received after the station 1189 * has already been added. 1190 */ 1191 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { 1192 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + 1193 sta->ht_cap.ampdu_factor); 1194 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density); 1195 an->mpdudensity = density; 1196 } 1197 1198 txtid->state |= AGGR_ADDBA_PROGRESS; 1199 txtid->paused = true; 1200 *ssn = txtid->seq_start = txtid->seq_next; 1201 txtid->bar_index = -1; 1202 1203 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf)); 1204 txtid->baw_head = txtid->baw_tail = 0; 1205 1206 return 0; 1207 } 1208 1209 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) 1210 { 1211 struct ath_node *an = (struct ath_node *)sta->drv_priv; 1212 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); 1213 struct ath_txq *txq = txtid->ac->txq; 1214 1215 if (txtid->state & AGGR_CLEANUP) 1216 return; 1217 1218 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) { 1219 txtid->state &= ~AGGR_ADDBA_PROGRESS; 1220 return; 1221 } 1222 1223 ath_txq_lock(sc, txq); 1224 txtid->paused = true; 1225 1226 /* 1227 * If frames are still being transmitted for this TID, they will be 1228 * cleaned up during tx completion. To prevent race conditions, this 1229 * TID can only be reused after all in-progress subframes have been 1230 * completed. 1231 */ 1232 if (txtid->baw_head != txtid->baw_tail) 1233 txtid->state |= AGGR_CLEANUP; 1234 else 1235 txtid->state &= ~AGGR_ADDBA_COMPLETE; 1236 1237 ath_tx_flush_tid(sc, txtid); 1238 ath_txq_unlock_complete(sc, txq); 1239 } 1240 1241 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc, 1242 struct ath_node *an) 1243 { 1244 struct ath_atx_tid *tid; 1245 struct ath_atx_ac *ac; 1246 struct ath_txq *txq; 1247 bool buffered; 1248 int tidno; 1249 1250 for (tidno = 0, tid = &an->tid[tidno]; 1251 tidno < WME_NUM_TID; tidno++, tid++) { 1252 1253 if (!tid->sched) 1254 continue; 1255 1256 ac = tid->ac; 1257 txq = ac->txq; 1258 1259 ath_txq_lock(sc, txq); 1260 1261 buffered = !skb_queue_empty(&tid->buf_q); 1262 1263 tid->sched = false; 1264 list_del(&tid->list); 1265 1266 if (ac->sched) { 1267 ac->sched = false; 1268 list_del(&ac->list); 1269 } 1270 1271 ath_txq_unlock(sc, txq); 1272 1273 ieee80211_sta_set_buffered(sta, tidno, buffered); 1274 } 1275 } 1276 1277 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an) 1278 { 1279 struct ath_atx_tid *tid; 1280 struct ath_atx_ac *ac; 1281 struct ath_txq *txq; 1282 int tidno; 1283 1284 for (tidno = 0, tid = &an->tid[tidno]; 1285 tidno < WME_NUM_TID; tidno++, tid++) { 1286 1287 ac = tid->ac; 1288 txq = ac->txq; 1289 1290 ath_txq_lock(sc, txq); 1291 ac->clear_ps_filter = true; 1292 1293 if (!skb_queue_empty(&tid->buf_q) && !tid->paused) { 1294 ath_tx_queue_tid(txq, tid); 1295 ath_txq_schedule(sc, txq); 1296 } 1297 1298 ath_txq_unlock_complete(sc, txq); 1299 } 1300 } 1301 1302 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) 1303 { 1304 struct ath_atx_tid *txtid; 1305 struct ath_node *an; 1306 1307 an = (struct ath_node *)sta->drv_priv; 1308 1309 txtid = ATH_AN_2_TID(an, tid); 1310 txtid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor; 1311 txtid->state |= AGGR_ADDBA_COMPLETE; 1312 txtid->state &= ~AGGR_ADDBA_PROGRESS; 1313 ath_tx_resume_tid(sc, txtid); 1314 } 1315 1316 /********************/ 1317 /* Queue Management */ 1318 /********************/ 1319 1320 static void ath_txq_drain_pending_buffers(struct ath_softc *sc, 1321 struct ath_txq *txq) 1322 { 1323 struct ath_atx_ac *ac, *ac_tmp; 1324 struct ath_atx_tid *tid, *tid_tmp; 1325 1326 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) { 1327 list_del(&ac->list); 1328 ac->sched = false; 1329 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) { 1330 list_del(&tid->list); 1331 tid->sched = false; 1332 ath_tid_drain(sc, txq, tid); 1333 } 1334 } 1335 } 1336 1337 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 1338 { 1339 struct ath_hw *ah = sc->sc_ah; 1340 struct ath9k_tx_queue_info qi; 1341 static const int subtype_txq_to_hwq[] = { 1342 [WME_AC_BE] = ATH_TXQ_AC_BE, 1343 [WME_AC_BK] = ATH_TXQ_AC_BK, 1344 [WME_AC_VI] = ATH_TXQ_AC_VI, 1345 [WME_AC_VO] = ATH_TXQ_AC_VO, 1346 }; 1347 int axq_qnum, i; 1348 1349 memset(&qi, 0, sizeof(qi)); 1350 qi.tqi_subtype = subtype_txq_to_hwq[subtype]; 1351 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; 1352 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; 1353 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; 1354 qi.tqi_physCompBuf = 0; 1355 1356 /* 1357 * Enable interrupts only for EOL and DESC conditions. 1358 * We mark tx descriptors to receive a DESC interrupt 1359 * when a tx queue gets deep; otherwise waiting for the 1360 * EOL to reap descriptors. Note that this is done to 1361 * reduce interrupt load and this only defers reaping 1362 * descriptors, never transmitting frames. Aside from 1363 * reducing interrupts this also permits more concurrency. 1364 * The only potential downside is if the tx queue backs 1365 * up in which case the top half of the kernel may backup 1366 * due to a lack of tx descriptors. 1367 * 1368 * The UAPSD queue is an exception, since we take a desc- 1369 * based intr on the EOSP frames. 1370 */ 1371 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1372 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE; 1373 } else { 1374 if (qtype == ATH9K_TX_QUEUE_UAPSD) 1375 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; 1376 else 1377 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | 1378 TXQ_FLAG_TXDESCINT_ENABLE; 1379 } 1380 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); 1381 if (axq_qnum == -1) { 1382 /* 1383 * NB: don't print a message, this happens 1384 * normally on parts with too few tx queues 1385 */ 1386 return NULL; 1387 } 1388 if (!ATH_TXQ_SETUP(sc, axq_qnum)) { 1389 struct ath_txq *txq = &sc->tx.txq[axq_qnum]; 1390 1391 txq->axq_qnum = axq_qnum; 1392 txq->mac80211_qnum = -1; 1393 txq->axq_link = NULL; 1394 __skb_queue_head_init(&txq->complete_q); 1395 INIT_LIST_HEAD(&txq->axq_q); 1396 INIT_LIST_HEAD(&txq->axq_acq); 1397 spin_lock_init(&txq->axq_lock); 1398 txq->axq_depth = 0; 1399 txq->axq_ampdu_depth = 0; 1400 txq->axq_tx_inprogress = false; 1401 sc->tx.txqsetup |= 1<<axq_qnum; 1402 1403 txq->txq_headidx = txq->txq_tailidx = 0; 1404 for (i = 0; i < ATH_TXFIFO_DEPTH; i++) 1405 INIT_LIST_HEAD(&txq->txq_fifo[i]); 1406 } 1407 return &sc->tx.txq[axq_qnum]; 1408 } 1409 1410 int ath_txq_update(struct ath_softc *sc, int qnum, 1411 struct ath9k_tx_queue_info *qinfo) 1412 { 1413 struct ath_hw *ah = sc->sc_ah; 1414 int error = 0; 1415 struct ath9k_tx_queue_info qi; 1416 1417 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum); 1418 1419 ath9k_hw_get_txq_props(ah, qnum, &qi); 1420 qi.tqi_aifs = qinfo->tqi_aifs; 1421 qi.tqi_cwmin = qinfo->tqi_cwmin; 1422 qi.tqi_cwmax = qinfo->tqi_cwmax; 1423 qi.tqi_burstTime = qinfo->tqi_burstTime; 1424 qi.tqi_readyTime = qinfo->tqi_readyTime; 1425 1426 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { 1427 ath_err(ath9k_hw_common(sc->sc_ah), 1428 "Unable to update hardware queue %u!\n", qnum); 1429 error = -EIO; 1430 } else { 1431 ath9k_hw_resettxqueue(ah, qnum); 1432 } 1433 1434 return error; 1435 } 1436 1437 int ath_cabq_update(struct ath_softc *sc) 1438 { 1439 struct ath9k_tx_queue_info qi; 1440 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf; 1441 int qnum = sc->beacon.cabq->axq_qnum; 1442 1443 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); 1444 /* 1445 * Ensure the readytime % is within the bounds. 1446 */ 1447 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND) 1448 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND; 1449 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND) 1450 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND; 1451 1452 qi.tqi_readyTime = (cur_conf->beacon_interval * 1453 sc->config.cabqReadytime) / 100; 1454 ath_txq_update(sc, qnum, &qi); 1455 1456 return 0; 1457 } 1458 1459 static bool bf_is_ampdu_not_probing(struct ath_buf *bf) 1460 { 1461 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu); 1462 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE); 1463 } 1464 1465 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq, 1466 struct list_head *list, bool retry_tx) 1467 { 1468 struct ath_buf *bf, *lastbf; 1469 struct list_head bf_head; 1470 struct ath_tx_status ts; 1471 1472 memset(&ts, 0, sizeof(ts)); 1473 ts.ts_status = ATH9K_TX_FLUSH; 1474 INIT_LIST_HEAD(&bf_head); 1475 1476 while (!list_empty(list)) { 1477 bf = list_first_entry(list, struct ath_buf, list); 1478 1479 if (bf->bf_stale) { 1480 list_del(&bf->list); 1481 1482 ath_tx_return_buffer(sc, bf); 1483 continue; 1484 } 1485 1486 lastbf = bf->bf_lastbf; 1487 list_cut_position(&bf_head, list, &lastbf->list); 1488 1489 txq->axq_depth--; 1490 if (bf_is_ampdu_not_probing(bf)) 1491 txq->axq_ampdu_depth--; 1492 1493 if (bf_isampdu(bf)) 1494 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0, 1495 retry_tx); 1496 else 1497 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0); 1498 } 1499 } 1500 1501 /* 1502 * Drain a given TX queue (could be Beacon or Data) 1503 * 1504 * This assumes output has been stopped and 1505 * we do not need to block ath_tx_tasklet. 1506 */ 1507 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx) 1508 { 1509 ath_txq_lock(sc, txq); 1510 1511 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 1512 int idx = txq->txq_tailidx; 1513 1514 while (!list_empty(&txq->txq_fifo[idx])) { 1515 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx], 1516 retry_tx); 1517 1518 INCR(idx, ATH_TXFIFO_DEPTH); 1519 } 1520 txq->txq_tailidx = idx; 1521 } 1522 1523 txq->axq_link = NULL; 1524 txq->axq_tx_inprogress = false; 1525 ath_drain_txq_list(sc, txq, &txq->axq_q, retry_tx); 1526 1527 /* flush any pending frames if aggregation is enabled */ 1528 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) && !retry_tx) 1529 ath_txq_drain_pending_buffers(sc, txq); 1530 1531 ath_txq_unlock_complete(sc, txq); 1532 } 1533 1534 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) 1535 { 1536 struct ath_hw *ah = sc->sc_ah; 1537 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1538 struct ath_txq *txq; 1539 int i; 1540 u32 npend = 0; 1541 1542 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) 1543 return true; 1544 1545 ath9k_hw_abort_tx_dma(ah); 1546 1547 /* Check if any queue remains active */ 1548 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1549 if (!ATH_TXQ_SETUP(sc, i)) 1550 continue; 1551 1552 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum)) 1553 npend |= BIT(i); 1554 } 1555 1556 if (npend) 1557 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend); 1558 1559 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1560 if (!ATH_TXQ_SETUP(sc, i)) 1561 continue; 1562 1563 /* 1564 * The caller will resume queues with ieee80211_wake_queues. 1565 * Mark the queue as not stopped to prevent ath_tx_complete 1566 * from waking the queue too early. 1567 */ 1568 txq = &sc->tx.txq[i]; 1569 txq->stopped = false; 1570 ath_draintxq(sc, txq, retry_tx); 1571 } 1572 1573 return !npend; 1574 } 1575 1576 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 1577 { 1578 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); 1579 sc->tx.txqsetup &= ~(1<<txq->axq_qnum); 1580 } 1581 1582 /* For each axq_acq entry, for each tid, try to schedule packets 1583 * for transmit until ampdu_depth has reached min Q depth. 1584 */ 1585 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) 1586 { 1587 struct ath_atx_ac *ac, *ac_tmp, *last_ac; 1588 struct ath_atx_tid *tid, *last_tid; 1589 1590 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags) || 1591 list_empty(&txq->axq_acq) || 1592 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) 1593 return; 1594 1595 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list); 1596 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list); 1597 1598 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) { 1599 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list); 1600 list_del(&ac->list); 1601 ac->sched = false; 1602 1603 while (!list_empty(&ac->tid_q)) { 1604 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, 1605 list); 1606 list_del(&tid->list); 1607 tid->sched = false; 1608 1609 if (tid->paused) 1610 continue; 1611 1612 ath_tx_sched_aggr(sc, txq, tid); 1613 1614 /* 1615 * add tid to round-robin queue if more frames 1616 * are pending for the tid 1617 */ 1618 if (!skb_queue_empty(&tid->buf_q)) 1619 ath_tx_queue_tid(txq, tid); 1620 1621 if (tid == last_tid || 1622 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) 1623 break; 1624 } 1625 1626 if (!list_empty(&ac->tid_q) && !ac->sched) { 1627 ac->sched = true; 1628 list_add_tail(&ac->list, &txq->axq_acq); 1629 } 1630 1631 if (ac == last_ac || 1632 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) 1633 return; 1634 } 1635 } 1636 1637 /***********/ 1638 /* TX, DMA */ 1639 /***********/ 1640 1641 /* 1642 * Insert a chain of ath_buf (descriptors) on a txq and 1643 * assume the descriptors are already chained together by caller. 1644 */ 1645 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 1646 struct list_head *head, bool internal) 1647 { 1648 struct ath_hw *ah = sc->sc_ah; 1649 struct ath_common *common = ath9k_hw_common(ah); 1650 struct ath_buf *bf, *bf_last; 1651 bool puttxbuf = false; 1652 bool edma; 1653 1654 /* 1655 * Insert the frame on the outbound list and 1656 * pass it on to the hardware. 1657 */ 1658 1659 if (list_empty(head)) 1660 return; 1661 1662 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); 1663 bf = list_first_entry(head, struct ath_buf, list); 1664 bf_last = list_entry(head->prev, struct ath_buf, list); 1665 1666 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n", 1667 txq->axq_qnum, txq->axq_depth); 1668 1669 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) { 1670 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]); 1671 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH); 1672 puttxbuf = true; 1673 } else { 1674 list_splice_tail_init(head, &txq->axq_q); 1675 1676 if (txq->axq_link) { 1677 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr); 1678 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n", 1679 txq->axq_qnum, txq->axq_link, 1680 ito64(bf->bf_daddr), bf->bf_desc); 1681 } else if (!edma) 1682 puttxbuf = true; 1683 1684 txq->axq_link = bf_last->bf_desc; 1685 } 1686 1687 if (puttxbuf) { 1688 TX_STAT_INC(txq->axq_qnum, puttxbuf); 1689 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 1690 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n", 1691 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); 1692 } 1693 1694 if (!edma) { 1695 TX_STAT_INC(txq->axq_qnum, txstart); 1696 ath9k_hw_txstart(ah, txq->axq_qnum); 1697 } 1698 1699 if (!internal) { 1700 txq->axq_depth++; 1701 if (bf_is_ampdu_not_probing(bf)) 1702 txq->axq_ampdu_depth++; 1703 } 1704 } 1705 1706 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid, 1707 struct sk_buff *skb, struct ath_tx_control *txctl) 1708 { 1709 struct ath_frame_info *fi = get_frame_info(skb); 1710 struct list_head bf_head; 1711 struct ath_buf *bf; 1712 1713 /* 1714 * Do not queue to h/w when any of the following conditions is true: 1715 * - there are pending frames in software queue 1716 * - the TID is currently paused for ADDBA/BAR request 1717 * - seqno is not within block-ack window 1718 * - h/w queue depth exceeds low water mark 1719 */ 1720 if (!skb_queue_empty(&tid->buf_q) || tid->paused || 1721 !BAW_WITHIN(tid->seq_start, tid->baw_size, tid->seq_next) || 1722 txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) { 1723 /* 1724 * Add this frame to software queue for scheduling later 1725 * for aggregation. 1726 */ 1727 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw); 1728 __skb_queue_tail(&tid->buf_q, skb); 1729 if (!txctl->an || !txctl->an->sleeping) 1730 ath_tx_queue_tid(txctl->txq, tid); 1731 return; 1732 } 1733 1734 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb, false); 1735 if (!bf) 1736 return; 1737 1738 bf->bf_state.bf_type = BUF_AMPDU; 1739 INIT_LIST_HEAD(&bf_head); 1740 list_add(&bf->list, &bf_head); 1741 1742 /* Add sub-frame to BAW */ 1743 ath_tx_addto_baw(sc, tid, bf->bf_state.seqno); 1744 1745 /* Queue to h/w without aggregation */ 1746 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw); 1747 bf->bf_lastbf = bf; 1748 ath_tx_fill_desc(sc, bf, txctl->txq, fi->framelen); 1749 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false); 1750 } 1751 1752 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, 1753 struct ath_atx_tid *tid, struct sk_buff *skb) 1754 { 1755 struct ath_frame_info *fi = get_frame_info(skb); 1756 struct list_head bf_head; 1757 struct ath_buf *bf; 1758 1759 bf = fi->bf; 1760 if (!bf) 1761 bf = ath_tx_setup_buffer(sc, txq, tid, skb, false); 1762 1763 if (!bf) 1764 return; 1765 1766 INIT_LIST_HEAD(&bf_head); 1767 list_add_tail(&bf->list, &bf_head); 1768 bf->bf_state.bf_type = 0; 1769 1770 bf->bf_lastbf = bf; 1771 ath_tx_fill_desc(sc, bf, txq, fi->framelen); 1772 ath_tx_txqaddbuf(sc, txq, &bf_head, false); 1773 TX_STAT_INC(txq->axq_qnum, queued); 1774 } 1775 1776 static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb, 1777 int framelen) 1778 { 1779 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1780 struct ieee80211_sta *sta = tx_info->control.sta; 1781 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key; 1782 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1783 const struct ieee80211_rate *rate; 1784 struct ath_frame_info *fi = get_frame_info(skb); 1785 struct ath_node *an = NULL; 1786 enum ath9k_key_type keytype; 1787 bool short_preamble = false; 1788 1789 /* 1790 * We check if Short Preamble is needed for the CTS rate by 1791 * checking the BSS's global flag. 1792 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. 1793 */ 1794 if (tx_info->control.vif && 1795 tx_info->control.vif->bss_conf.use_short_preamble) 1796 short_preamble = true; 1797 1798 rate = ieee80211_get_rts_cts_rate(hw, tx_info); 1799 keytype = ath9k_cmn_get_hw_crypto_keytype(skb); 1800 1801 if (sta) 1802 an = (struct ath_node *) sta->drv_priv; 1803 1804 memset(fi, 0, sizeof(*fi)); 1805 if (hw_key) 1806 fi->keyix = hw_key->hw_key_idx; 1807 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0) 1808 fi->keyix = an->ps_key; 1809 else 1810 fi->keyix = ATH9K_TXKEYIX_INVALID; 1811 fi->keytype = keytype; 1812 fi->framelen = framelen; 1813 fi->rtscts_rate = rate->hw_value; 1814 if (short_preamble) 1815 fi->rtscts_rate |= rate->hw_value_short; 1816 } 1817 1818 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate) 1819 { 1820 struct ath_hw *ah = sc->sc_ah; 1821 struct ath9k_channel *curchan = ah->curchan; 1822 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && 1823 (curchan->channelFlags & CHANNEL_5GHZ) && 1824 (chainmask == 0x7) && (rate < 0x90)) 1825 return 0x3; 1826 else 1827 return chainmask; 1828 } 1829 1830 /* 1831 * Assign a descriptor (and sequence number if necessary, 1832 * and map buffer for DMA. Frees skb on error 1833 */ 1834 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc, 1835 struct ath_txq *txq, 1836 struct ath_atx_tid *tid, 1837 struct sk_buff *skb, 1838 bool dequeue) 1839 { 1840 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 1841 struct ath_frame_info *fi = get_frame_info(skb); 1842 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1843 struct ath_buf *bf; 1844 int fragno; 1845 u16 seqno; 1846 1847 bf = ath_tx_get_buffer(sc); 1848 if (!bf) { 1849 ath_dbg(common, XMIT, "TX buffers are full\n"); 1850 goto error; 1851 } 1852 1853 ATH_TXBUF_RESET(bf); 1854 1855 if (tid) { 1856 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG; 1857 seqno = tid->seq_next; 1858 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT); 1859 1860 if (fragno) 1861 hdr->seq_ctrl |= cpu_to_le16(fragno); 1862 1863 if (!ieee80211_has_morefrags(hdr->frame_control)) 1864 INCR(tid->seq_next, IEEE80211_SEQ_MAX); 1865 1866 bf->bf_state.seqno = seqno; 1867 } 1868 1869 bf->bf_mpdu = skb; 1870 1871 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, 1872 skb->len, DMA_TO_DEVICE); 1873 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) { 1874 bf->bf_mpdu = NULL; 1875 bf->bf_buf_addr = 0; 1876 ath_err(ath9k_hw_common(sc->sc_ah), 1877 "dma_mapping_error() on TX\n"); 1878 ath_tx_return_buffer(sc, bf); 1879 goto error; 1880 } 1881 1882 fi->bf = bf; 1883 1884 return bf; 1885 1886 error: 1887 if (dequeue) 1888 __skb_unlink(skb, &tid->buf_q); 1889 dev_kfree_skb_any(skb); 1890 return NULL; 1891 } 1892 1893 /* FIXME: tx power */ 1894 static void ath_tx_start_dma(struct ath_softc *sc, struct sk_buff *skb, 1895 struct ath_tx_control *txctl) 1896 { 1897 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1898 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1899 struct ath_atx_tid *tid = NULL; 1900 struct ath_buf *bf; 1901 u8 tidno; 1902 1903 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) && txctl->an && 1904 ieee80211_is_data_qos(hdr->frame_control)) { 1905 tidno = ieee80211_get_qos_ctl(hdr)[0] & 1906 IEEE80211_QOS_CTL_TID_MASK; 1907 tid = ATH_AN_2_TID(txctl->an, tidno); 1908 1909 WARN_ON(tid->ac->txq != txctl->txq); 1910 } 1911 1912 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) { 1913 /* 1914 * Try aggregation if it's a unicast data frame 1915 * and the destination is HT capable. 1916 */ 1917 ath_tx_send_ampdu(sc, tid, skb, txctl); 1918 } else { 1919 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb, false); 1920 if (!bf) 1921 return; 1922 1923 bf->bf_state.bfs_paprd = txctl->paprd; 1924 1925 if (txctl->paprd) 1926 bf->bf_state.bfs_paprd_timestamp = jiffies; 1927 1928 ath_tx_send_normal(sc, txctl->txq, tid, skb); 1929 } 1930 } 1931 1932 /* Upon failure caller should free skb */ 1933 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, 1934 struct ath_tx_control *txctl) 1935 { 1936 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 1937 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1938 struct ieee80211_sta *sta = info->control.sta; 1939 struct ieee80211_vif *vif = info->control.vif; 1940 struct ath_softc *sc = hw->priv; 1941 struct ath_txq *txq = txctl->txq; 1942 int padpos, padsize; 1943 int frmlen = skb->len + FCS_LEN; 1944 int q; 1945 1946 /* NOTE: sta can be NULL according to net/mac80211.h */ 1947 if (sta) 1948 txctl->an = (struct ath_node *)sta->drv_priv; 1949 1950 if (info->control.hw_key) 1951 frmlen += info->control.hw_key->icv_len; 1952 1953 /* 1954 * As a temporary workaround, assign seq# here; this will likely need 1955 * to be cleaned up to work better with Beacon transmission and virtual 1956 * BSSes. 1957 */ 1958 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { 1959 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) 1960 sc->tx.seq_no += 0x10; 1961 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); 1962 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); 1963 } 1964 1965 /* Add the padding after the header if this is not already done */ 1966 padpos = ath9k_cmn_padpos(hdr->frame_control); 1967 padsize = padpos & 3; 1968 if (padsize && skb->len > padpos) { 1969 if (skb_headroom(skb) < padsize) 1970 return -ENOMEM; 1971 1972 skb_push(skb, padsize); 1973 memmove(skb->data, skb->data + padsize, padpos); 1974 hdr = (struct ieee80211_hdr *) skb->data; 1975 } 1976 1977 if ((vif && vif->type != NL80211_IFTYPE_AP && 1978 vif->type != NL80211_IFTYPE_AP_VLAN) || 1979 !ieee80211_is_data(hdr->frame_control)) 1980 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT; 1981 1982 setup_frame_info(hw, skb, frmlen); 1983 1984 /* 1985 * At this point, the vif, hw_key and sta pointers in the tx control 1986 * info are no longer valid (overwritten by the ath_frame_info data. 1987 */ 1988 1989 q = skb_get_queue_mapping(skb); 1990 1991 ath_txq_lock(sc, txq); 1992 if (txq == sc->tx.txq_map[q] && 1993 ++txq->pending_frames > sc->tx.txq_max_pending[q] && 1994 !txq->stopped) { 1995 ieee80211_stop_queue(sc->hw, q); 1996 txq->stopped = true; 1997 } 1998 1999 ath_tx_start_dma(sc, skb, txctl); 2000 2001 ath_txq_unlock(sc, txq); 2002 2003 return 0; 2004 } 2005 2006 /*****************/ 2007 /* TX Completion */ 2008 /*****************/ 2009 2010 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, 2011 int tx_flags, struct ath_txq *txq) 2012 { 2013 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2014 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2015 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; 2016 int q, padpos, padsize; 2017 unsigned long flags; 2018 2019 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb); 2020 2021 if (sc->sc_ah->caldata) 2022 sc->sc_ah->caldata->paprd_packet_sent = true; 2023 2024 if (!(tx_flags & ATH_TX_ERROR)) 2025 /* Frame was ACKed */ 2026 tx_info->flags |= IEEE80211_TX_STAT_ACK; 2027 2028 padpos = ath9k_cmn_padpos(hdr->frame_control); 2029 padsize = padpos & 3; 2030 if (padsize && skb->len>padpos+padsize) { 2031 /* 2032 * Remove MAC header padding before giving the frame back to 2033 * mac80211. 2034 */ 2035 memmove(skb->data + padsize, skb->data, padpos); 2036 skb_pull(skb, padsize); 2037 } 2038 2039 spin_lock_irqsave(&sc->sc_pm_lock, flags); 2040 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) { 2041 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK; 2042 ath_dbg(common, PS, 2043 "Going back to sleep after having received TX status (0x%lx)\n", 2044 sc->ps_flags & (PS_WAIT_FOR_BEACON | 2045 PS_WAIT_FOR_CAB | 2046 PS_WAIT_FOR_PSPOLL_DATA | 2047 PS_WAIT_FOR_TX_ACK)); 2048 } 2049 spin_unlock_irqrestore(&sc->sc_pm_lock, flags); 2050 2051 q = skb_get_queue_mapping(skb); 2052 if (txq == sc->tx.txq_map[q]) { 2053 if (WARN_ON(--txq->pending_frames < 0)) 2054 txq->pending_frames = 0; 2055 2056 if (txq->stopped && 2057 txq->pending_frames < sc->tx.txq_max_pending[q]) { 2058 ieee80211_wake_queue(sc->hw, q); 2059 txq->stopped = false; 2060 } 2061 } 2062 2063 __skb_queue_tail(&txq->complete_q, skb); 2064 } 2065 2066 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 2067 struct ath_txq *txq, struct list_head *bf_q, 2068 struct ath_tx_status *ts, int txok) 2069 { 2070 struct sk_buff *skb = bf->bf_mpdu; 2071 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2072 unsigned long flags; 2073 int tx_flags = 0; 2074 2075 if (!txok) 2076 tx_flags |= ATH_TX_ERROR; 2077 2078 if (ts->ts_status & ATH9K_TXERR_FILT) 2079 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 2080 2081 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE); 2082 bf->bf_buf_addr = 0; 2083 2084 if (bf->bf_state.bfs_paprd) { 2085 if (time_after(jiffies, 2086 bf->bf_state.bfs_paprd_timestamp + 2087 msecs_to_jiffies(ATH_PAPRD_TIMEOUT))) 2088 dev_kfree_skb_any(skb); 2089 else 2090 complete(&sc->paprd_complete); 2091 } else { 2092 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags); 2093 ath_tx_complete(sc, skb, tx_flags, txq); 2094 } 2095 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't 2096 * accidentally reference it later. 2097 */ 2098 bf->bf_mpdu = NULL; 2099 2100 /* 2101 * Return the list of ath_buf of this mpdu to free queue 2102 */ 2103 spin_lock_irqsave(&sc->tx.txbuflock, flags); 2104 list_splice_tail_init(bf_q, &sc->tx.txbuf); 2105 spin_unlock_irqrestore(&sc->tx.txbuflock, flags); 2106 } 2107 2108 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf, 2109 struct ath_tx_status *ts, int nframes, int nbad, 2110 int txok) 2111 { 2112 struct sk_buff *skb = bf->bf_mpdu; 2113 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2114 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 2115 struct ieee80211_hw *hw = sc->hw; 2116 struct ath_hw *ah = sc->sc_ah; 2117 u8 i, tx_rateindex; 2118 2119 if (txok) 2120 tx_info->status.ack_signal = ts->ts_rssi; 2121 2122 tx_rateindex = ts->ts_rateindex; 2123 WARN_ON(tx_rateindex >= hw->max_rates); 2124 2125 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { 2126 tx_info->flags |= IEEE80211_TX_STAT_AMPDU; 2127 2128 BUG_ON(nbad > nframes); 2129 } 2130 tx_info->status.ampdu_len = nframes; 2131 tx_info->status.ampdu_ack_len = nframes - nbad; 2132 2133 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 && 2134 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) { 2135 /* 2136 * If an underrun error is seen assume it as an excessive 2137 * retry only if max frame trigger level has been reached 2138 * (2 KB for single stream, and 4 KB for dual stream). 2139 * Adjust the long retry as if the frame was tried 2140 * hw->max_rate_tries times to affect how rate control updates 2141 * PER for the failed rate. 2142 * In case of congestion on the bus penalizing this type of 2143 * underruns should help hardware actually transmit new frames 2144 * successfully by eventually preferring slower rates. 2145 * This itself should also alleviate congestion on the bus. 2146 */ 2147 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN | 2148 ATH9K_TX_DELIM_UNDERRUN)) && 2149 ieee80211_is_data(hdr->frame_control) && 2150 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level) 2151 tx_info->status.rates[tx_rateindex].count = 2152 hw->max_rate_tries; 2153 } 2154 2155 for (i = tx_rateindex + 1; i < hw->max_rates; i++) { 2156 tx_info->status.rates[i].count = 0; 2157 tx_info->status.rates[i].idx = -1; 2158 } 2159 2160 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1; 2161 } 2162 2163 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq, 2164 struct ath_tx_status *ts, struct ath_buf *bf, 2165 struct list_head *bf_head) 2166 { 2167 int txok; 2168 2169 txq->axq_depth--; 2170 txok = !(ts->ts_status & ATH9K_TXERR_MASK); 2171 txq->axq_tx_inprogress = false; 2172 if (bf_is_ampdu_not_probing(bf)) 2173 txq->axq_ampdu_depth--; 2174 2175 if (!bf_isampdu(bf)) { 2176 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok); 2177 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok); 2178 } else 2179 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok, true); 2180 2181 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) 2182 ath_txq_schedule(sc, txq); 2183 } 2184 2185 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 2186 { 2187 struct ath_hw *ah = sc->sc_ah; 2188 struct ath_common *common = ath9k_hw_common(ah); 2189 struct ath_buf *bf, *lastbf, *bf_held = NULL; 2190 struct list_head bf_head; 2191 struct ath_desc *ds; 2192 struct ath_tx_status ts; 2193 int status; 2194 2195 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n", 2196 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), 2197 txq->axq_link); 2198 2199 ath_txq_lock(sc, txq); 2200 for (;;) { 2201 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) 2202 break; 2203 2204 if (list_empty(&txq->axq_q)) { 2205 txq->axq_link = NULL; 2206 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) 2207 ath_txq_schedule(sc, txq); 2208 break; 2209 } 2210 bf = list_first_entry(&txq->axq_q, struct ath_buf, list); 2211 2212 /* 2213 * There is a race condition that a BH gets scheduled 2214 * after sw writes TxE and before hw re-load the last 2215 * descriptor to get the newly chained one. 2216 * Software must keep the last DONE descriptor as a 2217 * holding descriptor - software does so by marking 2218 * it with the STALE flag. 2219 */ 2220 bf_held = NULL; 2221 if (bf->bf_stale) { 2222 bf_held = bf; 2223 if (list_is_last(&bf_held->list, &txq->axq_q)) 2224 break; 2225 2226 bf = list_entry(bf_held->list.next, struct ath_buf, 2227 list); 2228 } 2229 2230 lastbf = bf->bf_lastbf; 2231 ds = lastbf->bf_desc; 2232 2233 memset(&ts, 0, sizeof(ts)); 2234 status = ath9k_hw_txprocdesc(ah, ds, &ts); 2235 if (status == -EINPROGRESS) 2236 break; 2237 2238 TX_STAT_INC(txq->axq_qnum, txprocdesc); 2239 2240 /* 2241 * Remove ath_buf's of the same transmit unit from txq, 2242 * however leave the last descriptor back as the holding 2243 * descriptor for hw. 2244 */ 2245 lastbf->bf_stale = true; 2246 INIT_LIST_HEAD(&bf_head); 2247 if (!list_is_singular(&lastbf->list)) 2248 list_cut_position(&bf_head, 2249 &txq->axq_q, lastbf->list.prev); 2250 2251 if (bf_held) { 2252 list_del(&bf_held->list); 2253 ath_tx_return_buffer(sc, bf_held); 2254 } 2255 2256 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); 2257 } 2258 ath_txq_unlock_complete(sc, txq); 2259 } 2260 2261 void ath_tx_tasklet(struct ath_softc *sc) 2262 { 2263 struct ath_hw *ah = sc->sc_ah; 2264 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs; 2265 int i; 2266 2267 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 2268 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) 2269 ath_tx_processq(sc, &sc->tx.txq[i]); 2270 } 2271 } 2272 2273 void ath_tx_edma_tasklet(struct ath_softc *sc) 2274 { 2275 struct ath_tx_status ts; 2276 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2277 struct ath_hw *ah = sc->sc_ah; 2278 struct ath_txq *txq; 2279 struct ath_buf *bf, *lastbf; 2280 struct list_head bf_head; 2281 int status; 2282 2283 for (;;) { 2284 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) 2285 break; 2286 2287 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts); 2288 if (status == -EINPROGRESS) 2289 break; 2290 if (status == -EIO) { 2291 ath_dbg(common, XMIT, "Error processing tx status\n"); 2292 break; 2293 } 2294 2295 /* Process beacon completions separately */ 2296 if (ts.qid == sc->beacon.beaconq) { 2297 sc->beacon.tx_processed = true; 2298 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); 2299 continue; 2300 } 2301 2302 txq = &sc->tx.txq[ts.qid]; 2303 2304 ath_txq_lock(sc, txq); 2305 2306 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) { 2307 ath_txq_unlock(sc, txq); 2308 return; 2309 } 2310 2311 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx], 2312 struct ath_buf, list); 2313 lastbf = bf->bf_lastbf; 2314 2315 INIT_LIST_HEAD(&bf_head); 2316 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx], 2317 &lastbf->list); 2318 2319 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) { 2320 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH); 2321 2322 if (!list_empty(&txq->axq_q)) { 2323 struct list_head bf_q; 2324 2325 INIT_LIST_HEAD(&bf_q); 2326 txq->axq_link = NULL; 2327 list_splice_tail_init(&txq->axq_q, &bf_q); 2328 ath_tx_txqaddbuf(sc, txq, &bf_q, true); 2329 } 2330 } 2331 2332 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head); 2333 ath_txq_unlock_complete(sc, txq); 2334 } 2335 } 2336 2337 /*****************/ 2338 /* Init, Cleanup */ 2339 /*****************/ 2340 2341 static int ath_txstatus_setup(struct ath_softc *sc, int size) 2342 { 2343 struct ath_descdma *dd = &sc->txsdma; 2344 u8 txs_len = sc->sc_ah->caps.txs_len; 2345 2346 dd->dd_desc_len = size * txs_len; 2347 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len, 2348 &dd->dd_desc_paddr, GFP_KERNEL); 2349 if (!dd->dd_desc) 2350 return -ENOMEM; 2351 2352 return 0; 2353 } 2354 2355 static int ath_tx_edma_init(struct ath_softc *sc) 2356 { 2357 int err; 2358 2359 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE); 2360 if (!err) 2361 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc, 2362 sc->txsdma.dd_desc_paddr, 2363 ATH_TXSTATUS_RING_SIZE); 2364 2365 return err; 2366 } 2367 2368 static void ath_tx_edma_cleanup(struct ath_softc *sc) 2369 { 2370 struct ath_descdma *dd = &sc->txsdma; 2371 2372 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, 2373 dd->dd_desc_paddr); 2374 } 2375 2376 int ath_tx_init(struct ath_softc *sc, int nbufs) 2377 { 2378 struct ath_common *common = ath9k_hw_common(sc->sc_ah); 2379 int error = 0; 2380 2381 spin_lock_init(&sc->tx.txbuflock); 2382 2383 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, 2384 "tx", nbufs, 1, 1); 2385 if (error != 0) { 2386 ath_err(common, 2387 "Failed to allocate tx descriptors: %d\n", error); 2388 goto err; 2389 } 2390 2391 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, 2392 "beacon", ATH_BCBUF, 1, 1); 2393 if (error != 0) { 2394 ath_err(common, 2395 "Failed to allocate beacon descriptors: %d\n", error); 2396 goto err; 2397 } 2398 2399 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work); 2400 2401 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { 2402 error = ath_tx_edma_init(sc); 2403 if (error) 2404 goto err; 2405 } 2406 2407 err: 2408 if (error != 0) 2409 ath_tx_cleanup(sc); 2410 2411 return error; 2412 } 2413 2414 void ath_tx_cleanup(struct ath_softc *sc) 2415 { 2416 if (sc->beacon.bdma.dd_desc_len != 0) 2417 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf); 2418 2419 if (sc->tx.txdma.dd_desc_len != 0) 2420 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf); 2421 2422 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) 2423 ath_tx_edma_cleanup(sc); 2424 } 2425 2426 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) 2427 { 2428 struct ath_atx_tid *tid; 2429 struct ath_atx_ac *ac; 2430 int tidno, acno; 2431 2432 for (tidno = 0, tid = &an->tid[tidno]; 2433 tidno < WME_NUM_TID; 2434 tidno++, tid++) { 2435 tid->an = an; 2436 tid->tidno = tidno; 2437 tid->seq_start = tid->seq_next = 0; 2438 tid->baw_size = WME_MAX_BA; 2439 tid->baw_head = tid->baw_tail = 0; 2440 tid->sched = false; 2441 tid->paused = false; 2442 tid->state &= ~AGGR_CLEANUP; 2443 __skb_queue_head_init(&tid->buf_q); 2444 acno = TID_TO_WME_AC(tidno); 2445 tid->ac = &an->ac[acno]; 2446 tid->state &= ~AGGR_ADDBA_COMPLETE; 2447 tid->state &= ~AGGR_ADDBA_PROGRESS; 2448 } 2449 2450 for (acno = 0, ac = &an->ac[acno]; 2451 acno < WME_NUM_AC; acno++, ac++) { 2452 ac->sched = false; 2453 ac->txq = sc->tx.txq_map[acno]; 2454 INIT_LIST_HEAD(&ac->tid_q); 2455 } 2456 } 2457 2458 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) 2459 { 2460 struct ath_atx_ac *ac; 2461 struct ath_atx_tid *tid; 2462 struct ath_txq *txq; 2463 int tidno; 2464 2465 for (tidno = 0, tid = &an->tid[tidno]; 2466 tidno < WME_NUM_TID; tidno++, tid++) { 2467 2468 ac = tid->ac; 2469 txq = ac->txq; 2470 2471 ath_txq_lock(sc, txq); 2472 2473 if (tid->sched) { 2474 list_del(&tid->list); 2475 tid->sched = false; 2476 } 2477 2478 if (ac->sched) { 2479 list_del(&ac->list); 2480 tid->ac->sched = false; 2481 } 2482 2483 ath_tid_drain(sc, txq, tid); 2484 tid->state &= ~AGGR_ADDBA_COMPLETE; 2485 tid->state &= ~AGGR_CLEANUP; 2486 2487 ath_txq_unlock(sc, txq); 2488 } 2489 } 2490