1 /* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "ath9k.h" 18 19 #define BITS_PER_BYTE 8 20 #define OFDM_PLCP_BITS 22 21 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f) 22 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) 23 #define L_STF 8 24 #define L_LTF 8 25 #define L_SIG 4 26 #define HT_SIG 8 27 #define HT_STF 4 28 #define HT_LTF(_ns) (4 * (_ns)) 29 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ 30 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ 31 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) 32 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) 33 34 #define OFDM_SIFS_TIME 16 35 36 static u32 bits_per_symbol[][2] = { 37 /* 20MHz 40MHz */ 38 { 26, 54 }, /* 0: BPSK */ 39 { 52, 108 }, /* 1: QPSK 1/2 */ 40 { 78, 162 }, /* 2: QPSK 3/4 */ 41 { 104, 216 }, /* 3: 16-QAM 1/2 */ 42 { 156, 324 }, /* 4: 16-QAM 3/4 */ 43 { 208, 432 }, /* 5: 64-QAM 2/3 */ 44 { 234, 486 }, /* 6: 64-QAM 3/4 */ 45 { 260, 540 }, /* 7: 64-QAM 5/6 */ 46 { 52, 108 }, /* 8: BPSK */ 47 { 104, 216 }, /* 9: QPSK 1/2 */ 48 { 156, 324 }, /* 10: QPSK 3/4 */ 49 { 208, 432 }, /* 11: 16-QAM 1/2 */ 50 { 312, 648 }, /* 12: 16-QAM 3/4 */ 51 { 416, 864 }, /* 13: 64-QAM 2/3 */ 52 { 468, 972 }, /* 14: 64-QAM 3/4 */ 53 { 520, 1080 }, /* 15: 64-QAM 5/6 */ 54 }; 55 56 #define IS_HT_RATE(_rate) ((_rate) & 0x80) 57 58 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq, 59 struct ath_atx_tid *tid, 60 struct list_head *bf_head); 61 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 62 struct list_head *bf_q, 63 int txok, int sendbar); 64 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 65 struct list_head *head); 66 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf); 67 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf, 68 int txok); 69 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds, 70 int nbad, int txok, bool update_rc); 71 72 /*********************/ 73 /* Aggregation logic */ 74 /*********************/ 75 76 static int ath_aggr_query(struct ath_softc *sc, struct ath_node *an, u8 tidno) 77 { 78 struct ath_atx_tid *tid; 79 tid = ATH_AN_2_TID(an, tidno); 80 81 if (tid->state & AGGR_ADDBA_COMPLETE || 82 tid->state & AGGR_ADDBA_PROGRESS) 83 return 1; 84 else 85 return 0; 86 } 87 88 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid) 89 { 90 struct ath_atx_ac *ac = tid->ac; 91 92 if (tid->paused) 93 return; 94 95 if (tid->sched) 96 return; 97 98 tid->sched = true; 99 list_add_tail(&tid->list, &ac->tid_q); 100 101 if (ac->sched) 102 return; 103 104 ac->sched = true; 105 list_add_tail(&ac->list, &txq->axq_acq); 106 } 107 108 static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 109 { 110 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; 111 112 spin_lock_bh(&txq->axq_lock); 113 tid->paused++; 114 spin_unlock_bh(&txq->axq_lock); 115 } 116 117 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 118 { 119 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; 120 121 ASSERT(tid->paused > 0); 122 spin_lock_bh(&txq->axq_lock); 123 124 tid->paused--; 125 126 if (tid->paused > 0) 127 goto unlock; 128 129 if (list_empty(&tid->buf_q)) 130 goto unlock; 131 132 ath_tx_queue_tid(txq, tid); 133 ath_txq_schedule(sc, txq); 134 unlock: 135 spin_unlock_bh(&txq->axq_lock); 136 } 137 138 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) 139 { 140 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; 141 struct ath_buf *bf; 142 struct list_head bf_head; 143 INIT_LIST_HEAD(&bf_head); 144 145 ASSERT(tid->paused > 0); 146 spin_lock_bh(&txq->axq_lock); 147 148 tid->paused--; 149 150 if (tid->paused > 0) { 151 spin_unlock_bh(&txq->axq_lock); 152 return; 153 } 154 155 while (!list_empty(&tid->buf_q)) { 156 bf = list_first_entry(&tid->buf_q, struct ath_buf, list); 157 ASSERT(!bf_isretried(bf)); 158 list_move_tail(&bf->list, &bf_head); 159 ath_tx_send_ht_normal(sc, txq, tid, &bf_head); 160 } 161 162 spin_unlock_bh(&txq->axq_lock); 163 } 164 165 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 166 int seqno) 167 { 168 int index, cindex; 169 170 index = ATH_BA_INDEX(tid->seq_start, seqno); 171 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 172 173 tid->tx_buf[cindex] = NULL; 174 175 while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) { 176 INCR(tid->seq_start, IEEE80211_SEQ_MAX); 177 INCR(tid->baw_head, ATH_TID_MAX_BUFS); 178 } 179 } 180 181 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid, 182 struct ath_buf *bf) 183 { 184 int index, cindex; 185 186 if (bf_isretried(bf)) 187 return; 188 189 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno); 190 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); 191 192 ASSERT(tid->tx_buf[cindex] == NULL); 193 tid->tx_buf[cindex] = bf; 194 195 if (index >= ((tid->baw_tail - tid->baw_head) & 196 (ATH_TID_MAX_BUFS - 1))) { 197 tid->baw_tail = cindex; 198 INCR(tid->baw_tail, ATH_TID_MAX_BUFS); 199 } 200 } 201 202 /* 203 * TODO: For frame(s) that are in the retry state, we will reuse the 204 * sequence number(s) without setting the retry bit. The 205 * alternative is to give up on these and BAR the receiver's window 206 * forward. 207 */ 208 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq, 209 struct ath_atx_tid *tid) 210 211 { 212 struct ath_buf *bf; 213 struct list_head bf_head; 214 INIT_LIST_HEAD(&bf_head); 215 216 for (;;) { 217 if (list_empty(&tid->buf_q)) 218 break; 219 220 bf = list_first_entry(&tid->buf_q, struct ath_buf, list); 221 list_move_tail(&bf->list, &bf_head); 222 223 if (bf_isretried(bf)) 224 ath_tx_update_baw(sc, tid, bf->bf_seqno); 225 226 spin_unlock(&txq->axq_lock); 227 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0); 228 spin_lock(&txq->axq_lock); 229 } 230 231 tid->seq_next = tid->seq_start; 232 tid->baw_tail = tid->baw_head; 233 } 234 235 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf) 236 { 237 struct sk_buff *skb; 238 struct ieee80211_hdr *hdr; 239 240 bf->bf_state.bf_type |= BUF_RETRY; 241 bf->bf_retries++; 242 243 skb = bf->bf_mpdu; 244 hdr = (struct ieee80211_hdr *)skb->data; 245 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); 246 } 247 248 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf) 249 { 250 struct ath_buf *tbf; 251 252 spin_lock_bh(&sc->tx.txbuflock); 253 ASSERT(!list_empty((&sc->tx.txbuf))); 254 tbf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); 255 list_del(&tbf->list); 256 spin_unlock_bh(&sc->tx.txbuflock); 257 258 ATH_TXBUF_RESET(tbf); 259 260 tbf->bf_mpdu = bf->bf_mpdu; 261 tbf->bf_buf_addr = bf->bf_buf_addr; 262 *(tbf->bf_desc) = *(bf->bf_desc); 263 tbf->bf_state = bf->bf_state; 264 tbf->bf_dmacontext = bf->bf_dmacontext; 265 266 return tbf; 267 } 268 269 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, 270 struct ath_buf *bf, struct list_head *bf_q, 271 int txok) 272 { 273 struct ath_node *an = NULL; 274 struct sk_buff *skb; 275 struct ieee80211_sta *sta; 276 struct ieee80211_hdr *hdr; 277 struct ath_atx_tid *tid = NULL; 278 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; 279 struct ath_desc *ds = bf_last->bf_desc; 280 struct list_head bf_head, bf_pending; 281 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0; 282 u32 ba[WME_BA_BMP_SIZE >> 5]; 283 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0; 284 bool rc_update = true; 285 286 skb = bf->bf_mpdu; 287 hdr = (struct ieee80211_hdr *)skb->data; 288 289 rcu_read_lock(); 290 291 sta = ieee80211_find_sta(sc->hw, hdr->addr1); 292 if (!sta) { 293 rcu_read_unlock(); 294 return; 295 } 296 297 an = (struct ath_node *)sta->drv_priv; 298 tid = ATH_AN_2_TID(an, bf->bf_tidno); 299 300 isaggr = bf_isaggr(bf); 301 memset(ba, 0, WME_BA_BMP_SIZE >> 3); 302 303 if (isaggr && txok) { 304 if (ATH_DS_TX_BA(ds)) { 305 seq_st = ATH_DS_BA_SEQ(ds); 306 memcpy(ba, ATH_DS_BA_BITMAP(ds), 307 WME_BA_BMP_SIZE >> 3); 308 } else { 309 /* 310 * AR5416 can become deaf/mute when BA 311 * issue happens. Chip needs to be reset. 312 * But AP code may have sychronization issues 313 * when perform internal reset in this routine. 314 * Only enable reset in STA mode for now. 315 */ 316 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) 317 needreset = 1; 318 } 319 } 320 321 INIT_LIST_HEAD(&bf_pending); 322 INIT_LIST_HEAD(&bf_head); 323 324 nbad = ath_tx_num_badfrms(sc, bf, txok); 325 while (bf) { 326 txfail = txpending = 0; 327 bf_next = bf->bf_next; 328 329 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) { 330 /* transmit completion, subframe is 331 * acked by block ack */ 332 acked_cnt++; 333 } else if (!isaggr && txok) { 334 /* transmit completion */ 335 acked_cnt++; 336 } else { 337 if (!(tid->state & AGGR_CLEANUP) && 338 ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) { 339 if (bf->bf_retries < ATH_MAX_SW_RETRIES) { 340 ath_tx_set_retry(sc, bf); 341 txpending = 1; 342 } else { 343 bf->bf_state.bf_type |= BUF_XRETRY; 344 txfail = 1; 345 sendbar = 1; 346 txfail_cnt++; 347 } 348 } else { 349 /* 350 * cleanup in progress, just fail 351 * the un-acked sub-frames 352 */ 353 txfail = 1; 354 } 355 } 356 357 if (bf_next == NULL) { 358 /* 359 * Make sure the last desc is reclaimed if it 360 * not a holding desc. 361 */ 362 if (!bf_last->bf_stale) 363 list_move_tail(&bf->list, &bf_head); 364 else 365 INIT_LIST_HEAD(&bf_head); 366 } else { 367 ASSERT(!list_empty(bf_q)); 368 list_move_tail(&bf->list, &bf_head); 369 } 370 371 if (!txpending) { 372 /* 373 * complete the acked-ones/xretried ones; update 374 * block-ack window 375 */ 376 spin_lock_bh(&txq->axq_lock); 377 ath_tx_update_baw(sc, tid, bf->bf_seqno); 378 spin_unlock_bh(&txq->axq_lock); 379 380 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) { 381 ath_tx_rc_status(bf, ds, nbad, txok, true); 382 rc_update = false; 383 } else { 384 ath_tx_rc_status(bf, ds, nbad, txok, false); 385 } 386 387 ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar); 388 } else { 389 /* retry the un-acked ones */ 390 if (bf->bf_next == NULL && bf_last->bf_stale) { 391 struct ath_buf *tbf; 392 393 tbf = ath_clone_txbuf(sc, bf_last); 394 ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc); 395 list_add_tail(&tbf->list, &bf_head); 396 } else { 397 /* 398 * Clear descriptor status words for 399 * software retry 400 */ 401 ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc); 402 } 403 404 /* 405 * Put this buffer to the temporary pending 406 * queue to retain ordering 407 */ 408 list_splice_tail_init(&bf_head, &bf_pending); 409 } 410 411 bf = bf_next; 412 } 413 414 if (tid->state & AGGR_CLEANUP) { 415 if (tid->baw_head == tid->baw_tail) { 416 tid->state &= ~AGGR_ADDBA_COMPLETE; 417 tid->addba_exchangeattempts = 0; 418 tid->state &= ~AGGR_CLEANUP; 419 420 /* send buffered frames as singles */ 421 ath_tx_flush_tid(sc, tid); 422 } 423 rcu_read_unlock(); 424 return; 425 } 426 427 /* prepend un-acked frames to the beginning of the pending frame queue */ 428 if (!list_empty(&bf_pending)) { 429 spin_lock_bh(&txq->axq_lock); 430 list_splice(&bf_pending, &tid->buf_q); 431 ath_tx_queue_tid(txq, tid); 432 spin_unlock_bh(&txq->axq_lock); 433 } 434 435 rcu_read_unlock(); 436 437 if (needreset) 438 ath_reset(sc, false); 439 } 440 441 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, 442 struct ath_atx_tid *tid) 443 { 444 const struct ath_rate_table *rate_table = sc->cur_rate_table; 445 struct sk_buff *skb; 446 struct ieee80211_tx_info *tx_info; 447 struct ieee80211_tx_rate *rates; 448 struct ath_tx_info_priv *tx_info_priv; 449 u32 max_4ms_framelen, frmlen; 450 u16 aggr_limit, legacy = 0, maxampdu; 451 int i; 452 453 skb = bf->bf_mpdu; 454 tx_info = IEEE80211_SKB_CB(skb); 455 rates = tx_info->control.rates; 456 tx_info_priv = (struct ath_tx_info_priv *)tx_info->rate_driver_data[0]; 457 458 /* 459 * Find the lowest frame length among the rate series that will have a 460 * 4ms transmit duration. 461 * TODO - TXOP limit needs to be considered. 462 */ 463 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; 464 465 for (i = 0; i < 4; i++) { 466 if (rates[i].count) { 467 if (!WLAN_RC_PHY_HT(rate_table->info[rates[i].idx].phy)) { 468 legacy = 1; 469 break; 470 } 471 472 frmlen = rate_table->info[rates[i].idx].max_4ms_framelen; 473 max_4ms_framelen = min(max_4ms_framelen, frmlen); 474 } 475 } 476 477 /* 478 * limit aggregate size by the minimum rate if rate selected is 479 * not a probe rate, if rate selected is a probe rate then 480 * avoid aggregation of this packet. 481 */ 482 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) 483 return 0; 484 485 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_DEFAULT); 486 487 /* 488 * h/w can accept aggregates upto 16 bit lengths (65535). 489 * The IE, however can hold upto 65536, which shows up here 490 * as zero. Ignore 65536 since we are constrained by hw. 491 */ 492 maxampdu = tid->an->maxampdu; 493 if (maxampdu) 494 aggr_limit = min(aggr_limit, maxampdu); 495 496 return aggr_limit; 497 } 498 499 /* 500 * Returns the number of delimiters to be added to 501 * meet the minimum required mpdudensity. 502 * caller should make sure that the rate is HT rate . 503 */ 504 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, 505 struct ath_buf *bf, u16 frmlen) 506 { 507 const struct ath_rate_table *rt = sc->cur_rate_table; 508 struct sk_buff *skb = bf->bf_mpdu; 509 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 510 u32 nsymbits, nsymbols, mpdudensity; 511 u16 minlen; 512 u8 rc, flags, rix; 513 int width, half_gi, ndelim, mindelim; 514 515 /* Select standard number of delimiters based on frame length alone */ 516 ndelim = ATH_AGGR_GET_NDELIM(frmlen); 517 518 /* 519 * If encryption enabled, hardware requires some more padding between 520 * subframes. 521 * TODO - this could be improved to be dependent on the rate. 522 * The hardware can keep up at lower rates, but not higher rates 523 */ 524 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) 525 ndelim += ATH_AGGR_ENCRYPTDELIM; 526 527 /* 528 * Convert desired mpdu density from microeconds to bytes based 529 * on highest rate in rate series (i.e. first rate) to determine 530 * required minimum length for subframe. Take into account 531 * whether high rate is 20 or 40Mhz and half or full GI. 532 */ 533 mpdudensity = tid->an->mpdudensity; 534 535 /* 536 * If there is no mpdu density restriction, no further calculation 537 * is needed. 538 */ 539 if (mpdudensity == 0) 540 return ndelim; 541 542 rix = tx_info->control.rates[0].idx; 543 flags = tx_info->control.rates[0].flags; 544 rc = rt->info[rix].ratecode; 545 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; 546 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; 547 548 if (half_gi) 549 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity); 550 else 551 nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity); 552 553 if (nsymbols == 0) 554 nsymbols = 1; 555 556 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; 557 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; 558 559 if (frmlen < minlen) { 560 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; 561 ndelim = max(mindelim, ndelim); 562 } 563 564 return ndelim; 565 } 566 567 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, 568 struct ath_atx_tid *tid, 569 struct list_head *bf_q) 570 { 571 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) 572 struct ath_buf *bf, *bf_first, *bf_prev = NULL; 573 int rl = 0, nframes = 0, ndelim, prev_al = 0; 574 u16 aggr_limit = 0, al = 0, bpad = 0, 575 al_delta, h_baw = tid->baw_size / 2; 576 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE; 577 578 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list); 579 580 do { 581 bf = list_first_entry(&tid->buf_q, struct ath_buf, list); 582 583 /* do not step over block-ack window */ 584 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) { 585 status = ATH_AGGR_BAW_CLOSED; 586 break; 587 } 588 589 if (!rl) { 590 aggr_limit = ath_lookup_rate(sc, bf, tid); 591 rl = 1; 592 } 593 594 /* do not exceed aggregation limit */ 595 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen; 596 597 if (nframes && 598 (aggr_limit < (al + bpad + al_delta + prev_al))) { 599 status = ATH_AGGR_LIMITED; 600 break; 601 } 602 603 /* do not exceed subframe limit */ 604 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) { 605 status = ATH_AGGR_LIMITED; 606 break; 607 } 608 nframes++; 609 610 /* add padding for previous frame to aggregation length */ 611 al += bpad + al_delta; 612 613 /* 614 * Get the delimiters needed to meet the MPDU 615 * density for this node. 616 */ 617 ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen); 618 bpad = PADBYTES(al_delta) + (ndelim << 2); 619 620 bf->bf_next = NULL; 621 bf->bf_desc->ds_link = 0; 622 623 /* link buffers of this frame to the aggregate */ 624 ath_tx_addto_baw(sc, tid, bf); 625 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim); 626 list_move_tail(&bf->list, bf_q); 627 if (bf_prev) { 628 bf_prev->bf_next = bf; 629 bf_prev->bf_desc->ds_link = bf->bf_daddr; 630 } 631 bf_prev = bf; 632 } while (!list_empty(&tid->buf_q)); 633 634 bf_first->bf_al = al; 635 bf_first->bf_nframes = nframes; 636 637 return status; 638 #undef PADBYTES 639 } 640 641 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, 642 struct ath_atx_tid *tid) 643 { 644 struct ath_buf *bf; 645 enum ATH_AGGR_STATUS status; 646 struct list_head bf_q; 647 648 do { 649 if (list_empty(&tid->buf_q)) 650 return; 651 652 INIT_LIST_HEAD(&bf_q); 653 654 status = ath_tx_form_aggr(sc, tid, &bf_q); 655 656 /* 657 * no frames picked up to be aggregated; 658 * block-ack window is not open. 659 */ 660 if (list_empty(&bf_q)) 661 break; 662 663 bf = list_first_entry(&bf_q, struct ath_buf, list); 664 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list); 665 666 /* if only one frame, send as non-aggregate */ 667 if (bf->bf_nframes == 1) { 668 bf->bf_state.bf_type &= ~BUF_AGGR; 669 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc); 670 ath_buf_set_rate(sc, bf); 671 ath_tx_txqaddbuf(sc, txq, &bf_q); 672 continue; 673 } 674 675 /* setup first desc of aggregate */ 676 bf->bf_state.bf_type |= BUF_AGGR; 677 ath_buf_set_rate(sc, bf); 678 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al); 679 680 /* anchor last desc of aggregate */ 681 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc); 682 683 txq->axq_aggr_depth++; 684 ath_tx_txqaddbuf(sc, txq, &bf_q); 685 686 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH && 687 status != ATH_AGGR_BAW_CLOSED); 688 } 689 690 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, 691 u16 tid, u16 *ssn) 692 { 693 struct ath_atx_tid *txtid; 694 struct ath_node *an; 695 696 an = (struct ath_node *)sta->drv_priv; 697 698 if (sc->sc_flags & SC_OP_TXAGGR) { 699 txtid = ATH_AN_2_TID(an, tid); 700 txtid->state |= AGGR_ADDBA_PROGRESS; 701 ath_tx_pause_tid(sc, txtid); 702 *ssn = txtid->seq_start; 703 } 704 705 return 0; 706 } 707 708 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) 709 { 710 struct ath_node *an = (struct ath_node *)sta->drv_priv; 711 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); 712 struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum]; 713 struct ath_buf *bf; 714 struct list_head bf_head; 715 INIT_LIST_HEAD(&bf_head); 716 717 if (txtid->state & AGGR_CLEANUP) 718 return 0; 719 720 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) { 721 txtid->state &= ~AGGR_ADDBA_PROGRESS; 722 txtid->addba_exchangeattempts = 0; 723 return 0; 724 } 725 726 ath_tx_pause_tid(sc, txtid); 727 728 /* drop all software retried frames and mark this TID */ 729 spin_lock_bh(&txq->axq_lock); 730 while (!list_empty(&txtid->buf_q)) { 731 bf = list_first_entry(&txtid->buf_q, struct ath_buf, list); 732 if (!bf_isretried(bf)) { 733 /* 734 * NB: it's based on the assumption that 735 * software retried frame will always stay 736 * at the head of software queue. 737 */ 738 break; 739 } 740 list_move_tail(&bf->list, &bf_head); 741 ath_tx_update_baw(sc, txtid, bf->bf_seqno); 742 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0); 743 } 744 spin_unlock_bh(&txq->axq_lock); 745 746 if (txtid->baw_head != txtid->baw_tail) { 747 txtid->state |= AGGR_CLEANUP; 748 } else { 749 txtid->state &= ~AGGR_ADDBA_COMPLETE; 750 txtid->addba_exchangeattempts = 0; 751 ath_tx_flush_tid(sc, txtid); 752 } 753 754 return 0; 755 } 756 757 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) 758 { 759 struct ath_atx_tid *txtid; 760 struct ath_node *an; 761 762 an = (struct ath_node *)sta->drv_priv; 763 764 if (sc->sc_flags & SC_OP_TXAGGR) { 765 txtid = ATH_AN_2_TID(an, tid); 766 txtid->baw_size = 767 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor; 768 txtid->state |= AGGR_ADDBA_COMPLETE; 769 txtid->state &= ~AGGR_ADDBA_PROGRESS; 770 ath_tx_resume_tid(sc, txtid); 771 } 772 } 773 774 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno) 775 { 776 struct ath_atx_tid *txtid; 777 778 if (!(sc->sc_flags & SC_OP_TXAGGR)) 779 return false; 780 781 txtid = ATH_AN_2_TID(an, tidno); 782 783 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) { 784 if (!(txtid->state & AGGR_ADDBA_PROGRESS) && 785 (txtid->addba_exchangeattempts < ADDBA_EXCHANGE_ATTEMPTS)) { 786 txtid->addba_exchangeattempts++; 787 return true; 788 } 789 } 790 791 return false; 792 } 793 794 /********************/ 795 /* Queue Management */ 796 /********************/ 797 798 static void ath_txq_drain_pending_buffers(struct ath_softc *sc, 799 struct ath_txq *txq) 800 { 801 struct ath_atx_ac *ac, *ac_tmp; 802 struct ath_atx_tid *tid, *tid_tmp; 803 804 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) { 805 list_del(&ac->list); 806 ac->sched = false; 807 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) { 808 list_del(&tid->list); 809 tid->sched = false; 810 ath_tid_drain(sc, txq, tid); 811 } 812 } 813 } 814 815 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 816 { 817 struct ath_hw *ah = sc->sc_ah; 818 struct ath9k_tx_queue_info qi; 819 int qnum; 820 821 memset(&qi, 0, sizeof(qi)); 822 qi.tqi_subtype = subtype; 823 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; 824 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; 825 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; 826 qi.tqi_physCompBuf = 0; 827 828 /* 829 * Enable interrupts only for EOL and DESC conditions. 830 * We mark tx descriptors to receive a DESC interrupt 831 * when a tx queue gets deep; otherwise waiting for the 832 * EOL to reap descriptors. Note that this is done to 833 * reduce interrupt load and this only defers reaping 834 * descriptors, never transmitting frames. Aside from 835 * reducing interrupts this also permits more concurrency. 836 * The only potential downside is if the tx queue backs 837 * up in which case the top half of the kernel may backup 838 * due to a lack of tx descriptors. 839 * 840 * The UAPSD queue is an exception, since we take a desc- 841 * based intr on the EOSP frames. 842 */ 843 if (qtype == ATH9K_TX_QUEUE_UAPSD) 844 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; 845 else 846 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | 847 TXQ_FLAG_TXDESCINT_ENABLE; 848 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); 849 if (qnum == -1) { 850 /* 851 * NB: don't print a message, this happens 852 * normally on parts with too few tx queues 853 */ 854 return NULL; 855 } 856 if (qnum >= ARRAY_SIZE(sc->tx.txq)) { 857 DPRINTF(sc, ATH_DBG_FATAL, 858 "qnum %u out of range, max %u!\n", 859 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq)); 860 ath9k_hw_releasetxqueue(ah, qnum); 861 return NULL; 862 } 863 if (!ATH_TXQ_SETUP(sc, qnum)) { 864 struct ath_txq *txq = &sc->tx.txq[qnum]; 865 866 txq->axq_qnum = qnum; 867 txq->axq_link = NULL; 868 INIT_LIST_HEAD(&txq->axq_q); 869 INIT_LIST_HEAD(&txq->axq_acq); 870 spin_lock_init(&txq->axq_lock); 871 txq->axq_depth = 0; 872 txq->axq_aggr_depth = 0; 873 txq->axq_totalqueued = 0; 874 txq->axq_linkbuf = NULL; 875 sc->tx.txqsetup |= 1<<qnum; 876 } 877 return &sc->tx.txq[qnum]; 878 } 879 880 static int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype) 881 { 882 int qnum; 883 884 switch (qtype) { 885 case ATH9K_TX_QUEUE_DATA: 886 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { 887 DPRINTF(sc, ATH_DBG_FATAL, 888 "HAL AC %u out of range, max %zu!\n", 889 haltype, ARRAY_SIZE(sc->tx.hwq_map)); 890 return -1; 891 } 892 qnum = sc->tx.hwq_map[haltype]; 893 break; 894 case ATH9K_TX_QUEUE_BEACON: 895 qnum = sc->beacon.beaconq; 896 break; 897 case ATH9K_TX_QUEUE_CAB: 898 qnum = sc->beacon.cabq->axq_qnum; 899 break; 900 default: 901 qnum = -1; 902 } 903 return qnum; 904 } 905 906 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb) 907 { 908 struct ath_txq *txq = NULL; 909 int qnum; 910 911 qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc); 912 txq = &sc->tx.txq[qnum]; 913 914 spin_lock_bh(&txq->axq_lock); 915 916 if (txq->axq_depth >= (ATH_TXBUF - 20)) { 917 DPRINTF(sc, ATH_DBG_XMIT, 918 "TX queue: %d is full, depth: %d\n", 919 qnum, txq->axq_depth); 920 ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb)); 921 txq->stopped = 1; 922 spin_unlock_bh(&txq->axq_lock); 923 return NULL; 924 } 925 926 spin_unlock_bh(&txq->axq_lock); 927 928 return txq; 929 } 930 931 int ath_txq_update(struct ath_softc *sc, int qnum, 932 struct ath9k_tx_queue_info *qinfo) 933 { 934 struct ath_hw *ah = sc->sc_ah; 935 int error = 0; 936 struct ath9k_tx_queue_info qi; 937 938 if (qnum == sc->beacon.beaconq) { 939 /* 940 * XXX: for beacon queue, we just save the parameter. 941 * It will be picked up by ath_beaconq_config when 942 * it's necessary. 943 */ 944 sc->beacon.beacon_qi = *qinfo; 945 return 0; 946 } 947 948 ASSERT(sc->tx.txq[qnum].axq_qnum == qnum); 949 950 ath9k_hw_get_txq_props(ah, qnum, &qi); 951 qi.tqi_aifs = qinfo->tqi_aifs; 952 qi.tqi_cwmin = qinfo->tqi_cwmin; 953 qi.tqi_cwmax = qinfo->tqi_cwmax; 954 qi.tqi_burstTime = qinfo->tqi_burstTime; 955 qi.tqi_readyTime = qinfo->tqi_readyTime; 956 957 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { 958 DPRINTF(sc, ATH_DBG_FATAL, 959 "Unable to update hardware queue %u!\n", qnum); 960 error = -EIO; 961 } else { 962 ath9k_hw_resettxqueue(ah, qnum); 963 } 964 965 return error; 966 } 967 968 int ath_cabq_update(struct ath_softc *sc) 969 { 970 struct ath9k_tx_queue_info qi; 971 int qnum = sc->beacon.cabq->axq_qnum; 972 973 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); 974 /* 975 * Ensure the readytime % is within the bounds. 976 */ 977 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND) 978 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND; 979 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND) 980 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND; 981 982 qi.tqi_readyTime = (sc->beacon_interval * 983 sc->config.cabqReadytime) / 100; 984 ath_txq_update(sc, qnum, &qi); 985 986 return 0; 987 } 988 989 /* 990 * Drain a given TX queue (could be Beacon or Data) 991 * 992 * This assumes output has been stopped and 993 * we do not need to block ath_tx_tasklet. 994 */ 995 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx) 996 { 997 struct ath_buf *bf, *lastbf; 998 struct list_head bf_head; 999 1000 INIT_LIST_HEAD(&bf_head); 1001 1002 for (;;) { 1003 spin_lock_bh(&txq->axq_lock); 1004 1005 if (list_empty(&txq->axq_q)) { 1006 txq->axq_link = NULL; 1007 txq->axq_linkbuf = NULL; 1008 spin_unlock_bh(&txq->axq_lock); 1009 break; 1010 } 1011 1012 bf = list_first_entry(&txq->axq_q, struct ath_buf, list); 1013 1014 if (bf->bf_stale) { 1015 list_del(&bf->list); 1016 spin_unlock_bh(&txq->axq_lock); 1017 1018 spin_lock_bh(&sc->tx.txbuflock); 1019 list_add_tail(&bf->list, &sc->tx.txbuf); 1020 spin_unlock_bh(&sc->tx.txbuflock); 1021 continue; 1022 } 1023 1024 lastbf = bf->bf_lastbf; 1025 if (!retry_tx) 1026 lastbf->bf_desc->ds_txstat.ts_flags = 1027 ATH9K_TX_SW_ABORTED; 1028 1029 /* remove ath_buf's of the same mpdu from txq */ 1030 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list); 1031 txq->axq_depth--; 1032 1033 spin_unlock_bh(&txq->axq_lock); 1034 1035 if (bf_isampdu(bf)) 1036 ath_tx_complete_aggr(sc, txq, bf, &bf_head, 0); 1037 else 1038 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0); 1039 } 1040 1041 /* flush any pending frames if aggregation is enabled */ 1042 if (sc->sc_flags & SC_OP_TXAGGR) { 1043 if (!retry_tx) { 1044 spin_lock_bh(&txq->axq_lock); 1045 ath_txq_drain_pending_buffers(sc, txq); 1046 spin_unlock_bh(&txq->axq_lock); 1047 } 1048 } 1049 } 1050 1051 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) 1052 { 1053 struct ath_hw *ah = sc->sc_ah; 1054 struct ath_txq *txq; 1055 int i, npend = 0; 1056 1057 if (sc->sc_flags & SC_OP_INVALID) 1058 return; 1059 1060 /* Stop beacon queue */ 1061 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); 1062 1063 /* Stop data queues */ 1064 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1065 if (ATH_TXQ_SETUP(sc, i)) { 1066 txq = &sc->tx.txq[i]; 1067 ath9k_hw_stoptxdma(ah, txq->axq_qnum); 1068 npend += ath9k_hw_numtxpending(ah, txq->axq_qnum); 1069 } 1070 } 1071 1072 if (npend) { 1073 int r; 1074 1075 DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n"); 1076 1077 spin_lock_bh(&sc->sc_resetlock); 1078 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true); 1079 if (r) 1080 DPRINTF(sc, ATH_DBG_FATAL, 1081 "Unable to reset hardware; reset status %d\n", 1082 r); 1083 spin_unlock_bh(&sc->sc_resetlock); 1084 } 1085 1086 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 1087 if (ATH_TXQ_SETUP(sc, i)) 1088 ath_draintxq(sc, &sc->tx.txq[i], retry_tx); 1089 } 1090 } 1091 1092 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 1093 { 1094 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); 1095 sc->tx.txqsetup &= ~(1<<txq->axq_qnum); 1096 } 1097 1098 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) 1099 { 1100 struct ath_atx_ac *ac; 1101 struct ath_atx_tid *tid; 1102 1103 if (list_empty(&txq->axq_acq)) 1104 return; 1105 1106 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list); 1107 list_del(&ac->list); 1108 ac->sched = false; 1109 1110 do { 1111 if (list_empty(&ac->tid_q)) 1112 return; 1113 1114 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list); 1115 list_del(&tid->list); 1116 tid->sched = false; 1117 1118 if (tid->paused) 1119 continue; 1120 1121 if ((txq->axq_depth % 2) == 0) 1122 ath_tx_sched_aggr(sc, txq, tid); 1123 1124 /* 1125 * add tid to round-robin queue if more frames 1126 * are pending for the tid 1127 */ 1128 if (!list_empty(&tid->buf_q)) 1129 ath_tx_queue_tid(txq, tid); 1130 1131 break; 1132 } while (!list_empty(&ac->tid_q)); 1133 1134 if (!list_empty(&ac->tid_q)) { 1135 if (!ac->sched) { 1136 ac->sched = true; 1137 list_add_tail(&ac->list, &txq->axq_acq); 1138 } 1139 } 1140 } 1141 1142 int ath_tx_setup(struct ath_softc *sc, int haltype) 1143 { 1144 struct ath_txq *txq; 1145 1146 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { 1147 DPRINTF(sc, ATH_DBG_FATAL, 1148 "HAL AC %u out of range, max %zu!\n", 1149 haltype, ARRAY_SIZE(sc->tx.hwq_map)); 1150 return 0; 1151 } 1152 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype); 1153 if (txq != NULL) { 1154 sc->tx.hwq_map[haltype] = txq->axq_qnum; 1155 return 1; 1156 } else 1157 return 0; 1158 } 1159 1160 /***********/ 1161 /* TX, DMA */ 1162 /***********/ 1163 1164 /* 1165 * Insert a chain of ath_buf (descriptors) on a txq and 1166 * assume the descriptors are already chained together by caller. 1167 */ 1168 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, 1169 struct list_head *head) 1170 { 1171 struct ath_hw *ah = sc->sc_ah; 1172 struct ath_buf *bf; 1173 1174 /* 1175 * Insert the frame on the outbound list and 1176 * pass it on to the hardware. 1177 */ 1178 1179 if (list_empty(head)) 1180 return; 1181 1182 bf = list_first_entry(head, struct ath_buf, list); 1183 1184 list_splice_tail_init(head, &txq->axq_q); 1185 txq->axq_depth++; 1186 txq->axq_totalqueued++; 1187 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list); 1188 1189 DPRINTF(sc, ATH_DBG_QUEUE, 1190 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth); 1191 1192 if (txq->axq_link == NULL) { 1193 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 1194 DPRINTF(sc, ATH_DBG_XMIT, 1195 "TXDP[%u] = %llx (%p)\n", 1196 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); 1197 } else { 1198 *txq->axq_link = bf->bf_daddr; 1199 DPRINTF(sc, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n", 1200 txq->axq_qnum, txq->axq_link, 1201 ito64(bf->bf_daddr), bf->bf_desc); 1202 } 1203 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link); 1204 ath9k_hw_txstart(ah, txq->axq_qnum); 1205 } 1206 1207 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) 1208 { 1209 struct ath_buf *bf = NULL; 1210 1211 spin_lock_bh(&sc->tx.txbuflock); 1212 1213 if (unlikely(list_empty(&sc->tx.txbuf))) { 1214 spin_unlock_bh(&sc->tx.txbuflock); 1215 return NULL; 1216 } 1217 1218 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); 1219 list_del(&bf->list); 1220 1221 spin_unlock_bh(&sc->tx.txbuflock); 1222 1223 return bf; 1224 } 1225 1226 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid, 1227 struct list_head *bf_head, 1228 struct ath_tx_control *txctl) 1229 { 1230 struct ath_buf *bf; 1231 1232 bf = list_first_entry(bf_head, struct ath_buf, list); 1233 bf->bf_state.bf_type |= BUF_AMPDU; 1234 1235 /* 1236 * Do not queue to h/w when any of the following conditions is true: 1237 * - there are pending frames in software queue 1238 * - the TID is currently paused for ADDBA/BAR request 1239 * - seqno is not within block-ack window 1240 * - h/w queue depth exceeds low water mark 1241 */ 1242 if (!list_empty(&tid->buf_q) || tid->paused || 1243 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) || 1244 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) { 1245 /* 1246 * Add this frame to software queue for scheduling later 1247 * for aggregation. 1248 */ 1249 list_move_tail(&bf->list, &tid->buf_q); 1250 ath_tx_queue_tid(txctl->txq, tid); 1251 return; 1252 } 1253 1254 /* Add sub-frame to BAW */ 1255 ath_tx_addto_baw(sc, tid, bf); 1256 1257 /* Queue to h/w without aggregation */ 1258 bf->bf_nframes = 1; 1259 bf->bf_lastbf = bf; 1260 ath_buf_set_rate(sc, bf); 1261 ath_tx_txqaddbuf(sc, txctl->txq, bf_head); 1262 } 1263 1264 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq, 1265 struct ath_atx_tid *tid, 1266 struct list_head *bf_head) 1267 { 1268 struct ath_buf *bf; 1269 1270 bf = list_first_entry(bf_head, struct ath_buf, list); 1271 bf->bf_state.bf_type &= ~BUF_AMPDU; 1272 1273 /* update starting sequence number for subsequent ADDBA request */ 1274 INCR(tid->seq_start, IEEE80211_SEQ_MAX); 1275 1276 bf->bf_nframes = 1; 1277 bf->bf_lastbf = bf; 1278 ath_buf_set_rate(sc, bf); 1279 ath_tx_txqaddbuf(sc, txq, bf_head); 1280 } 1281 1282 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, 1283 struct list_head *bf_head) 1284 { 1285 struct ath_buf *bf; 1286 1287 bf = list_first_entry(bf_head, struct ath_buf, list); 1288 1289 bf->bf_lastbf = bf; 1290 bf->bf_nframes = 1; 1291 ath_buf_set_rate(sc, bf); 1292 ath_tx_txqaddbuf(sc, txq, bf_head); 1293 } 1294 1295 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) 1296 { 1297 struct ieee80211_hdr *hdr; 1298 enum ath9k_pkt_type htype; 1299 __le16 fc; 1300 1301 hdr = (struct ieee80211_hdr *)skb->data; 1302 fc = hdr->frame_control; 1303 1304 if (ieee80211_is_beacon(fc)) 1305 htype = ATH9K_PKT_TYPE_BEACON; 1306 else if (ieee80211_is_probe_resp(fc)) 1307 htype = ATH9K_PKT_TYPE_PROBE_RESP; 1308 else if (ieee80211_is_atim(fc)) 1309 htype = ATH9K_PKT_TYPE_ATIM; 1310 else if (ieee80211_is_pspoll(fc)) 1311 htype = ATH9K_PKT_TYPE_PSPOLL; 1312 else 1313 htype = ATH9K_PKT_TYPE_NORMAL; 1314 1315 return htype; 1316 } 1317 1318 static bool is_pae(struct sk_buff *skb) 1319 { 1320 struct ieee80211_hdr *hdr; 1321 __le16 fc; 1322 1323 hdr = (struct ieee80211_hdr *)skb->data; 1324 fc = hdr->frame_control; 1325 1326 if (ieee80211_is_data(fc)) { 1327 if (ieee80211_is_nullfunc(fc) || 1328 /* Port Access Entity (IEEE 802.1X) */ 1329 (skb->protocol == cpu_to_be16(ETH_P_PAE))) { 1330 return true; 1331 } 1332 } 1333 1334 return false; 1335 } 1336 1337 static int get_hw_crypto_keytype(struct sk_buff *skb) 1338 { 1339 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1340 1341 if (tx_info->control.hw_key) { 1342 if (tx_info->control.hw_key->alg == ALG_WEP) 1343 return ATH9K_KEY_TYPE_WEP; 1344 else if (tx_info->control.hw_key->alg == ALG_TKIP) 1345 return ATH9K_KEY_TYPE_TKIP; 1346 else if (tx_info->control.hw_key->alg == ALG_CCMP) 1347 return ATH9K_KEY_TYPE_AES; 1348 } 1349 1350 return ATH9K_KEY_TYPE_CLEAR; 1351 } 1352 1353 static void assign_aggr_tid_seqno(struct sk_buff *skb, 1354 struct ath_buf *bf) 1355 { 1356 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1357 struct ieee80211_hdr *hdr; 1358 struct ath_node *an; 1359 struct ath_atx_tid *tid; 1360 __le16 fc; 1361 u8 *qc; 1362 1363 if (!tx_info->control.sta) 1364 return; 1365 1366 an = (struct ath_node *)tx_info->control.sta->drv_priv; 1367 hdr = (struct ieee80211_hdr *)skb->data; 1368 fc = hdr->frame_control; 1369 1370 if (ieee80211_is_data_qos(fc)) { 1371 qc = ieee80211_get_qos_ctl(hdr); 1372 bf->bf_tidno = qc[0] & 0xf; 1373 } 1374 1375 /* 1376 * For HT capable stations, we save tidno for later use. 1377 * We also override seqno set by upper layer with the one 1378 * in tx aggregation state. 1379 * 1380 * If fragmentation is on, the sequence number is 1381 * not overridden, since it has been 1382 * incremented by the fragmentation routine. 1383 * 1384 * FIXME: check if the fragmentation threshold exceeds 1385 * IEEE80211 max. 1386 */ 1387 tid = ATH_AN_2_TID(an, bf->bf_tidno); 1388 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << 1389 IEEE80211_SEQ_SEQ_SHIFT); 1390 bf->bf_seqno = tid->seq_next; 1391 INCR(tid->seq_next, IEEE80211_SEQ_MAX); 1392 } 1393 1394 static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb, 1395 struct ath_txq *txq) 1396 { 1397 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1398 int flags = 0; 1399 1400 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */ 1401 flags |= ATH9K_TXDESC_INTREQ; 1402 1403 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) 1404 flags |= ATH9K_TXDESC_NOACK; 1405 1406 return flags; 1407 } 1408 1409 /* 1410 * rix - rate index 1411 * pktlen - total bytes (delims + data + fcs + pads + pad delims) 1412 * width - 0 for 20 MHz, 1 for 40 MHz 1413 * half_gi - to use 4us v/s 3.6 us for symbol time 1414 */ 1415 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf, 1416 int width, int half_gi, bool shortPreamble) 1417 { 1418 const struct ath_rate_table *rate_table = sc->cur_rate_table; 1419 u32 nbits, nsymbits, duration, nsymbols; 1420 u8 rc; 1421 int streams, pktlen; 1422 1423 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen; 1424 rc = rate_table->info[rix].ratecode; 1425 1426 /* for legacy rates, use old function to compute packet duration */ 1427 if (!IS_HT_RATE(rc)) 1428 return ath9k_hw_computetxtime(sc->sc_ah, rate_table, pktlen, 1429 rix, shortPreamble); 1430 1431 /* find number of symbols: PLCP + data */ 1432 nbits = (pktlen << 3) + OFDM_PLCP_BITS; 1433 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; 1434 nsymbols = (nbits + nsymbits - 1) / nsymbits; 1435 1436 if (!half_gi) 1437 duration = SYMBOL_TIME(nsymbols); 1438 else 1439 duration = SYMBOL_TIME_HALFGI(nsymbols); 1440 1441 /* addup duration for legacy/ht training and signal fields */ 1442 streams = HT_RC_2_STREAMS(rc); 1443 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); 1444 1445 return duration; 1446 } 1447 1448 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf) 1449 { 1450 const struct ath_rate_table *rt = sc->cur_rate_table; 1451 struct ath9k_11n_rate_series series[4]; 1452 struct sk_buff *skb; 1453 struct ieee80211_tx_info *tx_info; 1454 struct ieee80211_tx_rate *rates; 1455 struct ieee80211_hdr *hdr; 1456 int i, flags = 0; 1457 u8 rix = 0, ctsrate = 0; 1458 bool is_pspoll; 1459 1460 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4); 1461 1462 skb = bf->bf_mpdu; 1463 tx_info = IEEE80211_SKB_CB(skb); 1464 rates = tx_info->control.rates; 1465 hdr = (struct ieee80211_hdr *)skb->data; 1466 is_pspoll = ieee80211_is_pspoll(hdr->frame_control); 1467 1468 /* 1469 * We check if Short Preamble is needed for the CTS rate by 1470 * checking the BSS's global flag. 1471 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. 1472 */ 1473 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT) 1474 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode | 1475 rt->info[tx_info->control.rts_cts_rate_idx].short_preamble; 1476 else 1477 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode; 1478 1479 /* 1480 * ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. 1481 * Check the first rate in the series to decide whether RTS/CTS 1482 * or CTS-to-self has to be used. 1483 */ 1484 if (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) 1485 flags = ATH9K_TXDESC_CTSENA; 1486 else if (rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) 1487 flags = ATH9K_TXDESC_RTSENA; 1488 1489 /* FIXME: Handle aggregation protection */ 1490 if (sc->config.ath_aggr_prot && 1491 (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) { 1492 flags = ATH9K_TXDESC_RTSENA; 1493 } 1494 1495 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ 1496 if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit)) 1497 flags &= ~(ATH9K_TXDESC_RTSENA); 1498 1499 for (i = 0; i < 4; i++) { 1500 if (!rates[i].count || (rates[i].idx < 0)) 1501 continue; 1502 1503 rix = rates[i].idx; 1504 series[i].Tries = rates[i].count; 1505 series[i].ChSel = sc->tx_chainmask; 1506 1507 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) 1508 series[i].Rate = rt->info[rix].ratecode | 1509 rt->info[rix].short_preamble; 1510 else 1511 series[i].Rate = rt->info[rix].ratecode; 1512 1513 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) 1514 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; 1515 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) 1516 series[i].RateFlags |= ATH9K_RATESERIES_2040; 1517 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) 1518 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI; 1519 1520 series[i].PktDuration = ath_pkt_duration(sc, rix, bf, 1521 (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) != 0, 1522 (rates[i].flags & IEEE80211_TX_RC_SHORT_GI), 1523 (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)); 1524 } 1525 1526 /* set dur_update_en for l-sig computation except for PS-Poll frames */ 1527 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc, 1528 bf->bf_lastbf->bf_desc, 1529 !is_pspoll, ctsrate, 1530 0, series, 4, flags); 1531 1532 if (sc->config.ath_aggr_prot && flags) 1533 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192); 1534 } 1535 1536 static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf, 1537 struct sk_buff *skb, 1538 struct ath_tx_control *txctl) 1539 { 1540 struct ath_wiphy *aphy = hw->priv; 1541 struct ath_softc *sc = aphy->sc; 1542 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1543 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1544 struct ath_tx_info_priv *tx_info_priv; 1545 int hdrlen; 1546 __le16 fc; 1547 1548 tx_info_priv = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC); 1549 if (unlikely(!tx_info_priv)) 1550 return -ENOMEM; 1551 tx_info->rate_driver_data[0] = tx_info_priv; 1552 tx_info_priv->aphy = aphy; 1553 tx_info_priv->frame_type = txctl->frame_type; 1554 hdrlen = ieee80211_get_hdrlen_from_skb(skb); 1555 fc = hdr->frame_control; 1556 1557 ATH_TXBUF_RESET(bf); 1558 1559 bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3); 1560 1561 if (conf_is_ht(&sc->hw->conf) && !is_pae(skb)) 1562 bf->bf_state.bf_type |= BUF_HT; 1563 1564 bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq); 1565 1566 bf->bf_keytype = get_hw_crypto_keytype(skb); 1567 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) { 1568 bf->bf_frmlen += tx_info->control.hw_key->icv_len; 1569 bf->bf_keyix = tx_info->control.hw_key->hw_key_idx; 1570 } else { 1571 bf->bf_keyix = ATH9K_TXKEYIX_INVALID; 1572 } 1573 1574 if (ieee80211_is_data_qos(fc) && (sc->sc_flags & SC_OP_TXAGGR)) 1575 assign_aggr_tid_seqno(skb, bf); 1576 1577 bf->bf_mpdu = skb; 1578 1579 bf->bf_dmacontext = dma_map_single(sc->dev, skb->data, 1580 skb->len, DMA_TO_DEVICE); 1581 if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) { 1582 bf->bf_mpdu = NULL; 1583 kfree(tx_info_priv); 1584 tx_info->rate_driver_data[0] = NULL; 1585 DPRINTF(sc, ATH_DBG_FATAL, "dma_mapping_error() on TX\n"); 1586 return -ENOMEM; 1587 } 1588 1589 bf->bf_buf_addr = bf->bf_dmacontext; 1590 return 0; 1591 } 1592 1593 /* FIXME: tx power */ 1594 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf, 1595 struct ath_tx_control *txctl) 1596 { 1597 struct sk_buff *skb = bf->bf_mpdu; 1598 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1599 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1600 struct ath_node *an = NULL; 1601 struct list_head bf_head; 1602 struct ath_desc *ds; 1603 struct ath_atx_tid *tid; 1604 struct ath_hw *ah = sc->sc_ah; 1605 int frm_type; 1606 __le16 fc; 1607 1608 frm_type = get_hw_packet_type(skb); 1609 fc = hdr->frame_control; 1610 1611 INIT_LIST_HEAD(&bf_head); 1612 list_add_tail(&bf->list, &bf_head); 1613 1614 ds = bf->bf_desc; 1615 ds->ds_link = 0; 1616 ds->ds_data = bf->bf_buf_addr; 1617 1618 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER, 1619 bf->bf_keyix, bf->bf_keytype, bf->bf_flags); 1620 1621 ath9k_hw_filltxdesc(ah, ds, 1622 skb->len, /* segment length */ 1623 true, /* first segment */ 1624 true, /* last segment */ 1625 ds); /* first descriptor */ 1626 1627 spin_lock_bh(&txctl->txq->axq_lock); 1628 1629 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) && 1630 tx_info->control.sta) { 1631 an = (struct ath_node *)tx_info->control.sta->drv_priv; 1632 tid = ATH_AN_2_TID(an, bf->bf_tidno); 1633 1634 if (!ieee80211_is_data_qos(fc)) { 1635 ath_tx_send_normal(sc, txctl->txq, &bf_head); 1636 goto tx_done; 1637 } 1638 1639 if (ath_aggr_query(sc, an, bf->bf_tidno)) { 1640 /* 1641 * Try aggregation if it's a unicast data frame 1642 * and the destination is HT capable. 1643 */ 1644 ath_tx_send_ampdu(sc, tid, &bf_head, txctl); 1645 } else { 1646 /* 1647 * Send this frame as regular when ADDBA 1648 * exchange is neither complete nor pending. 1649 */ 1650 ath_tx_send_ht_normal(sc, txctl->txq, 1651 tid, &bf_head); 1652 } 1653 } else { 1654 ath_tx_send_normal(sc, txctl->txq, &bf_head); 1655 } 1656 1657 tx_done: 1658 spin_unlock_bh(&txctl->txq->axq_lock); 1659 } 1660 1661 /* Upon failure caller should free skb */ 1662 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, 1663 struct ath_tx_control *txctl) 1664 { 1665 struct ath_wiphy *aphy = hw->priv; 1666 struct ath_softc *sc = aphy->sc; 1667 struct ath_buf *bf; 1668 int r; 1669 1670 bf = ath_tx_get_buffer(sc); 1671 if (!bf) { 1672 DPRINTF(sc, ATH_DBG_XMIT, "TX buffers are full\n"); 1673 return -1; 1674 } 1675 1676 r = ath_tx_setup_buffer(hw, bf, skb, txctl); 1677 if (unlikely(r)) { 1678 struct ath_txq *txq = txctl->txq; 1679 1680 DPRINTF(sc, ATH_DBG_FATAL, "TX mem alloc failure\n"); 1681 1682 /* upon ath_tx_processq() this TX queue will be resumed, we 1683 * guarantee this will happen by knowing beforehand that 1684 * we will at least have to run TX completionon one buffer 1685 * on the queue */ 1686 spin_lock_bh(&txq->axq_lock); 1687 if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) { 1688 ieee80211_stop_queue(sc->hw, 1689 skb_get_queue_mapping(skb)); 1690 txq->stopped = 1; 1691 } 1692 spin_unlock_bh(&txq->axq_lock); 1693 1694 spin_lock_bh(&sc->tx.txbuflock); 1695 list_add_tail(&bf->list, &sc->tx.txbuf); 1696 spin_unlock_bh(&sc->tx.txbuflock); 1697 1698 return r; 1699 } 1700 1701 ath_tx_start_dma(sc, bf, txctl); 1702 1703 return 0; 1704 } 1705 1706 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb) 1707 { 1708 struct ath_wiphy *aphy = hw->priv; 1709 struct ath_softc *sc = aphy->sc; 1710 int hdrlen, padsize; 1711 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1712 struct ath_tx_control txctl; 1713 1714 memset(&txctl, 0, sizeof(struct ath_tx_control)); 1715 1716 /* 1717 * As a temporary workaround, assign seq# here; this will likely need 1718 * to be cleaned up to work better with Beacon transmission and virtual 1719 * BSSes. 1720 */ 1721 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { 1722 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; 1723 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) 1724 sc->tx.seq_no += 0x10; 1725 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); 1726 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); 1727 } 1728 1729 /* Add the padding after the header if this is not already done */ 1730 hdrlen = ieee80211_get_hdrlen_from_skb(skb); 1731 if (hdrlen & 3) { 1732 padsize = hdrlen % 4; 1733 if (skb_headroom(skb) < padsize) { 1734 DPRINTF(sc, ATH_DBG_XMIT, "TX CABQ padding failed\n"); 1735 dev_kfree_skb_any(skb); 1736 return; 1737 } 1738 skb_push(skb, padsize); 1739 memmove(skb->data, skb->data + padsize, hdrlen); 1740 } 1741 1742 txctl.txq = sc->beacon.cabq; 1743 1744 DPRINTF(sc, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb); 1745 1746 if (ath_tx_start(hw, skb, &txctl) != 0) { 1747 DPRINTF(sc, ATH_DBG_XMIT, "CABQ TX failed\n"); 1748 goto exit; 1749 } 1750 1751 return; 1752 exit: 1753 dev_kfree_skb_any(skb); 1754 } 1755 1756 /*****************/ 1757 /* TX Completion */ 1758 /*****************/ 1759 1760 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, 1761 int tx_flags) 1762 { 1763 struct ieee80211_hw *hw = sc->hw; 1764 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1765 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info); 1766 int hdrlen, padsize; 1767 int frame_type = ATH9K_NOT_INTERNAL; 1768 1769 DPRINTF(sc, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb); 1770 1771 if (tx_info_priv) { 1772 hw = tx_info_priv->aphy->hw; 1773 frame_type = tx_info_priv->frame_type; 1774 } 1775 1776 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK || 1777 tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) { 1778 kfree(tx_info_priv); 1779 tx_info->rate_driver_data[0] = NULL; 1780 } 1781 1782 if (tx_flags & ATH_TX_BAR) 1783 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; 1784 1785 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) { 1786 /* Frame was ACKed */ 1787 tx_info->flags |= IEEE80211_TX_STAT_ACK; 1788 } 1789 1790 hdrlen = ieee80211_get_hdrlen_from_skb(skb); 1791 padsize = hdrlen & 3; 1792 if (padsize && hdrlen >= 24) { 1793 /* 1794 * Remove MAC header padding before giving the frame back to 1795 * mac80211. 1796 */ 1797 memmove(skb->data + padsize, skb->data, hdrlen); 1798 skb_pull(skb, padsize); 1799 } 1800 1801 if (sc->sc_flags & SC_OP_WAIT_FOR_TX_ACK) { 1802 sc->sc_flags &= ~SC_OP_WAIT_FOR_TX_ACK; 1803 DPRINTF(sc, ATH_DBG_PS, "Going back to sleep after having " 1804 "received TX status (0x%x)\n", 1805 sc->sc_flags & (SC_OP_WAIT_FOR_BEACON | 1806 SC_OP_WAIT_FOR_CAB | 1807 SC_OP_WAIT_FOR_PSPOLL_DATA | 1808 SC_OP_WAIT_FOR_TX_ACK)); 1809 } 1810 1811 if (frame_type == ATH9K_NOT_INTERNAL) 1812 ieee80211_tx_status(hw, skb); 1813 else 1814 ath9k_tx_status(hw, skb); 1815 } 1816 1817 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, 1818 struct list_head *bf_q, 1819 int txok, int sendbar) 1820 { 1821 struct sk_buff *skb = bf->bf_mpdu; 1822 unsigned long flags; 1823 int tx_flags = 0; 1824 1825 1826 if (sendbar) 1827 tx_flags = ATH_TX_BAR; 1828 1829 if (!txok) { 1830 tx_flags |= ATH_TX_ERROR; 1831 1832 if (bf_isxretried(bf)) 1833 tx_flags |= ATH_TX_XRETRY; 1834 } 1835 1836 dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE); 1837 ath_tx_complete(sc, skb, tx_flags); 1838 1839 /* 1840 * Return the list of ath_buf of this mpdu to free queue 1841 */ 1842 spin_lock_irqsave(&sc->tx.txbuflock, flags); 1843 list_splice_tail_init(bf_q, &sc->tx.txbuf); 1844 spin_unlock_irqrestore(&sc->tx.txbuflock, flags); 1845 } 1846 1847 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf, 1848 int txok) 1849 { 1850 struct ath_buf *bf_last = bf->bf_lastbf; 1851 struct ath_desc *ds = bf_last->bf_desc; 1852 u16 seq_st = 0; 1853 u32 ba[WME_BA_BMP_SIZE >> 5]; 1854 int ba_index; 1855 int nbad = 0; 1856 int isaggr = 0; 1857 1858 if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED) 1859 return 0; 1860 1861 isaggr = bf_isaggr(bf); 1862 if (isaggr) { 1863 seq_st = ATH_DS_BA_SEQ(ds); 1864 memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3); 1865 } 1866 1867 while (bf) { 1868 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno); 1869 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) 1870 nbad++; 1871 1872 bf = bf->bf_next; 1873 } 1874 1875 return nbad; 1876 } 1877 1878 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds, 1879 int nbad, int txok, bool update_rc) 1880 { 1881 struct sk_buff *skb = bf->bf_mpdu; 1882 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1883 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 1884 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info); 1885 struct ieee80211_hw *hw = tx_info_priv->aphy->hw; 1886 u8 i, tx_rateindex; 1887 1888 if (txok) 1889 tx_info->status.ack_signal = ds->ds_txstat.ts_rssi; 1890 1891 tx_rateindex = ds->ds_txstat.ts_rateindex; 1892 WARN_ON(tx_rateindex >= hw->max_rates); 1893 1894 tx_info_priv->update_rc = update_rc; 1895 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) 1896 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 1897 1898 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 && 1899 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) { 1900 if (ieee80211_is_data(hdr->frame_control)) { 1901 memcpy(&tx_info_priv->tx, &ds->ds_txstat, 1902 sizeof(tx_info_priv->tx)); 1903 tx_info_priv->n_frames = bf->bf_nframes; 1904 tx_info_priv->n_bad_frames = nbad; 1905 } 1906 } 1907 1908 for (i = tx_rateindex + 1; i < hw->max_rates; i++) 1909 tx_info->status.rates[i].count = 0; 1910 1911 tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1; 1912 } 1913 1914 static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq) 1915 { 1916 int qnum; 1917 1918 spin_lock_bh(&txq->axq_lock); 1919 if (txq->stopped && 1920 sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) { 1921 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc); 1922 if (qnum != -1) { 1923 ieee80211_wake_queue(sc->hw, qnum); 1924 txq->stopped = 0; 1925 } 1926 } 1927 spin_unlock_bh(&txq->axq_lock); 1928 } 1929 1930 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 1931 { 1932 struct ath_hw *ah = sc->sc_ah; 1933 struct ath_buf *bf, *lastbf, *bf_held = NULL; 1934 struct list_head bf_head; 1935 struct ath_desc *ds; 1936 int txok; 1937 int status; 1938 1939 DPRINTF(sc, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n", 1940 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), 1941 txq->axq_link); 1942 1943 for (;;) { 1944 spin_lock_bh(&txq->axq_lock); 1945 if (list_empty(&txq->axq_q)) { 1946 txq->axq_link = NULL; 1947 txq->axq_linkbuf = NULL; 1948 spin_unlock_bh(&txq->axq_lock); 1949 break; 1950 } 1951 bf = list_first_entry(&txq->axq_q, struct ath_buf, list); 1952 1953 /* 1954 * There is a race condition that a BH gets scheduled 1955 * after sw writes TxE and before hw re-load the last 1956 * descriptor to get the newly chained one. 1957 * Software must keep the last DONE descriptor as a 1958 * holding descriptor - software does so by marking 1959 * it with the STALE flag. 1960 */ 1961 bf_held = NULL; 1962 if (bf->bf_stale) { 1963 bf_held = bf; 1964 if (list_is_last(&bf_held->list, &txq->axq_q)) { 1965 txq->axq_link = NULL; 1966 txq->axq_linkbuf = NULL; 1967 spin_unlock_bh(&txq->axq_lock); 1968 1969 /* 1970 * The holding descriptor is the last 1971 * descriptor in queue. It's safe to remove 1972 * the last holding descriptor in BH context. 1973 */ 1974 spin_lock_bh(&sc->tx.txbuflock); 1975 list_move_tail(&bf_held->list, &sc->tx.txbuf); 1976 spin_unlock_bh(&sc->tx.txbuflock); 1977 1978 break; 1979 } else { 1980 bf = list_entry(bf_held->list.next, 1981 struct ath_buf, list); 1982 } 1983 } 1984 1985 lastbf = bf->bf_lastbf; 1986 ds = lastbf->bf_desc; 1987 1988 status = ath9k_hw_txprocdesc(ah, ds); 1989 if (status == -EINPROGRESS) { 1990 spin_unlock_bh(&txq->axq_lock); 1991 break; 1992 } 1993 if (bf->bf_desc == txq->axq_lastdsWithCTS) 1994 txq->axq_lastdsWithCTS = NULL; 1995 if (ds == txq->axq_gatingds) 1996 txq->axq_gatingds = NULL; 1997 1998 /* 1999 * Remove ath_buf's of the same transmit unit from txq, 2000 * however leave the last descriptor back as the holding 2001 * descriptor for hw. 2002 */ 2003 lastbf->bf_stale = true; 2004 INIT_LIST_HEAD(&bf_head); 2005 if (!list_is_singular(&lastbf->list)) 2006 list_cut_position(&bf_head, 2007 &txq->axq_q, lastbf->list.prev); 2008 2009 txq->axq_depth--; 2010 if (bf_isaggr(bf)) 2011 txq->axq_aggr_depth--; 2012 2013 txok = (ds->ds_txstat.ts_status == 0); 2014 spin_unlock_bh(&txq->axq_lock); 2015 2016 if (bf_held) { 2017 spin_lock_bh(&sc->tx.txbuflock); 2018 list_move_tail(&bf_held->list, &sc->tx.txbuf); 2019 spin_unlock_bh(&sc->tx.txbuflock); 2020 } 2021 2022 if (!bf_isampdu(bf)) { 2023 /* 2024 * This frame is sent out as a single frame. 2025 * Use hardware retry status for this frame. 2026 */ 2027 bf->bf_retries = ds->ds_txstat.ts_longretry; 2028 if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY) 2029 bf->bf_state.bf_type |= BUF_XRETRY; 2030 ath_tx_rc_status(bf, ds, 0, txok, true); 2031 } 2032 2033 if (bf_isampdu(bf)) 2034 ath_tx_complete_aggr(sc, txq, bf, &bf_head, txok); 2035 else 2036 ath_tx_complete_buf(sc, bf, &bf_head, txok, 0); 2037 2038 ath_wake_mac80211_queue(sc, txq); 2039 2040 spin_lock_bh(&txq->axq_lock); 2041 if (sc->sc_flags & SC_OP_TXAGGR) 2042 ath_txq_schedule(sc, txq); 2043 spin_unlock_bh(&txq->axq_lock); 2044 } 2045 } 2046 2047 2048 void ath_tx_tasklet(struct ath_softc *sc) 2049 { 2050 int i; 2051 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1); 2052 2053 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask); 2054 2055 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 2056 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) 2057 ath_tx_processq(sc, &sc->tx.txq[i]); 2058 } 2059 } 2060 2061 /*****************/ 2062 /* Init, Cleanup */ 2063 /*****************/ 2064 2065 int ath_tx_init(struct ath_softc *sc, int nbufs) 2066 { 2067 int error = 0; 2068 2069 spin_lock_init(&sc->tx.txbuflock); 2070 2071 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, 2072 "tx", nbufs, 1); 2073 if (error != 0) { 2074 DPRINTF(sc, ATH_DBG_FATAL, 2075 "Failed to allocate tx descriptors: %d\n", error); 2076 goto err; 2077 } 2078 2079 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, 2080 "beacon", ATH_BCBUF, 1); 2081 if (error != 0) { 2082 DPRINTF(sc, ATH_DBG_FATAL, 2083 "Failed to allocate beacon descriptors: %d\n", error); 2084 goto err; 2085 } 2086 2087 err: 2088 if (error != 0) 2089 ath_tx_cleanup(sc); 2090 2091 return error; 2092 } 2093 2094 void ath_tx_cleanup(struct ath_softc *sc) 2095 { 2096 if (sc->beacon.bdma.dd_desc_len != 0) 2097 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf); 2098 2099 if (sc->tx.txdma.dd_desc_len != 0) 2100 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf); 2101 } 2102 2103 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) 2104 { 2105 struct ath_atx_tid *tid; 2106 struct ath_atx_ac *ac; 2107 int tidno, acno; 2108 2109 for (tidno = 0, tid = &an->tid[tidno]; 2110 tidno < WME_NUM_TID; 2111 tidno++, tid++) { 2112 tid->an = an; 2113 tid->tidno = tidno; 2114 tid->seq_start = tid->seq_next = 0; 2115 tid->baw_size = WME_MAX_BA; 2116 tid->baw_head = tid->baw_tail = 0; 2117 tid->sched = false; 2118 tid->paused = false; 2119 tid->state &= ~AGGR_CLEANUP; 2120 INIT_LIST_HEAD(&tid->buf_q); 2121 acno = TID_TO_WME_AC(tidno); 2122 tid->ac = &an->ac[acno]; 2123 tid->state &= ~AGGR_ADDBA_COMPLETE; 2124 tid->state &= ~AGGR_ADDBA_PROGRESS; 2125 tid->addba_exchangeattempts = 0; 2126 } 2127 2128 for (acno = 0, ac = &an->ac[acno]; 2129 acno < WME_NUM_AC; acno++, ac++) { 2130 ac->sched = false; 2131 INIT_LIST_HEAD(&ac->tid_q); 2132 2133 switch (acno) { 2134 case WME_AC_BE: 2135 ac->qnum = ath_tx_get_qnum(sc, 2136 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE); 2137 break; 2138 case WME_AC_BK: 2139 ac->qnum = ath_tx_get_qnum(sc, 2140 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK); 2141 break; 2142 case WME_AC_VI: 2143 ac->qnum = ath_tx_get_qnum(sc, 2144 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI); 2145 break; 2146 case WME_AC_VO: 2147 ac->qnum = ath_tx_get_qnum(sc, 2148 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO); 2149 break; 2150 } 2151 } 2152 } 2153 2154 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) 2155 { 2156 int i; 2157 struct ath_atx_ac *ac, *ac_tmp; 2158 struct ath_atx_tid *tid, *tid_tmp; 2159 struct ath_txq *txq; 2160 2161 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { 2162 if (ATH_TXQ_SETUP(sc, i)) { 2163 txq = &sc->tx.txq[i]; 2164 2165 spin_lock(&txq->axq_lock); 2166 2167 list_for_each_entry_safe(ac, 2168 ac_tmp, &txq->axq_acq, list) { 2169 tid = list_first_entry(&ac->tid_q, 2170 struct ath_atx_tid, list); 2171 if (tid && tid->an != an) 2172 continue; 2173 list_del(&ac->list); 2174 ac->sched = false; 2175 2176 list_for_each_entry_safe(tid, 2177 tid_tmp, &ac->tid_q, list) { 2178 list_del(&tid->list); 2179 tid->sched = false; 2180 ath_tid_drain(sc, txq, tid); 2181 tid->state &= ~AGGR_ADDBA_COMPLETE; 2182 tid->addba_exchangeattempts = 0; 2183 tid->state &= ~AGGR_CLEANUP; 2184 } 2185 } 2186 2187 spin_unlock(&txq->axq_lock); 2188 } 2189 } 2190 } 2191