1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #include "hal_desc.h" 8 #include "hal_wcn7850.h" 9 #include "hw.h" 10 #include "hal.h" 11 #include "hal_tx.h" 12 13 static const struct hal_srng_config hw_srng_config_template[] = { 14 /* TODO: max_rings can populated by querying HW capabilities */ 15 [HAL_REO_DST] = { 16 .start_ring_id = HAL_SRNG_RING_ID_REO2SW1, 17 .max_rings = 8, 18 .entry_size = sizeof(struct hal_reo_dest_ring) >> 2, 19 .mac_type = ATH12K_HAL_SRNG_UMAC, 20 .ring_dir = HAL_SRNG_DIR_DST, 21 .max_size = HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE, 22 }, 23 [HAL_REO_EXCEPTION] = { 24 /* Designating REO2SW0 ring as exception ring. 25 * Any of theREO2SW rings can be used as exception ring. 26 */ 27 .start_ring_id = HAL_SRNG_RING_ID_REO2SW0, 28 .max_rings = 1, 29 .entry_size = sizeof(struct hal_reo_dest_ring) >> 2, 30 .mac_type = ATH12K_HAL_SRNG_UMAC, 31 .ring_dir = HAL_SRNG_DIR_DST, 32 .max_size = HAL_REO_REO2SW0_RING_BASE_MSB_RING_SIZE, 33 }, 34 [HAL_REO_REINJECT] = { 35 .start_ring_id = HAL_SRNG_RING_ID_SW2REO, 36 .max_rings = 4, 37 .entry_size = sizeof(struct hal_reo_entrance_ring) >> 2, 38 .mac_type = ATH12K_HAL_SRNG_UMAC, 39 .ring_dir = HAL_SRNG_DIR_SRC, 40 .max_size = HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE, 41 }, 42 [HAL_REO_CMD] = { 43 .start_ring_id = HAL_SRNG_RING_ID_REO_CMD, 44 .max_rings = 1, 45 .entry_size = (sizeof(struct hal_tlv_64_hdr) + 46 sizeof(struct hal_reo_get_queue_stats)) >> 2, 47 .mac_type = ATH12K_HAL_SRNG_UMAC, 48 .ring_dir = HAL_SRNG_DIR_SRC, 49 .max_size = HAL_REO_CMD_RING_BASE_MSB_RING_SIZE, 50 }, 51 [HAL_REO_STATUS] = { 52 .start_ring_id = HAL_SRNG_RING_ID_REO_STATUS, 53 .max_rings = 1, 54 .entry_size = (sizeof(struct hal_tlv_64_hdr) + 55 sizeof(struct hal_reo_get_queue_stats_status)) >> 2, 56 .mac_type = ATH12K_HAL_SRNG_UMAC, 57 .ring_dir = HAL_SRNG_DIR_DST, 58 .max_size = HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE, 59 }, 60 [HAL_TCL_DATA] = { 61 .start_ring_id = HAL_SRNG_RING_ID_SW2TCL1, 62 .max_rings = 6, 63 .entry_size = sizeof(struct hal_tcl_data_cmd) >> 2, 64 .mac_type = ATH12K_HAL_SRNG_UMAC, 65 .ring_dir = HAL_SRNG_DIR_SRC, 66 .max_size = HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE, 67 }, 68 [HAL_TCL_CMD] = { 69 .start_ring_id = HAL_SRNG_RING_ID_SW2TCL_CMD, 70 .max_rings = 1, 71 .entry_size = sizeof(struct hal_tcl_gse_cmd) >> 2, 72 .mac_type = ATH12K_HAL_SRNG_UMAC, 73 .ring_dir = HAL_SRNG_DIR_SRC, 74 .max_size = HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE, 75 }, 76 [HAL_TCL_STATUS] = { 77 .start_ring_id = HAL_SRNG_RING_ID_TCL_STATUS, 78 .max_rings = 1, 79 .entry_size = (sizeof(struct hal_tlv_hdr) + 80 sizeof(struct hal_tcl_status_ring)) >> 2, 81 .mac_type = ATH12K_HAL_SRNG_UMAC, 82 .ring_dir = HAL_SRNG_DIR_DST, 83 .max_size = HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE, 84 }, 85 [HAL_CE_SRC] = { 86 .start_ring_id = HAL_SRNG_RING_ID_CE0_SRC, 87 .max_rings = 16, 88 .entry_size = sizeof(struct hal_ce_srng_src_desc) >> 2, 89 .mac_type = ATH12K_HAL_SRNG_UMAC, 90 .ring_dir = HAL_SRNG_DIR_SRC, 91 .max_size = HAL_CE_SRC_RING_BASE_MSB_RING_SIZE, 92 }, 93 [HAL_CE_DST] = { 94 .start_ring_id = HAL_SRNG_RING_ID_CE0_DST, 95 .max_rings = 16, 96 .entry_size = sizeof(struct hal_ce_srng_dest_desc) >> 2, 97 .mac_type = ATH12K_HAL_SRNG_UMAC, 98 .ring_dir = HAL_SRNG_DIR_SRC, 99 .max_size = HAL_CE_DST_RING_BASE_MSB_RING_SIZE, 100 }, 101 [HAL_CE_DST_STATUS] = { 102 .start_ring_id = HAL_SRNG_RING_ID_CE0_DST_STATUS, 103 .max_rings = 16, 104 .entry_size = sizeof(struct hal_ce_srng_dst_status_desc) >> 2, 105 .mac_type = ATH12K_HAL_SRNG_UMAC, 106 .ring_dir = HAL_SRNG_DIR_DST, 107 .max_size = HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE, 108 }, 109 [HAL_WBM_IDLE_LINK] = { 110 .start_ring_id = HAL_SRNG_RING_ID_WBM_IDLE_LINK, 111 .max_rings = 1, 112 .entry_size = sizeof(struct hal_wbm_link_desc) >> 2, 113 .mac_type = ATH12K_HAL_SRNG_UMAC, 114 .ring_dir = HAL_SRNG_DIR_SRC, 115 .max_size = HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE, 116 }, 117 [HAL_SW2WBM_RELEASE] = { 118 .start_ring_id = HAL_SRNG_RING_ID_WBM_SW0_RELEASE, 119 .max_rings = 2, 120 .entry_size = sizeof(struct hal_wbm_release_ring) >> 2, 121 .mac_type = ATH12K_HAL_SRNG_UMAC, 122 .ring_dir = HAL_SRNG_DIR_SRC, 123 .max_size = HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE, 124 }, 125 [HAL_WBM2SW_RELEASE] = { 126 .start_ring_id = HAL_SRNG_RING_ID_WBM2SW0_RELEASE, 127 .max_rings = 8, 128 .entry_size = sizeof(struct hal_wbm_release_ring) >> 2, 129 .mac_type = ATH12K_HAL_SRNG_UMAC, 130 .ring_dir = HAL_SRNG_DIR_DST, 131 .max_size = HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE, 132 }, 133 [HAL_RXDMA_BUF] = { 134 .start_ring_id = HAL_SRNG_SW2RXDMA_BUF0, 135 .max_rings = 1, 136 .entry_size = sizeof(struct hal_wbm_buffer_ring) >> 2, 137 .mac_type = ATH12K_HAL_SRNG_DMAC, 138 .ring_dir = HAL_SRNG_DIR_SRC, 139 .max_size = HAL_RXDMA_RING_MAX_SIZE_BE, 140 }, 141 [HAL_RXDMA_DST] = { 142 .start_ring_id = HAL_SRNG_RING_ID_WMAC1_RXDMA2SW0, 143 .max_rings = 0, 144 .entry_size = 0, 145 .mac_type = ATH12K_HAL_SRNG_PMAC, 146 .ring_dir = HAL_SRNG_DIR_DST, 147 .max_size = HAL_RXDMA_RING_MAX_SIZE_BE, 148 }, 149 [HAL_RXDMA_MONITOR_BUF] = {}, 150 [HAL_RXDMA_MONITOR_STATUS] = { 151 .start_ring_id = HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_STATBUF, 152 .max_rings = 1, 153 .entry_size = sizeof(struct hal_wbm_buffer_ring) >> 2, 154 .mac_type = ATH12K_HAL_SRNG_PMAC, 155 .ring_dir = HAL_SRNG_DIR_SRC, 156 .max_size = HAL_RXDMA_RING_MAX_SIZE_BE, 157 }, 158 [HAL_RXDMA_MONITOR_DESC] = { 0, }, 159 [HAL_RXDMA_DIR_BUF] = { 160 .start_ring_id = HAL_SRNG_RING_ID_RXDMA_DIR_BUF, 161 .max_rings = 2, 162 .entry_size = 8 >> 2, /* TODO: Define the struct */ 163 .mac_type = ATH12K_HAL_SRNG_PMAC, 164 .ring_dir = HAL_SRNG_DIR_SRC, 165 .max_size = HAL_RXDMA_RING_MAX_SIZE_BE, 166 }, 167 [HAL_PPE2TCL] = {}, 168 [HAL_PPE_RELEASE] = {}, 169 [HAL_TX_MONITOR_BUF] = {}, 170 [HAL_RXDMA_MONITOR_DST] = {}, 171 [HAL_TX_MONITOR_DST] = {} 172 }; 173 174 const struct ath12k_hw_regs wcn7850_regs = { 175 /* SW2TCL(x) R0 ring configuration address */ 176 .tcl1_ring_id = 0x00000908, 177 .tcl1_ring_misc = 0x00000910, 178 .tcl1_ring_tp_addr_lsb = 0x0000091c, 179 .tcl1_ring_tp_addr_msb = 0x00000920, 180 .tcl1_ring_consumer_int_setup_ix0 = 0x00000930, 181 .tcl1_ring_consumer_int_setup_ix1 = 0x00000934, 182 .tcl1_ring_msi1_base_lsb = 0x00000948, 183 .tcl1_ring_msi1_base_msb = 0x0000094c, 184 .tcl1_ring_msi1_data = 0x00000950, 185 .tcl_ring_base_lsb = 0x00000b58, 186 .tcl1_ring_base_lsb = 0x00000900, 187 .tcl1_ring_base_msb = 0x00000904, 188 .tcl2_ring_base_lsb = 0x00000978, 189 190 /* TCL STATUS ring address */ 191 .tcl_status_ring_base_lsb = 0x00000d38, 192 193 .wbm_idle_ring_base_lsb = 0x00000d3c, 194 .wbm_idle_ring_misc_addr = 0x00000d4c, 195 .wbm_r0_idle_list_cntl_addr = 0x00000240, 196 .wbm_r0_idle_list_size_addr = 0x00000244, 197 .wbm_scattered_ring_base_lsb = 0x00000250, 198 .wbm_scattered_ring_base_msb = 0x00000254, 199 .wbm_scattered_desc_head_info_ix0 = 0x00000260, 200 .wbm_scattered_desc_head_info_ix1 = 0x00000264, 201 .wbm_scattered_desc_tail_info_ix0 = 0x00000270, 202 .wbm_scattered_desc_tail_info_ix1 = 0x00000274, 203 .wbm_scattered_desc_ptr_hp_addr = 0x00000027c, 204 205 .wbm_sw_release_ring_base_lsb = 0x0000037c, 206 .wbm_sw1_release_ring_base_lsb = 0x00000284, 207 .wbm0_release_ring_base_lsb = 0x00000e08, 208 .wbm1_release_ring_base_lsb = 0x00000e80, 209 210 /* PCIe base address */ 211 .pcie_qserdes_sysclk_en_sel = 0x01e0e0a8, 212 .pcie_pcs_osc_dtct_config_base = 0x01e0f45c, 213 214 /* PPE release ring address */ 215 .ppe_rel_ring_base = 0x0000043c, 216 217 /* REO DEST ring address */ 218 .reo2_ring_base = 0x0000055c, 219 .reo1_misc_ctrl_addr = 0x00000b7c, 220 .reo1_sw_cookie_cfg0 = 0x00000050, 221 .reo1_sw_cookie_cfg1 = 0x00000054, 222 .reo1_qdesc_lut_base0 = 0x00000058, 223 .reo1_qdesc_lut_base1 = 0x0000005c, 224 .reo1_ring_base_lsb = 0x000004e4, 225 .reo1_ring_base_msb = 0x000004e8, 226 .reo1_ring_id = 0x000004ec, 227 .reo1_ring_misc = 0x000004f4, 228 .reo1_ring_hp_addr_lsb = 0x000004f8, 229 .reo1_ring_hp_addr_msb = 0x000004fc, 230 .reo1_ring_producer_int_setup = 0x00000508, 231 .reo1_ring_msi1_base_lsb = 0x0000052C, 232 .reo1_ring_msi1_base_msb = 0x00000530, 233 .reo1_ring_msi1_data = 0x00000534, 234 .reo1_aging_thres_ix0 = 0x00000b08, 235 .reo1_aging_thres_ix1 = 0x00000b0c, 236 .reo1_aging_thres_ix2 = 0x00000b10, 237 .reo1_aging_thres_ix3 = 0x00000b14, 238 239 /* REO Exception ring address */ 240 .reo2_sw0_ring_base = 0x000008a4, 241 242 /* REO Reinject ring address */ 243 .sw2reo_ring_base = 0x00000304, 244 .sw2reo1_ring_base = 0x0000037c, 245 246 /* REO cmd ring address */ 247 .reo_cmd_ring_base = 0x0000028c, 248 249 /* REO status ring address */ 250 .reo_status_ring_base = 0x00000a84, 251 252 /* CE base address */ 253 .umac_ce0_src_reg_base = 0x01b80000, 254 .umac_ce0_dest_reg_base = 0x01b81000, 255 .umac_ce1_src_reg_base = 0x01b82000, 256 .umac_ce1_dest_reg_base = 0x01b83000, 257 258 .gcc_gcc_pcie_hot_rst = 0x1e40304, 259 260 .qrtr_node_id = 0x1e03164, 261 }; 262 263 static inline 264 bool ath12k_hal_rx_desc_get_first_msdu_wcn7850(struct hal_rx_desc *desc) 265 { 266 return !!le16_get_bits(desc->u.wcn7850.msdu_end.info5, 267 RX_MSDU_END_INFO5_FIRST_MSDU); 268 } 269 270 static inline 271 bool ath12k_hal_rx_desc_get_last_msdu_wcn7850(struct hal_rx_desc *desc) 272 { 273 return !!le16_get_bits(desc->u.wcn7850.msdu_end.info5, 274 RX_MSDU_END_INFO5_LAST_MSDU); 275 } 276 277 u8 ath12k_hal_rx_desc_get_l3_pad_bytes_wcn7850(struct hal_rx_desc *desc) 278 { 279 return le16_get_bits(desc->u.wcn7850.msdu_end.info5, 280 RX_MSDU_END_INFO5_L3_HDR_PADDING); 281 } 282 283 static inline 284 bool ath12k_hal_rx_desc_encrypt_valid_wcn7850(struct hal_rx_desc *desc) 285 { 286 return !!le32_get_bits(desc->u.wcn7850.mpdu_start.info4, 287 RX_MPDU_START_INFO4_ENCRYPT_INFO_VALID); 288 } 289 290 static inline 291 u32 ath12k_hal_rx_desc_get_encrypt_type_wcn7850(struct hal_rx_desc *desc) 292 { 293 if (!ath12k_hal_rx_desc_encrypt_valid_wcn7850(desc)) 294 return HAL_ENCRYPT_TYPE_OPEN; 295 296 return le32_get_bits(desc->u.wcn7850.mpdu_start.info2, 297 RX_MPDU_START_INFO2_ENC_TYPE); 298 } 299 300 static inline 301 u8 ath12k_hal_rx_desc_get_decap_type_wcn7850(struct hal_rx_desc *desc) 302 { 303 return le32_get_bits(desc->u.wcn7850.msdu_end.info11, 304 RX_MSDU_END_INFO11_DECAP_FORMAT); 305 } 306 307 static inline 308 u8 ath12k_hal_rx_desc_get_mesh_ctl_wcn7850(struct hal_rx_desc *desc) 309 { 310 return le32_get_bits(desc->u.wcn7850.msdu_end.info11, 311 RX_MSDU_END_INFO11_MESH_CTRL_PRESENT); 312 } 313 314 static inline 315 bool ath12k_hal_rx_desc_get_mpdu_seq_ctl_vld_wcn7850(struct hal_rx_desc *desc) 316 { 317 return !!le32_get_bits(desc->u.wcn7850.mpdu_start.info4, 318 RX_MPDU_START_INFO4_MPDU_SEQ_CTRL_VALID); 319 } 320 321 static inline 322 bool ath12k_hal_rx_desc_get_mpdu_fc_valid_wcn7850(struct hal_rx_desc *desc) 323 { 324 return !!le32_get_bits(desc->u.wcn7850.mpdu_start.info4, 325 RX_MPDU_START_INFO4_MPDU_FCTRL_VALID); 326 } 327 328 static inline 329 u16 ath12k_hal_rx_desc_get_mpdu_start_seq_no_wcn7850(struct hal_rx_desc *desc) 330 { 331 return le32_get_bits(desc->u.wcn7850.mpdu_start.info4, 332 RX_MPDU_START_INFO4_MPDU_SEQ_NUM); 333 } 334 335 static inline 336 u16 ath12k_hal_rx_desc_get_msdu_len_wcn7850(struct hal_rx_desc *desc) 337 { 338 return le32_get_bits(desc->u.wcn7850.msdu_end.info10, 339 RX_MSDU_END_INFO10_MSDU_LENGTH); 340 } 341 342 static inline 343 u8 ath12k_hal_rx_desc_get_msdu_sgi_wcn7850(struct hal_rx_desc *desc) 344 { 345 return le32_get_bits(desc->u.wcn7850.msdu_end.info12, 346 RX_MSDU_END_INFO12_SGI); 347 } 348 349 static inline 350 u8 ath12k_hal_rx_desc_get_msdu_rate_mcs_wcn7850(struct hal_rx_desc *desc) 351 { 352 return le32_get_bits(desc->u.wcn7850.msdu_end.info12, 353 RX_MSDU_END_INFO12_RATE_MCS); 354 } 355 356 static inline 357 u8 ath12k_hal_rx_desc_get_msdu_rx_bw_wcn7850(struct hal_rx_desc *desc) 358 { 359 return le32_get_bits(desc->u.wcn7850.msdu_end.info12, 360 RX_MSDU_END_INFO12_RECV_BW); 361 } 362 363 static inline 364 u32 ath12k_hal_rx_desc_get_msdu_freq_wcn7850(struct hal_rx_desc *desc) 365 { 366 return __le32_to_cpu(desc->u.wcn7850.msdu_end.phy_meta_data); 367 } 368 369 static inline 370 u8 ath12k_hal_rx_desc_get_msdu_pkt_type_wcn7850(struct hal_rx_desc *desc) 371 { 372 return le32_get_bits(desc->u.wcn7850.msdu_end.info12, 373 RX_MSDU_END_INFO12_PKT_TYPE); 374 } 375 376 static inline 377 u8 ath12k_hal_rx_desc_get_msdu_nss_wcn7850(struct hal_rx_desc *desc) 378 { 379 return le32_get_bits(desc->u.wcn7850.msdu_end.info12, 380 RX_MSDU_END_INFO12_MIMO_SS_BITMAP); 381 } 382 383 static inline 384 u8 ath12k_hal_rx_desc_get_mpdu_tid_wcn7850(struct hal_rx_desc *desc) 385 { 386 return le32_get_bits(desc->u.wcn7850.mpdu_start.info2, 387 RX_MPDU_START_INFO2_TID); 388 } 389 390 static inline 391 u16 ath12k_hal_rx_desc_get_mpdu_peer_id_wcn7850(struct hal_rx_desc *desc) 392 { 393 return __le16_to_cpu(desc->u.wcn7850.mpdu_start.sw_peer_id); 394 } 395 396 void ath12k_hal_rx_desc_copy_end_tlv_wcn7850(struct hal_rx_desc *fdesc, 397 struct hal_rx_desc *ldesc) 398 { 399 memcpy(&fdesc->u.wcn7850.msdu_end, &ldesc->u.wcn7850.msdu_end, 400 sizeof(struct rx_msdu_end_qcn9274)); 401 } 402 403 u32 ath12k_hal_rx_desc_get_mpdu_start_tag_wcn7850(struct hal_rx_desc *desc) 404 { 405 return le64_get_bits(desc->u.wcn7850.mpdu_start_tag, 406 HAL_TLV_HDR_TAG); 407 } 408 409 u32 ath12k_hal_rx_desc_get_mpdu_ppdu_id_wcn7850(struct hal_rx_desc *desc) 410 { 411 return __le16_to_cpu(desc->u.wcn7850.mpdu_start.phy_ppdu_id); 412 } 413 414 void ath12k_hal_rx_desc_set_msdu_len_wcn7850(struct hal_rx_desc *desc, u16 len) 415 { 416 u32 info = __le32_to_cpu(desc->u.wcn7850.msdu_end.info10); 417 418 info &= ~RX_MSDU_END_INFO10_MSDU_LENGTH; 419 info |= u32_encode_bits(len, RX_MSDU_END_INFO10_MSDU_LENGTH); 420 421 desc->u.wcn7850.msdu_end.info10 = __cpu_to_le32(info); 422 } 423 424 u8 *ath12k_hal_rx_desc_get_msdu_payload_wcn7850(struct hal_rx_desc *desc) 425 { 426 return &desc->u.wcn7850.msdu_payload[0]; 427 } 428 429 u32 ath12k_hal_rx_desc_get_mpdu_start_offset_wcn7850(void) 430 { 431 return offsetof(struct hal_rx_desc_wcn7850, mpdu_start_tag); 432 } 433 434 u32 ath12k_hal_rx_desc_get_msdu_end_offset_wcn7850(void) 435 { 436 return offsetof(struct hal_rx_desc_wcn7850, msdu_end_tag); 437 } 438 439 static inline 440 bool ath12k_hal_rx_desc_mac_addr2_valid_wcn7850(struct hal_rx_desc *desc) 441 { 442 return __le32_to_cpu(desc->u.wcn7850.mpdu_start.info4) & 443 RX_MPDU_START_INFO4_MAC_ADDR2_VALID; 444 } 445 446 static inline 447 u8 *ath12k_hal_rx_desc_mpdu_start_addr2_wcn7850(struct hal_rx_desc *desc) 448 { 449 return desc->u.wcn7850.mpdu_start.addr2; 450 } 451 452 static inline 453 bool ath12k_hal_rx_desc_is_da_mcbc_wcn7850(struct hal_rx_desc *desc) 454 { 455 return __le32_to_cpu(desc->u.wcn7850.msdu_end.info13) & 456 RX_MSDU_END_INFO13_MCAST_BCAST; 457 } 458 459 static inline 460 bool ath12k_hal_rx_h_msdu_done_wcn7850(struct hal_rx_desc *desc) 461 { 462 return !!le32_get_bits(desc->u.wcn7850.msdu_end.info14, 463 RX_MSDU_END_INFO14_MSDU_DONE); 464 } 465 466 static inline 467 bool ath12k_hal_rx_h_l4_cksum_fail_wcn7850(struct hal_rx_desc *desc) 468 { 469 return !!le32_get_bits(desc->u.wcn7850.msdu_end.info13, 470 RX_MSDU_END_INFO13_TCP_UDP_CKSUM_FAIL); 471 } 472 473 static inline 474 bool ath12k_hal_rx_h_ip_cksum_fail_wcn7850(struct hal_rx_desc *desc) 475 { 476 return !!le32_get_bits(desc->u.wcn7850.msdu_end.info13, 477 RX_MSDU_END_INFO13_IP_CKSUM_FAIL); 478 } 479 480 static inline 481 bool ath12k_hal_rx_h_is_decrypted_wcn7850(struct hal_rx_desc *desc) 482 { 483 return (le32_get_bits(desc->u.wcn7850.msdu_end.info14, 484 RX_MSDU_END_INFO14_DECRYPT_STATUS_CODE) == 485 RX_DESC_DECRYPT_STATUS_CODE_OK); 486 } 487 488 u32 ath12k_hal_get_rx_desc_size_wcn7850(void) 489 { 490 return sizeof(struct hal_rx_desc_wcn7850); 491 } 492 493 u8 ath12k_hal_rx_desc_get_msdu_src_link_wcn7850(struct hal_rx_desc *desc) 494 { 495 return 0; 496 } 497 498 static u32 ath12k_hal_rx_h_mpdu_err_wcn7850(struct hal_rx_desc *desc) 499 { 500 u32 info = __le32_to_cpu(desc->u.wcn7850.msdu_end.info13); 501 u32 errmap = 0; 502 503 if (info & RX_MSDU_END_INFO13_FCS_ERR) 504 errmap |= HAL_RX_MPDU_ERR_FCS; 505 506 if (info & RX_MSDU_END_INFO13_DECRYPT_ERR) 507 errmap |= HAL_RX_MPDU_ERR_DECRYPT; 508 509 if (info & RX_MSDU_END_INFO13_TKIP_MIC_ERR) 510 errmap |= HAL_RX_MPDU_ERR_TKIP_MIC; 511 512 if (info & RX_MSDU_END_INFO13_A_MSDU_ERROR) 513 errmap |= HAL_RX_MPDU_ERR_AMSDU_ERR; 514 515 if (info & RX_MSDU_END_INFO13_OVERFLOW_ERR) 516 errmap |= HAL_RX_MPDU_ERR_OVERFLOW; 517 518 if (info & RX_MSDU_END_INFO13_MSDU_LEN_ERR) 519 errmap |= HAL_RX_MPDU_ERR_MSDU_LEN; 520 521 if (info & RX_MSDU_END_INFO13_MPDU_LEN_ERR) 522 errmap |= HAL_RX_MPDU_ERR_MPDU_LEN; 523 524 return errmap; 525 } 526 527 void ath12k_hal_rx_desc_get_crypto_hdr_wcn7850(struct hal_rx_desc *desc, 528 u8 *crypto_hdr, 529 enum hal_encrypt_type enctype) 530 { 531 unsigned int key_id; 532 533 switch (enctype) { 534 case HAL_ENCRYPT_TYPE_OPEN: 535 return; 536 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 537 case HAL_ENCRYPT_TYPE_TKIP_MIC: 538 crypto_hdr[0] = 539 HAL_RX_MPDU_INFO_PN_GET_BYTE2(desc->u.wcn7850.mpdu_start.pn[0]); 540 crypto_hdr[1] = 0; 541 crypto_hdr[2] = 542 HAL_RX_MPDU_INFO_PN_GET_BYTE1(desc->u.wcn7850.mpdu_start.pn[0]); 543 break; 544 case HAL_ENCRYPT_TYPE_CCMP_128: 545 case HAL_ENCRYPT_TYPE_CCMP_256: 546 case HAL_ENCRYPT_TYPE_GCMP_128: 547 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 548 crypto_hdr[0] = 549 HAL_RX_MPDU_INFO_PN_GET_BYTE1(desc->u.wcn7850.mpdu_start.pn[0]); 550 crypto_hdr[1] = 551 HAL_RX_MPDU_INFO_PN_GET_BYTE2(desc->u.wcn7850.mpdu_start.pn[0]); 552 crypto_hdr[2] = 0; 553 break; 554 case HAL_ENCRYPT_TYPE_WEP_40: 555 case HAL_ENCRYPT_TYPE_WEP_104: 556 case HAL_ENCRYPT_TYPE_WEP_128: 557 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 558 case HAL_ENCRYPT_TYPE_WAPI: 559 return; 560 } 561 key_id = u32_get_bits(__le32_to_cpu(desc->u.wcn7850.mpdu_start.info5), 562 RX_MPDU_START_INFO5_KEY_ID); 563 crypto_hdr[3] = 0x20 | (key_id << 6); 564 crypto_hdr[4] = HAL_RX_MPDU_INFO_PN_GET_BYTE3(desc->u.wcn7850.mpdu_start.pn[0]); 565 crypto_hdr[5] = HAL_RX_MPDU_INFO_PN_GET_BYTE4(desc->u.wcn7850.mpdu_start.pn[0]); 566 crypto_hdr[6] = HAL_RX_MPDU_INFO_PN_GET_BYTE1(desc->u.wcn7850.mpdu_start.pn[1]); 567 crypto_hdr[7] = HAL_RX_MPDU_INFO_PN_GET_BYTE2(desc->u.wcn7850.mpdu_start.pn[1]); 568 } 569 570 void ath12k_hal_rx_desc_get_dot11_hdr_wcn7850(struct hal_rx_desc *desc, 571 struct ieee80211_hdr *hdr) 572 { 573 hdr->frame_control = desc->u.wcn7850.mpdu_start.frame_ctrl; 574 hdr->duration_id = desc->u.wcn7850.mpdu_start.duration; 575 ether_addr_copy(hdr->addr1, desc->u.wcn7850.mpdu_start.addr1); 576 ether_addr_copy(hdr->addr2, desc->u.wcn7850.mpdu_start.addr2); 577 ether_addr_copy(hdr->addr3, desc->u.wcn7850.mpdu_start.addr3); 578 if (__le32_to_cpu(desc->u.wcn7850.mpdu_start.info4) & 579 RX_MPDU_START_INFO4_MAC_ADDR4_VALID) { 580 ether_addr_copy(hdr->addr4, desc->u.wcn7850.mpdu_start.addr4); 581 } 582 hdr->seq_ctrl = desc->u.wcn7850.mpdu_start.seq_ctrl; 583 } 584 585 void ath12k_hal_extract_rx_desc_data_wcn7850(struct hal_rx_desc_data *rx_desc_data, 586 struct hal_rx_desc *rx_desc, 587 struct hal_rx_desc *ldesc) 588 { 589 rx_desc_data->is_first_msdu = ath12k_hal_rx_desc_get_first_msdu_wcn7850(ldesc); 590 rx_desc_data->is_last_msdu = ath12k_hal_rx_desc_get_last_msdu_wcn7850(ldesc); 591 rx_desc_data->l3_pad_bytes = ath12k_hal_rx_desc_get_l3_pad_bytes_wcn7850(ldesc); 592 rx_desc_data->enctype = ath12k_hal_rx_desc_get_encrypt_type_wcn7850(rx_desc); 593 rx_desc_data->decap_type = ath12k_hal_rx_desc_get_decap_type_wcn7850(rx_desc); 594 rx_desc_data->mesh_ctrl_present = 595 ath12k_hal_rx_desc_get_mesh_ctl_wcn7850(rx_desc); 596 rx_desc_data->seq_ctl_valid = 597 ath12k_hal_rx_desc_get_mpdu_seq_ctl_vld_wcn7850(rx_desc); 598 rx_desc_data->fc_valid = ath12k_hal_rx_desc_get_mpdu_fc_valid_wcn7850(rx_desc); 599 rx_desc_data->seq_no = ath12k_hal_rx_desc_get_mpdu_start_seq_no_wcn7850(rx_desc); 600 rx_desc_data->msdu_len = ath12k_hal_rx_desc_get_msdu_len_wcn7850(ldesc); 601 rx_desc_data->sgi = ath12k_hal_rx_desc_get_msdu_sgi_wcn7850(rx_desc); 602 rx_desc_data->rate_mcs = ath12k_hal_rx_desc_get_msdu_rate_mcs_wcn7850(rx_desc); 603 rx_desc_data->bw = ath12k_hal_rx_desc_get_msdu_rx_bw_wcn7850(rx_desc); 604 rx_desc_data->phy_meta_data = ath12k_hal_rx_desc_get_msdu_freq_wcn7850(rx_desc); 605 rx_desc_data->pkt_type = ath12k_hal_rx_desc_get_msdu_pkt_type_wcn7850(rx_desc); 606 rx_desc_data->nss = hweight8(ath12k_hal_rx_desc_get_msdu_nss_wcn7850(rx_desc)); 607 rx_desc_data->tid = ath12k_hal_rx_desc_get_mpdu_tid_wcn7850(rx_desc); 608 rx_desc_data->peer_id = ath12k_hal_rx_desc_get_mpdu_peer_id_wcn7850(rx_desc); 609 rx_desc_data->addr2_present = ath12k_hal_rx_desc_mac_addr2_valid_wcn7850(rx_desc); 610 rx_desc_data->addr2 = ath12k_hal_rx_desc_mpdu_start_addr2_wcn7850(rx_desc); 611 rx_desc_data->is_mcbc = ath12k_hal_rx_desc_is_da_mcbc_wcn7850(rx_desc); 612 rx_desc_data->msdu_done = ath12k_hal_rx_h_msdu_done_wcn7850(ldesc); 613 rx_desc_data->l4_csum_fail = ath12k_hal_rx_h_l4_cksum_fail_wcn7850(rx_desc); 614 rx_desc_data->ip_csum_fail = ath12k_hal_rx_h_ip_cksum_fail_wcn7850(rx_desc); 615 rx_desc_data->is_decrypted = ath12k_hal_rx_h_is_decrypted_wcn7850(rx_desc); 616 rx_desc_data->err_bitmap = ath12k_hal_rx_h_mpdu_err_wcn7850(rx_desc); 617 } 618 619 int ath12k_hal_srng_create_config_wcn7850(struct ath12k_hal *hal) 620 { 621 struct hal_srng_config *s; 622 623 hal->srng_config = kmemdup(hw_srng_config_template, 624 sizeof(hw_srng_config_template), 625 GFP_KERNEL); 626 if (!hal->srng_config) 627 return -ENOMEM; 628 629 s = &hal->srng_config[HAL_REO_DST]; 630 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_BASE_LSB(hal); 631 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_HP; 632 s->reg_size[0] = HAL_REO2_RING_BASE_LSB(hal) - HAL_REO1_RING_BASE_LSB(hal); 633 s->reg_size[1] = HAL_REO2_RING_HP - HAL_REO1_RING_HP; 634 635 s = &hal->srng_config[HAL_REO_EXCEPTION]; 636 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_SW0_RING_BASE_LSB(hal); 637 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_SW0_RING_HP; 638 639 s = &hal->srng_config[HAL_REO_REINJECT]; 640 s->max_rings = 1; 641 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_BASE_LSB(hal); 642 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_HP; 643 644 s = &hal->srng_config[HAL_REO_CMD]; 645 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_RING_BASE_LSB(hal); 646 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_HP; 647 648 s = &hal->srng_config[HAL_REO_STATUS]; 649 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_RING_BASE_LSB(hal); 650 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_HP; 651 652 s = &hal->srng_config[HAL_TCL_DATA]; 653 s->max_rings = 5; 654 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_BASE_LSB(hal); 655 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_HP; 656 s->reg_size[0] = HAL_TCL2_RING_BASE_LSB(hal) - HAL_TCL1_RING_BASE_LSB(hal); 657 s->reg_size[1] = HAL_TCL2_RING_HP - HAL_TCL1_RING_HP; 658 659 s = &hal->srng_config[HAL_TCL_CMD]; 660 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_BASE_LSB(hal); 661 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_HP; 662 663 s = &hal->srng_config[HAL_TCL_STATUS]; 664 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_BASE_LSB(hal); 665 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_HP; 666 667 s = &hal->srng_config[HAL_CE_SRC]; 668 s->max_rings = 12; 669 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(hal) + HAL_CE_DST_RING_BASE_LSB; 670 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(hal) + HAL_CE_DST_RING_HP; 671 s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(hal) - 672 HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(hal); 673 s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(hal) - 674 HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(hal); 675 676 s = &hal->srng_config[HAL_CE_DST]; 677 s->max_rings = 12; 678 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal) + HAL_CE_DST_RING_BASE_LSB; 679 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal) + HAL_CE_DST_RING_HP; 680 s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(hal) - 681 HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal); 682 s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(hal) - 683 HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal); 684 685 s = &hal->srng_config[HAL_CE_DST_STATUS]; 686 s->max_rings = 12; 687 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal) + 688 HAL_CE_DST_STATUS_RING_BASE_LSB; 689 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal) + HAL_CE_DST_STATUS_RING_HP; 690 s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(hal) - 691 HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal); 692 s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(hal) - 693 HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal); 694 695 s = &hal->srng_config[HAL_WBM_IDLE_LINK]; 696 s->reg_start[0] = 697 HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_BASE_LSB(hal); 698 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_HP; 699 700 s = &hal->srng_config[HAL_SW2WBM_RELEASE]; 701 s->max_rings = 1; 702 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + 703 HAL_WBM_SW_RELEASE_RING_BASE_LSB(hal); 704 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SW_RELEASE_RING_HP; 705 706 s = &hal->srng_config[HAL_WBM2SW_RELEASE]; 707 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_BASE_LSB(hal); 708 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_HP; 709 s->reg_size[0] = HAL_WBM1_RELEASE_RING_BASE_LSB(hal) - 710 HAL_WBM0_RELEASE_RING_BASE_LSB(hal); 711 s->reg_size[1] = HAL_WBM1_RELEASE_RING_HP - HAL_WBM0_RELEASE_RING_HP; 712 713 s = &hal->srng_config[HAL_RXDMA_BUF]; 714 s->max_rings = 2; 715 s->mac_type = ATH12K_HAL_SRNG_PMAC; 716 717 s = &hal->srng_config[HAL_RXDMA_DST]; 718 s->max_rings = 1; 719 s->entry_size = sizeof(struct hal_reo_entrance_ring) >> 2; 720 721 /* below rings are not used */ 722 s = &hal->srng_config[HAL_RXDMA_DIR_BUF]; 723 s->max_rings = 0; 724 725 s = &hal->srng_config[HAL_PPE2TCL]; 726 s->max_rings = 0; 727 728 s = &hal->srng_config[HAL_PPE_RELEASE]; 729 s->max_rings = 0; 730 731 s = &hal->srng_config[HAL_TX_MONITOR_BUF]; 732 s->max_rings = 0; 733 734 s = &hal->srng_config[HAL_TX_MONITOR_DST]; 735 s->max_rings = 0; 736 737 s = &hal->srng_config[HAL_PPE2TCL]; 738 s->max_rings = 0; 739 740 return 0; 741 } 742 743 const struct ath12k_hal_tcl_to_wbm_rbm_map 744 ath12k_hal_tcl_to_wbm_rbm_map_wcn7850[DP_TCL_NUM_RING_MAX] = { 745 { 746 .wbm_ring_num = 0, 747 .rbm_id = HAL_RX_BUF_RBM_SW0_BM, 748 }, 749 { 750 .wbm_ring_num = 2, 751 .rbm_id = HAL_RX_BUF_RBM_SW2_BM, 752 }, 753 { 754 .wbm_ring_num = 4, 755 .rbm_id = HAL_RX_BUF_RBM_SW4_BM, 756 }, 757 }; 758 759 const struct ath12k_hw_hal_params ath12k_hw_hal_params_wcn7850 = { 760 .rx_buf_rbm = HAL_RX_BUF_RBM_SW1_BM, 761 .wbm2sw_cc_enable = HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN | 762 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN | 763 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN | 764 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN, 765 }; 766 767 const struct hal_ops hal_wcn7850_ops = { 768 .create_srng_config = ath12k_hal_srng_create_config_wcn7850, 769 .rx_desc_set_msdu_len = ath12k_hal_rx_desc_set_msdu_len_wcn7850, 770 .rx_desc_get_dot11_hdr = ath12k_hal_rx_desc_get_dot11_hdr_wcn7850, 771 .rx_desc_get_crypto_header = ath12k_hal_rx_desc_get_crypto_hdr_wcn7850, 772 .rx_desc_copy_end_tlv = ath12k_hal_rx_desc_copy_end_tlv_wcn7850, 773 .rx_desc_get_msdu_src_link_id = ath12k_hal_rx_desc_get_msdu_src_link_wcn7850, 774 .extract_rx_desc_data = ath12k_hal_extract_rx_desc_data_wcn7850, 775 .rx_desc_get_l3_pad_bytes = ath12k_hal_rx_desc_get_l3_pad_bytes_wcn7850, 776 .rx_desc_get_mpdu_start_tag = ath12k_hal_rx_desc_get_mpdu_start_tag_wcn7850, 777 .rx_desc_get_mpdu_ppdu_id = ath12k_hal_rx_desc_get_mpdu_ppdu_id_wcn7850, 778 .rx_desc_get_msdu_payload = ath12k_hal_rx_desc_get_msdu_payload_wcn7850, 779 .ce_dst_setup = ath12k_wifi7_hal_ce_dst_setup, 780 .srng_src_hw_init = ath12k_wifi7_hal_srng_src_hw_init, 781 .srng_dst_hw_init = ath12k_wifi7_hal_srng_dst_hw_init, 782 .set_umac_srng_ptr_addr = ath12k_wifi7_hal_set_umac_srng_ptr_addr, 783 .srng_update_shadow_config = ath12k_wifi7_hal_srng_update_shadow_config, 784 .srng_get_ring_id = ath12k_wifi7_hal_srng_get_ring_id, 785 .ce_get_desc_size = ath12k_wifi7_hal_ce_get_desc_size, 786 .ce_src_set_desc = ath12k_wifi7_hal_ce_src_set_desc, 787 .ce_dst_set_desc = ath12k_wifi7_hal_ce_dst_set_desc, 788 .ce_dst_status_get_length = ath12k_wifi7_hal_ce_dst_status_get_length, 789 .set_link_desc_addr = ath12k_wifi7_hal_set_link_desc_addr, 790 .tx_set_dscp_tid_map = ath12k_wifi7_hal_tx_set_dscp_tid_map, 791 .tx_configure_bank_register = 792 ath12k_wifi7_hal_tx_configure_bank_register, 793 .reoq_lut_addr_read_enable = ath12k_wifi7_hal_reoq_lut_addr_read_enable, 794 .reoq_lut_set_max_peerid = ath12k_wifi7_hal_reoq_lut_set_max_peerid, 795 .write_reoq_lut_addr = ath12k_wifi7_hal_write_reoq_lut_addr, 796 .write_ml_reoq_lut_addr = ath12k_wifi7_hal_write_ml_reoq_lut_addr, 797 .setup_link_idle_list = ath12k_wifi7_hal_setup_link_idle_list, 798 .reo_init_cmd_ring = ath12k_wifi7_hal_reo_init_cmd_ring_tlv64, 799 .reo_shared_qaddr_cache_clear = ath12k_wifi7_hal_reo_shared_qaddr_cache_clear, 800 .reo_hw_setup = ath12k_wifi7_hal_reo_hw_setup, 801 .rx_buf_addr_info_set = ath12k_wifi7_hal_rx_buf_addr_info_set, 802 .rx_buf_addr_info_get = ath12k_wifi7_hal_rx_buf_addr_info_get, 803 .cc_config = ath12k_wifi7_hal_cc_config, 804 .get_idle_link_rbm = ath12k_wifi7_hal_get_idle_link_rbm, 805 .rx_msdu_list_get = ath12k_wifi7_hal_rx_msdu_list_get, 806 .rx_reo_ent_buf_paddr_get = ath12k_wifi7_hal_rx_reo_ent_buf_paddr_get, 807 .reo_cmd_enc_tlv_hdr = ath12k_hal_encode_tlv64_hdr, 808 .reo_status_dec_tlv_hdr = ath12k_hal_decode_tlv64_hdr, 809 }; 810