1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #ifndef ATH12K_HAL_TX_H 8 #define ATH12K_HAL_TX_H 9 10 #include "../mac.h" 11 #include "hal_desc.h" 12 13 /* TODO: check all these data can be managed with struct ath12k_tx_desc_info for perf */ 14 struct hal_tx_info { 15 u16 meta_data_flags; /* %HAL_TCL_DATA_CMD_INFO0_META_ */ 16 u8 ring_id; 17 u8 rbm_id; 18 u32 desc_id; 19 enum hal_tcl_desc_type type; 20 enum hal_tcl_encap_type encap_type; 21 dma_addr_t paddr; 22 u32 data_len; 23 u32 pkt_offset; 24 enum hal_encrypt_type encrypt_type; 25 u32 flags0; /* %HAL_TCL_DATA_CMD_INFO1_ */ 26 u32 flags1; /* %HAL_TCL_DATA_CMD_INFO2_ */ 27 u16 addr_search_flags; /* %HAL_TCL_DATA_CMD_INFO0_ADDR(X/Y)_ */ 28 u16 bss_ast_hash; 29 u16 bss_ast_idx; 30 u8 tid; 31 u8 search_type; /* %HAL_TX_ADDR_SEARCH_ */ 32 u8 lmac_id; 33 u8 vdev_id; 34 u8 dscp_tid_tbl_idx; 35 bool enable_mesh; 36 int bank_id; 37 }; 38 39 /* TODO: Check if the actual desc macros can be used instead */ 40 #define HAL_TX_STATUS_FLAGS_FIRST_MSDU BIT(0) 41 #define HAL_TX_STATUS_FLAGS_LAST_MSDU BIT(1) 42 #define HAL_TX_STATUS_FLAGS_MSDU_IN_AMSDU BIT(2) 43 #define HAL_TX_STATUS_FLAGS_RATE_STATS_VALID BIT(3) 44 #define HAL_TX_STATUS_FLAGS_RATE_LDPC BIT(4) 45 #define HAL_TX_STATUS_FLAGS_RATE_STBC BIT(5) 46 #define HAL_TX_STATUS_FLAGS_OFDMA BIT(6) 47 48 #define HAL_TX_STATUS_DESC_LEN sizeof(struct hal_wbm_release_ring) 49 50 /* Tx status parsed from srng desc */ 51 struct hal_tx_status { 52 enum hal_wbm_rel_src_module buf_rel_source; 53 enum hal_wbm_tqm_rel_reason status; 54 s8 ack_rssi; 55 u32 flags; /* %HAL_TX_STATUS_FLAGS_ */ 56 u32 ppdu_id; 57 u8 try_cnt; 58 u8 tid; 59 u16 peer_id; 60 enum hal_tx_rate_stats_pkt_type pkt_type; 61 enum hal_tx_rate_stats_sgi sgi; 62 enum ath12k_supported_bw bw; 63 u8 mcs; 64 u16 tones; 65 u8 ofdma; 66 }; 67 68 #define HAL_TX_PHY_DESC_INFO0_BF_TYPE GENMASK(17, 16) 69 #define HAL_TX_PHY_DESC_INFO0_PREAMBLE_11B BIT(20) 70 #define HAL_TX_PHY_DESC_INFO0_PKT_TYPE GENMASK(24, 21) 71 #define HAL_TX_PHY_DESC_INFO0_BANDWIDTH GENMASK(30, 28) 72 #define HAL_TX_PHY_DESC_INFO1_MCS GENMASK(3, 0) 73 #define HAL_TX_PHY_DESC_INFO1_STBC BIT(6) 74 #define HAL_TX_PHY_DESC_INFO2_NSS GENMASK(23, 21) 75 #define HAL_TX_PHY_DESC_INFO3_AP_PKT_BW GENMASK(6, 4) 76 #define HAL_TX_PHY_DESC_INFO3_LTF_SIZE GENMASK(20, 19) 77 #define HAL_TX_PHY_DESC_INFO3_ACTIVE_CHANNEL GENMASK(17, 15) 78 79 struct hal_tx_phy_desc { 80 __le32 info0; 81 __le32 info1; 82 __le32 info2; 83 __le32 info3; 84 } __packed; 85 86 #define HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_15_0 GENMASK(15, 0) 87 #define HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_31_16 GENMASK(31, 16) 88 #define HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_15_0 GENMASK(15, 0) 89 #define HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_31_16 GENMASK(31, 16) 90 91 struct hal_tx_fes_status_prot { 92 __le64 reserved; 93 __le32 info0; 94 __le32 info1; 95 __le32 reserved1[11]; 96 } __packed; 97 98 #define HAL_TX_FES_STAT_USR_PPDU_INFO0_DURATION GENMASK(15, 0) 99 100 struct hal_tx_fes_status_user_ppdu { 101 __le64 reserved; 102 __le32 info0; 103 __le32 reserved1[3]; 104 } __packed; 105 106 #define HAL_TX_FES_STAT_STRT_INFO0_PROT_TS_LOWER_32 GENMASK(31, 0) 107 #define HAL_TX_FES_STAT_STRT_INFO1_PROT_TS_UPPER_32 GENMASK(31, 0) 108 109 struct hal_tx_fes_status_start_prot { 110 __le32 info0; 111 __le32 info1; 112 __le64 reserved; 113 } __packed; 114 115 #define HAL_TX_FES_STATUS_START_INFO0_MEDIUM_PROT_TYPE GENMASK(29, 27) 116 117 struct hal_tx_fes_status_start { 118 __le32 reserved; 119 __le32 info0; 120 __le64 reserved1; 121 } __packed; 122 123 #define HAL_TX_Q_EXT_INFO0_FRAME_CTRL GENMASK(15, 0) 124 #define HAL_TX_Q_EXT_INFO0_QOS_CTRL GENMASK(31, 16) 125 #define HAL_TX_Q_EXT_INFO1_AMPDU_FLAG BIT(0) 126 127 struct hal_tx_queue_exten { 128 __le32 info0; 129 __le32 info1; 130 } __packed; 131 132 #define HAL_TX_FES_SETUP_INFO0_NUM_OF_USERS GENMASK(28, 23) 133 134 struct hal_tx_fes_setup { 135 __le32 schedule_id; 136 __le32 info0; 137 __le64 reserved; 138 } __packed; 139 140 #define HAL_TX_PPDU_SETUP_INFO0_MEDIUM_PROT_TYPE GENMASK(2, 0) 141 #define HAL_TX_PPDU_SETUP_INFO1_PROT_FRAME_ADDR1_31_0 GENMASK(31, 0) 142 #define HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR1_47_32 GENMASK(15, 0) 143 #define HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR2_15_0 GENMASK(31, 16) 144 #define HAL_TX_PPDU_SETUP_INFO3_PROT_FRAME_ADDR2_47_16 GENMASK(31, 0) 145 #define HAL_TX_PPDU_SETUP_INFO4_PROT_FRAME_ADDR3_31_0 GENMASK(31, 0) 146 #define HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR3_47_32 GENMASK(15, 0) 147 #define HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR4_15_0 GENMASK(31, 16) 148 #define HAL_TX_PPDU_SETUP_INFO6_PROT_FRAME_ADDR4_47_16 GENMASK(31, 0) 149 150 struct hal_tx_pcu_ppdu_setup_init { 151 __le32 info0; 152 __le32 info1; 153 __le32 info2; 154 __le32 info3; 155 __le32 reserved; 156 __le32 info4; 157 __le32 info5; 158 __le32 info6; 159 } __packed; 160 161 #define HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_15_0 GENMASK(15, 0) 162 #define HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_31_16 GENMASK(31, 16) 163 164 struct hal_tx_fes_status_end { 165 __le32 reserved[2]; 166 __le32 info0; 167 __le32 reserved1[19]; 168 } __packed; 169 170 #define HAL_TX_BANK_CONFIG_EPD BIT(0) 171 #define HAL_TX_BANK_CONFIG_ENCAP_TYPE GENMASK(2, 1) 172 #define HAL_TX_BANK_CONFIG_ENCRYPT_TYPE GENMASK(6, 3) 173 #define HAL_TX_BANK_CONFIG_SRC_BUFFER_SWAP BIT(7) 174 #define HAL_TX_BANK_CONFIG_LINK_META_SWAP BIT(8) 175 #define HAL_TX_BANK_CONFIG_INDEX_LOOKUP_EN BIT(9) 176 #define HAL_TX_BANK_CONFIG_ADDRX_EN BIT(10) 177 #define HAL_TX_BANK_CONFIG_ADDRY_EN BIT(11) 178 #define HAL_TX_BANK_CONFIG_MESH_EN GENMASK(13, 12) 179 #define HAL_TX_BANK_CONFIG_VDEV_ID_CHECK_EN BIT(14) 180 #define HAL_TX_BANK_CONFIG_PMAC_ID GENMASK(16, 15) 181 /* STA mode will have MCAST_PKT_CTRL instead of DSCP_TID_MAP bitfield */ 182 #define HAL_TX_BANK_CONFIG_DSCP_TIP_MAP_ID GENMASK(22, 17) 183 184 void ath12k_wifi7_hal_tx_set_dscp_tid_map(struct ath12k_base *ab, int id); 185 void ath12k_wifi7_hal_tx_cmd_desc_setup(struct ath12k_base *ab, 186 struct hal_tcl_data_cmd *tcl_cmd, 187 struct hal_tx_info *ti); 188 int ath12k_wifi7_hal_reo_cmd_send(struct ath12k_base *ab, struct hal_srng *srng, 189 enum hal_reo_cmd_type type, 190 struct ath12k_hal_reo_cmd *cmd); 191 void ath12k_wifi7_hal_tx_configure_bank_register(struct ath12k_base *ab, 192 u32 bank_config, 193 u8 bank_id); 194 #endif 195