1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #include "../debug.h" 8 #include "../hal.h" 9 #include "../hif.h" 10 #include "hal_tx.h" 11 #include "hal_rx.h" 12 #include "hal_desc.h" 13 #include "hal.h" 14 15 static 16 void ath12k_wifi7_hal_reo_set_desc_hdr(struct hal_desc_header *hdr, 17 u8 owner, u8 buffer_type, u32 magic) 18 { 19 hdr->info0 = le32_encode_bits(owner, HAL_DESC_HDR_INFO0_OWNER) | 20 le32_encode_bits(buffer_type, HAL_DESC_HDR_INFO0_BUF_TYPE); 21 22 /* Magic pattern in reserved bits for debugging */ 23 hdr->info0 |= le32_encode_bits(magic, HAL_DESC_HDR_INFO0_DBG_RESERVED); 24 } 25 26 static int ath12k_wifi7_hal_reo_cmd_queue_stats(struct ath12k_hal *hal, void *tlv, 27 struct ath12k_hal_reo_cmd *cmd) 28 { 29 struct hal_reo_get_queue_stats *desc; 30 31 desc = hal->ops->reo_cmd_enc_tlv_hdr(tlv, HAL_REO_GET_QUEUE_STATS, 32 sizeof(*desc)); 33 memset_startat(desc, 0, queue_addr_lo); 34 35 desc->cmd.info0 &= ~cpu_to_le32(HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED); 36 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS) 37 desc->cmd.info0 |= cpu_to_le32(HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED); 38 39 desc->queue_addr_lo = cpu_to_le32(cmd->addr_lo); 40 desc->info0 = le32_encode_bits(cmd->addr_hi, 41 HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI); 42 if (cmd->flag & HAL_REO_CMD_FLG_STATS_CLEAR) 43 desc->info0 |= cpu_to_le32(HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS); 44 45 return le32_get_bits(desc->cmd.info0, HAL_REO_CMD_HDR_INFO0_CMD_NUMBER); 46 } 47 48 static int ath12k_wifi7_hal_reo_cmd_flush_cache(struct ath12k_hal *hal, void *tlv, 49 struct ath12k_hal_reo_cmd *cmd) 50 { 51 struct hal_reo_flush_cache *desc; 52 u8 avail_slot = ffz(hal->avail_blk_resource); 53 54 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER) { 55 if (avail_slot >= HAL_MAX_AVAIL_BLK_RES) 56 return -ENOSPC; 57 58 hal->current_blk_index = avail_slot; 59 } 60 61 desc = hal->ops->reo_cmd_enc_tlv_hdr(tlv, HAL_REO_FLUSH_CACHE, 62 sizeof(*desc)); 63 memset_startat(desc, 0, cache_addr_lo); 64 65 desc->cmd.info0 &= ~cpu_to_le32(HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED); 66 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS) 67 desc->cmd.info0 |= cpu_to_le32(HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED); 68 69 desc->cache_addr_lo = cpu_to_le32(cmd->addr_lo); 70 desc->info0 = le32_encode_bits(cmd->addr_hi, 71 HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI); 72 73 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS) 74 desc->info0 |= cpu_to_le32(HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS); 75 76 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER) { 77 desc->info0 |= cpu_to_le32(HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE); 78 desc->info0 |= 79 le32_encode_bits(avail_slot, 80 HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX); 81 } 82 83 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_NO_INVAL) 84 desc->info0 |= cpu_to_le32(HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE); 85 86 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_ALL) 87 desc->info0 |= cpu_to_le32(HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL); 88 89 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_QUEUE_1K_DESC) 90 desc->info0 |= cpu_to_le32(HAL_REO_FLUSH_CACHE_INFO0_FLUSH_QUEUE_1K_DESC); 91 92 return le32_get_bits(desc->cmd.info0, HAL_REO_CMD_HDR_INFO0_CMD_NUMBER); 93 } 94 95 static int 96 ath12k_wifi7_hal_reo_cmd_update_rx_queue(struct ath12k_hal *hal, void *tlv, 97 struct ath12k_hal_reo_cmd *cmd) 98 { 99 struct hal_reo_update_rx_queue *desc; 100 101 desc = hal->ops->reo_cmd_enc_tlv_hdr(tlv, HAL_REO_UPDATE_RX_REO_QUEUE, 102 sizeof(*desc)); 103 memset_startat(desc, 0, queue_addr_lo); 104 105 desc->cmd.info0 &= ~cpu_to_le32(HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED); 106 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS) 107 desc->cmd.info0 |= cpu_to_le32(HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED); 108 109 desc->queue_addr_lo = cpu_to_le32(cmd->addr_lo); 110 desc->info0 = 111 le32_encode_bits(cmd->addr_hi, 112 HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI) | 113 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_RX_QUEUE_NUM), 114 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RX_QUEUE_NUM) | 115 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_VLD), 116 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_VLD) | 117 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_ALDC), 118 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_ASSOC_LNK_DESC_CNT) | 119 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_DIS_DUP_DETECTION), 120 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_DIS_DUP_DETECTION) | 121 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_SOFT_REORDER_EN), 122 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SOFT_REORDER_EN) | 123 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_AC), 124 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC) | 125 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_BAR), 126 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BAR) | 127 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_RETRY), 128 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RETRY) | 129 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_CHECK_2K_MODE), 130 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_CHECK_2K_MODE) | 131 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_OOR_MODE), 132 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_OOR_MODE) | 133 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_BA_WINDOW_SIZE), 134 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BA_WINDOW_SIZE) | 135 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_CHECK), 136 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_CHECK) | 137 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_EVEN_PN), 138 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_EVEN_PN) | 139 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_UNEVEN_PN), 140 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_UNEVEN_PN) | 141 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE), 142 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_HANDLE_ENABLE) | 143 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_SIZE), 144 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_SIZE) | 145 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG), 146 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_IGNORE_AMPDU_FLG) | 147 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_SVLD), 148 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SVLD) | 149 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_SSN), 150 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SSN) | 151 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_SEQ_2K_ERR), 152 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SEQ_2K_ERR) | 153 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_VALID), 154 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_VALID) | 155 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_PN), 156 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN); 157 158 desc->info1 = 159 le32_encode_bits(cmd->rx_queue_num, 160 HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER) | 161 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_VLD), 162 HAL_REO_UPD_RX_QUEUE_INFO1_VLD) | 163 le32_encode_bits(u32_get_bits(cmd->upd1, HAL_REO_CMD_UPD1_ALDC), 164 HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER) | 165 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_DIS_DUP_DETECTION), 166 HAL_REO_UPD_RX_QUEUE_INFO1_DIS_DUP_DETECTION) | 167 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_SOFT_REORDER_EN), 168 HAL_REO_UPD_RX_QUEUE_INFO1_SOFT_REORDER_EN) | 169 le32_encode_bits(u32_get_bits(cmd->upd1, HAL_REO_CMD_UPD1_AC), 170 HAL_REO_UPD_RX_QUEUE_INFO1_AC) | 171 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_BAR), 172 HAL_REO_UPD_RX_QUEUE_INFO1_BAR) | 173 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_CHECK_2K_MODE), 174 HAL_REO_UPD_RX_QUEUE_INFO1_CHECK_2K_MODE) | 175 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_RETRY), 176 HAL_REO_UPD_RX_QUEUE_INFO1_RETRY) | 177 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_OOR_MODE), 178 HAL_REO_UPD_RX_QUEUE_INFO1_OOR_MODE) | 179 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_PN_CHECK), 180 HAL_REO_UPD_RX_QUEUE_INFO1_PN_CHECK) | 181 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_EVEN_PN), 182 HAL_REO_UPD_RX_QUEUE_INFO1_EVEN_PN) | 183 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_UNEVEN_PN), 184 HAL_REO_UPD_RX_QUEUE_INFO1_UNEVEN_PN) | 185 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE), 186 HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE) | 187 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG), 188 HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG); 189 190 if (cmd->pn_size == 24) 191 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_24; 192 else if (cmd->pn_size == 48) 193 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_48; 194 else if (cmd->pn_size == 128) 195 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_128; 196 197 if (cmd->ba_window_size < 1) 198 cmd->ba_window_size = 1; 199 200 if (cmd->ba_window_size == 1) 201 cmd->ba_window_size++; 202 203 desc->info2 = 204 le32_encode_bits(cmd->ba_window_size - 1, 205 HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE) | 206 le32_encode_bits(cmd->pn_size, HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE) | 207 le32_encode_bits(!!(cmd->upd2 & HAL_REO_CMD_UPD2_SVLD), 208 HAL_REO_UPD_RX_QUEUE_INFO2_SVLD) | 209 le32_encode_bits(u32_get_bits(cmd->upd2, HAL_REO_CMD_UPD2_SSN), 210 HAL_REO_UPD_RX_QUEUE_INFO2_SSN) | 211 le32_encode_bits(!!(cmd->upd2 & HAL_REO_CMD_UPD2_SEQ_2K_ERR), 212 HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR) | 213 le32_encode_bits(!!(cmd->upd2 & HAL_REO_CMD_UPD2_PN_ERR), 214 HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR); 215 216 return le32_get_bits(desc->cmd.info0, HAL_REO_CMD_HDR_INFO0_CMD_NUMBER); 217 } 218 219 int ath12k_wifi7_hal_reo_cmd_send(struct ath12k_base *ab, struct hal_srng *srng, 220 enum hal_reo_cmd_type type, 221 struct ath12k_hal_reo_cmd *cmd) 222 { 223 struct ath12k_hal *hal = &ab->hal; 224 void *reo_desc; 225 int ret; 226 227 spin_lock_bh(&srng->lock); 228 229 ath12k_hal_srng_access_begin(ab, srng); 230 reo_desc = ath12k_hal_srng_src_get_next_entry(ab, srng); 231 if (!reo_desc) { 232 ret = -ENOBUFS; 233 goto out; 234 } 235 236 switch (type) { 237 case HAL_REO_CMD_GET_QUEUE_STATS: 238 ret = ath12k_wifi7_hal_reo_cmd_queue_stats(hal, reo_desc, cmd); 239 break; 240 case HAL_REO_CMD_FLUSH_CACHE: 241 ret = ath12k_wifi7_hal_reo_cmd_flush_cache(hal, reo_desc, cmd); 242 break; 243 case HAL_REO_CMD_UPDATE_RX_QUEUE: 244 ret = ath12k_wifi7_hal_reo_cmd_update_rx_queue(hal, reo_desc, cmd); 245 break; 246 case HAL_REO_CMD_FLUSH_QUEUE: 247 case HAL_REO_CMD_UNBLOCK_CACHE: 248 case HAL_REO_CMD_FLUSH_TIMEOUT_LIST: 249 ath12k_warn(ab, "Unsupported reo command %d\n", type); 250 ret = -EOPNOTSUPP; 251 break; 252 default: 253 ath12k_warn(ab, "Unknown reo command %d\n", type); 254 ret = -EINVAL; 255 break; 256 } 257 258 out: 259 ath12k_hal_srng_access_end(ab, srng); 260 spin_unlock_bh(&srng->lock); 261 262 return ret; 263 } 264 265 void ath12k_wifi7_hal_rx_buf_addr_info_set(struct ath12k_buffer_addr *binfo, 266 dma_addr_t paddr, u32 cookie, 267 u8 manager) 268 { 269 u32 paddr_lo, paddr_hi; 270 271 paddr_lo = lower_32_bits(paddr); 272 paddr_hi = upper_32_bits(paddr); 273 binfo->info0 = le32_encode_bits(paddr_lo, BUFFER_ADDR_INFO0_ADDR); 274 binfo->info1 = le32_encode_bits(paddr_hi, BUFFER_ADDR_INFO1_ADDR) | 275 le32_encode_bits(cookie, BUFFER_ADDR_INFO1_SW_COOKIE) | 276 le32_encode_bits(manager, BUFFER_ADDR_INFO1_RET_BUF_MGR); 277 } 278 279 void ath12k_wifi7_hal_rx_buf_addr_info_get(struct ath12k_buffer_addr *binfo, 280 dma_addr_t *paddr, 281 u32 *cookie, u8 *rbm) 282 { 283 *paddr = (((u64)le32_get_bits(binfo->info1, BUFFER_ADDR_INFO1_ADDR)) << 32) | 284 le32_get_bits(binfo->info0, BUFFER_ADDR_INFO0_ADDR); 285 *cookie = le32_get_bits(binfo->info1, BUFFER_ADDR_INFO1_SW_COOKIE); 286 *rbm = le32_get_bits(binfo->info1, BUFFER_ADDR_INFO1_RET_BUF_MGR); 287 } 288 289 void 290 ath12k_wifi7_hal_rx_msdu_link_info_get(struct hal_rx_msdu_link *link, 291 u32 *num_msdus, u32 *msdu_cookies, 292 enum hal_rx_buf_return_buf_manager *rbm) 293 { 294 struct hal_rx_msdu_details *msdu; 295 u32 val; 296 int i; 297 298 *num_msdus = HAL_NUM_RX_MSDUS_PER_LINK_DESC; 299 300 msdu = &link->msdu_link[0]; 301 *rbm = le32_get_bits(msdu->buf_addr_info.info1, 302 BUFFER_ADDR_INFO1_RET_BUF_MGR); 303 304 for (i = 0; i < *num_msdus; i++) { 305 msdu = &link->msdu_link[i]; 306 307 val = le32_get_bits(msdu->buf_addr_info.info0, 308 BUFFER_ADDR_INFO0_ADDR); 309 if (val == 0) { 310 *num_msdus = i; 311 break; 312 } 313 *msdu_cookies = le32_get_bits(msdu->buf_addr_info.info1, 314 BUFFER_ADDR_INFO1_SW_COOKIE); 315 msdu_cookies++; 316 } 317 } 318 319 int ath12k_wifi7_hal_desc_reo_parse_err(struct ath12k_dp *dp, 320 struct hal_reo_dest_ring *desc, 321 dma_addr_t *paddr, u32 *desc_bank) 322 { 323 struct ath12k_base *ab = dp->ab; 324 enum hal_reo_dest_ring_push_reason push_reason; 325 enum hal_reo_dest_ring_error_code err_code; 326 u32 cookie; 327 328 push_reason = le32_get_bits(desc->info0, 329 HAL_REO_DEST_RING_INFO0_PUSH_REASON); 330 err_code = le32_get_bits(desc->info0, 331 HAL_REO_DEST_RING_INFO0_ERROR_CODE); 332 dp->device_stats.reo_error[err_code]++; 333 334 if (push_reason != HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED && 335 push_reason != HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) { 336 ath12k_warn(ab, "expected error push reason code, received %d\n", 337 push_reason); 338 return -EINVAL; 339 } 340 341 ath12k_wifi7_hal_rx_reo_ent_paddr_get(&desc->buf_addr_info, paddr, 342 &cookie); 343 *desc_bank = u32_get_bits(cookie, DP_LINK_DESC_BANK_MASK); 344 345 return 0; 346 } 347 348 int ath12k_wifi7_hal_wbm_desc_parse_err(struct ath12k_dp *dp, void *desc, 349 struct hal_rx_wbm_rel_info *rel_info) 350 { 351 struct hal_wbm_release_ring *wbm_desc = desc; 352 struct hal_wbm_release_ring_cc_rx *wbm_cc_desc = desc; 353 enum hal_wbm_rel_desc_type type; 354 enum hal_wbm_rel_src_module rel_src; 355 bool hw_cc_done; 356 u64 desc_va; 357 u32 val; 358 359 type = le32_get_bits(wbm_desc->info0, HAL_WBM_RELEASE_INFO0_DESC_TYPE); 360 /* We expect only WBM_REL buffer type */ 361 if (type != HAL_WBM_REL_DESC_TYPE_REL_MSDU) { 362 WARN_ON(1); 363 return -EINVAL; 364 } 365 366 rel_src = le32_get_bits(wbm_desc->info0, 367 HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE); 368 if (rel_src != HAL_WBM_REL_SRC_MODULE_RXDMA && 369 rel_src != HAL_WBM_REL_SRC_MODULE_REO) 370 return -EINVAL; 371 372 /* The format of wbm rel ring desc changes based on the 373 * hw cookie conversion status 374 */ 375 hw_cc_done = le32_get_bits(wbm_desc->info0, 376 HAL_WBM_RELEASE_RX_INFO0_CC_STATUS); 377 378 if (!hw_cc_done) { 379 val = le32_get_bits(wbm_desc->buf_addr_info.info1, 380 BUFFER_ADDR_INFO1_RET_BUF_MGR); 381 if (val != HAL_RX_BUF_RBM_SW3_BM) { 382 dp->device_stats.invalid_rbm++; 383 return -EINVAL; 384 } 385 386 rel_info->cookie = le32_get_bits(wbm_desc->buf_addr_info.info1, 387 BUFFER_ADDR_INFO1_SW_COOKIE); 388 389 rel_info->rx_desc = NULL; 390 } else { 391 val = le32_get_bits(wbm_cc_desc->info0, 392 HAL_WBM_RELEASE_RX_CC_INFO0_RBM); 393 if (val != HAL_RX_BUF_RBM_SW3_BM) { 394 dp->device_stats.invalid_rbm++; 395 return -EINVAL; 396 } 397 398 rel_info->cookie = le32_get_bits(wbm_cc_desc->info1, 399 HAL_WBM_RELEASE_RX_CC_INFO1_COOKIE); 400 401 desc_va = ((u64)le32_to_cpu(wbm_cc_desc->buf_va_hi) << 32 | 402 le32_to_cpu(wbm_cc_desc->buf_va_lo)); 403 rel_info->rx_desc = 404 (struct ath12k_rx_desc_info *)((unsigned long)desc_va); 405 } 406 407 rel_info->err_rel_src = rel_src; 408 rel_info->hw_cc_done = hw_cc_done; 409 410 rel_info->first_msdu = le32_get_bits(wbm_desc->info3, 411 HAL_WBM_RELEASE_INFO3_FIRST_MSDU); 412 rel_info->last_msdu = le32_get_bits(wbm_desc->info3, 413 HAL_WBM_RELEASE_INFO3_LAST_MSDU); 414 rel_info->continuation = le32_get_bits(wbm_desc->info3, 415 HAL_WBM_RELEASE_INFO3_CONTINUATION); 416 417 if (rel_info->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO) { 418 rel_info->push_reason = 419 le32_get_bits(wbm_desc->info0, 420 HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON); 421 rel_info->err_code = 422 le32_get_bits(wbm_desc->info0, 423 HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE); 424 } else { 425 rel_info->push_reason = 426 le32_get_bits(wbm_desc->info0, 427 HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON); 428 rel_info->err_code = 429 le32_get_bits(wbm_desc->info0, 430 HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE); 431 } 432 433 rel_info->peer_metadata = wbm_desc->info2; 434 435 return 0; 436 } 437 438 void ath12k_wifi7_hal_rx_reo_ent_paddr_get(struct ath12k_buffer_addr *buff_addr, 439 dma_addr_t *paddr, u32 *cookie) 440 { 441 *paddr = ((u64)(le32_get_bits(buff_addr->info1, 442 BUFFER_ADDR_INFO1_ADDR)) << 32) | 443 le32_get_bits(buff_addr->info0, BUFFER_ADDR_INFO0_ADDR); 444 445 *cookie = le32_get_bits(buff_addr->info1, BUFFER_ADDR_INFO1_SW_COOKIE); 446 } 447 448 void ath12k_wifi7_hal_rx_reo_ent_buf_paddr_get(void *rx_desc, dma_addr_t *paddr, 449 u32 *sw_cookie, 450 struct ath12k_buffer_addr **pp_buf_addr, 451 u8 *rbm, u32 *msdu_cnt) 452 { 453 struct hal_reo_entrance_ring *reo_ent_ring = 454 (struct hal_reo_entrance_ring *)rx_desc; 455 struct ath12k_buffer_addr *buf_addr_info; 456 struct rx_mpdu_desc *rx_mpdu_desc_info_details; 457 458 rx_mpdu_desc_info_details = 459 (struct rx_mpdu_desc *)&reo_ent_ring->rx_mpdu_info; 460 461 *msdu_cnt = le32_get_bits(rx_mpdu_desc_info_details->info0, 462 RX_MPDU_DESC_INFO0_MSDU_COUNT); 463 464 buf_addr_info = (struct ath12k_buffer_addr *)&reo_ent_ring->buf_addr_info; 465 466 *paddr = (((u64)le32_get_bits(buf_addr_info->info1, 467 BUFFER_ADDR_INFO1_ADDR)) << 32) | 468 le32_get_bits(buf_addr_info->info0, 469 BUFFER_ADDR_INFO0_ADDR); 470 471 *sw_cookie = le32_get_bits(buf_addr_info->info1, 472 BUFFER_ADDR_INFO1_SW_COOKIE); 473 *rbm = le32_get_bits(buf_addr_info->info1, 474 BUFFER_ADDR_INFO1_RET_BUF_MGR); 475 476 *pp_buf_addr = (void *)buf_addr_info; 477 } 478 479 void ath12k_wifi7_hal_rx_msdu_list_get(struct ath12k *ar, 480 void *link_desc_opaque, 481 void *msdu_list_opaque, u16 *num_msdus) 482 { 483 struct hal_rx_msdu_link *link_desc = 484 (struct hal_rx_msdu_link *)link_desc_opaque; 485 struct hal_rx_msdu_list *msdu_list = 486 (struct hal_rx_msdu_list *)msdu_list_opaque; 487 struct hal_rx_msdu_details *msdu_details = NULL; 488 struct rx_msdu_desc *msdu_desc_info = NULL; 489 u32 last = 0, first = 0; 490 u8 tmp = 0; 491 int i; 492 493 last = u32_encode_bits(last, RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU); 494 first = u32_encode_bits(first, RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU); 495 msdu_details = &link_desc->msdu_link[0]; 496 497 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 498 if (!i && le32_get_bits(msdu_details[i].buf_addr_info.info0, 499 BUFFER_ADDR_INFO0_ADDR) == 0) 500 break; 501 if (le32_get_bits(msdu_details[i].buf_addr_info.info0, 502 BUFFER_ADDR_INFO0_ADDR) == 0) { 503 msdu_desc_info = &msdu_details[i - 1].rx_msdu_info; 504 msdu_desc_info->info0 |= cpu_to_le32(last); 505 break; 506 } 507 msdu_desc_info = &msdu_details[i].rx_msdu_info; 508 509 if (!i) 510 msdu_desc_info->info0 |= cpu_to_le32(first); 511 else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 512 msdu_desc_info->info0 |= cpu_to_le32(last); 513 msdu_list->msdu_info[i].msdu_flags = le32_to_cpu(msdu_desc_info->info0); 514 msdu_list->msdu_info[i].msdu_len = 515 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info->info0); 516 msdu_list->sw_cookie[i] = 517 le32_get_bits(msdu_details[i].buf_addr_info.info1, 518 BUFFER_ADDR_INFO1_SW_COOKIE); 519 tmp = le32_get_bits(msdu_details[i].buf_addr_info.info1, 520 BUFFER_ADDR_INFO1_RET_BUF_MGR); 521 msdu_list->paddr[i] = 522 ((u64)(le32_get_bits(msdu_details[i].buf_addr_info.info1, 523 BUFFER_ADDR_INFO1_ADDR)) << 32) | 524 le32_get_bits(msdu_details[i].buf_addr_info.info0, 525 BUFFER_ADDR_INFO0_ADDR); 526 msdu_list->rbm[i] = tmp; 527 } 528 *num_msdus = i; 529 } 530 531 void 532 ath12k_wifi7_hal_rx_msdu_link_desc_set(struct ath12k_base *ab, 533 struct hal_wbm_release_ring *desc, 534 struct ath12k_buffer_addr *buf_addr_info, 535 enum hal_wbm_rel_bm_act action) 536 { 537 desc->buf_addr_info = *buf_addr_info; 538 desc->info0 |= le32_encode_bits(HAL_WBM_REL_SRC_MODULE_SW, 539 HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE) | 540 le32_encode_bits(action, HAL_WBM_RELEASE_INFO0_BM_ACTION) | 541 le32_encode_bits(HAL_WBM_REL_DESC_TYPE_MSDU_LINK, 542 HAL_WBM_RELEASE_INFO0_DESC_TYPE); 543 } 544 545 void ath12k_wifi7_hal_reo_status_queue_stats(struct ath12k_base *ab, 546 struct hal_reo_get_queue_stats_status *desc, 547 struct hal_reo_status *status) 548 { 549 status->uniform_hdr.cmd_num = 550 le32_get_bits(desc->hdr.info0, 551 HAL_REO_STATUS_HDR_INFO0_STATUS_NUM); 552 status->uniform_hdr.cmd_status = 553 le32_get_bits(desc->hdr.info0, 554 HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS); 555 556 ath12k_dbg(ab, ATH12K_DBG_HAL, "Queue stats status:\n"); 557 ath12k_dbg(ab, ATH12K_DBG_HAL, "header: cmd_num %d status %d\n", 558 status->uniform_hdr.cmd_num, 559 status->uniform_hdr.cmd_status); 560 ath12k_dbg(ab, ATH12K_DBG_HAL, "ssn %u cur_idx %u\n", 561 le32_get_bits(desc->info0, 562 HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN), 563 le32_get_bits(desc->info0, 564 HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX)); 565 ath12k_dbg(ab, ATH12K_DBG_HAL, "pn = [%08x, %08x, %08x, %08x]\n", 566 desc->pn[0], desc->pn[1], desc->pn[2], desc->pn[3]); 567 ath12k_dbg(ab, ATH12K_DBG_HAL, "last_rx: enqueue_tstamp %08x dequeue_tstamp %08x\n", 568 desc->last_rx_enqueue_timestamp, 569 desc->last_rx_dequeue_timestamp); 570 ath12k_dbg(ab, ATH12K_DBG_HAL, "rx_bitmap [%08x %08x %08x %08x %08x %08x %08x %08x]\n", 571 desc->rx_bitmap[0], desc->rx_bitmap[1], desc->rx_bitmap[2], 572 desc->rx_bitmap[3], desc->rx_bitmap[4], desc->rx_bitmap[5], 573 desc->rx_bitmap[6], desc->rx_bitmap[7]); 574 ath12k_dbg(ab, ATH12K_DBG_HAL, "count: cur_mpdu %u cur_msdu %u\n", 575 le32_get_bits(desc->info1, 576 HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT), 577 le32_get_bits(desc->info1, 578 HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT)); 579 ath12k_dbg(ab, ATH12K_DBG_HAL, "fwd_timeout %u fwd_bar %u dup_count %u\n", 580 le32_get_bits(desc->info2, 581 HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT), 582 le32_get_bits(desc->info2, 583 HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT), 584 le32_get_bits(desc->info2, 585 HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT)); 586 ath12k_dbg(ab, ATH12K_DBG_HAL, "frames_in_order %u bar_rcvd %u\n", 587 le32_get_bits(desc->info3, 588 HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT), 589 le32_get_bits(desc->info3, 590 HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT)); 591 ath12k_dbg(ab, ATH12K_DBG_HAL, "num_mpdus %d num_msdus %d total_bytes %d\n", 592 desc->num_mpdu_frames, desc->num_msdu_frames, 593 desc->total_bytes); 594 ath12k_dbg(ab, ATH12K_DBG_HAL, "late_rcvd %u win_jump_2k %u hole_cnt %u\n", 595 le32_get_bits(desc->info4, 596 HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU), 597 le32_get_bits(desc->info2, 598 HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_WINDOW_JMP2K), 599 le32_get_bits(desc->info4, 600 HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT)); 601 ath12k_dbg(ab, ATH12K_DBG_HAL, "looping count %u\n", 602 le32_get_bits(desc->info5, 603 HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT)); 604 } 605 606 void ath12k_wifi7_hal_reo_flush_queue_status(struct ath12k_base *ab, 607 struct hal_reo_flush_queue_status *desc, 608 struct hal_reo_status *status) 609 { 610 status->uniform_hdr.cmd_num = 611 le32_get_bits(desc->hdr.info0, 612 HAL_REO_STATUS_HDR_INFO0_STATUS_NUM); 613 status->uniform_hdr.cmd_status = 614 le32_get_bits(desc->hdr.info0, 615 HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS); 616 status->u.flush_queue.err_detected = 617 le32_get_bits(desc->info0, 618 HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED); 619 } 620 621 void 622 ath12k_wifi7_hal_reo_flush_cache_status(struct ath12k_base *ab, 623 struct hal_reo_flush_cache_status *desc, 624 struct hal_reo_status *status) 625 { 626 struct ath12k_hal *hal = &ab->hal; 627 628 status->uniform_hdr.cmd_num = 629 le32_get_bits(desc->hdr.info0, 630 HAL_REO_STATUS_HDR_INFO0_STATUS_NUM); 631 status->uniform_hdr.cmd_status = 632 le32_get_bits(desc->hdr.info0, 633 HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS); 634 635 status->u.flush_cache.err_detected = 636 le32_get_bits(desc->info0, 637 HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR); 638 status->u.flush_cache.err_code = 639 le32_get_bits(desc->info0, 640 HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE); 641 if (!status->u.flush_cache.err_code) 642 hal->avail_blk_resource |= BIT(hal->current_blk_index); 643 644 status->u.flush_cache.cache_controller_flush_status_hit = 645 le32_get_bits(desc->info0, 646 HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_STATUS_HIT); 647 648 status->u.flush_cache.cache_controller_flush_status_desc_type = 649 le32_get_bits(desc->info0, 650 HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE); 651 status->u.flush_cache.cache_controller_flush_status_client_id = 652 le32_get_bits(desc->info0, 653 HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID); 654 status->u.flush_cache.cache_controller_flush_status_err = 655 le32_get_bits(desc->info0, 656 HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR); 657 status->u.flush_cache.cache_controller_flush_status_cnt = 658 le32_get_bits(desc->info0, 659 HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT); 660 } 661 662 void ath12k_wifi7_hal_reo_unblk_cache_status(struct ath12k_base *ab, 663 struct hal_reo_unblock_cache_status *desc, 664 struct hal_reo_status *status) 665 { 666 struct ath12k_hal *hal = &ab->hal; 667 668 status->uniform_hdr.cmd_num = 669 le32_get_bits(desc->hdr.info0, 670 HAL_REO_STATUS_HDR_INFO0_STATUS_NUM); 671 status->uniform_hdr.cmd_status = 672 le32_get_bits(desc->hdr.info0, 673 HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS); 674 675 status->u.unblock_cache.err_detected = 676 le32_get_bits(desc->info0, 677 HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR); 678 status->u.unblock_cache.unblock_type = 679 le32_get_bits(desc->info0, 680 HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_TYPE); 681 682 if (!status->u.unblock_cache.err_detected && 683 status->u.unblock_cache.unblock_type == 684 HAL_REO_STATUS_UNBLOCK_BLOCKING_RESOURCE) 685 hal->avail_blk_resource &= ~BIT(hal->current_blk_index); 686 } 687 688 void 689 ath12k_wifi7_hal_reo_flush_timeout_list_status(struct ath12k_base *ab, 690 struct hal_reo_flush_timeout_list_status *desc, 691 struct hal_reo_status *status) 692 { 693 status->uniform_hdr.cmd_num = 694 le32_get_bits(desc->hdr.info0, 695 HAL_REO_STATUS_HDR_INFO0_STATUS_NUM); 696 status->uniform_hdr.cmd_status = 697 le32_get_bits(desc->hdr.info0, 698 HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS); 699 700 status->u.timeout_list.err_detected = 701 le32_get_bits(desc->info0, 702 HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR); 703 status->u.timeout_list.list_empty = 704 le32_get_bits(desc->info0, 705 HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_LIST_EMPTY); 706 707 status->u.timeout_list.release_desc_cnt = 708 le32_get_bits(desc->info1, 709 HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT); 710 status->u.timeout_list.fwd_buf_cnt = 711 le32_get_bits(desc->info0, 712 HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT); 713 } 714 715 void 716 ath12k_wifi7_hal_reo_desc_thresh_reached_status(struct ath12k_base *ab, 717 struct hal_reo_desc_thresh_reached_status *desc, 718 struct hal_reo_status *status) 719 { 720 status->uniform_hdr.cmd_num = 721 le32_get_bits(desc->hdr.info0, 722 HAL_REO_STATUS_HDR_INFO0_STATUS_NUM); 723 status->uniform_hdr.cmd_status = 724 le32_get_bits(desc->hdr.info0, 725 HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS); 726 727 status->u.desc_thresh_reached.threshold_idx = 728 le32_get_bits(desc->info0, 729 HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX); 730 731 status->u.desc_thresh_reached.link_desc_counter0 = 732 le32_get_bits(desc->info1, 733 HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0); 734 735 status->u.desc_thresh_reached.link_desc_counter1 = 736 le32_get_bits(desc->info2, 737 HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1); 738 739 status->u.desc_thresh_reached.link_desc_counter2 = 740 le32_get_bits(desc->info3, 741 HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2); 742 743 status->u.desc_thresh_reached.link_desc_counter_sum = 744 le32_get_bits(desc->info4, 745 HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM); 746 } 747 748 void ath12k_wifi7_hal_reo_update_rx_reo_queue_status(struct ath12k_base *ab, 749 struct hal_reo_status_hdr *desc, 750 struct hal_reo_status *status) 751 { 752 status->uniform_hdr.cmd_num = 753 le32_get_bits(desc->info0, 754 HAL_REO_STATUS_HDR_INFO0_STATUS_NUM); 755 status->uniform_hdr.cmd_status = 756 le32_get_bits(desc->info0, 757 HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS); 758 } 759 760 u32 ath12k_wifi7_hal_reo_qdesc_size(u32 ba_window_size, u8 tid) 761 { 762 u32 num_ext_desc, num_1k_desc = 0; 763 764 if (ba_window_size <= 1) { 765 if (tid != HAL_DESC_REO_NON_QOS_TID) 766 num_ext_desc = 1; 767 else 768 num_ext_desc = 0; 769 770 } else if (ba_window_size <= 105) { 771 num_ext_desc = 1; 772 } else if (ba_window_size <= 210) { 773 num_ext_desc = 2; 774 } else if (ba_window_size <= 256) { 775 num_ext_desc = 3; 776 } else { 777 num_ext_desc = 10; 778 num_1k_desc = 1; 779 } 780 781 return sizeof(struct hal_rx_reo_queue) + 782 (num_ext_desc * sizeof(struct hal_rx_reo_queue_ext)) + 783 (num_1k_desc * sizeof(struct hal_rx_reo_queue_1k)); 784 } 785 786 void ath12k_wifi7_hal_reo_qdesc_setup(struct hal_rx_reo_queue *qdesc, 787 int tid, u32 ba_window_size, 788 u32 start_seq, enum hal_pn_type type) 789 { 790 struct hal_rx_reo_queue_ext *ext_desc; 791 792 ath12k_wifi7_hal_reo_set_desc_hdr(&qdesc->desc_hdr, HAL_DESC_REO_OWNED, 793 HAL_DESC_REO_QUEUE_DESC, 794 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0); 795 796 qdesc->rx_queue_num = le32_encode_bits(tid, HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER); 797 798 qdesc->info0 = 799 le32_encode_bits(1, HAL_RX_REO_QUEUE_INFO0_VLD) | 800 le32_encode_bits(1, HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER) | 801 le32_encode_bits(ath12k_tid_to_ac(tid), HAL_RX_REO_QUEUE_INFO0_AC); 802 803 if (ba_window_size < 1) 804 ba_window_size = 1; 805 806 if (ba_window_size == 1 && tid != HAL_DESC_REO_NON_QOS_TID) 807 ba_window_size++; 808 809 if (ba_window_size == 1) 810 qdesc->info0 |= le32_encode_bits(1, HAL_RX_REO_QUEUE_INFO0_RETRY); 811 812 qdesc->info0 |= le32_encode_bits(ba_window_size - 1, 813 HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE); 814 switch (type) { 815 case HAL_PN_TYPE_NONE: 816 case HAL_PN_TYPE_WAPI_EVEN: 817 case HAL_PN_TYPE_WAPI_UNEVEN: 818 break; 819 case HAL_PN_TYPE_WPA: 820 qdesc->info0 |= 821 le32_encode_bits(1, HAL_RX_REO_QUEUE_INFO0_PN_CHECK) | 822 le32_encode_bits(HAL_RX_REO_QUEUE_PN_SIZE_48, 823 HAL_RX_REO_QUEUE_INFO0_PN_SIZE); 824 break; 825 } 826 827 /* TODO: Set Ignore ampdu flags based on BA window size and/or 828 * AMPDU capabilities 829 */ 830 qdesc->info0 |= le32_encode_bits(1, HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG); 831 832 qdesc->info1 |= le32_encode_bits(0, HAL_RX_REO_QUEUE_INFO1_SVLD); 833 834 if (start_seq <= 0xfff) 835 qdesc->info1 = le32_encode_bits(start_seq, 836 HAL_RX_REO_QUEUE_INFO1_SSN); 837 838 if (tid == HAL_DESC_REO_NON_QOS_TID) 839 return; 840 841 ext_desc = qdesc->ext_desc; 842 843 /* TODO: HW queue descriptors are currently allocated for max BA 844 * window size for all QOS TIDs so that same descriptor can be used 845 * later when ADDBA request is received. This should be changed to 846 * allocate HW queue descriptors based on BA window size being 847 * negotiated (0 for non BA cases), and reallocate when BA window 848 * size changes and also send WMI message to FW to change the REO 849 * queue descriptor in Rx peer entry as part of dp_rx_tid_update. 850 */ 851 memset(ext_desc, 0, 3 * sizeof(*ext_desc)); 852 ath12k_wifi7_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, 853 HAL_DESC_REO_OWNED, 854 HAL_DESC_REO_QUEUE_EXT_DESC, 855 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1); 856 ext_desc++; 857 ath12k_wifi7_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, 858 HAL_DESC_REO_OWNED, 859 HAL_DESC_REO_QUEUE_EXT_DESC, 860 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2); 861 ext_desc++; 862 ath12k_wifi7_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, 863 HAL_DESC_REO_OWNED, 864 HAL_DESC_REO_QUEUE_EXT_DESC, 865 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3); 866 } 867 868 void ath12k_wifi7_hal_reo_init_cmd_ring_tlv64(struct ath12k_base *ab, 869 struct hal_srng *srng) 870 { 871 struct hal_srng_params params; 872 struct hal_tlv_64_hdr *tlv; 873 struct hal_reo_get_queue_stats *desc; 874 int i, cmd_num = 1; 875 int entry_size; 876 u8 *entry; 877 878 memset(¶ms, 0, sizeof(params)); 879 880 entry_size = ath12k_hal_srng_get_entrysize(ab, HAL_REO_CMD); 881 ath12k_hal_srng_get_params(ab, srng, ¶ms); 882 entry = (u8 *)params.ring_base_vaddr; 883 884 for (i = 0; i < params.num_entries; i++) { 885 tlv = (struct hal_tlv_64_hdr *)entry; 886 desc = (struct hal_reo_get_queue_stats *)tlv->value; 887 desc->cmd.info0 = le32_encode_bits(cmd_num++, 888 HAL_REO_CMD_HDR_INFO0_CMD_NUMBER); 889 entry += entry_size; 890 } 891 } 892 893 void ath12k_wifi7_hal_reo_init_cmd_ring_tlv32(struct ath12k_base *ab, 894 struct hal_srng *srng) 895 { 896 struct hal_reo_get_queue_stats *desc; 897 struct hal_srng_params params; 898 struct hal_tlv_hdr *tlv; 899 int i, cmd_num = 1; 900 int entry_size; 901 u8 *entry; 902 903 memset(¶ms, 0, sizeof(params)); 904 905 entry_size = ath12k_hal_srng_get_entrysize(ab, HAL_REO_CMD); 906 ath12k_hal_srng_get_params(ab, srng, ¶ms); 907 entry = (u8 *)params.ring_base_vaddr; 908 909 for (i = 0; i < params.num_entries; i++) { 910 tlv = (struct hal_tlv_hdr *)entry; 911 desc = (struct hal_reo_get_queue_stats *)tlv->value; 912 desc->cmd.info0 = le32_encode_bits(cmd_num++, 913 HAL_REO_CMD_HDR_INFO0_CMD_NUMBER); 914 entry += entry_size; 915 } 916 } 917 918 void ath12k_wifi7_hal_reo_hw_setup(struct ath12k_base *ab, u32 ring_hash_map) 919 { 920 struct ath12k_hal *hal = &ab->hal; 921 922 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; 923 u32 val; 924 925 val = ath12k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); 926 927 val |= u32_encode_bits(1, HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE) | 928 u32_encode_bits(1, HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE); 929 ath12k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); 930 931 val = ath12k_hif_read32(ab, reo_base + HAL_REO1_MISC_CTRL_ADDR(hal)); 932 933 val &= ~(HAL_REO1_MISC_CTL_FRAG_DST_RING | 934 HAL_REO1_MISC_CTL_BAR_DST_RING); 935 val |= u32_encode_bits(HAL_SRNG_RING_ID_REO2SW0, 936 HAL_REO1_MISC_CTL_FRAG_DST_RING); 937 val |= u32_encode_bits(HAL_SRNG_RING_ID_REO2SW0, 938 HAL_REO1_MISC_CTL_BAR_DST_RING); 939 ath12k_hif_write32(ab, reo_base + HAL_REO1_MISC_CTRL_ADDR(hal), val); 940 941 ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(hal), 942 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_USEC); 943 ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(hal), 944 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_USEC); 945 ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(hal), 946 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_USEC); 947 ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(hal), 948 HAL_DEFAULT_VO_REO_TIMEOUT_USEC); 949 950 ath12k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, 951 ring_hash_map); 952 ath12k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, 953 ring_hash_map); 954 } 955 956 void ath12k_wifi7_hal_reo_shared_qaddr_cache_clear(struct ath12k_base *ab) 957 { 958 u32 val; 959 struct ath12k_hal *hal = &ab->hal; 960 struct ath12k_dp *dp = ath12k_ab_to_dp(ab); 961 962 lockdep_assert_held(&dp->dp_lock); 963 val = ath12k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + 964 HAL_REO1_QDESC_ADDR(hal)); 965 966 val |= u32_encode_bits(1, HAL_REO_QDESC_ADDR_READ_CLEAR_QDESC_ARRAY); 967 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + 968 HAL_REO1_QDESC_ADDR(hal), val); 969 970 val &= ~HAL_REO_QDESC_ADDR_READ_CLEAR_QDESC_ARRAY; 971 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + 972 HAL_REO1_QDESC_ADDR(hal), val); 973 } 974