1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 #include "hal_desc.h" 7 #include "hal_qcn9274.h" 8 #include "hw.h" 9 #include "hal.h" 10 #include "hal_tx.h" 11 12 static const struct hal_srng_config hw_srng_config_template[] = { 13 /* TODO: max_rings can populated by querying HW capabilities */ 14 [HAL_REO_DST] = { 15 .start_ring_id = HAL_SRNG_RING_ID_REO2SW1, 16 .max_rings = 8, 17 .entry_size = sizeof(struct hal_reo_dest_ring) >> 2, 18 .mac_type = ATH12K_HAL_SRNG_UMAC, 19 .ring_dir = HAL_SRNG_DIR_DST, 20 .max_size = HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE, 21 }, 22 [HAL_REO_EXCEPTION] = { 23 /* Designating REO2SW0 ring as exception ring. 24 * Any of theREO2SW rings can be used as exception ring. 25 */ 26 .start_ring_id = HAL_SRNG_RING_ID_REO2SW0, 27 .max_rings = 1, 28 .entry_size = sizeof(struct hal_reo_dest_ring) >> 2, 29 .mac_type = ATH12K_HAL_SRNG_UMAC, 30 .ring_dir = HAL_SRNG_DIR_DST, 31 .max_size = HAL_REO_REO2SW0_RING_BASE_MSB_RING_SIZE, 32 }, 33 [HAL_REO_REINJECT] = { 34 .start_ring_id = HAL_SRNG_RING_ID_SW2REO, 35 .max_rings = 4, 36 .entry_size = sizeof(struct hal_reo_entrance_ring) >> 2, 37 .mac_type = ATH12K_HAL_SRNG_UMAC, 38 .ring_dir = HAL_SRNG_DIR_SRC, 39 .max_size = HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE, 40 }, 41 [HAL_REO_CMD] = { 42 .start_ring_id = HAL_SRNG_RING_ID_REO_CMD, 43 .max_rings = 1, 44 .entry_size = (sizeof(struct hal_tlv_64_hdr) + 45 sizeof(struct hal_reo_get_queue_stats)) >> 2, 46 .mac_type = ATH12K_HAL_SRNG_UMAC, 47 .ring_dir = HAL_SRNG_DIR_SRC, 48 .max_size = HAL_REO_CMD_RING_BASE_MSB_RING_SIZE, 49 }, 50 [HAL_REO_STATUS] = { 51 .start_ring_id = HAL_SRNG_RING_ID_REO_STATUS, 52 .max_rings = 1, 53 .entry_size = (sizeof(struct hal_tlv_64_hdr) + 54 sizeof(struct hal_reo_get_queue_stats_status)) >> 2, 55 .mac_type = ATH12K_HAL_SRNG_UMAC, 56 .ring_dir = HAL_SRNG_DIR_DST, 57 .max_size = HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE, 58 }, 59 [HAL_TCL_DATA] = { 60 .start_ring_id = HAL_SRNG_RING_ID_SW2TCL1, 61 .max_rings = 6, 62 .entry_size = sizeof(struct hal_tcl_data_cmd) >> 2, 63 .mac_type = ATH12K_HAL_SRNG_UMAC, 64 .ring_dir = HAL_SRNG_DIR_SRC, 65 .max_size = HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE, 66 }, 67 [HAL_TCL_CMD] = { 68 .start_ring_id = HAL_SRNG_RING_ID_SW2TCL_CMD, 69 .max_rings = 1, 70 .entry_size = sizeof(struct hal_tcl_gse_cmd) >> 2, 71 .mac_type = ATH12K_HAL_SRNG_UMAC, 72 .ring_dir = HAL_SRNG_DIR_SRC, 73 .max_size = HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE, 74 }, 75 [HAL_TCL_STATUS] = { 76 .start_ring_id = HAL_SRNG_RING_ID_TCL_STATUS, 77 .max_rings = 1, 78 .entry_size = (sizeof(struct hal_tlv_hdr) + 79 sizeof(struct hal_tcl_status_ring)) >> 2, 80 .mac_type = ATH12K_HAL_SRNG_UMAC, 81 .ring_dir = HAL_SRNG_DIR_DST, 82 .max_size = HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE, 83 }, 84 [HAL_CE_SRC] = { 85 .start_ring_id = HAL_SRNG_RING_ID_CE0_SRC, 86 .max_rings = 16, 87 .entry_size = sizeof(struct hal_ce_srng_src_desc) >> 2, 88 .mac_type = ATH12K_HAL_SRNG_UMAC, 89 .ring_dir = HAL_SRNG_DIR_SRC, 90 .max_size = HAL_CE_SRC_RING_BASE_MSB_RING_SIZE, 91 }, 92 [HAL_CE_DST] = { 93 .start_ring_id = HAL_SRNG_RING_ID_CE0_DST, 94 .max_rings = 16, 95 .entry_size = sizeof(struct hal_ce_srng_dest_desc) >> 2, 96 .mac_type = ATH12K_HAL_SRNG_UMAC, 97 .ring_dir = HAL_SRNG_DIR_SRC, 98 .max_size = HAL_CE_DST_RING_BASE_MSB_RING_SIZE, 99 }, 100 [HAL_CE_DST_STATUS] = { 101 .start_ring_id = HAL_SRNG_RING_ID_CE0_DST_STATUS, 102 .max_rings = 16, 103 .entry_size = sizeof(struct hal_ce_srng_dst_status_desc) >> 2, 104 .mac_type = ATH12K_HAL_SRNG_UMAC, 105 .ring_dir = HAL_SRNG_DIR_DST, 106 .max_size = HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE, 107 }, 108 [HAL_WBM_IDLE_LINK] = { 109 .start_ring_id = HAL_SRNG_RING_ID_WBM_IDLE_LINK, 110 .max_rings = 1, 111 .entry_size = sizeof(struct hal_wbm_link_desc) >> 2, 112 .mac_type = ATH12K_HAL_SRNG_UMAC, 113 .ring_dir = HAL_SRNG_DIR_SRC, 114 .max_size = HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE, 115 }, 116 [HAL_SW2WBM_RELEASE] = { 117 .start_ring_id = HAL_SRNG_RING_ID_WBM_SW0_RELEASE, 118 .max_rings = 2, 119 .entry_size = sizeof(struct hal_wbm_release_ring) >> 2, 120 .mac_type = ATH12K_HAL_SRNG_UMAC, 121 .ring_dir = HAL_SRNG_DIR_SRC, 122 .max_size = HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE, 123 }, 124 [HAL_WBM2SW_RELEASE] = { 125 .start_ring_id = HAL_SRNG_RING_ID_WBM2SW0_RELEASE, 126 .max_rings = 8, 127 .entry_size = sizeof(struct hal_wbm_release_ring) >> 2, 128 .mac_type = ATH12K_HAL_SRNG_UMAC, 129 .ring_dir = HAL_SRNG_DIR_DST, 130 .max_size = HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE, 131 }, 132 [HAL_RXDMA_BUF] = { 133 .start_ring_id = HAL_SRNG_SW2RXDMA_BUF0, 134 .max_rings = 1, 135 .entry_size = sizeof(struct hal_wbm_buffer_ring) >> 2, 136 .mac_type = ATH12K_HAL_SRNG_DMAC, 137 .ring_dir = HAL_SRNG_DIR_SRC, 138 .max_size = HAL_RXDMA_RING_MAX_SIZE_BE, 139 }, 140 [HAL_RXDMA_DST] = { 141 .start_ring_id = HAL_SRNG_RING_ID_WMAC1_RXDMA2SW0, 142 .max_rings = 0, 143 .entry_size = 0, 144 .mac_type = ATH12K_HAL_SRNG_PMAC, 145 .ring_dir = HAL_SRNG_DIR_DST, 146 .max_size = HAL_RXDMA_RING_MAX_SIZE_BE, 147 }, 148 [HAL_RXDMA_MONITOR_BUF] = { 149 .start_ring_id = HAL_SRNG_SW2RXMON_BUF0, 150 .max_rings = 1, 151 .entry_size = sizeof(struct hal_mon_buf_ring) >> 2, 152 .mac_type = ATH12K_HAL_SRNG_PMAC, 153 .ring_dir = HAL_SRNG_DIR_SRC, 154 .max_size = HAL_RXDMA_RING_MAX_SIZE_BE, 155 }, 156 [HAL_RXDMA_MONITOR_STATUS] = { 157 .start_ring_id = HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_STATBUF, 158 .max_rings = 1, 159 .entry_size = sizeof(struct hal_wbm_buffer_ring) >> 2, 160 .mac_type = ATH12K_HAL_SRNG_PMAC, 161 .ring_dir = HAL_SRNG_DIR_SRC, 162 .max_size = HAL_RXDMA_RING_MAX_SIZE_BE, 163 }, 164 [HAL_RXDMA_MONITOR_DESC] = { 0, }, 165 [HAL_RXDMA_DIR_BUF] = { 166 .start_ring_id = HAL_SRNG_RING_ID_RXDMA_DIR_BUF, 167 .max_rings = 2, 168 .entry_size = 8 >> 2, /* TODO: Define the struct */ 169 .mac_type = ATH12K_HAL_SRNG_PMAC, 170 .ring_dir = HAL_SRNG_DIR_SRC, 171 .max_size = HAL_RXDMA_RING_MAX_SIZE_BE, 172 }, 173 [HAL_PPE2TCL] = { 174 .start_ring_id = HAL_SRNG_RING_ID_PPE2TCL1, 175 .max_rings = 1, 176 .entry_size = sizeof(struct hal_tcl_entrance_from_ppe_ring) >> 2, 177 .mac_type = ATH12K_HAL_SRNG_PMAC, 178 .ring_dir = HAL_SRNG_DIR_SRC, 179 .max_size = HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE, 180 }, 181 [HAL_PPE_RELEASE] = { 182 .start_ring_id = HAL_SRNG_RING_ID_WBM_PPE_RELEASE, 183 .max_rings = 1, 184 .entry_size = sizeof(struct hal_wbm_release_ring) >> 2, 185 .mac_type = ATH12K_HAL_SRNG_PMAC, 186 .ring_dir = HAL_SRNG_DIR_SRC, 187 .max_size = HAL_WBM2PPE_RELEASE_RING_BASE_MSB_RING_SIZE, 188 }, 189 [HAL_TX_MONITOR_BUF] = { 190 .start_ring_id = HAL_SRNG_RING_ID_WMAC1_SW2TXMON_BUF0, 191 .max_rings = 1, 192 .entry_size = sizeof(struct hal_mon_buf_ring) >> 2, 193 .mac_type = ATH12K_HAL_SRNG_PMAC, 194 .ring_dir = HAL_SRNG_DIR_SRC, 195 .max_size = HAL_RXDMA_RING_MAX_SIZE_BE, 196 }, 197 [HAL_RXDMA_MONITOR_DST] = { 198 .start_ring_id = HAL_SRNG_RING_ID_WMAC1_SW2RXMON_BUF0, 199 .max_rings = 1, 200 .entry_size = sizeof(struct hal_mon_dest_desc) >> 2, 201 .mac_type = ATH12K_HAL_SRNG_PMAC, 202 .ring_dir = HAL_SRNG_DIR_DST, 203 .max_size = HAL_RXDMA_RING_MAX_SIZE_BE, 204 }, 205 [HAL_TX_MONITOR_DST] = { 206 .start_ring_id = HAL_SRNG_RING_ID_WMAC1_TXMON2SW0_BUF0, 207 .max_rings = 1, 208 .entry_size = sizeof(struct hal_mon_dest_desc) >> 2, 209 .mac_type = ATH12K_HAL_SRNG_PMAC, 210 .ring_dir = HAL_SRNG_DIR_DST, 211 .max_size = HAL_RXDMA_RING_MAX_SIZE_BE, 212 } 213 }; 214 215 const struct ath12k_hw_regs qcn9274_v1_regs = { 216 /* SW2TCL(x) R0 ring configuration address */ 217 .tcl1_ring_id = 0x00000908, 218 .tcl1_ring_misc = 0x00000910, 219 .tcl1_ring_tp_addr_lsb = 0x0000091c, 220 .tcl1_ring_tp_addr_msb = 0x00000920, 221 .tcl1_ring_consumer_int_setup_ix0 = 0x00000930, 222 .tcl1_ring_consumer_int_setup_ix1 = 0x00000934, 223 .tcl1_ring_msi1_base_lsb = 0x00000948, 224 .tcl1_ring_msi1_base_msb = 0x0000094c, 225 .tcl1_ring_msi1_data = 0x00000950, 226 .tcl_ring_base_lsb = 0x00000b58, 227 .tcl1_ring_base_lsb = 0x00000900, 228 .tcl1_ring_base_msb = 0x00000904, 229 .tcl2_ring_base_lsb = 0x00000978, 230 231 /* TCL STATUS ring address */ 232 .tcl_status_ring_base_lsb = 0x00000d38, 233 234 .wbm_idle_ring_base_lsb = 0x00000d0c, 235 .wbm_idle_ring_misc_addr = 0x00000d1c, 236 .wbm_r0_idle_list_cntl_addr = 0x00000210, 237 .wbm_r0_idle_list_size_addr = 0x00000214, 238 .wbm_scattered_ring_base_lsb = 0x00000220, 239 .wbm_scattered_ring_base_msb = 0x00000224, 240 .wbm_scattered_desc_head_info_ix0 = 0x00000230, 241 .wbm_scattered_desc_head_info_ix1 = 0x00000234, 242 .wbm_scattered_desc_tail_info_ix0 = 0x00000240, 243 .wbm_scattered_desc_tail_info_ix1 = 0x00000244, 244 .wbm_scattered_desc_ptr_hp_addr = 0x0000024c, 245 246 .wbm_sw_release_ring_base_lsb = 0x0000034c, 247 .wbm_sw1_release_ring_base_lsb = 0x000003c4, 248 .wbm0_release_ring_base_lsb = 0x00000dd8, 249 .wbm1_release_ring_base_lsb = 0x00000e50, 250 251 /* PCIe base address */ 252 .pcie_qserdes_sysclk_en_sel = 0x01e0c0a8, 253 .pcie_pcs_osc_dtct_config_base = 0x01e0d45c, 254 255 /* PPE release ring address */ 256 .ppe_rel_ring_base = 0x0000043c, 257 258 /* REO DEST ring address */ 259 .reo2_ring_base = 0x0000055c, 260 .reo1_misc_ctrl_addr = 0x00000b7c, 261 .reo1_sw_cookie_cfg0 = 0x00000050, 262 .reo1_sw_cookie_cfg1 = 0x00000054, 263 .reo1_qdesc_lut_base0 = 0x00000058, 264 .reo1_qdesc_lut_base1 = 0x0000005c, 265 .reo1_ring_base_lsb = 0x000004e4, 266 .reo1_ring_base_msb = 0x000004e8, 267 .reo1_ring_id = 0x000004ec, 268 .reo1_ring_misc = 0x000004f4, 269 .reo1_ring_hp_addr_lsb = 0x000004f8, 270 .reo1_ring_hp_addr_msb = 0x000004fc, 271 .reo1_ring_producer_int_setup = 0x00000508, 272 .reo1_ring_msi1_base_lsb = 0x0000052C, 273 .reo1_ring_msi1_base_msb = 0x00000530, 274 .reo1_ring_msi1_data = 0x00000534, 275 .reo1_aging_thres_ix0 = 0x00000b08, 276 .reo1_aging_thres_ix1 = 0x00000b0c, 277 .reo1_aging_thres_ix2 = 0x00000b10, 278 .reo1_aging_thres_ix3 = 0x00000b14, 279 280 /* REO Exception ring address */ 281 .reo2_sw0_ring_base = 0x000008a4, 282 283 /* REO Reinject ring address */ 284 .sw2reo_ring_base = 0x00000304, 285 .sw2reo1_ring_base = 0x0000037c, 286 287 /* REO cmd ring address */ 288 .reo_cmd_ring_base = 0x0000028c, 289 290 /* REO status ring address */ 291 .reo_status_ring_base = 0x00000a84, 292 293 /* CE base address */ 294 .umac_ce0_src_reg_base = 0x01b80000, 295 .umac_ce0_dest_reg_base = 0x01b81000, 296 .umac_ce1_src_reg_base = 0x01b82000, 297 .umac_ce1_dest_reg_base = 0x01b83000, 298 299 .gcc_gcc_pcie_hot_rst = 0x1e38338, 300 301 .qrtr_node_id = 0x1e03164, 302 }; 303 304 const struct ath12k_hw_regs qcn9274_v2_regs = { 305 /* SW2TCL(x) R0 ring configuration address */ 306 .tcl1_ring_id = 0x00000908, 307 .tcl1_ring_misc = 0x00000910, 308 .tcl1_ring_tp_addr_lsb = 0x0000091c, 309 .tcl1_ring_tp_addr_msb = 0x00000920, 310 .tcl1_ring_consumer_int_setup_ix0 = 0x00000930, 311 .tcl1_ring_consumer_int_setup_ix1 = 0x00000934, 312 .tcl1_ring_msi1_base_lsb = 0x00000948, 313 .tcl1_ring_msi1_base_msb = 0x0000094c, 314 .tcl1_ring_msi1_data = 0x00000950, 315 .tcl_ring_base_lsb = 0x00000b58, 316 .tcl1_ring_base_lsb = 0x00000900, 317 .tcl1_ring_base_msb = 0x00000904, 318 .tcl2_ring_base_lsb = 0x00000978, 319 320 /* TCL STATUS ring address */ 321 .tcl_status_ring_base_lsb = 0x00000d38, 322 323 /* WBM idle link ring address */ 324 .wbm_idle_ring_base_lsb = 0x00000d3c, 325 .wbm_idle_ring_misc_addr = 0x00000d4c, 326 .wbm_r0_idle_list_cntl_addr = 0x00000240, 327 .wbm_r0_idle_list_size_addr = 0x00000244, 328 .wbm_scattered_ring_base_lsb = 0x00000250, 329 .wbm_scattered_ring_base_msb = 0x00000254, 330 .wbm_scattered_desc_head_info_ix0 = 0x00000260, 331 .wbm_scattered_desc_head_info_ix1 = 0x00000264, 332 .wbm_scattered_desc_tail_info_ix0 = 0x00000270, 333 .wbm_scattered_desc_tail_info_ix1 = 0x00000274, 334 .wbm_scattered_desc_ptr_hp_addr = 0x0000027c, 335 336 /* SW2WBM release ring address */ 337 .wbm_sw_release_ring_base_lsb = 0x0000037c, 338 .wbm_sw1_release_ring_base_lsb = 0x000003f4, 339 340 /* WBM2SW release ring address */ 341 .wbm0_release_ring_base_lsb = 0x00000e08, 342 .wbm1_release_ring_base_lsb = 0x00000e80, 343 344 /* PCIe base address */ 345 .pcie_qserdes_sysclk_en_sel = 0x01e0c0a8, 346 .pcie_pcs_osc_dtct_config_base = 0x01e0d45c, 347 348 /* PPE release ring address */ 349 .ppe_rel_ring_base = 0x0000046c, 350 351 /* REO DEST ring address */ 352 .reo2_ring_base = 0x00000578, 353 .reo1_misc_ctrl_addr = 0x00000b9c, 354 .reo1_sw_cookie_cfg0 = 0x0000006c, 355 .reo1_sw_cookie_cfg1 = 0x00000070, 356 .reo1_qdesc_lut_base0 = 0x00000074, 357 .reo1_qdesc_lut_base1 = 0x00000078, 358 .reo1_qdesc_addr = 0x0000007c, 359 .reo1_qdesc_max_peerid = 0x00000088, 360 .reo1_ring_base_lsb = 0x00000500, 361 .reo1_ring_base_msb = 0x00000504, 362 .reo1_ring_id = 0x00000508, 363 .reo1_ring_misc = 0x00000510, 364 .reo1_ring_hp_addr_lsb = 0x00000514, 365 .reo1_ring_hp_addr_msb = 0x00000518, 366 .reo1_ring_producer_int_setup = 0x00000524, 367 .reo1_ring_msi1_base_lsb = 0x00000548, 368 .reo1_ring_msi1_base_msb = 0x0000054C, 369 .reo1_ring_msi1_data = 0x00000550, 370 .reo1_aging_thres_ix0 = 0x00000B28, 371 .reo1_aging_thres_ix1 = 0x00000B2C, 372 .reo1_aging_thres_ix2 = 0x00000B30, 373 .reo1_aging_thres_ix3 = 0x00000B34, 374 375 /* REO Exception ring address */ 376 .reo2_sw0_ring_base = 0x000008c0, 377 378 /* REO Reinject ring address */ 379 .sw2reo_ring_base = 0x00000320, 380 .sw2reo1_ring_base = 0x00000398, 381 382 /* REO cmd ring address */ 383 .reo_cmd_ring_base = 0x000002A8, 384 385 /* REO status ring address */ 386 .reo_status_ring_base = 0x00000aa0, 387 388 /* CE base address */ 389 .umac_ce0_src_reg_base = 0x01b80000, 390 .umac_ce0_dest_reg_base = 0x01b81000, 391 .umac_ce1_src_reg_base = 0x01b82000, 392 .umac_ce1_dest_reg_base = 0x01b83000, 393 394 .gcc_gcc_pcie_hot_rst = 0x1e38338, 395 396 .qrtr_node_id = 0x1e03164, 397 }; 398 399 const struct ath12k_hw_regs ipq5332_regs = { 400 /* SW2TCL(x) R0 ring configuration address */ 401 .tcl1_ring_id = 0x00000918, 402 .tcl1_ring_misc = 0x00000920, 403 .tcl1_ring_tp_addr_lsb = 0x0000092c, 404 .tcl1_ring_tp_addr_msb = 0x00000930, 405 .tcl1_ring_consumer_int_setup_ix0 = 0x00000940, 406 .tcl1_ring_consumer_int_setup_ix1 = 0x00000944, 407 .tcl1_ring_msi1_base_lsb = 0x00000958, 408 .tcl1_ring_msi1_base_msb = 0x0000095c, 409 .tcl1_ring_base_lsb = 0x00000910, 410 .tcl1_ring_base_msb = 0x00000914, 411 .tcl1_ring_msi1_data = 0x00000960, 412 .tcl2_ring_base_lsb = 0x00000988, 413 .tcl_ring_base_lsb = 0x00000b68, 414 415 /* TCL STATUS ring address */ 416 .tcl_status_ring_base_lsb = 0x00000d48, 417 418 /* REO DEST ring address */ 419 .reo2_ring_base = 0x00000578, 420 .reo1_misc_ctrl_addr = 0x00000b9c, 421 .reo1_sw_cookie_cfg0 = 0x0000006c, 422 .reo1_sw_cookie_cfg1 = 0x00000070, 423 .reo1_qdesc_lut_base0 = 0x00000074, 424 .reo1_qdesc_lut_base1 = 0x00000078, 425 .reo1_ring_base_lsb = 0x00000500, 426 .reo1_ring_base_msb = 0x00000504, 427 .reo1_ring_id = 0x00000508, 428 .reo1_ring_misc = 0x00000510, 429 .reo1_ring_hp_addr_lsb = 0x00000514, 430 .reo1_ring_hp_addr_msb = 0x00000518, 431 .reo1_ring_producer_int_setup = 0x00000524, 432 .reo1_ring_msi1_base_lsb = 0x00000548, 433 .reo1_ring_msi1_base_msb = 0x0000054C, 434 .reo1_ring_msi1_data = 0x00000550, 435 .reo1_aging_thres_ix0 = 0x00000B28, 436 .reo1_aging_thres_ix1 = 0x00000B2C, 437 .reo1_aging_thres_ix2 = 0x00000B30, 438 .reo1_aging_thres_ix3 = 0x00000B34, 439 440 /* REO Exception ring address */ 441 .reo2_sw0_ring_base = 0x000008c0, 442 443 /* REO Reinject ring address */ 444 .sw2reo_ring_base = 0x00000320, 445 .sw2reo1_ring_base = 0x00000398, 446 447 /* REO cmd ring address */ 448 .reo_cmd_ring_base = 0x000002A8, 449 450 /* REO status ring address */ 451 .reo_status_ring_base = 0x00000aa0, 452 453 /* WBM idle link ring address */ 454 .wbm_idle_ring_base_lsb = 0x00000d3c, 455 .wbm_idle_ring_misc_addr = 0x00000d4c, 456 .wbm_r0_idle_list_cntl_addr = 0x00000240, 457 .wbm_r0_idle_list_size_addr = 0x00000244, 458 .wbm_scattered_ring_base_lsb = 0x00000250, 459 .wbm_scattered_ring_base_msb = 0x00000254, 460 .wbm_scattered_desc_head_info_ix0 = 0x00000260, 461 .wbm_scattered_desc_head_info_ix1 = 0x00000264, 462 .wbm_scattered_desc_tail_info_ix0 = 0x00000270, 463 .wbm_scattered_desc_tail_info_ix1 = 0x00000274, 464 .wbm_scattered_desc_ptr_hp_addr = 0x0000027c, 465 466 /* SW2WBM release ring address */ 467 .wbm_sw_release_ring_base_lsb = 0x0000037c, 468 469 /* WBM2SW release ring address */ 470 .wbm0_release_ring_base_lsb = 0x00000e08, 471 .wbm1_release_ring_base_lsb = 0x00000e80, 472 473 /* PPE release ring address */ 474 .ppe_rel_ring_base = 0x0000046c, 475 476 /* CE address */ 477 .umac_ce0_src_reg_base = 0x00740000 - 478 HAL_IPQ5332_CE_WFSS_REG_BASE, 479 .umac_ce0_dest_reg_base = 0x00741000 - 480 HAL_IPQ5332_CE_WFSS_REG_BASE, 481 .umac_ce1_src_reg_base = 0x00742000 - 482 HAL_IPQ5332_CE_WFSS_REG_BASE, 483 .umac_ce1_dest_reg_base = 0x00743000 - 484 HAL_IPQ5332_CE_WFSS_REG_BASE, 485 }; 486 487 static inline 488 bool ath12k_hal_rx_desc_get_first_msdu_qcn9274(struct hal_rx_desc *desc) 489 { 490 return !!le16_get_bits(desc->u.qcn9274_compact.msdu_end.info5, 491 RX_MSDU_END_INFO5_FIRST_MSDU); 492 } 493 494 static inline 495 bool ath12k_hal_rx_desc_get_last_msdu_qcn9274(struct hal_rx_desc *desc) 496 { 497 return !!le16_get_bits(desc->u.qcn9274_compact.msdu_end.info5, 498 RX_MSDU_END_INFO5_LAST_MSDU); 499 } 500 501 u8 ath12k_hal_rx_desc_get_l3_pad_bytes_qcn9274(struct hal_rx_desc *desc) 502 { 503 return le16_get_bits(desc->u.qcn9274_compact.msdu_end.info5, 504 RX_MSDU_END_INFO5_L3_HDR_PADDING); 505 } 506 507 static inline 508 bool ath12k_hal_rx_desc_encrypt_valid_qcn9274(struct hal_rx_desc *desc) 509 { 510 return !!le32_get_bits(desc->u.qcn9274_compact.mpdu_start.info4, 511 RX_MPDU_START_INFO4_ENCRYPT_INFO_VALID); 512 } 513 514 static inline 515 u32 ath12k_hal_rx_desc_get_encrypt_type_qcn9274(struct hal_rx_desc *desc) 516 { 517 if (!ath12k_hal_rx_desc_encrypt_valid_qcn9274(desc)) 518 return HAL_ENCRYPT_TYPE_OPEN; 519 520 return le32_get_bits(desc->u.qcn9274_compact.mpdu_start.info2, 521 RX_MPDU_START_INFO2_ENC_TYPE); 522 } 523 524 static inline 525 u8 ath12k_hal_rx_desc_get_decap_type_qcn9274(struct hal_rx_desc *desc) 526 { 527 return le32_get_bits(desc->u.qcn9274_compact.msdu_end.info11, 528 RX_MSDU_END_INFO11_DECAP_FORMAT); 529 } 530 531 static inline 532 u8 ath12k_hal_rx_desc_get_mesh_ctl_qcn9274(struct hal_rx_desc *desc) 533 { 534 return le32_get_bits(desc->u.qcn9274_compact.msdu_end.info11, 535 RX_MSDU_END_INFO11_MESH_CTRL_PRESENT); 536 } 537 538 static inline 539 bool ath12k_hal_rx_desc_get_mpdu_seq_ctl_vld_qcn9274(struct hal_rx_desc *desc) 540 { 541 return !!le32_get_bits(desc->u.qcn9274_compact.mpdu_start.info4, 542 RX_MPDU_START_INFO4_MPDU_SEQ_CTRL_VALID); 543 } 544 545 static inline 546 bool ath12k_hal_rx_desc_get_mpdu_fc_valid_qcn9274(struct hal_rx_desc *desc) 547 { 548 return !!le32_get_bits(desc->u.qcn9274_compact.mpdu_start.info4, 549 RX_MPDU_START_INFO4_MPDU_FCTRL_VALID); 550 } 551 552 static inline 553 u16 ath12k_hal_rx_desc_get_mpdu_start_seq_no_qcn9274(struct hal_rx_desc *desc) 554 { 555 return le32_get_bits(desc->u.qcn9274_compact.mpdu_start.info4, 556 RX_MPDU_START_INFO4_MPDU_SEQ_NUM); 557 } 558 559 static inline 560 u16 ath12k_hal_rx_desc_get_msdu_len_qcn9274(struct hal_rx_desc *desc) 561 { 562 return le32_get_bits(desc->u.qcn9274_compact.msdu_end.info10, 563 RX_MSDU_END_INFO10_MSDU_LENGTH); 564 } 565 566 static inline 567 u8 ath12k_hal_rx_desc_get_msdu_sgi_qcn9274(struct hal_rx_desc *desc) 568 { 569 return le32_get_bits(desc->u.qcn9274_compact.msdu_end.info12, 570 RX_MSDU_END_INFO12_SGI); 571 } 572 573 static inline 574 u8 ath12k_hal_rx_desc_get_msdu_rate_mcs_qcn9274(struct hal_rx_desc *desc) 575 { 576 return le32_get_bits(desc->u.qcn9274_compact.msdu_end.info12, 577 RX_MSDU_END_INFO12_RATE_MCS); 578 } 579 580 static inline 581 u8 ath12k_hal_rx_desc_get_msdu_rx_bw_qcn9274(struct hal_rx_desc *desc) 582 { 583 return le32_get_bits(desc->u.qcn9274_compact.msdu_end.info12, 584 RX_MSDU_END_INFO12_RECV_BW); 585 } 586 587 static inline 588 u32 ath12k_hal_rx_desc_get_msdu_freq_qcn9274(struct hal_rx_desc *desc) 589 { 590 return __le32_to_cpu(desc->u.qcn9274_compact.msdu_end.phy_meta_data); 591 } 592 593 static inline 594 u8 ath12k_hal_rx_desc_get_msdu_pkt_type_qcn9274(struct hal_rx_desc *desc) 595 { 596 return le32_get_bits(desc->u.qcn9274_compact.msdu_end.info12, 597 RX_MSDU_END_INFO12_PKT_TYPE); 598 } 599 600 static inline 601 u8 ath12k_hal_rx_desc_get_msdu_nss_qcn9274(struct hal_rx_desc *desc) 602 { 603 return le32_get_bits(desc->u.qcn9274_compact.msdu_end.info12, 604 RX_MSDU_END_INFO12_MIMO_SS_BITMAP); 605 } 606 607 static inline 608 u8 ath12k_hal_rx_desc_get_mpdu_tid_qcn9274(struct hal_rx_desc *desc) 609 { 610 return le16_get_bits(desc->u.qcn9274_compact.msdu_end.info5, 611 RX_MSDU_END_INFO5_TID); 612 } 613 614 static inline 615 u16 ath12k_hal_rx_desc_get_mpdu_peer_id_qcn9274(struct hal_rx_desc *desc) 616 { 617 return __le16_to_cpu(desc->u.qcn9274_compact.mpdu_start.sw_peer_id); 618 } 619 620 void ath12k_hal_rx_desc_copy_end_tlv_qcn9274(struct hal_rx_desc *fdesc, 621 struct hal_rx_desc *ldesc) 622 { 623 fdesc->u.qcn9274_compact.msdu_end = ldesc->u.qcn9274_compact.msdu_end; 624 } 625 626 u32 ath12k_hal_rx_desc_get_mpdu_ppdu_id_qcn9274(struct hal_rx_desc *desc) 627 { 628 return __le16_to_cpu(desc->u.qcn9274_compact.mpdu_start.phy_ppdu_id); 629 } 630 631 void ath12k_hal_rx_desc_set_msdu_len_qcn9274(struct hal_rx_desc *desc, u16 len) 632 { 633 u32 info = __le32_to_cpu(desc->u.qcn9274_compact.msdu_end.info10); 634 635 info = u32_replace_bits(info, len, RX_MSDU_END_INFO10_MSDU_LENGTH); 636 desc->u.qcn9274_compact.msdu_end.info10 = __cpu_to_le32(info); 637 } 638 639 u8 *ath12k_hal_rx_desc_get_msdu_payload_qcn9274(struct hal_rx_desc *desc) 640 { 641 return &desc->u.qcn9274_compact.msdu_payload[0]; 642 } 643 644 u32 ath12k_hal_rx_desc_get_mpdu_start_offset_qcn9274(void) 645 { 646 return offsetof(struct hal_rx_desc_qcn9274_compact, mpdu_start); 647 } 648 649 u32 ath12k_hal_rx_desc_get_msdu_end_offset_qcn9274(void) 650 { 651 return offsetof(struct hal_rx_desc_qcn9274_compact, msdu_end); 652 } 653 654 static inline 655 bool ath12k_hal_rx_desc_mac_addr2_valid_qcn9274(struct hal_rx_desc *desc) 656 { 657 return __le32_to_cpu(desc->u.qcn9274_compact.mpdu_start.info4) & 658 RX_MPDU_START_INFO4_MAC_ADDR2_VALID; 659 } 660 661 static inline 662 u8 *ath12k_hal_rx_desc_mpdu_start_addr2_qcn9274(struct hal_rx_desc *desc) 663 { 664 return desc->u.qcn9274_compact.mpdu_start.addr2; 665 } 666 667 static inline 668 bool ath12k_hal_rx_desc_is_da_mcbc_qcn9274(struct hal_rx_desc *desc) 669 { 670 return __le16_to_cpu(desc->u.qcn9274_compact.msdu_end.info5) & 671 RX_MSDU_END_INFO5_DA_IS_MCBC; 672 } 673 674 static inline 675 bool ath12k_hal_rx_h_msdu_done_qcn9274(struct hal_rx_desc *desc) 676 { 677 return !!le32_get_bits(desc->u.qcn9274_compact.msdu_end.info14, 678 RX_MSDU_END_INFO14_MSDU_DONE); 679 } 680 681 static inline 682 bool ath12k_hal_rx_h_l4_cksum_fail_qcn9274(struct hal_rx_desc *desc) 683 { 684 return !!le32_get_bits(desc->u.qcn9274_compact.msdu_end.info13, 685 RX_MSDU_END_INFO13_TCP_UDP_CKSUM_FAIL); 686 } 687 688 static inline 689 bool ath12k_hal_rx_h_ip_cksum_fail_qcn9274(struct hal_rx_desc *desc) 690 { 691 return !!le32_get_bits(desc->u.qcn9274_compact.msdu_end.info13, 692 RX_MSDU_END_INFO13_IP_CKSUM_FAIL); 693 } 694 695 static inline 696 bool ath12k_hal_rx_h_is_decrypted_qcn9274(struct hal_rx_desc *desc) 697 { 698 return (le32_get_bits(desc->u.qcn9274_compact.msdu_end.info14, 699 RX_MSDU_END_INFO14_DECRYPT_STATUS_CODE) == 700 RX_DESC_DECRYPT_STATUS_CODE_OK); 701 } 702 703 u32 ath12k_hal_get_rx_desc_size_qcn9274(void) 704 { 705 return sizeof(struct hal_rx_desc_qcn9274_compact); 706 } 707 708 u8 ath12k_hal_rx_desc_get_msdu_src_link_qcn9274(struct hal_rx_desc *desc) 709 { 710 return le64_get_bits(desc->u.qcn9274_compact.msdu_end.msdu_end_tag, 711 RX_MSDU_END_64_TLV_SRC_LINK_ID); 712 } 713 714 u16 ath12k_hal_rx_mpdu_start_wmask_get_qcn9274(void) 715 { 716 return QCN9274_MPDU_START_WMASK; 717 } 718 719 u32 ath12k_hal_rx_msdu_end_wmask_get_qcn9274(void) 720 { 721 return QCN9274_MSDU_END_WMASK; 722 } 723 724 static u32 ath12k_hal_rx_h_mpdu_err_qcn9274(struct hal_rx_desc *desc) 725 { 726 u32 info = __le32_to_cpu(desc->u.qcn9274_compact.msdu_end.info13); 727 u32 errmap = 0; 728 729 if (info & RX_MSDU_END_INFO13_FCS_ERR) 730 errmap |= HAL_RX_MPDU_ERR_FCS; 731 732 if (info & RX_MSDU_END_INFO13_DECRYPT_ERR) 733 errmap |= HAL_RX_MPDU_ERR_DECRYPT; 734 735 if (info & RX_MSDU_END_INFO13_TKIP_MIC_ERR) 736 errmap |= HAL_RX_MPDU_ERR_TKIP_MIC; 737 738 if (info & RX_MSDU_END_INFO13_A_MSDU_ERROR) 739 errmap |= HAL_RX_MPDU_ERR_AMSDU_ERR; 740 741 if (info & RX_MSDU_END_INFO13_OVERFLOW_ERR) 742 errmap |= HAL_RX_MPDU_ERR_OVERFLOW; 743 744 if (info & RX_MSDU_END_INFO13_MSDU_LEN_ERR) 745 errmap |= HAL_RX_MPDU_ERR_MSDU_LEN; 746 747 if (info & RX_MSDU_END_INFO13_MPDU_LEN_ERR) 748 errmap |= HAL_RX_MPDU_ERR_MPDU_LEN; 749 750 return errmap; 751 } 752 753 void ath12k_hal_rx_desc_get_crypto_hdr_qcn9274(struct hal_rx_desc *desc, 754 u8 *crypto_hdr, 755 enum hal_encrypt_type enctype) 756 { 757 unsigned int key_id; 758 759 switch (enctype) { 760 case HAL_ENCRYPT_TYPE_OPEN: 761 return; 762 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 763 case HAL_ENCRYPT_TYPE_TKIP_MIC: 764 crypto_hdr[0] = 765 HAL_RX_MPDU_INFO_PN_GET_BYTE2(desc->u.qcn9274_compact.mpdu_start.pn[0]); 766 crypto_hdr[1] = 0; 767 crypto_hdr[2] = 768 HAL_RX_MPDU_INFO_PN_GET_BYTE1(desc->u.qcn9274_compact.mpdu_start.pn[0]); 769 break; 770 case HAL_ENCRYPT_TYPE_CCMP_128: 771 case HAL_ENCRYPT_TYPE_CCMP_256: 772 case HAL_ENCRYPT_TYPE_GCMP_128: 773 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 774 crypto_hdr[0] = 775 HAL_RX_MPDU_INFO_PN_GET_BYTE1(desc->u.qcn9274_compact.mpdu_start.pn[0]); 776 crypto_hdr[1] = 777 HAL_RX_MPDU_INFO_PN_GET_BYTE2(desc->u.qcn9274_compact.mpdu_start.pn[0]); 778 crypto_hdr[2] = 0; 779 break; 780 case HAL_ENCRYPT_TYPE_WEP_40: 781 case HAL_ENCRYPT_TYPE_WEP_104: 782 case HAL_ENCRYPT_TYPE_WEP_128: 783 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 784 case HAL_ENCRYPT_TYPE_WAPI: 785 return; 786 } 787 key_id = le32_get_bits(desc->u.qcn9274_compact.mpdu_start.info5, 788 RX_MPDU_START_INFO5_KEY_ID); 789 crypto_hdr[3] = 0x20 | (key_id << 6); 790 crypto_hdr[4] = 791 HAL_RX_MPDU_INFO_PN_GET_BYTE3(desc->u.qcn9274_compact.mpdu_start.pn[0]); 792 crypto_hdr[5] = 793 HAL_RX_MPDU_INFO_PN_GET_BYTE4(desc->u.qcn9274_compact.mpdu_start.pn[0]); 794 crypto_hdr[6] = 795 HAL_RX_MPDU_INFO_PN_GET_BYTE1(desc->u.qcn9274_compact.mpdu_start.pn[1]); 796 crypto_hdr[7] = 797 HAL_RX_MPDU_INFO_PN_GET_BYTE2(desc->u.qcn9274_compact.mpdu_start.pn[1]); 798 } 799 800 void ath12k_hal_rx_desc_get_dot11_hdr_qcn9274(struct hal_rx_desc *desc, 801 struct ieee80211_hdr *hdr) 802 { 803 hdr->frame_control = desc->u.qcn9274_compact.mpdu_start.frame_ctrl; 804 hdr->duration_id = desc->u.qcn9274_compact.mpdu_start.duration; 805 ether_addr_copy(hdr->addr1, desc->u.qcn9274_compact.mpdu_start.addr1); 806 ether_addr_copy(hdr->addr2, desc->u.qcn9274_compact.mpdu_start.addr2); 807 ether_addr_copy(hdr->addr3, desc->u.qcn9274_compact.mpdu_start.addr3); 808 if (__le32_to_cpu(desc->u.qcn9274_compact.mpdu_start.info4) & 809 RX_MPDU_START_INFO4_MAC_ADDR4_VALID) { 810 ether_addr_copy(hdr->addr4, desc->u.qcn9274_compact.mpdu_start.addr4); 811 } 812 hdr->seq_ctrl = desc->u.qcn9274_compact.mpdu_start.seq_ctrl; 813 } 814 815 void ath12k_hal_extract_rx_desc_data_qcn9274(struct hal_rx_desc_data *rx_desc_data, 816 struct hal_rx_desc *rx_desc, 817 struct hal_rx_desc *ldesc) 818 { 819 rx_desc_data->is_first_msdu = ath12k_hal_rx_desc_get_first_msdu_qcn9274(ldesc); 820 rx_desc_data->is_last_msdu = ath12k_hal_rx_desc_get_last_msdu_qcn9274(ldesc); 821 rx_desc_data->l3_pad_bytes = ath12k_hal_rx_desc_get_l3_pad_bytes_qcn9274(ldesc); 822 rx_desc_data->enctype = ath12k_hal_rx_desc_get_encrypt_type_qcn9274(rx_desc); 823 rx_desc_data->decap_type = ath12k_hal_rx_desc_get_decap_type_qcn9274(rx_desc); 824 rx_desc_data->mesh_ctrl_present = 825 ath12k_hal_rx_desc_get_mesh_ctl_qcn9274(rx_desc); 826 rx_desc_data->seq_ctl_valid = 827 ath12k_hal_rx_desc_get_mpdu_seq_ctl_vld_qcn9274(rx_desc); 828 rx_desc_data->fc_valid = ath12k_hal_rx_desc_get_mpdu_fc_valid_qcn9274(rx_desc); 829 rx_desc_data->seq_no = ath12k_hal_rx_desc_get_mpdu_start_seq_no_qcn9274(rx_desc); 830 rx_desc_data->msdu_len = ath12k_hal_rx_desc_get_msdu_len_qcn9274(ldesc); 831 rx_desc_data->sgi = ath12k_hal_rx_desc_get_msdu_sgi_qcn9274(rx_desc); 832 rx_desc_data->rate_mcs = ath12k_hal_rx_desc_get_msdu_rate_mcs_qcn9274(rx_desc); 833 rx_desc_data->bw = ath12k_hal_rx_desc_get_msdu_rx_bw_qcn9274(rx_desc); 834 rx_desc_data->phy_meta_data = ath12k_hal_rx_desc_get_msdu_freq_qcn9274(rx_desc); 835 rx_desc_data->pkt_type = ath12k_hal_rx_desc_get_msdu_pkt_type_qcn9274(rx_desc); 836 rx_desc_data->nss = hweight8(ath12k_hal_rx_desc_get_msdu_nss_qcn9274(rx_desc)); 837 rx_desc_data->tid = ath12k_hal_rx_desc_get_mpdu_tid_qcn9274(rx_desc); 838 rx_desc_data->peer_id = ath12k_hal_rx_desc_get_mpdu_peer_id_qcn9274(rx_desc); 839 rx_desc_data->addr2_present = ath12k_hal_rx_desc_mac_addr2_valid_qcn9274(rx_desc); 840 rx_desc_data->addr2 = ath12k_hal_rx_desc_mpdu_start_addr2_qcn9274(rx_desc); 841 rx_desc_data->is_mcbc = ath12k_hal_rx_desc_is_da_mcbc_qcn9274(rx_desc); 842 rx_desc_data->msdu_done = ath12k_hal_rx_h_msdu_done_qcn9274(ldesc); 843 rx_desc_data->l4_csum_fail = ath12k_hal_rx_h_l4_cksum_fail_qcn9274(rx_desc); 844 rx_desc_data->ip_csum_fail = ath12k_hal_rx_h_ip_cksum_fail_qcn9274(rx_desc); 845 rx_desc_data->is_decrypted = ath12k_hal_rx_h_is_decrypted_qcn9274(rx_desc); 846 rx_desc_data->err_bitmap = ath12k_hal_rx_h_mpdu_err_qcn9274(rx_desc); 847 } 848 849 const struct ath12k_hw_hal_params ath12k_hw_hal_params_qcn9274 = { 850 .rx_buf_rbm = HAL_RX_BUF_RBM_SW3_BM, 851 .wbm2sw_cc_enable = HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN | 852 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW1_EN | 853 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN | 854 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN | 855 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN, 856 }; 857 858 const struct ath12k_hw_hal_params ath12k_hw_hal_params_ipq5332 = { 859 .rx_buf_rbm = HAL_RX_BUF_RBM_SW3_BM, 860 .wbm2sw_cc_enable = HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN | 861 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW1_EN | 862 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN | 863 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN | 864 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN, 865 }; 866 867 static int ath12k_hal_srng_create_config_qcn9274(struct ath12k_hal *hal) 868 { 869 struct hal_srng_config *s; 870 871 hal->srng_config = kmemdup(hw_srng_config_template, 872 sizeof(hw_srng_config_template), 873 GFP_KERNEL); 874 if (!hal->srng_config) 875 return -ENOMEM; 876 877 s = &hal->srng_config[HAL_REO_DST]; 878 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_BASE_LSB(hal); 879 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_HP; 880 s->reg_size[0] = HAL_REO2_RING_BASE_LSB(hal) - HAL_REO1_RING_BASE_LSB(hal); 881 s->reg_size[1] = HAL_REO2_RING_HP - HAL_REO1_RING_HP; 882 883 s = &hal->srng_config[HAL_REO_EXCEPTION]; 884 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_SW0_RING_BASE_LSB(hal); 885 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_SW0_RING_HP; 886 887 s = &hal->srng_config[HAL_REO_REINJECT]; 888 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_BASE_LSB(hal); 889 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_HP; 890 s->reg_size[0] = HAL_SW2REO1_RING_BASE_LSB(hal) - HAL_SW2REO_RING_BASE_LSB(hal); 891 s->reg_size[1] = HAL_SW2REO1_RING_HP - HAL_SW2REO_RING_HP; 892 893 s = &hal->srng_config[HAL_REO_CMD]; 894 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_RING_BASE_LSB(hal); 895 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_HP; 896 897 s = &hal->srng_config[HAL_REO_STATUS]; 898 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_RING_BASE_LSB(hal); 899 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_HP; 900 901 s = &hal->srng_config[HAL_TCL_DATA]; 902 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_BASE_LSB(hal); 903 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_HP; 904 s->reg_size[0] = HAL_TCL2_RING_BASE_LSB(hal) - HAL_TCL1_RING_BASE_LSB(hal); 905 s->reg_size[1] = HAL_TCL2_RING_HP - HAL_TCL1_RING_HP; 906 907 s = &hal->srng_config[HAL_TCL_CMD]; 908 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_BASE_LSB(hal); 909 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_HP; 910 911 s = &hal->srng_config[HAL_TCL_STATUS]; 912 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_BASE_LSB(hal); 913 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_HP; 914 915 s = &hal->srng_config[HAL_CE_SRC]; 916 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(hal) + HAL_CE_DST_RING_BASE_LSB; 917 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(hal) + HAL_CE_DST_RING_HP; 918 s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(hal) - 919 HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(hal); 920 s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(hal) - 921 HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(hal); 922 923 s = &hal->srng_config[HAL_CE_DST]; 924 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal) + HAL_CE_DST_RING_BASE_LSB; 925 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal) + HAL_CE_DST_RING_HP; 926 s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(hal) - 927 HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal); 928 s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(hal) - 929 HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal); 930 931 s = &hal->srng_config[HAL_CE_DST_STATUS]; 932 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal) + 933 HAL_CE_DST_STATUS_RING_BASE_LSB; 934 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal) + HAL_CE_DST_STATUS_RING_HP; 935 s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(hal) - 936 HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal); 937 s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(hal) - 938 HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal); 939 940 s = &hal->srng_config[HAL_WBM_IDLE_LINK]; 941 s->reg_start[0] = 942 HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_BASE_LSB(hal); 943 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_HP; 944 945 s = &hal->srng_config[HAL_SW2WBM_RELEASE]; 946 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + 947 HAL_WBM_SW_RELEASE_RING_BASE_LSB(hal); 948 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SW_RELEASE_RING_HP; 949 s->reg_size[0] = HAL_WBM_SW1_RELEASE_RING_BASE_LSB(hal) - 950 HAL_WBM_SW_RELEASE_RING_BASE_LSB(hal); 951 s->reg_size[1] = HAL_WBM_SW1_RELEASE_RING_HP - HAL_WBM_SW_RELEASE_RING_HP; 952 953 s = &hal->srng_config[HAL_WBM2SW_RELEASE]; 954 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_BASE_LSB(hal); 955 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_HP; 956 s->reg_size[0] = HAL_WBM1_RELEASE_RING_BASE_LSB(hal) - 957 HAL_WBM0_RELEASE_RING_BASE_LSB(hal); 958 s->reg_size[1] = HAL_WBM1_RELEASE_RING_HP - HAL_WBM0_RELEASE_RING_HP; 959 960 /* Some LMAC rings are not accessed from the host: 961 * RXDMA_BUG, RXDMA_DST, RXDMA_MONITOR_BUF, RXDMA_MONITOR_STATUS, 962 * RXDMA_MONITOR_DST, RXDMA_MONITOR_DESC, RXDMA_DIR_BUF_SRC, 963 * RXDMA_RX_MONITOR_BUF, TX_MONITOR_BUF, TX_MONITOR_DST, SW2RXDMA 964 */ 965 s = &hal->srng_config[HAL_PPE2TCL]; 966 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_PPE2TCL1_RING_BASE_LSB; 967 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_PPE2TCL1_RING_HP; 968 969 s = &hal->srng_config[HAL_PPE_RELEASE]; 970 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + 971 HAL_WBM_PPE_RELEASE_RING_BASE_LSB(hal); 972 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_PPE_RELEASE_RING_HP; 973 974 return 0; 975 } 976 977 const struct ath12k_hal_tcl_to_wbm_rbm_map 978 ath12k_hal_tcl_to_wbm_rbm_map_qcn9274[DP_TCL_NUM_RING_MAX] = { 979 { 980 .wbm_ring_num = 0, 981 .rbm_id = HAL_RX_BUF_RBM_SW0_BM, 982 }, 983 { 984 .wbm_ring_num = 1, 985 .rbm_id = HAL_RX_BUF_RBM_SW1_BM, 986 }, 987 { 988 .wbm_ring_num = 2, 989 .rbm_id = HAL_RX_BUF_RBM_SW2_BM, 990 }, 991 { 992 .wbm_ring_num = 4, 993 .rbm_id = HAL_RX_BUF_RBM_SW4_BM, 994 }, 995 }; 996 997 const struct hal_ops hal_qcn9274_ops = { 998 .create_srng_config = ath12k_hal_srng_create_config_qcn9274, 999 .rx_desc_set_msdu_len = ath12k_hal_rx_desc_set_msdu_len_qcn9274, 1000 .rx_desc_get_dot11_hdr = ath12k_hal_rx_desc_get_dot11_hdr_qcn9274, 1001 .rx_desc_get_crypto_header = ath12k_hal_rx_desc_get_crypto_hdr_qcn9274, 1002 .rx_desc_copy_end_tlv = ath12k_hal_rx_desc_copy_end_tlv_qcn9274, 1003 .rx_desc_get_msdu_src_link_id = ath12k_hal_rx_desc_get_msdu_src_link_qcn9274, 1004 .extract_rx_desc_data = ath12k_hal_extract_rx_desc_data_qcn9274, 1005 .rx_desc_get_l3_pad_bytes = ath12k_hal_rx_desc_get_l3_pad_bytes_qcn9274, 1006 .rx_desc_get_mpdu_ppdu_id = ath12k_hal_rx_desc_get_mpdu_ppdu_id_qcn9274, 1007 .rx_desc_get_msdu_payload = ath12k_hal_rx_desc_get_msdu_payload_qcn9274, 1008 .ce_dst_setup = ath12k_wifi7_hal_ce_dst_setup, 1009 .srng_src_hw_init = ath12k_wifi7_hal_srng_src_hw_init, 1010 .srng_dst_hw_init = ath12k_wifi7_hal_srng_dst_hw_init, 1011 .set_umac_srng_ptr_addr = ath12k_wifi7_hal_set_umac_srng_ptr_addr, 1012 .srng_update_shadow_config = ath12k_wifi7_hal_srng_update_shadow_config, 1013 .srng_get_ring_id = ath12k_wifi7_hal_srng_get_ring_id, 1014 .ce_get_desc_size = ath12k_wifi7_hal_ce_get_desc_size, 1015 .ce_src_set_desc = ath12k_wifi7_hal_ce_src_set_desc, 1016 .ce_dst_set_desc = ath12k_wifi7_hal_ce_dst_set_desc, 1017 .ce_dst_status_get_length = ath12k_wifi7_hal_ce_dst_status_get_length, 1018 .set_link_desc_addr = ath12k_wifi7_hal_set_link_desc_addr, 1019 .tx_set_dscp_tid_map = ath12k_wifi7_hal_tx_set_dscp_tid_map, 1020 .tx_configure_bank_register = 1021 ath12k_wifi7_hal_tx_configure_bank_register, 1022 .reoq_lut_addr_read_enable = ath12k_wifi7_hal_reoq_lut_addr_read_enable, 1023 .reoq_lut_set_max_peerid = ath12k_wifi7_hal_reoq_lut_set_max_peerid, 1024 .write_reoq_lut_addr = ath12k_wifi7_hal_write_reoq_lut_addr, 1025 .write_ml_reoq_lut_addr = ath12k_wifi7_hal_write_ml_reoq_lut_addr, 1026 .setup_link_idle_list = ath12k_wifi7_hal_setup_link_idle_list, 1027 .reo_init_cmd_ring = ath12k_wifi7_hal_reo_init_cmd_ring_tlv64, 1028 .reo_hw_setup = ath12k_wifi7_hal_reo_hw_setup, 1029 .reo_shared_qaddr_cache_clear = ath12k_wifi7_hal_reo_shared_qaddr_cache_clear, 1030 .rx_buf_addr_info_set = ath12k_wifi7_hal_rx_buf_addr_info_set, 1031 .rx_buf_addr_info_get = ath12k_wifi7_hal_rx_buf_addr_info_get, 1032 .cc_config = ath12k_wifi7_hal_cc_config, 1033 .get_idle_link_rbm = ath12k_wifi7_hal_get_idle_link_rbm, 1034 .rx_msdu_list_get = ath12k_wifi7_hal_rx_msdu_list_get, 1035 .rx_reo_ent_buf_paddr_get = ath12k_wifi7_hal_rx_reo_ent_buf_paddr_get, 1036 .reo_cmd_enc_tlv_hdr = ath12k_hal_encode_tlv64_hdr, 1037 .reo_status_dec_tlv_hdr = ath12k_hal_decode_tlv64_hdr, 1038 }; 1039