1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include "hal_qcc2072.h" 7 #include "hal_wcn7850.h" 8 9 const struct ath12k_hw_regs qcc2072_regs = { 10 /* SW2TCL(x) R0 ring configuration address */ 11 .tcl1_ring_id = 0x00000920, 12 .tcl1_ring_misc = 0x00000928, 13 .tcl1_ring_tp_addr_lsb = 0x00000934, 14 .tcl1_ring_tp_addr_msb = 0x00000938, 15 .tcl1_ring_consumer_int_setup_ix0 = 0x00000948, 16 .tcl1_ring_consumer_int_setup_ix1 = 0x0000094c, 17 .tcl1_ring_msi1_base_lsb = 0x00000960, 18 .tcl1_ring_msi1_base_msb = 0x00000964, 19 .tcl1_ring_msi1_data = 0x00000968, 20 .tcl_ring_base_lsb = 0x00000b70, 21 .tcl1_ring_base_lsb = 0x00000918, 22 .tcl1_ring_base_msb = 0x0000091c, 23 .tcl2_ring_base_lsb = 0x00000990, 24 25 /* TCL STATUS ring address */ 26 .tcl_status_ring_base_lsb = 0x00000d50, 27 28 .wbm_idle_ring_base_lsb = 0x00000d3c, 29 .wbm_idle_ring_misc_addr = 0x00000d4c, 30 .wbm_r0_idle_list_cntl_addr = 0x00000240, 31 .wbm_r0_idle_list_size_addr = 0x00000244, 32 .wbm_scattered_ring_base_lsb = 0x00000250, 33 .wbm_scattered_ring_base_msb = 0x00000254, 34 .wbm_scattered_desc_head_info_ix0 = 0x00000260, 35 .wbm_scattered_desc_head_info_ix1 = 0x00000264, 36 .wbm_scattered_desc_tail_info_ix0 = 0x00000270, 37 .wbm_scattered_desc_tail_info_ix1 = 0x00000274, 38 .wbm_scattered_desc_ptr_hp_addr = 0x00000027c, 39 40 .wbm_sw_release_ring_base_lsb = 0x0000037c, 41 .wbm_sw1_release_ring_base_lsb = ATH12K_HW_REG_UNDEFINED, 42 .wbm0_release_ring_base_lsb = 0x00000e08, 43 .wbm1_release_ring_base_lsb = 0x00000e80, 44 45 /* PCIe base address */ 46 .pcie_qserdes_sysclk_en_sel = 0x01e0c0ac, 47 .pcie_pcs_osc_dtct_config_base = 0x01e0cc58, 48 49 /* PPE release ring address */ 50 .ppe_rel_ring_base = 0x0000046c, 51 52 /* REO DEST ring address */ 53 .reo2_ring_base = 0x00000578, 54 .reo1_misc_ctrl_addr = 0x00000ba0, 55 .reo1_sw_cookie_cfg0 = 0x0000006c, 56 .reo1_sw_cookie_cfg1 = 0x00000070, 57 .reo1_qdesc_lut_base0 = ATH12K_HW_REG_UNDEFINED, 58 .reo1_qdesc_lut_base1 = ATH12K_HW_REG_UNDEFINED, 59 60 .reo1_ring_base_lsb = 0x00000500, 61 .reo1_ring_base_msb = 0x00000504, 62 .reo1_ring_id = 0x00000508, 63 .reo1_ring_misc = 0x00000510, 64 .reo1_ring_hp_addr_lsb = 0x00000514, 65 .reo1_ring_hp_addr_msb = 0x00000518, 66 .reo1_ring_producer_int_setup = 0x00000524, 67 .reo1_ring_msi1_base_lsb = 0x00000548, 68 .reo1_ring_msi1_base_msb = 0x0000054c, 69 .reo1_ring_msi1_data = 0x00000550, 70 .reo1_aging_thres_ix0 = 0x00000b2c, 71 .reo1_aging_thres_ix1 = 0x00000b30, 72 .reo1_aging_thres_ix2 = 0x00000b34, 73 .reo1_aging_thres_ix3 = 0x00000b38, 74 75 /* REO Exception ring address */ 76 .reo2_sw0_ring_base = 0x000008c0, 77 78 /* REO Reinject ring address */ 79 .sw2reo_ring_base = 0x00000320, 80 .sw2reo1_ring_base = 0x00000398, 81 82 /* REO cmd ring address */ 83 .reo_cmd_ring_base = 0x000002a8, 84 85 /* REO status ring address */ 86 .reo_status_ring_base = 0x00000aa0, 87 88 /* CE base address */ 89 .umac_ce0_src_reg_base = 0x01b80000, 90 .umac_ce0_dest_reg_base = 0x01b81000, 91 .umac_ce1_src_reg_base = 0x01b82000, 92 .umac_ce1_dest_reg_base = 0x01b83000, 93 94 .gcc_gcc_pcie_hot_rst = 0x1e65304, 95 96 .qrtr_node_id = 0x1e03300, 97 }; 98 99 static void ath12k_hal_rx_desc_set_msdu_len_qcc2072(struct hal_rx_desc *desc, u16 len) 100 { 101 u32 info = __le32_to_cpu(desc->u.qcc2072.msdu_end.info10); 102 103 info &= ~RX_MSDU_END_INFO10_MSDU_LENGTH; 104 info |= u32_encode_bits(len, RX_MSDU_END_INFO10_MSDU_LENGTH); 105 106 desc->u.qcc2072.msdu_end.info10 = __cpu_to_le32(info); 107 } 108 109 static void ath12k_hal_rx_desc_get_dot11_hdr_qcc2072(struct hal_rx_desc *desc, 110 struct ieee80211_hdr *hdr) 111 { 112 hdr->frame_control = desc->u.qcc2072.mpdu_start.frame_ctrl; 113 hdr->duration_id = desc->u.qcc2072.mpdu_start.duration; 114 ether_addr_copy(hdr->addr1, desc->u.qcc2072.mpdu_start.addr1); 115 ether_addr_copy(hdr->addr2, desc->u.qcc2072.mpdu_start.addr2); 116 ether_addr_copy(hdr->addr3, desc->u.qcc2072.mpdu_start.addr3); 117 118 if (__le32_to_cpu(desc->u.qcc2072.mpdu_start.info4) & 119 RX_MPDU_START_INFO4_MAC_ADDR4_VALID) 120 ether_addr_copy(hdr->addr4, desc->u.qcc2072.mpdu_start.addr4); 121 122 hdr->seq_ctrl = desc->u.qcc2072.mpdu_start.seq_ctrl; 123 } 124 125 static void ath12k_hal_rx_desc_get_crypto_hdr_qcc2072(struct hal_rx_desc *desc, 126 u8 *crypto_hdr, 127 enum hal_encrypt_type enctype) 128 { 129 unsigned int key_id; 130 131 switch (enctype) { 132 case HAL_ENCRYPT_TYPE_OPEN: 133 return; 134 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 135 case HAL_ENCRYPT_TYPE_TKIP_MIC: 136 crypto_hdr[0] = 137 HAL_RX_MPDU_INFO_PN_GET_BYTE2(desc->u.qcc2072.mpdu_start.pn[0]); 138 crypto_hdr[1] = 0; 139 crypto_hdr[2] = 140 HAL_RX_MPDU_INFO_PN_GET_BYTE1(desc->u.qcc2072.mpdu_start.pn[0]); 141 break; 142 case HAL_ENCRYPT_TYPE_CCMP_128: 143 case HAL_ENCRYPT_TYPE_CCMP_256: 144 case HAL_ENCRYPT_TYPE_GCMP_128: 145 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 146 crypto_hdr[0] = 147 HAL_RX_MPDU_INFO_PN_GET_BYTE1(desc->u.qcc2072.mpdu_start.pn[0]); 148 crypto_hdr[1] = 149 HAL_RX_MPDU_INFO_PN_GET_BYTE2(desc->u.qcc2072.mpdu_start.pn[0]); 150 crypto_hdr[2] = 0; 151 break; 152 case HAL_ENCRYPT_TYPE_WEP_40: 153 case HAL_ENCRYPT_TYPE_WEP_104: 154 case HAL_ENCRYPT_TYPE_WEP_128: 155 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 156 case HAL_ENCRYPT_TYPE_WAPI: 157 return; 158 } 159 160 key_id = u32_get_bits(__le32_to_cpu(desc->u.qcc2072.mpdu_start.info5), 161 RX_MPDU_START_INFO5_KEY_ID); 162 crypto_hdr[3] = 0x20 | (key_id << 6); 163 crypto_hdr[4] = HAL_RX_MPDU_INFO_PN_GET_BYTE3(desc->u.qcc2072.mpdu_start.pn[0]); 164 crypto_hdr[5] = HAL_RX_MPDU_INFO_PN_GET_BYTE4(desc->u.qcc2072.mpdu_start.pn[0]); 165 crypto_hdr[6] = HAL_RX_MPDU_INFO_PN_GET_BYTE1(desc->u.qcc2072.mpdu_start.pn[1]); 166 crypto_hdr[7] = HAL_RX_MPDU_INFO_PN_GET_BYTE2(desc->u.qcc2072.mpdu_start.pn[1]); 167 } 168 169 static void ath12k_hal_rx_desc_copy_end_tlv_qcc2072(struct hal_rx_desc *fdesc, 170 struct hal_rx_desc *ldesc) 171 { 172 memcpy(&fdesc->u.qcc2072.msdu_end, &ldesc->u.qcc2072.msdu_end, 173 sizeof(struct rx_msdu_end_qcn9274)); 174 } 175 176 static u8 ath12k_hal_rx_desc_get_msdu_src_link_qcc2072(struct hal_rx_desc *desc) 177 { 178 return 0; 179 } 180 181 static u8 ath12k_hal_rx_desc_get_l3_pad_bytes_qcc2072(struct hal_rx_desc *desc) 182 { 183 return le16_get_bits(desc->u.qcc2072.msdu_end.info5, 184 RX_MSDU_END_INFO5_L3_HDR_PADDING); 185 } 186 187 static u32 ath12k_hal_rx_desc_get_mpdu_start_tag_qcc2072(struct hal_rx_desc *desc) 188 { 189 return le32_get_bits(desc->u.qcc2072.mpdu_start_tag, 190 HAL_TLV_HDR_TAG); 191 } 192 193 static u32 ath12k_hal_rx_desc_get_mpdu_ppdu_id_qcc2072(struct hal_rx_desc *desc) 194 { 195 return __le16_to_cpu(desc->u.qcc2072.mpdu_start.phy_ppdu_id); 196 } 197 198 static u8 *ath12k_hal_rx_desc_get_msdu_payload_qcc2072(struct hal_rx_desc *desc) 199 { 200 return &desc->u.qcc2072.msdu_payload[0]; 201 } 202 203 static bool ath12k_hal_rx_desc_get_first_msdu_qcc2072(struct hal_rx_desc *desc) 204 { 205 return !!le16_get_bits(desc->u.qcc2072.msdu_end.info5, 206 RX_MSDU_END_INFO5_FIRST_MSDU); 207 } 208 209 static bool ath12k_hal_rx_desc_get_last_msdu_qcc2072(struct hal_rx_desc *desc) 210 { 211 return !!le16_get_bits(desc->u.qcc2072.msdu_end.info5, 212 RX_MSDU_END_INFO5_LAST_MSDU); 213 } 214 215 static bool ath12k_hal_rx_desc_encrypt_valid_qcc2072(struct hal_rx_desc *desc) 216 { 217 return !!le32_get_bits(desc->u.qcc2072.mpdu_start.info4, 218 RX_MPDU_START_INFO4_ENCRYPT_INFO_VALID); 219 } 220 221 static u32 ath12k_hal_rx_desc_get_encrypt_type_qcc2072(struct hal_rx_desc *desc) 222 { 223 if (!ath12k_hal_rx_desc_encrypt_valid_qcc2072(desc)) 224 return HAL_ENCRYPT_TYPE_OPEN; 225 226 return le32_get_bits(desc->u.qcc2072.mpdu_start.info2, 227 RX_MPDU_START_INFO2_ENC_TYPE); 228 } 229 230 static u8 ath12k_hal_rx_desc_get_decap_type_qcc2072(struct hal_rx_desc *desc) 231 { 232 return le32_get_bits(desc->u.qcc2072.msdu_end.info11, 233 RX_MSDU_END_INFO11_DECAP_FORMAT); 234 } 235 236 static u8 ath12k_hal_rx_desc_get_mesh_ctl_qcc2072(struct hal_rx_desc *desc) 237 { 238 return le32_get_bits(desc->u.qcc2072.msdu_end.info11, 239 RX_MSDU_END_INFO11_MESH_CTRL_PRESENT); 240 } 241 242 static bool ath12k_hal_rx_desc_get_mpdu_seq_ctl_vld_qcc2072(struct hal_rx_desc *desc) 243 { 244 return !!le32_get_bits(desc->u.qcc2072.mpdu_start.info4, 245 RX_MPDU_START_INFO4_MPDU_SEQ_CTRL_VALID); 246 } 247 248 static bool ath12k_hal_rx_desc_get_mpdu_fc_valid_qcc2072(struct hal_rx_desc *desc) 249 { 250 return !!le32_get_bits(desc->u.qcc2072.mpdu_start.info4, 251 RX_MPDU_START_INFO4_MPDU_FCTRL_VALID); 252 } 253 254 static u16 ath12k_hal_rx_desc_get_mpdu_start_seq_no_qcc2072(struct hal_rx_desc *desc) 255 { 256 return le32_get_bits(desc->u.qcc2072.mpdu_start.info4, 257 RX_MPDU_START_INFO4_MPDU_SEQ_NUM); 258 } 259 260 static u16 ath12k_hal_rx_desc_get_msdu_len_qcc2072(struct hal_rx_desc *desc) 261 { 262 return le32_get_bits(desc->u.qcc2072.msdu_end.info10, 263 RX_MSDU_END_INFO10_MSDU_LENGTH); 264 } 265 266 static u8 ath12k_hal_rx_desc_get_msdu_sgi_qcc2072(struct hal_rx_desc *desc) 267 { 268 return le32_get_bits(desc->u.qcc2072.msdu_end.info12, 269 RX_MSDU_END_INFO12_SGI); 270 } 271 272 static u8 ath12k_hal_rx_desc_get_msdu_rate_mcs_qcc2072(struct hal_rx_desc *desc) 273 { 274 return le32_get_bits(desc->u.qcc2072.msdu_end.info12, 275 RX_MSDU_END_INFO12_RATE_MCS); 276 } 277 278 static u8 ath12k_hal_rx_desc_get_msdu_rx_bw_qcc2072(struct hal_rx_desc *desc) 279 { 280 return le32_get_bits(desc->u.qcc2072.msdu_end.info12, 281 RX_MSDU_END_INFO12_RECV_BW); 282 } 283 284 static u32 ath12k_hal_rx_desc_get_msdu_freq_qcc2072(struct hal_rx_desc *desc) 285 { 286 return __le32_to_cpu(desc->u.qcc2072.msdu_end.phy_meta_data); 287 } 288 289 static u8 ath12k_hal_rx_desc_get_msdu_pkt_type_qcc2072(struct hal_rx_desc *desc) 290 { 291 return le32_get_bits(desc->u.qcc2072.msdu_end.info12, 292 RX_MSDU_END_INFO12_PKT_TYPE); 293 } 294 295 static u8 ath12k_hal_rx_desc_get_msdu_nss_qcc2072(struct hal_rx_desc *desc) 296 { 297 return le32_get_bits(desc->u.qcc2072.msdu_end.info12, 298 RX_MSDU_END_INFO12_MIMO_SS_BITMAP); 299 } 300 301 static u8 ath12k_hal_rx_desc_get_mpdu_tid_qcc2072(struct hal_rx_desc *desc) 302 { 303 return le32_get_bits(desc->u.qcc2072.mpdu_start.info2, 304 RX_MPDU_START_INFO2_TID); 305 } 306 307 static u16 ath12k_hal_rx_desc_get_mpdu_peer_id_qcc2072(struct hal_rx_desc *desc) 308 { 309 return __le16_to_cpu(desc->u.qcc2072.mpdu_start.sw_peer_id); 310 } 311 312 static bool ath12k_hal_rx_desc_mac_addr2_valid_qcc2072(struct hal_rx_desc *desc) 313 { 314 return __le32_to_cpu(desc->u.qcc2072.mpdu_start.info4) & 315 RX_MPDU_START_INFO4_MAC_ADDR2_VALID; 316 } 317 318 static u8 *ath12k_hal_rx_desc_mpdu_start_addr2_qcc2072(struct hal_rx_desc *desc) 319 { 320 return desc->u.qcc2072.mpdu_start.addr2; 321 } 322 323 static bool ath12k_hal_rx_desc_is_da_mcbc_qcc2072(struct hal_rx_desc *desc) 324 { 325 return __le32_to_cpu(desc->u.qcc2072.msdu_end.info13) & 326 RX_MSDU_END_INFO13_MCAST_BCAST; 327 } 328 329 static bool ath12k_hal_rx_h_msdu_done_qcc2072(struct hal_rx_desc *desc) 330 { 331 return !!le32_get_bits(desc->u.qcc2072.msdu_end.info14, 332 RX_MSDU_END_INFO14_MSDU_DONE); 333 } 334 335 static bool ath12k_hal_rx_h_l4_cksum_fail_qcc2072(struct hal_rx_desc *desc) 336 { 337 return !!le32_get_bits(desc->u.qcc2072.msdu_end.info13, 338 RX_MSDU_END_INFO13_TCP_UDP_CKSUM_FAIL); 339 } 340 341 static bool ath12k_hal_rx_h_ip_cksum_fail_qcc2072(struct hal_rx_desc *desc) 342 { 343 return !!le32_get_bits(desc->u.qcc2072.msdu_end.info13, 344 RX_MSDU_END_INFO13_IP_CKSUM_FAIL); 345 } 346 347 static bool ath12k_hal_rx_h_is_decrypted_qcc2072(struct hal_rx_desc *desc) 348 { 349 return (le32_get_bits(desc->u.qcc2072.msdu_end.info14, 350 RX_MSDU_END_INFO14_DECRYPT_STATUS_CODE) == 351 RX_DESC_DECRYPT_STATUS_CODE_OK); 352 } 353 354 static u32 ath12k_hal_rx_h_mpdu_err_qcc2072(struct hal_rx_desc *desc) 355 { 356 u32 info = __le32_to_cpu(desc->u.qcc2072.msdu_end.info13); 357 u32 errmap = 0; 358 359 if (info & RX_MSDU_END_INFO13_FCS_ERR) 360 errmap |= HAL_RX_MPDU_ERR_FCS; 361 362 if (info & RX_MSDU_END_INFO13_DECRYPT_ERR) 363 errmap |= HAL_RX_MPDU_ERR_DECRYPT; 364 365 if (info & RX_MSDU_END_INFO13_TKIP_MIC_ERR) 366 errmap |= HAL_RX_MPDU_ERR_TKIP_MIC; 367 368 if (info & RX_MSDU_END_INFO13_A_MSDU_ERROR) 369 errmap |= HAL_RX_MPDU_ERR_AMSDU_ERR; 370 371 if (info & RX_MSDU_END_INFO13_OVERFLOW_ERR) 372 errmap |= HAL_RX_MPDU_ERR_OVERFLOW; 373 374 if (info & RX_MSDU_END_INFO13_MSDU_LEN_ERR) 375 errmap |= HAL_RX_MPDU_ERR_MSDU_LEN; 376 377 if (info & RX_MSDU_END_INFO13_MPDU_LEN_ERR) 378 errmap |= HAL_RX_MPDU_ERR_MPDU_LEN; 379 380 return errmap; 381 } 382 383 static void ath12k_hal_extract_rx_desc_data_qcc2072(struct hal_rx_desc_data *rx_desc_data, 384 struct hal_rx_desc *rx_desc, 385 struct hal_rx_desc *ldesc) 386 { 387 rx_desc_data->is_first_msdu = ath12k_hal_rx_desc_get_first_msdu_qcc2072(ldesc); 388 rx_desc_data->is_last_msdu = ath12k_hal_rx_desc_get_last_msdu_qcc2072(ldesc); 389 rx_desc_data->l3_pad_bytes = ath12k_hal_rx_desc_get_l3_pad_bytes_qcc2072(ldesc); 390 rx_desc_data->enctype = ath12k_hal_rx_desc_get_encrypt_type_qcc2072(rx_desc); 391 rx_desc_data->decap_type = ath12k_hal_rx_desc_get_decap_type_qcc2072(rx_desc); 392 rx_desc_data->mesh_ctrl_present = 393 ath12k_hal_rx_desc_get_mesh_ctl_qcc2072(rx_desc); 394 rx_desc_data->seq_ctl_valid = 395 ath12k_hal_rx_desc_get_mpdu_seq_ctl_vld_qcc2072(rx_desc); 396 rx_desc_data->fc_valid = ath12k_hal_rx_desc_get_mpdu_fc_valid_qcc2072(rx_desc); 397 rx_desc_data->seq_no = ath12k_hal_rx_desc_get_mpdu_start_seq_no_qcc2072(rx_desc); 398 rx_desc_data->msdu_len = ath12k_hal_rx_desc_get_msdu_len_qcc2072(ldesc); 399 rx_desc_data->sgi = ath12k_hal_rx_desc_get_msdu_sgi_qcc2072(rx_desc); 400 rx_desc_data->rate_mcs = ath12k_hal_rx_desc_get_msdu_rate_mcs_qcc2072(rx_desc); 401 rx_desc_data->bw = ath12k_hal_rx_desc_get_msdu_rx_bw_qcc2072(rx_desc); 402 rx_desc_data->phy_meta_data = ath12k_hal_rx_desc_get_msdu_freq_qcc2072(rx_desc); 403 rx_desc_data->pkt_type = ath12k_hal_rx_desc_get_msdu_pkt_type_qcc2072(rx_desc); 404 rx_desc_data->nss = hweight8(ath12k_hal_rx_desc_get_msdu_nss_qcc2072(rx_desc)); 405 rx_desc_data->tid = ath12k_hal_rx_desc_get_mpdu_tid_qcc2072(rx_desc); 406 rx_desc_data->peer_id = ath12k_hal_rx_desc_get_mpdu_peer_id_qcc2072(rx_desc); 407 rx_desc_data->addr2_present = ath12k_hal_rx_desc_mac_addr2_valid_qcc2072(rx_desc); 408 rx_desc_data->addr2 = ath12k_hal_rx_desc_mpdu_start_addr2_qcc2072(rx_desc); 409 rx_desc_data->is_mcbc = ath12k_hal_rx_desc_is_da_mcbc_qcc2072(rx_desc); 410 rx_desc_data->msdu_done = ath12k_hal_rx_h_msdu_done_qcc2072(ldesc); 411 rx_desc_data->l4_csum_fail = ath12k_hal_rx_h_l4_cksum_fail_qcc2072(rx_desc); 412 rx_desc_data->ip_csum_fail = ath12k_hal_rx_h_ip_cksum_fail_qcc2072(rx_desc); 413 rx_desc_data->is_decrypted = ath12k_hal_rx_h_is_decrypted_qcc2072(rx_desc); 414 rx_desc_data->err_bitmap = ath12k_hal_rx_h_mpdu_err_qcc2072(rx_desc); 415 } 416 417 static int ath12k_hal_srng_create_config_qcc2072(struct ath12k_hal *hal) 418 { 419 struct hal_srng_config *s; 420 int ret; 421 422 ret = ath12k_hal_srng_create_config_wcn7850(hal); 423 if (ret) 424 return ret; 425 426 s = &hal->srng_config[HAL_REO_CMD]; 427 s->entry_size = (sizeof(struct hal_tlv_hdr) + 428 sizeof(struct hal_reo_get_queue_stats_qcc2072)) >> 2; 429 430 s = &hal->srng_config[HAL_REO_STATUS]; 431 s->entry_size = (sizeof(struct hal_tlv_hdr) + 432 sizeof(struct hal_reo_get_queue_stats_status_qcc2072)) >> 2; 433 434 return 0; 435 } 436 437 static u16 ath12k_hal_reo_status_dec_tlv_hdr_qcc2072(void *tlv, void **desc) 438 { 439 struct hal_reo_get_queue_stats_status_qcc2072 *status_tlv; 440 u16 tag; 441 442 tag = ath12k_hal_decode_tlv32_hdr(tlv, (void **)&status_tlv); 443 /* 444 * actual desc of REO status entry starts after tlv32_padding, 445 * see hal_reo_get_queue_stats_status_qcc2072 446 */ 447 *desc = &status_tlv->status; 448 449 return tag; 450 } 451 452 const struct hal_ops hal_qcc2072_ops = { 453 .create_srng_config = ath12k_hal_srng_create_config_qcc2072, 454 .rx_desc_set_msdu_len = ath12k_hal_rx_desc_set_msdu_len_qcc2072, 455 .rx_desc_get_dot11_hdr = ath12k_hal_rx_desc_get_dot11_hdr_qcc2072, 456 .rx_desc_get_crypto_header = ath12k_hal_rx_desc_get_crypto_hdr_qcc2072, 457 .rx_desc_copy_end_tlv = ath12k_hal_rx_desc_copy_end_tlv_qcc2072, 458 .rx_desc_get_msdu_src_link_id = ath12k_hal_rx_desc_get_msdu_src_link_qcc2072, 459 .extract_rx_desc_data = ath12k_hal_extract_rx_desc_data_qcc2072, 460 .rx_desc_get_l3_pad_bytes = ath12k_hal_rx_desc_get_l3_pad_bytes_qcc2072, 461 .rx_desc_get_mpdu_start_tag = ath12k_hal_rx_desc_get_mpdu_start_tag_qcc2072, 462 .rx_desc_get_mpdu_ppdu_id = ath12k_hal_rx_desc_get_mpdu_ppdu_id_qcc2072, 463 .rx_desc_get_msdu_payload = ath12k_hal_rx_desc_get_msdu_payload_qcc2072, 464 .ce_dst_setup = ath12k_wifi7_hal_ce_dst_setup, 465 .srng_src_hw_init = ath12k_wifi7_hal_srng_src_hw_init, 466 .srng_dst_hw_init = ath12k_wifi7_hal_srng_dst_hw_init, 467 .set_umac_srng_ptr_addr = ath12k_wifi7_hal_set_umac_srng_ptr_addr, 468 .srng_update_shadow_config = ath12k_wifi7_hal_srng_update_shadow_config, 469 .srng_get_ring_id = ath12k_wifi7_hal_srng_get_ring_id, 470 .ce_get_desc_size = ath12k_wifi7_hal_ce_get_desc_size, 471 .ce_src_set_desc = ath12k_wifi7_hal_ce_src_set_desc, 472 .ce_dst_set_desc = ath12k_wifi7_hal_ce_dst_set_desc, 473 .ce_dst_status_get_length = ath12k_wifi7_hal_ce_dst_status_get_length, 474 .set_link_desc_addr = ath12k_wifi7_hal_set_link_desc_addr, 475 .tx_set_dscp_tid_map = ath12k_wifi7_hal_tx_set_dscp_tid_map, 476 .tx_configure_bank_register = 477 ath12k_wifi7_hal_tx_configure_bank_register, 478 .reoq_lut_addr_read_enable = ath12k_wifi7_hal_reoq_lut_addr_read_enable, 479 .reoq_lut_set_max_peerid = ath12k_wifi7_hal_reoq_lut_set_max_peerid, 480 .write_reoq_lut_addr = ath12k_wifi7_hal_write_reoq_lut_addr, 481 .write_ml_reoq_lut_addr = ath12k_wifi7_hal_write_ml_reoq_lut_addr, 482 .setup_link_idle_list = ath12k_wifi7_hal_setup_link_idle_list, 483 .reo_init_cmd_ring = ath12k_wifi7_hal_reo_init_cmd_ring_tlv32, 484 .reo_hw_setup = ath12k_wifi7_hal_reo_hw_setup, 485 .rx_buf_addr_info_set = ath12k_wifi7_hal_rx_buf_addr_info_set, 486 .rx_buf_addr_info_get = ath12k_wifi7_hal_rx_buf_addr_info_get, 487 .cc_config = ath12k_wifi7_hal_cc_config, 488 .get_idle_link_rbm = ath12k_wifi7_hal_get_idle_link_rbm, 489 .rx_msdu_list_get = ath12k_wifi7_hal_rx_msdu_list_get, 490 .rx_reo_ent_buf_paddr_get = ath12k_wifi7_hal_rx_reo_ent_buf_paddr_get, 491 .reo_cmd_enc_tlv_hdr = ath12k_hal_encode_tlv32_hdr, 492 .reo_status_dec_tlv_hdr = ath12k_hal_reo_status_dec_tlv_hdr_qcc2072, 493 }; 494 495 u32 ath12k_hal_rx_desc_get_mpdu_start_offset_qcc2072(void) 496 { 497 return offsetof(struct hal_rx_desc_qcc2072, mpdu_start_tag); 498 } 499 500 u32 ath12k_hal_rx_desc_get_msdu_end_offset_qcc2072(void) 501 { 502 return offsetof(struct hal_rx_desc_qcc2072, msdu_end_tag); 503 } 504