1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 #include "../core.h" 7 8 #ifndef ATH12K_HAL_DESC_H 9 #define ATH12K_HAL_DESC_H 10 11 enum hal_tlv_tag { 12 HAL_MACTX_CBF_START = 0 /* 0x0 */, 13 HAL_PHYRX_DATA = 1 /* 0x1 */, 14 HAL_PHYRX_CBF_DATA_RESP = 2 /* 0x2 */, 15 HAL_PHYRX_ABORT_REQUEST = 3 /* 0x3 */, 16 HAL_PHYRX_USER_ABORT_NOTIFICATION = 4 /* 0x4 */, 17 HAL_MACTX_DATA_RESP = 5 /* 0x5 */, 18 HAL_MACTX_CBF_DATA = 6 /* 0x6 */, 19 HAL_MACTX_CBF_DONE = 7 /* 0x7 */, 20 HAL_PHYRX_LMR_DATA_RESP = 8 /* 0x8 */, 21 HAL_RXPCU_TO_UCODE_START = 9 /* 0x9 */, 22 HAL_RXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU = 10 /* 0xa */, 23 HAL_RXPCU_TO_UCODE_FULL_MPDU_DATA = 11 /* 0xb */, 24 HAL_RXPCU_TO_UCODE_FCS_STATUS = 12 /* 0xc */, 25 HAL_RXPCU_TO_UCODE_MPDU_DELIMITER = 13 /* 0xd */, 26 HAL_RXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER = 14 /* 0xe */, 27 HAL_RXPCU_TO_UCODE_MPDU_HEADER_DATA = 15 /* 0xf */, 28 HAL_RXPCU_TO_UCODE_END = 16 /* 0x10 */, 29 HAL_MACRX_CBF_READ_REQUEST = 32 /* 0x20 */, 30 HAL_MACRX_CBF_DATA_REQUEST = 33 /* 0x21 */, 31 HAL_MACRXXPECT_NDP_RECEPTION = 34 /* 0x22 */, 32 HAL_MACRX_FREEZE_CAPTURE_CHANNEL = 35 /* 0x23 */, 33 HAL_MACRX_NDP_TIMEOUT = 36 /* 0x24 */, 34 HAL_MACRX_ABORT_ACK = 37 /* 0x25 */, 35 HAL_MACRX_REQ_IMPLICIT_FB = 38 /* 0x26 */, 36 HAL_MACRX_CHAIN_MASK = 39 /* 0x27 */, 37 HAL_MACRX_NAP_USER = 40 /* 0x28 */, 38 HAL_MACRX_ABORT_REQUEST = 41 /* 0x29 */, 39 HAL_PHYTX_OTHER_TRANSMIT_INFO16 = 42 /* 0x2a */, 40 HAL_PHYTX_ABORT_ACK = 43 /* 0x2b */, 41 HAL_PHYTX_ABORT_REQUEST = 44 /* 0x2c */, 42 HAL_PHYTX_PKT_END = 45 /* 0x2d */, 43 HAL_PHYTX_PPDU_HEADER_INFO_REQUEST = 46 /* 0x2e */, 44 HAL_PHYTX_REQUEST_CTRL_INFO = 47 /* 0x2f */, 45 HAL_PHYTX_DATA_REQUEST = 48 /* 0x30 */, 46 HAL_PHYTX_BF_CV_LOADING_DONE = 49 /* 0x31 */, 47 HAL_PHYTX_NAP_ACK = 50 /* 0x32 */, 48 HAL_PHYTX_NAP_DONE = 51 /* 0x33 */, 49 HAL_PHYTX_OFF_ACK = 52 /* 0x34 */, 50 HAL_PHYTX_ON_ACK = 53 /* 0x35 */, 51 HAL_PHYTX_SYNTH_OFF_ACK = 54 /* 0x36 */, 52 HAL_PHYTX_DEBUG16 = 55 /* 0x37 */, 53 HAL_MACTX_ABORT_REQUEST = 56 /* 0x38 */, 54 HAL_MACTX_ABORT_ACK = 57 /* 0x39 */, 55 HAL_MACTX_PKT_END = 58 /* 0x3a */, 56 HAL_MACTX_PRE_PHY_DESC = 59 /* 0x3b */, 57 HAL_MACTX_BF_PARAMS_COMMON = 60 /* 0x3c */, 58 HAL_MACTX_BF_PARAMS_PER_USER = 61 /* 0x3d */, 59 HAL_MACTX_PREFETCH_CV = 62 /* 0x3e */, 60 HAL_MACTX_USER_DESC_COMMON = 63 /* 0x3f */, 61 HAL_MACTX_USER_DESC_PER_USER = 64 /* 0x40 */, 62 HAL_XAMPLE_USER_TLV_16 = 65 /* 0x41 */, 63 HAL_XAMPLE_TLV_16 = 66 /* 0x42 */, 64 HAL_MACTX_PHY_OFF = 67 /* 0x43 */, 65 HAL_MACTX_PHY_ON = 68 /* 0x44 */, 66 HAL_MACTX_SYNTH_OFF = 69 /* 0x45 */, 67 HAL_MACTXXPECT_CBF_COMMON = 70 /* 0x46 */, 68 HAL_MACTXXPECT_CBF_PER_USER = 71 /* 0x47 */, 69 HAL_MACTX_PHY_DESC = 72 /* 0x48 */, 70 HAL_MACTX_L_SIG_A = 73 /* 0x49 */, 71 HAL_MACTX_L_SIG_B = 74 /* 0x4a */, 72 HAL_MACTX_HT_SIG = 75 /* 0x4b */, 73 HAL_MACTX_VHT_SIG_A = 76 /* 0x4c */, 74 HAL_MACTX_VHT_SIG_B_SU20 = 77 /* 0x4d */, 75 HAL_MACTX_VHT_SIG_B_SU40 = 78 /* 0x4e */, 76 HAL_MACTX_VHT_SIG_B_SU80 = 79 /* 0x4f */, 77 HAL_MACTX_VHT_SIG_B_SU160 = 80 /* 0x50 */, 78 HAL_MACTX_VHT_SIG_B_MU20 = 81 /* 0x51 */, 79 HAL_MACTX_VHT_SIG_B_MU40 = 82 /* 0x52 */, 80 HAL_MACTX_VHT_SIG_B_MU80 = 83 /* 0x53 */, 81 HAL_MACTX_VHT_SIG_B_MU160 = 84 /* 0x54 */, 82 HAL_MACTX_SERVICE = 85 /* 0x55 */, 83 HAL_MACTX_HE_SIG_A_SU = 86 /* 0x56 */, 84 HAL_MACTX_HE_SIG_A_MU_DL = 87 /* 0x57 */, 85 HAL_MACTX_HE_SIG_A_MU_UL = 88 /* 0x58 */, 86 HAL_MACTX_HE_SIG_B1_MU = 89 /* 0x59 */, 87 HAL_MACTX_HE_SIG_B2_MU = 90 /* 0x5a */, 88 HAL_MACTX_HE_SIG_B2_OFDMA = 91 /* 0x5b */, 89 HAL_MACTX_DELETE_CV = 92 /* 0x5c */, 90 HAL_MACTX_MU_UPLINK_COMMON = 93 /* 0x5d */, 91 HAL_MACTX_MU_UPLINK_USER_SETUP = 94 /* 0x5e */, 92 HAL_MACTX_OTHER_TRANSMIT_INFO = 95 /* 0x5f */, 93 HAL_MACTX_PHY_NAP = 96 /* 0x60 */, 94 HAL_MACTX_DEBUG = 97 /* 0x61 */, 95 HAL_PHYRX_ABORT_ACK = 98 /* 0x62 */, 96 HAL_PHYRX_GENERATED_CBF_DETAILS = 99 /* 0x63 */, 97 HAL_PHYRX_RSSI_LEGACY = 100 /* 0x64 */, 98 HAL_PHYRX_RSSI_HT = 101 /* 0x65 */, 99 HAL_PHYRX_USER_INFO = 102 /* 0x66 */, 100 HAL_PHYRX_PKT_END = 103 /* 0x67 */, 101 HAL_PHYRX_DEBUG = 104 /* 0x68 */, 102 HAL_PHYRX_CBF_TRANSFER_DONE = 105 /* 0x69 */, 103 HAL_PHYRX_CBF_TRANSFER_ABORT = 106 /* 0x6a */, 104 HAL_PHYRX_L_SIG_A = 107 /* 0x6b */, 105 HAL_PHYRX_L_SIG_B = 108 /* 0x6c */, 106 HAL_PHYRX_HT_SIG = 109 /* 0x6d */, 107 HAL_PHYRX_VHT_SIG_A = 110 /* 0x6e */, 108 HAL_PHYRX_VHT_SIG_B_SU20 = 111 /* 0x6f */, 109 HAL_PHYRX_VHT_SIG_B_SU40 = 112 /* 0x70 */, 110 HAL_PHYRX_VHT_SIG_B_SU80 = 113 /* 0x71 */, 111 HAL_PHYRX_VHT_SIG_B_SU160 = 114 /* 0x72 */, 112 HAL_PHYRX_VHT_SIG_B_MU20 = 115 /* 0x73 */, 113 HAL_PHYRX_VHT_SIG_B_MU40 = 116 /* 0x74 */, 114 HAL_PHYRX_VHT_SIG_B_MU80 = 117 /* 0x75 */, 115 HAL_PHYRX_VHT_SIG_B_MU160 = 118 /* 0x76 */, 116 HAL_PHYRX_HE_SIG_A_SU = 119 /* 0x77 */, 117 HAL_PHYRX_HE_SIG_A_MU_DL = 120 /* 0x78 */, 118 HAL_PHYRX_HE_SIG_A_MU_UL = 121 /* 0x79 */, 119 HAL_PHYRX_HE_SIG_B1_MU = 122 /* 0x7a */, 120 HAL_PHYRX_HE_SIG_B2_MU = 123 /* 0x7b */, 121 HAL_PHYRX_HE_SIG_B2_OFDMA = 124 /* 0x7c */, 122 HAL_PHYRX_OTHER_RECEIVE_INFO = 125 /* 0x7d */, 123 HAL_PHYRX_COMMON_USER_INFO = 126 /* 0x7e */, 124 HAL_PHYRX_DATA_DONE = 127 /* 0x7f */, 125 HAL_COEX_TX_REQ = 128 /* 0x80 */, 126 HAL_DUMMY = 129 /* 0x81 */, 127 HALXAMPLE_TLV_32_NAME = 130 /* 0x82 */, 128 HAL_MPDU_LIMIT = 131 /* 0x83 */, 129 HAL_NA_LENGTH_END = 132 /* 0x84 */, 130 HAL_OLE_BUF_STATUS = 133 /* 0x85 */, 131 HAL_PCU_PPDU_SETUP_DONE = 134 /* 0x86 */, 132 HAL_PCU_PPDU_SETUP_END = 135 /* 0x87 */, 133 HAL_PCU_PPDU_SETUP_INIT = 136 /* 0x88 */, 134 HAL_PCU_PPDU_SETUP_START = 137 /* 0x89 */, 135 HAL_PDG_FES_SETUP = 138 /* 0x8a */, 136 HAL_PDG_RESPONSE = 139 /* 0x8b */, 137 HAL_PDG_TX_REQ = 140 /* 0x8c */, 138 HAL_SCH_WAIT_INSTR = 141 /* 0x8d */, 139 HAL_TQM_FLOWMPTY_STATUS = 143 /* 0x8f */, 140 HAL_TQM_FLOW_NOTMPTY_STATUS = 144 /* 0x90 */, 141 HAL_TQM_GEN_MPDU_LENGTH_LIST = 145 /* 0x91 */, 142 HAL_TQM_GEN_MPDU_LENGTH_LIST_STATUS = 146 /* 0x92 */, 143 HAL_TQM_GEN_MPDUS = 147 /* 0x93 */, 144 HAL_TQM_GEN_MPDUS_STATUS = 148 /* 0x94 */, 145 HAL_TQM_REMOVE_MPDU = 149 /* 0x95 */, 146 HAL_TQM_REMOVE_MPDU_STATUS = 150 /* 0x96 */, 147 HAL_TQM_REMOVE_MSDU = 151 /* 0x97 */, 148 HAL_TQM_REMOVE_MSDU_STATUS = 152 /* 0x98 */, 149 HAL_TQM_UPDATE_TX_MPDU_COUNT = 153 /* 0x99 */, 150 HAL_TQM_WRITE_CMD = 154 /* 0x9a */, 151 HAL_OFDMA_TRIGGER_DETAILS = 155 /* 0x9b */, 152 HAL_TX_DATA = 156 /* 0x9c */, 153 HAL_TX_FES_SETUP = 157 /* 0x9d */, 154 HAL_RX_PACKET = 158 /* 0x9e */, 155 HALXPECTED_RESPONSE = 159 /* 0x9f */, 156 HAL_TX_MPDU_END = 160 /* 0xa0 */, 157 HAL_TX_MPDU_START = 161 /* 0xa1 */, 158 HAL_TX_MSDU_END = 162 /* 0xa2 */, 159 HAL_TX_MSDU_START = 163 /* 0xa3 */, 160 HAL_TX_SW_MODE_SETUP = 164 /* 0xa4 */, 161 HAL_TXPCU_BUFFER_STATUS = 165 /* 0xa5 */, 162 HAL_TXPCU_USER_BUFFER_STATUS = 166 /* 0xa6 */, 163 HAL_DATA_TO_TIME_CONFIG = 167 /* 0xa7 */, 164 HALXAMPLE_USER_TLV_32 = 168 /* 0xa8 */, 165 HAL_MPDU_INFO = 169 /* 0xa9 */, 166 HAL_PDG_USER_SETUP = 170 /* 0xaa */, 167 HAL_TX_11AH_SETUP = 171 /* 0xab */, 168 HAL_REO_UPDATE_RX_REO_QUEUE_STATUS = 172 /* 0xac */, 169 HAL_TX_PEER_ENTRY = 173 /* 0xad */, 170 HAL_TX_RAW_OR_NATIVE_FRAME_SETUP = 174 /* 0xae */, 171 HALXAMPLE_USER_TLV_44 = 175 /* 0xaf */, 172 HAL_TX_FLUSH = 176 /* 0xb0 */, 173 HAL_TX_FLUSH_REQ = 177 /* 0xb1 */, 174 HAL_TQM_WRITE_CMD_STATUS = 178 /* 0xb2 */, 175 HAL_TQM_GET_MPDU_QUEUE_STATS = 179 /* 0xb3 */, 176 HAL_TQM_GET_MSDU_FLOW_STATS = 180 /* 0xb4 */, 177 HALXAMPLE_USER_CTLV_44 = 181 /* 0xb5 */, 178 HAL_TX_FES_STATUS_START = 182 /* 0xb6 */, 179 HAL_TX_FES_STATUS_USER_PPDU = 183 /* 0xb7 */, 180 HAL_TX_FES_STATUS_USER_RESPONSE = 184 /* 0xb8 */, 181 HAL_TX_FES_STATUS_END = 185 /* 0xb9 */, 182 HAL_RX_TRIG_INFO = 186 /* 0xba */, 183 HAL_RXPCU_TX_SETUP_CLEAR = 187 /* 0xbb */, 184 HAL_RX_FRAME_BITMAP_REQ = 188 /* 0xbc */, 185 HAL_RX_FRAME_BITMAP_ACK = 189 /* 0xbd */, 186 HAL_COEX_RX_STATUS = 190 /* 0xbe */, 187 HAL_RX_START_PARAM = 191 /* 0xbf */, 188 HAL_RX_PPDU_START = 192 /* 0xc0 */, 189 HAL_RX_PPDU_END = 193 /* 0xc1 */, 190 HAL_RX_MPDU_START = 194 /* 0xc2 */, 191 HAL_RX_MPDU_END = 195 /* 0xc3 */, 192 HAL_RX_MSDU_START = 196 /* 0xc4 */, 193 HAL_RX_MSDU_END = 197 /* 0xc5 */, 194 HAL_RX_ATTENTION = 198 /* 0xc6 */, 195 HAL_RECEIVED_RESPONSE_INFO = 199 /* 0xc7 */, 196 HAL_RX_PHY_SLEEP = 200 /* 0xc8 */, 197 HAL_RX_HEADER = 201 /* 0xc9 */, 198 HAL_RX_PEER_ENTRY = 202 /* 0xca */, 199 HAL_RX_FLUSH = 203 /* 0xcb */, 200 HAL_RX_RESPONSE_REQUIRED_INFO = 204 /* 0xcc */, 201 HAL_RX_FRAMELESS_BAR_DETAILS = 205 /* 0xcd */, 202 HAL_TQM_GET_MPDU_QUEUE_STATS_STATUS = 206 /* 0xce */, 203 HAL_TQM_GET_MSDU_FLOW_STATS_STATUS = 207 /* 0xcf */, 204 HAL_TX_CBF_INFO = 208 /* 0xd0 */, 205 HAL_PCU_PPDU_SETUP_USER = 209 /* 0xd1 */, 206 HAL_RX_MPDU_PCU_START = 210 /* 0xd2 */, 207 HAL_RX_PM_INFO = 211 /* 0xd3 */, 208 HAL_RX_USER_PPDU_END = 212 /* 0xd4 */, 209 HAL_RX_PRE_PPDU_START = 213 /* 0xd5 */, 210 HAL_RX_PREAMBLE = 214 /* 0xd6 */, 211 HAL_TX_FES_SETUP_COMPLETE = 215 /* 0xd7 */, 212 HAL_TX_LAST_MPDU_FETCHED = 216 /* 0xd8 */, 213 HAL_TXDMA_STOP_REQUEST = 217 /* 0xd9 */, 214 HAL_RXPCU_SETUP = 218 /* 0xda */, 215 HAL_RXPCU_USER_SETUP = 219 /* 0xdb */, 216 HAL_TX_FES_STATUS_ACK_OR_BA = 220 /* 0xdc */, 217 HAL_TQM_ACKED_MPDU = 221 /* 0xdd */, 218 HAL_COEX_TX_RESP = 222 /* 0xde */, 219 HAL_COEX_TX_STATUS = 223 /* 0xdf */, 220 HAL_MACTX_COEX_PHY_CTRL = 224 /* 0xe0 */, 221 HAL_COEX_STATUS_BROADCAST = 225 /* 0xe1 */, 222 HAL_RESPONSE_START_STATUS = 226 /* 0xe2 */, 223 HAL_RESPONSEND_STATUS = 227 /* 0xe3 */, 224 HAL_CRYPTO_STATUS = 228 /* 0xe4 */, 225 HAL_RECEIVED_TRIGGER_INFO = 229 /* 0xe5 */, 226 HAL_COEX_TX_STOP_CTRL = 230 /* 0xe6 */, 227 HAL_RX_PPDU_ACK_REPORT = 231 /* 0xe7 */, 228 HAL_RX_PPDU_NO_ACK_REPORT = 232 /* 0xe8 */, 229 HAL_SCH_COEX_STATUS = 233 /* 0xe9 */, 230 HAL_SCHEDULER_COMMAND_STATUS = 234 /* 0xea */, 231 HAL_SCHEDULER_RX_PPDU_NO_RESPONSE_STATUS = 235 /* 0xeb */, 232 HAL_TX_FES_STATUS_PROT = 236 /* 0xec */, 233 HAL_TX_FES_STATUS_START_PPDU = 237 /* 0xed */, 234 HAL_TX_FES_STATUS_START_PROT = 238 /* 0xee */, 235 HAL_TXPCU_PHYTX_DEBUG32 = 239 /* 0xef */, 236 HAL_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 = 240 /* 0xf0 */, 237 HAL_TX_MPDU_COUNT_TRANSFERND = 241 /* 0xf1 */, 238 HAL_WHO_ANCHOR_OFFSET = 242 /* 0xf2 */, 239 HAL_WHO_ANCHOR_VALUE = 243 /* 0xf3 */, 240 HAL_WHO_CCE_INFO = 244 /* 0xf4 */, 241 HAL_WHO_COMMIT = 245 /* 0xf5 */, 242 HAL_WHO_COMMIT_DONE = 246 /* 0xf6 */, 243 HAL_WHO_FLUSH = 247 /* 0xf7 */, 244 HAL_WHO_L2_LLC = 248 /* 0xf8 */, 245 HAL_WHO_L2_PAYLOAD = 249 /* 0xf9 */, 246 HAL_WHO_L3_CHECKSUM = 250 /* 0xfa */, 247 HAL_WHO_L3_INFO = 251 /* 0xfb */, 248 HAL_WHO_L4_CHECKSUM = 252 /* 0xfc */, 249 HAL_WHO_L4_INFO = 253 /* 0xfd */, 250 HAL_WHO_MSDU = 254 /* 0xfe */, 251 HAL_WHO_MSDU_MISC = 255 /* 0xff */, 252 HAL_WHO_PACKET_DATA = 256 /* 0x100 */, 253 HAL_WHO_PACKET_HDR = 257 /* 0x101 */, 254 HAL_WHO_PPDU_END = 258 /* 0x102 */, 255 HAL_WHO_PPDU_START = 259 /* 0x103 */, 256 HAL_WHO_TSO = 260 /* 0x104 */, 257 HAL_WHO_WMAC_HEADER_PV0 = 261 /* 0x105 */, 258 HAL_WHO_WMAC_HEADER_PV1 = 262 /* 0x106 */, 259 HAL_WHO_WMAC_IV = 263 /* 0x107 */, 260 HAL_MPDU_INFO_END = 264 /* 0x108 */, 261 HAL_MPDU_INFO_BITMAP = 265 /* 0x109 */, 262 HAL_TX_QUEUE_EXTENSION = 266 /* 0x10a */, 263 HAL_SCHEDULER_SELFGEN_RESPONSE_STATUS = 267 /* 0x10b */, 264 HAL_TQM_UPDATE_TX_MPDU_COUNT_STATUS = 268 /* 0x10c */, 265 HAL_TQM_ACKED_MPDU_STATUS = 269 /* 0x10d */, 266 HAL_TQM_ADD_MSDU_STATUS = 270 /* 0x10e */, 267 HAL_TQM_LIST_GEN_DONE = 271 /* 0x10f */, 268 HAL_WHO_TERMINATE = 272 /* 0x110 */, 269 HAL_TX_LAST_MPDU_END = 273 /* 0x111 */, 270 HAL_TX_CV_DATA = 274 /* 0x112 */, 271 HAL_PPDU_TX_END = 275 /* 0x113 */, 272 HAL_PROT_TX_END = 276 /* 0x114 */, 273 HAL_MPDU_INFO_GLOBAL_END = 277 /* 0x115 */, 274 HAL_TQM_SCH_INSTR_GLOBAL_END = 278 /* 0x116 */, 275 HAL_RX_PPDU_END_USER_STATS = 279 /* 0x117 */, 276 HAL_RX_PPDU_END_USER_STATS_EXT = 280 /* 0x118 */, 277 HAL_REO_GET_QUEUE_STATS = 281 /* 0x119 */, 278 HAL_REO_FLUSH_QUEUE = 282 /* 0x11a */, 279 HAL_REO_FLUSH_CACHE = 283 /* 0x11b */, 280 HAL_REO_UNBLOCK_CACHE = 284 /* 0x11c */, 281 HAL_REO_GET_QUEUE_STATS_STATUS = 285 /* 0x11d */, 282 HAL_REO_FLUSH_QUEUE_STATUS = 286 /* 0x11e */, 283 HAL_REO_FLUSH_CACHE_STATUS = 287 /* 0x11f */, 284 HAL_REO_UNBLOCK_CACHE_STATUS = 288 /* 0x120 */, 285 HAL_TQM_FLUSH_CACHE = 289 /* 0x121 */, 286 HAL_TQM_UNBLOCK_CACHE = 290 /* 0x122 */, 287 HAL_TQM_FLUSH_CACHE_STATUS = 291 /* 0x123 */, 288 HAL_TQM_UNBLOCK_CACHE_STATUS = 292 /* 0x124 */, 289 HAL_RX_PPDU_END_STATUS_DONE = 293 /* 0x125 */, 290 HAL_RX_STATUS_BUFFER_DONE = 294 /* 0x126 */, 291 HAL_TX_DATA_SYNC = 297 /* 0x129 */, 292 HAL_PHYRX_CBF_READ_REQUEST_ACK = 298 /* 0x12a */, 293 HAL_TQM_GET_MPDU_HEAD_INFO = 299 /* 0x12b */, 294 HAL_TQM_SYNC_CMD = 300 /* 0x12c */, 295 HAL_TQM_GET_MPDU_HEAD_INFO_STATUS = 301 /* 0x12d */, 296 HAL_TQM_SYNC_CMD_STATUS = 302 /* 0x12e */, 297 HAL_TQM_THRESHOLD_DROP_NOTIFICATION_STATUS = 303 /* 0x12f */, 298 HAL_TQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 304 /* 0x130 */, 299 HAL_REO_FLUSH_TIMEOUT_LIST = 305 /* 0x131 */, 300 HAL_REO_FLUSH_TIMEOUT_LIST_STATUS = 306 /* 0x132 */, 301 HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 307 /* 0x133 */, 302 HAL_SCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS = 308 /* 0x134 */, 303 HALXAMPLE_USER_TLV_32_NAME = 309 /* 0x135 */, 304 HAL_RX_PPDU_START_USER_INFO = 310 /* 0x136 */, 305 HAL_RX_RING_MASK = 311 /* 0x137 */, 306 HAL_COEX_MAC_NAP = 312 /* 0x138 */, 307 HAL_RXPCU_PPDU_END_INFO = 313 /* 0x139 */, 308 HAL_WHO_MESH_CONTROL = 314 /* 0x13a */, 309 HAL_PDG_SW_MODE_BW_START = 315 /* 0x13b */, 310 HAL_PDG_SW_MODE_BW_END = 316 /* 0x13c */, 311 HAL_PDG_WAIT_FOR_MAC_REQUEST = 317 /* 0x13d */, 312 HAL_PDG_WAIT_FOR_PHY_REQUEST = 318 /* 0x13e */, 313 HAL_SCHEDULER_END = 319 /* 0x13f */, 314 HAL_RX_PPDU_START_DROPPED = 320 /* 0x140 */, 315 HAL_RX_PPDU_END_DROPPED = 321 /* 0x141 */, 316 HAL_RX_PPDU_END_STATUS_DONE_DROPPED = 322 /* 0x142 */, 317 HAL_RX_MPDU_START_DROPPED = 323 /* 0x143 */, 318 HAL_RX_MSDU_START_DROPPED = 324 /* 0x144 */, 319 HAL_RX_MSDU_END_DROPPED = 325 /* 0x145 */, 320 HAL_RX_MPDU_END_DROPPED = 326 /* 0x146 */, 321 HAL_RX_ATTENTION_DROPPED = 327 /* 0x147 */, 322 HAL_TXPCU_USER_SETUP = 328 /* 0x148 */, 323 HAL_RXPCU_USER_SETUP_EXT = 329 /* 0x149 */, 324 HAL_CMD_PART_0_END = 330 /* 0x14a */, 325 HAL_MACTX_SYNTH_ON = 331 /* 0x14b */, 326 HAL_SCH_CRITICAL_TLV_REFERENCE = 332 /* 0x14c */, 327 HAL_TQM_MPDU_GLOBAL_START = 333 /* 0x14d */, 328 HALXAMPLE_TLV_32 = 334 /* 0x14e */, 329 HAL_TQM_UPDATE_TX_MSDU_FLOW = 335 /* 0x14f */, 330 HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD = 336 /* 0x150 */, 331 HAL_TQM_UPDATE_TX_MSDU_FLOW_STATUS = 337 /* 0x151 */, 332 HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS = 338 /* 0x152 */, 333 HAL_REO_UPDATE_RX_REO_QUEUE = 339 /* 0x153 */, 334 HAL_TQM_MPDU_QUEUEMPTY_STATUS = 340 /* 0x154 */, 335 HAL_TQM_2_SCH_MPDU_AVAILABLE = 341 /* 0x155 */, 336 HAL_PDG_TRIG_RESPONSE = 342 /* 0x156 */, 337 HAL_TRIGGER_RESPONSE_TX_DONE = 343 /* 0x157 */, 338 HAL_ABORT_FROM_PHYRX_DETAILS = 344 /* 0x158 */, 339 HAL_SCH_TQM_CMD_WRAPPER = 345 /* 0x159 */, 340 HAL_MPDUS_AVAILABLE = 346 /* 0x15a */, 341 HAL_RECEIVED_RESPONSE_INFO_PART2 = 347 /* 0x15b */, 342 HAL_PHYRX_TX_START_TIMING = 348 /* 0x15c */, 343 HAL_TXPCU_PREAMBLE_DONE = 349 /* 0x15d */, 344 HAL_NDP_PREAMBLE_DONE = 350 /* 0x15e */, 345 HAL_SCH_TQM_CMD_WRAPPER_RBO_DROP = 351 /* 0x15f */, 346 HAL_SCH_TQM_CMD_WRAPPER_CONT_DROP = 352 /* 0x160 */, 347 HAL_MACTX_CLEAR_PREV_TX_INFO = 353 /* 0x161 */, 348 HAL_TX_PUNCTURE_SETUP = 354 /* 0x162 */, 349 HAL_R2R_STATUS_END = 355 /* 0x163 */, 350 HAL_MACTX_PREFETCH_CV_COMMON = 356 /* 0x164 */, 351 HAL_END_OF_FLUSH_MARKER = 357 /* 0x165 */, 352 HAL_MACTX_MU_UPLINK_COMMON_PUNC = 358 /* 0x166 */, 353 HAL_MACTX_MU_UPLINK_USER_SETUP_PUNC = 359 /* 0x167 */, 354 HAL_RECEIVED_RESPONSE_USER_7_0 = 360 /* 0x168 */, 355 HAL_RECEIVED_RESPONSE_USER_15_8 = 361 /* 0x169 */, 356 HAL_RECEIVED_RESPONSE_USER_23_16 = 362 /* 0x16a */, 357 HAL_RECEIVED_RESPONSE_USER_31_24 = 363 /* 0x16b */, 358 HAL_RECEIVED_RESPONSE_USER_36_32 = 364 /* 0x16c */, 359 HAL_TX_LOOPBACK_SETUP = 365 /* 0x16d */, 360 HAL_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS = 366 /* 0x16e */, 361 HAL_SCH_WAIT_INSTR_TX_PATH = 367 /* 0x16f */, 362 HAL_MACTX_OTHER_TRANSMIT_INFO_TX2TX = 368 /* 0x170 */, 363 HAL_MACTX_OTHER_TRANSMIT_INFOMUPHY_SETUP = 369 /* 0x171 */, 364 HAL_PHYRX_OTHER_RECEIVE_INFOVM_DETAILS = 370 /* 0x172 */, 365 HAL_TX_WUR_DATA = 371 /* 0x173 */, 366 HAL_RX_PPDU_END_START = 372 /* 0x174 */, 367 HAL_RX_PPDU_END_MIDDLE = 373 /* 0x175 */, 368 HAL_RX_PPDU_END_LAST = 374 /* 0x176 */, 369 HAL_MACTX_BACKOFF_BASED_TRANSMISSION = 375 /* 0x177 */, 370 HAL_MACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX = 376 /* 0x178 */, 371 HAL_SRP_INFO = 377 /* 0x179 */, 372 HAL_OBSS_SR_INFO = 378 /* 0x17a */, 373 HAL_SCHEDULER_SW_MSG_STATUS = 379 /* 0x17b */, 374 HAL_HWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT = 380 /* 0x17c */, 375 HAL_RXPCU_SETUP_COMPLETE = 381 /* 0x17d */, 376 HAL_SNOOP_PPDU_START = 382 /* 0x17e */, 377 HAL_SNOOP_MPDU_USR_DBG_INFO = 383 /* 0x17f */, 378 HAL_SNOOP_MSDU_USR_DBG_INFO = 384 /* 0x180 */, 379 HAL_SNOOP_MSDU_USR_DATA = 385 /* 0x181 */, 380 HAL_SNOOP_MPDU_USR_STAT_INFO = 386 /* 0x182 */, 381 HAL_SNOOP_PPDU_END = 387 /* 0x183 */, 382 HAL_SNOOP_SPARE = 388 /* 0x184 */, 383 HAL_PHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON = 390 /* 0x186 */, 384 HAL_PHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER = 391 /* 0x187 */, 385 HAL_MACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS = 392 /* 0x188 */, 386 HAL_PHYRX_OTHER_RECEIVE_INFO_108PVM_DETAILS = 393 /* 0x189 */, 387 HAL_SCH_TLV_WRAPPER = 394 /* 0x18a */, 388 HAL_SCHEDULER_STATUS_WRAPPER = 395 /* 0x18b */, 389 HAL_MPDU_INFO_6X = 396 /* 0x18c */, 390 HAL_MACTX_11AZ_USER_DESC_PER_USER = 397 /* 0x18d */, 391 HAL_MACTX_U_SIGHT_SU_MU = 398 /* 0x18e */, 392 HAL_MACTX_U_SIGHT_TB = 399 /* 0x18f */, 393 HAL_PHYRX_U_SIGHT_SU_MU = 403 /* 0x193 */, 394 HAL_PHYRX_U_SIGHT_TB = 404 /* 0x194 */, 395 HAL_MACRX_LMR_READ_REQUEST = 408 /* 0x198 */, 396 HAL_MACRX_LMR_DATA_REQUEST = 409 /* 0x199 */, 397 HAL_PHYRX_LMR_TRANSFER_DONE = 410 /* 0x19a */, 398 HAL_PHYRX_LMR_TRANSFER_ABORT = 411 /* 0x19b */, 399 HAL_PHYRX_LMR_READ_REQUEST_ACK = 412 /* 0x19c */, 400 HAL_MACRX_SECURE_LTF_SEQ_PTR = 413 /* 0x19d */, 401 HAL_PHYRX_USER_INFO_MU_UL = 414 /* 0x19e */, 402 HAL_MPDU_QUEUE_OVERVIEW = 415 /* 0x19f */, 403 HAL_SCHEDULER_NAV_INFO = 416 /* 0x1a0 */, 404 HAL_LMR_PEER_ENTRY = 418 /* 0x1a2 */, 405 HAL_LMR_MPDU_START = 419 /* 0x1a3 */, 406 HAL_LMR_DATA = 420 /* 0x1a4 */, 407 HAL_LMR_MPDU_END = 421 /* 0x1a5 */, 408 HAL_REO_GET_QUEUE_1K_STATS_STATUS = 422 /* 0x1a6 */, 409 HAL_RX_FRAME_1K_BITMAP_ACK = 423 /* 0x1a7 */, 410 HAL_TX_FES_STATUS_1K_BA = 424 /* 0x1a8 */, 411 HAL_TQM_ACKED_1K_MPDU = 425 /* 0x1a9 */, 412 HAL_MACRX_INBSS_OBSS_IND = 426 /* 0x1aa */, 413 HAL_PHYRX_LOCATION = 427 /* 0x1ab */, 414 HAL_MLO_TX_NOTIFICATION_SU = 428 /* 0x1ac */, 415 HAL_MLO_TX_NOTIFICATION_MU = 429 /* 0x1ad */, 416 HAL_MLO_TX_REQ_SU = 430 /* 0x1ae */, 417 HAL_MLO_TX_REQ_MU = 431 /* 0x1af */, 418 HAL_MLO_TX_RESP = 432 /* 0x1b0 */, 419 HAL_MLO_RX_NOTIFICATION = 433 /* 0x1b1 */, 420 HAL_MLO_BKOFF_TRUNC_REQ = 434 /* 0x1b2 */, 421 HAL_MLO_TBTT_NOTIFICATION = 435 /* 0x1b3 */, 422 HAL_MLO_MESSAGE = 436 /* 0x1b4 */, 423 HAL_MLO_TS_SYNC_MSG = 437 /* 0x1b5 */, 424 HAL_MLO_FES_SETUP = 438 /* 0x1b6 */, 425 HAL_MLO_PDG_FES_SETUP_SU = 439 /* 0x1b7 */, 426 HAL_MLO_PDG_FES_SETUP_MU = 440 /* 0x1b8 */, 427 HAL_MPDU_INFO_1K_BITMAP = 441 /* 0x1b9 */, 428 HAL_MON_BUF_ADDR = 442 /* 0x1ba */, 429 HAL_TX_FRAG_STATE = 443 /* 0x1bb */, 430 HAL_MACTXHT_SIG_USR_OFDMA = 446 /* 0x1be */, 431 HAL_PHYRXHT_SIG_CMN_PUNC = 448 /* 0x1c0 */, 432 HAL_PHYRXHT_SIG_CMN_OFDMA = 450 /* 0x1c2 */, 433 HAL_PHYRXHT_SIG_USR_OFDMA = 454 /* 0x1c6 */, 434 HAL_PHYRX_PKT_END_PART1 = 456 /* 0x1c8 */, 435 HAL_MACTXXPECT_NDP_RECEPTION = 457 /* 0x1c9 */, 436 HAL_MACTX_SECURE_LTF_SEQ_PTR = 458 /* 0x1ca */, 437 HAL_MLO_PDG_BKOFF_TRUNC_NOTIFY = 460 /* 0x1cc */, 438 HAL_PHYRX_11AZ_INTEGRITY_DATA = 461 /* 0x1cd */, 439 HAL_PHYTX_LOCATION = 462 /* 0x1ce */, 440 HAL_PHYTX_11AZ_INTEGRITY_DATA = 463 /* 0x1cf */, 441 HAL_MACTXHT_SIG_USR_SU = 466 /* 0x1d2 */, 442 HAL_MACTXHT_SIG_USR_MU_MIMO = 467 /* 0x1d3 */, 443 HAL_PHYRXHT_SIG_USR_SU = 468 /* 0x1d4 */, 444 HAL_PHYRXHT_SIG_USR_MU_MIMO = 469 /* 0x1d5 */, 445 HAL_PHYRX_GENERIC_U_SIG = 470 /* 0x1d6 */, 446 HAL_PHYRX_GENERIC_EHT_SIG = 471 /* 0x1d7 */, 447 HAL_OVERWRITE_RESP_START = 472 /* 0x1d8 */, 448 HAL_OVERWRITE_RESP_PREAMBLE_INFO = 473 /* 0x1d9 */, 449 HAL_OVERWRITE_RESP_FRAME_INFO = 474 /* 0x1da */, 450 HAL_OVERWRITE_RESP_END = 475 /* 0x1db */, 451 HAL_RXPCUARLY_RX_INDICATION = 476 /* 0x1dc */, 452 HAL_MON_DROP = 477 /* 0x1dd */, 453 HAL_MACRX_MU_UPLINK_COMMON_SNIFF = 478 /* 0x1de */, 454 HAL_MACRX_MU_UPLINK_USER_SETUP_SNIFF = 479 /* 0x1df */, 455 HAL_MACRX_MU_UPLINK_USER_SEL_SNIFF = 480 /* 0x1e0 */, 456 HAL_MACRX_MU_UPLINK_FCS_STATUS_SNIFF = 481 /* 0x1e1 */, 457 HAL_MACTX_PREFETCH_CV_DMA = 482 /* 0x1e2 */, 458 HAL_MACTX_PREFETCH_CV_PER_USER = 483 /* 0x1e3 */, 459 HAL_PHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS = 484 /* 0x1e4 */, 460 HAL_MACTX_BF_PARAMS_UPDATE_COMMON = 485 /* 0x1e5 */, 461 HAL_MACTX_BF_PARAMS_UPDATE_PER_USER = 486 /* 0x1e6 */, 462 HAL_RANGING_USER_DETAILS = 487 /* 0x1e7 */, 463 HAL_PHYTX_CV_CORR_STATUS = 488 /* 0x1e8 */, 464 HAL_PHYTX_CV_CORR_COMMON = 489 /* 0x1e9 */, 465 HAL_PHYTX_CV_CORR_USER = 490 /* 0x1ea */, 466 HAL_MACTX_CV_CORR_COMMON = 491 /* 0x1eb */, 467 HAL_MACTX_CV_CORR_MAC_INFO_GROUP = 492 /* 0x1ec */, 468 HAL_BW_PUNCTUREVAL_WRAPPER = 493 /* 0x1ed */, 469 HAL_MACTX_RX_NOTIFICATION_FOR_PHY = 494 /* 0x1ee */, 470 HAL_MACTX_TX_NOTIFICATION_FOR_PHY = 495 /* 0x1ef */, 471 HAL_MACTX_MU_UPLINK_COMMON_PER_BW = 496 /* 0x1f0 */, 472 HAL_MACTX_MU_UPLINK_USER_SETUP_PER_BW = 497 /* 0x1f1 */, 473 HAL_RX_PPDU_END_USER_STATS_EXT2 = 498 /* 0x1f2 */, 474 HAL_FW2SW_MON = 499 /* 0x1f3 */, 475 HAL_WSI_DIRECT_MESSAGE = 500 /* 0x1f4 */, 476 HAL_MACTXMLSR_PRE_SWITCH = 501 /* 0x1f5 */, 477 HAL_MACTXMLSR_SWITCH = 502 /* 0x1f6 */, 478 HAL_MACTXMLSR_SWITCH_BACK = 503 /* 0x1f7 */, 479 HAL_PHYTXMLSR_SWITCH_ACK = 504 /* 0x1f8 */, 480 HAL_PHYTXMLSR_SWITCH_BACK_ACK = 505 /* 0x1f9 */, 481 HAL_SPARE_REUSE_TAG_0 = 506 /* 0x1fa */, 482 HAL_SPARE_REUSE_TAG_1 = 507 /* 0x1fb */, 483 HAL_SPARE_REUSE_TAG_2 = 508 /* 0x1fc */, 484 HAL_SPARE_REUSE_TAG_3 = 509 /* 0x1fd */, 485 /* FIXME: Assign correct value for HAL_TCL_DATA_CMD */ 486 HAL_TCL_DATA_CMD = 510, 487 HAL_TLV_BASE = 511 /* 0x1ff */, 488 }; 489 490 #define RX_MPDU_DESC_INFO0_MSDU_COUNT GENMASK(7, 0) 491 #define RX_MPDU_DESC_INFO0_FRAG_FLAG BIT(8) 492 #define RX_MPDU_DESC_INFO0_MPDU_RETRY BIT(9) 493 #define RX_MPDU_DESC_INFO0_AMPDU_FLAG BIT(10) 494 #define RX_MPDU_DESC_INFO0_BAR_FRAME BIT(11) 495 #define RX_MPDU_DESC_INFO0_VALID_PN BIT(12) 496 #define RX_MPDU_DESC_INFO0_RAW_MPDU BIT(13) 497 #define RX_MPDU_DESC_INFO0_MORE_FRAG_FLAG BIT(14) 498 #define RX_MPDU_DESC_INFO0_SRC_INFO GENMASK(26, 15) 499 #define RX_MPDU_DESC_INFO0_MPDU_QOS_CTRL_VALID BIT(27) 500 #define RX_MPDU_DESC_INFO0_TID GENMASK(31, 28) 501 502 /* Peer Metadata classification */ 503 504 /* Version 0 */ 505 #define RX_MPDU_DESC_META_DATA_V0_PEER_ID GENMASK(15, 0) 506 #define RX_MPDU_DESC_META_DATA_V0_VDEV_ID GENMASK(23, 16) 507 508 /* Version 1 */ 509 #define RX_MPDU_DESC_META_DATA_V1_PEER_ID GENMASK(13, 0) 510 #define RX_MPDU_DESC_META_DATA_V1_LOGICAL_LINK_ID GENMASK(15, 14) 511 #define RX_MPDU_DESC_META_DATA_V1_VDEV_ID GENMASK(23, 16) 512 #define RX_MPDU_DESC_META_DATA_V1_LMAC_ID GENMASK(25, 24) 513 #define RX_MPDU_DESC_META_DATA_V1_DEVICE_ID GENMASK(28, 26) 514 515 /* Version 1A */ 516 #define RX_MPDU_DESC_META_DATA_V1A_PEER_ID GENMASK(13, 0) 517 #define RX_MPDU_DESC_META_DATA_V1A_VDEV_ID GENMASK(21, 14) 518 #define RX_MPDU_DESC_META_DATA_V1A_LOGICAL_LINK_ID GENMASK(25, 22) 519 #define RX_MPDU_DESC_META_DATA_V1A_DEVICE_ID GENMASK(28, 26) 520 521 /* Version 1B */ 522 #define RX_MPDU_DESC_META_DATA_V1B_PEER_ID GENMASK(13, 0) 523 #define RX_MPDU_DESC_META_DATA_V1B_VDEV_ID GENMASK(21, 14) 524 #define RX_MPDU_DESC_META_DATA_V1B_HW_LINK_ID GENMASK(25, 22) 525 #define RX_MPDU_DESC_META_DATA_V1B_DEVICE_ID GENMASK(28, 26) 526 527 struct rx_mpdu_desc { 528 __le32 info0; /* %RX_MPDU_DESC_INFO */ 529 __le32 peer_meta_data; 530 } __packed; 531 532 /* rx_mpdu_desc 533 * Producer: RXDMA 534 * Consumer: REO/SW/FW 535 * 536 * msdu_count 537 * The number of MSDUs within the MPDU 538 * 539 * fragment_flag 540 * When set, this MPDU is a fragment and REO should forward this 541 * fragment MPDU to the REO destination ring without any reorder 542 * checks, pn checks or bitmap update. This implies that REO is 543 * forwarding the pointer to the MSDU link descriptor. 544 * 545 * mpdu_retry_bit 546 * The retry bit setting from the MPDU header of the received frame 547 * 548 * ampdu_flag 549 * Indicates the MPDU was received as part of an A-MPDU. 550 * 551 * bar_frame 552 * Indicates the received frame is a BAR frame. After processing, 553 * this frame shall be pushed to SW or deleted. 554 * 555 * valid_pn 556 * When not set, REO will not perform a PN sequence number check. 557 * 558 * raw_mpdu 559 * Field only valid when first_msdu_in_mpdu_flag is set. Indicates 560 * the contents in the MSDU buffer contains a 'RAW' MPDU. This 561 * 'RAW' MPDU might be spread out over multiple MSDU buffers. 562 * 563 * more_fragment_flag 564 * The More Fragment bit setting from the MPDU header of the 565 * received frame 566 * 567 * src_info 568 * Source (Virtual) device/interface info associated with this peer. 569 * This field gets passed on by REO to PPE in the EDMA descriptor. 570 * 571 * mpdu_qos_control_valid 572 * When set, the MPDU has a QoS control field 573 * 574 * tid 575 * Field only valid when mpdu_qos_control_valid is set 576 */ 577 578 enum hal_rx_msdu_desc_reo_dest_ind { 579 HAL_RX_MSDU_DESC_REO_DEST_IND_TCL, 580 HAL_RX_MSDU_DESC_REO_DEST_IND_SW1, 581 HAL_RX_MSDU_DESC_REO_DEST_IND_SW2, 582 HAL_RX_MSDU_DESC_REO_DEST_IND_SW3, 583 HAL_RX_MSDU_DESC_REO_DEST_IND_SW4, 584 HAL_RX_MSDU_DESC_REO_DEST_IND_RELEASE, 585 HAL_RX_MSDU_DESC_REO_DEST_IND_FW, 586 HAL_RX_MSDU_DESC_REO_DEST_IND_SW5, 587 HAL_RX_MSDU_DESC_REO_DEST_IND_SW6, 588 HAL_RX_MSDU_DESC_REO_DEST_IND_SW7, 589 HAL_RX_MSDU_DESC_REO_DEST_IND_SW8, 590 }; 591 592 #define RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU BIT(0) 593 #define RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU BIT(1) 594 #define RX_MSDU_DESC_INFO0_MSDU_CONTINUATION BIT(2) 595 #define RX_MSDU_DESC_INFO0_MSDU_LENGTH GENMASK(16, 3) 596 #define RX_MSDU_DESC_INFO0_MSDU_DROP BIT(17) 597 #define RX_MSDU_DESC_INFO0_VALID_SA BIT(18) 598 #define RX_MSDU_DESC_INFO0_VALID_DA BIT(19) 599 #define RX_MSDU_DESC_INFO0_DA_MCBC BIT(20) 600 #define RX_MSDU_DESC_INFO0_L3_HDR_PAD_MSB BIT(21) 601 #define RX_MSDU_DESC_INFO0_TCP_UDP_CHKSUM_FAIL BIT(22) 602 #define RX_MSDU_DESC_INFO0_IP_CHKSUM_FAIL BIT(23) 603 #define RX_MSDU_DESC_INFO0_FROM_DS BIT(24) 604 #define RX_MSDU_DESC_INFO0_TO_DS BIT(25) 605 #define RX_MSDU_DESC_INFO0_INTRA_BSS BIT(26) 606 #define RX_MSDU_DESC_INFO0_DST_CHIP_ID GENMASK(28, 27) 607 #define RX_MSDU_DESC_INFO0_DECAP_FORMAT GENMASK(30, 29) 608 609 #define HAL_RX_MSDU_PKT_LENGTH_GET(val) \ 610 (le32_get_bits((val), RX_MSDU_DESC_INFO0_MSDU_LENGTH)) 611 612 struct rx_msdu_desc { 613 __le32 info0; 614 } __packed; 615 616 /* rx_msdu_desc 617 * 618 * first_msdu_in_mpdu 619 * Indicates first msdu in mpdu. 620 * 621 * last_msdu_in_mpdu 622 * Indicates last msdu in mpdu. This flag can be true only when 623 * 'Msdu_continuation' set to 0. This implies that when an msdu 624 * is spread out over multiple buffers and thus msdu_continuation 625 * is set, only for the very last buffer of the msdu, can the 626 * 'last_msdu_in_mpdu' be set. 627 * 628 * When both first_msdu_in_mpdu and last_msdu_in_mpdu are set, 629 * the MPDU that this MSDU belongs to only contains a single MSDU. 630 * 631 * msdu_continuation 632 * When set, this MSDU buffer was not able to hold the entire MSDU. 633 * The next buffer will therefore contain additional information 634 * related to this MSDU. 635 * 636 * msdu_length 637 * Field is only valid in combination with the 'first_msdu_in_mpdu' 638 * being set. Full MSDU length in bytes after decapsulation. This 639 * field is still valid for MPDU frames without A-MSDU. It still 640 * represents MSDU length after decapsulation Or in case of RAW 641 * MPDUs, it indicates the length of the entire MPDU (without FCS 642 * field). 643 * 644 * msdu_drop 645 * Indicates that REO shall drop this MSDU and not forward it to 646 * any other ring. 647 * 648 * valid_sa 649 * Indicates OLE found a valid SA entry for this MSDU. 650 * 651 * valid_da 652 * When set, OLE found a valid DA entry for this MSDU. 653 * 654 * da_mcbc 655 * Field Only valid if valid_da is set. Indicates the DA address 656 * is a Multicast or Broadcast address for this MSDU. 657 * 658 * l3_header_padding_msb 659 * Passed on from 'RX_MSDU_END' TLV (only the MSB is reported as 660 * the LSB is always zero). Number of bytes padded to make sure 661 * that the L3 header will always start of a Dword boundary 662 * 663 * tcp_udp_checksum_fail 664 * Passed on from 'RX_ATTENTION' TLV 665 * Indicates that the computed checksum did not match the checksum 666 * in the TCP/UDP header. 667 * 668 * ip_checksum_fail 669 * Passed on from 'RX_ATTENTION' TLV 670 * Indicates that the computed checksum did not match the checksum 671 * in the IP header. 672 * 673 * from_DS 674 * Set if the 'from DS' bit is set in the frame control. 675 * 676 * to_DS 677 * Set if the 'to DS' bit is set in the frame control. 678 * 679 * intra_bss 680 * This packet needs intra-BSS routing by SW as the 'vdev_id' 681 * for the destination is the same as the 'vdev_id' that this 682 * MSDU was got in. 683 * 684 * dest_chip_id 685 * If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 686 * to support intra-BSS routing with multi-chip multi-link operation. 687 * This indicates into which chip's TCL the packet should be queued. 688 * 689 * decap_format 690 * Indicates the format after decapsulation: 691 */ 692 693 #define RX_MSDU_EXT_DESC_INFO0_REO_DEST_IND GENMASK(4, 0) 694 #define RX_MSDU_EXT_DESC_INFO0_SERVICE_CODE GENMASK(13, 5) 695 #define RX_MSDU_EXT_DESC_INFO0_PRIORITY_VALID BIT(14) 696 #define RX_MSDU_EXT_DESC_INFO0_DATA_OFFSET GENMASK(26, 15) 697 #define RX_MSDU_EXT_DESC_INFO0_SRC_LINK_ID GENMASK(29, 27) 698 699 struct rx_msdu_ext_desc { 700 __le32 info0; 701 } __packed; 702 703 /* rx_msdu_ext_desc 704 * 705 * reo_destination_indication 706 * The ID of the REO exit ring where the MSDU frame shall push 707 * after (MPDU level) reordering has finished. 708 * 709 * service_code 710 * Opaque service code between PPE and Wi-Fi 711 * 712 * priority_valid 713 * 714 * data_offset 715 * The offset to Rx packet data within the buffer (including 716 * Rx DMA offset programming and L3 header padding inserted 717 * by Rx OLE). 718 * 719 * src_link_id 720 * Set to the link ID of the PMAC that received the frame 721 */ 722 723 #define HAL_REO_DEST_RING_INFO0_BUFFER_TYPE BIT(0) 724 #define HAL_REO_DEST_RING_INFO0_PUSH_REASON GENMASK(2, 1) 725 #define HAL_REO_DEST_RING_INFO0_ERROR_CODE GENMASK(7, 3) 726 #define HAL_REO_DEST_RING_INFO0_MSDU_DATA_SIZE GENMASK(11, 8) 727 #define HAL_REO_DEST_RING_INFO0_SW_EXCEPTION BIT(12) 728 #define HAL_REO_DEST_RING_INFO0_SRC_LINK_ID GENMASK(15, 13) 729 #define HAL_REO_DEST_RING_INFO0_SIGNATURE GENMASK(19, 16) 730 #define HAL_REO_DEST_RING_INFO0_RING_ID GENMASK(27, 20) 731 #define HAL_REO_DEST_RING_INFO0_LOOPING_COUNT GENMASK(31, 28) 732 733 struct hal_reo_dest_ring { 734 struct ath12k_buffer_addr buf_addr_info; 735 struct rx_mpdu_desc rx_mpdu_info; 736 struct rx_msdu_desc rx_msdu_info; 737 __le32 buf_va_lo; 738 __le32 buf_va_hi; 739 __le32 info0; /* %HAL_REO_DEST_RING_INFO0_ */ 740 } __packed; 741 742 /* hal_reo_dest_ring 743 * 744 * Producer: RXDMA 745 * Consumer: REO/SW/FW 746 * 747 * buf_addr_info 748 * Details of the physical address of a buffer or MSDU 749 * link descriptor. 750 * 751 * rx_mpdu_info 752 * General information related to the MPDU that is passed 753 * on from REO entrance ring to the REO destination ring. 754 * 755 * rx_msdu_info 756 * General information related to the MSDU that is passed 757 * on from RXDMA all the way to the REO destination ring. 758 * 759 * buf_va_lo 760 * Field only valid if Reo_dest_buffer_type is set to MSDU_buf_address 761 * Lower 32 bits of the 64-bit virtual address corresponding 762 * to Buf_or_link_desc_addr_info 763 * 764 * buf_va_hi 765 * Address (upper 32 bits) of the REO queue descriptor. 766 * Upper 32 bits of the 64-bit virtual address corresponding 767 * to Buf_or_link_desc_addr_info 768 * 769 * buffer_type 770 * Indicates the type of address provided in the buf_addr_info. 771 * Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_. 772 * 773 * push_reason 774 * Reason for pushing this frame to this exit ring. Values are 775 * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_. 776 * 777 * error_code 778 * Valid only when 'push_reason' is set. All error codes are 779 * defined in enum %HAL_REO_DEST_RING_ERROR_CODE_. 780 * 781 * captured_msdu_data_size 782 * The number of following REO_DESTINATION STRUCTs that have 783 * been replaced with msdu_data extracted from the msdu_buffer 784 * and copied into the ring for easy FW/SW access. 785 * 786 * sw_exception 787 * This field has the same setting as the SW_exception field 788 * in the corresponding REO_entrance_ring descriptor. 789 * When set, the REO entrance descriptor is generated by FW, 790 * and the MPDU was processed in the following way: 791 * - NO re-order function is needed. 792 * - MPDU delinking is determined by the setting of Entrance 793 * ring field: SW_excection_mpdu_delink 794 * - Destination ring selection is based on the setting of 795 * the Entrance ring field SW_exception_destination _ring_valid 796 * 797 * src_link_id 798 * Set to the link ID of the PMAC that received the frame 799 * 800 * signature 801 * Set to value 0x8 when msdu capture mode is enabled for this ring 802 * 803 * ring_id 804 * The buffer pointer ring id. 805 * 0 - Idle ring 806 * 1 - N refers to other rings. 807 * 808 * looping_count 809 * Indicates the number of times the producer of entries into 810 * this ring has looped around the ring. 811 */ 812 813 #define HAL_REO_TO_PPE_RING_INFO0_DATA_LENGTH GENMASK(15, 0) 814 #define HAL_REO_TO_PPE_RING_INFO0_DATA_OFFSET GENMASK(23, 16) 815 #define HAL_REO_TO_PPE_RING_INFO0_POOL_ID GENMASK(28, 24) 816 #define HAL_REO_TO_PPE_RING_INFO0_PREHEADER BIT(29) 817 #define HAL_REO_TO_PPE_RING_INFO0_TSO_EN BIT(30) 818 #define HAL_REO_TO_PPE_RING_INFO0_MORE BIT(31) 819 820 struct hal_reo_to_ppe_ring { 821 __le32 buffer_addr; 822 __le32 info0; /* %HAL_REO_TO_PPE_RING_INFO0_ */ 823 } __packed; 824 825 /* hal_reo_to_ppe_ring 826 * 827 * Producer: REO 828 * Consumer: PPE 829 * 830 * buf_addr_info 831 * Details of the physical address of a buffer or MSDU 832 * link descriptor. 833 * 834 * data_length 835 * Length of valid data in bytes 836 * 837 * data_offset 838 * Offset to the data from buffer pointer. Can be used to 839 * strip header in the data for tunnel termination etc. 840 * 841 * pool_id 842 * REO has global configuration register for this field. 843 * It may have several free buffer pools, each 844 * RX-Descriptor ring can fetch free buffer from specific 845 * buffer pool; pool id will indicate which pool the buffer 846 * will be released to; POOL_ID Zero returned to SW 847 * 848 * preheader 849 * Disabled: 0 (Default) 850 * Enabled: 1 851 * 852 * tso_en 853 * Disabled: 0 (Default) 854 * Enabled: 1 855 * 856 * more 857 * More Segments followed 858 */ 859 860 enum hal_rx_reo_dest_ring { 861 HAL_RX_REO_DEST_RING_TCL, 862 HAL_RX_REO_DEST_RING_SW1, 863 HAL_RX_REO_DEST_RING_SW2, 864 HAL_RX_REO_DEST_RING_SW3, 865 HAL_RX_REO_DEST_RING_SW4, 866 HAL_RX_REO_DEST_RING_RELEASE, 867 HAL_RX_REO_DEST_RING_FW, 868 HAL_RX_REO_DEST_RING_SW5, 869 HAL_RX_REO_DEST_RING_SW6, 870 HAL_RX_REO_DEST_RING_SW7, 871 HAL_RX_REO_DEST_RING_SW8, 872 }; 873 874 #define HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 875 #define HAL_REO_ENTR_RING_INFO0_MPDU_BYTE_COUNT GENMASK(21, 8) 876 #define HAL_REO_ENTR_RING_INFO0_DEST_IND GENMASK(26, 22) 877 #define HAL_REO_ENTR_RING_INFO0_FRAMELESS_BAR BIT(27) 878 879 #define HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON GENMASK(1, 0) 880 #define HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE GENMASK(6, 2) 881 #define HAL_REO_ENTR_RING_INFO1_MPDU_FRAG_NUM GENMASK(10, 7) 882 #define HAL_REO_ENTR_RING_INFO1_SW_EXCEPTION BIT(11) 883 #define HAL_REO_ENTR_RING_INFO1_SW_EXCEPT_MPDU_DELINK BIT(12) 884 #define HAL_REO_ENTR_RING_INFO1_SW_EXCEPTION_RING_VLD BIT(13) 885 #define HAL_REO_ENTR_RING_INFO1_SW_EXCEPTION_RING GENMASK(18, 14) 886 #define HAL_REO_ENTR_RING_INFO1_MPDU_SEQ_NUM GENMASK(30, 19) 887 888 #define HAL_REO_ENTR_RING_INFO2_PHY_PPDU_ID GENMASK(15, 0) 889 #define HAL_REO_ENTR_RING_INFO2_SRC_LINK_ID GENMASK(18, 16) 890 #define HAL_REO_ENTR_RING_INFO2_RING_ID GENMASK(27, 20) 891 #define HAL_REO_ENTR_RING_INFO2_LOOPING_COUNT GENMASK(31, 28) 892 893 struct hal_reo_entrance_ring { 894 struct ath12k_buffer_addr buf_addr_info; 895 struct rx_mpdu_desc rx_mpdu_info; 896 __le32 queue_addr_lo; 897 __le32 info0; /* %HAL_REO_ENTR_RING_INFO0_ */ 898 __le32 info1; /* %HAL_REO_ENTR_RING_INFO1_ */ 899 __le32 info2; /* %HAL_REO_DEST_RING_INFO2_ */ 900 901 } __packed; 902 903 /* hal_reo_entrance_ring 904 * 905 * Producer: RXDMA 906 * Consumer: REO 907 * 908 * buf_addr_info 909 * Details of the physical address of a buffer or MSDU 910 * link descriptor. 911 * 912 * rx_mpdu_info 913 * General information related to the MPDU that is passed 914 * on from REO entrance ring to the REO destination ring. 915 * 916 * queue_addr_lo 917 * Address (lower 32 bits) of the REO queue descriptor. 918 * 919 * queue_addr_hi 920 * Address (upper 8 bits) of the REO queue descriptor. 921 * 922 * mpdu_byte_count 923 * An approximation of the number of bytes received in this MPDU. 924 * Used to keeps stats on the amount of data flowing 925 * through a queue. 926 * 927 * reo_destination_indication 928 * The id of the reo exit ring where the msdu frame shall push 929 * after (MPDU level) reordering has finished. Values are defined 930 * in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_. 931 * 932 * frameless_bar 933 * Indicates that this REO entrance ring struct contains BAR info 934 * from a multi TID BAR frame. The original multi TID BAR frame 935 * itself contained all the REO info for the first TID, but all 936 * the subsequent TID info and their linkage to the REO descriptors 937 * is passed down as 'frameless' BAR info. 938 * 939 * The only fields valid in this descriptor when this bit is set 940 * are queue_addr_lo, queue_addr_hi, mpdu_sequence_number, 941 * bar_frame and peer_meta_data. 942 * 943 * rxdma_push_reason 944 * Reason for pushing this frame to this exit ring. Values are 945 * defined in enum %HAL_REO_ENTR_RING_RXDMA_PUSH_REASON_. 946 * 947 * rxdma_error_code 948 * Valid only when 'push_reason' is set. All error codes are 949 * defined in enum %HAL_REO_ENTR_RING_RXDMA_ECODE_. 950 * 951 * mpdu_fragment_number 952 * Field only valid when Reo_level_mpdu_frame_info. 953 * Rx_mpdu_desc_info_details.Fragment_flag is set. 954 * 955 * sw_exception 956 * When not set, REO is performing all its default MPDU processing 957 * operations, 958 * When set, this REO entrance descriptor is generated by FW, and 959 * should be processed as an exception. This implies: 960 * NO re-order function is needed. 961 * MPDU delinking is determined by the setting of field 962 * SW_excection_mpdu_delink 963 * 964 * sw_exception_mpdu_delink 965 * Field only valid when SW_exception is set. 966 * 1'b0: REO should NOT delink the MPDU, and thus pass this 967 * MPDU on to the destination ring as is. This implies that 968 * in the REO_DESTINATION_RING struct field 969 * Buf_or_link_desc_addr_info should point to an MSDU link 970 * descriptor 971 * 1'b1: REO should perform the normal MPDU delink into MSDU operations. 972 * 973 * sw_exception_dest_ring 974 * Field only valid when fields SW_exception and SW 975 * exception_destination_ring_valid are set. values are defined 976 * in %HAL_RX_REO_DEST_RING_. 977 * 978 * mpdu_seq_number 979 * The field can have two different meanings based on the setting 980 * of sub-field Reo level mpdu frame info. 981 * Rx_mpdu_desc_info_details. BAR_frame 982 * 'BAR_frame' is NOT set: 983 * The MPDU sequence number of the received frame. 984 * 'BAR_frame' is set. 985 * The MPDU Start sequence number from the BAR frame 986 * 987 * phy_ppdu_id 988 * A PPDU counter value that PHY increments for every PPDU received 989 * 990 * src_link_id 991 * Set to the link ID of the PMAC that received the frame 992 * 993 * ring_id 994 * The buffer pointer ring id. 995 * 0 - Idle ring 996 * 1 - N refers to other rings. 997 * 998 * looping_count 999 * Indicates the number of times the producer of entries into 1000 * this ring has looped around the ring. 1001 */ 1002 1003 #define HAL_REO_CMD_HDR_INFO0_CMD_NUMBER GENMASK(15, 0) 1004 #define HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED BIT(16) 1005 1006 struct hal_reo_cmd_hdr { 1007 __le32 info0; 1008 } __packed; 1009 1010 #define HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 1011 #define HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS BIT(8) 1012 1013 struct hal_reo_get_queue_stats { 1014 struct hal_reo_cmd_hdr cmd; 1015 __le32 queue_addr_lo; 1016 __le32 info0; 1017 __le32 rsvd0[6]; 1018 __le32 tlv64_pad; 1019 } __packed; 1020 1021 /* hal_reo_get_queue_stats 1022 * Producer: SW 1023 * Consumer: REO 1024 * 1025 * cmd 1026 * Details for command execution tracking purposes. 1027 * 1028 * queue_addr_lo 1029 * Address (lower 32 bits) of the REO queue descriptor. 1030 * 1031 * queue_addr_hi 1032 * Address (upper 8 bits) of the REO queue descriptor. 1033 * 1034 * clear_stats 1035 * Clear stats settings. When set, Clear the stats after 1036 * generating the status. 1037 * 1038 * Following stats will be cleared. 1039 * Timeout_count 1040 * Forward_due_to_bar_count 1041 * Duplicate_count 1042 * Frames_in_order_count 1043 * BAR_received_count 1044 * MPDU_Frames_processed_count 1045 * MSDU_Frames_processed_count 1046 * Total_processed_byte_count 1047 * Late_receive_MPDU_count 1048 * window_jump_2k 1049 * Hole_count 1050 */ 1051 1052 struct hal_reo_get_queue_stats_qcc2072 { 1053 struct hal_reo_cmd_hdr cmd; 1054 __le32 queue_addr_lo; 1055 __le32 info0; 1056 __le32 rsvd0[6]; 1057 } __packed; 1058 1059 #define HAL_REO_FLUSH_QUEUE_INFO0_DESC_ADDR_HI GENMASK(7, 0) 1060 #define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_DESC_ADDR BIT(8) 1061 #define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_RESRC_IDX GENMASK(10, 9) 1062 1063 struct hal_reo_flush_queue { 1064 struct hal_reo_cmd_hdr cmd; 1065 __le32 desc_addr_lo; 1066 __le32 info0; 1067 __le32 rsvd0[6]; 1068 } __packed; 1069 1070 #define HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI GENMASK(7, 0) 1071 #define HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS BIT(8) 1072 #define HAL_REO_FLUSH_CACHE_INFO0_RELEASE_BLOCK_IDX BIT(9) 1073 #define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX GENMASK(11, 10) 1074 #define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE BIT(12) 1075 #define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE BIT(13) 1076 #define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL BIT(14) 1077 #define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_QUEUE_1K_DESC BIT(15) 1078 1079 struct hal_reo_flush_cache { 1080 struct hal_reo_cmd_hdr cmd; 1081 __le32 cache_addr_lo; 1082 __le32 info0; 1083 __le32 rsvd0[6]; 1084 } __packed; 1085 1086 #define HAL_TCL_DATA_CMD_INFO0_CMD_TYPE BIT(0) 1087 #define HAL_TCL_DATA_CMD_INFO0_DESC_TYPE BIT(1) 1088 #define HAL_TCL_DATA_CMD_INFO0_BANK_ID GENMASK(7, 2) 1089 #define HAL_TCL_DATA_CMD_INFO0_TX_NOTIFY_FRAME GENMASK(10, 8) 1090 #define HAL_TCL_DATA_CMD_INFO0_HDR_LEN_READ_SEL BIT(11) 1091 #define HAL_TCL_DATA_CMD_INFO0_BUF_TIMESTAMP GENMASK(30, 12) 1092 #define HAL_TCL_DATA_CMD_INFO0_BUF_TIMESTAMP_VLD BIT(31) 1093 1094 #define HAL_TCL_DATA_CMD_INFO1_CMD_NUM GENMASK(31, 16) 1095 1096 #define HAL_TCL_DATA_CMD_INFO2_DATA_LEN GENMASK(15, 0) 1097 #define HAL_TCL_DATA_CMD_INFO2_IP4_CKSUM_EN BIT(16) 1098 #define HAL_TCL_DATA_CMD_INFO2_UDP4_CKSUM_EN BIT(17) 1099 #define HAL_TCL_DATA_CMD_INFO2_UDP6_CKSUM_EN BIT(18) 1100 #define HAL_TCL_DATA_CMD_INFO2_TCP4_CKSUM_EN BIT(19) 1101 #define HAL_TCL_DATA_CMD_INFO2_TCP6_CKSUM_EN BIT(20) 1102 #define HAL_TCL_DATA_CMD_INFO2_TO_FW BIT(21) 1103 #define HAL_TCL_DATA_CMD_INFO2_PKT_OFFSET GENMASK(31, 23) 1104 1105 #define HAL_TCL_DATA_CMD_INFO3_TID_OVERWRITE BIT(0) 1106 #define HAL_TCL_DATA_CMD_INFO3_FLOW_OVERRIDE_EN BIT(1) 1107 #define HAL_TCL_DATA_CMD_INFO3_CLASSIFY_INFO_SEL GENMASK(3, 2) 1108 #define HAL_TCL_DATA_CMD_INFO3_TID GENMASK(7, 4) 1109 #define HAL_TCL_DATA_CMD_INFO3_FLOW_OVERRIDE BIT(8) 1110 #define HAL_TCL_DATA_CMD_INFO3_PMAC_ID GENMASK(10, 9) 1111 #define HAL_TCL_DATA_CMD_INFO3_MSDU_COLOR GENMASK(12, 11) 1112 #define HAL_TCL_DATA_CMD_INFO3_VDEV_ID GENMASK(31, 24) 1113 1114 #define HAL_TCL_DATA_CMD_INFO4_SEARCH_INDEX GENMASK(19, 0) 1115 #define HAL_TCL_DATA_CMD_INFO4_CACHE_SET_NUM GENMASK(23, 20) 1116 #define HAL_TCL_DATA_CMD_INFO4_IDX_LOOKUP_OVERRIDE BIT(24) 1117 1118 #define HAL_TCL_DATA_CMD_INFO5_RING_ID GENMASK(27, 20) 1119 #define HAL_TCL_DATA_CMD_INFO5_LOOPING_COUNT GENMASK(31, 28) 1120 1121 struct hal_tcl_data_cmd { 1122 struct ath12k_buffer_addr buf_addr_info; 1123 __le32 info0; 1124 __le32 info1; 1125 __le32 info2; 1126 __le32 info3; 1127 __le32 info4; 1128 __le32 info5; 1129 } __packed; 1130 1131 /* hal_tcl_data_cmd 1132 * 1133 * buf_addr_info 1134 * Details of the physical address of a buffer or MSDU 1135 * link descriptor. 1136 * 1137 * tcl_cmd_type 1138 * used to select the type of TCL Command descriptor 1139 * 1140 * desc_type 1141 * Indicates the type of address provided in the buf_addr_info. 1142 * Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_. 1143 * 1144 * bank_id 1145 * used to select one of the TCL register banks for fields removed 1146 * from 'TCL_DATA_CMD' that do not change often within one virtual 1147 * device or a set of virtual devices: 1148 * 1149 * tx_notify_frame 1150 * TCL copies this value to 'TQM_ENTRANCE_RING' field FW_tx_notify_frame. 1151 * 1152 * hdr_length_read_sel 1153 * used to select the per 'encap_type' register set for MSDU header 1154 * read length 1155 * 1156 * buffer_timestamp 1157 * buffer_timestamp_valid 1158 * Frame system entrance timestamp. It shall be filled by first 1159 * module (SW, TCL or TQM) that sees the frames first. 1160 * 1161 * cmd_num 1162 * This number can be used to match against status. 1163 * 1164 * data_length 1165 * MSDU length in case of direct descriptor. Length of link 1166 * extension descriptor in case of Link extension descriptor. 1167 * 1168 * *_checksum_en 1169 * Enable checksum replacement for ipv4, udp_over_ipv4, ipv6, 1170 * udp_over_ipv6, tcp_over_ipv4 and tcp_over_ipv6. 1171 * 1172 * to_fw 1173 * Forward packet to FW along with classification result. The 1174 * packet will not be forward to TQM when this bit is set. 1175 * 1'b0: Use classification result to forward the packet. 1176 * 1'b1: Override classification result & forward packet only to fw 1177 * 1178 * packet_offset 1179 * Packet offset from Metadata in case of direct buffer descriptor. 1180 * 1181 * hlos_tid_overwrite 1182 * 1183 * When set, TCL shall ignore the IP DSCP and VLAN PCP 1184 * fields and use HLOS_TID as the final TID. Otherwise TCL 1185 * shall consider the DSCP and PCP fields as well as HLOS_TID 1186 * and choose a final TID based on the configured priority 1187 * 1188 * flow_override_enable 1189 * TCL uses this to select the flow pointer from the peer table, 1190 * which can be overridden by SW for pre-encrypted raw WiFi packets 1191 * that cannot be parsed for UDP or for other MLO 1192 * 0 - FP_PARSE_IP: Use the flow-pointer based on parsing the IPv4 1193 * or IPv6 header. 1194 * 1 - FP_USE_OVERRIDE: Use the who_classify_info_sel and 1195 * flow_override fields to select the flow-pointer 1196 * 1197 * who_classify_info_sel 1198 * Field only valid when flow_override_enable is set to FP_USE_OVERRIDE. 1199 * This field is used to select one of the 'WHO_CLASSIFY_INFO's in the 1200 * peer table in case more than 2 flows are mapped to a single TID. 1201 * 0: To choose Flow 0 and 1 of any TID use this value. 1202 * 1: To choose Flow 2 and 3 of any TID use this value. 1203 * 2: To choose Flow 4 and 5 of any TID use this value. 1204 * 3: To choose Flow 6 and 7 of any TID use this value. 1205 * 1206 * If who_classify_info sel is not in sync with the num_tx_classify_info 1207 * field from address search, then TCL will set 'who_classify_info_sel' 1208 * to 0 use flows 0 and 1. 1209 * 1210 * hlos_tid 1211 * HLOS MSDU priority 1212 * Field is used when HLOS_TID_overwrite is set. 1213 * 1214 * flow_override 1215 * Field only valid when flow_override_enable is set to FP_USE_OVERRIDE 1216 * TCL uses this to select the flow pointer from the peer table, 1217 * which can be overridden by SW for pre-encrypted raw WiFi packets 1218 * that cannot be parsed for UDP or for other MLO 1219 * 0 - FP_USE_NON_UDP: Use the non-UDP flow pointer (flow 0) 1220 * 1 - FP_USE_UDP: Use the UDP flow pointer (flow 1) 1221 * 1222 * pmac_id 1223 * TCL uses this PMAC_ID in address search, i.e, while 1224 * finding matching entry for the packet in AST corresponding 1225 * to given PMAC_ID 1226 * 1227 * If PMAC ID is all 1s (=> value 3), it indicates wildcard 1228 * match for any PMAC 1229 * 1230 * vdev_id 1231 * Virtual device ID to check against the address search entry to 1232 * avoid security issues from transmitting packets from an incorrect 1233 * virtual device 1234 * 1235 * search_index 1236 * The index that will be used for index based address or 1237 * flow search. The field is valid when 'search_type' is 1 or 2. 1238 * 1239 * cache_set_num 1240 * 1241 * Cache set number that should be used to cache the index 1242 * based search results, for address and flow search. This 1243 * value should be equal to LSB four bits of the hash value of 1244 * match data, in case of search index points to an entry which 1245 * may be used in content based search also. The value can be 1246 * anything when the entry pointed by search index will not be 1247 * used for content based search. 1248 * 1249 * index_loop_override 1250 * When set, address search and packet routing is forced to use 1251 * 'search_index' instead of following the register configuration 1252 * selected by Bank_id. 1253 * 1254 * ring_id 1255 * The buffer pointer ring ID. 1256 * 0 refers to the IDLE ring 1257 * 1 - N refers to other rings 1258 * 1259 * looping_count 1260 * 1261 * A count value that indicates the number of times the 1262 * producer of entries into the Ring has looped around the 1263 * ring. 1264 * 1265 * At initialization time, this value is set to 0. On the 1266 * first loop, this value is set to 1. After the max value is 1267 * reached allowed by the number of bits for this field, the 1268 * count value continues with 0 again. 1269 * 1270 * In case SW is the consumer of the ring entries, it can 1271 * use this field to figure out up to where the producer of 1272 * entries has created new entries. This eliminates the need to 1273 * check where the head pointer' of the ring is located once 1274 * the SW starts processing an interrupt indicating that new 1275 * entries have been put into this ring... 1276 * 1277 * Also note that SW if it wants only needs to look at the 1278 * LSB bit of this count value. 1279 */ 1280 1281 #define HAL_TCL_DESC_LEN sizeof(struct hal_tcl_data_cmd) 1282 1283 #define HAL_TX_MSDU_EXT_INFO0_BUF_PTR_LO GENMASK(31, 0) 1284 1285 #define HAL_TX_MSDU_EXT_INFO1_BUF_PTR_HI GENMASK(7, 0) 1286 #define HAL_TX_MSDU_EXT_INFO1_EXTN_OVERRIDE BIT(8) 1287 #define HAL_TX_MSDU_EXT_INFO1_ENCAP_TYPE GENMASK(10, 9) 1288 #define HAL_TX_MSDU_EXT_INFO1_ENCRYPT_TYPE GENMASK(14, 11) 1289 #define HAL_TX_MSDU_EXT_INFO1_BUF_LEN GENMASK(31, 16) 1290 1291 struct hal_tx_msdu_ext_desc { 1292 __le32 rsvd0[6]; 1293 __le32 info0; 1294 __le32 info1; 1295 __le32 rsvd1[10]; 1296 }; 1297 1298 struct hal_tcl_gse_cmd { 1299 __le32 ctrl_buf_addr_lo; 1300 __le32 info0; 1301 __le32 meta_data[2]; 1302 __le32 rsvd0[2]; 1303 __le32 info1; 1304 } __packed; 1305 1306 /* hal_tcl_gse_cmd 1307 * 1308 * ctrl_buf_addr_lo, ctrl_buf_addr_hi 1309 * Address of a control buffer containing additional info needed 1310 * for this command execution. 1311 * 1312 * meta_data 1313 * Meta data to be returned in the status descriptor 1314 */ 1315 1316 enum hal_tcl_cache_op_res { 1317 HAL_TCL_CACHE_OP_RES_DONE, 1318 HAL_TCL_CACHE_OP_RES_NOT_FOUND, 1319 HAL_TCL_CACHE_OP_RES_TIMEOUT, 1320 }; 1321 1322 struct hal_tcl_status_ring { 1323 __le32 info0; 1324 __le32 msdu_byte_count; 1325 __le32 msdu_timestamp; 1326 __le32 meta_data[2]; 1327 __le32 info1; 1328 __le32 rsvd0; 1329 __le32 info2; 1330 } __packed; 1331 1332 /* hal_tcl_status_ring 1333 * 1334 * msdu_cnt 1335 * msdu_byte_count 1336 * MSDU count of Entry and MSDU byte count for entry 1. 1337 * 1338 */ 1339 1340 #define HAL_CE_SRC_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0) 1341 #define HAL_CE_SRC_DESC_ADDR_INFO_HASH_EN BIT(8) 1342 #define HAL_CE_SRC_DESC_ADDR_INFO_BYTE_SWAP BIT(9) 1343 #define HAL_CE_SRC_DESC_ADDR_INFO_DEST_SWAP BIT(10) 1344 #define HAL_CE_SRC_DESC_ADDR_INFO_GATHER BIT(11) 1345 #define HAL_CE_SRC_DESC_ADDR_INFO_LEN GENMASK(31, 16) 1346 1347 #define HAL_CE_SRC_DESC_META_INFO_DATA GENMASK(15, 0) 1348 1349 #define HAL_CE_SRC_DESC_FLAGS_RING_ID GENMASK(27, 20) 1350 #define HAL_CE_SRC_DESC_FLAGS_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT 1351 1352 struct hal_ce_srng_src_desc { 1353 __le32 buffer_addr_low; 1354 __le32 buffer_addr_info; /* %HAL_CE_SRC_DESC_ADDR_INFO_ */ 1355 __le32 meta_info; /* %HAL_CE_SRC_DESC_META_INFO_ */ 1356 __le32 flags; /* %HAL_CE_SRC_DESC_FLAGS_ */ 1357 } __packed; 1358 1359 /* hal_ce_srng_src_desc 1360 * 1361 * buffer_addr_lo 1362 * LSB 32 bits of the 40 Bit Pointer to the source buffer 1363 * 1364 * buffer_addr_hi 1365 * MSB 8 bits of the 40 Bit Pointer to the source buffer 1366 * 1367 * toeplitz_en 1368 * Enable generation of 32-bit Toeplitz-LFSR hash for 1369 * data transfer. In case of gather field in first source 1370 * ring entry of the gather copy cycle in taken into account. 1371 * 1372 * src_swap 1373 * Treats source memory organization as big-endian. For 1374 * each dword read (4 bytes), the byte 0 is swapped with byte 3 1375 * and byte 1 is swapped with byte 2. 1376 * In case of gather field in first source ring entry of 1377 * the gather copy cycle in taken into account. 1378 * 1379 * dest_swap 1380 * Treats destination memory organization as big-endian. 1381 * For each dword write (4 bytes), the byte 0 is swapped with 1382 * byte 3 and byte 1 is swapped with byte 2. 1383 * In case of gather field in first source ring entry of 1384 * the gather copy cycle in taken into account. 1385 * 1386 * gather 1387 * Enables gather of multiple copy engine source 1388 * descriptors to one destination. 1389 * 1390 * ce_res_0 1391 * Reserved 1392 * 1393 * 1394 * length 1395 * Length of the buffer in units of octets of the current 1396 * descriptor 1397 * 1398 * fw_metadata 1399 * Meta data used by FW. 1400 * In case of gather field in first source ring entry of 1401 * the gather copy cycle in taken into account. 1402 * 1403 * ce_res_1 1404 * Reserved 1405 * 1406 * ce_res_2 1407 * Reserved 1408 * 1409 * ring_id 1410 * The buffer pointer ring ID. 1411 * 0 refers to the IDLE ring 1412 * 1 - N refers to other rings 1413 * Helps with debugging when dumping ring contents. 1414 * 1415 * looping_count 1416 * A count value that indicates the number of times the 1417 * producer of entries into the Ring has looped around the 1418 * ring. 1419 * 1420 * At initialization time, this value is set to 0. On the 1421 * first loop, this value is set to 1. After the max value is 1422 * reached allowed by the number of bits for this field, the 1423 * count value continues with 0 again. 1424 * 1425 * In case SW is the consumer of the ring entries, it can 1426 * use this field to figure out up to where the producer of 1427 * entries has created new entries. This eliminates the need to 1428 * check where the head pointer' of the ring is located once 1429 * the SW starts processing an interrupt indicating that new 1430 * entries have been put into this ring... 1431 * 1432 * Also note that SW if it wants only needs to look at the 1433 * LSB bit of this count value. 1434 */ 1435 1436 #define HAL_CE_DEST_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0) 1437 #define HAL_CE_DEST_DESC_ADDR_INFO_RING_ID GENMASK(27, 20) 1438 #define HAL_CE_DEST_DESC_ADDR_INFO_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT 1439 1440 struct hal_ce_srng_dest_desc { 1441 __le32 buffer_addr_low; 1442 __le32 buffer_addr_info; /* %HAL_CE_DEST_DESC_ADDR_INFO_ */ 1443 } __packed; 1444 1445 /* hal_ce_srng_dest_desc 1446 * 1447 * dst_buffer_low 1448 * LSB 32 bits of the 40 Bit Pointer to the Destination 1449 * buffer 1450 * 1451 * dst_buffer_high 1452 * MSB 8 bits of the 40 Bit Pointer to the Destination 1453 * buffer 1454 * 1455 * ce_res_4 1456 * Reserved 1457 * 1458 * ring_id 1459 * The buffer pointer ring ID. 1460 * 0 refers to the IDLE ring 1461 * 1 - N refers to other rings 1462 * Helps with debugging when dumping ring contents. 1463 * 1464 * looping_count 1465 * A count value that indicates the number of times the 1466 * producer of entries into the Ring has looped around the 1467 * ring. 1468 * 1469 * At initialization time, this value is set to 0. On the 1470 * first loop, this value is set to 1. After the max value is 1471 * reached allowed by the number of bits for this field, the 1472 * count value continues with 0 again. 1473 * 1474 * In case SW is the consumer of the ring entries, it can 1475 * use this field to figure out up to where the producer of 1476 * entries has created new entries. This eliminates the need to 1477 * check where the head pointer' of the ring is located once 1478 * the SW starts processing an interrupt indicating that new 1479 * entries have been put into this ring... 1480 * 1481 * Also note that SW if it wants only needs to look at the 1482 * LSB bit of this count value. 1483 */ 1484 1485 #define HAL_CE_DST_STATUS_DESC_FLAGS_HASH_EN BIT(8) 1486 #define HAL_CE_DST_STATUS_DESC_FLAGS_BYTE_SWAP BIT(9) 1487 #define HAL_CE_DST_STATUS_DESC_FLAGS_DEST_SWAP BIT(10) 1488 #define HAL_CE_DST_STATUS_DESC_FLAGS_GATHER BIT(11) 1489 #define HAL_CE_DST_STATUS_DESC_FLAGS_LEN GENMASK(31, 16) 1490 1491 #define HAL_CE_DST_STATUS_DESC_META_INFO_DATA GENMASK(15, 0) 1492 #define HAL_CE_DST_STATUS_DESC_META_INFO_RING_ID GENMASK(27, 20) 1493 #define HAL_CE_DST_STATUS_DESC_META_INFO_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT 1494 1495 struct hal_ce_srng_dst_status_desc { 1496 __le32 flags; /* %HAL_CE_DST_STATUS_DESC_FLAGS_ */ 1497 __le32 toeplitz_hash0; 1498 __le32 toeplitz_hash1; 1499 __le32 meta_info; /* HAL_CE_DST_STATUS_DESC_META_INFO_ */ 1500 } __packed; 1501 1502 /* hal_ce_srng_dst_status_desc 1503 * 1504 * ce_res_5 1505 * Reserved 1506 * 1507 * toeplitz_en 1508 * 1509 * src_swap 1510 * Source memory buffer swapped 1511 * 1512 * dest_swap 1513 * Destination memory buffer swapped 1514 * 1515 * gather 1516 * Gather of multiple copy engine source descriptors to one 1517 * destination enabled 1518 * 1519 * ce_res_6 1520 * Reserved 1521 * 1522 * length 1523 * Sum of all the Lengths of the source descriptor in the 1524 * gather chain 1525 * 1526 * toeplitz_hash_0 1527 * 32 LS bits of 64 bit Toeplitz LFSR hash result 1528 * 1529 * toeplitz_hash_1 1530 * 32 MS bits of 64 bit Toeplitz LFSR hash result 1531 * 1532 * fw_metadata 1533 * Meta data used by FW 1534 * In case of gather field in first source ring entry of 1535 * the gather copy cycle in taken into account. 1536 * 1537 * ce_res_7 1538 * Reserved 1539 * 1540 * ring_id 1541 * The buffer pointer ring ID. 1542 * 0 refers to the IDLE ring 1543 * 1 - N refers to other rings 1544 * Helps with debugging when dumping ring contents. 1545 * 1546 * looping_count 1547 * A count value that indicates the number of times the 1548 * producer of entries into the Ring has looped around the 1549 * ring. 1550 * 1551 * At initialization time, this value is set to 0. On the 1552 * first loop, this value is set to 1. After the max value is 1553 * reached allowed by the number of bits for this field, the 1554 * count value continues with 0 again. 1555 * 1556 * In case SW is the consumer of the ring entries, it can 1557 * use this field to figure out up to where the producer of 1558 * entries has created new entries. This eliminates the need to 1559 * check where the head pointer' of the ring is located once 1560 * the SW starts processing an interrupt indicating that new 1561 * entries have been put into this ring... 1562 * 1563 * Also note that SW if it wants only needs to look at the 1564 * LSB bit of this count value. 1565 */ 1566 1567 #define HAL_TX_RATE_STATS_INFO0_VALID BIT(0) 1568 #define HAL_TX_RATE_STATS_INFO0_BW GENMASK(3, 1) 1569 #define HAL_TX_RATE_STATS_INFO0_PKT_TYPE GENMASK(7, 4) 1570 #define HAL_TX_RATE_STATS_INFO0_STBC BIT(8) 1571 #define HAL_TX_RATE_STATS_INFO0_LDPC BIT(9) 1572 #define HAL_TX_RATE_STATS_INFO0_SGI GENMASK(11, 10) 1573 #define HAL_TX_RATE_STATS_INFO0_MCS GENMASK(15, 12) 1574 #define HAL_TX_RATE_STATS_INFO0_OFDMA_TX BIT(16) 1575 #define HAL_TX_RATE_STATS_INFO0_TONES_IN_RU GENMASK(28, 17) 1576 1577 struct hal_tx_rate_stats { 1578 __le32 info0; 1579 __le32 tsf; 1580 } __packed; 1581 1582 #define HAL_WBM_COMPL_RX_INFO0_REL_SRC_MODULE GENMASK(2, 0) 1583 #define HAL_WBM_COMPL_RX_INFO0_BM_ACTION GENMASK(5, 3) 1584 #define HAL_WBM_COMPL_RX_INFO0_DESC_TYPE GENMASK(8, 6) 1585 #define HAL_WBM_COMPL_RX_INFO0_RBM GENMASK(12, 9) 1586 #define HAL_WBM_COMPL_RX_INFO0_RXDMA_PUSH_REASON GENMASK(18, 17) 1587 #define HAL_WBM_COMPL_RX_INFO0_RXDMA_ERROR_CODE GENMASK(23, 19) 1588 #define HAL_WBM_COMPL_RX_INFO0_REO_PUSH_REASON GENMASK(25, 24) 1589 #define HAL_WBM_COMPL_RX_INFO0_REO_ERROR_CODE GENMASK(30, 26) 1590 #define HAL_WBM_COMPL_RX_INFO0_WBM_INTERNAL_ERROR BIT(31) 1591 1592 #define HAL_WBM_COMPL_RX_INFO1_PHY_ADDR_HI GENMASK(7, 0) 1593 #define HAL_WBM_COMPL_RX_INFO1_SW_COOKIE GENMASK(27, 8) 1594 #define HAL_WBM_COMPL_RX_INFO1_LOOPING_COUNT GENMASK(31, 28) 1595 1596 struct hal_wbm_completion_ring_rx { 1597 __le32 addr_lo; 1598 __le32 addr_hi; 1599 __le32 info0; 1600 struct rx_mpdu_desc rx_mpdu_info; 1601 struct rx_msdu_desc rx_msdu_info; 1602 __le32 phy_addr_lo; 1603 __le32 info1; 1604 } __packed; 1605 1606 #define HAL_WBM_COMPL_TX_INFO0_REL_SRC_MODULE GENMASK(2, 0) 1607 #define HAL_WBM_COMPL_TX_INFO0_DESC_TYPE GENMASK(8, 6) 1608 #define HAL_WBM_COMPL_TX_INFO0_RBM GENMASK(12, 9) 1609 #define HAL_WBM_COMPL_TX_INFO0_TQM_RELEASE_REASON GENMASK(16, 13) 1610 #define HAL_WBM_COMPL_TX_INFO0_RBM_OVERRIDE_VLD BIT(17) 1611 #define HAL_WBM_COMPL_TX_INFO0_SW_COOKIE_LO GENMASK(29, 18) 1612 #define HAL_WBM_COMPL_TX_INFO0_CC_DONE BIT(30) 1613 #define HAL_WBM_COMPL_TX_INFO0_WBM_INTERNAL_ERROR BIT(31) 1614 1615 #define HAL_WBM_COMPL_TX_INFO1_TQM_STATUS_NUMBER GENMASK(23, 0) 1616 #define HAL_WBM_COMPL_TX_INFO1_TRANSMIT_COUNT GENMASK(30, 24) 1617 #define HAL_WBM_COMPL_TX_INFO1_SW_REL_DETAILS_VALID BIT(31) 1618 1619 #define HAL_WBM_COMPL_TX_INFO2_ACK_FRAME_RSSI GENMASK(7, 0) 1620 #define HAL_WBM_COMPL_TX_INFO2_FIRST_MSDU BIT(8) 1621 #define HAL_WBM_COMPL_TX_INFO2_LAST_MSDU BIT(9) 1622 #define HAL_WBM_COMPL_TX_INFO2_FW_TX_NOTIF_FRAME GENMASK(12, 10) 1623 #define HAL_WBM_COMPL_TX_INFO2_BUFFER_TIMESTAMP GENMASK(31, 13) 1624 1625 #define HAL_WBM_COMPL_TX_INFO3_PEER_ID GENMASK(15, 0) 1626 #define HAL_WBM_COMPL_TX_INFO3_TID GENMASK(19, 16) 1627 #define HAL_WBM_COMPL_TX_INFO3_SW_COOKIE_HI GENMASK(27, 20) 1628 #define HAL_WBM_COMPL_TX_INFO3_LOOPING_COUNT GENMASK(31, 28) 1629 1630 struct hal_wbm_completion_ring_tx { 1631 __le32 buf_va_lo; 1632 __le32 buf_va_hi; 1633 __le32 info0; 1634 __le32 info1; 1635 __le32 info2; 1636 struct hal_tx_rate_stats rate_stats; 1637 __le32 info3; 1638 } __packed; 1639 1640 #define HAL_WBM_RELEASE_TX_INFO0_REL_SRC_MODULE GENMASK(2, 0) 1641 #define HAL_WBM_RELEASE_TX_INFO0_BM_ACTION GENMASK(5, 3) 1642 #define HAL_WBM_RELEASE_TX_INFO0_DESC_TYPE GENMASK(8, 6) 1643 #define HAL_WBM_RELEASE_TX_INFO0_FIRST_MSDU_IDX GENMASK(12, 9) 1644 #define HAL_WBM_RELEASE_TX_INFO0_TQM_RELEASE_REASON GENMASK(18, 13) 1645 #define HAL_WBM_RELEASE_TX_INFO0_RBM_OVERRIDE_VLD BIT(17) 1646 #define HAL_WBM_RELEASE_TX_INFO0_SW_BUFFER_COOKIE_11_0 GENMASK(29, 18) 1647 #define HAL_WBM_RELEASE_TX_INFO0_WBM_INTERNAL_ERROR BIT(31) 1648 1649 #define HAL_WBM_RELEASE_TX_INFO1_TQM_STATUS_NUMBER GENMASK(23, 0) 1650 #define HAL_WBM_RELEASE_TX_INFO1_TRANSMIT_COUNT GENMASK(30, 24) 1651 #define HAL_WBM_RELEASE_TX_INFO1_SW_REL_DETAILS_VALID BIT(31) 1652 1653 #define HAL_WBM_RELEASE_TX_INFO2_ACK_FRAME_RSSI GENMASK(7, 0) 1654 #define HAL_WBM_RELEASE_TX_INFO2_FIRST_MSDU BIT(8) 1655 #define HAL_WBM_RELEASE_TX_INFO2_LAST_MSDU BIT(9) 1656 #define HAL_WBM_RELEASE_TX_INFO2_FW_TX_NOTIF_FRAME GENMASK(12, 10) 1657 #define HAL_WBM_RELEASE_TX_INFO2_BUFFER_TIMESTAMP GENMASK(31, 13) 1658 1659 #define HAL_WBM_RELEASE_TX_INFO3_PEER_ID GENMASK(15, 0) 1660 #define HAL_WBM_RELEASE_TX_INFO3_TID GENMASK(19, 16) 1661 #define HAL_WBM_RELEASE_TX_INFO3_SW_BUFFER_COOKIE_19_12 GENMASK(27, 20) 1662 #define HAL_WBM_RELEASE_TX_INFO3_LOOPING_COUNT GENMASK(31, 28) 1663 1664 struct hal_wbm_release_ring_tx { 1665 struct ath12k_buffer_addr buf_addr_info; 1666 __le32 info0; 1667 __le32 info1; 1668 __le32 info2; 1669 struct hal_tx_rate_stats rate_stats; 1670 __le32 info3; 1671 } __packed; 1672 1673 #define HAL_WBM_RELEASE_RX_INFO0_REL_SRC_MODULE GENMASK(2, 0) 1674 #define HAL_WBM_RELEASE_RX_INFO0_BM_ACTION GENMASK(5, 3) 1675 #define HAL_WBM_RELEASE_RX_INFO0_DESC_TYPE GENMASK(8, 6) 1676 #define HAL_WBM_RELEASE_RX_INFO0_FIRST_MSDU_IDX GENMASK(12, 9) 1677 #define HAL_WBM_RELEASE_RX_INFO0_CC_STATUS BIT(16) 1678 #define HAL_WBM_RELEASE_RX_INFO0_RXDMA_PUSH_REASON GENMASK(18, 17) 1679 #define HAL_WBM_RELEASE_RX_INFO0_RXDMA_ERROR_CODE GENMASK(23, 19) 1680 #define HAL_WBM_RELEASE_RX_INFO0_REO_PUSH_REASON GENMASK(25, 24) 1681 #define HAL_WBM_RELEASE_RX_INFO0_REO_ERROR_CODE GENMASK(30, 26) 1682 #define HAL_WBM_RELEASE_RX_INFO0_WBM_INTERNAL_ERROR BIT(31) 1683 1684 #define HAL_WBM_RELEASE_RX_INFO2_RING_ID GENMASK(27, 20) 1685 #define HAL_WBM_RELEASE_RX_INFO2_LOOPING_COUNT GENMASK(31, 28) 1686 1687 struct hal_wbm_release_ring_rx { 1688 struct ath12k_buffer_addr buf_addr_info; 1689 __le32 info0; 1690 struct rx_mpdu_desc rx_mpdu_info; 1691 struct rx_msdu_desc rx_msdu_info; 1692 __le32 info1; 1693 __le32 info2; 1694 } __packed; 1695 1696 #define HAL_WBM_RELEASE_RX_CC_INFO0_RBM GENMASK(12, 9) 1697 #define HAL_WBM_RELEASE_RX_CC_INFO1_COOKIE GENMASK(27, 8) 1698 /* Used when hw cc is success */ 1699 struct hal_wbm_release_ring_cc_rx { 1700 __le32 buf_va_lo; 1701 __le32 buf_va_hi; 1702 __le32 info0; 1703 struct rx_mpdu_desc rx_mpdu_info; 1704 struct rx_msdu_desc rx_msdu_info; 1705 __le32 buf_pa_lo; 1706 __le32 info1; 1707 } __packed; 1708 1709 #define HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE GENMASK(2, 0) 1710 #define HAL_WBM_RELEASE_INFO0_BM_ACTION GENMASK(5, 3) 1711 #define HAL_WBM_RELEASE_INFO0_DESC_TYPE GENMASK(8, 6) 1712 #define HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON GENMASK(18, 17) 1713 #define HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE GENMASK(23, 19) 1714 #define HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON GENMASK(25, 24) 1715 #define HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE GENMASK(30, 26) 1716 #define HAL_WBM_RELEASE_INFO0_WBM_INTERNAL_ERROR BIT(31) 1717 1718 #define HAL_WBM_RELEASE_INFO3_FIRST_MSDU BIT(0) 1719 #define HAL_WBM_RELEASE_INFO3_LAST_MSDU BIT(1) 1720 #define HAL_WBM_RELEASE_INFO3_CONTINUATION BIT(2) 1721 1722 #define HAL_WBM_RELEASE_INFO5_LOOPING_COUNT GENMASK(31, 28) 1723 1724 struct hal_wbm_release_ring { 1725 struct ath12k_buffer_addr buf_addr_info; 1726 __le32 info0; 1727 __le32 info1; 1728 __le32 info2; 1729 __le32 info3; 1730 __le32 info4; 1731 __le32 info5; 1732 } __packed; 1733 1734 /* hal_wbm_release_ring 1735 * 1736 * Producer: SW/TQM/RXDMA/REO/SWITCH 1737 * Consumer: WBM/SW/FW 1738 * 1739 * HTT tx status is overlaid on wbm_release ring on 4-byte words 2, 3, 4 and 5 1740 * for software based completions. 1741 * 1742 * buf_addr_info 1743 * Details of the physical address of the buffer or link descriptor. 1744 * 1745 * release_source_module 1746 * Indicates which module initiated the release of this buffer/descriptor. 1747 * Values are defined in enum %HAL_WBM_REL_SRC_MODULE_. 1748 * 1749 * buffer_or_desc_type 1750 * Field only valid when WBM is marked as the return_buffer_manager in 1751 * the Released_Buffer_address_info. Indicates that type of buffer or 1752 * descriptor is being released. Values are in enum %HAL_WBM_REL_DESC_TYPE. 1753 * 1754 * wbm_internal_error 1755 * Is set when WBM got a buffer pointer but the action was to push it to 1756 * the idle link descriptor ring or do link related activity OR 1757 * Is set when WBM got a link buffer pointer but the action was to push it 1758 * to the buffer descriptor ring. 1759 * 1760 * looping_count 1761 * A count value that indicates the number of times the 1762 * producer of entries into the Buffer Manager Ring has looped 1763 * around the ring. 1764 * 1765 * At initialization time, this value is set to 0. On the 1766 * first loop, this value is set to 1. After the max value is 1767 * reached allowed by the number of bits for this field, the 1768 * count value continues with 0 again. 1769 * 1770 * In case SW is the consumer of the ring entries, it can 1771 * use this field to figure out up to where the producer of 1772 * entries has created new entries. This eliminates the need to 1773 * check where the head pointer' of the ring is located once 1774 * the SW starts processing an interrupt indicating that new 1775 * entries have been put into this ring... 1776 * 1777 * Also note that SW if it wants only needs to look at the 1778 * LSB bit of this count value. 1779 */ 1780 1781 /** 1782 * enum hal_wbm_tqm_rel_reason - TQM release reason code 1783 * @HAL_WBM_TQM_REL_REASON_FRAME_ACKED: ACK or BACK received for the frame 1784 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU: Command remove_mpdus initiated by SW 1785 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX: Command remove transmitted_mpdus 1786 * initiated by sw. 1787 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX: Command remove untransmitted_mpdus 1788 * initiated by sw. 1789 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES: Command remove aged msdus or 1790 * mpdus. 1791 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1: Remove command initiated by 1792 * fw with fw_reason1. 1793 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2: Remove command initiated by 1794 * fw with fw_reason2. 1795 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3: Remove command initiated by 1796 * fw with fw_reason3. 1797 * @HAL_WBM_TQM_REL_REASON_CMD_DISABLE_QUEUE: Remove command initiated by 1798 * fw with disable queue. 1799 * @HAL_WBM_TQM_REL_REASON_CMD_TILL_NONMATCHING: Remove command initiated by 1800 * fw to remove all mpdu until 1st non-match. 1801 * @HAL_WBM_TQM_REL_REASON_DROP_THRESHOLD: Dropped due to drop threshold 1802 * criteria 1803 * @HAL_WBM_TQM_REL_REASON_DROP_LINK_DESC_UNAVAIL: Dropped due to link desc 1804 * not available 1805 * @HAL_WBM_TQM_REL_REASON_DROP_OR_INVALID_MSDU: Dropped due drop bit set or 1806 * null flow 1807 * @HAL_WBM_TQM_REL_REASON_MULTICAST_DROP: Dropped due mcast drop set for VDEV 1808 * @HAL_WBM_TQM_REL_REASON_VDEV_MISMATCH_DROP: Dropped due to being set with 1809 * 'TCL_drop_reason' 1810 */ 1811 enum hal_wbm_tqm_rel_reason { 1812 HAL_WBM_TQM_REL_REASON_FRAME_ACKED, 1813 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU, 1814 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX, 1815 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX, 1816 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES, 1817 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1, 1818 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2, 1819 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3, 1820 HAL_WBM_TQM_REL_REASON_CMD_DISABLE_QUEUE, 1821 HAL_WBM_TQM_REL_REASON_CMD_TILL_NONMATCHING, 1822 HAL_WBM_TQM_REL_REASON_DROP_THRESHOLD, 1823 HAL_WBM_TQM_REL_REASON_DROP_LINK_DESC_UNAVAIL, 1824 HAL_WBM_TQM_REL_REASON_DROP_OR_INVALID_MSDU, 1825 HAL_WBM_TQM_REL_REASON_MULTICAST_DROP, 1826 HAL_WBM_TQM_REL_REASON_VDEV_MISMATCH_DROP, 1827 }; 1828 1829 struct hal_wbm_buffer_ring { 1830 struct ath12k_buffer_addr buf_addr_info; 1831 }; 1832 1833 enum hal_mon_end_reason { 1834 HAL_MON_STATUS_BUFFER_FULL, 1835 HAL_MON_FLUSH_DETECTED, 1836 HAL_MON_END_OF_PPDU, 1837 HAL_MON_PPDU_TRUNCATED, 1838 }; 1839 1840 #define HAL_SW_MONITOR_RING_INFO0_RXDMA_PUSH_REASON GENMASK(1, 0) 1841 #define HAL_SW_MONITOR_RING_INFO0_RXDMA_ERROR_CODE GENMASK(6, 2) 1842 #define HAL_SW_MONITOR_RING_INFO0_MPDU_FRAGMENT_NUMBER GENMASK(10, 7) 1843 #define HAL_SW_MONITOR_RING_INFO0_FRAMELESS_BAR BIT(11) 1844 #define HAL_SW_MONITOR_RING_INFO0_STATUS_BUF_COUNT GENMASK(15, 12) 1845 #define HAL_SW_MONITOR_RING_INFO0_END_OF_PPDU BIT(16) 1846 1847 #define HAL_SW_MONITOR_RING_INFO1_PHY_PPDU_ID GENMASK(15, 0) 1848 #define HAL_SW_MONITOR_RING_INFO1_RING_ID GENMASK(27, 20) 1849 #define HAL_SW_MONITOR_RING_INFO1_LOOPING_COUNT GENMASK(31, 28) 1850 1851 struct hal_sw_monitor_ring { 1852 struct ath12k_buffer_addr buf_addr_info; 1853 struct rx_mpdu_desc rx_mpdu_info; 1854 struct ath12k_buffer_addr status_buff_addr_info; 1855 __le32 info0; /* %HAL_SW_MONITOR_RING_INFO0 */ 1856 __le32 info1; /* %HAL_SW_MONITOR_RING_INFO1 */ 1857 } __packed; 1858 1859 /* hal_sw_monitor_ring 1860 * 1861 * Producer: RXDMA 1862 * Consumer: REO/SW/FW 1863 * buf_addr_info 1864 * Details of the physical address of a buffer or MSDU 1865 * link descriptor. 1866 * 1867 * rx_mpdu_info 1868 * Details related to the MPDU being pushed to SW, valid 1869 * only if end_of_ppdu is set to 0. 1870 * 1871 * status_buff_addr_info 1872 * Details of the physical address of the first status 1873 * buffer used for the PPDU (either the PPDU that included the 1874 * MPDU being pushed to SW if end_of_ppdu = 0, or the PPDU 1875 * whose end is indicated through end_of_ppdu = 1) 1876 * 1877 * rxdma_push_reason 1878 * Indicates why RXDMA pushed the frame to this ring 1879 * 1880 * <enum 0 rxdma_error_detected> RXDMA detected an error an 1881 * pushed this frame to this queue 1882 * 1883 * <enum 1 rxdma_routing_instruction> RXDMA pushed the 1884 * frame to this queue per received routing instructions. No 1885 * error within RXDMA was detected 1886 * 1887 * <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a 1888 * result the MSDU link descriptor might not have the 1889 * last_msdu_in_mpdu_flag set, but instead WBM might just see a 1890 * NULL pointer in the MSDU link descriptor. This is to be 1891 * considered a normal condition for this scenario. 1892 * 1893 * rxdma_error_code 1894 * Field only valid when rxdma_push_reason is set to 1895 * 'rxdma_error_detected.' 1896 * 1897 * <enum 0 rxdma_overflow_err>MPDU frame is not complete 1898 * due to a FIFO overflow error in RXPCU. 1899 * 1900 * <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete 1901 * due to receiving incomplete MPDU from the PHY 1902 * 1903 * <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption 1904 * error or CRYPTO received an encrypted frame, but did not get 1905 * a valid corresponding key id in the peer entry. 1906 * 1907 * <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC 1908 * error 1909 * 1910 * <enum 5 rxdma_unecrypted_err>CRYPTO reported an 1911 * unencrypted frame error when encrypted was expected 1912 * 1913 * <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU 1914 * length error 1915 * 1916 * <enum 7 rxdma_msdu_limit_err>RX OLE reported that max 1917 * number of MSDUs allowed in an MPDU got exceeded 1918 * 1919 * <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing 1920 * error 1921 * 1922 * <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU 1923 * parsing error 1924 * 1925 * <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout 1926 * during SA search 1927 * 1928 * <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout 1929 * during DA search 1930 * 1931 * <enum 12 rxdma_flow_timeout_err>RX OLE reported a 1932 * timeout during flow search 1933 * 1934 * <enum 13 rxdma_flush_request>RXDMA received a flush 1935 * request 1936 * 1937 * <enum 14 rxdma_amsdu_fragment_err>Rx PCU reported A-MSDU 1938 * present as well as a fragmented MPDU. 1939 * 1940 * mpdu_fragment_number 1941 * Field only valid when Reo_level_mpdu_frame_info. 1942 * Rx_mpdu_desc_info_details.Fragment_flag is set and 1943 * end_of_ppdu is set to 0. 1944 * 1945 * The fragment number from the 802.11 header. 1946 * 1947 * Note that the sequence number is embedded in the field: 1948 * Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. 1949 * Mpdu_sequence_number 1950 * 1951 * frameless_bar 1952 * When set, this SW monitor ring struct contains BAR info 1953 * from a multi TID BAR frame. The original multi TID BAR frame 1954 * itself contained all the REO info for the first TID, but all 1955 * the subsequent TID info and their linkage to the REO 1956 * descriptors is passed down as 'frameless' BAR info. 1957 * 1958 * The only fields valid in this descriptor when this bit 1959 * is within the 1960 * 1961 * Reo_level_mpdu_frame_info: 1962 * Within Rx_mpdu_desc_info_details: 1963 * Mpdu_Sequence_number 1964 * BAR_frame 1965 * Peer_meta_data 1966 * All other fields shall be set to 0. 1967 * 1968 * status_buf_count 1969 * A count of status buffers used so far for the PPDU 1970 * (either the PPDU that included the MPDU being pushed to SW 1971 * if end_of_ppdu = 0, or the PPDU whose end is indicated 1972 * through end_of_ppdu = 1) 1973 * 1974 * end_of_ppdu 1975 * Some hw RXDMA can be configured to generate a separate 1976 * 'SW_MONITOR_RING' descriptor at the end of a PPDU (either 1977 * through an 'RX_PPDU_END' TLV or through an 'RX_FLUSH') to 1978 * demarcate PPDUs. 1979 * 1980 * For such a descriptor, this bit is set to 1 and fields 1981 * Reo_level_mpdu_frame_info, mpdu_fragment_number and 1982 * Frameless_bar are all set to 0. 1983 * 1984 * Otherwise this bit is set to 0. 1985 * 1986 * phy_ppdu_id 1987 * A PPDU counter value that PHY increments for every PPDU 1988 * received 1989 * 1990 * The counter value wraps around. Some hw RXDMA can be 1991 * configured to copy this from the RX_PPDU_START TLV for every 1992 * output descriptor. 1993 * 1994 * ring_id 1995 * For debugging. 1996 * This field is filled in by the SRNG module. 1997 * It help to identify the ring that is being looked 1998 * 1999 * looping_count 2000 * For debugging. 2001 * This field is filled in by the SRNG module. 2002 * 2003 * A count value that indicates the number of times the 2004 * producer of entries into this Ring has looped around the 2005 * ring. 2006 * At initialization time, this value is set to 0. On the 2007 * first loop, this value is set to 1. After the max value is 2008 * reached allowed by the number of bits for this field, the 2009 * count value continues with 0 again. 2010 * 2011 * In case SW is the consumer of the ring entries, it can 2012 * use this field to figure out up to where the producer of 2013 * entries has created new entries. This eliminates the need to 2014 * check where the head pointer' of the ring is located once 2015 * the SW starts processing an interrupt indicating that new 2016 * entries have been put into this ring... 2017 */ 2018 2019 enum hal_desc_owner { 2020 HAL_DESC_OWNER_WBM, 2021 HAL_DESC_OWNER_SW, 2022 HAL_DESC_OWNER_TQM, 2023 HAL_DESC_OWNER_RXDMA, 2024 HAL_DESC_OWNER_REO, 2025 HAL_DESC_OWNER_SWITCH, 2026 }; 2027 2028 enum hal_desc_buf_type { 2029 HAL_DESC_BUF_TYPE_TX_MSDU_LINK, 2030 HAL_DESC_BUF_TYPE_TX_MPDU_LINK, 2031 HAL_DESC_BUF_TYPE_TX_MPDU_QUEUE_HEAD, 2032 HAL_DESC_BUF_TYPE_TX_MPDU_QUEUE_EXT, 2033 HAL_DESC_BUF_TYPE_TX_FLOW, 2034 HAL_DESC_BUF_TYPE_TX_BUFFER, 2035 HAL_DESC_BUF_TYPE_RX_MSDU_LINK, 2036 HAL_DESC_BUF_TYPE_RX_MPDU_LINK, 2037 HAL_DESC_BUF_TYPE_RX_REO_QUEUE, 2038 HAL_DESC_BUF_TYPE_RX_REO_QUEUE_EXT, 2039 HAL_DESC_BUF_TYPE_RX_BUFFER, 2040 HAL_DESC_BUF_TYPE_IDLE_LINK, 2041 }; 2042 2043 #define HAL_DESC_REO_OWNED 4 2044 #define HAL_DESC_REO_QUEUE_DESC 8 2045 #define HAL_DESC_REO_QUEUE_EXT_DESC 9 2046 2047 #define HAL_DESC_HDR_INFO0_OWNER GENMASK(3, 0) 2048 #define HAL_DESC_HDR_INFO0_BUF_TYPE GENMASK(7, 4) 2049 #define HAL_DESC_HDR_INFO0_DBG_RESERVED GENMASK(31, 8) 2050 2051 struct hal_desc_header { 2052 __le32 info0; 2053 } __packed; 2054 2055 struct hal_rx_mpdu_link_ptr { 2056 struct ath12k_buffer_addr addr_info; 2057 } __packed; 2058 2059 struct hal_rx_msdu_details { 2060 struct ath12k_buffer_addr buf_addr_info; 2061 struct rx_msdu_desc rx_msdu_info; 2062 struct rx_msdu_ext_desc rx_msdu_ext_info; 2063 } __packed; 2064 2065 #define HAL_RX_MSDU_LNK_INFO0_RX_QUEUE_NUMBER GENMASK(15, 0) 2066 #define HAL_RX_MSDU_LNK_INFO0_FIRST_MSDU_LNK BIT(16) 2067 2068 struct hal_rx_msdu_link { 2069 struct hal_desc_header desc_hdr; 2070 struct ath12k_buffer_addr buf_addr_info; 2071 __le32 info0; 2072 __le32 pn[4]; 2073 struct hal_rx_msdu_details msdu_link[6]; 2074 } __packed; 2075 2076 struct hal_rx_reo_queue_ext { 2077 struct hal_desc_header desc_hdr; 2078 __le32 rsvd; 2079 struct hal_rx_mpdu_link_ptr mpdu_link[15]; 2080 } __packed; 2081 2082 /* hal_rx_reo_queue_ext 2083 * Consumer: REO 2084 * Producer: REO 2085 * 2086 * descriptor_header 2087 * Details about which module owns this struct. 2088 * 2089 * mpdu_link 2090 * Pointer to the next MPDU_link descriptor in the MPDU queue. 2091 */ 2092 2093 enum hal_rx_reo_queue_pn_size { 2094 HAL_RX_REO_QUEUE_PN_SIZE_24, 2095 HAL_RX_REO_QUEUE_PN_SIZE_48, 2096 HAL_RX_REO_QUEUE_PN_SIZE_128, 2097 }; 2098 2099 #define HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER GENMASK(15, 0) 2100 2101 #define HAL_RX_REO_QUEUE_INFO0_VLD BIT(0) 2102 #define HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER GENMASK(2, 1) 2103 #define HAL_RX_REO_QUEUE_INFO0_DIS_DUP_DETECTION BIT(3) 2104 #define HAL_RX_REO_QUEUE_INFO0_SOFT_REORDER_EN BIT(4) 2105 #define HAL_RX_REO_QUEUE_INFO0_AC GENMASK(6, 5) 2106 #define HAL_RX_REO_QUEUE_INFO0_BAR BIT(7) 2107 #define HAL_RX_REO_QUEUE_INFO0_RETRY BIT(8) 2108 #define HAL_RX_REO_QUEUE_INFO0_CHECK_2K_MODE BIT(9) 2109 #define HAL_RX_REO_QUEUE_INFO0_OOR_MODE BIT(10) 2110 #define HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE GENMASK(20, 11) 2111 #define HAL_RX_REO_QUEUE_INFO0_PN_CHECK BIT(21) 2112 #define HAL_RX_REO_QUEUE_INFO0_EVEN_PN BIT(22) 2113 #define HAL_RX_REO_QUEUE_INFO0_UNEVEN_PN BIT(23) 2114 #define HAL_RX_REO_QUEUE_INFO0_PN_HANDLE_ENABLE BIT(24) 2115 #define HAL_RX_REO_QUEUE_INFO0_PN_SIZE GENMASK(26, 25) 2116 #define HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG BIT(27) 2117 2118 #define HAL_RX_REO_QUEUE_INFO1_SVLD BIT(0) 2119 #define HAL_RX_REO_QUEUE_INFO1_SSN GENMASK(12, 1) 2120 #define HAL_RX_REO_QUEUE_INFO1_CURRENT_IDX GENMASK(22, 13) 2121 #define HAL_RX_REO_QUEUE_INFO1_SEQ_2K_ERR BIT(23) 2122 #define HAL_RX_REO_QUEUE_INFO1_PN_ERR BIT(24) 2123 #define HAL_RX_REO_QUEUE_INFO1_PN_VALID BIT(31) 2124 2125 #define HAL_RX_REO_QUEUE_INFO2_MPDU_COUNT GENMASK(6, 0) 2126 #define HAL_RX_REO_QUEUE_INFO2_MSDU_COUNT (31, 7) 2127 2128 #define HAL_RX_REO_QUEUE_INFO3_TIMEOUT_COUNT GENMASK(9, 4) 2129 #define HAL_RX_REO_QUEUE_INFO3_FWD_DUE_TO_BAR_CNT GENMASK(15, 10) 2130 #define HAL_RX_REO_QUEUE_INFO3_DUPLICATE_COUNT GENMASK(31, 16) 2131 2132 #define HAL_RX_REO_QUEUE_INFO4_FRAME_IN_ORD_COUNT GENMASK(23, 0) 2133 #define HAL_RX_REO_QUEUE_INFO4_BAR_RECVD_COUNT GENMASK(31, 24) 2134 2135 #define HAL_RX_REO_QUEUE_INFO5_LATE_RX_MPDU_COUNT GENMASK(11, 0) 2136 #define HAL_RX_REO_QUEUE_INFO5_WINDOW_JUMP_2K GENMASK(15, 12) 2137 #define HAL_RX_REO_QUEUE_INFO5_HOLE_COUNT GENMASK(31, 16) 2138 2139 struct hal_rx_reo_queue { 2140 struct hal_desc_header desc_hdr; 2141 __le32 rx_queue_num; 2142 __le32 info0; 2143 __le32 info1; 2144 __le32 pn[4]; 2145 __le32 last_rx_enqueue_timestamp; 2146 __le32 last_rx_dequeue_timestamp; 2147 __le32 next_aging_queue[2]; 2148 __le32 prev_aging_queue[2]; 2149 __le32 rx_bitmap[9]; 2150 __le32 info2; 2151 __le32 info3; 2152 __le32 info4; 2153 __le32 processed_mpdus; 2154 __le32 processed_msdus; 2155 __le32 processed_total_bytes; 2156 __le32 info5; 2157 __le32 rsvd[2]; 2158 struct hal_rx_reo_queue_ext ext_desc[]; 2159 } __packed; 2160 2161 /* hal_rx_reo_queue 2162 * 2163 * descriptor_header 2164 * Details about which module owns this struct. Note that sub field 2165 * Buffer_type shall be set to receive_reo_queue_descriptor. 2166 * 2167 * receive_queue_number 2168 * Indicates the MPDU queue ID to which this MPDU link descriptor belongs. 2169 * 2170 * vld 2171 * Valid bit indicating a session is established and the queue descriptor 2172 * is valid. 2173 * associated_link_descriptor_counter 2174 * Indicates which of the 3 link descriptor counters shall be incremented 2175 * or decremented when link descriptors are added or removed from this 2176 * flow queue. 2177 * disable_duplicate_detection 2178 * When set, do not perform any duplicate detection. 2179 * soft_reorder_enable 2180 * When set, REO has been instructed to not perform the actual re-ordering 2181 * of frames for this queue, but just to insert the reorder opcodes. 2182 * ac 2183 * Indicates the access category of the queue descriptor. 2184 * bar 2185 * Indicates if BAR has been received. 2186 * retry 2187 * Retry bit is checked if this bit is set. 2188 * chk_2k_mode 2189 * Indicates what type of operation is expected from Reo when the received 2190 * frame SN falls within the 2K window. 2191 * oor_mode 2192 * Indicates what type of operation is expected when the received frame 2193 * falls within the OOR window. 2194 * ba_window_size 2195 * Indicates the negotiated (window size + 1). Max of 256 bits. 2196 * 2197 * A value 255 means 256 bitmap, 63 means 64 bitmap, 0 (means non-BA 2198 * session, with window size of 0). The 3 values here are the main values 2199 * validated, but other values should work as well. 2200 * 2201 * A BA window size of 0 (=> one frame entry bitmat), means that there is 2202 * no additional rx_reo_queue_ext desc. following rx_reo_queue in memory. 2203 * A BA window size of 1 - 105, means that there is 1 rx_reo_queue_ext. 2204 * A BA window size of 106 - 210, means that there are 2 rx_reo_queue_ext. 2205 * A BA window size of 211 - 256, means that there are 3 rx_reo_queue_ext. 2206 * pn_check_needed, pn_shall_be_even, pn_shall_be_uneven, pn_handling_enable, 2207 * pn_size 2208 * REO shall perform the PN increment check, even number check, uneven 2209 * number check, PN error check and size of the PN field check. 2210 * ignore_ampdu_flag 2211 * REO shall ignore the ampdu_flag on entrance descriptor for this queue. 2212 * 2213 * svld 2214 * Sequence number in next field is valid one. 2215 * ssn 2216 * Starting Sequence number of the session. 2217 * current_index 2218 * Points to last forwarded packet 2219 * seq_2k_error_detected_flag 2220 * REO has detected a 2k error jump in the sequence number and from that 2221 * moment forward, all new frames are forwarded directly to FW, without 2222 * duplicate detect, reordering, etc. 2223 * pn_error_detected_flag 2224 * REO has detected a PN error. 2225 */ 2226 2227 #define HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 2228 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RX_QUEUE_NUM BIT(8) 2229 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_VLD BIT(9) 2230 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_ASSOC_LNK_DESC_CNT BIT(10) 2231 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_DIS_DUP_DETECTION BIT(11) 2232 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SOFT_REORDER_EN BIT(12) 2233 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC BIT(13) 2234 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BAR BIT(14) 2235 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RETRY BIT(15) 2236 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_CHECK_2K_MODE BIT(16) 2237 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_OOR_MODE BIT(17) 2238 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BA_WINDOW_SIZE BIT(18) 2239 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_CHECK BIT(19) 2240 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_EVEN_PN BIT(20) 2241 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_UNEVEN_PN BIT(21) 2242 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_HANDLE_ENABLE BIT(22) 2243 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_SIZE BIT(23) 2244 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_IGNORE_AMPDU_FLG BIT(24) 2245 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SVLD BIT(25) 2246 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SSN BIT(26) 2247 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SEQ_2K_ERR BIT(27) 2248 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_ERR BIT(28) 2249 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_VALID BIT(29) 2250 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN BIT(30) 2251 2252 #define HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER GENMASK(15, 0) 2253 #define HAL_REO_UPD_RX_QUEUE_INFO1_VLD BIT(16) 2254 #define HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER GENMASK(18, 17) 2255 #define HAL_REO_UPD_RX_QUEUE_INFO1_DIS_DUP_DETECTION BIT(19) 2256 #define HAL_REO_UPD_RX_QUEUE_INFO1_SOFT_REORDER_EN BIT(20) 2257 #define HAL_REO_UPD_RX_QUEUE_INFO1_AC GENMASK(22, 21) 2258 #define HAL_REO_UPD_RX_QUEUE_INFO1_BAR BIT(23) 2259 #define HAL_REO_UPD_RX_QUEUE_INFO1_RETRY BIT(24) 2260 #define HAL_REO_UPD_RX_QUEUE_INFO1_CHECK_2K_MODE BIT(25) 2261 #define HAL_REO_UPD_RX_QUEUE_INFO1_OOR_MODE BIT(26) 2262 #define HAL_REO_UPD_RX_QUEUE_INFO1_PN_CHECK BIT(27) 2263 #define HAL_REO_UPD_RX_QUEUE_INFO1_EVEN_PN BIT(28) 2264 #define HAL_REO_UPD_RX_QUEUE_INFO1_UNEVEN_PN BIT(29) 2265 #define HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE BIT(30) 2266 #define HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG BIT(31) 2267 2268 #define HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE GENMASK(9, 0) 2269 #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE GENMASK(11, 10) 2270 #define HAL_REO_UPD_RX_QUEUE_INFO2_SVLD BIT(12) 2271 #define HAL_REO_UPD_RX_QUEUE_INFO2_SSN GENMASK(24, 13) 2272 #define HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR BIT(25) 2273 #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR BIT(26) 2274 #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_VALID BIT(27) 2275 2276 struct hal_reo_update_rx_queue { 2277 struct hal_reo_cmd_hdr cmd; 2278 __le32 queue_addr_lo; 2279 __le32 info0; 2280 __le32 info1; 2281 __le32 info2; 2282 __le32 pn[4]; 2283 } __packed; 2284 2285 struct hal_rx_reo_queue_1k { 2286 struct hal_desc_header desc_hdr; 2287 __le32 rx_bitmap_1023_288[23]; 2288 __le32 reserved[8]; 2289 } __packed; 2290 2291 #define HAL_REO_UNBLOCK_CACHE_INFO0_UNBLK_CACHE BIT(0) 2292 #define HAL_REO_UNBLOCK_CACHE_INFO0_RESOURCE_IDX GENMASK(2, 1) 2293 2294 struct hal_reo_unblock_cache { 2295 struct hal_reo_cmd_hdr cmd; 2296 __le32 info0; 2297 __le32 rsvd[7]; 2298 } __packed; 2299 2300 enum hal_reo_exec_status { 2301 HAL_REO_EXEC_STATUS_SUCCESS, 2302 HAL_REO_EXEC_STATUS_BLOCKED, 2303 HAL_REO_EXEC_STATUS_FAILED, 2304 HAL_REO_EXEC_STATUS_RESOURCE_BLOCKED, 2305 }; 2306 2307 #define HAL_REO_STATUS_HDR_INFO0_STATUS_NUM GENMASK(15, 0) 2308 #define HAL_REO_STATUS_HDR_INFO0_EXEC_TIME GENMASK(25, 16) 2309 #define HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS GENMASK(27, 26) 2310 2311 struct hal_reo_status_hdr { 2312 __le32 info0; 2313 __le32 timestamp; 2314 } __packed; 2315 2316 /* hal_reo_status_hdr 2317 * Producer: REO 2318 * Consumer: SW 2319 * 2320 * status_num 2321 * The value in this field is equal to value of the reo command 2322 * number. This field helps to correlate the statuses with the REO 2323 * commands. 2324 * 2325 * execution_time (in us) 2326 * The amount of time REO took to execute the command. Note that 2327 * this time does not include the duration of the command waiting 2328 * in the command ring, before the execution started. 2329 * 2330 * execution_status 2331 * Execution status of the command. Values are defined in 2332 * enum %HAL_REO_EXEC_STATUS_. 2333 */ 2334 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN GENMASK(11, 0) 2335 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX GENMASK(21, 12) 2336 2337 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT GENMASK(6, 0) 2338 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT GENMASK(31, 7) 2339 2340 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_WINDOW_JMP2K GENMASK(3, 0) 2341 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT GENMASK(9, 4) 2342 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT GENMASK(15, 10) 2343 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT GENMASK(31, 16) 2344 2345 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT GENMASK(23, 0) 2346 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT GENMASK(31, 24) 2347 2348 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU GENMASK(11, 0) 2349 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT GENMASK(27, 12) 2350 2351 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT GENMASK(31, 28) 2352 2353 struct hal_reo_get_queue_stats_status { 2354 struct hal_reo_status_hdr hdr; 2355 __le32 info0; 2356 __le32 pn[4]; 2357 __le32 last_rx_enqueue_timestamp; 2358 __le32 last_rx_dequeue_timestamp; 2359 __le32 rx_bitmap[9]; 2360 __le32 info1; 2361 __le32 info2; 2362 __le32 info3; 2363 __le32 num_mpdu_frames; 2364 __le32 num_msdu_frames; 2365 __le32 total_bytes; 2366 __le32 info4; 2367 __le32 info5; 2368 } __packed; 2369 2370 /* hal_reo_get_queue_stats_status 2371 * Producer: REO 2372 * Consumer: SW 2373 * 2374 * status_hdr 2375 * Details that can link this status with the original command. It 2376 * also contains info on how long REO took to execute this command. 2377 * 2378 * ssn 2379 * Starting Sequence number of the session, this changes whenever 2380 * window moves (can be filled by SW then maintained by REO). 2381 * 2382 * current_index 2383 * Points to last forwarded packet. 2384 * 2385 * pn 2386 * Bits of the PN number. 2387 * 2388 * last_rx_enqueue_timestamp 2389 * last_rx_dequeue_timestamp 2390 * Timestamp of arrival of the last MPDU for this queue and 2391 * Timestamp of forwarding an MPDU accordingly. 2392 * 2393 * rx_bitmap 2394 * When a bit is set, the corresponding frame is currently held 2395 * in the re-order queue. The bitmap is Fully managed by HW. 2396 * 2397 * current_mpdu_count 2398 * current_msdu_count 2399 * The number of MPDUs and MSDUs in the queue. 2400 * 2401 * timeout_count 2402 * The number of times REO started forwarding frames even though 2403 * there is a hole in the bitmap. Forwarding reason is timeout. 2404 * 2405 * forward_due_to_bar_count 2406 * The number of times REO started forwarding frames even though 2407 * there is a hole in the bitmap. Fwd reason is reception of BAR. 2408 * 2409 * duplicate_count 2410 * The number of duplicate frames that have been detected. 2411 * 2412 * frames_in_order_count 2413 * The number of frames that have been received in order (without 2414 * a hole that prevented them from being forwarded immediately). 2415 * 2416 * bar_received_count 2417 * The number of times a BAR frame is received. 2418 * 2419 * mpdu_frames_processed_count 2420 * msdu_frames_processed_count 2421 * The total number of MPDU/MSDU frames that have been processed. 2422 * 2423 * total_bytes 2424 * An approximation of the number of bytes received for this queue. 2425 * 2426 * late_receive_mpdu_count 2427 * The number of MPDUs received after the window had already moved 2428 * on. The 'late' sequence window is defined as 2429 * (Window SSN - 256) - (Window SSN - 1). 2430 * 2431 * window_jump_2k 2432 * The number of times the window moved more than 2K 2433 * 2434 * hole_count 2435 * The number of times a hole was created in the receive bitmap. 2436 * 2437 * looping_count 2438 * A count value that indicates the number of times the producer of 2439 * entries into this Ring has looped around the ring. 2440 */ 2441 2442 struct hal_reo_get_queue_stats_status_qcc2072 { 2443 __le32 tlv32_padding; 2444 struct hal_reo_get_queue_stats_status status; 2445 } __packed; 2446 2447 #define HAL_REO_STATUS_LOOP_CNT GENMASK(31, 28) 2448 2449 #define HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED BIT(0) 2450 #define HAL_REO_FLUSH_QUEUE_INFO0_RSVD GENMASK(31, 1) 2451 #define HAL_REO_FLUSH_QUEUE_INFO1_RSVD GENMASK(27, 0) 2452 2453 struct hal_reo_flush_queue_status { 2454 struct hal_reo_status_hdr hdr; 2455 __le32 info0; 2456 __le32 rsvd0[21]; 2457 __le32 info1; 2458 } __packed; 2459 2460 /* hal_reo_flush_queue_status 2461 * Producer: REO 2462 * Consumer: SW 2463 * 2464 * status_hdr 2465 * Details that can link this status with the original command. It 2466 * also contains info on how long REO took to execute this command. 2467 * 2468 * error_detected 2469 * Status of blocking resource 2470 * 2471 * 0 - No error has been detected while executing this command 2472 * 1 - Error detected. The resource to be used for blocking was 2473 * already in use. 2474 * 2475 * looping_count 2476 * A count value that indicates the number of times the producer of 2477 * entries into this Ring has looped around the ring. 2478 */ 2479 2480 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR BIT(0) 2481 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE GENMASK(2, 1) 2482 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_STATUS_HIT BIT(8) 2483 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE GENMASK(11, 9) 2484 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID GENMASK(15, 12) 2485 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR GENMASK(17, 16) 2486 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT GENMASK(25, 18) 2487 2488 struct hal_reo_flush_cache_status { 2489 struct hal_reo_status_hdr hdr; 2490 __le32 info0; 2491 __le32 rsvd0[21]; 2492 __le32 info1; 2493 } __packed; 2494 2495 /* hal_reo_flush_cache_status 2496 * Producer: REO 2497 * Consumer: SW 2498 * 2499 * status_hdr 2500 * Details that can link this status with the original command. It 2501 * also contains info on how long REO took to execute this command. 2502 * 2503 * error_detected 2504 * Status for blocking resource handling 2505 * 2506 * 0 - No error has been detected while executing this command 2507 * 1 - An error in the blocking resource management was detected 2508 * 2509 * block_error_details 2510 * only valid when error_detected is set 2511 * 2512 * 0 - No blocking related errors found 2513 * 1 - Blocking resource is already in use 2514 * 2 - Resource requested to be unblocked, was not blocked 2515 * 2516 * cache_controller_flush_status_hit 2517 * The status that the cache controller returned on executing the 2518 * flush command. 2519 * 2520 * 0 - miss; 1 - hit 2521 * 2522 * cache_controller_flush_status_desc_type 2523 * Flush descriptor type 2524 * 2525 * cache_controller_flush_status_client_id 2526 * Module who made the flush request 2527 * 2528 * In REO, this is always 0 2529 * 2530 * cache_controller_flush_status_error 2531 * Error condition 2532 * 2533 * 0 - No error found 2534 * 1 - HW interface is still busy 2535 * 2 - Line currently locked. Used for one line flush command 2536 * 3 - At least one line is still locked. 2537 * Used for cache flush command. 2538 * 2539 * cache_controller_flush_count 2540 * The number of lines that were actually flushed out 2541 * 2542 * looping_count 2543 * A count value that indicates the number of times the producer of 2544 * entries into this Ring has looped around the ring. 2545 */ 2546 2547 #define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR BIT(0) 2548 #define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_TYPE BIT(1) 2549 2550 struct hal_reo_unblock_cache_status { 2551 struct hal_reo_status_hdr hdr; 2552 __le32 info0; 2553 __le32 rsvd0[21]; 2554 __le32 info1; 2555 } __packed; 2556 2557 /* hal_reo_unblock_cache_status 2558 * Producer: REO 2559 * Consumer: SW 2560 * 2561 * status_hdr 2562 * Details that can link this status with the original command. It 2563 * also contains info on how long REO took to execute this command. 2564 * 2565 * error_detected 2566 * 0 - No error has been detected while executing this command 2567 * 1 - The blocking resource was not in use, and therefore it could 2568 * not be unblocked. 2569 * 2570 * unblock_type 2571 * Reference to the type of unblock command 2572 * 0 - Unblock a blocking resource 2573 * 1 - The entire cache usage is unblock 2574 * 2575 * looping_count 2576 * A count value that indicates the number of times the producer of 2577 * entries into this Ring has looped around the ring. 2578 */ 2579 2580 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR BIT(0) 2581 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_LIST_EMPTY BIT(1) 2582 2583 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT GENMASK(15, 0) 2584 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT GENMASK(31, 16) 2585 2586 struct hal_reo_flush_timeout_list_status { 2587 struct hal_reo_status_hdr hdr; 2588 __le32 info0; 2589 __le32 info1; 2590 __le32 rsvd0[20]; 2591 __le32 info2; 2592 } __packed; 2593 2594 /* hal_reo_flush_timeout_list_status 2595 * Producer: REO 2596 * Consumer: SW 2597 * 2598 * status_hdr 2599 * Details that can link this status with the original command. It 2600 * also contains info on how long REO took to execute this command. 2601 * 2602 * error_detected 2603 * 0 - No error has been detected while executing this command 2604 * 1 - Command not properly executed and returned with error 2605 * 2606 * timeout_list_empty 2607 * When set, REO has depleted the timeout list and all entries are 2608 * gone. 2609 * 2610 * release_desc_count 2611 * Producer: SW; Consumer: REO 2612 * The number of link descriptor released 2613 * 2614 * forward_buf_count 2615 * Producer: SW; Consumer: REO 2616 * The number of buffers forwarded to the REO destination rings 2617 * 2618 * looping_count 2619 * A count value that indicates the number of times the producer of 2620 * entries into this Ring has looped around the ring. 2621 */ 2622 2623 #define HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX GENMASK(1, 0) 2624 #define HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0 GENMASK(23, 0) 2625 #define HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1 GENMASK(23, 0) 2626 #define HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2 GENMASK(23, 0) 2627 #define HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM GENMASK(25, 0) 2628 2629 struct hal_reo_desc_thresh_reached_status { 2630 struct hal_reo_status_hdr hdr; 2631 __le32 info0; 2632 __le32 info1; 2633 __le32 info2; 2634 __le32 info3; 2635 __le32 info4; 2636 __le32 rsvd0[17]; 2637 __le32 info5; 2638 } __packed; 2639 2640 /* hal_reo_desc_thresh_reached_status 2641 * Producer: REO 2642 * Consumer: SW 2643 * 2644 * status_hdr 2645 * Details that can link this status with the original command. It 2646 * also contains info on how long REO took to execute this command. 2647 * 2648 * threshold_index 2649 * The index of the threshold register whose value got reached 2650 * 2651 * link_descriptor_counter0 2652 * link_descriptor_counter1 2653 * link_descriptor_counter2 2654 * link_descriptor_counter_sum 2655 * Value of the respective counters at generation of this message 2656 * 2657 * looping_count 2658 * A count value that indicates the number of times the producer of 2659 * entries into this Ring has looped around the ring. 2660 */ 2661 2662 #define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_DATA_LENGTH GENMASK(13, 0) 2663 #define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_L4_CSUM_STATUS BIT(14) 2664 #define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_L3_CSUM_STATUS BIT(15) 2665 #define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_PID GENMASK(27, 24) 2666 #define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_QDISC BIT(28) 2667 #define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_MULTICAST BIT(29) 2668 #define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_MORE BIT(30) 2669 #define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_VALID_TOGGLE BIT(31) 2670 2671 struct hal_tcl_entrance_from_ppe_ring { 2672 __le32 buffer_addr; 2673 __le32 info0; 2674 } __packed; 2675 2676 #define HAL_MON_DEST_COOKIE_BUF_ID GENMASK(17, 0) 2677 2678 #define HAL_MON_DEST_INFO0_END_OFFSET GENMASK(11, 0) 2679 #define HAL_MON_DEST_INFO0_END_REASON GENMASK(17, 16) 2680 #define HAL_MON_DEST_INFO0_INITIATOR BIT(18) 2681 #define HAL_MON_DEST_INFO0_EMPTY_DESC BIT(19) 2682 #define HAL_MON_DEST_INFO0_RING_ID GENMASK(27, 20) 2683 #define HAL_MON_DEST_INFO0_LOOPING_COUNT GENMASK(31, 28) 2684 2685 struct hal_mon_dest_desc { 2686 __le32 cookie; 2687 __le32 reserved; 2688 __le32 ppdu_id; 2689 __le32 info0; 2690 }; 2691 2692 /* hal_mon_dest_ring 2693 * Producer : TxMon/RxMon 2694 * Consumer : SW 2695 * cookie 2696 * bit 0 -17 buf_id to track the skb's vaddr. 2697 * ppdu_id 2698 * Phy ppdu_id 2699 * end_offset 2700 * The offset into status buffer where DMA ended, ie., offset to the last 2701 * TLV + last TLV size. 2702 * flush_detected 2703 * Indicates whether 'tx_flush' or 'rx_flush' occurred. 2704 * end_of_ppdu 2705 * Indicates end of ppdu. 2706 * pmac_id 2707 * Indicates PMAC that received from frame. 2708 * empty_descriptor 2709 * This descriptor is written on flush or end of ppdu or end of status 2710 * buffer. 2711 * ring_id 2712 * updated by SRNG. 2713 * looping_count 2714 * updated by SRNG. 2715 */ 2716 2717 #define HAL_TX_MSDU_METADATA_INFO0_ENCRYPT_FLAG BIT(8) 2718 #define HAL_TX_MSDU_METADATA_INFO0_ENCRYPT_TYPE GENMASK(16, 15) 2719 #define HAL_TX_MSDU_METADATA_INFO0_HOST_TX_DESC_POOL BIT(31) 2720 2721 struct hal_tx_msdu_metadata { 2722 __le32 info0; 2723 __le32 rsvd0[6]; 2724 } __packed; 2725 2726 /* hal_tx_msdu_metadata 2727 * valid_encrypt_type 2728 * if set, encrypt type is valid 2729 * encrypt_type 2730 * 0 = NO_ENCRYPT, 2731 * 1 = ENCRYPT, 2732 * 2 ~ 3 - Reserved 2733 * host_tx_desc_pool 2734 * If set, Firmware allocates tx_descriptors 2735 * in WAL_BUFFERID_TX_HOST_DATA_EXP,instead 2736 * of WAL_BUFFERID_TX_TCL_DATA_EXP. 2737 * Use cases: 2738 * Any time firmware uses TQM-BYPASS for Data 2739 * TID, firmware expect host to set this bit. 2740 */ 2741 2742 #endif /* ATH12K_HAL_DESC_H */ 2743