1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #ifndef ATH12K_HAL_WIFI7_H 8 #define ATH12K_HAL_WIFI7_H 9 10 #include "../core.h" 11 #include "../hal.h" 12 #include "hal_desc.h" 13 #include "hal_tx.h" 14 #include "hal_rx.h" 15 #include "hal_rx_desc.h" 16 17 /* calculate the register address from bar0 of shadow register x */ 18 #define HAL_SHADOW_BASE_ADDR 0x000008fc 19 #define HAL_SHADOW_NUM_REGS 40 20 #define HAL_HP_OFFSET_IN_REG_START 1 21 #define HAL_OFFSET_FROM_HP_TO_TP 4 22 23 #define HAL_SHADOW_REG(x) (HAL_SHADOW_BASE_ADDR + (4 * (x))) 24 #define HAL_REO_QDESC_MAX_PEERID 8191 25 26 /* WCSS Relative address */ 27 #define HAL_SEQ_WCSS_CMEM_OFFSET 0x00100000 28 #define HAL_SEQ_WCSS_UMAC_OFFSET 0x00a00000 29 #define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000 30 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000 31 #define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(hal) \ 32 ((hal)->regs->umac_ce0_src_reg_base) 33 #define HAL_SEQ_WCSS_UMAC_CE0_DST_REG(hal) \ 34 ((hal)->regs->umac_ce0_dest_reg_base) 35 #define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(hal) \ 36 ((hal)->regs->umac_ce1_src_reg_base) 37 #define HAL_SEQ_WCSS_UMAC_CE1_DST_REG(hal) \ 38 ((hal)->regs->umac_ce1_dest_reg_base) 39 #define HAL_SEQ_WCSS_UMAC_WBM_REG 0x00a34000 40 41 #define HAL_CE_WFSS_CE_REG_BASE 0x01b80000 42 43 #define HAL_TCL_SW_CONFIG_BANK_ADDR 0x00a4408c 44 45 /* SW2TCL(x) R0 ring configuration address */ 46 #define HAL_TCL1_RING_CMN_CTRL_REG 0x00000020 47 #define HAL_TCL1_RING_DSCP_TID_MAP 0x00000240 48 49 #define HAL_TCL1_RING_BASE_LSB(hal) \ 50 ((hal)->regs->tcl1_ring_base_lsb) 51 #define HAL_TCL1_RING_BASE_MSB(hal) \ 52 ((hal)->regs->tcl1_ring_base_msb) 53 #define HAL_TCL1_RING_ID(hal) ((hal)->regs->tcl1_ring_id) 54 #define HAL_TCL1_RING_MISC(hal) \ 55 ((hal)->regs->tcl1_ring_misc) 56 #define HAL_TCL1_RING_TP_ADDR_LSB(hal) \ 57 ((hal)->regs->tcl1_ring_tp_addr_lsb) 58 #define HAL_TCL1_RING_TP_ADDR_MSB(hal) \ 59 ((hal)->regs->tcl1_ring_tp_addr_msb) 60 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(hal) \ 61 ((hal)->regs->tcl1_ring_consumer_int_setup_ix0) 62 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(hal) \ 63 ((hal)->regs->tcl1_ring_consumer_int_setup_ix1) 64 #define HAL_TCL1_RING_MSI1_BASE_LSB(hal) \ 65 ((hal)->regs->tcl1_ring_msi1_base_lsb) 66 #define HAL_TCL1_RING_MSI1_BASE_MSB(hal) \ 67 ((hal)->regs->tcl1_ring_msi1_base_msb) 68 #define HAL_TCL1_RING_MSI1_DATA(hal) \ 69 ((hal)->regs->tcl1_ring_msi1_data) 70 #define HAL_TCL2_RING_BASE_LSB(hal) \ 71 ((hal)->regs->tcl2_ring_base_lsb) 72 #define HAL_TCL_RING_BASE_LSB(hal) \ 73 ((hal)->regs->tcl_ring_base_lsb) 74 75 #define HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET(hal) ({ typeof(hal) _hal = (hal); \ 76 (HAL_TCL1_RING_MSI1_BASE_LSB(_hal) - HAL_TCL1_RING_BASE_LSB(_hal)); }) 77 #define HAL_TCL1_RING_MSI1_BASE_MSB_OFFSET(hal) ({ typeof(hal) _hal = (hal); \ 78 (HAL_TCL1_RING_MSI1_BASE_MSB(_hal) - HAL_TCL1_RING_BASE_LSB(_hal)); }) 79 #define HAL_TCL1_RING_MSI1_DATA_OFFSET(hal) ({ typeof(hal) _hal = (hal); \ 80 (HAL_TCL1_RING_MSI1_DATA(_hal) - HAL_TCL1_RING_BASE_LSB(_hal)); }) 81 #define HAL_TCL1_RING_BASE_MSB_OFFSET(hal) ({ typeof(hal) _hal = (hal); \ 82 (HAL_TCL1_RING_BASE_MSB(_hal) - HAL_TCL1_RING_BASE_LSB(_hal)); }) 83 #define HAL_TCL1_RING_ID_OFFSET(hal) ({ typeof(hal) _hal = (hal); \ 84 (HAL_TCL1_RING_ID(_hal) - HAL_TCL1_RING_BASE_LSB(_hal)); }) 85 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET(hal) ({ typeof(hal) _hal = (hal); \ 86 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(_hal) - HAL_TCL1_RING_BASE_LSB(_hal)); }) 87 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET(hal) ({ typeof(hal) _hal = (hal); \ 88 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(_hal) - HAL_TCL1_RING_BASE_LSB(_hal)); }) 89 #define HAL_TCL1_RING_TP_ADDR_LSB_OFFSET(hal) ({ typeof(hal) _hal = (hal); \ 90 (HAL_TCL1_RING_TP_ADDR_LSB(_hal) - HAL_TCL1_RING_BASE_LSB(_hal)); }) 91 #define HAL_TCL1_RING_TP_ADDR_MSB_OFFSET(hal) ({ typeof(hal) _hal = (hal); \ 92 (HAL_TCL1_RING_TP_ADDR_MSB(_hal) - HAL_TCL1_RING_BASE_LSB(_hal)); }) 93 #define HAL_TCL1_RING_MISC_OFFSET(hal) ({ typeof(hal) _hal = (hal); \ 94 (HAL_TCL1_RING_MISC(_hal) - HAL_TCL1_RING_BASE_LSB(_hal)); }) 95 96 /* SW2TCL(x) R2 ring pointers (head/tail) address */ 97 #define HAL_TCL1_RING_HP 0x00002000 98 #define HAL_TCL1_RING_TP 0x00002004 99 #define HAL_TCL2_RING_HP 0x00002008 100 #define HAL_TCL_RING_HP 0x00002028 101 102 #define HAL_TCL1_RING_TP_OFFSET \ 103 (HAL_TCL1_RING_TP - HAL_TCL1_RING_HP) 104 105 /* TCL STATUS ring address */ 106 #define HAL_TCL_STATUS_RING_BASE_LSB(hal) \ 107 ((hal)->regs->tcl_status_ring_base_lsb) 108 #define HAL_TCL_STATUS_RING_HP 0x00002048 109 110 /* PPE2TCL1 Ring address */ 111 #define HAL_TCL_PPE2TCL1_RING_BASE_LSB 0x00000c48 112 #define HAL_TCL_PPE2TCL1_RING_HP 0x00002038 113 114 /* WBM PPE Release Ring address */ 115 #define HAL_WBM_PPE_RELEASE_RING_BASE_LSB(hal) \ 116 ((hal)->regs->ppe_rel_ring_base) 117 #define HAL_WBM_PPE_RELEASE_RING_HP 0x00003020 118 119 /* REO2SW(x) R0 ring configuration address */ 120 #define HAL_REO1_GEN_ENABLE 0x00000000 121 #define HAL_REO1_MISC_CTRL_ADDR(hal) \ 122 ((hal)->regs->reo1_misc_ctrl_addr) 123 #define HAL_REO1_DEST_RING_CTRL_IX_0 0x00000004 124 #define HAL_REO1_DEST_RING_CTRL_IX_1 0x00000008 125 #define HAL_REO1_DEST_RING_CTRL_IX_2 0x0000000c 126 #define HAL_REO1_DEST_RING_CTRL_IX_3 0x00000010 127 #define HAL_REO1_QDESC_ADDR(hal) ((hal)->regs->reo1_qdesc_addr) 128 #define HAL_REO1_QDESC_MAX_PEERID(hal) ((hal)->regs->reo1_qdesc_max_peerid) 129 #define HAL_REO1_SW_COOKIE_CFG0(hal) ((hal)->regs->reo1_sw_cookie_cfg0) 130 #define HAL_REO1_SW_COOKIE_CFG1(hal) ((hal)->regs->reo1_sw_cookie_cfg1) 131 #define HAL_REO1_QDESC_LUT_BASE0(hal) ((hal)->regs->reo1_qdesc_lut_base0) 132 #define HAL_REO1_QDESC_LUT_BASE1(hal) ((hal)->regs->reo1_qdesc_lut_base1) 133 #define HAL_REO1_RING_BASE_LSB(hal) ((hal)->regs->reo1_ring_base_lsb) 134 #define HAL_REO1_RING_BASE_MSB(hal) ((hal)->regs->reo1_ring_base_msb) 135 #define HAL_REO1_RING_ID(hal) ((hal)->regs->reo1_ring_id) 136 #define HAL_REO1_RING_MISC(hal) ((hal)->regs->reo1_ring_misc) 137 #define HAL_REO1_RING_HP_ADDR_LSB(hal) ((hal)->regs->reo1_ring_hp_addr_lsb) 138 #define HAL_REO1_RING_HP_ADDR_MSB(hal) ((hal)->regs->reo1_ring_hp_addr_msb) 139 #define HAL_REO1_RING_PRODUCER_INT_SETUP(hal) \ 140 ((hal)->regs->reo1_ring_producer_int_setup) 141 #define HAL_REO1_RING_MSI1_BASE_LSB(hal) \ 142 ((hal)->regs->reo1_ring_msi1_base_lsb) 143 #define HAL_REO1_RING_MSI1_BASE_MSB(hal) \ 144 ((hal)->regs->reo1_ring_msi1_base_msb) 145 #define HAL_REO1_RING_MSI1_DATA(hal) ((hal)->regs->reo1_ring_msi1_data) 146 #define HAL_REO2_RING_BASE_LSB(hal) ((hal)->regs->reo2_ring_base) 147 #define HAL_REO1_AGING_THRESH_IX_0(hal) ((hal)->regs->reo1_aging_thres_ix0) 148 #define HAL_REO1_AGING_THRESH_IX_1(hal) ((hal)->regs->reo1_aging_thres_ix1) 149 #define HAL_REO1_AGING_THRESH_IX_2(hal) ((hal)->regs->reo1_aging_thres_ix2) 150 #define HAL_REO1_AGING_THRESH_IX_3(hal) ((hal)->regs->reo1_aging_thres_ix3) 151 152 /* REO2SW(x) R2 ring pointers (head/tail) address */ 153 #define HAL_REO1_RING_HP 0x00003048 154 #define HAL_REO1_RING_TP 0x0000304c 155 #define HAL_REO2_RING_HP 0x00003050 156 157 #define HAL_REO1_RING_TP_OFFSET (HAL_REO1_RING_TP - HAL_REO1_RING_HP) 158 159 /* REO2SW0 ring configuration address */ 160 #define HAL_REO_SW0_RING_BASE_LSB(hal) \ 161 ((hal)->regs->reo2_sw0_ring_base) 162 163 /* REO2SW0 R2 ring pointer (head/tail) address */ 164 #define HAL_REO_SW0_RING_HP 0x00003088 165 166 /* REO CMD R0 address */ 167 #define HAL_REO_CMD_RING_BASE_LSB(hal) \ 168 ((hal)->regs->reo_cmd_ring_base) 169 170 /* REO CMD R2 address */ 171 #define HAL_REO_CMD_HP 0x00003020 172 173 /* SW2REO R0 address */ 174 #define HAL_SW2REO_RING_BASE_LSB(hal) \ 175 ((hal)->regs->sw2reo_ring_base) 176 #define HAL_SW2REO1_RING_BASE_LSB(hal) \ 177 ((hal)->regs->sw2reo1_ring_base) 178 179 /* SW2REO R2 address */ 180 #define HAL_SW2REO_RING_HP 0x00003028 181 #define HAL_SW2REO1_RING_HP 0x00003030 182 183 /* CE ring R0 address */ 184 #define HAL_CE_SRC_RING_BASE_LSB 0x00000000 185 #define HAL_CE_DST_RING_BASE_LSB 0x00000000 186 #define HAL_CE_DST_STATUS_RING_BASE_LSB 0x00000058 187 #define HAL_CE_DST_RING_CTRL 0x000000b0 188 189 /* CE ring R2 address */ 190 #define HAL_CE_DST_RING_HP 0x00000400 191 #define HAL_CE_DST_STATUS_RING_HP 0x00000408 192 193 /* REO status address */ 194 #define HAL_REO_STATUS_RING_BASE_LSB(hal) \ 195 ((hal)->regs->reo_status_ring_base) 196 #define HAL_REO_STATUS_HP 0x000030a8 197 198 /* WBM Idle R0 address */ 199 #define HAL_WBM_IDLE_LINK_RING_BASE_LSB(hal) \ 200 ((hal)->regs->wbm_idle_ring_base_lsb) 201 #define HAL_WBM_IDLE_LINK_RING_MISC_ADDR(hal) \ 202 ((hal)->regs->wbm_idle_ring_misc_addr) 203 #define HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR(hal) \ 204 ((hal)->regs->wbm_r0_idle_list_cntl_addr) 205 #define HAL_WBM_R0_IDLE_LIST_SIZE_ADDR(hal) \ 206 ((hal)->regs->wbm_r0_idle_list_size_addr) 207 #define HAL_WBM_SCATTERED_RING_BASE_LSB(hal) \ 208 ((hal)->regs->wbm_scattered_ring_base_lsb) 209 #define HAL_WBM_SCATTERED_RING_BASE_MSB(hal) \ 210 ((hal)->regs->wbm_scattered_ring_base_msb) 211 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0(hal) \ 212 ((hal)->regs->wbm_scattered_desc_head_info_ix0) 213 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1(hal) \ 214 ((hal)->regs->wbm_scattered_desc_head_info_ix1) 215 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0(hal) \ 216 ((hal)->regs->wbm_scattered_desc_tail_info_ix0) 217 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1(hal) \ 218 ((hal)->regs->wbm_scattered_desc_tail_info_ix1) 219 #define HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR(hal) \ 220 ((hal)->regs->wbm_scattered_desc_ptr_hp_addr) 221 222 /* WBM Idle R2 address */ 223 #define HAL_WBM_IDLE_LINK_RING_HP 0x000030b8 224 225 /* SW2WBM R0 release address */ 226 #define HAL_WBM_SW_RELEASE_RING_BASE_LSB(hal) \ 227 ((hal)->regs->wbm_sw_release_ring_base_lsb) 228 #define HAL_WBM_SW1_RELEASE_RING_BASE_LSB(hal) \ 229 ((hal)->regs->wbm_sw1_release_ring_base_lsb) 230 231 /* SW2WBM R2 release address */ 232 #define HAL_WBM_SW_RELEASE_RING_HP 0x00003010 233 #define HAL_WBM_SW1_RELEASE_RING_HP 0x00003018 234 235 /* WBM2SW R0 release address */ 236 #define HAL_WBM0_RELEASE_RING_BASE_LSB(hal) \ 237 ((hal)->regs->wbm0_release_ring_base_lsb) 238 239 #define HAL_WBM1_RELEASE_RING_BASE_LSB(hal) \ 240 ((hal)->regs->wbm1_release_ring_base_lsb) 241 242 /* WBM2SW R2 release address */ 243 #define HAL_WBM0_RELEASE_RING_HP 0x000030c8 244 #define HAL_WBM1_RELEASE_RING_HP 0x000030d0 245 246 /* WBM cookie config address and mask */ 247 #define HAL_WBM_SW_COOKIE_CFG0 0x00000040 248 #define HAL_WBM_SW_COOKIE_CFG1 0x00000044 249 #define HAL_WBM_SW_COOKIE_CFG2 0x00000090 250 #define HAL_WBM_SW_COOKIE_CONVERT_CFG 0x00000094 251 252 #define HAL_WBM_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB GENMASK(7, 0) 253 #define HAL_WBM_SW_COOKIE_CFG_COOKIE_PPT_MSB GENMASK(12, 8) 254 #define HAL_WBM_SW_COOKIE_CFG_COOKIE_SPT_MSB GENMASK(17, 13) 255 #define HAL_WBM_SW_COOKIE_CFG_ALIGN BIT(18) 256 #define HAL_WBM_SW_COOKIE_CFG_RELEASE_PATH_EN BIT(0) 257 #define HAL_WBM_SW_COOKIE_CFG_ERR_PATH_EN BIT(1) 258 #define HAL_WBM_SW_COOKIE_CFG_CONV_IND_EN BIT(3) 259 260 #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN BIT(1) 261 #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW1_EN BIT(2) 262 #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN BIT(3) 263 #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN BIT(4) 264 #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN BIT(5) 265 #define HAL_WBM_SW_COOKIE_CONV_CFG_GLOBAL_EN BIT(8) 266 267 /* TCL ring field mask and offset */ 268 #define HAL_TCL1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8) 269 #define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0) 270 #define HAL_TCL1_RING_ID_ENTRY_SIZE GENMASK(7, 0) 271 #define HAL_TCL1_RING_MISC_MSI_RING_ID_DISABLE BIT(0) 272 #define HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE BIT(1) 273 #define HAL_TCL1_RING_MISC_MSI_SWAP BIT(3) 274 #define HAL_TCL1_RING_MISC_HOST_FW_SWAP BIT(4) 275 #define HAL_TCL1_RING_MISC_DATA_TLV_SWAP BIT(5) 276 #define HAL_TCL1_RING_MISC_SRNG_ENABLE BIT(6) 277 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_INTR_TMR_THOLD GENMASK(31, 16) 278 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD GENMASK(14, 0) 279 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD GENMASK(15, 0) 280 #define HAL_TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8) 281 #define HAL_TCL1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0) 282 #define HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN BIT(23) 283 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP GENMASK(31, 0) 284 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP0 GENMASK(2, 0) 285 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP1 GENMASK(5, 3) 286 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP2 GENMASK(8, 6) 287 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP3 GENMASK(11, 9) 288 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP4 GENMASK(14, 12) 289 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP5 GENMASK(17, 15) 290 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP6 GENMASK(20, 18) 291 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP7 GENMASK(23, 21) 292 293 /* REO ring field mask and offset */ 294 #define HAL_REO1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8) 295 #define HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0) 296 #define HAL_REO1_RING_ID_RING_ID GENMASK(15, 8) 297 #define HAL_REO1_RING_ID_ENTRY_SIZE GENMASK(7, 0) 298 #define HAL_REO1_RING_MISC_MSI_SWAP BIT(3) 299 #define HAL_REO1_RING_MISC_HOST_FW_SWAP BIT(4) 300 #define HAL_REO1_RING_MISC_DATA_TLV_SWAP BIT(5) 301 #define HAL_REO1_RING_MISC_SRNG_ENABLE BIT(6) 302 #define HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD GENMASK(31, 16) 303 #define HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD GENMASK(14, 0) 304 #define HAL_REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8) 305 #define HAL_REO1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0) 306 #define HAL_REO1_MISC_CTL_FRAG_DST_RING GENMASK(20, 17) 307 #define HAL_REO1_MISC_CTL_BAR_DST_RING GENMASK(24, 21) 308 #define HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE BIT(2) 309 #define HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE BIT(3) 310 #define HAL_REO1_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB GENMASK(7, 0) 311 #define HAL_REO1_SW_COOKIE_CFG_COOKIE_PPT_MSB GENMASK(12, 8) 312 #define HAL_REO1_SW_COOKIE_CFG_COOKIE_SPT_MSB GENMASK(17, 13) 313 #define HAL_REO1_SW_COOKIE_CFG_ALIGN BIT(18) 314 #define HAL_REO1_SW_COOKIE_CFG_ENABLE BIT(19) 315 #define HAL_REO1_SW_COOKIE_CFG_GLOBAL_ENABLE BIT(20) 316 #define HAL_REO_QDESC_ADDR_READ_LUT_ENABLE BIT(7) 317 #define HAL_REO_QDESC_ADDR_READ_CLEAR_QDESC_ARRAY BIT(6) 318 319 /* CE ring bit field mask and shift */ 320 #define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN GENMASK(15, 0) 321 322 #define HAL_ADDR_LSB_REG_MASK 0xffffffff 323 324 #define HAL_ADDR_MSB_REG_SHIFT 32 325 326 /* WBM ring bit field mask and shift */ 327 #define HAL_WBM_LINK_DESC_IDLE_LIST_MODE BIT(1) 328 #define HAL_WBM_SCATTER_BUFFER_SIZE GENMASK(10, 2) 329 #define HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST GENMASK(31, 16) 330 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32 GENMASK(7, 0) 331 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG GENMASK(31, 8) 332 333 #define HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1 GENMASK(20, 8) 334 #define HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1 GENMASK(20, 8) 335 336 #define HAL_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE BIT(6) 337 #define HAL_WBM_IDLE_LINK_RING_MISC_RIND_ID_DISABLE BIT(0) 338 339 #define BASE_ADDR_MATCH_TAG_VAL 0x5 340 341 #define HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE 0x000fffff 342 #define HAL_REO_REO2SW0_RING_BASE_MSB_RING_SIZE 0x000fffff 343 #define HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE 0x0000ffff 344 #define HAL_REO_CMD_RING_BASE_MSB_RING_SIZE 0x0000ffff 345 #define HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 346 #define HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE 0x000fffff 347 #define HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE 0x000fffff 348 #define HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 349 #define HAL_CE_SRC_RING_BASE_MSB_RING_SIZE 0x0000ffff 350 #define HAL_CE_DST_RING_BASE_MSB_RING_SIZE 0x0000ffff 351 #define HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 352 #define HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE 0x000fffff 353 #define HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE 0x0000ffff 354 #define HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE 0x000fffff 355 #define HAL_RXDMA_RING_MAX_SIZE 0x0000ffff 356 #define HAL_RXDMA_RING_MAX_SIZE_BE 0x000fffff 357 #define HAL_WBM2PPE_RELEASE_RING_BASE_MSB_RING_SIZE 0x000fffff 358 359 #define HAL_WBM2SW_REL_ERR_RING_NUM 3 360 /* Add any other errors here and return them in 361 * ath12k_hal_rx_desc_get_err(). 362 */ 363 364 #define HAL_IPQ5332_CE_WFSS_REG_BASE 0x740000 365 #define HAL_IPQ5332_CE_SIZE 0x100000 366 367 #define HAL_RX_MAX_BA_WINDOW 256 368 369 #define HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_USEC (100 * 1000) 370 #define HAL_DEFAULT_VO_REO_TIMEOUT_USEC (40 * 1000) 371 372 #define HAL_SRNG_DESC_LOOP_CNT 0xf0000000 373 374 #define HAL_REO_CMD_FLG_NEED_STATUS BIT(0) 375 #define HAL_REO_CMD_FLG_STATS_CLEAR BIT(1) 376 #define HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER BIT(2) 377 #define HAL_REO_CMD_FLG_FLUSH_RELEASE_BLOCKING BIT(3) 378 #define HAL_REO_CMD_FLG_FLUSH_NO_INVAL BIT(4) 379 #define HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS BIT(5) 380 #define HAL_REO_CMD_FLG_FLUSH_ALL BIT(6) 381 #define HAL_REO_CMD_FLG_UNBLK_RESOURCE BIT(7) 382 #define HAL_REO_CMD_FLG_UNBLK_CACHE BIT(8) 383 #define HAL_REO_CMD_FLG_FLUSH_QUEUE_1K_DESC BIT(9) 384 385 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO0_UPD_* fields */ 386 #define HAL_REO_CMD_UPD0_RX_QUEUE_NUM BIT(8) 387 #define HAL_REO_CMD_UPD0_VLD BIT(9) 388 #define HAL_REO_CMD_UPD0_ALDC BIT(10) 389 #define HAL_REO_CMD_UPD0_DIS_DUP_DETECTION BIT(11) 390 #define HAL_REO_CMD_UPD0_SOFT_REORDER_EN BIT(12) 391 #define HAL_REO_CMD_UPD0_AC BIT(13) 392 #define HAL_REO_CMD_UPD0_BAR BIT(14) 393 #define HAL_REO_CMD_UPD0_RETRY BIT(15) 394 #define HAL_REO_CMD_UPD0_CHECK_2K_MODE BIT(16) 395 #define HAL_REO_CMD_UPD0_OOR_MODE BIT(17) 396 #define HAL_REO_CMD_UPD0_BA_WINDOW_SIZE BIT(18) 397 #define HAL_REO_CMD_UPD0_PN_CHECK BIT(19) 398 #define HAL_REO_CMD_UPD0_EVEN_PN BIT(20) 399 #define HAL_REO_CMD_UPD0_UNEVEN_PN BIT(21) 400 #define HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE BIT(22) 401 #define HAL_REO_CMD_UPD0_PN_SIZE BIT(23) 402 #define HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG BIT(24) 403 #define HAL_REO_CMD_UPD0_SVLD BIT(25) 404 #define HAL_REO_CMD_UPD0_SSN BIT(26) 405 #define HAL_REO_CMD_UPD0_SEQ_2K_ERR BIT(27) 406 #define HAL_REO_CMD_UPD0_PN_ERR BIT(28) 407 #define HAL_REO_CMD_UPD0_PN_VALID BIT(29) 408 #define HAL_REO_CMD_UPD0_PN BIT(30) 409 410 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO1_* fields */ 411 #define HAL_REO_CMD_UPD1_VLD BIT(16) 412 #define HAL_REO_CMD_UPD1_ALDC GENMASK(18, 17) 413 #define HAL_REO_CMD_UPD1_DIS_DUP_DETECTION BIT(19) 414 #define HAL_REO_CMD_UPD1_SOFT_REORDER_EN BIT(20) 415 #define HAL_REO_CMD_UPD1_AC GENMASK(22, 21) 416 #define HAL_REO_CMD_UPD1_BAR BIT(23) 417 #define HAL_REO_CMD_UPD1_RETRY BIT(24) 418 #define HAL_REO_CMD_UPD1_CHECK_2K_MODE BIT(25) 419 #define HAL_REO_CMD_UPD1_OOR_MODE BIT(26) 420 #define HAL_REO_CMD_UPD1_PN_CHECK BIT(27) 421 #define HAL_REO_CMD_UPD1_EVEN_PN BIT(28) 422 #define HAL_REO_CMD_UPD1_UNEVEN_PN BIT(29) 423 #define HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE BIT(30) 424 #define HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG BIT(31) 425 426 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO2_* fields */ 427 #define HAL_REO_CMD_UPD2_SVLD BIT(10) 428 #define HAL_REO_CMD_UPD2_SSN GENMASK(22, 11) 429 #define HAL_REO_CMD_UPD2_SEQ_2K_ERR BIT(23) 430 #define HAL_REO_CMD_UPD2_PN_ERR BIT(24) 431 432 struct hal_reo_status_queue_stats { 433 u16 ssn; 434 u16 curr_idx; 435 u32 pn[4]; 436 u32 last_rx_queue_ts; 437 u32 last_rx_dequeue_ts; 438 u32 rx_bitmap[8]; /* Bitmap from 0-255 */ 439 u32 curr_mpdu_cnt; 440 u32 curr_msdu_cnt; 441 u16 fwd_due_to_bar_cnt; 442 u16 dup_cnt; 443 u32 frames_in_order_cnt; 444 u32 num_mpdu_processed_cnt; 445 u32 num_msdu_processed_cnt; 446 u32 total_num_processed_byte_cnt; 447 u32 late_rx_mpdu_cnt; 448 u32 reorder_hole_cnt; 449 u8 timeout_cnt; 450 u8 bar_rx_cnt; 451 u8 num_window_2k_jump_cnt; 452 }; 453 454 struct hal_reo_status_flush_queue { 455 bool err_detected; 456 }; 457 458 enum hal_reo_status_flush_cache_err_code { 459 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_SUCCESS, 460 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_IN_USE, 461 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_NOT_FOUND, 462 }; 463 464 struct hal_reo_status_flush_cache { 465 bool err_detected; 466 enum hal_reo_status_flush_cache_err_code err_code; 467 bool cache_controller_flush_status_hit; 468 u8 cache_controller_flush_status_desc_type; 469 u8 cache_controller_flush_status_client_id; 470 u8 cache_controller_flush_status_err; 471 u8 cache_controller_flush_status_cnt; 472 }; 473 474 enum hal_reo_status_unblock_cache_type { 475 HAL_REO_STATUS_UNBLOCK_BLOCKING_RESOURCE, 476 HAL_REO_STATUS_UNBLOCK_ENTIRE_CACHE_USAGE, 477 }; 478 479 struct hal_reo_status_unblock_cache { 480 bool err_detected; 481 enum hal_reo_status_unblock_cache_type unblock_type; 482 }; 483 484 struct hal_reo_status_flush_timeout_list { 485 bool err_detected; 486 bool list_empty; 487 u16 release_desc_cnt; 488 u16 fwd_buf_cnt; 489 }; 490 491 enum hal_reo_threshold_idx { 492 HAL_REO_THRESHOLD_IDX_DESC_COUNTER0, 493 HAL_REO_THRESHOLD_IDX_DESC_COUNTER1, 494 HAL_REO_THRESHOLD_IDX_DESC_COUNTER2, 495 HAL_REO_THRESHOLD_IDX_DESC_COUNTER_SUM, 496 }; 497 498 struct hal_reo_status_desc_thresh_reached { 499 enum hal_reo_threshold_idx threshold_idx; 500 u32 link_desc_counter0; 501 u32 link_desc_counter1; 502 u32 link_desc_counter2; 503 u32 link_desc_counter_sum; 504 }; 505 506 struct hal_reo_status { 507 struct hal_reo_status_header uniform_hdr; 508 u8 loop_cnt; 509 union { 510 struct hal_reo_status_queue_stats queue_stats; 511 struct hal_reo_status_flush_queue flush_queue; 512 struct hal_reo_status_flush_cache flush_cache; 513 struct hal_reo_status_unblock_cache unblock_cache; 514 struct hal_reo_status_flush_timeout_list timeout_list; 515 struct hal_reo_status_desc_thresh_reached desc_thresh_reached; 516 } u; 517 }; 518 519 int ath12k_wifi7_hal_init(struct ath12k_base *ab); 520 void ath12k_wifi7_hal_ce_dst_setup(struct ath12k_base *ab, 521 struct hal_srng *srng, int ring_num); 522 void ath12k_wifi7_hal_srng_dst_hw_init(struct ath12k_base *ab, 523 struct hal_srng *srng); 524 void ath12k_wifi7_hal_srng_src_hw_init(struct ath12k_base *ab, 525 struct hal_srng *srng); 526 void ath12k_wifi7_hal_set_umac_srng_ptr_addr(struct ath12k_base *ab, 527 struct hal_srng *srng); 528 int ath12k_wifi7_hal_srng_update_shadow_config(struct ath12k_base *ab, 529 enum hal_ring_type ring_type, 530 int ring_num); 531 int ath12k_wifi7_hal_srng_get_ring_id(struct ath12k_hal *hal, 532 enum hal_ring_type type, 533 int ring_num, int mac_id); 534 u32 ath12k_wifi7_hal_ce_get_desc_size(enum hal_ce_desc type); 535 void ath12k_wifi7_hal_cc_config(struct ath12k_base *ab); 536 enum hal_rx_buf_return_buf_manager 537 ath12k_wifi7_hal_get_idle_link_rbm(struct ath12k_hal *hal, u8 device_id); 538 void ath12k_wifi7_hal_ce_src_set_desc(struct hal_ce_srng_src_desc *desc, 539 dma_addr_t paddr, 540 u32 len, u32 id, u8 byte_swap_data); 541 void ath12k_wifi7_hal_ce_dst_set_desc(struct hal_ce_srng_dest_desc *desc, 542 dma_addr_t paddr); 543 void 544 ath12k_wifi7_hal_set_link_desc_addr(struct hal_wbm_link_desc *desc, 545 u32 cookie, dma_addr_t paddr, 546 enum hal_rx_buf_return_buf_manager rbm); 547 u32 548 ath12k_wifi7_hal_ce_dst_status_get_length(struct hal_ce_srng_dst_status_desc *desc); 549 void 550 ath12k_wifi7_hal_setup_link_idle_list(struct ath12k_base *ab, 551 struct hal_wbm_idle_scatter_list *sbuf, 552 u32 nsbufs, u32 tot_link_desc, 553 u32 end_offset); 554 void ath12k_wifi7_hal_reoq_lut_addr_read_enable(struct ath12k_base *ab); 555 void ath12k_wifi7_hal_reoq_lut_set_max_peerid(struct ath12k_base *ab); 556 void ath12k_wifi7_hal_write_reoq_lut_addr(struct ath12k_base *ab, 557 dma_addr_t paddr); 558 void ath12k_wifi7_hal_write_ml_reoq_lut_addr(struct ath12k_base *ab, 559 dma_addr_t paddr); 560 u32 ath12k_wifi7_hal_reo_qdesc_size(u32 ba_window_size, u8 tid); 561 #endif 562