1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 #include "hw.h" 7 #include "hal_desc.h" 8 #include "../hal.h" 9 #include "hal.h" 10 #include "hal_tx.h" 11 #include "../debug.h" 12 #include "../hif.h" 13 #include "hal_qcn9274.h" 14 #include "hal_wcn7850.h" 15 #include "hal_qcc2072.h" 16 17 static const struct ath12k_hw_version_map ath12k_wifi7_hw_ver_map[] = { 18 [ATH12K_HW_QCN9274_HW10] = { 19 .hal_ops = &hal_qcn9274_ops, 20 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9274_compact), 21 .tcl_to_wbm_rbm_map = ath12k_hal_tcl_to_wbm_rbm_map_qcn9274, 22 .hal_params = &ath12k_hw_hal_params_qcn9274, 23 .hw_regs = &qcn9274_v1_regs, 24 }, 25 [ATH12K_HW_QCN9274_HW20] = { 26 .hal_ops = &hal_qcn9274_ops, 27 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9274_compact), 28 .tcl_to_wbm_rbm_map = ath12k_hal_tcl_to_wbm_rbm_map_qcn9274, 29 .hal_params = &ath12k_hw_hal_params_qcn9274, 30 .hw_regs = &qcn9274_v2_regs, 31 }, 32 [ATH12K_HW_WCN7850_HW20] = { 33 .hal_ops = &hal_wcn7850_ops, 34 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn7850), 35 .tcl_to_wbm_rbm_map = ath12k_hal_tcl_to_wbm_rbm_map_wcn7850, 36 .hal_params = &ath12k_hw_hal_params_wcn7850, 37 .hw_regs = &wcn7850_regs, 38 }, 39 [ATH12K_HW_IPQ5332_HW10] = { 40 .hal_ops = &hal_qcn9274_ops, 41 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9274_compact), 42 .tcl_to_wbm_rbm_map = ath12k_hal_tcl_to_wbm_rbm_map_qcn9274, 43 .hal_params = &ath12k_hw_hal_params_ipq5332, 44 .hw_regs = &ipq5332_regs, 45 }, 46 [ATH12K_HW_QCC2072_HW10] = { 47 .hal_ops = &hal_qcc2072_ops, 48 .hal_desc_sz = sizeof(struct hal_rx_desc_qcc2072), 49 .tcl_to_wbm_rbm_map = ath12k_hal_tcl_to_wbm_rbm_map_wcn7850, 50 .hal_params = &ath12k_hw_hal_params_wcn7850, 51 .hw_regs = &qcc2072_regs, 52 }, 53 }; 54 55 int ath12k_wifi7_hal_init(struct ath12k_base *ab) 56 { 57 struct ath12k_hal *hal = &ab->hal; 58 59 memset(hal, 0, sizeof(*hal)); 60 61 hal->ops = ath12k_wifi7_hw_ver_map[ab->hw_rev].hal_ops; 62 hal->hal_desc_sz = ath12k_wifi7_hw_ver_map[ab->hw_rev].hal_desc_sz; 63 hal->tcl_to_wbm_rbm_map = ath12k_wifi7_hw_ver_map[ab->hw_rev].tcl_to_wbm_rbm_map; 64 hal->regs = ath12k_wifi7_hw_ver_map[ab->hw_rev].hw_regs; 65 hal->hal_params = ath12k_wifi7_hw_ver_map[ab->hw_rev].hal_params; 66 hal->hal_wbm_release_ring_tx_size = sizeof(struct hal_wbm_release_ring_tx); 67 68 return 0; 69 } 70 71 static unsigned int ath12k_wifi7_hal_reo1_ring_id_offset(struct ath12k_hal *hal) 72 { 73 return HAL_REO1_RING_ID(hal) - HAL_REO1_RING_BASE_LSB(hal); 74 } 75 76 static unsigned 77 int ath12k_wifi7_hal_reo1_ring_msi1_base_lsb_offset(struct ath12k_hal *hal) 78 { 79 return HAL_REO1_RING_MSI1_BASE_LSB(hal) - HAL_REO1_RING_BASE_LSB(hal); 80 } 81 82 static unsigned 83 int ath12k_wifi7_hal_reo1_ring_msi1_base_msb_offset(struct ath12k_hal *hal) 84 { 85 return HAL_REO1_RING_MSI1_BASE_MSB(hal) - HAL_REO1_RING_BASE_LSB(hal); 86 } 87 88 static unsigned int ath12k_wifi7_hal_reo1_ring_msi1_data_offset(struct ath12k_hal *hal) 89 { 90 return HAL_REO1_RING_MSI1_DATA(hal) - HAL_REO1_RING_BASE_LSB(hal); 91 } 92 93 static unsigned int ath12k_wifi7_hal_reo1_ring_base_msb_offset(struct ath12k_hal *hal) 94 { 95 return HAL_REO1_RING_BASE_MSB(hal) - HAL_REO1_RING_BASE_LSB(hal); 96 } 97 98 static unsigned 99 int ath12k_wifi7_hal_reo1_ring_producer_int_setup_offset(struct ath12k_hal *hal) 100 { 101 return HAL_REO1_RING_PRODUCER_INT_SETUP(hal) - HAL_REO1_RING_BASE_LSB(hal); 102 } 103 104 static unsigned int ath12k_wifi7_hal_reo1_ring_hp_addr_lsb_offset(struct ath12k_hal *hal) 105 { 106 return HAL_REO1_RING_HP_ADDR_LSB(hal) - HAL_REO1_RING_BASE_LSB(hal); 107 } 108 109 static unsigned int ath12k_wifi7_hal_reo1_ring_hp_addr_msb_offset(struct ath12k_hal *hal) 110 { 111 return HAL_REO1_RING_HP_ADDR_MSB(hal) - HAL_REO1_RING_BASE_LSB(hal); 112 } 113 114 static unsigned int ath12k_wifi7_hal_reo1_ring_misc_offset(struct ath12k_hal *hal) 115 { 116 return HAL_REO1_RING_MISC(hal) - HAL_REO1_RING_BASE_LSB(hal); 117 } 118 119 void ath12k_wifi7_hal_ce_dst_setup(struct ath12k_base *ab, 120 struct hal_srng *srng, int ring_num) 121 { 122 struct hal_srng_config *srng_config = &ab->hal.srng_config[HAL_CE_DST]; 123 u32 addr; 124 u32 val; 125 126 addr = HAL_CE_DST_RING_CTRL + 127 srng_config->reg_start[HAL_SRNG_REG_GRP_R0] + 128 ring_num * srng_config->reg_size[HAL_SRNG_REG_GRP_R0]; 129 130 val = ath12k_hif_read32(ab, addr); 131 val &= ~HAL_CE_DST_R0_DEST_CTRL_MAX_LEN; 132 val |= u32_encode_bits(srng->u.dst_ring.max_buffer_length, 133 HAL_CE_DST_R0_DEST_CTRL_MAX_LEN); 134 ath12k_hif_write32(ab, addr, val); 135 } 136 137 void ath12k_wifi7_hal_srng_dst_hw_init(struct ath12k_base *ab, 138 struct hal_srng *srng) 139 { 140 struct ath12k_hal *hal = &ab->hal; 141 u32 val; 142 u64 hp_addr; 143 u32 reg_base; 144 145 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0]; 146 147 if (srng->flags & HAL_SRNG_FLAGS_MSI_INTR) { 148 ath12k_hif_write32(ab, reg_base + 149 ath12k_wifi7_hal_reo1_ring_msi1_base_lsb_offset(hal), 150 srng->msi_addr); 151 152 val = u32_encode_bits(((u64)srng->msi_addr >> HAL_ADDR_MSB_REG_SHIFT), 153 HAL_REO1_RING_MSI1_BASE_MSB_ADDR) | 154 HAL_REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE; 155 ath12k_hif_write32(ab, reg_base + 156 ath12k_wifi7_hal_reo1_ring_msi1_base_msb_offset(hal), 157 val); 158 159 ath12k_hif_write32(ab, 160 reg_base + 161 ath12k_wifi7_hal_reo1_ring_msi1_data_offset(hal), 162 srng->msi_data); 163 } 164 165 ath12k_hif_write32(ab, reg_base, srng->ring_base_paddr); 166 167 val = u32_encode_bits(((u64)srng->ring_base_paddr >> HAL_ADDR_MSB_REG_SHIFT), 168 HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB) | 169 u32_encode_bits((srng->entry_size * srng->num_entries), 170 HAL_REO1_RING_BASE_MSB_RING_SIZE); 171 ath12k_hif_write32(ab, reg_base + ath12k_wifi7_hal_reo1_ring_base_msb_offset(hal), 172 val); 173 174 val = u32_encode_bits(srng->ring_id, HAL_REO1_RING_ID_RING_ID) | 175 u32_encode_bits(srng->entry_size, HAL_REO1_RING_ID_ENTRY_SIZE); 176 ath12k_hif_write32(ab, reg_base + ath12k_wifi7_hal_reo1_ring_id_offset(hal), val); 177 178 /* interrupt setup */ 179 val = u32_encode_bits((srng->intr_timer_thres_us >> 3), 180 HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD); 181 182 val |= u32_encode_bits((srng->intr_batch_cntr_thres_entries * srng->entry_size), 183 HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD); 184 185 ath12k_hif_write32(ab, 186 reg_base + 187 ath12k_wifi7_hal_reo1_ring_producer_int_setup_offset(hal), 188 val); 189 190 hp_addr = hal->rdp.paddr + 191 ((unsigned long)srng->u.dst_ring.hp_addr - 192 (unsigned long)hal->rdp.vaddr); 193 ath12k_hif_write32(ab, reg_base + 194 ath12k_wifi7_hal_reo1_ring_hp_addr_lsb_offset(hal), 195 hp_addr & HAL_ADDR_LSB_REG_MASK); 196 ath12k_hif_write32(ab, reg_base + 197 ath12k_wifi7_hal_reo1_ring_hp_addr_msb_offset(hal), 198 hp_addr >> HAL_ADDR_MSB_REG_SHIFT); 199 200 /* Initialize head and tail pointers to indicate ring is empty */ 201 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R2]; 202 ath12k_hif_write32(ab, reg_base, 0); 203 ath12k_hif_write32(ab, reg_base + HAL_REO1_RING_TP_OFFSET, 0); 204 *srng->u.dst_ring.hp_addr = 0; 205 206 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0]; 207 val = 0; 208 if (srng->flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP) 209 val |= HAL_REO1_RING_MISC_DATA_TLV_SWAP; 210 if (srng->flags & HAL_SRNG_FLAGS_RING_PTR_SWAP) 211 val |= HAL_REO1_RING_MISC_HOST_FW_SWAP; 212 if (srng->flags & HAL_SRNG_FLAGS_MSI_SWAP) 213 val |= HAL_REO1_RING_MISC_MSI_SWAP; 214 val |= HAL_REO1_RING_MISC_SRNG_ENABLE; 215 216 ath12k_hif_write32(ab, reg_base + ath12k_wifi7_hal_reo1_ring_misc_offset(hal), 217 val); 218 } 219 220 void ath12k_wifi7_hal_srng_src_hw_init(struct ath12k_base *ab, 221 struct hal_srng *srng) 222 { 223 struct ath12k_hal *hal = &ab->hal; 224 u32 val; 225 u64 tp_addr; 226 u32 reg_base; 227 228 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0]; 229 230 if (srng->flags & HAL_SRNG_FLAGS_MSI_INTR) { 231 ath12k_hif_write32(ab, reg_base + 232 HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET(hal), 233 srng->msi_addr); 234 235 val = u32_encode_bits(((u64)srng->msi_addr >> HAL_ADDR_MSB_REG_SHIFT), 236 HAL_TCL1_RING_MSI1_BASE_MSB_ADDR) | 237 HAL_TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE; 238 ath12k_hif_write32(ab, reg_base + 239 HAL_TCL1_RING_MSI1_BASE_MSB_OFFSET(hal), 240 val); 241 242 ath12k_hif_write32(ab, reg_base + 243 HAL_TCL1_RING_MSI1_DATA_OFFSET(hal), 244 srng->msi_data); 245 } 246 247 ath12k_hif_write32(ab, reg_base, srng->ring_base_paddr); 248 249 val = u32_encode_bits(((u64)srng->ring_base_paddr >> HAL_ADDR_MSB_REG_SHIFT), 250 HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB) | 251 u32_encode_bits((srng->entry_size * srng->num_entries), 252 HAL_TCL1_RING_BASE_MSB_RING_SIZE); 253 ath12k_hif_write32(ab, reg_base + HAL_TCL1_RING_BASE_MSB_OFFSET(hal), val); 254 255 val = u32_encode_bits(srng->entry_size, HAL_REO1_RING_ID_ENTRY_SIZE); 256 ath12k_hif_write32(ab, reg_base + HAL_TCL1_RING_ID_OFFSET(hal), val); 257 258 val = u32_encode_bits(srng->intr_timer_thres_us, 259 HAL_TCL1_RING_CONSR_INT_SETUP_IX0_INTR_TMR_THOLD); 260 261 val |= u32_encode_bits((srng->intr_batch_cntr_thres_entries * srng->entry_size), 262 HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD); 263 264 ath12k_hif_write32(ab, 265 reg_base + HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET(hal), 266 val); 267 268 val = 0; 269 if (srng->flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) { 270 val |= u32_encode_bits(srng->u.src_ring.low_threshold, 271 HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD); 272 } 273 ath12k_hif_write32(ab, 274 reg_base + HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET(hal), 275 val); 276 277 if (srng->ring_id != HAL_SRNG_RING_ID_WBM_IDLE_LINK) { 278 tp_addr = hal->rdp.paddr + 279 ((unsigned long)srng->u.src_ring.tp_addr - 280 (unsigned long)hal->rdp.vaddr); 281 ath12k_hif_write32(ab, 282 reg_base + HAL_TCL1_RING_TP_ADDR_LSB_OFFSET(hal), 283 tp_addr & HAL_ADDR_LSB_REG_MASK); 284 ath12k_hif_write32(ab, 285 reg_base + HAL_TCL1_RING_TP_ADDR_MSB_OFFSET(hal), 286 tp_addr >> HAL_ADDR_MSB_REG_SHIFT); 287 } 288 289 /* Initialize head and tail pointers to indicate ring is empty */ 290 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R2]; 291 ath12k_hif_write32(ab, reg_base, 0); 292 ath12k_hif_write32(ab, reg_base + HAL_TCL1_RING_TP_OFFSET, 0); 293 *srng->u.src_ring.tp_addr = 0; 294 295 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0]; 296 val = 0; 297 if (srng->flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP) 298 val |= HAL_TCL1_RING_MISC_DATA_TLV_SWAP; 299 if (srng->flags & HAL_SRNG_FLAGS_RING_PTR_SWAP) 300 val |= HAL_TCL1_RING_MISC_HOST_FW_SWAP; 301 if (srng->flags & HAL_SRNG_FLAGS_MSI_SWAP) 302 val |= HAL_TCL1_RING_MISC_MSI_SWAP; 303 304 /* Loop count is not used for SRC rings */ 305 val |= HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE; 306 307 val |= HAL_TCL1_RING_MISC_SRNG_ENABLE; 308 309 if (srng->ring_id == HAL_SRNG_RING_ID_WBM_IDLE_LINK) 310 val |= HAL_TCL1_RING_MISC_MSI_RING_ID_DISABLE; 311 312 ath12k_hif_write32(ab, reg_base + HAL_TCL1_RING_MISC_OFFSET(hal), val); 313 } 314 315 void ath12k_wifi7_hal_set_umac_srng_ptr_addr(struct ath12k_base *ab, 316 struct hal_srng *srng) 317 { 318 u32 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R2]; 319 320 if (srng->ring_dir == HAL_SRNG_DIR_SRC) { 321 if (!ab->hw_params->supports_shadow_regs) { 322 srng->u.src_ring.hp_addr = 323 (u32 *)((unsigned long)ab->mem + reg_base); 324 } else { 325 ath12k_dbg(ab, ATH12K_DBG_HAL, 326 "hal reg_base 0x%x shadow 0x%lx\n", 327 reg_base, 328 (unsigned long)srng->u.src_ring.hp_addr - 329 (unsigned long)ab->mem); 330 } 331 } else { 332 if (!ab->hw_params->supports_shadow_regs) { 333 srng->u.dst_ring.tp_addr = 334 (u32 *)((unsigned long)ab->mem + reg_base + 335 (HAL_REO1_RING_TP - HAL_REO1_RING_HP)); 336 } else { 337 ath12k_dbg(ab, ATH12K_DBG_HAL, 338 "target_reg 0x%x shadow 0x%lx\n", 339 reg_base + HAL_REO1_RING_TP - HAL_REO1_RING_HP, 340 (unsigned long)srng->u.dst_ring.tp_addr - 341 (unsigned long)ab->mem); 342 } 343 } 344 } 345 346 int ath12k_wifi7_hal_srng_get_ring_id(struct ath12k_hal *hal, 347 enum hal_ring_type type, 348 int ring_num, int mac_id) 349 { 350 struct hal_srng_config *srng_config = &hal->srng_config[type]; 351 int ring_id; 352 353 if (ring_num >= srng_config->max_rings) { 354 ath12k_warn(hal, "invalid ring number :%d\n", ring_num); 355 return -EINVAL; 356 } 357 358 ring_id = srng_config->start_ring_id + ring_num; 359 if (srng_config->mac_type == ATH12K_HAL_SRNG_PMAC) 360 ring_id += mac_id * HAL_SRNG_RINGS_PER_PMAC; 361 362 if (WARN_ON(ring_id >= HAL_SRNG_RING_ID_MAX)) 363 return -EINVAL; 364 365 return ring_id; 366 } 367 368 static 369 void ath12k_wifi7_hal_srng_update_hp_tp_addr(struct ath12k_base *ab, 370 int shadow_cfg_idx, 371 enum hal_ring_type ring_type, 372 int ring_num) 373 { 374 struct hal_srng *srng; 375 struct ath12k_hal *hal = &ab->hal; 376 int ring_id; 377 struct hal_srng_config *srng_config = &hal->srng_config[ring_type]; 378 379 ring_id = ath12k_wifi7_hal_srng_get_ring_id(hal, ring_type, ring_num, 380 0); 381 if (ring_id < 0) 382 return; 383 384 srng = &hal->srng_list[ring_id]; 385 386 if (srng_config->ring_dir == HAL_SRNG_DIR_DST) 387 srng->u.dst_ring.tp_addr = (u32 *)(HAL_SHADOW_REG(shadow_cfg_idx) + 388 (unsigned long)ab->mem); 389 else 390 srng->u.src_ring.hp_addr = (u32 *)(HAL_SHADOW_REG(shadow_cfg_idx) + 391 (unsigned long)ab->mem); 392 } 393 394 u32 ath12k_wifi7_hal_ce_get_desc_size(enum hal_ce_desc type) 395 { 396 switch (type) { 397 case HAL_CE_DESC_SRC: 398 return sizeof(struct hal_ce_srng_src_desc); 399 case HAL_CE_DESC_DST: 400 return sizeof(struct hal_ce_srng_dest_desc); 401 case HAL_CE_DESC_DST_STATUS: 402 return sizeof(struct hal_ce_srng_dst_status_desc); 403 } 404 405 return 0; 406 } 407 408 int ath12k_wifi7_hal_srng_update_shadow_config(struct ath12k_base *ab, 409 enum hal_ring_type ring_type, 410 int ring_num) 411 { 412 struct ath12k_hal *hal = &ab->hal; 413 struct hal_srng_config *srng_config = &hal->srng_config[ring_type]; 414 int shadow_cfg_idx = hal->num_shadow_reg_configured; 415 u32 target_reg; 416 417 if (shadow_cfg_idx >= HAL_SHADOW_NUM_REGS_MAX) 418 return -EINVAL; 419 420 hal->num_shadow_reg_configured++; 421 422 target_reg = srng_config->reg_start[HAL_HP_OFFSET_IN_REG_START]; 423 target_reg += srng_config->reg_size[HAL_HP_OFFSET_IN_REG_START] * 424 ring_num; 425 426 /* For destination ring, shadow the TP */ 427 if (srng_config->ring_dir == HAL_SRNG_DIR_DST) 428 target_reg += HAL_OFFSET_FROM_HP_TO_TP; 429 430 hal->shadow_reg_addr[shadow_cfg_idx] = target_reg; 431 432 /* update hp/tp addr to hal structure*/ 433 ath12k_wifi7_hal_srng_update_hp_tp_addr(ab, shadow_cfg_idx, ring_type, 434 ring_num); 435 436 ath12k_dbg(ab, ATH12K_DBG_HAL, 437 "target_reg %x, shadow reg 0x%x shadow_idx 0x%x, ring_type %d, ring num %d", 438 target_reg, 439 HAL_SHADOW_REG(shadow_cfg_idx), 440 shadow_cfg_idx, 441 ring_type, ring_num); 442 443 return 0; 444 } 445 446 void ath12k_wifi7_hal_ce_src_set_desc(struct hal_ce_srng_src_desc *desc, 447 dma_addr_t paddr, 448 u32 len, u32 id, u8 byte_swap_data) 449 { 450 desc->buffer_addr_low = cpu_to_le32(paddr & HAL_ADDR_LSB_REG_MASK); 451 desc->buffer_addr_info = 452 le32_encode_bits(((u64)paddr >> HAL_ADDR_MSB_REG_SHIFT), 453 HAL_CE_SRC_DESC_ADDR_INFO_ADDR_HI) | 454 le32_encode_bits(byte_swap_data, 455 HAL_CE_SRC_DESC_ADDR_INFO_BYTE_SWAP) | 456 le32_encode_bits(0, HAL_CE_SRC_DESC_ADDR_INFO_GATHER) | 457 le32_encode_bits(len, HAL_CE_SRC_DESC_ADDR_INFO_LEN); 458 desc->meta_info = le32_encode_bits(id, HAL_CE_SRC_DESC_META_INFO_DATA); 459 } 460 461 void ath12k_wifi7_hal_ce_dst_set_desc(struct hal_ce_srng_dest_desc *desc, 462 dma_addr_t paddr) 463 { 464 desc->buffer_addr_low = cpu_to_le32(paddr & HAL_ADDR_LSB_REG_MASK); 465 desc->buffer_addr_info = 466 le32_encode_bits(((u64)paddr >> HAL_ADDR_MSB_REG_SHIFT), 467 HAL_CE_DEST_DESC_ADDR_INFO_ADDR_HI); 468 } 469 470 void ath12k_wifi7_hal_set_link_desc_addr(struct hal_wbm_link_desc *desc, 471 u32 cookie, dma_addr_t paddr, 472 enum hal_rx_buf_return_buf_manager rbm) 473 { 474 desc->buf_addr_info.info0 = le32_encode_bits((paddr & HAL_ADDR_LSB_REG_MASK), 475 BUFFER_ADDR_INFO0_ADDR); 476 desc->buf_addr_info.info1 = 477 le32_encode_bits(((u64)paddr >> HAL_ADDR_MSB_REG_SHIFT), 478 BUFFER_ADDR_INFO1_ADDR) | 479 le32_encode_bits(rbm, BUFFER_ADDR_INFO1_RET_BUF_MGR) | 480 le32_encode_bits(cookie, BUFFER_ADDR_INFO1_SW_COOKIE); 481 } 482 483 u32 ath12k_wifi7_hal_ce_dst_status_get_length(struct hal_ce_srng_dst_status_desc *desc) 484 { 485 u32 len; 486 487 len = le32_get_bits(READ_ONCE(desc->flags), HAL_CE_DST_STATUS_DESC_FLAGS_LEN); 488 desc->flags &= ~cpu_to_le32(HAL_CE_DST_STATUS_DESC_FLAGS_LEN); 489 490 return len; 491 } 492 493 void 494 ath12k_wifi7_hal_setup_link_idle_list(struct ath12k_base *ab, 495 struct hal_wbm_idle_scatter_list *sbuf, 496 u32 nsbufs, u32 tot_link_desc, 497 u32 end_offset) 498 { 499 struct ath12k_hal *hal = &ab->hal; 500 struct ath12k_buffer_addr *link_addr; 501 int i; 502 u32 reg_scatter_buf_sz = HAL_WBM_IDLE_SCATTER_BUF_SIZE / 64; 503 u32 val; 504 505 link_addr = (void *)sbuf[0].vaddr + HAL_WBM_IDLE_SCATTER_BUF_SIZE; 506 507 for (i = 1; i < nsbufs; i++) { 508 link_addr->info0 = cpu_to_le32(sbuf[i].paddr & HAL_ADDR_LSB_REG_MASK); 509 510 link_addr->info1 = 511 le32_encode_bits((u64)sbuf[i].paddr >> HAL_ADDR_MSB_REG_SHIFT, 512 HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32) | 513 le32_encode_bits(BASE_ADDR_MATCH_TAG_VAL, 514 HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG); 515 516 link_addr = (void *)sbuf[i].vaddr + 517 HAL_WBM_IDLE_SCATTER_BUF_SIZE; 518 } 519 520 val = u32_encode_bits(reg_scatter_buf_sz, HAL_WBM_SCATTER_BUFFER_SIZE) | 521 u32_encode_bits(0x1, HAL_WBM_LINK_DESC_IDLE_LIST_MODE); 522 523 ath12k_hif_write32(ab, 524 HAL_SEQ_WCSS_UMAC_WBM_REG + 525 HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR(hal), 526 val); 527 528 val = u32_encode_bits(reg_scatter_buf_sz * nsbufs, 529 HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST); 530 ath12k_hif_write32(ab, 531 HAL_SEQ_WCSS_UMAC_WBM_REG + 532 HAL_WBM_R0_IDLE_LIST_SIZE_ADDR(hal), 533 val); 534 535 val = u32_encode_bits(sbuf[0].paddr & HAL_ADDR_LSB_REG_MASK, 536 BUFFER_ADDR_INFO0_ADDR); 537 ath12k_hif_write32(ab, 538 HAL_SEQ_WCSS_UMAC_WBM_REG + 539 HAL_WBM_SCATTERED_RING_BASE_LSB(hal), 540 val); 541 542 val = u32_encode_bits(BASE_ADDR_MATCH_TAG_VAL, 543 HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG) | 544 u32_encode_bits((u64)sbuf[0].paddr >> HAL_ADDR_MSB_REG_SHIFT, 545 HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32); 546 ath12k_hif_write32(ab, 547 HAL_SEQ_WCSS_UMAC_WBM_REG + 548 HAL_WBM_SCATTERED_RING_BASE_MSB(hal), 549 val); 550 551 /* Setup head and tail pointers for the idle list */ 552 val = u32_encode_bits(sbuf[nsbufs - 1].paddr, BUFFER_ADDR_INFO0_ADDR); 553 ath12k_hif_write32(ab, 554 HAL_SEQ_WCSS_UMAC_WBM_REG + 555 HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0(hal), 556 val); 557 558 val = u32_encode_bits(((u64)sbuf[nsbufs - 1].paddr >> HAL_ADDR_MSB_REG_SHIFT), 559 HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32) | 560 u32_encode_bits((end_offset >> 2), 561 HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1); 562 ath12k_hif_write32(ab, 563 HAL_SEQ_WCSS_UMAC_WBM_REG + 564 HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1(hal), 565 val); 566 567 val = u32_encode_bits(sbuf[0].paddr, BUFFER_ADDR_INFO0_ADDR); 568 ath12k_hif_write32(ab, 569 HAL_SEQ_WCSS_UMAC_WBM_REG + 570 HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0(hal), 571 val); 572 573 val = u32_encode_bits(sbuf[0].paddr, BUFFER_ADDR_INFO0_ADDR); 574 ath12k_hif_write32(ab, 575 HAL_SEQ_WCSS_UMAC_WBM_REG + 576 HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0(hal), 577 val); 578 579 val = u32_encode_bits(((u64)sbuf[0].paddr >> HAL_ADDR_MSB_REG_SHIFT), 580 HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32) | 581 u32_encode_bits(0, HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1); 582 ath12k_hif_write32(ab, 583 HAL_SEQ_WCSS_UMAC_WBM_REG + 584 HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1(hal), 585 val); 586 587 val = 2 * tot_link_desc; 588 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_WBM_REG + 589 HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR(hal), 590 val); 591 592 /* Enable the SRNG */ 593 val = u32_encode_bits(1, HAL_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE) | 594 u32_encode_bits(1, HAL_WBM_IDLE_LINK_RING_MISC_RIND_ID_DISABLE); 595 ath12k_hif_write32(ab, 596 HAL_SEQ_WCSS_UMAC_WBM_REG + 597 HAL_WBM_IDLE_LINK_RING_MISC_ADDR(hal), 598 val); 599 } 600 601 void ath12k_wifi7_hal_tx_configure_bank_register(struct ath12k_base *ab, 602 u32 bank_config, 603 u8 bank_id) 604 { 605 ath12k_hif_write32(ab, HAL_TCL_SW_CONFIG_BANK_ADDR + 4 * bank_id, 606 bank_config); 607 } 608 609 void ath12k_wifi7_hal_reoq_lut_addr_read_enable(struct ath12k_base *ab) 610 { 611 struct ath12k_hal *hal = &ab->hal; 612 613 u32 val = ath12k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + 614 HAL_REO1_QDESC_ADDR(hal)); 615 616 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_ADDR(hal), 617 val | HAL_REO_QDESC_ADDR_READ_LUT_ENABLE); 618 } 619 620 void ath12k_wifi7_hal_reoq_lut_set_max_peerid(struct ath12k_base *ab) 621 { 622 struct ath12k_hal *hal = &ab->hal; 623 624 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_MAX_PEERID(hal), 625 HAL_REO_QDESC_MAX_PEERID); 626 } 627 628 void ath12k_wifi7_hal_write_reoq_lut_addr(struct ath12k_base *ab, 629 dma_addr_t paddr) 630 { 631 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + 632 HAL_REO1_QDESC_LUT_BASE0(&ab->hal), paddr); 633 } 634 635 void ath12k_wifi7_hal_write_ml_reoq_lut_addr(struct ath12k_base *ab, 636 dma_addr_t paddr) 637 { 638 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + 639 HAL_REO1_QDESC_LUT_BASE1(&ab->hal), paddr); 640 } 641 642 void ath12k_wifi7_hal_cc_config(struct ath12k_base *ab) 643 { 644 u32 cmem_base = ab->qmi.dev_mem[ATH12K_QMI_DEVMEM_CMEM_INDEX].start; 645 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; 646 u32 wbm_base = HAL_SEQ_WCSS_UMAC_WBM_REG; 647 u32 val = 0; 648 struct ath12k_hal *hal = &ab->hal; 649 650 if (ath12k_ftm_mode) 651 return; 652 653 ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG0(hal), cmem_base); 654 655 val |= u32_encode_bits(ATH12K_CMEM_ADDR_MSB, 656 HAL_REO1_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB) | 657 u32_encode_bits(ATH12K_CC_PPT_MSB, 658 HAL_REO1_SW_COOKIE_CFG_COOKIE_PPT_MSB) | 659 u32_encode_bits(ATH12K_CC_SPT_MSB, 660 HAL_REO1_SW_COOKIE_CFG_COOKIE_SPT_MSB) | 661 u32_encode_bits(1, HAL_REO1_SW_COOKIE_CFG_ALIGN) | 662 u32_encode_bits(1, HAL_REO1_SW_COOKIE_CFG_ENABLE) | 663 u32_encode_bits(1, HAL_REO1_SW_COOKIE_CFG_GLOBAL_ENABLE); 664 665 ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG1(hal), val); 666 667 /* Enable HW CC for WBM */ 668 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG0, cmem_base); 669 670 val = u32_encode_bits(ATH12K_CMEM_ADDR_MSB, 671 HAL_WBM_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB) | 672 u32_encode_bits(ATH12K_CC_PPT_MSB, 673 HAL_WBM_SW_COOKIE_CFG_COOKIE_PPT_MSB) | 674 u32_encode_bits(ATH12K_CC_SPT_MSB, 675 HAL_WBM_SW_COOKIE_CFG_COOKIE_SPT_MSB) | 676 u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_ALIGN); 677 678 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG1, val); 679 680 /* Enable conversion complete indication */ 681 val = ath12k_hif_read32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG2); 682 val |= u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_RELEASE_PATH_EN) | 683 u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_ERR_PATH_EN) | 684 u32_encode_bits(1, HAL_WBM_SW_COOKIE_CFG_CONV_IND_EN); 685 686 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG2, val); 687 688 /* Enable Cookie conversion for WBM2SW Rings */ 689 val = ath12k_hif_read32(ab, wbm_base + HAL_WBM_SW_COOKIE_CONVERT_CFG); 690 val |= u32_encode_bits(1, HAL_WBM_SW_COOKIE_CONV_CFG_GLOBAL_EN) | 691 hal->hal_params->wbm2sw_cc_enable; 692 693 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CONVERT_CFG, val); 694 } 695 696 enum hal_rx_buf_return_buf_manager 697 ath12k_wifi7_hal_get_idle_link_rbm(struct ath12k_hal *hal, u8 device_id) 698 { 699 switch (device_id) { 700 case 0: 701 return HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST; 702 case 1: 703 return HAL_RX_BUF_RBM_WBM_DEV1_IDLE_DESC_LIST; 704 case 2: 705 return HAL_RX_BUF_RBM_WBM_DEV2_IDLE_DESC_LIST; 706 default: 707 ath12k_warn(hal, 708 "invalid %d device id, so choose default rbm\n", 709 device_id); 710 WARN_ON(1); 711 return HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST; 712 } 713 } 714