1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for the Airoha AN8801 Gigabit PHY. 4 * 5 * Copyright (C) 2025 Airoha Technology Corp. 6 * Copyright (C) 2025 Collabora Ltd. 7 * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bitops.h> 12 #include <linux/delay.h> 13 #include <linux/errno.h> 14 #include <linux/etherdevice.h> 15 #include <linux/init.h> 16 #include <linux/minmax.h> 17 #include <linux/netdevice.h> 18 #include <linux/of.h> 19 #include <linux/phy.h> 20 #include <linux/pm_wakeirq.h> 21 22 #include "air_phy_lib.h" 23 24 #define AN8801R_PHY_ID 0xc0ff0421 25 26 /* MII Registers */ 27 28 /* MII Registers - Airoha Page 1 */ 29 #define AN8801_EXT_REG_PHY 0x14 30 #define AN8801_EXT_PHY_STATUS0 GENMASK(1, 0) 31 #define AN8801_EXT_PHY_DOWNSHIFT_CTL GENMASK(3, 2) /* 2 to 5 1G auto-neg attempts (0..3) */ 32 #define AN8801_EXT_PHY_DOWNSHIFT_EN BIT(4) 33 #define AN8801_EXT_PHY_CTRL0 BIT(5) 34 #define AN8801_EXT_PHY_STATUS1 GENMASK(8, 6) 35 #define AN8801_EXT_PHY_CTRL1 GENMASK(14, 9) 36 37 /* MII Registers - Airoha Page 4 */ 38 #define AN8801_PBUS_ACCESS BIT(28) 39 #define AN8801_PBUS_EPHY_ACCESS BIT(24) 40 #define AN8801_PBUS_CL22_ACCESS BIT(23) 41 42 /* BPBUS Registers */ 43 #define AN8801_BPBUS_REG_LED_GPIO 0x54 44 #define AN8801_BPBUS_REG_LED_ID_SEL 0x58 45 #define LED_ID_GPIO_SEL(led, gpio) ((led) << ((gpio) * 3)) 46 #define LED_ID_GPIO_SEL_MASK(gpio) (0x7 << ((gpio) * 3)) 47 #define AN8801_BPBUS_REG_GPIO_MODE 0x70 48 #define AN8801_BPBUS_REG_PHY_IRQ_GPIO 0x7c 49 #define AN8801_PHY_IRQ_GPIO_NUM_MASK GENMASK(19, 16) 50 #define AN8801_PHY_IRQ_GPIO_NUM 1 51 52 #define AN8801_BPBUS_REG_CKO 0x1a4 53 #define AN8801_CKO_OUTPUT_MODE_AUTO 3 54 55 #define AN8801_BPBUS_REG_LINK_MODE 0x5054 56 #define AN8801_BPBUS_LINK_MODE_1000 BIT(0) 57 58 #define AN8801_BPBUS_REG_BYPASS_PTP 0x21c004 59 #define AN8801_BYP_PTP_SGMII_TO_GPHY BIT(8) 60 #define AN8801_BYP_PTP_RGMII_TO_GPHY BIT(0) 61 62 #define AN8801_BPBUS_REG_TXDLY_STEP 0x21c024 63 #define RGMII_DELAY_STEP_MASK GENMASK(2, 0) 64 #define RGMII_DELAY_NO_STEP 0 65 #define RGMII_DELAY_STEP_1 1 66 #define RGMII_DELAY_STEP_2 2 67 #define RGMII_DELAY_STEP_3 3 68 #define RGMII_DELAY_STEP_4 4 69 #define RGMII_DELAY_STEP_5 5 70 #define RGMII_DELAY_STEP_6 6 71 #define RGMII_DELAY_STEP_7 7 72 #define RGMII_TXDELAY_FORCE_MODE BIT(24) 73 74 /* Default RGMII TX delay setting, corresponding to a 1.883ns delay */ 75 #define AN8801_RGMII_TXDELAY_DEFAULT RGMII_DELAY_STEP_4 76 77 #define AN8801_BPBUS_REG_RXDLY_STEP 0x21c02c 78 #define RGMII_RXDELAY_ALIGN BIT(4) 79 #define RGMII_RXDELAY_FORCE_MODE BIT(24) 80 81 /* Default RGMII RX delay setting, corresponding to a 1.992ns delay, 82 * when align bit is set or -0.008ns otherwise. 83 */ 84 #define AN8801_RGMII_RXDELAY_DEFAULT RGMII_DELAY_NO_STEP 85 86 #define AN8801_BPBUS_REG_EFIFO_CTL(x) (0x270004 + (0x100 * (x))) /* 0..2 */ 87 #define AN8801_EFIFO_ALL_EN GENMASK(7, 0) 88 #define AN8801_EFIFO_RX_EN BIT(0) 89 #define AN8801_EFIFO_TX_EN BIT(1) 90 #define AN8801_EFIFO_RX_CLK_EN BIT(2) 91 #define AN8801_EFIFO_TX_CLK_EN BIT(3) 92 #define AN8801_EFIFO_RX_EEE_EN BIT(4) 93 #define AN8801_EFIFO_TX_EEE_EN BIT(5) 94 #define AN8801_EFIFO_RX_ODD_NIBBLE_EN BIT(6) 95 #define AN8801_EFIFO_TX_ODD_NIBBLE_EN BIT(7) 96 97 #define AN8801_BPBUS_REG_WOL_MAC_16_47 0x285114 98 #define AN8801_BPBUS_REG_WOL_MAC_0_15 0x285118 99 100 #define AN8801_BPBUS_REG_WAKEUP_CTL1 0x285400 101 #define AN8801_WOL_WAKE_MAGIC_EN GENMASK(3, 1) 102 #define AN8801_WOL_WAKE_LNKCHG_EN BIT(4) 103 104 #define AN8801_BPBUS_REG_WAKEUP_CTL2 0x285404 105 #define AN8801_WAKE_OUT_TYPE_PULSE BIT(0) /* Set/Unset: Pulse/Static */ 106 #define AN8801_WAKE_OUT_POLARITY_NEG BIT(1) /* Set/Unset: Negative/Positive */ 107 #define AN8801_WAKE_OUT_WIDTH GENMASK(3, 2) 108 #define AN8801_WAKE_OUT_84MS 0 109 #define AN8801_WAKE_OUT_168MS 1 110 #define AN8801_WAKE_OUT_336MS 2 111 #define AN8801_WAKE_OUT_672MS 3 112 #define AN8801_WAKE_OUT_EN BIT(4) 113 #define AN8801_PME_WAKEUP_CLR BIT(8) 114 115 #define AN8801_BPBUS_REG_WAKE_IRQ_EN 0x285700 116 #define AN8801_BPBUS_REG_WAKE_IRQ_STS 0x285704 117 #define AN8801_IRQ_WAKE_LNKCHG BIT(0) /* Wake on link change */ 118 #define AN8801_IRQ_WAKE_UNIPKT BIT(1) /* Wake on unicast packet */ 119 #define AN8801_IRQ_WAKE_MULPKT BIT(2) /* Wake on multicast packet */ 120 #define AN8801_IRQ_WAKE_BCPKT BIT(3) /* Wake on broadcast packet */ 121 #define AN8801_IRQ_WAKE_MAGICPKT BIT(4) /* Wake on magic packet */ 122 #define AN8801_IRQ_WAKE_ALL GENMASK(4, 0) 123 124 /* MDIO_MMD_VEND1 Registers */ 125 #define AN8801_PHY_TX_PAIR_DLY_SEL_GBE 0x13 126 #define AN8801_PHY_PAIR_DLY_SEL_A_GBE GENMASK(14, 12) 127 #define AN8801_PHY_PAIR_DLY_SEL_B_GBE GENMASK(10, 8) 128 #define AN8801_PHY_PAIR_DLY_SEL_C_GBE GENMASK(6, 4) 129 #define AN8801_PHY_PAIR_DLY_SEL_D_GBE GENMASK(2, 0) 130 #define AN8801_PHY_RXADC_CTRL 0xd8 131 #define AN8801_PHY_RXADC_SAMP_PHSEL_A BIT(12) 132 #define AN8801_PHY_RXADC_SAMP_PHSEL_B BIT(8) 133 #define AN8801_PHY_RXADC_SAMP_PHSEL_C BIT(4) 134 #define AN8801_PHY_RXADC_SAMP_PHSEL_D BIT(0) 135 #define AN8801_PHY_RXADC_REV_0 0xd9 136 #define AN8801_PHY_RXADC_REV_MASK_A GENMASK(15, 8) 137 #define AN8801_PHY_RXADC_REV_MASK_B GENMASK(7, 0) 138 #define AN8801_PHY_RXADC_REV_1 0xda 139 #define AN8801_PHY_RXADC_REV_MASK_C GENMASK(15, 8) 140 #define AN8801_PHY_RXADC_REV_MASK_D GENMASK(7, 0) 141 142 /* MDIO_MMD_VEND2 Registers */ 143 #define LED_BCR 0x21 144 #define LED_BCR_MODE_MASK GENMASK(1, 0) 145 #define LED_BCR_TIME_TEST BIT(2) 146 #define LED_BCR_CLK_EN BIT(3) 147 #define LED_BCR_EVT_ALL BIT(4) 148 #define LED_BCR_EXT_CTRL BIT(15) 149 #define LED_BCR_MODE_DISABLE 0 150 #define LED_BCR_MODE_2LED 1 151 #define LED_BCR_MODE_3LED_1 2 152 #define LED_BCR_MODE_3LED_2 3 153 154 #define LED_ON_DUR 0x22 155 #define LED_ON_DUR_MASK GENMASK(15, 0) 156 157 #define LED_BLINK_DUR 0x23 158 #define LED_BLINK_DUR_MASK GENMASK(15, 0) 159 160 #define LED_ON_CTRL(i) (0x24 + ((i) * 2)) 161 #define LED_ON_EVT_MASK GENMASK(6, 0) 162 #define LED_ON_EVT_LINK_1000M BIT(0) 163 #define LED_ON_EVT_LINK_100M BIT(1) 164 #define LED_ON_EVT_LINK_10M BIT(2) 165 #define LED_ON_EVT_LINK_DN BIT(3) 166 #define LED_ON_EVT_FDX BIT(4) 167 #define LED_ON_EVT_HDX BIT(5) 168 #define LED_ON_EVT_FORCE BIT(6) 169 #define LED_ON_POL BIT(14) 170 #define LED_ON_EN BIT(15) 171 172 #define LED_BLINK_CTRL(i) (0x25 + ((i) * 2)) 173 #define LED_BLINK_EVT_MASK GENMASK(9, 0) 174 #define LED_BLINK_EVT_1000M_TX BIT(0) 175 #define LED_BLINK_EVT_1000M_RX BIT(1) 176 #define LED_BLINK_EVT_100M_TX BIT(2) 177 #define LED_BLINK_EVT_100M_RX BIT(3) 178 #define LED_BLINK_EVT_10M_TX BIT(4) 179 #define LED_BLINK_EVT_10M_RX BIT(5) 180 #define LED_BLINK_EVT_COLLISION BIT(6) 181 #define LED_BLINK_EVT_RX_CRC_ERR BIT(7) 182 #define LED_BLINK_EVT_RX_IDLE_ERR BIT(8) 183 #define LED_BLINK_EVT_FORCE BIT(9) 184 185 #define AN8801R_NUM_LEDS 3 186 #define AN8801_PERIOD_SHIFT 15 187 #define AN8801_PERIOD_UNIT 32768 /* (1 << AN8801_PERIOD_SHIFT) */ 188 #define AN8801_MAX_PERIOD_MS 2147 189 190 #define AN8801_REG_PHY_INTERNAL0 0x600 191 #define AN8801_REG_PHY_INTERNAL1 0x601 192 #define AN8801_PHY_INTFUNC_MASK GENMASK(15, 0) /* PHY internal functions */ 193 194 enum an8801r_led_fn { 195 AN8801R_LED_FN_NONE, 196 AN8801R_LED_FN_LINK, 197 AN8801R_LED_FN_ACTIVITY, 198 AN8801R_LED_FN_MAX, 199 }; 200 201 struct an8801r_priv { 202 bool wake_magic_enabled; 203 bool wake_lnkchg_enabled; 204 }; 205 206 static const unsigned long an8801r_led_trig = BIT(TRIGGER_NETDEV_LINK) | 207 BIT(TRIGGER_NETDEV_LINK_10) | 208 BIT(TRIGGER_NETDEV_LINK_100) | 209 BIT(TRIGGER_NETDEV_LINK_1000) | 210 BIT(TRIGGER_NETDEV_RX) | 211 BIT(TRIGGER_NETDEV_RX_ERR) | 212 BIT(TRIGGER_NETDEV_TX); 213 214 static int an8801_buckpbus_reg_rmw(struct phy_device *phydev, 215 u32 addr, u32 mask, u32 set) 216 { 217 return air_phy_buckpbus_reg_modify(phydev, 218 addr | AN8801_PBUS_ACCESS, 219 mask, set); 220 } 221 222 static int an8801_buckpbus_reg_set_bits(struct phy_device *phydev, 223 u32 addr, u32 mask) 224 { 225 return air_phy_buckpbus_reg_modify(phydev, 226 addr | AN8801_PBUS_ACCESS, 227 mask, mask); 228 } 229 230 static int an8801_buckpbus_reg_clear_bits(struct phy_device *phydev, 231 u32 addr, u32 mask) 232 { 233 return air_phy_buckpbus_reg_modify(phydev, 234 addr | AN8801_PBUS_ACCESS, 235 mask, 0); 236 } 237 238 static int an8801_buckpbus_reg_write(struct phy_device *phydev, u32 addr, 239 u32 data) 240 { 241 return air_phy_buckpbus_reg_write(phydev, 242 addr | AN8801_PBUS_ACCESS, 243 data); 244 } 245 246 static int an8801_buckpbus_reg_read(struct phy_device *phydev, u32 addr, 247 u32 *data) 248 { 249 return air_phy_buckpbus_reg_read(phydev, 250 addr | AN8801_PBUS_ACCESS, 251 data); 252 } 253 254 static u32 an8801r_led_blink_ms_to_hw(unsigned long req_ms) 255 { 256 u32 req_ns, regval; 257 258 if (req_ms > AN8801_MAX_PERIOD_MS) 259 req_ms = AN8801_MAX_PERIOD_MS; 260 261 req_ns = req_ms * NSEC_PER_MSEC; 262 263 /* Round to the nearest period unit... */ 264 regval = req_ns + (AN8801_PERIOD_UNIT / 2); 265 266 /* ...and now divide by the full period */ 267 regval >>= AN8801_PERIOD_SHIFT; 268 269 return regval; 270 } 271 272 static int an8801r_led_blink_set(struct phy_device *phydev, u8 index, 273 unsigned long *delay_on, 274 unsigned long *delay_off) 275 { 276 u32 hw_delay_on, hw_delay_off; 277 u16 blink_dur; 278 bool blink; 279 int ret; 280 281 if (index >= AN8801R_NUM_LEDS) 282 return -EINVAL; 283 284 if (delay_on && delay_off) { 285 blink = true; 286 287 if (*delay_on == 0 || *delay_off == 0) { 288 *delay_on = 64; 289 *delay_off = 64; 290 } 291 292 hw_delay_on = an8801r_led_blink_ms_to_hw(*delay_on); 293 hw_delay_off = an8801r_led_blink_ms_to_hw(*delay_off); 294 } else { 295 blink = false; 296 } 297 298 if (blink) { 299 blink_dur = (u16)min(hw_delay_on + hw_delay_off, 300 LED_BLINK_DUR_MASK); 301 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LED_BLINK_DUR, 302 blink_dur); 303 if (ret) 304 goto error; 305 306 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, LED_ON_DUR, 307 hw_delay_on); 308 if (ret) 309 goto error; 310 } 311 312 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_BLINK_CTRL(index), 313 LED_BLINK_EVT_MASK, 314 blink ? LED_BLINK_EVT_FORCE : 0); 315 if (ret) 316 return ret; 317 318 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index), 319 LED_ON_EVT_MASK, 320 0); 321 if (ret) 322 return ret; 323 324 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index), 325 LED_ON_EN, blink ? LED_ON_EN : 0); 326 327 error: 328 phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index), 329 LED_ON_EN, 0); 330 return ret; 331 } 332 333 static int an8801r_led_brightness_set(struct phy_device *phydev, u8 index, 334 enum led_brightness value) 335 { 336 int ret; 337 338 if (index >= AN8801R_NUM_LEDS) 339 return -EINVAL; 340 341 /* Disable blink first if previously enabled */ 342 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_BLINK_CTRL(index), 343 LED_BLINK_EVT_MASK, 0); 344 if (ret) 345 return ret; 346 347 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index), 348 LED_ON_EVT_MASK, 349 (value == LED_OFF) ? 0 : LED_ON_EVT_FORCE); 350 if (ret) 351 return ret; 352 353 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index), 354 LED_ON_EN, (value == LED_OFF) ? 0 : LED_ON_EN); 355 } 356 357 static int an8801r_led_hw_control_get(struct phy_device *phydev, u8 index, 358 unsigned long *rules) 359 { 360 int on, blink; 361 362 if (index >= AN8801R_NUM_LEDS) 363 return -EINVAL; 364 365 on = phy_read_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index)); 366 if (on < 0) 367 return on; 368 369 blink = phy_read_mmd(phydev, MDIO_MMD_VEND2, LED_BLINK_CTRL(index)); 370 if (blink < 0) 371 return blink; 372 373 if (FIELD_GET(LED_ON_EVT_LINK_10M, on)) 374 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 375 376 if (FIELD_GET(LED_ON_EVT_LINK_100M, on)) 377 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 378 379 if (FIELD_GET(LED_ON_EVT_LINK_1000M, on)) 380 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 381 382 if (FIELD_GET(LED_ON_EVT_LINK_10M, on) && 383 FIELD_GET(LED_ON_EVT_LINK_100M, on) && 384 FIELD_GET(LED_ON_EVT_LINK_1000M, on)) 385 __set_bit(TRIGGER_NETDEV_LINK, rules); 386 387 if (FIELD_GET(LED_BLINK_EVT_10M_RX, blink) || 388 FIELD_GET(LED_BLINK_EVT_100M_RX, blink) || 389 FIELD_GET(LED_BLINK_EVT_1000M_RX, blink)) 390 __set_bit(TRIGGER_NETDEV_RX, rules); 391 392 if (FIELD_GET(LED_BLINK_EVT_10M_TX, blink) || 393 FIELD_GET(LED_BLINK_EVT_100M_TX, blink) || 394 FIELD_GET(LED_BLINK_EVT_1000M_TX, blink)) 395 __set_bit(TRIGGER_NETDEV_TX, rules); 396 397 if (FIELD_GET(LED_BLINK_EVT_RX_CRC_ERR, blink)) 398 __set_bit(TRIGGER_NETDEV_RX_ERR, rules); 399 400 return 0; 401 } 402 403 static int an8801r_led_trig_to_hw(unsigned long rules, u16 *on, u16 *blink) 404 { 405 /* All combinations of the supported triggers are allowed */ 406 if (rules & ~an8801r_led_trig) 407 return -EOPNOTSUPP; 408 409 if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) 410 *on |= LED_ON_EVT_LINK_10M; 411 412 if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) 413 *on |= LED_ON_EVT_LINK_100M; 414 415 if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) 416 *on |= LED_ON_EVT_LINK_1000M; 417 418 if (test_bit(TRIGGER_NETDEV_LINK, &rules)) { 419 *on |= LED_ON_EVT_LINK_10M; 420 *on |= LED_ON_EVT_LINK_100M; 421 *on |= LED_ON_EVT_LINK_1000M; 422 } 423 424 if (test_bit(TRIGGER_NETDEV_RX, &rules)) { 425 *blink |= LED_BLINK_EVT_10M_RX; 426 *blink |= LED_BLINK_EVT_100M_RX; 427 *blink |= LED_BLINK_EVT_1000M_RX; 428 } 429 430 if (test_bit(TRIGGER_NETDEV_TX, &rules)) { 431 *blink |= LED_BLINK_EVT_10M_TX; 432 *blink |= LED_BLINK_EVT_100M_TX; 433 *blink |= LED_BLINK_EVT_1000M_TX; 434 } 435 436 if (test_bit(TRIGGER_NETDEV_RX_ERR, &rules)) 437 *blink |= LED_BLINK_EVT_RX_CRC_ERR; 438 439 return 0; 440 } 441 442 static int an8801r_led_hw_is_supported(struct phy_device *phydev, u8 index, 443 unsigned long rules) 444 { 445 u16 on = 0, blink = 0; 446 447 if (index >= AN8801R_NUM_LEDS) 448 return -EINVAL; 449 450 return an8801r_led_trig_to_hw(rules, &on, &blink); 451 } 452 453 static int an8801r_led_hw_control_set(struct phy_device *phydev, u8 index, 454 unsigned long rules) 455 { 456 u16 on = 0, blink = 0; 457 int ret; 458 459 if (index >= AN8801R_NUM_LEDS) 460 return -EINVAL; 461 462 ret = an8801r_led_trig_to_hw(rules, &on, &blink); 463 if (ret) 464 return ret; 465 466 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index), 467 LED_ON_EVT_MASK, on); 468 if (ret) 469 return ret; 470 471 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_BLINK_CTRL(index), 472 LED_BLINK_EVT_MASK, blink); 473 if (ret) 474 return ret; 475 476 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index), 477 LED_ON_EN, (on | blink) ? LED_ON_EN : 0); 478 } 479 480 static int an8801r_led_polarity_set(struct phy_device *phydev, int index, 481 unsigned long modes) 482 { 483 bool active_high = true; 484 unsigned long mode; 485 486 if (index >= AN8801R_NUM_LEDS) 487 return -EINVAL; 488 489 for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) { 490 switch (mode) { 491 case PHY_LED_ACTIVE_HIGH: 492 break; 493 case PHY_LED_ACTIVE_LOW: 494 active_high = false; 495 break; 496 default: 497 return -EINVAL; 498 } 499 } 500 501 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, LED_ON_CTRL(index), 502 LED_ON_POL, active_high ? LED_ON_POL : 0); 503 } 504 505 static int an8801r_led_init(struct phy_device *phydev, u8 *led_cfg) 506 { 507 int led_id, ret; 508 509 /* Set LED BCR Enable */ 510 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, LED_BCR, 511 LED_BCR_EXT_CTRL | LED_BCR_CLK_EN); 512 if (ret) 513 return ret; 514 515 for (led_id = 0; led_id < AN8801R_NUM_LEDS; led_id++) { 516 unsigned long led_trigger = 0; 517 u32 led_gpio = led_id + 1; 518 519 switch (led_cfg[led_id]) { 520 case AN8801R_LED_FN_LINK: 521 led_trigger = BIT(TRIGGER_NETDEV_LINK); 522 break; 523 case AN8801R_LED_FN_ACTIVITY: 524 led_trigger = BIT(TRIGGER_NETDEV_RX) | 525 BIT(TRIGGER_NETDEV_TX); 526 break; 527 default: 528 led_trigger = 0; 529 break; 530 } 531 532 ret = an8801_buckpbus_reg_set_bits(phydev, 533 AN8801_BPBUS_REG_LED_GPIO, 534 BIT(led_gpio)); 535 if (ret) 536 return ret; 537 538 ret = an8801_buckpbus_reg_rmw(phydev, 539 AN8801_BPBUS_REG_LED_ID_SEL, 540 LED_ID_GPIO_SEL_MASK(led_gpio), 541 LED_ID_GPIO_SEL(led_id, 542 led_gpio)); 543 if (ret) 544 return ret; 545 546 ret = an8801_buckpbus_reg_clear_bits(phydev, 547 AN8801_BPBUS_REG_GPIO_MODE, 548 BIT(led_gpio)); 549 if (ret) 550 return ret; 551 552 if (!led_trigger) 553 continue; 554 555 ret = an8801r_led_hw_control_set(phydev, led_id, led_trigger); 556 if (ret) 557 return ret; 558 } 559 560 return ret; 561 } 562 563 static int an8801r_reset_wake(struct phy_device *phydev) 564 { 565 struct an8801r_priv *priv = phydev->priv; 566 u32 reg_val = 0; 567 int ret; 568 569 /* Enable wakeup clear and disable wake up output */ 570 ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKEUP_CTL2, 571 AN8801_PME_WAKEUP_CLR | 572 AN8801_WAKE_OUT_POLARITY_NEG); 573 if (ret) 574 return ret; 575 576 /* Clear WAKEUP_CTL1 register before enabling the wakeup events 577 * again 578 */ 579 ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKEUP_CTL1, 580 0); 581 if (ret) 582 return ret; 583 584 if (priv->wake_magic_enabled) 585 reg_val |= AN8801_WOL_WAKE_MAGIC_EN; 586 587 if (priv->wake_lnkchg_enabled) 588 reg_val |= AN8801_WOL_WAKE_LNKCHG_EN; 589 590 ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKEUP_CTL1, 591 reg_val); 592 if (ret) 593 return ret; 594 595 /* Disable wake up clear and re-enable wake up output */ 596 return an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKEUP_CTL2, 597 AN8801_WAKE_OUT_POLARITY_NEG | 598 AN8801_WAKE_OUT_EN); 599 } 600 601 static int an8801r_ack_interrupt(struct phy_device *phydev) 602 { 603 int ret; 604 605 /* Reset wake status */ 606 ret = an8801r_reset_wake(phydev); 607 if (ret) 608 return ret; 609 610 /* Clear the interrupts by writing the reg */ 611 return an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_WAKE_IRQ_STS, 612 AN8801_IRQ_WAKE_ALL); 613 } 614 615 static int an8801r_config_intr(struct phy_device *phydev) 616 { 617 int ret; 618 619 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 620 u32 val = FIELD_PREP(AN8801_PHY_IRQ_GPIO_NUM_MASK, 621 AN8801_PHY_IRQ_GPIO_NUM); 622 623 ret = an8801_buckpbus_reg_write(phydev, 624 AN8801_BPBUS_REG_PHY_IRQ_GPIO, 625 val); 626 if (ret) 627 return ret; 628 629 ret = an8801_buckpbus_reg_set_bits(phydev, 630 AN8801_BPBUS_REG_WAKE_IRQ_EN, 631 AN8801_IRQ_WAKE_LNKCHG); 632 if (ret) 633 return ret; 634 635 } else { 636 ret = an8801_buckpbus_reg_write(phydev, 637 AN8801_BPBUS_REG_PHY_IRQ_GPIO, 638 0); 639 if (ret) 640 return ret; 641 642 ret = an8801_buckpbus_reg_clear_bits(phydev, 643 AN8801_BPBUS_REG_WAKE_IRQ_EN, 644 AN8801_IRQ_WAKE_LNKCHG); 645 if (ret) 646 return ret; 647 } 648 649 return an8801r_ack_interrupt(phydev); 650 } 651 652 static irqreturn_t an8801r_handle_interrupt(struct phy_device *phydev) 653 { 654 u32 irq_status = 0; 655 bool irq_handled = false; 656 int ret; 657 658 ret = an8801_buckpbus_reg_read(phydev, AN8801_BPBUS_REG_WAKE_IRQ_STS, 659 &irq_status); 660 if (ret) 661 return IRQ_NONE; 662 663 ret = an8801r_ack_interrupt(phydev); 664 if (ret) 665 return IRQ_NONE; 666 667 if (irq_status & AN8801_IRQ_WAKE_MAGICPKT) { 668 pm_wakeup_event(&phydev->mdio.dev, 0); 669 irq_handled = true; 670 } 671 672 if (irq_status & AN8801_IRQ_WAKE_LNKCHG) { 673 phy_trigger_machine(phydev); 674 irq_handled = true; 675 } 676 677 return irq_handled ? IRQ_HANDLED : IRQ_NONE; 678 } 679 680 static void an8801r_get_wol(struct phy_device *phydev, 681 struct ethtool_wolinfo *wol) 682 { 683 u32 reg_val; 684 int ret; 685 686 /* If the PHY is not capable of waking the system, then WoL can not 687 * be supported. 688 */ 689 if (!device_can_wakeup(&phydev->mdio.dev)) { 690 wol->supported = 0; 691 return; 692 } 693 694 wol->supported = WAKE_MAGIC; 695 wol->wolopts = 0; 696 697 ret = an8801_buckpbus_reg_read(phydev, AN8801_BPBUS_REG_WAKEUP_CTL1, 698 ®_val); 699 if (ret) 700 return; 701 702 if (reg_val & AN8801_WOL_WAKE_MAGIC_EN) 703 wol->wolopts |= WAKE_MAGIC; 704 else 705 wol->wolopts &= ~WAKE_MAGIC; 706 } 707 708 static int an8801r_set_wol(struct phy_device *phydev, 709 struct ethtool_wolinfo *wol) 710 { 711 struct an8801r_priv *priv = phydev->priv; 712 struct net_device *attach_dev; 713 const u8 *macaddr; 714 u32 reg_val; 715 int ret; 716 717 if (!device_can_wakeup(&phydev->mdio.dev)) 718 return -EOPNOTSUPP; 719 720 if (wol->wolopts & ~WAKE_MAGIC) 721 return -EINVAL; 722 723 if (wol->wolopts & WAKE_MAGIC) { 724 attach_dev = phydev->attached_dev; 725 if (!attach_dev) 726 return -ENODEV; 727 728 macaddr = (const u8 *)attach_dev->dev_addr; 729 if (!is_valid_ether_addr(macaddr)) 730 return -EINVAL; 731 732 /* MAC bits 16..47 */ 733 reg_val = (macaddr[2] << 24) | (macaddr[3] << 16); 734 reg_val |= (macaddr[4] << 8) | (macaddr[5]); 735 736 ret = an8801_buckpbus_reg_write(phydev, 737 AN8801_BPBUS_REG_WOL_MAC_16_47, 738 reg_val); 739 if (ret) 740 return ret; 741 742 /* MAC bits 0..15 */ 743 reg_val = (macaddr[0] << 8) | (macaddr[1]); 744 745 ret = an8801_buckpbus_reg_write(phydev, 746 AN8801_BPBUS_REG_WOL_MAC_0_15, 747 reg_val); 748 if (ret) 749 return ret; 750 751 ret = an8801_buckpbus_reg_set_bits(phydev, 752 AN8801_BPBUS_REG_WAKEUP_CTL1, 753 AN8801_WOL_WAKE_MAGIC_EN); 754 if (ret) 755 return ret; 756 757 ret = an8801_buckpbus_reg_set_bits(phydev, 758 AN8801_BPBUS_REG_WAKE_IRQ_EN, 759 AN8801_IRQ_WAKE_MAGICPKT); 760 if (ret) 761 return ret; 762 763 } else { 764 ret = an8801_buckpbus_reg_clear_bits(phydev, 765 AN8801_BPBUS_REG_WAKEUP_CTL1, 766 AN8801_WOL_WAKE_MAGIC_EN); 767 if (ret) 768 return ret; 769 770 ret = an8801_buckpbus_reg_clear_bits(phydev, 771 AN8801_BPBUS_REG_WAKE_IRQ_EN, 772 AN8801_IRQ_WAKE_MAGICPKT); 773 if (ret) 774 return ret; 775 } 776 777 priv->wake_magic_enabled = !!(wol->wolopts & WAKE_MAGIC); 778 779 return device_set_wakeup_enable(&phydev->mdio.dev, 780 priv->wake_magic_enabled); 781 } 782 783 static int an8801r_of_init_leds(struct phy_device *phydev, u8 *led_cfg) 784 { 785 struct device *dev = &phydev->mdio.dev; 786 struct device_node *np = dev->of_node; 787 struct device_node *leds; 788 u32 function_enum_idx; 789 int ret = 0; 790 791 if (!np) 792 return 0; 793 794 /* If devicetree is present, leds configuration is required */ 795 leds = of_get_child_by_name(np, "leds"); 796 if (!leds) 797 return 0; 798 799 for_each_available_child_of_node_scoped(leds, led) { 800 u32 led_idx; 801 802 ret = of_property_read_u32(led, "reg", &led_idx); 803 if (ret) 804 goto out; 805 806 if (led_idx >= AN8801R_NUM_LEDS) { 807 ret = -EINVAL; 808 goto out; 809 } 810 811 ret = of_property_read_u32(led, "function-enumerator", 812 &function_enum_idx); 813 if (ret) { 814 function_enum_idx = AN8801R_LED_FN_NONE; 815 ret = 0; 816 } 817 818 if (function_enum_idx >= AN8801R_LED_FN_MAX) { 819 ret = -EINVAL; 820 goto out; 821 } 822 823 led_cfg[led_idx] = function_enum_idx; 824 } 825 out: 826 of_node_put(leds); 827 return ret; 828 } 829 830 static int an8801r_rgmii_rxdelay(struct phy_device *phydev, bool enable, 831 u16 delay_steps) 832 { 833 u32 reg_val; 834 835 if (delay_steps > RGMII_DELAY_STEP_MASK) 836 return -EINVAL; 837 838 if (enable) { 839 /* Set force mode bit to enable RX delay insertion */ 840 reg_val = delay_steps | RGMII_RXDELAY_FORCE_MODE; 841 842 /* Set align bit to add extra offset for RX delay */ 843 reg_val |= RGMII_RXDELAY_ALIGN; 844 } else { 845 reg_val = 0; 846 } 847 848 return an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_RXDLY_STEP, 849 reg_val); 850 } 851 852 static int an8801r_rgmii_txdelay(struct phy_device *phydev, bool enable, 853 u16 delay_steps) 854 { 855 u32 reg_val; 856 857 if (delay_steps > RGMII_DELAY_STEP_MASK) 858 return -EINVAL; 859 860 if (enable) { 861 /* Set force mode bit to enable TX delay insertion */ 862 reg_val = delay_steps | RGMII_TXDELAY_FORCE_MODE; 863 } else { 864 reg_val = 0; 865 } 866 867 return an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_TXDLY_STEP, 868 reg_val); 869 } 870 871 static int an8801r_rgmii_delay_config(struct phy_device *phydev) 872 { 873 bool enable_delay; 874 u16 delay_step; 875 int ret; 876 877 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 878 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { 879 enable_delay = true; 880 delay_step = AN8801_RGMII_TXDELAY_DEFAULT; 881 } else { 882 enable_delay = false; 883 delay_step = RGMII_DELAY_NO_STEP; 884 } 885 886 ret = an8801r_rgmii_txdelay(phydev, enable_delay, delay_step); 887 if (ret) 888 return ret; 889 890 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 891 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { 892 enable_delay = true; 893 delay_step = AN8801_RGMII_RXDELAY_DEFAULT; 894 } else { 895 enable_delay = false; 896 delay_step = RGMII_DELAY_NO_STEP; 897 } 898 899 return an8801r_rgmii_rxdelay(phydev, enable_delay, delay_step); 900 } 901 902 static int an8801r_config_init(struct phy_device *phydev) 903 { 904 u8 led_default_function[AN8801R_NUM_LEDS] = { 0 }; 905 int ret; 906 907 ret = an8801r_of_init_leds(phydev, led_default_function); 908 if (ret) 909 return ret; 910 911 /* Disable Low Power Mode (LPM) */ 912 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AN8801_REG_PHY_INTERNAL0, 913 FIELD_PREP(AN8801_PHY_INTFUNC_MASK, 0x1e)); 914 if (ret) 915 return ret; 916 917 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AN8801_REG_PHY_INTERNAL1, 918 FIELD_PREP(AN8801_PHY_INTFUNC_MASK, 0x2)); 919 if (ret) 920 return ret; 921 922 /* Set the PHY to perform auto-downshift after 3 auto-negotiation 923 * attempts 924 */ 925 ret = phy_write_paged(phydev, AIR_PHY_PAGE_EXTENDED_1, 926 AN8801_EXT_REG_PHY, 927 FIELD_PREP(AN8801_EXT_PHY_CTRL1, 0x1d) | 928 FIELD_PREP(AN8801_EXT_PHY_DOWNSHIFT_CTL, 1) | 929 AN8801_EXT_PHY_DOWNSHIFT_EN); 930 if (ret < 0) 931 return ret; 932 933 ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_BYPASS_PTP, 934 AN8801_BYP_PTP_RGMII_TO_GPHY); 935 if (ret) 936 return ret; 937 938 ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_EFIFO_CTL(0), 939 AN8801_EFIFO_RX_EN | 940 AN8801_EFIFO_TX_EN | 941 AN8801_EFIFO_RX_CLK_EN | 942 AN8801_EFIFO_TX_CLK_EN | 943 AN8801_EFIFO_RX_EEE_EN | 944 AN8801_EFIFO_TX_EEE_EN); 945 if (ret) 946 return ret; 947 948 ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_EFIFO_CTL(1), 949 AN8801_EFIFO_ALL_EN); 950 if (ret) 951 return ret; 952 953 ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_EFIFO_CTL(2), 954 AN8801_EFIFO_ALL_EN); 955 if (ret) 956 return ret; 957 958 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 959 AN8801_PHY_TX_PAIR_DLY_SEL_GBE, 960 FIELD_PREP(AN8801_PHY_PAIR_DLY_SEL_A_GBE, 4) | 961 FIELD_PREP(AN8801_PHY_PAIR_DLY_SEL_C_GBE, 4)); 962 if (ret) 963 return ret; 964 965 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8801_PHY_RXADC_CTRL, 966 AN8801_PHY_RXADC_SAMP_PHSEL_A | 967 AN8801_PHY_RXADC_SAMP_PHSEL_C); 968 if (ret) 969 return ret; 970 971 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8801_PHY_RXADC_REV_0, 972 FIELD_PREP(AN8801_PHY_RXADC_REV_MASK_A, 1)); 973 if (ret) 974 return ret; 975 976 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8801_PHY_RXADC_REV_1, 977 FIELD_PREP(AN8801_PHY_RXADC_REV_MASK_C, 1)); 978 if (ret) 979 return ret; 980 981 ret = an8801r_rgmii_delay_config(phydev); 982 if (ret) 983 return ret; 984 985 ret = an8801_buckpbus_reg_write(phydev, AN8801_BPBUS_REG_CKO, 986 AN8801_CKO_OUTPUT_MODE_AUTO); 987 if (ret) 988 return ret; 989 990 ret = an8801r_led_init(phydev, led_default_function); 991 if (ret) { 992 phydev_err(phydev, "Cannot initialize LEDs: %d\n", ret); 993 return ret; 994 } 995 996 return 0; 997 } 998 999 static int an8801r_read_status(struct phy_device *phydev) 1000 { 1001 int prev_speed, ret; 1002 u32 val; 1003 1004 prev_speed = phydev->speed; 1005 1006 ret = genphy_read_status(phydev); 1007 if (ret) 1008 return ret; 1009 1010 if (!phydev->link) { 1011 phydev->speed = SPEED_UNKNOWN; 1012 return 0; 1013 } 1014 1015 if (prev_speed != phydev->speed) { 1016 /* Ensure that PHY switches to 1G speed when available, 1017 * by configuring the function mode for either 1G or 100M/10M 1018 * operation. 1019 * Therefore, set the link mode register, after read_status 1020 * determines the link speed. 1021 */ 1022 val = phydev->speed == SPEED_1000 ? 1023 AN8801_BPBUS_LINK_MODE_1000 : 0; 1024 1025 return an8801_buckpbus_reg_rmw(phydev, 1026 AN8801_BPBUS_REG_LINK_MODE, 1027 AN8801_BPBUS_LINK_MODE_1000, 1028 val); 1029 } 1030 1031 return 0; 1032 } 1033 1034 static int an8801r_probe(struct phy_device *phydev) 1035 { 1036 struct device *dev = &phydev->mdio.dev; 1037 struct an8801r_priv *priv; 1038 1039 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1040 if (!priv) 1041 return -ENOMEM; 1042 1043 priv->wake_lnkchg_enabled = true; 1044 1045 phydev->priv = priv; 1046 1047 /* Mark this PHY as wakeup capable and register the interrupt as a 1048 * wakeup IRQ if the PHY is marked as a wakeup source in devicetree, 1049 * and the interrupt is valid. 1050 */ 1051 if (of_property_read_bool(dev->of_node, "wakeup-source") && 1052 phy_interrupt_is_valid(phydev)) { 1053 device_set_wakeup_capable(dev, true); 1054 devm_pm_set_wake_irq(dev, phydev->irq); 1055 } 1056 1057 return 0; 1058 } 1059 1060 static int an8801r_suspend(struct phy_device *phydev) 1061 { 1062 struct an8801r_priv *priv = phydev->priv; 1063 int ret; 1064 1065 /* If the PHY may wake up by a Wake-on-LAN (WOL) event, disable the link 1066 * interrupt to only keep the WOL magic interrupt enabled 1067 */ 1068 if (device_may_wakeup(&phydev->mdio.dev)) { 1069 priv->wake_lnkchg_enabled = false; 1070 1071 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1072 ret = an8801_buckpbus_reg_clear_bits(phydev, 1073 AN8801_BPBUS_REG_WAKE_IRQ_EN, 1074 AN8801_IRQ_WAKE_LNKCHG); 1075 if (ret) 1076 return ret; 1077 } 1078 1079 /* Reset WOL status */ 1080 ret = an8801r_reset_wake(phydev); 1081 if (ret) 1082 return ret; 1083 } 1084 1085 if (!phydev->wol_enabled) 1086 return genphy_suspend(phydev); 1087 1088 return 0; 1089 } 1090 1091 static int an8801r_resume(struct phy_device *phydev) 1092 { 1093 struct an8801r_priv *priv = phydev->priv; 1094 int ret; 1095 1096 ret = genphy_resume(phydev); 1097 if (ret) 1098 return ret; 1099 1100 /* Restore the interrupt enable so phylib can receive link 1101 * state interrupts. 1102 */ 1103 if (device_may_wakeup(&phydev->mdio.dev)) { 1104 priv->wake_lnkchg_enabled = true; 1105 1106 ret = an8801_buckpbus_reg_set_bits(phydev, 1107 AN8801_BPBUS_REG_WAKEUP_CTL1, 1108 AN8801_WOL_WAKE_LNKCHG_EN); 1109 if (ret) 1110 return ret; 1111 1112 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1113 ret = an8801_buckpbus_reg_set_bits(phydev, 1114 AN8801_BPBUS_REG_WAKE_IRQ_EN, 1115 AN8801_IRQ_WAKE_LNKCHG); 1116 } 1117 } 1118 1119 return ret; 1120 } 1121 1122 static struct phy_driver airoha_driver[] = { 1123 { 1124 PHY_ID_MATCH_MODEL(AN8801R_PHY_ID), 1125 .name = "Airoha AN8801R", 1126 .probe = an8801r_probe, 1127 .config_init = an8801r_config_init, 1128 .suspend = an8801r_suspend, 1129 .resume = an8801r_resume, 1130 .config_aneg = genphy_config_aneg, 1131 .read_status = an8801r_read_status, 1132 .config_intr = an8801r_config_intr, 1133 .handle_interrupt = an8801r_handle_interrupt, 1134 .set_wol = an8801r_set_wol, 1135 .get_wol = an8801r_get_wol, 1136 .read_page = air_phy_read_page, 1137 .write_page = air_phy_write_page, 1138 .flags = PHY_ALWAYS_CALL_SUSPEND, 1139 .led_brightness_set = an8801r_led_brightness_set, 1140 .led_blink_set = an8801r_led_blink_set, 1141 .led_hw_is_supported = an8801r_led_hw_is_supported, 1142 .led_hw_control_set = an8801r_led_hw_control_set, 1143 .led_hw_control_get = an8801r_led_hw_control_get, 1144 .led_polarity_set = an8801r_led_polarity_set, 1145 } }; 1146 module_phy_driver(airoha_driver); 1147 1148 static struct mdio_device_id __maybe_unused an8801_tbl[] = { 1149 { PHY_ID_MATCH_MODEL(AN8801R_PHY_ID) }, 1150 { } 1151 }; 1152 MODULE_DEVICE_TABLE(mdio, an8801_tbl); 1153 1154 MODULE_DESCRIPTION("Airoha AN8801 PHY driver"); 1155 MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>"); 1156 MODULE_LICENSE("GPL"); 1157