1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2015 - 2025 Beijing WangXun Technology Co., Ltd. */ 3 /* Copyright (c) 1999 - 2025 Intel Corporation. */ 4 5 #include <linux/ptp_classify.h> 6 #include <linux/clocksource.h> 7 #include <linux/pci.h> 8 9 #include "wx_type.h" 10 #include "wx_ptp.h" 11 #include "wx_hw.h" 12 13 #define WX_INCVAL_10GB 0xCCCCCC 14 #define WX_INCVAL_1GB 0x800000 15 #define WX_INCVAL_100 0xA00000 16 #define WX_INCVAL_10 0xC7F380 17 #define WX_INCVAL_EM 0x2000000 18 #define WX_INCVAL_AML 0xA00000 19 20 #define WX_INCVAL_SHIFT_10GB 20 21 #define WX_INCVAL_SHIFT_1GB 18 22 #define WX_INCVAL_SHIFT_100 15 23 #define WX_INCVAL_SHIFT_10 12 24 #define WX_INCVAL_SHIFT_EM 22 25 #define WX_INCVAL_SHIFT_AML 21 26 27 #define WX_OVERFLOW_PERIOD (HZ * 30) 28 #define WX_PTP_TX_TIMEOUT (HZ) 29 30 #define WX_1588_PPS_WIDTH_EM 120 31 32 #define WX_NS_PER_SEC 1000000000ULL 33 34 static u64 wx_ptp_timecounter_cyc2time(struct wx *wx, u64 timestamp) 35 { 36 unsigned int seq; 37 u64 ns; 38 39 do { 40 seq = read_seqbegin(&wx->hw_tc_lock); 41 ns = timecounter_cyc2time(&wx->hw_tc, timestamp); 42 } while (read_seqretry(&wx->hw_tc_lock, seq)); 43 44 return ns; 45 } 46 47 static u64 wx_ptp_readtime(struct wx *wx, struct ptp_system_timestamp *sts) 48 { 49 u32 timeh1, timeh2, timel; 50 51 timeh1 = rd32ptp(wx, WX_TSC_1588_SYSTIMH); 52 ptp_read_system_prets(sts); 53 timel = rd32ptp(wx, WX_TSC_1588_SYSTIML); 54 ptp_read_system_postts(sts); 55 timeh2 = rd32ptp(wx, WX_TSC_1588_SYSTIMH); 56 57 if (timeh1 != timeh2) { 58 ptp_read_system_prets(sts); 59 timel = rd32ptp(wx, WX_TSC_1588_SYSTIML); 60 ptp_read_system_prets(sts); 61 } 62 return (u64)timel | (u64)timeh2 << 32; 63 } 64 65 static int wx_ptp_adjfine(struct ptp_clock_info *ptp, long ppb) 66 { 67 struct wx *wx = container_of(ptp, struct wx, ptp_caps); 68 u64 incval, mask; 69 70 smp_mb(); /* Force any pending update before accessing. */ 71 incval = READ_ONCE(wx->base_incval); 72 incval = adjust_by_scaled_ppm(incval, ppb); 73 74 mask = (wx->mac.type == wx_mac_em) ? 0x7FFFFFF : 0xFFFFFF; 75 incval &= mask; 76 if (wx->mac.type != wx_mac_em) 77 incval |= 2 << 24; 78 79 wr32ptp(wx, WX_TSC_1588_INC, incval); 80 81 return 0; 82 } 83 84 static int wx_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 85 { 86 struct wx *wx = container_of(ptp, struct wx, ptp_caps); 87 unsigned long flags; 88 89 write_seqlock_irqsave(&wx->hw_tc_lock, flags); 90 timecounter_adjtime(&wx->hw_tc, delta); 91 write_sequnlock_irqrestore(&wx->hw_tc_lock, flags); 92 93 if (wx->ptp_setup_sdp) 94 wx->ptp_setup_sdp(wx); 95 96 return 0; 97 } 98 99 static int wx_ptp_gettimex64(struct ptp_clock_info *ptp, 100 struct timespec64 *ts, 101 struct ptp_system_timestamp *sts) 102 { 103 struct wx *wx = container_of(ptp, struct wx, ptp_caps); 104 u64 ns, stamp; 105 106 stamp = wx_ptp_readtime(wx, sts); 107 ns = wx_ptp_timecounter_cyc2time(wx, stamp); 108 *ts = ns_to_timespec64(ns); 109 110 return 0; 111 } 112 113 static int wx_ptp_settime64(struct ptp_clock_info *ptp, 114 const struct timespec64 *ts) 115 { 116 struct wx *wx = container_of(ptp, struct wx, ptp_caps); 117 unsigned long flags; 118 u64 ns; 119 120 ns = timespec64_to_ns(ts); 121 /* reset the timecounter */ 122 write_seqlock_irqsave(&wx->hw_tc_lock, flags); 123 timecounter_init(&wx->hw_tc, &wx->hw_cc, ns); 124 write_sequnlock_irqrestore(&wx->hw_tc_lock, flags); 125 126 if (wx->ptp_setup_sdp) 127 wx->ptp_setup_sdp(wx); 128 129 return 0; 130 } 131 132 /** 133 * wx_ptp_clear_tx_timestamp - utility function to clear Tx timestamp state 134 * @wx: the private board structure 135 * 136 * This function should be called whenever the state related to a Tx timestamp 137 * needs to be cleared. This helps ensure that all related bits are reset for 138 * the next Tx timestamp event. 139 */ 140 static void wx_ptp_clear_tx_timestamp(struct wx *wx) 141 { 142 rd32ptp(wx, WX_TSC_1588_STMPH); 143 if (wx->ptp_tx_skb) { 144 dev_kfree_skb_any(wx->ptp_tx_skb); 145 wx->ptp_tx_skb = NULL; 146 } 147 clear_bit_unlock(WX_STATE_PTP_TX_IN_PROGRESS, wx->state); 148 } 149 150 /** 151 * wx_ptp_convert_to_hwtstamp - convert register value to hw timestamp 152 * @wx: private board structure 153 * @hwtstamp: stack timestamp structure 154 * @timestamp: unsigned 64bit system time value 155 * 156 * We need to convert the adapter's RX/TXSTMP registers into a hwtstamp value 157 * which can be used by the stack's ptp functions. 158 * 159 * The lock is used to protect consistency of the cyclecounter and the SYSTIME 160 * registers. However, it does not need to protect against the Rx or Tx 161 * timestamp registers, as there can't be a new timestamp until the old one is 162 * unlatched by reading. 163 * 164 * In addition to the timestamp in hardware, some controllers need a software 165 * overflow cyclecounter, and this function takes this into account as well. 166 **/ 167 static void wx_ptp_convert_to_hwtstamp(struct wx *wx, 168 struct skb_shared_hwtstamps *hwtstamp, 169 u64 timestamp) 170 { 171 u64 ns; 172 173 ns = wx_ptp_timecounter_cyc2time(wx, timestamp); 174 hwtstamp->hwtstamp = ns_to_ktime(ns); 175 } 176 177 /** 178 * wx_ptp_tx_hwtstamp - utility function which checks for TX time stamp 179 * @wx: the private board struct 180 * 181 * if the timestamp is valid, we convert it into the timecounter ns 182 * value, then store that result into the shhwtstamps structure which 183 * is passed up the network stack 184 */ 185 static void wx_ptp_tx_hwtstamp(struct wx *wx) 186 { 187 struct skb_shared_hwtstamps shhwtstamps; 188 struct sk_buff *skb = wx->ptp_tx_skb; 189 u64 regval = 0; 190 191 regval |= (u64)rd32ptp(wx, WX_TSC_1588_STMPL); 192 regval |= (u64)rd32ptp(wx, WX_TSC_1588_STMPH) << 32; 193 194 wx_ptp_convert_to_hwtstamp(wx, &shhwtstamps, regval); 195 196 wx->ptp_tx_skb = NULL; 197 clear_bit_unlock(WX_STATE_PTP_TX_IN_PROGRESS, wx->state); 198 skb_tstamp_tx(skb, &shhwtstamps); 199 dev_kfree_skb_any(skb); 200 wx->tx_hwtstamp_pkts++; 201 } 202 203 static int wx_ptp_tx_hwtstamp_work(struct wx *wx) 204 { 205 u32 tsynctxctl; 206 207 /* we have to have a valid skb to poll for a timestamp */ 208 if (!wx->ptp_tx_skb) { 209 wx_ptp_clear_tx_timestamp(wx); 210 return 0; 211 } 212 213 /* stop polling once we have a valid timestamp */ 214 tsynctxctl = rd32ptp(wx, WX_TSC_1588_CTL); 215 if (tsynctxctl & WX_TSC_1588_CTL_VALID) { 216 wx_ptp_tx_hwtstamp(wx); 217 return 0; 218 } 219 220 return -1; 221 } 222 223 /** 224 * wx_ptp_overflow_check - watchdog task to detect SYSTIME overflow 225 * @wx: pointer to wx struct 226 * 227 * this watchdog task periodically reads the timecounter 228 * in order to prevent missing when the system time registers wrap 229 * around. This needs to be run approximately twice a minute for the fastest 230 * overflowing hardware. We run it for all hardware since it shouldn't have a 231 * large impact. 232 */ 233 static void wx_ptp_overflow_check(struct wx *wx) 234 { 235 bool timeout = time_is_before_jiffies(wx->last_overflow_check + 236 WX_OVERFLOW_PERIOD); 237 unsigned long flags; 238 239 if (timeout) { 240 /* Update the timecounter */ 241 write_seqlock_irqsave(&wx->hw_tc_lock, flags); 242 timecounter_read(&wx->hw_tc); 243 write_sequnlock_irqrestore(&wx->hw_tc_lock, flags); 244 245 wx->last_overflow_check = jiffies; 246 } 247 } 248 249 /** 250 * wx_ptp_rx_hang - detect error case when Rx timestamp registers latched 251 * @wx: pointer to wx struct 252 * 253 * this watchdog task is scheduled to detect error case where hardware has 254 * dropped an Rx packet that was timestamped when the ring is full. The 255 * particular error is rare but leaves the device in a state unable to 256 * timestamp any future packets. 257 */ 258 static void wx_ptp_rx_hang(struct wx *wx) 259 { 260 struct wx_ring *rx_ring; 261 unsigned long rx_event; 262 u32 tsyncrxctl; 263 int n; 264 265 tsyncrxctl = rd32(wx, WX_PSR_1588_CTL); 266 267 /* if we don't have a valid timestamp in the registers, just update the 268 * timeout counter and exit 269 */ 270 if (!(tsyncrxctl & WX_PSR_1588_CTL_VALID)) { 271 wx->last_rx_ptp_check = jiffies; 272 return; 273 } 274 275 /* determine the most recent watchdog or rx_timestamp event */ 276 rx_event = wx->last_rx_ptp_check; 277 for (n = 0; n < wx->num_rx_queues; n++) { 278 rx_ring = wx->rx_ring[n]; 279 if (time_after(rx_ring->last_rx_timestamp, rx_event)) 280 rx_event = rx_ring->last_rx_timestamp; 281 } 282 283 /* only need to read the high RXSTMP register to clear the lock */ 284 if (time_is_before_jiffies(rx_event + 5 * HZ)) { 285 rd32(wx, WX_PSR_1588_STMPH); 286 wx->last_rx_ptp_check = jiffies; 287 288 wx->rx_hwtstamp_cleared++; 289 dev_warn(&wx->pdev->dev, "clearing RX Timestamp hang"); 290 } 291 } 292 293 /** 294 * wx_ptp_tx_hang - detect error case where Tx timestamp never finishes 295 * @wx: private network wx structure 296 */ 297 static void wx_ptp_tx_hang(struct wx *wx) 298 { 299 bool timeout = time_is_before_jiffies(wx->ptp_tx_start + 300 WX_PTP_TX_TIMEOUT); 301 302 if (!wx->ptp_tx_skb) 303 return; 304 305 if (!test_bit(WX_STATE_PTP_TX_IN_PROGRESS, wx->state)) 306 return; 307 308 /* If we haven't received a timestamp within the timeout, it is 309 * reasonable to assume that it will never occur, so we can unlock the 310 * timestamp bit when this occurs. 311 */ 312 if (timeout) { 313 wx_ptp_clear_tx_timestamp(wx); 314 wx->tx_hwtstamp_timeouts++; 315 dev_warn(&wx->pdev->dev, "clearing Tx timestamp hang\n"); 316 } 317 } 318 319 static long wx_ptp_do_aux_work(struct ptp_clock_info *ptp) 320 { 321 struct wx *wx = container_of(ptp, struct wx, ptp_caps); 322 int ts_done; 323 324 ts_done = wx_ptp_tx_hwtstamp_work(wx); 325 326 wx_ptp_overflow_check(wx); 327 if (unlikely(test_bit(WX_FLAG_RX_HWTSTAMP_IN_REGISTER, 328 wx->flags))) 329 wx_ptp_rx_hang(wx); 330 wx_ptp_tx_hang(wx); 331 332 return ts_done ? 1 : HZ; 333 } 334 335 static u64 wx_ptp_trigger_calc(struct wx *wx) 336 { 337 struct cyclecounter *cc = &wx->hw_cc; 338 unsigned long flags; 339 u64 ns = 0; 340 u32 rem; 341 342 /* Read the current clock time, and save the cycle counter value */ 343 write_seqlock_irqsave(&wx->hw_tc_lock, flags); 344 ns = timecounter_read(&wx->hw_tc); 345 wx->pps_edge_start = wx->hw_tc.cycle_last; 346 write_sequnlock_irqrestore(&wx->hw_tc_lock, flags); 347 wx->pps_edge_end = wx->pps_edge_start; 348 349 /* Figure out how far past the next second we are */ 350 div_u64_rem(ns, WX_NS_PER_SEC, &rem); 351 352 /* Figure out how many nanoseconds to add to round the clock edge up 353 * to the next full second 354 */ 355 rem = (WX_NS_PER_SEC - rem); 356 357 /* Adjust the clock edge to align with the next full second. */ 358 wx->pps_edge_start += div_u64(((u64)rem << cc->shift), cc->mult); 359 wx->pps_edge_end += div_u64(((u64)(rem + wx->pps_width) << 360 cc->shift), cc->mult); 361 362 return (ns + rem); 363 } 364 365 static int wx_ptp_setup_sdp(struct wx *wx) 366 { 367 struct cyclecounter *cc = &wx->hw_cc; 368 u32 tsauxc; 369 u64 nsec; 370 371 if (wx->pps_width >= WX_NS_PER_SEC) { 372 wx_err(wx, "PTP pps width cannot be longer than 1s!\n"); 373 return -EINVAL; 374 } 375 376 /* disable the pin first */ 377 wr32ptp(wx, WX_TSC_1588_AUX_CTL, 0); 378 WX_WRITE_FLUSH(wx); 379 380 if (!test_bit(WX_FLAG_PTP_PPS_ENABLED, wx->flags)) { 381 if (wx->pps_enabled) { 382 wx->pps_enabled = false; 383 wx_set_pps(wx, false, 0, 0); 384 } 385 return 0; 386 } 387 388 wx->pps_enabled = true; 389 nsec = wx_ptp_trigger_calc(wx); 390 wx_set_pps(wx, wx->pps_enabled, nsec, wx->pps_edge_start); 391 392 tsauxc = WX_TSC_1588_AUX_CTL_PLSG | WX_TSC_1588_AUX_CTL_EN_TT0 | 393 WX_TSC_1588_AUX_CTL_EN_TT1 | WX_TSC_1588_AUX_CTL_EN_TS0; 394 wr32ptp(wx, WX_TSC_1588_TRGT_L(0), (u32)wx->pps_edge_start); 395 wr32ptp(wx, WX_TSC_1588_TRGT_H(0), (u32)(wx->pps_edge_start >> 32)); 396 wr32ptp(wx, WX_TSC_1588_TRGT_L(1), (u32)wx->pps_edge_end); 397 wr32ptp(wx, WX_TSC_1588_TRGT_H(1), (u32)(wx->pps_edge_end >> 32)); 398 wr32ptp(wx, WX_TSC_1588_SDP(0), 399 WX_TSC_1588_SDP_FUN_SEL_TT0 | WX_TSC_1588_SDP_OUT_LEVEL_H); 400 wr32ptp(wx, WX_TSC_1588_SDP(1), WX_TSC_1588_SDP_FUN_SEL_TS0); 401 wr32ptp(wx, WX_TSC_1588_AUX_CTL, tsauxc); 402 wr32ptp(wx, WX_TSC_1588_INT_EN, WX_TSC_1588_INT_EN_TT1); 403 WX_WRITE_FLUSH(wx); 404 405 /* Adjust the clock edge to align with the next full second. */ 406 wx->sec_to_cc = div_u64(((u64)WX_NS_PER_SEC << cc->shift), cc->mult); 407 408 return 0; 409 } 410 411 static int wx_ptp_feature_enable(struct ptp_clock_info *ptp, 412 struct ptp_clock_request *rq, int on) 413 { 414 struct wx *wx = container_of(ptp, struct wx, ptp_caps); 415 416 /** 417 * When PPS is enabled, unmask the interrupt for the ClockOut 418 * feature, so that the interrupt handler can send the PPS 419 * event when the clock SDP triggers. Clear mask when PPS is 420 * disabled 421 */ 422 if (rq->type != PTP_CLK_REQ_PEROUT || !wx->ptp_setup_sdp) 423 return -EOPNOTSUPP; 424 425 /* Reject requests with unsupported flags */ 426 if (rq->perout.flags & ~(PTP_PEROUT_DUTY_CYCLE | 427 PTP_PEROUT_PHASE)) 428 return -EOPNOTSUPP; 429 430 if (rq->perout.phase.sec || rq->perout.phase.nsec) { 431 wx_err(wx, "Absolute start time not supported.\n"); 432 return -EINVAL; 433 } 434 435 if (rq->perout.period.sec != 1 || rq->perout.period.nsec) { 436 wx_err(wx, "Only 1pps is supported.\n"); 437 return -EINVAL; 438 } 439 440 if (rq->perout.flags & PTP_PEROUT_DUTY_CYCLE) { 441 struct timespec64 ts_on; 442 443 ts_on.tv_sec = rq->perout.on.sec; 444 ts_on.tv_nsec = rq->perout.on.nsec; 445 wx->pps_width = timespec64_to_ns(&ts_on); 446 } else { 447 wx->pps_width = 120000000; 448 } 449 450 if (on) 451 set_bit(WX_FLAG_PTP_PPS_ENABLED, wx->flags); 452 else 453 clear_bit(WX_FLAG_PTP_PPS_ENABLED, wx->flags); 454 455 return wx->ptp_setup_sdp(wx); 456 } 457 458 void wx_ptp_check_pps_event(struct wx *wx) 459 { 460 u32 tsauxc, int_status; 461 462 /* this check is necessary in case the interrupt was enabled via some 463 * alternative means (ex. debug_fs). Better to check here than 464 * everywhere that calls this function. 465 */ 466 if (!wx->ptp_clock) 467 return; 468 469 int_status = rd32ptp(wx, WX_TSC_1588_INT_ST); 470 if (int_status & WX_TSC_1588_INT_ST_TT1) { 471 /* disable the pin first */ 472 wr32ptp(wx, WX_TSC_1588_AUX_CTL, 0); 473 WX_WRITE_FLUSH(wx); 474 475 wx_ptp_trigger_calc(wx); 476 477 tsauxc = WX_TSC_1588_AUX_CTL_PLSG | WX_TSC_1588_AUX_CTL_EN_TT0 | 478 WX_TSC_1588_AUX_CTL_EN_TT1 | WX_TSC_1588_AUX_CTL_EN_TS0; 479 wr32ptp(wx, WX_TSC_1588_TRGT_L(0), (u32)wx->pps_edge_start); 480 wr32ptp(wx, WX_TSC_1588_TRGT_H(0), (u32)(wx->pps_edge_start >> 32)); 481 wr32ptp(wx, WX_TSC_1588_TRGT_L(1), (u32)wx->pps_edge_end); 482 wr32ptp(wx, WX_TSC_1588_TRGT_H(1), (u32)(wx->pps_edge_end >> 32)); 483 wr32ptp(wx, WX_TSC_1588_AUX_CTL, tsauxc); 484 WX_WRITE_FLUSH(wx); 485 } 486 } 487 EXPORT_SYMBOL(wx_ptp_check_pps_event); 488 489 static long wx_ptp_create_clock(struct wx *wx) 490 { 491 struct net_device *netdev = wx->netdev; 492 long err; 493 494 /* do nothing if we already have a clock device */ 495 if (!IS_ERR_OR_NULL(wx->ptp_clock)) 496 return 0; 497 498 snprintf(wx->ptp_caps.name, sizeof(wx->ptp_caps.name), 499 "%s", netdev->name); 500 wx->ptp_caps.owner = THIS_MODULE; 501 wx->ptp_caps.n_alarm = 0; 502 wx->ptp_caps.n_ext_ts = 0; 503 wx->ptp_caps.pps = 0; 504 wx->ptp_caps.adjfine = wx_ptp_adjfine; 505 wx->ptp_caps.adjtime = wx_ptp_adjtime; 506 wx->ptp_caps.gettimex64 = wx_ptp_gettimex64; 507 wx->ptp_caps.settime64 = wx_ptp_settime64; 508 wx->ptp_caps.do_aux_work = wx_ptp_do_aux_work; 509 switch (wx->mac.type) { 510 case wx_mac_aml: 511 case wx_mac_aml40: 512 wx->ptp_caps.max_adj = 250000000; 513 wx->ptp_caps.n_per_out = 1; 514 wx->ptp_setup_sdp = wx_ptp_setup_sdp; 515 wx->ptp_caps.enable = wx_ptp_feature_enable; 516 break; 517 case wx_mac_sp: 518 wx->ptp_caps.max_adj = 250000000; 519 wx->ptp_caps.n_per_out = 0; 520 wx->ptp_setup_sdp = NULL; 521 break; 522 case wx_mac_em: 523 wx->ptp_caps.max_adj = 500000000; 524 wx->ptp_caps.n_per_out = 1; 525 wx->ptp_setup_sdp = wx_ptp_setup_sdp; 526 wx->ptp_caps.enable = wx_ptp_feature_enable; 527 break; 528 default: 529 return -EOPNOTSUPP; 530 } 531 532 wx->ptp_clock = ptp_clock_register(&wx->ptp_caps, &wx->pdev->dev); 533 if (IS_ERR(wx->ptp_clock)) { 534 err = PTR_ERR(wx->ptp_clock); 535 wx->ptp_clock = NULL; 536 wx_err(wx, "ptp clock register failed\n"); 537 return err; 538 } else if (wx->ptp_clock) { 539 dev_info(&wx->pdev->dev, "registered PHC device on %s\n", 540 netdev->name); 541 } 542 543 /* Set the default timestamp mode to disabled here. We do this in 544 * create_clock instead of initialization, because we don't want to 545 * override the previous settings during a suspend/resume cycle. 546 */ 547 wx->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; 548 wx->tstamp_config.tx_type = HWTSTAMP_TX_OFF; 549 550 return 0; 551 } 552 553 static int wx_ptp_set_timestamp_mode(struct wx *wx, 554 struct kernel_hwtstamp_config *config) 555 { 556 u32 tsync_tx_ctl = WX_TSC_1588_CTL_ENABLED; 557 u32 tsync_rx_ctl = WX_PSR_1588_CTL_ENABLED; 558 DECLARE_BITMAP(flags, WX_PF_FLAGS_NBITS); 559 u32 tsync_rx_mtrl = PTP_EV_PORT << 16; 560 bool is_l2 = false; 561 u32 regval; 562 563 memcpy(flags, wx->flags, sizeof(wx->flags)); 564 565 switch (config->tx_type) { 566 case HWTSTAMP_TX_OFF: 567 tsync_tx_ctl = 0; 568 break; 569 case HWTSTAMP_TX_ON: 570 break; 571 default: 572 return -ERANGE; 573 } 574 575 switch (config->rx_filter) { 576 case HWTSTAMP_FILTER_NONE: 577 tsync_rx_ctl = 0; 578 tsync_rx_mtrl = 0; 579 clear_bit(WX_FLAG_RX_HWTSTAMP_ENABLED, flags); 580 clear_bit(WX_FLAG_RX_HWTSTAMP_IN_REGISTER, flags); 581 break; 582 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 583 tsync_rx_ctl |= WX_PSR_1588_CTL_TYPE_L4_V1; 584 tsync_rx_mtrl |= WX_PSR_1588_MSG_V1_SYNC; 585 set_bit(WX_FLAG_RX_HWTSTAMP_ENABLED, flags); 586 set_bit(WX_FLAG_RX_HWTSTAMP_IN_REGISTER, flags); 587 break; 588 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 589 tsync_rx_ctl |= WX_PSR_1588_CTL_TYPE_L4_V1; 590 tsync_rx_mtrl |= WX_PSR_1588_MSG_V1_DELAY_REQ; 591 set_bit(WX_FLAG_RX_HWTSTAMP_ENABLED, flags); 592 set_bit(WX_FLAG_RX_HWTSTAMP_IN_REGISTER, flags); 593 break; 594 case HWTSTAMP_FILTER_PTP_V2_EVENT: 595 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 596 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 597 case HWTSTAMP_FILTER_PTP_V2_SYNC: 598 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 599 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 600 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 601 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 602 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 603 tsync_rx_ctl |= WX_PSR_1588_CTL_TYPE_EVENT_V2; 604 is_l2 = true; 605 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 606 set_bit(WX_FLAG_RX_HWTSTAMP_ENABLED, flags); 607 set_bit(WX_FLAG_RX_HWTSTAMP_IN_REGISTER, flags); 608 break; 609 default: 610 /* register PSR_1588_MSG must be set in order to do V1 packets, 611 * therefore it is not possible to time stamp both V1 Sync and 612 * Delay_Req messages unless hardware supports timestamping all 613 * packets => return error 614 */ 615 config->rx_filter = HWTSTAMP_FILTER_NONE; 616 return -ERANGE; 617 } 618 619 /* define ethertype filter for timestamping L2 packets */ 620 if (is_l2) 621 wr32(wx, WX_PSR_ETYPE_SWC(WX_PSR_ETYPE_SWC_FILTER_1588), 622 (WX_PSR_ETYPE_SWC_FILTER_EN | /* enable filter */ 623 WX_PSR_ETYPE_SWC_1588 | /* enable timestamping */ 624 ETH_P_1588)); /* 1588 eth protocol type */ 625 else 626 wr32(wx, WX_PSR_ETYPE_SWC(WX_PSR_ETYPE_SWC_FILTER_1588), 0); 627 628 /* enable/disable TX */ 629 regval = rd32ptp(wx, WX_TSC_1588_CTL); 630 regval &= ~WX_TSC_1588_CTL_ENABLED; 631 regval |= tsync_tx_ctl; 632 wr32ptp(wx, WX_TSC_1588_CTL, regval); 633 634 /* enable/disable RX */ 635 regval = rd32(wx, WX_PSR_1588_CTL); 636 regval &= ~(WX_PSR_1588_CTL_ENABLED | WX_PSR_1588_CTL_TYPE_MASK); 637 regval |= tsync_rx_ctl; 638 wr32(wx, WX_PSR_1588_CTL, regval); 639 640 /* define which PTP packets are time stamped */ 641 wr32(wx, WX_PSR_1588_MSG, tsync_rx_mtrl); 642 643 WX_WRITE_FLUSH(wx); 644 645 /* configure adapter flags only when HW is actually configured */ 646 memcpy(wx->flags, flags, sizeof(wx->flags)); 647 648 /* clear TX/RX timestamp state, just to be sure */ 649 wx_ptp_clear_tx_timestamp(wx); 650 rd32(wx, WX_PSR_1588_STMPH); 651 652 return 0; 653 } 654 655 static u64 wx_ptp_read(struct cyclecounter *hw_cc) 656 { 657 struct wx *wx = container_of(hw_cc, struct wx, hw_cc); 658 659 return wx_ptp_readtime(wx, NULL); 660 } 661 662 static void wx_ptp_link_speed_adjust(struct wx *wx, u32 *shift, u32 *incval) 663 { 664 switch (wx->mac.type) { 665 case wx_mac_aml: 666 case wx_mac_aml40: 667 *shift = WX_INCVAL_SHIFT_AML; 668 *incval = WX_INCVAL_AML; 669 return; 670 case wx_mac_em: 671 *shift = WX_INCVAL_SHIFT_EM; 672 *incval = WX_INCVAL_EM; 673 return; 674 default: 675 break; 676 } 677 678 switch (wx->speed) { 679 case SPEED_10: 680 *shift = WX_INCVAL_SHIFT_10; 681 *incval = WX_INCVAL_10; 682 break; 683 case SPEED_100: 684 *shift = WX_INCVAL_SHIFT_100; 685 *incval = WX_INCVAL_100; 686 break; 687 case SPEED_1000: 688 *shift = WX_INCVAL_SHIFT_1GB; 689 *incval = WX_INCVAL_1GB; 690 break; 691 case SPEED_10000: 692 default: 693 *shift = WX_INCVAL_SHIFT_10GB; 694 *incval = WX_INCVAL_10GB; 695 break; 696 } 697 } 698 699 /** 700 * wx_ptp_reset_cyclecounter - create the cycle counter from hw 701 * @wx: pointer to the wx structure 702 * 703 * This function should be called to set the proper values for the TSC_1588_INC 704 * register and tell the cyclecounter structure what the tick rate of SYSTIME 705 * is. It does not directly modify SYSTIME registers or the timecounter 706 * structure. It should be called whenever a new TSC_1588_INC value is 707 * necessary, such as during initialization or when the link speed changes. 708 */ 709 void wx_ptp_reset_cyclecounter(struct wx *wx) 710 { 711 u32 incval = 0, mask = 0; 712 struct cyclecounter cc; 713 unsigned long flags; 714 715 /* For some of the boards below this mask is technically incorrect. 716 * The timestamp mask overflows at approximately 61bits. However the 717 * particular hardware does not overflow on an even bitmask value. 718 * Instead, it overflows due to conversion of upper 32bits billions of 719 * cycles. Timecounters are not really intended for this purpose so 720 * they do not properly function if the overflow point isn't 2^N-1. 721 * However, the actual SYSTIME values in question take ~138 years to 722 * overflow. In practice this means they won't actually overflow. A 723 * proper fix to this problem would require modification of the 724 * timecounter delta calculations. 725 */ 726 cc.mask = CLOCKSOURCE_MASK(64); 727 cc.mult = 1; 728 cc.shift = 0; 729 730 cc.read = wx_ptp_read; 731 wx_ptp_link_speed_adjust(wx, &cc.shift, &incval); 732 733 /* update the base incval used to calculate frequency adjustment */ 734 WRITE_ONCE(wx->base_incval, incval); 735 736 mask = (wx->mac.type == wx_mac_em) ? 0x7FFFFFF : 0xFFFFFF; 737 incval &= mask; 738 if (wx->mac.type != wx_mac_em) 739 incval |= 2 << 24; 740 wr32ptp(wx, WX_TSC_1588_INC, incval); 741 742 smp_mb(); /* Force the above update. */ 743 744 /* need lock to prevent incorrect read while modifying cyclecounter */ 745 write_seqlock_irqsave(&wx->hw_tc_lock, flags); 746 memcpy(&wx->hw_cc, &cc, sizeof(wx->hw_cc)); 747 write_sequnlock_irqrestore(&wx->hw_tc_lock, flags); 748 } 749 EXPORT_SYMBOL(wx_ptp_reset_cyclecounter); 750 751 void wx_ptp_reset(struct wx *wx) 752 { 753 unsigned long flags; 754 755 /* reset the hardware timestamping mode */ 756 wx_ptp_set_timestamp_mode(wx, &wx->tstamp_config); 757 wx_ptp_reset_cyclecounter(wx); 758 759 wr32ptp(wx, WX_TSC_1588_SYSTIML, 0); 760 wr32ptp(wx, WX_TSC_1588_SYSTIMH, 0); 761 WX_WRITE_FLUSH(wx); 762 763 write_seqlock_irqsave(&wx->hw_tc_lock, flags); 764 timecounter_init(&wx->hw_tc, &wx->hw_cc, 765 ktime_to_ns(ktime_get_real())); 766 write_sequnlock_irqrestore(&wx->hw_tc_lock, flags); 767 768 wx->last_overflow_check = jiffies; 769 ptp_schedule_worker(wx->ptp_clock, HZ); 770 771 /* Now that the shift has been calculated and the systime 772 * registers reset, (re-)enable the Clock out feature 773 */ 774 if (wx->ptp_setup_sdp) 775 wx->ptp_setup_sdp(wx); 776 } 777 EXPORT_SYMBOL(wx_ptp_reset); 778 779 void wx_ptp_init(struct wx *wx) 780 { 781 /* Initialize the seqlock_t first, since the user might call the clock 782 * functions any time after we've initialized the ptp clock device. 783 */ 784 seqlock_init(&wx->hw_tc_lock); 785 786 /* obtain a ptp clock device, or re-use an existing device */ 787 if (wx_ptp_create_clock(wx)) 788 return; 789 790 wx->tx_hwtstamp_pkts = 0; 791 wx->tx_hwtstamp_timeouts = 0; 792 wx->tx_hwtstamp_skipped = 0; 793 wx->tx_hwtstamp_errors = 0; 794 wx->rx_hwtstamp_cleared = 0; 795 /* reset the ptp related hardware bits */ 796 wx_ptp_reset(wx); 797 798 /* enter the WX_STATE_PTP_RUNNING state */ 799 set_bit(WX_STATE_PTP_RUNNING, wx->state); 800 } 801 EXPORT_SYMBOL(wx_ptp_init); 802 803 /** 804 * wx_ptp_suspend - stop ptp work items 805 * @wx: pointer to wx struct 806 * 807 * This function suspends ptp activity, and prevents more work from being 808 * generated, but does not destroy the clock device. 809 */ 810 void wx_ptp_suspend(struct wx *wx) 811 { 812 /* leave the WX_STATE_PTP_RUNNING STATE */ 813 if (!test_and_clear_bit(WX_STATE_PTP_RUNNING, wx->state)) 814 return; 815 816 clear_bit(WX_FLAG_PTP_PPS_ENABLED, wx->flags); 817 if (wx->ptp_setup_sdp) 818 wx->ptp_setup_sdp(wx); 819 820 wx_ptp_clear_tx_timestamp(wx); 821 } 822 EXPORT_SYMBOL(wx_ptp_suspend); 823 824 /** 825 * wx_ptp_stop - destroy the ptp_clock device 826 * @wx: pointer to wx struct 827 * 828 * Completely destroy the ptp_clock device, and disable all PTP related 829 * features. Intended to be run when the device is being closed. 830 */ 831 void wx_ptp_stop(struct wx *wx) 832 { 833 /* first, suspend ptp activity */ 834 wx_ptp_suspend(wx); 835 836 /* now destroy the ptp clock device */ 837 if (wx->ptp_clock) { 838 ptp_clock_unregister(wx->ptp_clock); 839 wx->ptp_clock = NULL; 840 dev_info(&wx->pdev->dev, "removed PHC on %s\n", wx->netdev->name); 841 } 842 } 843 EXPORT_SYMBOL(wx_ptp_stop); 844 845 /** 846 * wx_ptp_rx_hwtstamp - utility function which checks for RX time stamp 847 * @wx: pointer to wx struct 848 * @skb: particular skb to send timestamp with 849 * 850 * if the timestamp is valid, we convert it into the timecounter ns 851 * value, then store that result into the shhwtstamps structure which 852 * is passed up the network stack 853 */ 854 void wx_ptp_rx_hwtstamp(struct wx *wx, struct sk_buff *skb) 855 { 856 u64 regval = 0; 857 u32 tsyncrxctl; 858 859 /* Read the tsyncrxctl register afterwards in order to prevent taking an 860 * I/O hit on every packet. 861 */ 862 tsyncrxctl = rd32(wx, WX_PSR_1588_CTL); 863 if (!(tsyncrxctl & WX_PSR_1588_CTL_VALID)) 864 return; 865 866 regval |= (u64)rd32(wx, WX_PSR_1588_STMPL); 867 regval |= (u64)rd32(wx, WX_PSR_1588_STMPH) << 32; 868 869 wx_ptp_convert_to_hwtstamp(wx, skb_hwtstamps(skb), regval); 870 } 871 872 int wx_hwtstamp_get(struct net_device *dev, 873 struct kernel_hwtstamp_config *cfg) 874 { 875 struct wx *wx = netdev_priv(dev); 876 877 if (!netif_running(dev)) 878 return -EINVAL; 879 880 *cfg = wx->tstamp_config; 881 882 return 0; 883 } 884 EXPORT_SYMBOL(wx_hwtstamp_get); 885 886 int wx_hwtstamp_set(struct net_device *dev, 887 struct kernel_hwtstamp_config *cfg, 888 struct netlink_ext_ack *extack) 889 { 890 struct wx *wx = netdev_priv(dev); 891 int err; 892 893 if (!netif_running(dev)) 894 return -EINVAL; 895 896 err = wx_ptp_set_timestamp_mode(wx, cfg); 897 if (err) 898 return err; 899 900 /* save these settings for future reference */ 901 memcpy(&wx->tstamp_config, cfg, sizeof(wx->tstamp_config)); 902 903 return 0; 904 } 905 EXPORT_SYMBOL(wx_hwtstamp_set); 906