1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2015 - 2025 Beijing WangXun Technology Co., Ltd. */ 3 /* Copyright (c) 1999 - 2025 Intel Corporation. */ 4 5 #include <linux/ptp_classify.h> 6 #include <linux/clocksource.h> 7 #include <linux/pci.h> 8 9 #include "wx_type.h" 10 #include "wx_ptp.h" 11 #include "wx_hw.h" 12 13 #define WX_INCVAL_10GB 0xCCCCCC 14 #define WX_INCVAL_1GB 0x800000 15 #define WX_INCVAL_100 0xA00000 16 #define WX_INCVAL_10 0xC7F380 17 #define WX_INCVAL_EM 0x2000000 18 19 #define WX_INCVAL_SHIFT_10GB 20 20 #define WX_INCVAL_SHIFT_1GB 18 21 #define WX_INCVAL_SHIFT_100 15 22 #define WX_INCVAL_SHIFT_10 12 23 #define WX_INCVAL_SHIFT_EM 22 24 25 #define WX_OVERFLOW_PERIOD (HZ * 30) 26 #define WX_PTP_TX_TIMEOUT (HZ) 27 28 #define WX_1588_PPS_WIDTH_EM 120 29 30 #define WX_NS_PER_SEC 1000000000ULL 31 32 static u64 wx_ptp_timecounter_cyc2time(struct wx *wx, u64 timestamp) 33 { 34 unsigned int seq; 35 u64 ns; 36 37 do { 38 seq = read_seqbegin(&wx->hw_tc_lock); 39 ns = timecounter_cyc2time(&wx->hw_tc, timestamp); 40 } while (read_seqretry(&wx->hw_tc_lock, seq)); 41 42 return ns; 43 } 44 45 static u64 wx_ptp_readtime(struct wx *wx, struct ptp_system_timestamp *sts) 46 { 47 u32 timeh1, timeh2, timel; 48 49 timeh1 = rd32ptp(wx, WX_TSC_1588_SYSTIMH); 50 ptp_read_system_prets(sts); 51 timel = rd32ptp(wx, WX_TSC_1588_SYSTIML); 52 ptp_read_system_postts(sts); 53 timeh2 = rd32ptp(wx, WX_TSC_1588_SYSTIMH); 54 55 if (timeh1 != timeh2) { 56 ptp_read_system_prets(sts); 57 timel = rd32ptp(wx, WX_TSC_1588_SYSTIML); 58 ptp_read_system_prets(sts); 59 } 60 return (u64)timel | (u64)timeh2 << 32; 61 } 62 63 static int wx_ptp_adjfine(struct ptp_clock_info *ptp, long ppb) 64 { 65 struct wx *wx = container_of(ptp, struct wx, ptp_caps); 66 u64 incval, mask; 67 68 smp_mb(); /* Force any pending update before accessing. */ 69 incval = READ_ONCE(wx->base_incval); 70 incval = adjust_by_scaled_ppm(incval, ppb); 71 72 mask = (wx->mac.type == wx_mac_em) ? 0x7FFFFFF : 0xFFFFFF; 73 incval &= mask; 74 if (wx->mac.type != wx_mac_em) 75 incval |= 2 << 24; 76 77 wr32ptp(wx, WX_TSC_1588_INC, incval); 78 79 return 0; 80 } 81 82 static int wx_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 83 { 84 struct wx *wx = container_of(ptp, struct wx, ptp_caps); 85 unsigned long flags; 86 87 write_seqlock_irqsave(&wx->hw_tc_lock, flags); 88 timecounter_adjtime(&wx->hw_tc, delta); 89 write_sequnlock_irqrestore(&wx->hw_tc_lock, flags); 90 91 if (wx->ptp_setup_sdp) 92 wx->ptp_setup_sdp(wx); 93 94 return 0; 95 } 96 97 static int wx_ptp_gettimex64(struct ptp_clock_info *ptp, 98 struct timespec64 *ts, 99 struct ptp_system_timestamp *sts) 100 { 101 struct wx *wx = container_of(ptp, struct wx, ptp_caps); 102 u64 ns, stamp; 103 104 stamp = wx_ptp_readtime(wx, sts); 105 ns = wx_ptp_timecounter_cyc2time(wx, stamp); 106 *ts = ns_to_timespec64(ns); 107 108 return 0; 109 } 110 111 static int wx_ptp_settime64(struct ptp_clock_info *ptp, 112 const struct timespec64 *ts) 113 { 114 struct wx *wx = container_of(ptp, struct wx, ptp_caps); 115 unsigned long flags; 116 u64 ns; 117 118 ns = timespec64_to_ns(ts); 119 /* reset the timecounter */ 120 write_seqlock_irqsave(&wx->hw_tc_lock, flags); 121 timecounter_init(&wx->hw_tc, &wx->hw_cc, ns); 122 write_sequnlock_irqrestore(&wx->hw_tc_lock, flags); 123 124 if (wx->ptp_setup_sdp) 125 wx->ptp_setup_sdp(wx); 126 127 return 0; 128 } 129 130 /** 131 * wx_ptp_clear_tx_timestamp - utility function to clear Tx timestamp state 132 * @wx: the private board structure 133 * 134 * This function should be called whenever the state related to a Tx timestamp 135 * needs to be cleared. This helps ensure that all related bits are reset for 136 * the next Tx timestamp event. 137 */ 138 static void wx_ptp_clear_tx_timestamp(struct wx *wx) 139 { 140 rd32ptp(wx, WX_TSC_1588_STMPH); 141 if (wx->ptp_tx_skb) { 142 dev_kfree_skb_any(wx->ptp_tx_skb); 143 wx->ptp_tx_skb = NULL; 144 } 145 clear_bit_unlock(WX_STATE_PTP_TX_IN_PROGRESS, wx->state); 146 } 147 148 /** 149 * wx_ptp_convert_to_hwtstamp - convert register value to hw timestamp 150 * @wx: private board structure 151 * @hwtstamp: stack timestamp structure 152 * @timestamp: unsigned 64bit system time value 153 * 154 * We need to convert the adapter's RX/TXSTMP registers into a hwtstamp value 155 * which can be used by the stack's ptp functions. 156 * 157 * The lock is used to protect consistency of the cyclecounter and the SYSTIME 158 * registers. However, it does not need to protect against the Rx or Tx 159 * timestamp registers, as there can't be a new timestamp until the old one is 160 * unlatched by reading. 161 * 162 * In addition to the timestamp in hardware, some controllers need a software 163 * overflow cyclecounter, and this function takes this into account as well. 164 **/ 165 static void wx_ptp_convert_to_hwtstamp(struct wx *wx, 166 struct skb_shared_hwtstamps *hwtstamp, 167 u64 timestamp) 168 { 169 u64 ns; 170 171 ns = wx_ptp_timecounter_cyc2time(wx, timestamp); 172 hwtstamp->hwtstamp = ns_to_ktime(ns); 173 } 174 175 /** 176 * wx_ptp_tx_hwtstamp - utility function which checks for TX time stamp 177 * @wx: the private board struct 178 * 179 * if the timestamp is valid, we convert it into the timecounter ns 180 * value, then store that result into the shhwtstamps structure which 181 * is passed up the network stack 182 */ 183 static void wx_ptp_tx_hwtstamp(struct wx *wx) 184 { 185 struct skb_shared_hwtstamps shhwtstamps; 186 struct sk_buff *skb = wx->ptp_tx_skb; 187 u64 regval = 0; 188 189 regval |= (u64)rd32ptp(wx, WX_TSC_1588_STMPL); 190 regval |= (u64)rd32ptp(wx, WX_TSC_1588_STMPH) << 32; 191 192 wx_ptp_convert_to_hwtstamp(wx, &shhwtstamps, regval); 193 194 wx->ptp_tx_skb = NULL; 195 clear_bit_unlock(WX_STATE_PTP_TX_IN_PROGRESS, wx->state); 196 skb_tstamp_tx(skb, &shhwtstamps); 197 dev_kfree_skb_any(skb); 198 wx->tx_hwtstamp_pkts++; 199 } 200 201 static int wx_ptp_tx_hwtstamp_work(struct wx *wx) 202 { 203 u32 tsynctxctl; 204 205 /* we have to have a valid skb to poll for a timestamp */ 206 if (!wx->ptp_tx_skb) { 207 wx_ptp_clear_tx_timestamp(wx); 208 return 0; 209 } 210 211 /* stop polling once we have a valid timestamp */ 212 tsynctxctl = rd32ptp(wx, WX_TSC_1588_CTL); 213 if (tsynctxctl & WX_TSC_1588_CTL_VALID) { 214 wx_ptp_tx_hwtstamp(wx); 215 return 0; 216 } 217 218 return -1; 219 } 220 221 /** 222 * wx_ptp_overflow_check - watchdog task to detect SYSTIME overflow 223 * @wx: pointer to wx struct 224 * 225 * this watchdog task periodically reads the timecounter 226 * in order to prevent missing when the system time registers wrap 227 * around. This needs to be run approximately twice a minute for the fastest 228 * overflowing hardware. We run it for all hardware since it shouldn't have a 229 * large impact. 230 */ 231 static void wx_ptp_overflow_check(struct wx *wx) 232 { 233 bool timeout = time_is_before_jiffies(wx->last_overflow_check + 234 WX_OVERFLOW_PERIOD); 235 unsigned long flags; 236 237 if (timeout) { 238 /* Update the timecounter */ 239 write_seqlock_irqsave(&wx->hw_tc_lock, flags); 240 timecounter_read(&wx->hw_tc); 241 write_sequnlock_irqrestore(&wx->hw_tc_lock, flags); 242 243 wx->last_overflow_check = jiffies; 244 } 245 } 246 247 /** 248 * wx_ptp_rx_hang - detect error case when Rx timestamp registers latched 249 * @wx: pointer to wx struct 250 * 251 * this watchdog task is scheduled to detect error case where hardware has 252 * dropped an Rx packet that was timestamped when the ring is full. The 253 * particular error is rare but leaves the device in a state unable to 254 * timestamp any future packets. 255 */ 256 static void wx_ptp_rx_hang(struct wx *wx) 257 { 258 struct wx_ring *rx_ring; 259 unsigned long rx_event; 260 u32 tsyncrxctl; 261 int n; 262 263 tsyncrxctl = rd32(wx, WX_PSR_1588_CTL); 264 265 /* if we don't have a valid timestamp in the registers, just update the 266 * timeout counter and exit 267 */ 268 if (!(tsyncrxctl & WX_PSR_1588_CTL_VALID)) { 269 wx->last_rx_ptp_check = jiffies; 270 return; 271 } 272 273 /* determine the most recent watchdog or rx_timestamp event */ 274 rx_event = wx->last_rx_ptp_check; 275 for (n = 0; n < wx->num_rx_queues; n++) { 276 rx_ring = wx->rx_ring[n]; 277 if (time_after(rx_ring->last_rx_timestamp, rx_event)) 278 rx_event = rx_ring->last_rx_timestamp; 279 } 280 281 /* only need to read the high RXSTMP register to clear the lock */ 282 if (time_is_before_jiffies(rx_event + 5 * HZ)) { 283 rd32(wx, WX_PSR_1588_STMPH); 284 wx->last_rx_ptp_check = jiffies; 285 286 wx->rx_hwtstamp_cleared++; 287 dev_warn(&wx->pdev->dev, "clearing RX Timestamp hang"); 288 } 289 } 290 291 /** 292 * wx_ptp_tx_hang - detect error case where Tx timestamp never finishes 293 * @wx: private network wx structure 294 */ 295 static void wx_ptp_tx_hang(struct wx *wx) 296 { 297 bool timeout = time_is_before_jiffies(wx->ptp_tx_start + 298 WX_PTP_TX_TIMEOUT); 299 300 if (!wx->ptp_tx_skb) 301 return; 302 303 if (!test_bit(WX_STATE_PTP_TX_IN_PROGRESS, wx->state)) 304 return; 305 306 /* If we haven't received a timestamp within the timeout, it is 307 * reasonable to assume that it will never occur, so we can unlock the 308 * timestamp bit when this occurs. 309 */ 310 if (timeout) { 311 wx_ptp_clear_tx_timestamp(wx); 312 wx->tx_hwtstamp_timeouts++; 313 dev_warn(&wx->pdev->dev, "clearing Tx timestamp hang\n"); 314 } 315 } 316 317 static long wx_ptp_do_aux_work(struct ptp_clock_info *ptp) 318 { 319 struct wx *wx = container_of(ptp, struct wx, ptp_caps); 320 int ts_done; 321 322 ts_done = wx_ptp_tx_hwtstamp_work(wx); 323 324 wx_ptp_overflow_check(wx); 325 if (unlikely(test_bit(WX_FLAG_RX_HWTSTAMP_IN_REGISTER, 326 wx->flags))) 327 wx_ptp_rx_hang(wx); 328 wx_ptp_tx_hang(wx); 329 330 return ts_done ? 1 : HZ; 331 } 332 333 static u64 wx_ptp_trigger_calc(struct wx *wx) 334 { 335 struct cyclecounter *cc = &wx->hw_cc; 336 unsigned long flags; 337 u64 ns = 0; 338 u32 rem; 339 340 /* Read the current clock time, and save the cycle counter value */ 341 write_seqlock_irqsave(&wx->hw_tc_lock, flags); 342 ns = timecounter_read(&wx->hw_tc); 343 wx->pps_edge_start = wx->hw_tc.cycle_last; 344 write_sequnlock_irqrestore(&wx->hw_tc_lock, flags); 345 wx->pps_edge_end = wx->pps_edge_start; 346 347 /* Figure out how far past the next second we are */ 348 div_u64_rem(ns, WX_NS_PER_SEC, &rem); 349 350 /* Figure out how many nanoseconds to add to round the clock edge up 351 * to the next full second 352 */ 353 rem = (WX_NS_PER_SEC - rem); 354 355 /* Adjust the clock edge to align with the next full second. */ 356 wx->pps_edge_start += div_u64(((u64)rem << cc->shift), cc->mult); 357 wx->pps_edge_end += div_u64(((u64)(rem + wx->pps_width) << 358 cc->shift), cc->mult); 359 360 return (ns + rem); 361 } 362 363 static int wx_ptp_setup_sdp(struct wx *wx) 364 { 365 struct cyclecounter *cc = &wx->hw_cc; 366 u32 tsauxc; 367 u64 nsec; 368 369 if (wx->pps_width >= WX_NS_PER_SEC) { 370 wx_err(wx, "PTP pps width cannot be longer than 1s!\n"); 371 return -EINVAL; 372 } 373 374 /* disable the pin first */ 375 wr32ptp(wx, WX_TSC_1588_AUX_CTL, 0); 376 WX_WRITE_FLUSH(wx); 377 378 if (!test_bit(WX_FLAG_PTP_PPS_ENABLED, wx->flags)) { 379 if (wx->pps_enabled) { 380 wx->pps_enabled = false; 381 wx_set_pps(wx, false, 0, 0); 382 } 383 return 0; 384 } 385 386 wx->pps_enabled = true; 387 nsec = wx_ptp_trigger_calc(wx); 388 wx_set_pps(wx, wx->pps_enabled, nsec, wx->pps_edge_start); 389 390 tsauxc = WX_TSC_1588_AUX_CTL_PLSG | WX_TSC_1588_AUX_CTL_EN_TT0 | 391 WX_TSC_1588_AUX_CTL_EN_TT1 | WX_TSC_1588_AUX_CTL_EN_TS0; 392 wr32ptp(wx, WX_TSC_1588_TRGT_L(0), (u32)wx->pps_edge_start); 393 wr32ptp(wx, WX_TSC_1588_TRGT_H(0), (u32)(wx->pps_edge_start >> 32)); 394 wr32ptp(wx, WX_TSC_1588_TRGT_L(1), (u32)wx->pps_edge_end); 395 wr32ptp(wx, WX_TSC_1588_TRGT_H(1), (u32)(wx->pps_edge_end >> 32)); 396 wr32ptp(wx, WX_TSC_1588_SDP(0), 397 WX_TSC_1588_SDP_FUN_SEL_TT0 | WX_TSC_1588_SDP_OUT_LEVEL_H); 398 wr32ptp(wx, WX_TSC_1588_SDP(1), WX_TSC_1588_SDP_FUN_SEL_TS0); 399 wr32ptp(wx, WX_TSC_1588_AUX_CTL, tsauxc); 400 wr32ptp(wx, WX_TSC_1588_INT_EN, WX_TSC_1588_INT_EN_TT1); 401 WX_WRITE_FLUSH(wx); 402 403 /* Adjust the clock edge to align with the next full second. */ 404 wx->sec_to_cc = div_u64(((u64)WX_NS_PER_SEC << cc->shift), cc->mult); 405 406 return 0; 407 } 408 409 static int wx_ptp_feature_enable(struct ptp_clock_info *ptp, 410 struct ptp_clock_request *rq, int on) 411 { 412 struct wx *wx = container_of(ptp, struct wx, ptp_caps); 413 414 /** 415 * When PPS is enabled, unmask the interrupt for the ClockOut 416 * feature, so that the interrupt handler can send the PPS 417 * event when the clock SDP triggers. Clear mask when PPS is 418 * disabled 419 */ 420 if (rq->type != PTP_CLK_REQ_PEROUT || !wx->ptp_setup_sdp) 421 return -EOPNOTSUPP; 422 423 /* Reject requests with unsupported flags */ 424 if (rq->perout.flags & ~(PTP_PEROUT_DUTY_CYCLE | 425 PTP_PEROUT_PHASE)) 426 return -EOPNOTSUPP; 427 428 if (rq->perout.phase.sec || rq->perout.phase.nsec) { 429 wx_err(wx, "Absolute start time not supported.\n"); 430 return -EINVAL; 431 } 432 433 if (rq->perout.period.sec != 1 || rq->perout.period.nsec) { 434 wx_err(wx, "Only 1pps is supported.\n"); 435 return -EINVAL; 436 } 437 438 if (rq->perout.flags & PTP_PEROUT_DUTY_CYCLE) { 439 struct timespec64 ts_on; 440 441 ts_on.tv_sec = rq->perout.on.sec; 442 ts_on.tv_nsec = rq->perout.on.nsec; 443 wx->pps_width = timespec64_to_ns(&ts_on); 444 } else { 445 wx->pps_width = 120000000; 446 } 447 448 if (on) 449 set_bit(WX_FLAG_PTP_PPS_ENABLED, wx->flags); 450 else 451 clear_bit(WX_FLAG_PTP_PPS_ENABLED, wx->flags); 452 453 return wx->ptp_setup_sdp(wx); 454 } 455 456 void wx_ptp_check_pps_event(struct wx *wx) 457 { 458 u32 tsauxc, int_status; 459 460 /* this check is necessary in case the interrupt was enabled via some 461 * alternative means (ex. debug_fs). Better to check here than 462 * everywhere that calls this function. 463 */ 464 if (!wx->ptp_clock) 465 return; 466 467 int_status = rd32ptp(wx, WX_TSC_1588_INT_ST); 468 if (int_status & WX_TSC_1588_INT_ST_TT1) { 469 /* disable the pin first */ 470 wr32ptp(wx, WX_TSC_1588_AUX_CTL, 0); 471 WX_WRITE_FLUSH(wx); 472 473 wx_ptp_trigger_calc(wx); 474 475 tsauxc = WX_TSC_1588_AUX_CTL_PLSG | WX_TSC_1588_AUX_CTL_EN_TT0 | 476 WX_TSC_1588_AUX_CTL_EN_TT1 | WX_TSC_1588_AUX_CTL_EN_TS0; 477 wr32ptp(wx, WX_TSC_1588_TRGT_L(0), (u32)wx->pps_edge_start); 478 wr32ptp(wx, WX_TSC_1588_TRGT_H(0), (u32)(wx->pps_edge_start >> 32)); 479 wr32ptp(wx, WX_TSC_1588_TRGT_L(1), (u32)wx->pps_edge_end); 480 wr32ptp(wx, WX_TSC_1588_TRGT_H(1), (u32)(wx->pps_edge_end >> 32)); 481 wr32ptp(wx, WX_TSC_1588_AUX_CTL, tsauxc); 482 WX_WRITE_FLUSH(wx); 483 } 484 } 485 EXPORT_SYMBOL(wx_ptp_check_pps_event); 486 487 static long wx_ptp_create_clock(struct wx *wx) 488 { 489 struct net_device *netdev = wx->netdev; 490 long err; 491 492 /* do nothing if we already have a clock device */ 493 if (!IS_ERR_OR_NULL(wx->ptp_clock)) 494 return 0; 495 496 snprintf(wx->ptp_caps.name, sizeof(wx->ptp_caps.name), 497 "%s", netdev->name); 498 wx->ptp_caps.owner = THIS_MODULE; 499 wx->ptp_caps.n_alarm = 0; 500 wx->ptp_caps.n_ext_ts = 0; 501 wx->ptp_caps.pps = 0; 502 wx->ptp_caps.adjfine = wx_ptp_adjfine; 503 wx->ptp_caps.adjtime = wx_ptp_adjtime; 504 wx->ptp_caps.gettimex64 = wx_ptp_gettimex64; 505 wx->ptp_caps.settime64 = wx_ptp_settime64; 506 wx->ptp_caps.do_aux_work = wx_ptp_do_aux_work; 507 if (wx->mac.type == wx_mac_em) { 508 wx->ptp_caps.max_adj = 500000000; 509 wx->ptp_caps.n_per_out = 1; 510 wx->ptp_setup_sdp = wx_ptp_setup_sdp; 511 wx->ptp_caps.enable = wx_ptp_feature_enable; 512 } else { 513 wx->ptp_caps.max_adj = 250000000; 514 wx->ptp_caps.n_per_out = 0; 515 wx->ptp_setup_sdp = NULL; 516 } 517 518 wx->ptp_clock = ptp_clock_register(&wx->ptp_caps, &wx->pdev->dev); 519 if (IS_ERR(wx->ptp_clock)) { 520 err = PTR_ERR(wx->ptp_clock); 521 wx->ptp_clock = NULL; 522 wx_err(wx, "ptp clock register failed\n"); 523 return err; 524 } else if (wx->ptp_clock) { 525 dev_info(&wx->pdev->dev, "registered PHC device on %s\n", 526 netdev->name); 527 } 528 529 /* Set the default timestamp mode to disabled here. We do this in 530 * create_clock instead of initialization, because we don't want to 531 * override the previous settings during a suspend/resume cycle. 532 */ 533 wx->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; 534 wx->tstamp_config.tx_type = HWTSTAMP_TX_OFF; 535 536 return 0; 537 } 538 539 static int wx_ptp_set_timestamp_mode(struct wx *wx, 540 struct kernel_hwtstamp_config *config) 541 { 542 u32 tsync_tx_ctl = WX_TSC_1588_CTL_ENABLED; 543 u32 tsync_rx_ctl = WX_PSR_1588_CTL_ENABLED; 544 DECLARE_BITMAP(flags, WX_PF_FLAGS_NBITS); 545 u32 tsync_rx_mtrl = PTP_EV_PORT << 16; 546 bool is_l2 = false; 547 u32 regval; 548 549 memcpy(flags, wx->flags, sizeof(wx->flags)); 550 551 switch (config->tx_type) { 552 case HWTSTAMP_TX_OFF: 553 tsync_tx_ctl = 0; 554 break; 555 case HWTSTAMP_TX_ON: 556 break; 557 default: 558 return -ERANGE; 559 } 560 561 switch (config->rx_filter) { 562 case HWTSTAMP_FILTER_NONE: 563 tsync_rx_ctl = 0; 564 tsync_rx_mtrl = 0; 565 clear_bit(WX_FLAG_RX_HWTSTAMP_ENABLED, flags); 566 clear_bit(WX_FLAG_RX_HWTSTAMP_IN_REGISTER, flags); 567 break; 568 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 569 tsync_rx_ctl |= WX_PSR_1588_CTL_TYPE_L4_V1; 570 tsync_rx_mtrl |= WX_PSR_1588_MSG_V1_SYNC; 571 set_bit(WX_FLAG_RX_HWTSTAMP_ENABLED, flags); 572 set_bit(WX_FLAG_RX_HWTSTAMP_IN_REGISTER, flags); 573 break; 574 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 575 tsync_rx_ctl |= WX_PSR_1588_CTL_TYPE_L4_V1; 576 tsync_rx_mtrl |= WX_PSR_1588_MSG_V1_DELAY_REQ; 577 set_bit(WX_FLAG_RX_HWTSTAMP_ENABLED, flags); 578 set_bit(WX_FLAG_RX_HWTSTAMP_IN_REGISTER, flags); 579 break; 580 case HWTSTAMP_FILTER_PTP_V2_EVENT: 581 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 582 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 583 case HWTSTAMP_FILTER_PTP_V2_SYNC: 584 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 585 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 586 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 587 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 588 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 589 tsync_rx_ctl |= WX_PSR_1588_CTL_TYPE_EVENT_V2; 590 is_l2 = true; 591 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 592 set_bit(WX_FLAG_RX_HWTSTAMP_ENABLED, flags); 593 set_bit(WX_FLAG_RX_HWTSTAMP_IN_REGISTER, flags); 594 break; 595 default: 596 /* register PSR_1588_MSG must be set in order to do V1 packets, 597 * therefore it is not possible to time stamp both V1 Sync and 598 * Delay_Req messages unless hardware supports timestamping all 599 * packets => return error 600 */ 601 config->rx_filter = HWTSTAMP_FILTER_NONE; 602 return -ERANGE; 603 } 604 605 /* define ethertype filter for timestamping L2 packets */ 606 if (is_l2) 607 wr32(wx, WX_PSR_ETYPE_SWC(WX_PSR_ETYPE_SWC_FILTER_1588), 608 (WX_PSR_ETYPE_SWC_FILTER_EN | /* enable filter */ 609 WX_PSR_ETYPE_SWC_1588 | /* enable timestamping */ 610 ETH_P_1588)); /* 1588 eth protocol type */ 611 else 612 wr32(wx, WX_PSR_ETYPE_SWC(WX_PSR_ETYPE_SWC_FILTER_1588), 0); 613 614 /* enable/disable TX */ 615 regval = rd32ptp(wx, WX_TSC_1588_CTL); 616 regval &= ~WX_TSC_1588_CTL_ENABLED; 617 regval |= tsync_tx_ctl; 618 wr32ptp(wx, WX_TSC_1588_CTL, regval); 619 620 /* enable/disable RX */ 621 regval = rd32(wx, WX_PSR_1588_CTL); 622 regval &= ~(WX_PSR_1588_CTL_ENABLED | WX_PSR_1588_CTL_TYPE_MASK); 623 regval |= tsync_rx_ctl; 624 wr32(wx, WX_PSR_1588_CTL, regval); 625 626 /* define which PTP packets are time stamped */ 627 wr32(wx, WX_PSR_1588_MSG, tsync_rx_mtrl); 628 629 WX_WRITE_FLUSH(wx); 630 631 /* configure adapter flags only when HW is actually configured */ 632 memcpy(wx->flags, flags, sizeof(wx->flags)); 633 634 /* clear TX/RX timestamp state, just to be sure */ 635 wx_ptp_clear_tx_timestamp(wx); 636 rd32(wx, WX_PSR_1588_STMPH); 637 638 return 0; 639 } 640 641 static u64 wx_ptp_read(const struct cyclecounter *hw_cc) 642 { 643 struct wx *wx = container_of(hw_cc, struct wx, hw_cc); 644 645 return wx_ptp_readtime(wx, NULL); 646 } 647 648 static void wx_ptp_link_speed_adjust(struct wx *wx, u32 *shift, u32 *incval) 649 { 650 if (wx->mac.type == wx_mac_em) { 651 *shift = WX_INCVAL_SHIFT_EM; 652 *incval = WX_INCVAL_EM; 653 return; 654 } 655 656 switch (wx->speed) { 657 case SPEED_10: 658 *shift = WX_INCVAL_SHIFT_10; 659 *incval = WX_INCVAL_10; 660 break; 661 case SPEED_100: 662 *shift = WX_INCVAL_SHIFT_100; 663 *incval = WX_INCVAL_100; 664 break; 665 case SPEED_1000: 666 *shift = WX_INCVAL_SHIFT_1GB; 667 *incval = WX_INCVAL_1GB; 668 break; 669 case SPEED_10000: 670 default: 671 *shift = WX_INCVAL_SHIFT_10GB; 672 *incval = WX_INCVAL_10GB; 673 break; 674 } 675 } 676 677 /** 678 * wx_ptp_reset_cyclecounter - create the cycle counter from hw 679 * @wx: pointer to the wx structure 680 * 681 * This function should be called to set the proper values for the TSC_1588_INC 682 * register and tell the cyclecounter structure what the tick rate of SYSTIME 683 * is. It does not directly modify SYSTIME registers or the timecounter 684 * structure. It should be called whenever a new TSC_1588_INC value is 685 * necessary, such as during initialization or when the link speed changes. 686 */ 687 void wx_ptp_reset_cyclecounter(struct wx *wx) 688 { 689 u32 incval = 0, mask = 0; 690 struct cyclecounter cc; 691 unsigned long flags; 692 693 /* For some of the boards below this mask is technically incorrect. 694 * The timestamp mask overflows at approximately 61bits. However the 695 * particular hardware does not overflow on an even bitmask value. 696 * Instead, it overflows due to conversion of upper 32bits billions of 697 * cycles. Timecounters are not really intended for this purpose so 698 * they do not properly function if the overflow point isn't 2^N-1. 699 * However, the actual SYSTIME values in question take ~138 years to 700 * overflow. In practice this means they won't actually overflow. A 701 * proper fix to this problem would require modification of the 702 * timecounter delta calculations. 703 */ 704 cc.mask = CLOCKSOURCE_MASK(64); 705 cc.mult = 1; 706 cc.shift = 0; 707 708 cc.read = wx_ptp_read; 709 wx_ptp_link_speed_adjust(wx, &cc.shift, &incval); 710 711 /* update the base incval used to calculate frequency adjustment */ 712 WRITE_ONCE(wx->base_incval, incval); 713 714 mask = (wx->mac.type == wx_mac_em) ? 0x7FFFFFF : 0xFFFFFF; 715 incval &= mask; 716 if (wx->mac.type != wx_mac_em) 717 incval |= 2 << 24; 718 wr32ptp(wx, WX_TSC_1588_INC, incval); 719 720 smp_mb(); /* Force the above update. */ 721 722 /* need lock to prevent incorrect read while modifying cyclecounter */ 723 write_seqlock_irqsave(&wx->hw_tc_lock, flags); 724 memcpy(&wx->hw_cc, &cc, sizeof(wx->hw_cc)); 725 write_sequnlock_irqrestore(&wx->hw_tc_lock, flags); 726 } 727 EXPORT_SYMBOL(wx_ptp_reset_cyclecounter); 728 729 void wx_ptp_reset(struct wx *wx) 730 { 731 unsigned long flags; 732 733 /* reset the hardware timestamping mode */ 734 wx_ptp_set_timestamp_mode(wx, &wx->tstamp_config); 735 wx_ptp_reset_cyclecounter(wx); 736 737 wr32ptp(wx, WX_TSC_1588_SYSTIML, 0); 738 wr32ptp(wx, WX_TSC_1588_SYSTIMH, 0); 739 WX_WRITE_FLUSH(wx); 740 741 write_seqlock_irqsave(&wx->hw_tc_lock, flags); 742 timecounter_init(&wx->hw_tc, &wx->hw_cc, 743 ktime_to_ns(ktime_get_real())); 744 write_sequnlock_irqrestore(&wx->hw_tc_lock, flags); 745 746 wx->last_overflow_check = jiffies; 747 ptp_schedule_worker(wx->ptp_clock, HZ); 748 749 /* Now that the shift has been calculated and the systime 750 * registers reset, (re-)enable the Clock out feature 751 */ 752 if (wx->ptp_setup_sdp) 753 wx->ptp_setup_sdp(wx); 754 } 755 EXPORT_SYMBOL(wx_ptp_reset); 756 757 void wx_ptp_init(struct wx *wx) 758 { 759 /* Initialize the seqlock_t first, since the user might call the clock 760 * functions any time after we've initialized the ptp clock device. 761 */ 762 seqlock_init(&wx->hw_tc_lock); 763 764 /* obtain a ptp clock device, or re-use an existing device */ 765 if (wx_ptp_create_clock(wx)) 766 return; 767 768 wx->tx_hwtstamp_pkts = 0; 769 wx->tx_hwtstamp_timeouts = 0; 770 wx->tx_hwtstamp_skipped = 0; 771 wx->tx_hwtstamp_errors = 0; 772 wx->rx_hwtstamp_cleared = 0; 773 /* reset the ptp related hardware bits */ 774 wx_ptp_reset(wx); 775 776 /* enter the WX_STATE_PTP_RUNNING state */ 777 set_bit(WX_STATE_PTP_RUNNING, wx->state); 778 } 779 EXPORT_SYMBOL(wx_ptp_init); 780 781 /** 782 * wx_ptp_suspend - stop ptp work items 783 * @wx: pointer to wx struct 784 * 785 * This function suspends ptp activity, and prevents more work from being 786 * generated, but does not destroy the clock device. 787 */ 788 void wx_ptp_suspend(struct wx *wx) 789 { 790 /* leave the WX_STATE_PTP_RUNNING STATE */ 791 if (!test_and_clear_bit(WX_STATE_PTP_RUNNING, wx->state)) 792 return; 793 794 clear_bit(WX_FLAG_PTP_PPS_ENABLED, wx->flags); 795 if (wx->ptp_setup_sdp) 796 wx->ptp_setup_sdp(wx); 797 798 wx_ptp_clear_tx_timestamp(wx); 799 } 800 EXPORT_SYMBOL(wx_ptp_suspend); 801 802 /** 803 * wx_ptp_stop - destroy the ptp_clock device 804 * @wx: pointer to wx struct 805 * 806 * Completely destroy the ptp_clock device, and disable all PTP related 807 * features. Intended to be run when the device is being closed. 808 */ 809 void wx_ptp_stop(struct wx *wx) 810 { 811 /* first, suspend ptp activity */ 812 wx_ptp_suspend(wx); 813 814 /* now destroy the ptp clock device */ 815 if (wx->ptp_clock) { 816 ptp_clock_unregister(wx->ptp_clock); 817 wx->ptp_clock = NULL; 818 dev_info(&wx->pdev->dev, "removed PHC on %s\n", wx->netdev->name); 819 } 820 } 821 EXPORT_SYMBOL(wx_ptp_stop); 822 823 /** 824 * wx_ptp_rx_hwtstamp - utility function which checks for RX time stamp 825 * @wx: pointer to wx struct 826 * @skb: particular skb to send timestamp with 827 * 828 * if the timestamp is valid, we convert it into the timecounter ns 829 * value, then store that result into the shhwtstamps structure which 830 * is passed up the network stack 831 */ 832 void wx_ptp_rx_hwtstamp(struct wx *wx, struct sk_buff *skb) 833 { 834 u64 regval = 0; 835 u32 tsyncrxctl; 836 837 /* Read the tsyncrxctl register afterwards in order to prevent taking an 838 * I/O hit on every packet. 839 */ 840 tsyncrxctl = rd32(wx, WX_PSR_1588_CTL); 841 if (!(tsyncrxctl & WX_PSR_1588_CTL_VALID)) 842 return; 843 844 regval |= (u64)rd32(wx, WX_PSR_1588_STMPL); 845 regval |= (u64)rd32(wx, WX_PSR_1588_STMPH) << 32; 846 847 wx_ptp_convert_to_hwtstamp(wx, skb_hwtstamps(skb), regval); 848 } 849 850 int wx_hwtstamp_get(struct net_device *dev, 851 struct kernel_hwtstamp_config *cfg) 852 { 853 struct wx *wx = netdev_priv(dev); 854 855 if (!netif_running(dev)) 856 return -EINVAL; 857 858 *cfg = wx->tstamp_config; 859 860 return 0; 861 } 862 EXPORT_SYMBOL(wx_hwtstamp_get); 863 864 int wx_hwtstamp_set(struct net_device *dev, 865 struct kernel_hwtstamp_config *cfg, 866 struct netlink_ext_ack *extack) 867 { 868 struct wx *wx = netdev_priv(dev); 869 int err; 870 871 if (!netif_running(dev)) 872 return -EINVAL; 873 874 err = wx_ptp_set_timestamp_mode(wx, cfg); 875 if (err) 876 return err; 877 878 /* save these settings for future reference */ 879 memcpy(&wx->tstamp_config, cfg, sizeof(wx->tstamp_config)); 880 881 return 0; 882 } 883 EXPORT_SYMBOL(wx_hwtstamp_set); 884