1 /**************************************************************************** 2 * Driver for Solarflare Solarstorm network controllers and boards 3 * Copyright 2005-2006 Fen Systems Ltd. 4 * Copyright 2005-2011 Solarflare Communications Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation, incorporated herein by reference. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/pci.h> 13 #include <linux/netdevice.h> 14 #include <linux/etherdevice.h> 15 #include <linux/delay.h> 16 #include <linux/notifier.h> 17 #include <linux/ip.h> 18 #include <linux/tcp.h> 19 #include <linux/in.h> 20 #include <linux/crc32.h> 21 #include <linux/ethtool.h> 22 #include <linux/topology.h> 23 #include <linux/gfp.h> 24 #include <linux/cpu_rmap.h> 25 #include "net_driver.h" 26 #include "efx.h" 27 #include "nic.h" 28 #include "selftest.h" 29 30 #include "mcdi.h" 31 #include "workarounds.h" 32 33 /************************************************************************** 34 * 35 * Type name strings 36 * 37 ************************************************************************** 38 */ 39 40 /* Loopback mode names (see LOOPBACK_MODE()) */ 41 const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; 42 const char *const efx_loopback_mode_names[] = { 43 [LOOPBACK_NONE] = "NONE", 44 [LOOPBACK_DATA] = "DATAPATH", 45 [LOOPBACK_GMAC] = "GMAC", 46 [LOOPBACK_XGMII] = "XGMII", 47 [LOOPBACK_XGXS] = "XGXS", 48 [LOOPBACK_XAUI] = "XAUI", 49 [LOOPBACK_GMII] = "GMII", 50 [LOOPBACK_SGMII] = "SGMII", 51 [LOOPBACK_XGBR] = "XGBR", 52 [LOOPBACK_XFI] = "XFI", 53 [LOOPBACK_XAUI_FAR] = "XAUI_FAR", 54 [LOOPBACK_GMII_FAR] = "GMII_FAR", 55 [LOOPBACK_SGMII_FAR] = "SGMII_FAR", 56 [LOOPBACK_XFI_FAR] = "XFI_FAR", 57 [LOOPBACK_GPHY] = "GPHY", 58 [LOOPBACK_PHYXS] = "PHYXS", 59 [LOOPBACK_PCS] = "PCS", 60 [LOOPBACK_PMAPMD] = "PMA/PMD", 61 [LOOPBACK_XPORT] = "XPORT", 62 [LOOPBACK_XGMII_WS] = "XGMII_WS", 63 [LOOPBACK_XAUI_WS] = "XAUI_WS", 64 [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", 65 [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", 66 [LOOPBACK_GMII_WS] = "GMII_WS", 67 [LOOPBACK_XFI_WS] = "XFI_WS", 68 [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", 69 [LOOPBACK_PHYXS_WS] = "PHYXS_WS", 70 }; 71 72 const unsigned int efx_reset_type_max = RESET_TYPE_MAX; 73 const char *const efx_reset_type_names[] = { 74 [RESET_TYPE_INVISIBLE] = "INVISIBLE", 75 [RESET_TYPE_ALL] = "ALL", 76 [RESET_TYPE_WORLD] = "WORLD", 77 [RESET_TYPE_DISABLE] = "DISABLE", 78 [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", 79 [RESET_TYPE_INT_ERROR] = "INT_ERROR", 80 [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY", 81 [RESET_TYPE_RX_DESC_FETCH] = "RX_DESC_FETCH", 82 [RESET_TYPE_TX_DESC_FETCH] = "TX_DESC_FETCH", 83 [RESET_TYPE_TX_SKIP] = "TX_SKIP", 84 [RESET_TYPE_MC_FAILURE] = "MC_FAILURE", 85 }; 86 87 #define EFX_MAX_MTU (9 * 1024) 88 89 /* Reset workqueue. If any NIC has a hardware failure then a reset will be 90 * queued onto this work queue. This is not a per-nic work queue, because 91 * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. 92 */ 93 static struct workqueue_struct *reset_workqueue; 94 95 /************************************************************************** 96 * 97 * Configurable values 98 * 99 *************************************************************************/ 100 101 /* 102 * Use separate channels for TX and RX events 103 * 104 * Set this to 1 to use separate channels for TX and RX. It allows us 105 * to control interrupt affinity separately for TX and RX. 106 * 107 * This is only used in MSI-X interrupt mode 108 */ 109 static bool separate_tx_channels; 110 module_param(separate_tx_channels, bool, 0444); 111 MODULE_PARM_DESC(separate_tx_channels, 112 "Use separate channels for TX and RX"); 113 114 /* This is the weight assigned to each of the (per-channel) virtual 115 * NAPI devices. 116 */ 117 static int napi_weight = 64; 118 119 /* This is the time (in jiffies) between invocations of the hardware 120 * monitor. On Falcon-based NICs, this will: 121 * - Check the on-board hardware monitor; 122 * - Poll the link state and reconfigure the hardware as necessary. 123 */ 124 static unsigned int efx_monitor_interval = 1 * HZ; 125 126 /* Initial interrupt moderation settings. They can be modified after 127 * module load with ethtool. 128 * 129 * The default for RX should strike a balance between increasing the 130 * round-trip latency and reducing overhead. 131 */ 132 static unsigned int rx_irq_mod_usec = 60; 133 134 /* Initial interrupt moderation settings. They can be modified after 135 * module load with ethtool. 136 * 137 * This default is chosen to ensure that a 10G link does not go idle 138 * while a TX queue is stopped after it has become full. A queue is 139 * restarted when it drops below half full. The time this takes (assuming 140 * worst case 3 descriptors per packet and 1024 descriptors) is 141 * 512 / 3 * 1.2 = 205 usec. 142 */ 143 static unsigned int tx_irq_mod_usec = 150; 144 145 /* This is the first interrupt mode to try out of: 146 * 0 => MSI-X 147 * 1 => MSI 148 * 2 => legacy 149 */ 150 static unsigned int interrupt_mode; 151 152 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), 153 * i.e. the number of CPUs among which we may distribute simultaneous 154 * interrupt handling. 155 * 156 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. 157 * The default (0) means to assign an interrupt to each core. 158 */ 159 static unsigned int rss_cpus; 160 module_param(rss_cpus, uint, 0444); 161 MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); 162 163 static bool phy_flash_cfg; 164 module_param(phy_flash_cfg, bool, 0644); 165 MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); 166 167 static unsigned irq_adapt_low_thresh = 8000; 168 module_param(irq_adapt_low_thresh, uint, 0644); 169 MODULE_PARM_DESC(irq_adapt_low_thresh, 170 "Threshold score for reducing IRQ moderation"); 171 172 static unsigned irq_adapt_high_thresh = 16000; 173 module_param(irq_adapt_high_thresh, uint, 0644); 174 MODULE_PARM_DESC(irq_adapt_high_thresh, 175 "Threshold score for increasing IRQ moderation"); 176 177 static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 178 NETIF_MSG_LINK | NETIF_MSG_IFDOWN | 179 NETIF_MSG_IFUP | NETIF_MSG_RX_ERR | 180 NETIF_MSG_TX_ERR | NETIF_MSG_HW); 181 module_param(debug, uint, 0); 182 MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value"); 183 184 /************************************************************************** 185 * 186 * Utility functions and prototypes 187 * 188 *************************************************************************/ 189 190 static void efx_start_interrupts(struct efx_nic *efx, bool may_keep_eventq); 191 static void efx_stop_interrupts(struct efx_nic *efx, bool may_keep_eventq); 192 static void efx_remove_channel(struct efx_channel *channel); 193 static void efx_remove_channels(struct efx_nic *efx); 194 static const struct efx_channel_type efx_default_channel_type; 195 static void efx_remove_port(struct efx_nic *efx); 196 static void efx_init_napi_channel(struct efx_channel *channel); 197 static void efx_fini_napi(struct efx_nic *efx); 198 static void efx_fini_napi_channel(struct efx_channel *channel); 199 static void efx_fini_struct(struct efx_nic *efx); 200 static void efx_start_all(struct efx_nic *efx); 201 static void efx_stop_all(struct efx_nic *efx); 202 203 #define EFX_ASSERT_RESET_SERIALISED(efx) \ 204 do { \ 205 if ((efx->state == STATE_READY) || \ 206 (efx->state == STATE_DISABLED)) \ 207 ASSERT_RTNL(); \ 208 } while (0) 209 210 static int efx_check_disabled(struct efx_nic *efx) 211 { 212 if (efx->state == STATE_DISABLED) { 213 netif_err(efx, drv, efx->net_dev, 214 "device is disabled due to earlier errors\n"); 215 return -EIO; 216 } 217 return 0; 218 } 219 220 /************************************************************************** 221 * 222 * Event queue processing 223 * 224 *************************************************************************/ 225 226 /* Process channel's event queue 227 * 228 * This function is responsible for processing the event queue of a 229 * single channel. The caller must guarantee that this function will 230 * never be concurrently called more than once on the same channel, 231 * though different channels may be being processed concurrently. 232 */ 233 static int efx_process_channel(struct efx_channel *channel, int budget) 234 { 235 int spent; 236 237 if (unlikely(!channel->enabled)) 238 return 0; 239 240 spent = efx_nic_process_eventq(channel, budget); 241 if (spent && efx_channel_has_rx_queue(channel)) { 242 struct efx_rx_queue *rx_queue = 243 efx_channel_get_rx_queue(channel); 244 245 /* Deliver last RX packet. */ 246 if (channel->rx_pkt) { 247 __efx_rx_packet(channel, channel->rx_pkt); 248 channel->rx_pkt = NULL; 249 } 250 if (rx_queue->enabled) { 251 efx_rx_strategy(channel); 252 efx_fast_push_rx_descriptors(rx_queue); 253 } 254 } 255 256 return spent; 257 } 258 259 /* Mark channel as finished processing 260 * 261 * Note that since we will not receive further interrupts for this 262 * channel before we finish processing and call the eventq_read_ack() 263 * method, there is no need to use the interrupt hold-off timers. 264 */ 265 static inline void efx_channel_processed(struct efx_channel *channel) 266 { 267 /* The interrupt handler for this channel may set work_pending 268 * as soon as we acknowledge the events we've seen. Make sure 269 * it's cleared before then. */ 270 channel->work_pending = false; 271 smp_wmb(); 272 273 efx_nic_eventq_read_ack(channel); 274 } 275 276 /* NAPI poll handler 277 * 278 * NAPI guarantees serialisation of polls of the same device, which 279 * provides the guarantee required by efx_process_channel(). 280 */ 281 static int efx_poll(struct napi_struct *napi, int budget) 282 { 283 struct efx_channel *channel = 284 container_of(napi, struct efx_channel, napi_str); 285 struct efx_nic *efx = channel->efx; 286 int spent; 287 288 netif_vdbg(efx, intr, efx->net_dev, 289 "channel %d NAPI poll executing on CPU %d\n", 290 channel->channel, raw_smp_processor_id()); 291 292 spent = efx_process_channel(channel, budget); 293 294 if (spent < budget) { 295 if (efx_channel_has_rx_queue(channel) && 296 efx->irq_rx_adaptive && 297 unlikely(++channel->irq_count == 1000)) { 298 if (unlikely(channel->irq_mod_score < 299 irq_adapt_low_thresh)) { 300 if (channel->irq_moderation > 1) { 301 channel->irq_moderation -= 1; 302 efx->type->push_irq_moderation(channel); 303 } 304 } else if (unlikely(channel->irq_mod_score > 305 irq_adapt_high_thresh)) { 306 if (channel->irq_moderation < 307 efx->irq_rx_moderation) { 308 channel->irq_moderation += 1; 309 efx->type->push_irq_moderation(channel); 310 } 311 } 312 channel->irq_count = 0; 313 channel->irq_mod_score = 0; 314 } 315 316 efx_filter_rfs_expire(channel); 317 318 /* There is no race here; although napi_disable() will 319 * only wait for napi_complete(), this isn't a problem 320 * since efx_channel_processed() will have no effect if 321 * interrupts have already been disabled. 322 */ 323 napi_complete(napi); 324 efx_channel_processed(channel); 325 } 326 327 return spent; 328 } 329 330 /* Process the eventq of the specified channel immediately on this CPU 331 * 332 * Disable hardware generated interrupts, wait for any existing 333 * processing to finish, then directly poll (and ack ) the eventq. 334 * Finally reenable NAPI and interrupts. 335 * 336 * This is for use only during a loopback self-test. It must not 337 * deliver any packets up the stack as this can result in deadlock. 338 */ 339 void efx_process_channel_now(struct efx_channel *channel) 340 { 341 struct efx_nic *efx = channel->efx; 342 343 BUG_ON(channel->channel >= efx->n_channels); 344 BUG_ON(!channel->enabled); 345 BUG_ON(!efx->loopback_selftest); 346 347 /* Disable interrupts and wait for ISRs to complete */ 348 efx_nic_disable_interrupts(efx); 349 if (efx->legacy_irq) { 350 synchronize_irq(efx->legacy_irq); 351 efx->legacy_irq_enabled = false; 352 } 353 if (channel->irq) 354 synchronize_irq(channel->irq); 355 356 /* Wait for any NAPI processing to complete */ 357 napi_disable(&channel->napi_str); 358 359 /* Poll the channel */ 360 efx_process_channel(channel, channel->eventq_mask + 1); 361 362 /* Ack the eventq. This may cause an interrupt to be generated 363 * when they are reenabled */ 364 efx_channel_processed(channel); 365 366 napi_enable(&channel->napi_str); 367 if (efx->legacy_irq) 368 efx->legacy_irq_enabled = true; 369 efx_nic_enable_interrupts(efx); 370 } 371 372 /* Create event queue 373 * Event queue memory allocations are done only once. If the channel 374 * is reset, the memory buffer will be reused; this guards against 375 * errors during channel reset and also simplifies interrupt handling. 376 */ 377 static int efx_probe_eventq(struct efx_channel *channel) 378 { 379 struct efx_nic *efx = channel->efx; 380 unsigned long entries; 381 382 netif_dbg(efx, probe, efx->net_dev, 383 "chan %d create event queue\n", channel->channel); 384 385 /* Build an event queue with room for one event per tx and rx buffer, 386 * plus some extra for link state events and MCDI completions. */ 387 entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); 388 EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); 389 channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; 390 391 return efx_nic_probe_eventq(channel); 392 } 393 394 /* Prepare channel's event queue */ 395 static void efx_init_eventq(struct efx_channel *channel) 396 { 397 netif_dbg(channel->efx, drv, channel->efx->net_dev, 398 "chan %d init event queue\n", channel->channel); 399 400 channel->eventq_read_ptr = 0; 401 402 efx_nic_init_eventq(channel); 403 } 404 405 /* Enable event queue processing and NAPI */ 406 static void efx_start_eventq(struct efx_channel *channel) 407 { 408 netif_dbg(channel->efx, ifup, channel->efx->net_dev, 409 "chan %d start event queue\n", channel->channel); 410 411 /* The interrupt handler for this channel may set work_pending 412 * as soon as we enable it. Make sure it's cleared before 413 * then. Similarly, make sure it sees the enabled flag set. 414 */ 415 channel->work_pending = false; 416 channel->enabled = true; 417 smp_wmb(); 418 419 napi_enable(&channel->napi_str); 420 efx_nic_eventq_read_ack(channel); 421 } 422 423 /* Disable event queue processing and NAPI */ 424 static void efx_stop_eventq(struct efx_channel *channel) 425 { 426 if (!channel->enabled) 427 return; 428 429 napi_disable(&channel->napi_str); 430 channel->enabled = false; 431 } 432 433 static void efx_fini_eventq(struct efx_channel *channel) 434 { 435 netif_dbg(channel->efx, drv, channel->efx->net_dev, 436 "chan %d fini event queue\n", channel->channel); 437 438 efx_nic_fini_eventq(channel); 439 } 440 441 static void efx_remove_eventq(struct efx_channel *channel) 442 { 443 netif_dbg(channel->efx, drv, channel->efx->net_dev, 444 "chan %d remove event queue\n", channel->channel); 445 446 efx_nic_remove_eventq(channel); 447 } 448 449 /************************************************************************** 450 * 451 * Channel handling 452 * 453 *************************************************************************/ 454 455 /* Allocate and initialise a channel structure. */ 456 static struct efx_channel * 457 efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel) 458 { 459 struct efx_channel *channel; 460 struct efx_rx_queue *rx_queue; 461 struct efx_tx_queue *tx_queue; 462 int j; 463 464 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 465 if (!channel) 466 return NULL; 467 468 channel->efx = efx; 469 channel->channel = i; 470 channel->type = &efx_default_channel_type; 471 472 for (j = 0; j < EFX_TXQ_TYPES; j++) { 473 tx_queue = &channel->tx_queue[j]; 474 tx_queue->efx = efx; 475 tx_queue->queue = i * EFX_TXQ_TYPES + j; 476 tx_queue->channel = channel; 477 } 478 479 rx_queue = &channel->rx_queue; 480 rx_queue->efx = efx; 481 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, 482 (unsigned long)rx_queue); 483 484 return channel; 485 } 486 487 /* Allocate and initialise a channel structure, copying parameters 488 * (but not resources) from an old channel structure. 489 */ 490 static struct efx_channel * 491 efx_copy_channel(const struct efx_channel *old_channel) 492 { 493 struct efx_channel *channel; 494 struct efx_rx_queue *rx_queue; 495 struct efx_tx_queue *tx_queue; 496 int j; 497 498 channel = kmalloc(sizeof(*channel), GFP_KERNEL); 499 if (!channel) 500 return NULL; 501 502 *channel = *old_channel; 503 504 channel->napi_dev = NULL; 505 memset(&channel->eventq, 0, sizeof(channel->eventq)); 506 507 for (j = 0; j < EFX_TXQ_TYPES; j++) { 508 tx_queue = &channel->tx_queue[j]; 509 if (tx_queue->channel) 510 tx_queue->channel = channel; 511 tx_queue->buffer = NULL; 512 memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); 513 } 514 515 rx_queue = &channel->rx_queue; 516 rx_queue->buffer = NULL; 517 memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); 518 setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, 519 (unsigned long)rx_queue); 520 521 return channel; 522 } 523 524 static int efx_probe_channel(struct efx_channel *channel) 525 { 526 struct efx_tx_queue *tx_queue; 527 struct efx_rx_queue *rx_queue; 528 int rc; 529 530 netif_dbg(channel->efx, probe, channel->efx->net_dev, 531 "creating channel %d\n", channel->channel); 532 533 rc = channel->type->pre_probe(channel); 534 if (rc) 535 goto fail; 536 537 rc = efx_probe_eventq(channel); 538 if (rc) 539 goto fail; 540 541 efx_for_each_channel_tx_queue(tx_queue, channel) { 542 rc = efx_probe_tx_queue(tx_queue); 543 if (rc) 544 goto fail; 545 } 546 547 efx_for_each_channel_rx_queue(rx_queue, channel) { 548 rc = efx_probe_rx_queue(rx_queue); 549 if (rc) 550 goto fail; 551 } 552 553 channel->n_rx_frm_trunc = 0; 554 555 return 0; 556 557 fail: 558 efx_remove_channel(channel); 559 return rc; 560 } 561 562 static void 563 efx_get_channel_name(struct efx_channel *channel, char *buf, size_t len) 564 { 565 struct efx_nic *efx = channel->efx; 566 const char *type; 567 int number; 568 569 number = channel->channel; 570 if (efx->tx_channel_offset == 0) { 571 type = ""; 572 } else if (channel->channel < efx->tx_channel_offset) { 573 type = "-rx"; 574 } else { 575 type = "-tx"; 576 number -= efx->tx_channel_offset; 577 } 578 snprintf(buf, len, "%s%s-%d", efx->name, type, number); 579 } 580 581 static void efx_set_channel_names(struct efx_nic *efx) 582 { 583 struct efx_channel *channel; 584 585 efx_for_each_channel(channel, efx) 586 channel->type->get_name(channel, 587 efx->channel_name[channel->channel], 588 sizeof(efx->channel_name[0])); 589 } 590 591 static int efx_probe_channels(struct efx_nic *efx) 592 { 593 struct efx_channel *channel; 594 int rc; 595 596 /* Restart special buffer allocation */ 597 efx->next_buffer_table = 0; 598 599 /* Probe channels in reverse, so that any 'extra' channels 600 * use the start of the buffer table. This allows the traffic 601 * channels to be resized without moving them or wasting the 602 * entries before them. 603 */ 604 efx_for_each_channel_rev(channel, efx) { 605 rc = efx_probe_channel(channel); 606 if (rc) { 607 netif_err(efx, probe, efx->net_dev, 608 "failed to create channel %d\n", 609 channel->channel); 610 goto fail; 611 } 612 } 613 efx_set_channel_names(efx); 614 615 return 0; 616 617 fail: 618 efx_remove_channels(efx); 619 return rc; 620 } 621 622 /* Channels are shutdown and reinitialised whilst the NIC is running 623 * to propagate configuration changes (mtu, checksum offload), or 624 * to clear hardware error conditions 625 */ 626 static void efx_start_datapath(struct efx_nic *efx) 627 { 628 struct efx_tx_queue *tx_queue; 629 struct efx_rx_queue *rx_queue; 630 struct efx_channel *channel; 631 632 /* Calculate the rx buffer allocation parameters required to 633 * support the current MTU, including padding for header 634 * alignment and overruns. 635 */ 636 efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + 637 EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + 638 efx->type->rx_buffer_hash_size + 639 efx->type->rx_buffer_padding); 640 efx->rx_buffer_order = get_order(efx->rx_buffer_len + 641 sizeof(struct efx_rx_page_state)); 642 643 /* We must keep at least one descriptor in a TX ring empty. 644 * We could avoid this when the queue size does not exactly 645 * match the hardware ring size, but it's not that important. 646 * Therefore we stop the queue when one more skb might fill 647 * the ring completely. We wake it when half way back to 648 * empty. 649 */ 650 efx->txq_stop_thresh = efx->txq_entries - efx_tx_max_skb_descs(efx); 651 efx->txq_wake_thresh = efx->txq_stop_thresh / 2; 652 653 /* Initialise the channels */ 654 efx_for_each_channel(channel, efx) { 655 efx_for_each_channel_tx_queue(tx_queue, channel) 656 efx_init_tx_queue(tx_queue); 657 658 /* The rx buffer allocation strategy is MTU dependent */ 659 efx_rx_strategy(channel); 660 661 efx_for_each_channel_rx_queue(rx_queue, channel) { 662 efx_init_rx_queue(rx_queue); 663 efx_nic_generate_fill_event(rx_queue); 664 } 665 666 WARN_ON(channel->rx_pkt != NULL); 667 efx_rx_strategy(channel); 668 } 669 670 if (netif_device_present(efx->net_dev)) 671 netif_tx_wake_all_queues(efx->net_dev); 672 } 673 674 static void efx_stop_datapath(struct efx_nic *efx) 675 { 676 struct efx_channel *channel; 677 struct efx_tx_queue *tx_queue; 678 struct efx_rx_queue *rx_queue; 679 struct pci_dev *dev = efx->pci_dev; 680 int rc; 681 682 EFX_ASSERT_RESET_SERIALISED(efx); 683 BUG_ON(efx->port_enabled); 684 685 /* Only perform flush if dma is enabled */ 686 if (dev->is_busmaster) { 687 rc = efx_nic_flush_queues(efx); 688 689 if (rc && EFX_WORKAROUND_7803(efx)) { 690 /* Schedule a reset to recover from the flush failure. The 691 * descriptor caches reference memory we're about to free, 692 * but falcon_reconfigure_mac_wrapper() won't reconnect 693 * the MACs because of the pending reset. */ 694 netif_err(efx, drv, efx->net_dev, 695 "Resetting to recover from flush failure\n"); 696 efx_schedule_reset(efx, RESET_TYPE_ALL); 697 } else if (rc) { 698 netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); 699 } else { 700 netif_dbg(efx, drv, efx->net_dev, 701 "successfully flushed all queues\n"); 702 } 703 } 704 705 efx_for_each_channel(channel, efx) { 706 /* RX packet processing is pipelined, so wait for the 707 * NAPI handler to complete. At least event queue 0 708 * might be kept active by non-data events, so don't 709 * use napi_synchronize() but actually disable NAPI 710 * temporarily. 711 */ 712 if (efx_channel_has_rx_queue(channel)) { 713 efx_stop_eventq(channel); 714 efx_start_eventq(channel); 715 } 716 717 efx_for_each_channel_rx_queue(rx_queue, channel) 718 efx_fini_rx_queue(rx_queue); 719 efx_for_each_possible_channel_tx_queue(tx_queue, channel) 720 efx_fini_tx_queue(tx_queue); 721 } 722 } 723 724 static void efx_remove_channel(struct efx_channel *channel) 725 { 726 struct efx_tx_queue *tx_queue; 727 struct efx_rx_queue *rx_queue; 728 729 netif_dbg(channel->efx, drv, channel->efx->net_dev, 730 "destroy chan %d\n", channel->channel); 731 732 efx_for_each_channel_rx_queue(rx_queue, channel) 733 efx_remove_rx_queue(rx_queue); 734 efx_for_each_possible_channel_tx_queue(tx_queue, channel) 735 efx_remove_tx_queue(tx_queue); 736 efx_remove_eventq(channel); 737 channel->type->post_remove(channel); 738 } 739 740 static void efx_remove_channels(struct efx_nic *efx) 741 { 742 struct efx_channel *channel; 743 744 efx_for_each_channel(channel, efx) 745 efx_remove_channel(channel); 746 } 747 748 int 749 efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries) 750 { 751 struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel; 752 u32 old_rxq_entries, old_txq_entries; 753 unsigned i, next_buffer_table = 0; 754 int rc; 755 756 rc = efx_check_disabled(efx); 757 if (rc) 758 return rc; 759 760 /* Not all channels should be reallocated. We must avoid 761 * reallocating their buffer table entries. 762 */ 763 efx_for_each_channel(channel, efx) { 764 struct efx_rx_queue *rx_queue; 765 struct efx_tx_queue *tx_queue; 766 767 if (channel->type->copy) 768 continue; 769 next_buffer_table = max(next_buffer_table, 770 channel->eventq.index + 771 channel->eventq.entries); 772 efx_for_each_channel_rx_queue(rx_queue, channel) 773 next_buffer_table = max(next_buffer_table, 774 rx_queue->rxd.index + 775 rx_queue->rxd.entries); 776 efx_for_each_channel_tx_queue(tx_queue, channel) 777 next_buffer_table = max(next_buffer_table, 778 tx_queue->txd.index + 779 tx_queue->txd.entries); 780 } 781 782 efx_device_detach_sync(efx); 783 efx_stop_all(efx); 784 efx_stop_interrupts(efx, true); 785 786 /* Clone channels (where possible) */ 787 memset(other_channel, 0, sizeof(other_channel)); 788 for (i = 0; i < efx->n_channels; i++) { 789 channel = efx->channel[i]; 790 if (channel->type->copy) 791 channel = channel->type->copy(channel); 792 if (!channel) { 793 rc = -ENOMEM; 794 goto out; 795 } 796 other_channel[i] = channel; 797 } 798 799 /* Swap entry counts and channel pointers */ 800 old_rxq_entries = efx->rxq_entries; 801 old_txq_entries = efx->txq_entries; 802 efx->rxq_entries = rxq_entries; 803 efx->txq_entries = txq_entries; 804 for (i = 0; i < efx->n_channels; i++) { 805 channel = efx->channel[i]; 806 efx->channel[i] = other_channel[i]; 807 other_channel[i] = channel; 808 } 809 810 /* Restart buffer table allocation */ 811 efx->next_buffer_table = next_buffer_table; 812 813 for (i = 0; i < efx->n_channels; i++) { 814 channel = efx->channel[i]; 815 if (!channel->type->copy) 816 continue; 817 rc = efx_probe_channel(channel); 818 if (rc) 819 goto rollback; 820 efx_init_napi_channel(efx->channel[i]); 821 } 822 823 out: 824 /* Destroy unused channel structures */ 825 for (i = 0; i < efx->n_channels; i++) { 826 channel = other_channel[i]; 827 if (channel && channel->type->copy) { 828 efx_fini_napi_channel(channel); 829 efx_remove_channel(channel); 830 kfree(channel); 831 } 832 } 833 834 efx_start_interrupts(efx, true); 835 efx_start_all(efx); 836 netif_device_attach(efx->net_dev); 837 return rc; 838 839 rollback: 840 /* Swap back */ 841 efx->rxq_entries = old_rxq_entries; 842 efx->txq_entries = old_txq_entries; 843 for (i = 0; i < efx->n_channels; i++) { 844 channel = efx->channel[i]; 845 efx->channel[i] = other_channel[i]; 846 other_channel[i] = channel; 847 } 848 goto out; 849 } 850 851 void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue) 852 { 853 mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100)); 854 } 855 856 static const struct efx_channel_type efx_default_channel_type = { 857 .pre_probe = efx_channel_dummy_op_int, 858 .post_remove = efx_channel_dummy_op_void, 859 .get_name = efx_get_channel_name, 860 .copy = efx_copy_channel, 861 .keep_eventq = false, 862 }; 863 864 int efx_channel_dummy_op_int(struct efx_channel *channel) 865 { 866 return 0; 867 } 868 869 void efx_channel_dummy_op_void(struct efx_channel *channel) 870 { 871 } 872 873 /************************************************************************** 874 * 875 * Port handling 876 * 877 **************************************************************************/ 878 879 /* This ensures that the kernel is kept informed (via 880 * netif_carrier_on/off) of the link status, and also maintains the 881 * link status's stop on the port's TX queue. 882 */ 883 void efx_link_status_changed(struct efx_nic *efx) 884 { 885 struct efx_link_state *link_state = &efx->link_state; 886 887 /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure 888 * that no events are triggered between unregister_netdev() and the 889 * driver unloading. A more general condition is that NETDEV_CHANGE 890 * can only be generated between NETDEV_UP and NETDEV_DOWN */ 891 if (!netif_running(efx->net_dev)) 892 return; 893 894 if (link_state->up != netif_carrier_ok(efx->net_dev)) { 895 efx->n_link_state_changes++; 896 897 if (link_state->up) 898 netif_carrier_on(efx->net_dev); 899 else 900 netif_carrier_off(efx->net_dev); 901 } 902 903 /* Status message for kernel log */ 904 if (link_state->up) 905 netif_info(efx, link, efx->net_dev, 906 "link up at %uMbps %s-duplex (MTU %d)%s\n", 907 link_state->speed, link_state->fd ? "full" : "half", 908 efx->net_dev->mtu, 909 (efx->promiscuous ? " [PROMISC]" : "")); 910 else 911 netif_info(efx, link, efx->net_dev, "link down\n"); 912 } 913 914 void efx_link_set_advertising(struct efx_nic *efx, u32 advertising) 915 { 916 efx->link_advertising = advertising; 917 if (advertising) { 918 if (advertising & ADVERTISED_Pause) 919 efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); 920 else 921 efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); 922 if (advertising & ADVERTISED_Asym_Pause) 923 efx->wanted_fc ^= EFX_FC_TX; 924 } 925 } 926 927 void efx_link_set_wanted_fc(struct efx_nic *efx, u8 wanted_fc) 928 { 929 efx->wanted_fc = wanted_fc; 930 if (efx->link_advertising) { 931 if (wanted_fc & EFX_FC_RX) 932 efx->link_advertising |= (ADVERTISED_Pause | 933 ADVERTISED_Asym_Pause); 934 else 935 efx->link_advertising &= ~(ADVERTISED_Pause | 936 ADVERTISED_Asym_Pause); 937 if (wanted_fc & EFX_FC_TX) 938 efx->link_advertising ^= ADVERTISED_Asym_Pause; 939 } 940 } 941 942 static void efx_fini_port(struct efx_nic *efx); 943 944 /* Push loopback/power/transmit disable settings to the PHY, and reconfigure 945 * the MAC appropriately. All other PHY configuration changes are pushed 946 * through phy_op->set_settings(), and pushed asynchronously to the MAC 947 * through efx_monitor(). 948 * 949 * Callers must hold the mac_lock 950 */ 951 int __efx_reconfigure_port(struct efx_nic *efx) 952 { 953 enum efx_phy_mode phy_mode; 954 int rc; 955 956 WARN_ON(!mutex_is_locked(&efx->mac_lock)); 957 958 /* Serialise the promiscuous flag with efx_set_rx_mode. */ 959 netif_addr_lock_bh(efx->net_dev); 960 netif_addr_unlock_bh(efx->net_dev); 961 962 /* Disable PHY transmit in mac level loopbacks */ 963 phy_mode = efx->phy_mode; 964 if (LOOPBACK_INTERNAL(efx)) 965 efx->phy_mode |= PHY_MODE_TX_DISABLED; 966 else 967 efx->phy_mode &= ~PHY_MODE_TX_DISABLED; 968 969 rc = efx->type->reconfigure_port(efx); 970 971 if (rc) 972 efx->phy_mode = phy_mode; 973 974 return rc; 975 } 976 977 /* Reinitialise the MAC to pick up new PHY settings, even if the port is 978 * disabled. */ 979 int efx_reconfigure_port(struct efx_nic *efx) 980 { 981 int rc; 982 983 EFX_ASSERT_RESET_SERIALISED(efx); 984 985 mutex_lock(&efx->mac_lock); 986 rc = __efx_reconfigure_port(efx); 987 mutex_unlock(&efx->mac_lock); 988 989 return rc; 990 } 991 992 /* Asynchronous work item for changing MAC promiscuity and multicast 993 * hash. Avoid a drain/rx_ingress enable by reconfiguring the current 994 * MAC directly. */ 995 static void efx_mac_work(struct work_struct *data) 996 { 997 struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); 998 999 mutex_lock(&efx->mac_lock); 1000 if (efx->port_enabled) 1001 efx->type->reconfigure_mac(efx); 1002 mutex_unlock(&efx->mac_lock); 1003 } 1004 1005 static int efx_probe_port(struct efx_nic *efx) 1006 { 1007 int rc; 1008 1009 netif_dbg(efx, probe, efx->net_dev, "create port\n"); 1010 1011 if (phy_flash_cfg) 1012 efx->phy_mode = PHY_MODE_SPECIAL; 1013 1014 /* Connect up MAC/PHY operations table */ 1015 rc = efx->type->probe_port(efx); 1016 if (rc) 1017 return rc; 1018 1019 /* Initialise MAC address to permanent address */ 1020 memcpy(efx->net_dev->dev_addr, efx->net_dev->perm_addr, ETH_ALEN); 1021 1022 return 0; 1023 } 1024 1025 static int efx_init_port(struct efx_nic *efx) 1026 { 1027 int rc; 1028 1029 netif_dbg(efx, drv, efx->net_dev, "init port\n"); 1030 1031 mutex_lock(&efx->mac_lock); 1032 1033 rc = efx->phy_op->init(efx); 1034 if (rc) 1035 goto fail1; 1036 1037 efx->port_initialized = true; 1038 1039 /* Reconfigure the MAC before creating dma queues (required for 1040 * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ 1041 efx->type->reconfigure_mac(efx); 1042 1043 /* Ensure the PHY advertises the correct flow control settings */ 1044 rc = efx->phy_op->reconfigure(efx); 1045 if (rc) 1046 goto fail2; 1047 1048 mutex_unlock(&efx->mac_lock); 1049 return 0; 1050 1051 fail2: 1052 efx->phy_op->fini(efx); 1053 fail1: 1054 mutex_unlock(&efx->mac_lock); 1055 return rc; 1056 } 1057 1058 static void efx_start_port(struct efx_nic *efx) 1059 { 1060 netif_dbg(efx, ifup, efx->net_dev, "start port\n"); 1061 BUG_ON(efx->port_enabled); 1062 1063 mutex_lock(&efx->mac_lock); 1064 efx->port_enabled = true; 1065 1066 /* efx_mac_work() might have been scheduled after efx_stop_port(), 1067 * and then cancelled by efx_flush_all() */ 1068 efx->type->reconfigure_mac(efx); 1069 1070 mutex_unlock(&efx->mac_lock); 1071 } 1072 1073 /* Prevent efx_mac_work() and efx_monitor() from working */ 1074 static void efx_stop_port(struct efx_nic *efx) 1075 { 1076 netif_dbg(efx, ifdown, efx->net_dev, "stop port\n"); 1077 1078 mutex_lock(&efx->mac_lock); 1079 efx->port_enabled = false; 1080 mutex_unlock(&efx->mac_lock); 1081 1082 /* Serialise against efx_set_multicast_list() */ 1083 netif_addr_lock_bh(efx->net_dev); 1084 netif_addr_unlock_bh(efx->net_dev); 1085 } 1086 1087 static void efx_fini_port(struct efx_nic *efx) 1088 { 1089 netif_dbg(efx, drv, efx->net_dev, "shut down port\n"); 1090 1091 if (!efx->port_initialized) 1092 return; 1093 1094 efx->phy_op->fini(efx); 1095 efx->port_initialized = false; 1096 1097 efx->link_state.up = false; 1098 efx_link_status_changed(efx); 1099 } 1100 1101 static void efx_remove_port(struct efx_nic *efx) 1102 { 1103 netif_dbg(efx, drv, efx->net_dev, "destroying port\n"); 1104 1105 efx->type->remove_port(efx); 1106 } 1107 1108 /************************************************************************** 1109 * 1110 * NIC handling 1111 * 1112 **************************************************************************/ 1113 1114 /* This configures the PCI device to enable I/O and DMA. */ 1115 static int efx_init_io(struct efx_nic *efx) 1116 { 1117 struct pci_dev *pci_dev = efx->pci_dev; 1118 dma_addr_t dma_mask = efx->type->max_dma_mask; 1119 int rc; 1120 1121 netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n"); 1122 1123 rc = pci_enable_device(pci_dev); 1124 if (rc) { 1125 netif_err(efx, probe, efx->net_dev, 1126 "failed to enable PCI device\n"); 1127 goto fail1; 1128 } 1129 1130 pci_set_master(pci_dev); 1131 1132 /* Set the PCI DMA mask. Try all possibilities from our 1133 * genuine mask down to 32 bits, because some architectures 1134 * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit 1135 * masks event though they reject 46 bit masks. 1136 */ 1137 while (dma_mask > 0x7fffffffUL) { 1138 if (dma_supported(&pci_dev->dev, dma_mask)) { 1139 rc = dma_set_mask(&pci_dev->dev, dma_mask); 1140 if (rc == 0) 1141 break; 1142 } 1143 dma_mask >>= 1; 1144 } 1145 if (rc) { 1146 netif_err(efx, probe, efx->net_dev, 1147 "could not find a suitable DMA mask\n"); 1148 goto fail2; 1149 } 1150 netif_dbg(efx, probe, efx->net_dev, 1151 "using DMA mask %llx\n", (unsigned long long) dma_mask); 1152 rc = dma_set_coherent_mask(&pci_dev->dev, dma_mask); 1153 if (rc) { 1154 /* dma_set_coherent_mask() is not *allowed* to 1155 * fail with a mask that dma_set_mask() accepted, 1156 * but just in case... 1157 */ 1158 netif_err(efx, probe, efx->net_dev, 1159 "failed to set consistent DMA mask\n"); 1160 goto fail2; 1161 } 1162 1163 efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR); 1164 rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc"); 1165 if (rc) { 1166 netif_err(efx, probe, efx->net_dev, 1167 "request for memory BAR failed\n"); 1168 rc = -EIO; 1169 goto fail3; 1170 } 1171 efx->membase = ioremap_nocache(efx->membase_phys, 1172 efx->type->mem_map_size); 1173 if (!efx->membase) { 1174 netif_err(efx, probe, efx->net_dev, 1175 "could not map memory BAR at %llx+%x\n", 1176 (unsigned long long)efx->membase_phys, 1177 efx->type->mem_map_size); 1178 rc = -ENOMEM; 1179 goto fail4; 1180 } 1181 netif_dbg(efx, probe, efx->net_dev, 1182 "memory BAR at %llx+%x (virtual %p)\n", 1183 (unsigned long long)efx->membase_phys, 1184 efx->type->mem_map_size, efx->membase); 1185 1186 return 0; 1187 1188 fail4: 1189 pci_release_region(efx->pci_dev, EFX_MEM_BAR); 1190 fail3: 1191 efx->membase_phys = 0; 1192 fail2: 1193 pci_disable_device(efx->pci_dev); 1194 fail1: 1195 return rc; 1196 } 1197 1198 static void efx_fini_io(struct efx_nic *efx) 1199 { 1200 netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n"); 1201 1202 if (efx->membase) { 1203 iounmap(efx->membase); 1204 efx->membase = NULL; 1205 } 1206 1207 if (efx->membase_phys) { 1208 pci_release_region(efx->pci_dev, EFX_MEM_BAR); 1209 efx->membase_phys = 0; 1210 } 1211 1212 pci_disable_device(efx->pci_dev); 1213 } 1214 1215 static unsigned int efx_wanted_parallelism(struct efx_nic *efx) 1216 { 1217 cpumask_var_t thread_mask; 1218 unsigned int count; 1219 int cpu; 1220 1221 if (rss_cpus) { 1222 count = rss_cpus; 1223 } else { 1224 if (unlikely(!zalloc_cpumask_var(&thread_mask, GFP_KERNEL))) { 1225 netif_warn(efx, probe, efx->net_dev, 1226 "RSS disabled due to allocation failure\n"); 1227 return 1; 1228 } 1229 1230 count = 0; 1231 for_each_online_cpu(cpu) { 1232 if (!cpumask_test_cpu(cpu, thread_mask)) { 1233 ++count; 1234 cpumask_or(thread_mask, thread_mask, 1235 topology_thread_cpumask(cpu)); 1236 } 1237 } 1238 1239 free_cpumask_var(thread_mask); 1240 } 1241 1242 /* If RSS is requested for the PF *and* VFs then we can't write RSS 1243 * table entries that are inaccessible to VFs 1244 */ 1245 if (efx_sriov_wanted(efx) && efx_vf_size(efx) > 1 && 1246 count > efx_vf_size(efx)) { 1247 netif_warn(efx, probe, efx->net_dev, 1248 "Reducing number of RSS channels from %u to %u for " 1249 "VF support. Increase vf-msix-limit to use more " 1250 "channels on the PF.\n", 1251 count, efx_vf_size(efx)); 1252 count = efx_vf_size(efx); 1253 } 1254 1255 return count; 1256 } 1257 1258 static int 1259 efx_init_rx_cpu_rmap(struct efx_nic *efx, struct msix_entry *xentries) 1260 { 1261 #ifdef CONFIG_RFS_ACCEL 1262 unsigned int i; 1263 int rc; 1264 1265 efx->net_dev->rx_cpu_rmap = alloc_irq_cpu_rmap(efx->n_rx_channels); 1266 if (!efx->net_dev->rx_cpu_rmap) 1267 return -ENOMEM; 1268 for (i = 0; i < efx->n_rx_channels; i++) { 1269 rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap, 1270 xentries[i].vector); 1271 if (rc) { 1272 free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); 1273 efx->net_dev->rx_cpu_rmap = NULL; 1274 return rc; 1275 } 1276 } 1277 #endif 1278 return 0; 1279 } 1280 1281 /* Probe the number and type of interrupts we are able to obtain, and 1282 * the resulting numbers of channels and RX queues. 1283 */ 1284 static int efx_probe_interrupts(struct efx_nic *efx) 1285 { 1286 unsigned int max_channels = 1287 min(efx->type->phys_addr_channels, EFX_MAX_CHANNELS); 1288 unsigned int extra_channels = 0; 1289 unsigned int i, j; 1290 int rc; 1291 1292 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) 1293 if (efx->extra_channel_type[i]) 1294 ++extra_channels; 1295 1296 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { 1297 struct msix_entry xentries[EFX_MAX_CHANNELS]; 1298 unsigned int n_channels; 1299 1300 n_channels = efx_wanted_parallelism(efx); 1301 if (separate_tx_channels) 1302 n_channels *= 2; 1303 n_channels += extra_channels; 1304 n_channels = min(n_channels, max_channels); 1305 1306 for (i = 0; i < n_channels; i++) 1307 xentries[i].entry = i; 1308 rc = pci_enable_msix(efx->pci_dev, xentries, n_channels); 1309 if (rc > 0) { 1310 netif_err(efx, drv, efx->net_dev, 1311 "WARNING: Insufficient MSI-X vectors" 1312 " available (%d < %u).\n", rc, n_channels); 1313 netif_err(efx, drv, efx->net_dev, 1314 "WARNING: Performance may be reduced.\n"); 1315 EFX_BUG_ON_PARANOID(rc >= n_channels); 1316 n_channels = rc; 1317 rc = pci_enable_msix(efx->pci_dev, xentries, 1318 n_channels); 1319 } 1320 1321 if (rc == 0) { 1322 efx->n_channels = n_channels; 1323 if (n_channels > extra_channels) 1324 n_channels -= extra_channels; 1325 if (separate_tx_channels) { 1326 efx->n_tx_channels = max(n_channels / 2, 1U); 1327 efx->n_rx_channels = max(n_channels - 1328 efx->n_tx_channels, 1329 1U); 1330 } else { 1331 efx->n_tx_channels = n_channels; 1332 efx->n_rx_channels = n_channels; 1333 } 1334 rc = efx_init_rx_cpu_rmap(efx, xentries); 1335 if (rc) { 1336 pci_disable_msix(efx->pci_dev); 1337 return rc; 1338 } 1339 for (i = 0; i < efx->n_channels; i++) 1340 efx_get_channel(efx, i)->irq = 1341 xentries[i].vector; 1342 } else { 1343 /* Fall back to single channel MSI */ 1344 efx->interrupt_mode = EFX_INT_MODE_MSI; 1345 netif_err(efx, drv, efx->net_dev, 1346 "could not enable MSI-X\n"); 1347 } 1348 } 1349 1350 /* Try single interrupt MSI */ 1351 if (efx->interrupt_mode == EFX_INT_MODE_MSI) { 1352 efx->n_channels = 1; 1353 efx->n_rx_channels = 1; 1354 efx->n_tx_channels = 1; 1355 rc = pci_enable_msi(efx->pci_dev); 1356 if (rc == 0) { 1357 efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; 1358 } else { 1359 netif_err(efx, drv, efx->net_dev, 1360 "could not enable MSI\n"); 1361 efx->interrupt_mode = EFX_INT_MODE_LEGACY; 1362 } 1363 } 1364 1365 /* Assume legacy interrupts */ 1366 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { 1367 efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); 1368 efx->n_rx_channels = 1; 1369 efx->n_tx_channels = 1; 1370 efx->legacy_irq = efx->pci_dev->irq; 1371 } 1372 1373 /* Assign extra channels if possible */ 1374 j = efx->n_channels; 1375 for (i = 0; i < EFX_MAX_EXTRA_CHANNELS; i++) { 1376 if (!efx->extra_channel_type[i]) 1377 continue; 1378 if (efx->interrupt_mode != EFX_INT_MODE_MSIX || 1379 efx->n_channels <= extra_channels) { 1380 efx->extra_channel_type[i]->handle_no_channel(efx); 1381 } else { 1382 --j; 1383 efx_get_channel(efx, j)->type = 1384 efx->extra_channel_type[i]; 1385 } 1386 } 1387 1388 /* RSS might be usable on VFs even if it is disabled on the PF */ 1389 efx->rss_spread = ((efx->n_rx_channels > 1 || !efx_sriov_wanted(efx)) ? 1390 efx->n_rx_channels : efx_vf_size(efx)); 1391 1392 return 0; 1393 } 1394 1395 /* Enable interrupts, then probe and start the event queues */ 1396 static void efx_start_interrupts(struct efx_nic *efx, bool may_keep_eventq) 1397 { 1398 struct efx_channel *channel; 1399 1400 BUG_ON(efx->state == STATE_DISABLED); 1401 1402 if (efx->legacy_irq) 1403 efx->legacy_irq_enabled = true; 1404 efx_nic_enable_interrupts(efx); 1405 1406 efx_for_each_channel(channel, efx) { 1407 if (!channel->type->keep_eventq || !may_keep_eventq) 1408 efx_init_eventq(channel); 1409 efx_start_eventq(channel); 1410 } 1411 1412 efx_mcdi_mode_event(efx); 1413 } 1414 1415 static void efx_stop_interrupts(struct efx_nic *efx, bool may_keep_eventq) 1416 { 1417 struct efx_channel *channel; 1418 1419 if (efx->state == STATE_DISABLED) 1420 return; 1421 1422 efx_mcdi_mode_poll(efx); 1423 1424 efx_nic_disable_interrupts(efx); 1425 if (efx->legacy_irq) { 1426 synchronize_irq(efx->legacy_irq); 1427 efx->legacy_irq_enabled = false; 1428 } 1429 1430 efx_for_each_channel(channel, efx) { 1431 if (channel->irq) 1432 synchronize_irq(channel->irq); 1433 1434 efx_stop_eventq(channel); 1435 if (!channel->type->keep_eventq || !may_keep_eventq) 1436 efx_fini_eventq(channel); 1437 } 1438 } 1439 1440 static void efx_remove_interrupts(struct efx_nic *efx) 1441 { 1442 struct efx_channel *channel; 1443 1444 /* Remove MSI/MSI-X interrupts */ 1445 efx_for_each_channel(channel, efx) 1446 channel->irq = 0; 1447 pci_disable_msi(efx->pci_dev); 1448 pci_disable_msix(efx->pci_dev); 1449 1450 /* Remove legacy interrupt */ 1451 efx->legacy_irq = 0; 1452 } 1453 1454 static void efx_set_channels(struct efx_nic *efx) 1455 { 1456 struct efx_channel *channel; 1457 struct efx_tx_queue *tx_queue; 1458 1459 efx->tx_channel_offset = 1460 separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0; 1461 1462 /* We need to mark which channels really have RX and TX 1463 * queues, and adjust the TX queue numbers if we have separate 1464 * RX-only and TX-only channels. 1465 */ 1466 efx_for_each_channel(channel, efx) { 1467 if (channel->channel < efx->n_rx_channels) 1468 channel->rx_queue.core_index = channel->channel; 1469 else 1470 channel->rx_queue.core_index = -1; 1471 1472 efx_for_each_channel_tx_queue(tx_queue, channel) 1473 tx_queue->queue -= (efx->tx_channel_offset * 1474 EFX_TXQ_TYPES); 1475 } 1476 } 1477 1478 static int efx_probe_nic(struct efx_nic *efx) 1479 { 1480 size_t i; 1481 int rc; 1482 1483 netif_dbg(efx, probe, efx->net_dev, "creating NIC\n"); 1484 1485 /* Carry out hardware-type specific initialisation */ 1486 rc = efx->type->probe(efx); 1487 if (rc) 1488 return rc; 1489 1490 /* Determine the number of channels and queues by trying to hook 1491 * in MSI-X interrupts. */ 1492 rc = efx_probe_interrupts(efx); 1493 if (rc) 1494 goto fail; 1495 1496 efx->type->dimension_resources(efx); 1497 1498 if (efx->n_channels > 1) 1499 get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key)); 1500 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++) 1501 efx->rx_indir_table[i] = 1502 ethtool_rxfh_indir_default(i, efx->rss_spread); 1503 1504 efx_set_channels(efx); 1505 netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); 1506 netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); 1507 1508 /* Initialise the interrupt moderation settings */ 1509 efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true, 1510 true); 1511 1512 return 0; 1513 1514 fail: 1515 efx->type->remove(efx); 1516 return rc; 1517 } 1518 1519 static void efx_remove_nic(struct efx_nic *efx) 1520 { 1521 netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n"); 1522 1523 efx_remove_interrupts(efx); 1524 efx->type->remove(efx); 1525 } 1526 1527 /************************************************************************** 1528 * 1529 * NIC startup/shutdown 1530 * 1531 *************************************************************************/ 1532 1533 static int efx_probe_all(struct efx_nic *efx) 1534 { 1535 int rc; 1536 1537 rc = efx_probe_nic(efx); 1538 if (rc) { 1539 netif_err(efx, probe, efx->net_dev, "failed to create NIC\n"); 1540 goto fail1; 1541 } 1542 1543 rc = efx_probe_port(efx); 1544 if (rc) { 1545 netif_err(efx, probe, efx->net_dev, "failed to create port\n"); 1546 goto fail2; 1547 } 1548 1549 BUILD_BUG_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_RXQ_MIN_ENT); 1550 if (WARN_ON(EFX_DEFAULT_DMAQ_SIZE < EFX_TXQ_MIN_ENT(efx))) { 1551 rc = -EINVAL; 1552 goto fail3; 1553 } 1554 efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE; 1555 1556 rc = efx_probe_filters(efx); 1557 if (rc) { 1558 netif_err(efx, probe, efx->net_dev, 1559 "failed to create filter tables\n"); 1560 goto fail3; 1561 } 1562 1563 rc = efx_probe_channels(efx); 1564 if (rc) 1565 goto fail4; 1566 1567 return 0; 1568 1569 fail4: 1570 efx_remove_filters(efx); 1571 fail3: 1572 efx_remove_port(efx); 1573 fail2: 1574 efx_remove_nic(efx); 1575 fail1: 1576 return rc; 1577 } 1578 1579 /* If the interface is supposed to be running but is not, start 1580 * the hardware and software data path, regular activity for the port 1581 * (MAC statistics, link polling, etc.) and schedule the port to be 1582 * reconfigured. Interrupts must already be enabled. This function 1583 * is safe to call multiple times, so long as the NIC is not disabled. 1584 * Requires the RTNL lock. 1585 */ 1586 static void efx_start_all(struct efx_nic *efx) 1587 { 1588 EFX_ASSERT_RESET_SERIALISED(efx); 1589 BUG_ON(efx->state == STATE_DISABLED); 1590 1591 /* Check that it is appropriate to restart the interface. All 1592 * of these flags are safe to read under just the rtnl lock */ 1593 if (efx->port_enabled || !netif_running(efx->net_dev)) 1594 return; 1595 1596 efx_start_port(efx); 1597 efx_start_datapath(efx); 1598 1599 /* Start the hardware monitor if there is one. Otherwise (we're link 1600 * event driven), we have to poll the PHY because after an event queue 1601 * flush, we could have a missed a link state change */ 1602 if (efx->type->monitor != NULL) { 1603 queue_delayed_work(efx->workqueue, &efx->monitor_work, 1604 efx_monitor_interval); 1605 } else { 1606 mutex_lock(&efx->mac_lock); 1607 if (efx->phy_op->poll(efx)) 1608 efx_link_status_changed(efx); 1609 mutex_unlock(&efx->mac_lock); 1610 } 1611 1612 efx->type->start_stats(efx); 1613 } 1614 1615 /* Flush all delayed work. Should only be called when no more delayed work 1616 * will be scheduled. This doesn't flush pending online resets (efx_reset), 1617 * since we're holding the rtnl_lock at this point. */ 1618 static void efx_flush_all(struct efx_nic *efx) 1619 { 1620 /* Make sure the hardware monitor and event self-test are stopped */ 1621 cancel_delayed_work_sync(&efx->monitor_work); 1622 efx_selftest_async_cancel(efx); 1623 /* Stop scheduled port reconfigurations */ 1624 cancel_work_sync(&efx->mac_work); 1625 } 1626 1627 /* Quiesce the hardware and software data path, and regular activity 1628 * for the port without bringing the link down. Safe to call multiple 1629 * times with the NIC in almost any state, but interrupts should be 1630 * enabled. Requires the RTNL lock. 1631 */ 1632 static void efx_stop_all(struct efx_nic *efx) 1633 { 1634 EFX_ASSERT_RESET_SERIALISED(efx); 1635 1636 /* port_enabled can be read safely under the rtnl lock */ 1637 if (!efx->port_enabled) 1638 return; 1639 1640 efx->type->stop_stats(efx); 1641 efx_stop_port(efx); 1642 1643 /* Flush efx_mac_work(), refill_workqueue, monitor_work */ 1644 efx_flush_all(efx); 1645 1646 /* Stop the kernel transmit interface. This is only valid if 1647 * the device is stopped or detached; otherwise the watchdog 1648 * may fire immediately. 1649 */ 1650 WARN_ON(netif_running(efx->net_dev) && 1651 netif_device_present(efx->net_dev)); 1652 netif_tx_disable(efx->net_dev); 1653 1654 efx_stop_datapath(efx); 1655 } 1656 1657 static void efx_remove_all(struct efx_nic *efx) 1658 { 1659 efx_remove_channels(efx); 1660 efx_remove_filters(efx); 1661 efx_remove_port(efx); 1662 efx_remove_nic(efx); 1663 } 1664 1665 /************************************************************************** 1666 * 1667 * Interrupt moderation 1668 * 1669 **************************************************************************/ 1670 1671 static unsigned int irq_mod_ticks(unsigned int usecs, unsigned int quantum_ns) 1672 { 1673 if (usecs == 0) 1674 return 0; 1675 if (usecs * 1000 < quantum_ns) 1676 return 1; /* never round down to 0 */ 1677 return usecs * 1000 / quantum_ns; 1678 } 1679 1680 /* Set interrupt moderation parameters */ 1681 int efx_init_irq_moderation(struct efx_nic *efx, unsigned int tx_usecs, 1682 unsigned int rx_usecs, bool rx_adaptive, 1683 bool rx_may_override_tx) 1684 { 1685 struct efx_channel *channel; 1686 unsigned int irq_mod_max = DIV_ROUND_UP(efx->type->timer_period_max * 1687 efx->timer_quantum_ns, 1688 1000); 1689 unsigned int tx_ticks; 1690 unsigned int rx_ticks; 1691 1692 EFX_ASSERT_RESET_SERIALISED(efx); 1693 1694 if (tx_usecs > irq_mod_max || rx_usecs > irq_mod_max) 1695 return -EINVAL; 1696 1697 tx_ticks = irq_mod_ticks(tx_usecs, efx->timer_quantum_ns); 1698 rx_ticks = irq_mod_ticks(rx_usecs, efx->timer_quantum_ns); 1699 1700 if (tx_ticks != rx_ticks && efx->tx_channel_offset == 0 && 1701 !rx_may_override_tx) { 1702 netif_err(efx, drv, efx->net_dev, "Channels are shared. " 1703 "RX and TX IRQ moderation must be equal\n"); 1704 return -EINVAL; 1705 } 1706 1707 efx->irq_rx_adaptive = rx_adaptive; 1708 efx->irq_rx_moderation = rx_ticks; 1709 efx_for_each_channel(channel, efx) { 1710 if (efx_channel_has_rx_queue(channel)) 1711 channel->irq_moderation = rx_ticks; 1712 else if (efx_channel_has_tx_queues(channel)) 1713 channel->irq_moderation = tx_ticks; 1714 } 1715 1716 return 0; 1717 } 1718 1719 void efx_get_irq_moderation(struct efx_nic *efx, unsigned int *tx_usecs, 1720 unsigned int *rx_usecs, bool *rx_adaptive) 1721 { 1722 /* We must round up when converting ticks to microseconds 1723 * because we round down when converting the other way. 1724 */ 1725 1726 *rx_adaptive = efx->irq_rx_adaptive; 1727 *rx_usecs = DIV_ROUND_UP(efx->irq_rx_moderation * 1728 efx->timer_quantum_ns, 1729 1000); 1730 1731 /* If channels are shared between RX and TX, so is IRQ 1732 * moderation. Otherwise, IRQ moderation is the same for all 1733 * TX channels and is not adaptive. 1734 */ 1735 if (efx->tx_channel_offset == 0) 1736 *tx_usecs = *rx_usecs; 1737 else 1738 *tx_usecs = DIV_ROUND_UP( 1739 efx->channel[efx->tx_channel_offset]->irq_moderation * 1740 efx->timer_quantum_ns, 1741 1000); 1742 } 1743 1744 /************************************************************************** 1745 * 1746 * Hardware monitor 1747 * 1748 **************************************************************************/ 1749 1750 /* Run periodically off the general workqueue */ 1751 static void efx_monitor(struct work_struct *data) 1752 { 1753 struct efx_nic *efx = container_of(data, struct efx_nic, 1754 monitor_work.work); 1755 1756 netif_vdbg(efx, timer, efx->net_dev, 1757 "hardware monitor executing on CPU %d\n", 1758 raw_smp_processor_id()); 1759 BUG_ON(efx->type->monitor == NULL); 1760 1761 /* If the mac_lock is already held then it is likely a port 1762 * reconfiguration is already in place, which will likely do 1763 * most of the work of monitor() anyway. */ 1764 if (mutex_trylock(&efx->mac_lock)) { 1765 if (efx->port_enabled) 1766 efx->type->monitor(efx); 1767 mutex_unlock(&efx->mac_lock); 1768 } 1769 1770 queue_delayed_work(efx->workqueue, &efx->monitor_work, 1771 efx_monitor_interval); 1772 } 1773 1774 /************************************************************************** 1775 * 1776 * ioctls 1777 * 1778 *************************************************************************/ 1779 1780 /* Net device ioctl 1781 * Context: process, rtnl_lock() held. 1782 */ 1783 static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) 1784 { 1785 struct efx_nic *efx = netdev_priv(net_dev); 1786 struct mii_ioctl_data *data = if_mii(ifr); 1787 1788 if (cmd == SIOCSHWTSTAMP) 1789 return efx_ptp_ioctl(efx, ifr, cmd); 1790 1791 /* Convert phy_id from older PRTAD/DEVAD format */ 1792 if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && 1793 (data->phy_id & 0xfc00) == 0x0400) 1794 data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; 1795 1796 return mdio_mii_ioctl(&efx->mdio, data, cmd); 1797 } 1798 1799 /************************************************************************** 1800 * 1801 * NAPI interface 1802 * 1803 **************************************************************************/ 1804 1805 static void efx_init_napi_channel(struct efx_channel *channel) 1806 { 1807 struct efx_nic *efx = channel->efx; 1808 1809 channel->napi_dev = efx->net_dev; 1810 netif_napi_add(channel->napi_dev, &channel->napi_str, 1811 efx_poll, napi_weight); 1812 } 1813 1814 static void efx_init_napi(struct efx_nic *efx) 1815 { 1816 struct efx_channel *channel; 1817 1818 efx_for_each_channel(channel, efx) 1819 efx_init_napi_channel(channel); 1820 } 1821 1822 static void efx_fini_napi_channel(struct efx_channel *channel) 1823 { 1824 if (channel->napi_dev) 1825 netif_napi_del(&channel->napi_str); 1826 channel->napi_dev = NULL; 1827 } 1828 1829 static void efx_fini_napi(struct efx_nic *efx) 1830 { 1831 struct efx_channel *channel; 1832 1833 efx_for_each_channel(channel, efx) 1834 efx_fini_napi_channel(channel); 1835 } 1836 1837 /************************************************************************** 1838 * 1839 * Kernel netpoll interface 1840 * 1841 *************************************************************************/ 1842 1843 #ifdef CONFIG_NET_POLL_CONTROLLER 1844 1845 /* Although in the common case interrupts will be disabled, this is not 1846 * guaranteed. However, all our work happens inside the NAPI callback, 1847 * so no locking is required. 1848 */ 1849 static void efx_netpoll(struct net_device *net_dev) 1850 { 1851 struct efx_nic *efx = netdev_priv(net_dev); 1852 struct efx_channel *channel; 1853 1854 efx_for_each_channel(channel, efx) 1855 efx_schedule_channel(channel); 1856 } 1857 1858 #endif 1859 1860 /************************************************************************** 1861 * 1862 * Kernel net device interface 1863 * 1864 *************************************************************************/ 1865 1866 /* Context: process, rtnl_lock() held. */ 1867 static int efx_net_open(struct net_device *net_dev) 1868 { 1869 struct efx_nic *efx = netdev_priv(net_dev); 1870 int rc; 1871 1872 netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n", 1873 raw_smp_processor_id()); 1874 1875 rc = efx_check_disabled(efx); 1876 if (rc) 1877 return rc; 1878 if (efx->phy_mode & PHY_MODE_SPECIAL) 1879 return -EBUSY; 1880 if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL)) 1881 return -EIO; 1882 1883 /* Notify the kernel of the link state polled during driver load, 1884 * before the monitor starts running */ 1885 efx_link_status_changed(efx); 1886 1887 efx_start_all(efx); 1888 efx_selftest_async_start(efx); 1889 return 0; 1890 } 1891 1892 /* Context: process, rtnl_lock() held. 1893 * Note that the kernel will ignore our return code; this method 1894 * should really be a void. 1895 */ 1896 static int efx_net_stop(struct net_device *net_dev) 1897 { 1898 struct efx_nic *efx = netdev_priv(net_dev); 1899 1900 netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n", 1901 raw_smp_processor_id()); 1902 1903 /* Stop the device and flush all the channels */ 1904 efx_stop_all(efx); 1905 1906 return 0; 1907 } 1908 1909 /* Context: process, dev_base_lock or RTNL held, non-blocking. */ 1910 static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev, 1911 struct rtnl_link_stats64 *stats) 1912 { 1913 struct efx_nic *efx = netdev_priv(net_dev); 1914 struct efx_mac_stats *mac_stats = &efx->mac_stats; 1915 1916 spin_lock_bh(&efx->stats_lock); 1917 1918 efx->type->update_stats(efx); 1919 1920 stats->rx_packets = mac_stats->rx_packets; 1921 stats->tx_packets = mac_stats->tx_packets; 1922 stats->rx_bytes = mac_stats->rx_bytes; 1923 stats->tx_bytes = mac_stats->tx_bytes; 1924 stats->rx_dropped = efx->n_rx_nodesc_drop_cnt; 1925 stats->multicast = mac_stats->rx_multicast; 1926 stats->collisions = mac_stats->tx_collision; 1927 stats->rx_length_errors = (mac_stats->rx_gtjumbo + 1928 mac_stats->rx_length_error); 1929 stats->rx_crc_errors = mac_stats->rx_bad; 1930 stats->rx_frame_errors = mac_stats->rx_align_error; 1931 stats->rx_fifo_errors = mac_stats->rx_overflow; 1932 stats->rx_missed_errors = mac_stats->rx_missed; 1933 stats->tx_window_errors = mac_stats->tx_late_collision; 1934 1935 stats->rx_errors = (stats->rx_length_errors + 1936 stats->rx_crc_errors + 1937 stats->rx_frame_errors + 1938 mac_stats->rx_symbol_error); 1939 stats->tx_errors = (stats->tx_window_errors + 1940 mac_stats->tx_bad); 1941 1942 spin_unlock_bh(&efx->stats_lock); 1943 1944 return stats; 1945 } 1946 1947 /* Context: netif_tx_lock held, BHs disabled. */ 1948 static void efx_watchdog(struct net_device *net_dev) 1949 { 1950 struct efx_nic *efx = netdev_priv(net_dev); 1951 1952 netif_err(efx, tx_err, efx->net_dev, 1953 "TX stuck with port_enabled=%d: resetting channels\n", 1954 efx->port_enabled); 1955 1956 efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); 1957 } 1958 1959 1960 /* Context: process, rtnl_lock() held. */ 1961 static int efx_change_mtu(struct net_device *net_dev, int new_mtu) 1962 { 1963 struct efx_nic *efx = netdev_priv(net_dev); 1964 int rc; 1965 1966 rc = efx_check_disabled(efx); 1967 if (rc) 1968 return rc; 1969 if (new_mtu > EFX_MAX_MTU) 1970 return -EINVAL; 1971 1972 netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu); 1973 1974 efx_device_detach_sync(efx); 1975 efx_stop_all(efx); 1976 1977 mutex_lock(&efx->mac_lock); 1978 net_dev->mtu = new_mtu; 1979 efx->type->reconfigure_mac(efx); 1980 mutex_unlock(&efx->mac_lock); 1981 1982 efx_start_all(efx); 1983 netif_device_attach(efx->net_dev); 1984 return 0; 1985 } 1986 1987 static int efx_set_mac_address(struct net_device *net_dev, void *data) 1988 { 1989 struct efx_nic *efx = netdev_priv(net_dev); 1990 struct sockaddr *addr = data; 1991 char *new_addr = addr->sa_data; 1992 1993 if (!is_valid_ether_addr(new_addr)) { 1994 netif_err(efx, drv, efx->net_dev, 1995 "invalid ethernet MAC address requested: %pM\n", 1996 new_addr); 1997 return -EADDRNOTAVAIL; 1998 } 1999 2000 memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); 2001 efx_sriov_mac_address_changed(efx); 2002 2003 /* Reconfigure the MAC */ 2004 mutex_lock(&efx->mac_lock); 2005 efx->type->reconfigure_mac(efx); 2006 mutex_unlock(&efx->mac_lock); 2007 2008 return 0; 2009 } 2010 2011 /* Context: netif_addr_lock held, BHs disabled. */ 2012 static void efx_set_rx_mode(struct net_device *net_dev) 2013 { 2014 struct efx_nic *efx = netdev_priv(net_dev); 2015 struct netdev_hw_addr *ha; 2016 union efx_multicast_hash *mc_hash = &efx->multicast_hash; 2017 u32 crc; 2018 int bit; 2019 2020 efx->promiscuous = !!(net_dev->flags & IFF_PROMISC); 2021 2022 /* Build multicast hash table */ 2023 if (efx->promiscuous || (net_dev->flags & IFF_ALLMULTI)) { 2024 memset(mc_hash, 0xff, sizeof(*mc_hash)); 2025 } else { 2026 memset(mc_hash, 0x00, sizeof(*mc_hash)); 2027 netdev_for_each_mc_addr(ha, net_dev) { 2028 crc = ether_crc_le(ETH_ALEN, ha->addr); 2029 bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); 2030 __set_bit_le(bit, mc_hash); 2031 } 2032 2033 /* Broadcast packets go through the multicast hash filter. 2034 * ether_crc_le() of the broadcast address is 0xbe2612ff 2035 * so we always add bit 0xff to the mask. 2036 */ 2037 __set_bit_le(0xff, mc_hash); 2038 } 2039 2040 if (efx->port_enabled) 2041 queue_work(efx->workqueue, &efx->mac_work); 2042 /* Otherwise efx_start_port() will do this */ 2043 } 2044 2045 static int efx_set_features(struct net_device *net_dev, netdev_features_t data) 2046 { 2047 struct efx_nic *efx = netdev_priv(net_dev); 2048 2049 /* If disabling RX n-tuple filtering, clear existing filters */ 2050 if (net_dev->features & ~data & NETIF_F_NTUPLE) 2051 efx_filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL); 2052 2053 return 0; 2054 } 2055 2056 static const struct net_device_ops efx_netdev_ops = { 2057 .ndo_open = efx_net_open, 2058 .ndo_stop = efx_net_stop, 2059 .ndo_get_stats64 = efx_net_stats, 2060 .ndo_tx_timeout = efx_watchdog, 2061 .ndo_start_xmit = efx_hard_start_xmit, 2062 .ndo_validate_addr = eth_validate_addr, 2063 .ndo_do_ioctl = efx_ioctl, 2064 .ndo_change_mtu = efx_change_mtu, 2065 .ndo_set_mac_address = efx_set_mac_address, 2066 .ndo_set_rx_mode = efx_set_rx_mode, 2067 .ndo_set_features = efx_set_features, 2068 #ifdef CONFIG_SFC_SRIOV 2069 .ndo_set_vf_mac = efx_sriov_set_vf_mac, 2070 .ndo_set_vf_vlan = efx_sriov_set_vf_vlan, 2071 .ndo_set_vf_spoofchk = efx_sriov_set_vf_spoofchk, 2072 .ndo_get_vf_config = efx_sriov_get_vf_config, 2073 #endif 2074 #ifdef CONFIG_NET_POLL_CONTROLLER 2075 .ndo_poll_controller = efx_netpoll, 2076 #endif 2077 .ndo_setup_tc = efx_setup_tc, 2078 #ifdef CONFIG_RFS_ACCEL 2079 .ndo_rx_flow_steer = efx_filter_rfs, 2080 #endif 2081 }; 2082 2083 static void efx_update_name(struct efx_nic *efx) 2084 { 2085 strcpy(efx->name, efx->net_dev->name); 2086 efx_mtd_rename(efx); 2087 efx_set_channel_names(efx); 2088 } 2089 2090 static int efx_netdev_event(struct notifier_block *this, 2091 unsigned long event, void *ptr) 2092 { 2093 struct net_device *net_dev = ptr; 2094 2095 if (net_dev->netdev_ops == &efx_netdev_ops && 2096 event == NETDEV_CHANGENAME) 2097 efx_update_name(netdev_priv(net_dev)); 2098 2099 return NOTIFY_DONE; 2100 } 2101 2102 static struct notifier_block efx_netdev_notifier = { 2103 .notifier_call = efx_netdev_event, 2104 }; 2105 2106 static ssize_t 2107 show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) 2108 { 2109 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 2110 return sprintf(buf, "%d\n", efx->phy_type); 2111 } 2112 static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL); 2113 2114 static int efx_register_netdev(struct efx_nic *efx) 2115 { 2116 struct net_device *net_dev = efx->net_dev; 2117 struct efx_channel *channel; 2118 int rc; 2119 2120 net_dev->watchdog_timeo = 5 * HZ; 2121 net_dev->irq = efx->pci_dev->irq; 2122 net_dev->netdev_ops = &efx_netdev_ops; 2123 SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); 2124 net_dev->gso_max_segs = EFX_TSO_MAX_SEGS; 2125 2126 rtnl_lock(); 2127 2128 /* Enable resets to be scheduled and check whether any were 2129 * already requested. If so, the NIC is probably hosed so we 2130 * abort. 2131 */ 2132 efx->state = STATE_READY; 2133 smp_mb(); /* ensure we change state before checking reset_pending */ 2134 if (efx->reset_pending) { 2135 netif_err(efx, probe, efx->net_dev, 2136 "aborting probe due to scheduled reset\n"); 2137 rc = -EIO; 2138 goto fail_locked; 2139 } 2140 2141 rc = dev_alloc_name(net_dev, net_dev->name); 2142 if (rc < 0) 2143 goto fail_locked; 2144 efx_update_name(efx); 2145 2146 /* Always start with carrier off; PHY events will detect the link */ 2147 netif_carrier_off(net_dev); 2148 2149 rc = register_netdevice(net_dev); 2150 if (rc) 2151 goto fail_locked; 2152 2153 efx_for_each_channel(channel, efx) { 2154 struct efx_tx_queue *tx_queue; 2155 efx_for_each_channel_tx_queue(tx_queue, channel) 2156 efx_init_tx_queue_core_txq(tx_queue); 2157 } 2158 2159 rtnl_unlock(); 2160 2161 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); 2162 if (rc) { 2163 netif_err(efx, drv, efx->net_dev, 2164 "failed to init net dev attributes\n"); 2165 goto fail_registered; 2166 } 2167 2168 return 0; 2169 2170 fail_registered: 2171 rtnl_lock(); 2172 unregister_netdevice(net_dev); 2173 fail_locked: 2174 efx->state = STATE_UNINIT; 2175 rtnl_unlock(); 2176 netif_err(efx, drv, efx->net_dev, "could not register net dev\n"); 2177 return rc; 2178 } 2179 2180 static void efx_unregister_netdev(struct efx_nic *efx) 2181 { 2182 struct efx_channel *channel; 2183 struct efx_tx_queue *tx_queue; 2184 2185 if (!efx->net_dev) 2186 return; 2187 2188 BUG_ON(netdev_priv(efx->net_dev) != efx); 2189 2190 /* Free up any skbs still remaining. This has to happen before 2191 * we try to unregister the netdev as running their destructors 2192 * may be needed to get the device ref. count to 0. */ 2193 efx_for_each_channel(channel, efx) { 2194 efx_for_each_channel_tx_queue(tx_queue, channel) 2195 efx_release_tx_buffers(tx_queue); 2196 } 2197 2198 strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); 2199 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); 2200 2201 rtnl_lock(); 2202 unregister_netdevice(efx->net_dev); 2203 efx->state = STATE_UNINIT; 2204 rtnl_unlock(); 2205 } 2206 2207 /************************************************************************** 2208 * 2209 * Device reset and suspend 2210 * 2211 **************************************************************************/ 2212 2213 /* Tears down the entire software state and most of the hardware state 2214 * before reset. */ 2215 void efx_reset_down(struct efx_nic *efx, enum reset_type method) 2216 { 2217 EFX_ASSERT_RESET_SERIALISED(efx); 2218 2219 efx_stop_all(efx); 2220 efx_stop_interrupts(efx, false); 2221 2222 mutex_lock(&efx->mac_lock); 2223 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) 2224 efx->phy_op->fini(efx); 2225 efx->type->fini(efx); 2226 } 2227 2228 /* This function will always ensure that the locks acquired in 2229 * efx_reset_down() are released. A failure return code indicates 2230 * that we were unable to reinitialise the hardware, and the 2231 * driver should be disabled. If ok is false, then the rx and tx 2232 * engines are not restarted, pending a RESET_DISABLE. */ 2233 int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok) 2234 { 2235 int rc; 2236 2237 EFX_ASSERT_RESET_SERIALISED(efx); 2238 2239 rc = efx->type->init(efx); 2240 if (rc) { 2241 netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n"); 2242 goto fail; 2243 } 2244 2245 if (!ok) 2246 goto fail; 2247 2248 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { 2249 rc = efx->phy_op->init(efx); 2250 if (rc) 2251 goto fail; 2252 if (efx->phy_op->reconfigure(efx)) 2253 netif_err(efx, drv, efx->net_dev, 2254 "could not restore PHY settings\n"); 2255 } 2256 2257 efx->type->reconfigure_mac(efx); 2258 2259 efx_start_interrupts(efx, false); 2260 efx_restore_filters(efx); 2261 efx_sriov_reset(efx); 2262 2263 mutex_unlock(&efx->mac_lock); 2264 2265 efx_start_all(efx); 2266 2267 return 0; 2268 2269 fail: 2270 efx->port_initialized = false; 2271 2272 mutex_unlock(&efx->mac_lock); 2273 2274 return rc; 2275 } 2276 2277 /* Reset the NIC using the specified method. Note that the reset may 2278 * fail, in which case the card will be left in an unusable state. 2279 * 2280 * Caller must hold the rtnl_lock. 2281 */ 2282 int efx_reset(struct efx_nic *efx, enum reset_type method) 2283 { 2284 int rc, rc2; 2285 bool disabled; 2286 2287 netif_info(efx, drv, efx->net_dev, "resetting (%s)\n", 2288 RESET_TYPE(method)); 2289 2290 efx_device_detach_sync(efx); 2291 efx_reset_down(efx, method); 2292 2293 rc = efx->type->reset(efx, method); 2294 if (rc) { 2295 netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n"); 2296 goto out; 2297 } 2298 2299 /* Clear flags for the scopes we covered. We assume the NIC and 2300 * driver are now quiescent so that there is no race here. 2301 */ 2302 efx->reset_pending &= -(1 << (method + 1)); 2303 2304 /* Reinitialise bus-mastering, which may have been turned off before 2305 * the reset was scheduled. This is still appropriate, even in the 2306 * RESET_TYPE_DISABLE since this driver generally assumes the hardware 2307 * can respond to requests. */ 2308 pci_set_master(efx->pci_dev); 2309 2310 out: 2311 /* Leave device stopped if necessary */ 2312 disabled = rc || method == RESET_TYPE_DISABLE; 2313 rc2 = efx_reset_up(efx, method, !disabled); 2314 if (rc2) { 2315 disabled = true; 2316 if (!rc) 2317 rc = rc2; 2318 } 2319 2320 if (disabled) { 2321 dev_close(efx->net_dev); 2322 netif_err(efx, drv, efx->net_dev, "has been disabled\n"); 2323 efx->state = STATE_DISABLED; 2324 } else { 2325 netif_dbg(efx, drv, efx->net_dev, "reset complete\n"); 2326 netif_device_attach(efx->net_dev); 2327 } 2328 return rc; 2329 } 2330 2331 /* The worker thread exists so that code that cannot sleep can 2332 * schedule a reset for later. 2333 */ 2334 static void efx_reset_work(struct work_struct *data) 2335 { 2336 struct efx_nic *efx = container_of(data, struct efx_nic, reset_work); 2337 unsigned long pending = ACCESS_ONCE(efx->reset_pending); 2338 2339 if (!pending) 2340 return; 2341 2342 rtnl_lock(); 2343 2344 /* We checked the state in efx_schedule_reset() but it may 2345 * have changed by now. Now that we have the RTNL lock, 2346 * it cannot change again. 2347 */ 2348 if (efx->state == STATE_READY) 2349 (void)efx_reset(efx, fls(pending) - 1); 2350 2351 rtnl_unlock(); 2352 } 2353 2354 void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) 2355 { 2356 enum reset_type method; 2357 2358 switch (type) { 2359 case RESET_TYPE_INVISIBLE: 2360 case RESET_TYPE_ALL: 2361 case RESET_TYPE_WORLD: 2362 case RESET_TYPE_DISABLE: 2363 method = type; 2364 netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n", 2365 RESET_TYPE(method)); 2366 break; 2367 default: 2368 method = efx->type->map_reset_reason(type); 2369 netif_dbg(efx, drv, efx->net_dev, 2370 "scheduling %s reset for %s\n", 2371 RESET_TYPE(method), RESET_TYPE(type)); 2372 break; 2373 } 2374 2375 set_bit(method, &efx->reset_pending); 2376 smp_mb(); /* ensure we change reset_pending before checking state */ 2377 2378 /* If we're not READY then just leave the flags set as the cue 2379 * to abort probing or reschedule the reset later. 2380 */ 2381 if (ACCESS_ONCE(efx->state) != STATE_READY) 2382 return; 2383 2384 /* efx_process_channel() will no longer read events once a 2385 * reset is scheduled. So switch back to poll'd MCDI completions. */ 2386 efx_mcdi_mode_poll(efx); 2387 2388 queue_work(reset_workqueue, &efx->reset_work); 2389 } 2390 2391 /************************************************************************** 2392 * 2393 * List of NICs we support 2394 * 2395 **************************************************************************/ 2396 2397 /* PCI device ID table */ 2398 static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = { 2399 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 2400 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0), 2401 .driver_data = (unsigned long) &falcon_a1_nic_type}, 2402 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 2403 PCI_DEVICE_ID_SOLARFLARE_SFC4000B), 2404 .driver_data = (unsigned long) &falcon_b0_nic_type}, 2405 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0803), /* SFC9020 */ 2406 .driver_data = (unsigned long) &siena_a0_nic_type}, 2407 {PCI_DEVICE(PCI_VENDOR_ID_SOLARFLARE, 0x0813), /* SFL9021 */ 2408 .driver_data = (unsigned long) &siena_a0_nic_type}, 2409 {0} /* end of list */ 2410 }; 2411 2412 /************************************************************************** 2413 * 2414 * Dummy PHY/MAC operations 2415 * 2416 * Can be used for some unimplemented operations 2417 * Needed so all function pointers are valid and do not have to be tested 2418 * before use 2419 * 2420 **************************************************************************/ 2421 int efx_port_dummy_op_int(struct efx_nic *efx) 2422 { 2423 return 0; 2424 } 2425 void efx_port_dummy_op_void(struct efx_nic *efx) {} 2426 2427 static bool efx_port_dummy_op_poll(struct efx_nic *efx) 2428 { 2429 return false; 2430 } 2431 2432 static const struct efx_phy_operations efx_dummy_phy_operations = { 2433 .init = efx_port_dummy_op_int, 2434 .reconfigure = efx_port_dummy_op_int, 2435 .poll = efx_port_dummy_op_poll, 2436 .fini = efx_port_dummy_op_void, 2437 }; 2438 2439 /************************************************************************** 2440 * 2441 * Data housekeeping 2442 * 2443 **************************************************************************/ 2444 2445 /* This zeroes out and then fills in the invariants in a struct 2446 * efx_nic (including all sub-structures). 2447 */ 2448 static int efx_init_struct(struct efx_nic *efx, 2449 struct pci_dev *pci_dev, struct net_device *net_dev) 2450 { 2451 int i; 2452 2453 /* Initialise common structures */ 2454 spin_lock_init(&efx->biu_lock); 2455 #ifdef CONFIG_SFC_MTD 2456 INIT_LIST_HEAD(&efx->mtd_list); 2457 #endif 2458 INIT_WORK(&efx->reset_work, efx_reset_work); 2459 INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); 2460 INIT_DELAYED_WORK(&efx->selftest_work, efx_selftest_async_work); 2461 efx->pci_dev = pci_dev; 2462 efx->msg_enable = debug; 2463 efx->state = STATE_UNINIT; 2464 strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); 2465 2466 efx->net_dev = net_dev; 2467 spin_lock_init(&efx->stats_lock); 2468 mutex_init(&efx->mac_lock); 2469 efx->phy_op = &efx_dummy_phy_operations; 2470 efx->mdio.dev = net_dev; 2471 INIT_WORK(&efx->mac_work, efx_mac_work); 2472 init_waitqueue_head(&efx->flush_wq); 2473 2474 for (i = 0; i < EFX_MAX_CHANNELS; i++) { 2475 efx->channel[i] = efx_alloc_channel(efx, i, NULL); 2476 if (!efx->channel[i]) 2477 goto fail; 2478 } 2479 2480 EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); 2481 2482 /* Higher numbered interrupt modes are less capable! */ 2483 efx->interrupt_mode = max(efx->type->max_interrupt_mode, 2484 interrupt_mode); 2485 2486 /* Would be good to use the net_dev name, but we're too early */ 2487 snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", 2488 pci_name(pci_dev)); 2489 efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); 2490 if (!efx->workqueue) 2491 goto fail; 2492 2493 return 0; 2494 2495 fail: 2496 efx_fini_struct(efx); 2497 return -ENOMEM; 2498 } 2499 2500 static void efx_fini_struct(struct efx_nic *efx) 2501 { 2502 int i; 2503 2504 for (i = 0; i < EFX_MAX_CHANNELS; i++) 2505 kfree(efx->channel[i]); 2506 2507 if (efx->workqueue) { 2508 destroy_workqueue(efx->workqueue); 2509 efx->workqueue = NULL; 2510 } 2511 } 2512 2513 /************************************************************************** 2514 * 2515 * PCI interface 2516 * 2517 **************************************************************************/ 2518 2519 /* Main body of final NIC shutdown code 2520 * This is called only at module unload (or hotplug removal). 2521 */ 2522 static void efx_pci_remove_main(struct efx_nic *efx) 2523 { 2524 /* Flush reset_work. It can no longer be scheduled since we 2525 * are not READY. 2526 */ 2527 BUG_ON(efx->state == STATE_READY); 2528 cancel_work_sync(&efx->reset_work); 2529 2530 #ifdef CONFIG_RFS_ACCEL 2531 free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); 2532 efx->net_dev->rx_cpu_rmap = NULL; 2533 #endif 2534 efx_stop_interrupts(efx, false); 2535 efx_nic_fini_interrupt(efx); 2536 efx_fini_port(efx); 2537 efx->type->fini(efx); 2538 efx_fini_napi(efx); 2539 efx_remove_all(efx); 2540 } 2541 2542 /* Final NIC shutdown 2543 * This is called only at module unload (or hotplug removal). 2544 */ 2545 static void efx_pci_remove(struct pci_dev *pci_dev) 2546 { 2547 struct efx_nic *efx; 2548 2549 efx = pci_get_drvdata(pci_dev); 2550 if (!efx) 2551 return; 2552 2553 /* Mark the NIC as fini, then stop the interface */ 2554 rtnl_lock(); 2555 dev_close(efx->net_dev); 2556 efx_stop_interrupts(efx, false); 2557 rtnl_unlock(); 2558 2559 efx_sriov_fini(efx); 2560 efx_unregister_netdev(efx); 2561 2562 efx_mtd_remove(efx); 2563 2564 efx_pci_remove_main(efx); 2565 2566 efx_fini_io(efx); 2567 netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n"); 2568 2569 efx_fini_struct(efx); 2570 pci_set_drvdata(pci_dev, NULL); 2571 free_netdev(efx->net_dev); 2572 }; 2573 2574 /* NIC VPD information 2575 * Called during probe to display the part number of the 2576 * installed NIC. VPD is potentially very large but this should 2577 * always appear within the first 512 bytes. 2578 */ 2579 #define SFC_VPD_LEN 512 2580 static void efx_print_product_vpd(struct efx_nic *efx) 2581 { 2582 struct pci_dev *dev = efx->pci_dev; 2583 char vpd_data[SFC_VPD_LEN]; 2584 ssize_t vpd_size; 2585 int i, j; 2586 2587 /* Get the vpd data from the device */ 2588 vpd_size = pci_read_vpd(dev, 0, sizeof(vpd_data), vpd_data); 2589 if (vpd_size <= 0) { 2590 netif_err(efx, drv, efx->net_dev, "Unable to read VPD\n"); 2591 return; 2592 } 2593 2594 /* Get the Read only section */ 2595 i = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA); 2596 if (i < 0) { 2597 netif_err(efx, drv, efx->net_dev, "VPD Read-only not found\n"); 2598 return; 2599 } 2600 2601 j = pci_vpd_lrdt_size(&vpd_data[i]); 2602 i += PCI_VPD_LRDT_TAG_SIZE; 2603 if (i + j > vpd_size) 2604 j = vpd_size - i; 2605 2606 /* Get the Part number */ 2607 i = pci_vpd_find_info_keyword(vpd_data, i, j, "PN"); 2608 if (i < 0) { 2609 netif_err(efx, drv, efx->net_dev, "Part number not found\n"); 2610 return; 2611 } 2612 2613 j = pci_vpd_info_field_size(&vpd_data[i]); 2614 i += PCI_VPD_INFO_FLD_HDR_SIZE; 2615 if (i + j > vpd_size) { 2616 netif_err(efx, drv, efx->net_dev, "Incomplete part number\n"); 2617 return; 2618 } 2619 2620 netif_info(efx, drv, efx->net_dev, 2621 "Part Number : %.*s\n", j, &vpd_data[i]); 2622 } 2623 2624 2625 /* Main body of NIC initialisation 2626 * This is called at module load (or hotplug insertion, theoretically). 2627 */ 2628 static int efx_pci_probe_main(struct efx_nic *efx) 2629 { 2630 int rc; 2631 2632 /* Do start-of-day initialisation */ 2633 rc = efx_probe_all(efx); 2634 if (rc) 2635 goto fail1; 2636 2637 efx_init_napi(efx); 2638 2639 rc = efx->type->init(efx); 2640 if (rc) { 2641 netif_err(efx, probe, efx->net_dev, 2642 "failed to initialise NIC\n"); 2643 goto fail3; 2644 } 2645 2646 rc = efx_init_port(efx); 2647 if (rc) { 2648 netif_err(efx, probe, efx->net_dev, 2649 "failed to initialise port\n"); 2650 goto fail4; 2651 } 2652 2653 rc = efx_nic_init_interrupt(efx); 2654 if (rc) 2655 goto fail5; 2656 efx_start_interrupts(efx, false); 2657 2658 return 0; 2659 2660 fail5: 2661 efx_fini_port(efx); 2662 fail4: 2663 efx->type->fini(efx); 2664 fail3: 2665 efx_fini_napi(efx); 2666 efx_remove_all(efx); 2667 fail1: 2668 return rc; 2669 } 2670 2671 /* NIC initialisation 2672 * 2673 * This is called at module load (or hotplug insertion, 2674 * theoretically). It sets up PCI mappings, resets the NIC, 2675 * sets up and registers the network devices with the kernel and hooks 2676 * the interrupt service routine. It does not prepare the device for 2677 * transmission; this is left to the first time one of the network 2678 * interfaces is brought up (i.e. efx_net_open). 2679 */ 2680 static int efx_pci_probe(struct pci_dev *pci_dev, 2681 const struct pci_device_id *entry) 2682 { 2683 struct net_device *net_dev; 2684 struct efx_nic *efx; 2685 int rc; 2686 2687 /* Allocate and initialise a struct net_device and struct efx_nic */ 2688 net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES, 2689 EFX_MAX_RX_QUEUES); 2690 if (!net_dev) 2691 return -ENOMEM; 2692 efx = netdev_priv(net_dev); 2693 efx->type = (const struct efx_nic_type *) entry->driver_data; 2694 net_dev->features |= (efx->type->offload_features | NETIF_F_SG | 2695 NETIF_F_HIGHDMA | NETIF_F_TSO | 2696 NETIF_F_RXCSUM); 2697 if (efx->type->offload_features & NETIF_F_V6_CSUM) 2698 net_dev->features |= NETIF_F_TSO6; 2699 /* Mask for features that also apply to VLAN devices */ 2700 net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | 2701 NETIF_F_HIGHDMA | NETIF_F_ALL_TSO | 2702 NETIF_F_RXCSUM); 2703 /* All offloads can be toggled */ 2704 net_dev->hw_features = net_dev->features & ~NETIF_F_HIGHDMA; 2705 pci_set_drvdata(pci_dev, efx); 2706 SET_NETDEV_DEV(net_dev, &pci_dev->dev); 2707 rc = efx_init_struct(efx, pci_dev, net_dev); 2708 if (rc) 2709 goto fail1; 2710 2711 netif_info(efx, probe, efx->net_dev, 2712 "Solarflare NIC detected\n"); 2713 2714 efx_print_product_vpd(efx); 2715 2716 /* Set up basic I/O (BAR mappings etc) */ 2717 rc = efx_init_io(efx); 2718 if (rc) 2719 goto fail2; 2720 2721 rc = efx_pci_probe_main(efx); 2722 if (rc) 2723 goto fail3; 2724 2725 rc = efx_register_netdev(efx); 2726 if (rc) 2727 goto fail4; 2728 2729 rc = efx_sriov_init(efx); 2730 if (rc) 2731 netif_err(efx, probe, efx->net_dev, 2732 "SR-IOV can't be enabled rc %d\n", rc); 2733 2734 netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n"); 2735 2736 /* Try to create MTDs, but allow this to fail */ 2737 rtnl_lock(); 2738 rc = efx_mtd_probe(efx); 2739 rtnl_unlock(); 2740 if (rc) 2741 netif_warn(efx, probe, efx->net_dev, 2742 "failed to create MTDs (%d)\n", rc); 2743 2744 return 0; 2745 2746 fail4: 2747 efx_pci_remove_main(efx); 2748 fail3: 2749 efx_fini_io(efx); 2750 fail2: 2751 efx_fini_struct(efx); 2752 fail1: 2753 pci_set_drvdata(pci_dev, NULL); 2754 WARN_ON(rc > 0); 2755 netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc); 2756 free_netdev(net_dev); 2757 return rc; 2758 } 2759 2760 static int efx_pm_freeze(struct device *dev) 2761 { 2762 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 2763 2764 rtnl_lock(); 2765 2766 if (efx->state != STATE_DISABLED) { 2767 efx->state = STATE_UNINIT; 2768 2769 efx_device_detach_sync(efx); 2770 2771 efx_stop_all(efx); 2772 efx_stop_interrupts(efx, false); 2773 } 2774 2775 rtnl_unlock(); 2776 2777 return 0; 2778 } 2779 2780 static int efx_pm_thaw(struct device *dev) 2781 { 2782 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); 2783 2784 rtnl_lock(); 2785 2786 if (efx->state != STATE_DISABLED) { 2787 efx_start_interrupts(efx, false); 2788 2789 mutex_lock(&efx->mac_lock); 2790 efx->phy_op->reconfigure(efx); 2791 mutex_unlock(&efx->mac_lock); 2792 2793 efx_start_all(efx); 2794 2795 netif_device_attach(efx->net_dev); 2796 2797 efx->state = STATE_READY; 2798 2799 efx->type->resume_wol(efx); 2800 } 2801 2802 rtnl_unlock(); 2803 2804 /* Reschedule any quenched resets scheduled during efx_pm_freeze() */ 2805 queue_work(reset_workqueue, &efx->reset_work); 2806 2807 return 0; 2808 } 2809 2810 static int efx_pm_poweroff(struct device *dev) 2811 { 2812 struct pci_dev *pci_dev = to_pci_dev(dev); 2813 struct efx_nic *efx = pci_get_drvdata(pci_dev); 2814 2815 efx->type->fini(efx); 2816 2817 efx->reset_pending = 0; 2818 2819 pci_save_state(pci_dev); 2820 return pci_set_power_state(pci_dev, PCI_D3hot); 2821 } 2822 2823 /* Used for both resume and restore */ 2824 static int efx_pm_resume(struct device *dev) 2825 { 2826 struct pci_dev *pci_dev = to_pci_dev(dev); 2827 struct efx_nic *efx = pci_get_drvdata(pci_dev); 2828 int rc; 2829 2830 rc = pci_set_power_state(pci_dev, PCI_D0); 2831 if (rc) 2832 return rc; 2833 pci_restore_state(pci_dev); 2834 rc = pci_enable_device(pci_dev); 2835 if (rc) 2836 return rc; 2837 pci_set_master(efx->pci_dev); 2838 rc = efx->type->reset(efx, RESET_TYPE_ALL); 2839 if (rc) 2840 return rc; 2841 rc = efx->type->init(efx); 2842 if (rc) 2843 return rc; 2844 efx_pm_thaw(dev); 2845 return 0; 2846 } 2847 2848 static int efx_pm_suspend(struct device *dev) 2849 { 2850 int rc; 2851 2852 efx_pm_freeze(dev); 2853 rc = efx_pm_poweroff(dev); 2854 if (rc) 2855 efx_pm_resume(dev); 2856 return rc; 2857 } 2858 2859 static const struct dev_pm_ops efx_pm_ops = { 2860 .suspend = efx_pm_suspend, 2861 .resume = efx_pm_resume, 2862 .freeze = efx_pm_freeze, 2863 .thaw = efx_pm_thaw, 2864 .poweroff = efx_pm_poweroff, 2865 .restore = efx_pm_resume, 2866 }; 2867 2868 static struct pci_driver efx_pci_driver = { 2869 .name = KBUILD_MODNAME, 2870 .id_table = efx_pci_table, 2871 .probe = efx_pci_probe, 2872 .remove = efx_pci_remove, 2873 .driver.pm = &efx_pm_ops, 2874 }; 2875 2876 /************************************************************************** 2877 * 2878 * Kernel module interface 2879 * 2880 *************************************************************************/ 2881 2882 module_param(interrupt_mode, uint, 0444); 2883 MODULE_PARM_DESC(interrupt_mode, 2884 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); 2885 2886 static int __init efx_init_module(void) 2887 { 2888 int rc; 2889 2890 printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); 2891 2892 rc = register_netdevice_notifier(&efx_netdev_notifier); 2893 if (rc) 2894 goto err_notifier; 2895 2896 rc = efx_init_sriov(); 2897 if (rc) 2898 goto err_sriov; 2899 2900 reset_workqueue = create_singlethread_workqueue("sfc_reset"); 2901 if (!reset_workqueue) { 2902 rc = -ENOMEM; 2903 goto err_reset; 2904 } 2905 2906 rc = pci_register_driver(&efx_pci_driver); 2907 if (rc < 0) 2908 goto err_pci; 2909 2910 return 0; 2911 2912 err_pci: 2913 destroy_workqueue(reset_workqueue); 2914 err_reset: 2915 efx_fini_sriov(); 2916 err_sriov: 2917 unregister_netdevice_notifier(&efx_netdev_notifier); 2918 err_notifier: 2919 return rc; 2920 } 2921 2922 static void __exit efx_exit_module(void) 2923 { 2924 printk(KERN_INFO "Solarflare NET driver unloading\n"); 2925 2926 pci_unregister_driver(&efx_pci_driver); 2927 destroy_workqueue(reset_workqueue); 2928 efx_fini_sriov(); 2929 unregister_netdevice_notifier(&efx_netdev_notifier); 2930 2931 } 2932 2933 module_init(efx_init_module); 2934 module_exit(efx_exit_module); 2935 2936 MODULE_AUTHOR("Solarflare Communications and " 2937 "Michael Brown <mbrown@fensystems.co.uk>"); 2938 MODULE_DESCRIPTION("Solarflare Communications network driver"); 2939 MODULE_LICENSE("GPL"); 2940 MODULE_DEVICE_TABLE(pci, efx_pci_table); 2941