1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet AVB device driver 3 * 4 * Copyright (C) 2014-2019 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * Based on the SuperH Ethernet driver 9 */ 10 11 #include <linux/cache.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_vlan.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/module.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/of.h> 24 #include <linux/of_mdio.h> 25 #include <linux/of_net.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/slab.h> 29 #include <linux/spinlock.h> 30 #include <linux/reset.h> 31 #include <linux/math64.h> 32 #include <net/ip.h> 33 #include <net/page_pool/helpers.h> 34 35 #include "ravb.h" 36 37 #define RAVB_DEF_MSG_ENABLE \ 38 (NETIF_MSG_LINK | \ 39 NETIF_MSG_TIMER | \ 40 NETIF_MSG_RX_ERR | \ 41 NETIF_MSG_TX_ERR) 42 43 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 44 u32 set) 45 { 46 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 47 } 48 49 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 50 { 51 int i; 52 53 for (i = 0; i < 10000; i++) { 54 if ((ravb_read(ndev, reg) & mask) == value) 55 return 0; 56 udelay(10); 57 } 58 return -ETIMEDOUT; 59 } 60 61 static int ravb_set_opmode(struct net_device *ndev, u32 opmode) 62 { 63 u32 csr_ops = 1U << (opmode & CCC_OPC); 64 u32 ccc_mask = CCC_OPC; 65 int error; 66 67 /* If gPTP active in config mode is supported it needs to be configured 68 * along with CSEL and operating mode in the same access. This is a 69 * hardware limitation. 70 */ 71 if (opmode & CCC_GAC) 72 ccc_mask |= CCC_GAC | CCC_CSEL; 73 74 /* Set operating mode */ 75 ravb_modify(ndev, CCC, ccc_mask, opmode); 76 /* Check if the operating mode is changed to the requested one */ 77 error = ravb_wait(ndev, CSR, CSR_OPS, csr_ops); 78 if (error) { 79 netdev_err(ndev, "failed to switch device to requested mode (%u)\n", 80 opmode & CCC_OPC); 81 } 82 83 return error; 84 } 85 86 static void ravb_set_rate_gbeth(struct net_device *ndev) 87 { 88 struct ravb_private *priv = netdev_priv(ndev); 89 90 switch (priv->speed) { 91 case 10: /* 10BASE */ 92 ravb_write(ndev, GBETH_GECMR_SPEED_10, GECMR); 93 break; 94 case 100: /* 100BASE */ 95 ravb_write(ndev, GBETH_GECMR_SPEED_100, GECMR); 96 break; 97 case 1000: /* 1000BASE */ 98 ravb_write(ndev, GBETH_GECMR_SPEED_1000, GECMR); 99 break; 100 } 101 } 102 103 static void ravb_set_rate_rcar(struct net_device *ndev) 104 { 105 struct ravb_private *priv = netdev_priv(ndev); 106 107 switch (priv->speed) { 108 case 100: /* 100BASE */ 109 ravb_write(ndev, GECMR_SPEED_100, GECMR); 110 break; 111 case 1000: /* 1000BASE */ 112 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 113 break; 114 } 115 } 116 117 /* Get MAC address from the MAC address registers 118 * 119 * Ethernet AVB device doesn't have ROM for MAC address. 120 * This function gets the MAC address that was used by a bootloader. 121 */ 122 static void ravb_read_mac_address(struct device_node *np, 123 struct net_device *ndev) 124 { 125 int ret; 126 127 ret = of_get_ethdev_address(np, ndev); 128 if (ret) { 129 u32 mahr = ravb_read(ndev, MAHR); 130 u32 malr = ravb_read(ndev, MALR); 131 u8 addr[ETH_ALEN]; 132 133 addr[0] = (mahr >> 24) & 0xFF; 134 addr[1] = (mahr >> 16) & 0xFF; 135 addr[2] = (mahr >> 8) & 0xFF; 136 addr[3] = (mahr >> 0) & 0xFF; 137 addr[4] = (malr >> 8) & 0xFF; 138 addr[5] = (malr >> 0) & 0xFF; 139 eth_hw_addr_set(ndev, addr); 140 } 141 } 142 143 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 144 { 145 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 146 mdiobb); 147 148 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 149 } 150 151 /* MDC pin control */ 152 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 153 { 154 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 155 } 156 157 /* Data I/O pin control */ 158 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 159 { 160 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 161 } 162 163 /* Set data bit */ 164 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 165 { 166 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 167 } 168 169 /* Get data bit */ 170 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 171 { 172 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 173 mdiobb); 174 175 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 176 } 177 178 /* MDIO bus control struct */ 179 static const struct mdiobb_ops bb_ops = { 180 .owner = THIS_MODULE, 181 .set_mdc = ravb_set_mdc, 182 .set_mdio_dir = ravb_set_mdio_dir, 183 .set_mdio_data = ravb_set_mdio_data, 184 .get_mdio_data = ravb_get_mdio_data, 185 }; 186 187 static struct ravb_rx_desc * 188 ravb_rx_get_desc(struct ravb_private *priv, unsigned int q, 189 unsigned int i) 190 { 191 return priv->rx_ring[q].raw + priv->info->rx_desc_size * i; 192 } 193 194 /* Free TX skb function for AVB-IP */ 195 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 196 { 197 struct ravb_private *priv = netdev_priv(ndev); 198 struct net_device_stats *stats = &priv->stats[q]; 199 unsigned int num_tx_desc = priv->num_tx_desc; 200 struct ravb_tx_desc *desc; 201 unsigned int entry; 202 int free_num = 0; 203 u32 size; 204 205 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 206 bool txed; 207 208 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 209 num_tx_desc); 210 desc = &priv->tx_ring[q][entry]; 211 txed = desc->die_dt == DT_FEMPTY; 212 if (free_txed_only && !txed) 213 break; 214 /* Descriptor type must be checked before all other reads */ 215 dma_rmb(); 216 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 217 /* Free the original skb. */ 218 if (priv->tx_skb[q][entry / num_tx_desc]) { 219 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 220 size, DMA_TO_DEVICE); 221 /* Last packet descriptor? */ 222 if (entry % num_tx_desc == num_tx_desc - 1) { 223 entry /= num_tx_desc; 224 dev_kfree_skb_any(priv->tx_skb[q][entry]); 225 priv->tx_skb[q][entry] = NULL; 226 if (txed) 227 stats->tx_packets++; 228 } 229 free_num++; 230 } 231 if (txed) 232 stats->tx_bytes += size; 233 desc->die_dt = DT_EEMPTY; 234 } 235 return free_num; 236 } 237 238 static void ravb_rx_ring_free(struct net_device *ndev, int q) 239 { 240 struct ravb_private *priv = netdev_priv(ndev); 241 unsigned int ring_size; 242 243 if (!priv->rx_ring[q].raw) 244 return; 245 246 ring_size = priv->info->rx_desc_size * (priv->num_rx_ring[q] + 1); 247 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q].raw, 248 priv->rx_desc_dma[q]); 249 priv->rx_ring[q].raw = NULL; 250 } 251 252 /* Free skb's and DMA buffers for Ethernet AVB */ 253 static void ravb_ring_free(struct net_device *ndev, int q) 254 { 255 struct ravb_private *priv = netdev_priv(ndev); 256 unsigned int num_tx_desc = priv->num_tx_desc; 257 unsigned int ring_size; 258 unsigned int i; 259 260 ravb_rx_ring_free(ndev, q); 261 262 if (priv->tx_ring[q]) { 263 ravb_tx_free(ndev, q, false); 264 265 ring_size = sizeof(struct ravb_tx_desc) * 266 (priv->num_tx_ring[q] * num_tx_desc + 1); 267 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 268 priv->tx_desc_dma[q]); 269 priv->tx_ring[q] = NULL; 270 } 271 272 /* Free RX buffers */ 273 for (i = 0; i < priv->num_rx_ring[q]; i++) { 274 if (priv->rx_buffers[q][i].page) 275 page_pool_put_page(priv->rx_pool[q], 276 priv->rx_buffers[q][i].page, 277 0, true); 278 } 279 kfree(priv->rx_buffers[q]); 280 priv->rx_buffers[q] = NULL; 281 page_pool_destroy(priv->rx_pool[q]); 282 283 /* Free aligned TX buffers */ 284 kfree(priv->tx_align[q]); 285 priv->tx_align[q] = NULL; 286 287 /* Free TX skb ringbuffer. 288 * SKBs are freed by ravb_tx_free() call above. 289 */ 290 kfree(priv->tx_skb[q]); 291 priv->tx_skb[q] = NULL; 292 } 293 294 static int 295 ravb_alloc_rx_buffer(struct net_device *ndev, int q, u32 entry, gfp_t gfp_mask, 296 struct ravb_rx_desc *rx_desc) 297 { 298 struct ravb_private *priv = netdev_priv(ndev); 299 const struct ravb_hw_info *info = priv->info; 300 struct ravb_rx_buffer *rx_buff; 301 dma_addr_t dma_addr; 302 unsigned int size; 303 304 rx_buff = &priv->rx_buffers[q][entry]; 305 size = info->rx_buffer_size; 306 rx_buff->page = page_pool_alloc(priv->rx_pool[q], &rx_buff->offset, 307 &size, gfp_mask); 308 if (unlikely(!rx_buff->page)) { 309 /* We just set the data size to 0 for a failed mapping which 310 * should prevent DMA from happening... 311 */ 312 rx_desc->ds_cc = cpu_to_le16(0); 313 return -ENOMEM; 314 } 315 316 dma_addr = page_pool_get_dma_addr(rx_buff->page) + rx_buff->offset; 317 dma_sync_single_for_device(ndev->dev.parent, dma_addr, 318 info->rx_buffer_size, DMA_FROM_DEVICE); 319 rx_desc->dptr = cpu_to_le32(dma_addr); 320 321 /* The end of the RX buffer is used to store skb shared data, so we need 322 * to ensure that the hardware leaves enough space for this. 323 */ 324 rx_desc->ds_cc = cpu_to_le16(info->rx_buffer_size - 325 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) - 326 ETH_FCS_LEN + sizeof(__sum16)); 327 return 0; 328 } 329 330 static u32 331 ravb_rx_ring_refill(struct net_device *ndev, int q, u32 count, gfp_t gfp_mask) 332 { 333 struct ravb_private *priv = netdev_priv(ndev); 334 struct ravb_rx_desc *rx_desc; 335 u32 i, entry; 336 337 for (i = 0; i < count; i++) { 338 entry = (priv->dirty_rx[q] + i) % priv->num_rx_ring[q]; 339 rx_desc = ravb_rx_get_desc(priv, q, entry); 340 341 if (!priv->rx_buffers[q][entry].page) { 342 if (unlikely(ravb_alloc_rx_buffer(ndev, q, entry, 343 gfp_mask, rx_desc))) 344 break; 345 } 346 /* Descriptor type must be set after all the above writes */ 347 dma_wmb(); 348 rx_desc->die_dt = DT_FEMPTY; 349 } 350 351 return i; 352 } 353 354 /* Format skb and descriptor buffer for Ethernet AVB */ 355 static void ravb_ring_format(struct net_device *ndev, int q) 356 { 357 struct ravb_private *priv = netdev_priv(ndev); 358 unsigned int num_tx_desc = priv->num_tx_desc; 359 struct ravb_rx_desc *rx_desc; 360 struct ravb_tx_desc *tx_desc; 361 struct ravb_desc *desc; 362 unsigned int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 363 num_tx_desc; 364 unsigned int i; 365 366 priv->cur_rx[q] = 0; 367 priv->cur_tx[q] = 0; 368 priv->dirty_rx[q] = 0; 369 priv->dirty_tx[q] = 0; 370 371 /* Regular RX descriptors have already been initialized by 372 * ravb_rx_ring_refill(), we just need to initialize the final link 373 * descriptor. 374 */ 375 rx_desc = ravb_rx_get_desc(priv, q, priv->num_rx_ring[q]); 376 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 377 rx_desc->die_dt = DT_LINKFIX; /* type */ 378 379 memset(priv->tx_ring[q], 0, tx_ring_size); 380 /* Build TX ring buffer */ 381 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 382 i++, tx_desc++) { 383 tx_desc->die_dt = DT_EEMPTY; 384 if (num_tx_desc > 1) { 385 tx_desc++; 386 tx_desc->die_dt = DT_EEMPTY; 387 } 388 } 389 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 390 tx_desc->die_dt = DT_LINKFIX; /* type */ 391 392 /* RX descriptor base address for best effort */ 393 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 394 desc->die_dt = DT_LINKFIX; /* type */ 395 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 396 397 /* TX descriptor base address for best effort */ 398 desc = &priv->desc_bat[q]; 399 desc->die_dt = DT_LINKFIX; /* type */ 400 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 401 } 402 403 static void *ravb_alloc_rx_desc(struct net_device *ndev, int q) 404 { 405 struct ravb_private *priv = netdev_priv(ndev); 406 unsigned int ring_size; 407 408 ring_size = priv->info->rx_desc_size * (priv->num_rx_ring[q] + 1); 409 410 priv->rx_ring[q].raw = dma_alloc_coherent(ndev->dev.parent, ring_size, 411 &priv->rx_desc_dma[q], 412 GFP_KERNEL); 413 414 return priv->rx_ring[q].raw; 415 } 416 417 /* Init skb and descriptor buffer for Ethernet AVB */ 418 static int ravb_ring_init(struct net_device *ndev, int q) 419 { 420 struct ravb_private *priv = netdev_priv(ndev); 421 unsigned int num_tx_desc = priv->num_tx_desc; 422 struct page_pool_params params = { 423 .order = 0, 424 .flags = PP_FLAG_DMA_MAP, 425 .pool_size = priv->num_rx_ring[q], 426 .nid = NUMA_NO_NODE, 427 .dev = ndev->dev.parent, 428 .dma_dir = DMA_FROM_DEVICE, 429 }; 430 unsigned int ring_size; 431 u32 num_filled; 432 433 /* Allocate RX page pool and buffers */ 434 priv->rx_pool[q] = page_pool_create(¶ms); 435 if (IS_ERR(priv->rx_pool[q])) 436 goto error; 437 438 /* Allocate RX buffers */ 439 priv->rx_buffers[q] = kzalloc_objs(*priv->rx_buffers[q], 440 priv->num_rx_ring[q]); 441 if (!priv->rx_buffers[q]) 442 goto error; 443 444 /* Allocate TX skb rings */ 445 priv->tx_skb[q] = kzalloc_objs(*priv->tx_skb[q], priv->num_tx_ring[q]); 446 if (!priv->tx_skb[q]) 447 goto error; 448 449 /* Allocate all RX descriptors. */ 450 if (!ravb_alloc_rx_desc(ndev, q)) 451 goto error; 452 453 /* Populate RX ring buffer. */ 454 priv->dirty_rx[q] = 0; 455 ring_size = priv->info->rx_desc_size * priv->num_rx_ring[q]; 456 memset(priv->rx_ring[q].raw, 0, ring_size); 457 num_filled = ravb_rx_ring_refill(ndev, q, priv->num_rx_ring[q], 458 GFP_KERNEL); 459 if (num_filled != priv->num_rx_ring[q]) 460 goto error; 461 462 if (num_tx_desc > 1) { 463 /* Allocate rings for the aligned buffers */ 464 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 465 DPTR_ALIGN - 1, GFP_KERNEL); 466 if (!priv->tx_align[q]) 467 goto error; 468 } 469 470 /* Allocate all TX descriptors. */ 471 ring_size = sizeof(struct ravb_tx_desc) * 472 (priv->num_tx_ring[q] * num_tx_desc + 1); 473 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 474 &priv->tx_desc_dma[q], 475 GFP_KERNEL); 476 if (!priv->tx_ring[q]) 477 goto error; 478 479 return 0; 480 481 error: 482 ravb_ring_free(ndev, q); 483 484 return -ENOMEM; 485 } 486 487 static void ravb_csum_init_gbeth(struct net_device *ndev) 488 { 489 bool tx_enable = ndev->features & NETIF_F_HW_CSUM; 490 bool rx_enable = ndev->features & NETIF_F_RXCSUM; 491 492 if (!(tx_enable || rx_enable)) 493 goto done; 494 495 ravb_write(ndev, 0, CSR0); 496 if (ravb_wait(ndev, CSR0, CSR0_TPE | CSR0_RPE, 0)) { 497 netdev_err(ndev, "Timeout enabling hardware checksum\n"); 498 499 if (tx_enable) 500 ndev->features &= ~NETIF_F_HW_CSUM; 501 502 if (rx_enable) 503 ndev->features &= ~NETIF_F_RXCSUM; 504 } else { 505 if (tx_enable) 506 ravb_write(ndev, CSR1_CSUM_ENABLE, CSR1); 507 508 if (rx_enable) 509 ravb_write(ndev, CSR2_CSUM_ENABLE, CSR2); 510 } 511 512 done: 513 ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0); 514 } 515 516 static void ravb_emac_init_gbeth(struct net_device *ndev) 517 { 518 struct ravb_private *priv = netdev_priv(ndev); 519 520 if (priv->phy_interface == PHY_INTERFACE_MODE_MII) { 521 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35); 522 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0); 523 } else { 524 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_RGMII, CXR35); 525 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 526 CXR31_SEL_LINK0); 527 } 528 529 /* Receive frame limit set register */ 530 ravb_write(ndev, priv->info->rx_max_frame_size + ETH_FCS_LEN, RFLR); 531 532 /* EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through */ 533 ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) | 534 ECMR_TE | ECMR_RE | ECMR_RCPT | 535 ECMR_TXF | ECMR_RXF, ECMR); 536 537 ravb_set_rate_gbeth(ndev); 538 539 /* Set MAC address */ 540 ravb_write(ndev, 541 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 542 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 543 ravb_write(ndev, (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 544 545 /* E-MAC status register clear */ 546 ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR); 547 548 ravb_csum_init_gbeth(ndev); 549 550 /* E-MAC interrupt enable register */ 551 ravb_write(ndev, ECSIPR_ICDIP, ECSIPR); 552 } 553 554 static void ravb_emac_init_rcar(struct net_device *ndev) 555 { 556 struct ravb_private *priv = netdev_priv(ndev); 557 558 /* Set receive frame length 559 * 560 * The length set here describes the frame from the destination address 561 * up to and including the CRC data. However only the frame data, 562 * excluding the CRC, are transferred to memory. To allow for the 563 * largest frames add the CRC length to the maximum Rx descriptor size. 564 */ 565 ravb_write(ndev, priv->info->rx_max_frame_size + ETH_FCS_LEN, RFLR); 566 567 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 568 ravb_write(ndev, ECMR_ZPF | ECMR_DM | 569 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 570 ECMR_TE | ECMR_RE, ECMR); 571 572 ravb_set_rate_rcar(ndev); 573 574 /* Set MAC address */ 575 ravb_write(ndev, 576 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 577 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 578 ravb_write(ndev, 579 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 580 581 /* E-MAC status register clear */ 582 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 583 584 /* E-MAC interrupt enable register */ 585 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 586 } 587 588 static void ravb_emac_init_rcar_gen4(struct net_device *ndev) 589 { 590 struct ravb_private *priv = netdev_priv(ndev); 591 bool mii = priv->phy_interface == PHY_INTERFACE_MODE_MII; 592 593 ravb_modify(ndev, APSR, APSR_MIISELECT, mii ? APSR_MIISELECT : 0); 594 595 ravb_emac_init_rcar(ndev); 596 } 597 598 /* E-MAC init function */ 599 static void ravb_emac_init(struct net_device *ndev) 600 { 601 struct ravb_private *priv = netdev_priv(ndev); 602 const struct ravb_hw_info *info = priv->info; 603 604 info->emac_init(ndev); 605 } 606 607 static int ravb_dmac_init_gbeth(struct net_device *ndev) 608 { 609 struct ravb_private *priv = netdev_priv(ndev); 610 int error; 611 612 error = ravb_ring_init(ndev, RAVB_BE); 613 if (error) 614 return error; 615 616 /* Descriptor format */ 617 ravb_ring_format(ndev, RAVB_BE); 618 619 /* Set DMAC RX */ 620 ravb_write(ndev, 0x60000000, RCR); 621 622 /* Set Max Frame Length (RTC) */ 623 ravb_write(ndev, 0x7ffc0000 | priv->info->rx_max_frame_size, RTC); 624 625 /* Set FIFO size */ 626 ravb_write(ndev, 0x00222200, TGC); 627 628 ravb_write(ndev, 0, TCCR); 629 630 /* Frame receive */ 631 ravb_write(ndev, RIC0_FRE0, RIC0); 632 /* Disable FIFO full warning */ 633 ravb_write(ndev, 0x0, RIC1); 634 /* Receive FIFO full error, descriptor empty */ 635 ravb_write(ndev, RIC2_QFE0 | RIC2_RFFE, RIC2); 636 637 ravb_write(ndev, TIC_FTE0, TIC); 638 639 return 0; 640 } 641 642 static int ravb_dmac_init_rcar(struct net_device *ndev) 643 { 644 struct ravb_private *priv = netdev_priv(ndev); 645 const struct ravb_hw_info *info = priv->info; 646 int error; 647 648 error = ravb_ring_init(ndev, RAVB_BE); 649 if (error) 650 return error; 651 error = ravb_ring_init(ndev, RAVB_NC); 652 if (error) { 653 ravb_ring_free(ndev, RAVB_BE); 654 return error; 655 } 656 657 /* Descriptor format */ 658 ravb_ring_format(ndev, RAVB_BE); 659 ravb_ring_format(ndev, RAVB_NC); 660 661 /* Set AVB RX */ 662 ravb_write(ndev, 663 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 664 665 /* Set FIFO size */ 666 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC); 667 668 /* Timestamp enable */ 669 ravb_write(ndev, TCCR_TFEN, TCCR); 670 671 /* Interrupt init: */ 672 if (info->multi_irqs) { 673 /* Clear DIL.DPLx */ 674 ravb_write(ndev, 0, DIL); 675 /* Set queue specific interrupt */ 676 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 677 } 678 /* Frame receive */ 679 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 680 /* Disable FIFO full warning */ 681 ravb_write(ndev, 0, RIC1); 682 /* Receive FIFO full error, descriptor empty */ 683 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 684 /* Frame transmitted, timestamp FIFO updated */ 685 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 686 687 return 0; 688 } 689 690 /* Device init function for Ethernet AVB */ 691 static int ravb_dmac_init(struct net_device *ndev) 692 { 693 struct ravb_private *priv = netdev_priv(ndev); 694 const struct ravb_hw_info *info = priv->info; 695 int error; 696 697 /* Set CONFIG mode */ 698 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 699 if (error) 700 return error; 701 702 error = info->dmac_init(ndev); 703 if (error) 704 return error; 705 706 /* Setting the control will start the AVB-DMAC process. */ 707 return ravb_set_opmode(ndev, CCC_OPC_OPERATION); 708 } 709 710 static void ravb_get_tx_tstamp(struct net_device *ndev) 711 { 712 struct ravb_private *priv = netdev_priv(ndev); 713 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 714 struct skb_shared_hwtstamps shhwtstamps; 715 struct sk_buff *skb; 716 struct timespec64 ts; 717 u16 tag, tfa_tag; 718 int count; 719 u32 tfa2; 720 721 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 722 while (count--) { 723 tfa2 = ravb_read(ndev, TFA2); 724 tfa_tag = (tfa2 & TFA2_TST) >> 16; 725 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 726 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 727 ravb_read(ndev, TFA1); 728 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 729 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 730 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 731 list) { 732 skb = ts_skb->skb; 733 tag = ts_skb->tag; 734 list_del(&ts_skb->list); 735 kfree(ts_skb); 736 if (tag == tfa_tag) { 737 skb_tstamp_tx(skb, &shhwtstamps); 738 dev_consume_skb_any(skb); 739 break; 740 } else { 741 dev_kfree_skb_any(skb); 742 } 743 } 744 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 745 } 746 } 747 748 static void ravb_rx_csum_gbeth(struct sk_buff *skb) 749 { 750 struct skb_shared_info *shinfo = skb_shinfo(skb); 751 size_t csum_len; 752 u16 *hw_csum; 753 754 /* The hardware checksum status is contained in 4 bytes appended to 755 * packet data. 756 * 757 * For ipv4, the first 2 bytes are the ip header checksum status. We can 758 * ignore this as it will always be re-checked in inet_gro_receive(). 759 * 760 * The last 2 bytes are the protocol checksum status which will be zero 761 * if the checksum has been validated. 762 */ 763 csum_len = sizeof(*hw_csum) * 2; 764 if (unlikely(skb->len < csum_len)) 765 return; 766 767 if (skb_is_nonlinear(skb)) { 768 skb_frag_t *last_frag = &shinfo->frags[shinfo->nr_frags - 1]; 769 770 hw_csum = (u16 *)(skb_frag_address(last_frag) + 771 skb_frag_size(last_frag)); 772 skb_frag_size_sub(last_frag, csum_len); 773 } else { 774 hw_csum = (u16 *)skb_tail_pointer(skb); 775 skb_trim(skb, skb->len - csum_len); 776 } 777 778 if (!get_unaligned(--hw_csum)) 779 skb->ip_summed = CHECKSUM_UNNECESSARY; 780 } 781 782 static void ravb_rx_csum(struct sk_buff *skb) 783 { 784 u8 *hw_csum; 785 786 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes 787 * appended to packet data 788 */ 789 if (unlikely(skb->len < sizeof(__sum16))) 790 return; 791 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); 792 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 793 skb->ip_summed = CHECKSUM_COMPLETE; 794 skb_trim(skb, skb->len - sizeof(__sum16)); 795 } 796 797 /* Packet receive function for Gigabit Ethernet */ 798 static int ravb_rx_gbeth(struct net_device *ndev, int budget, int q) 799 { 800 struct ravb_private *priv = netdev_priv(ndev); 801 const struct ravb_hw_info *info = priv->info; 802 struct net_device_stats *stats; 803 struct ravb_rx_desc *desc; 804 int rx_packets = 0; 805 u8 desc_status; 806 u16 desc_len; 807 u8 die_dt; 808 int entry; 809 int limit; 810 int i; 811 812 limit = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q]; 813 stats = &priv->stats[q]; 814 815 for (i = 0; i < limit; i++, priv->cur_rx[q]++) { 816 struct sk_buff *skb = NULL; 817 818 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 819 desc = &priv->rx_ring[q].desc[entry]; 820 if (rx_packets == budget || desc->die_dt == DT_FEMPTY) 821 break; 822 823 /* Descriptor type must be checked before all other reads */ 824 dma_rmb(); 825 desc_status = desc->msc; 826 desc_len = le16_to_cpu(desc->ds_cc) & RX_DS; 827 828 /* We use 0-byte descriptors to mark the DMA mapping errors */ 829 if (!desc_len) 830 continue; 831 832 if (desc_status & MSC_MC) 833 stats->multicast++; 834 835 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | MSC_CEEF)) { 836 stats->rx_errors++; 837 if (desc_status & MSC_CRC) 838 stats->rx_crc_errors++; 839 if (desc_status & MSC_RFE) 840 stats->rx_frame_errors++; 841 if (desc_status & (MSC_RTLF | MSC_RTSF)) 842 stats->rx_length_errors++; 843 if (desc_status & MSC_CEEF) 844 stats->rx_missed_errors++; 845 } else { 846 struct ravb_rx_buffer *rx_buff; 847 void *rx_addr; 848 849 rx_buff = &priv->rx_buffers[q][entry]; 850 rx_addr = page_address(rx_buff->page) + rx_buff->offset; 851 die_dt = desc->die_dt & 0xF0; 852 dma_sync_single_for_cpu(ndev->dev.parent, 853 le32_to_cpu(desc->dptr), 854 desc_len, DMA_FROM_DEVICE); 855 856 switch (die_dt) { 857 case DT_FSINGLE: 858 case DT_FSTART: 859 /* Start of packet: Set initial data length. */ 860 skb = napi_build_skb(rx_addr, 861 info->rx_buffer_size); 862 if (unlikely(!skb)) { 863 stats->rx_errors++; 864 page_pool_put_page(priv->rx_pool[q], 865 rx_buff->page, 0, 866 true); 867 goto refill; 868 } 869 skb_mark_for_recycle(skb); 870 skb_put(skb, desc_len); 871 872 /* Save this skb if the packet spans multiple 873 * descriptors. 874 */ 875 if (die_dt == DT_FSTART) 876 priv->rx_1st_skb = skb; 877 break; 878 879 case DT_FMID: 880 case DT_FEND: 881 /* Continuing a packet: Add this buffer as an RX 882 * frag. 883 */ 884 885 /* rx_1st_skb will be NULL if napi_build_skb() 886 * failed for the first descriptor of a 887 * multi-descriptor packet. 888 */ 889 if (unlikely(!priv->rx_1st_skb)) { 890 stats->rx_errors++; 891 page_pool_put_page(priv->rx_pool[q], 892 rx_buff->page, 0, 893 true); 894 895 /* We may find a DT_FSINGLE or DT_FSTART 896 * descriptor in the queue which we can 897 * process, so don't give up yet. 898 */ 899 continue; 900 } 901 skb_add_rx_frag(priv->rx_1st_skb, 902 skb_shinfo(priv->rx_1st_skb)->nr_frags, 903 rx_buff->page, rx_buff->offset, 904 desc_len, info->rx_buffer_size); 905 906 /* Set skb to point at the whole packet so that 907 * we only need one code path for finishing a 908 * packet. 909 */ 910 skb = priv->rx_1st_skb; 911 } 912 913 switch (die_dt) { 914 case DT_FSINGLE: 915 case DT_FEND: 916 /* Finishing a packet: Determine protocol & 917 * checksum, hand off to NAPI and update our 918 * stats. 919 */ 920 skb->protocol = eth_type_trans(skb, ndev); 921 if (ndev->features & NETIF_F_RXCSUM) 922 ravb_rx_csum_gbeth(skb); 923 stats->rx_bytes += skb->len; 924 napi_gro_receive(&priv->napi[q], skb); 925 rx_packets++; 926 927 /* Clear rx_1st_skb so that it will only be 928 * non-NULL when valid. 929 */ 930 priv->rx_1st_skb = NULL; 931 } 932 933 /* Mark this RX buffer as consumed. */ 934 rx_buff->page = NULL; 935 } 936 } 937 938 refill: 939 /* Refill the RX ring buffers. */ 940 priv->dirty_rx[q] += ravb_rx_ring_refill(ndev, q, 941 priv->cur_rx[q] - priv->dirty_rx[q], 942 GFP_ATOMIC); 943 944 stats->rx_packets += rx_packets; 945 return rx_packets; 946 } 947 948 static void ravb_rx_rcar_hwstamp(struct ravb_private *priv, int q, 949 struct ravb_ex_rx_desc *desc, 950 struct sk_buff *skb) 951 { 952 struct skb_shared_hwtstamps *shhwtstamps; 953 struct timespec64 ts; 954 bool get_ts; 955 956 if (q == RAVB_NC) 957 get_ts = priv->tstamp_rx_ctrl != HWTSTAMP_FILTER_NONE; 958 else 959 get_ts = priv->tstamp_rx_ctrl == HWTSTAMP_FILTER_ALL; 960 961 if (!get_ts) 962 return; 963 964 shhwtstamps = skb_hwtstamps(skb); 965 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 966 ts.tv_sec = ((u64)le16_to_cpu(desc->ts_sh) << 32) 967 | le32_to_cpu(desc->ts_sl); 968 ts.tv_nsec = le32_to_cpu(desc->ts_n); 969 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 970 } 971 972 /* Packet receive function for Ethernet AVB */ 973 static int ravb_rx_rcar(struct net_device *ndev, int budget, int q) 974 { 975 struct ravb_private *priv = netdev_priv(ndev); 976 const struct ravb_hw_info *info = priv->info; 977 struct net_device_stats *stats = &priv->stats[q]; 978 struct ravb_ex_rx_desc *desc; 979 unsigned int limit, i; 980 struct sk_buff *skb; 981 int rx_packets = 0; 982 u8 desc_status; 983 u16 pkt_len; 984 int entry; 985 986 limit = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q]; 987 for (i = 0; i < limit; i++, priv->cur_rx[q]++) { 988 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 989 desc = &priv->rx_ring[q].ex_desc[entry]; 990 if (rx_packets == budget || desc->die_dt == DT_FEMPTY) 991 break; 992 993 /* Descriptor type must be checked before all other reads */ 994 dma_rmb(); 995 desc_status = desc->msc; 996 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 997 998 /* We use 0-byte descriptors to mark the DMA mapping errors */ 999 if (!pkt_len) 1000 continue; 1001 1002 if (desc_status & MSC_MC) 1003 stats->multicast++; 1004 1005 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 1006 MSC_CEEF)) { 1007 stats->rx_errors++; 1008 if (desc_status & MSC_CRC) 1009 stats->rx_crc_errors++; 1010 if (desc_status & MSC_RFE) 1011 stats->rx_frame_errors++; 1012 if (desc_status & (MSC_RTLF | MSC_RTSF)) 1013 stats->rx_length_errors++; 1014 if (desc_status & MSC_CEEF) 1015 stats->rx_missed_errors++; 1016 } else { 1017 struct ravb_rx_buffer *rx_buff; 1018 void *rx_addr; 1019 1020 rx_buff = &priv->rx_buffers[q][entry]; 1021 rx_addr = page_address(rx_buff->page) + rx_buff->offset; 1022 dma_sync_single_for_cpu(ndev->dev.parent, 1023 le32_to_cpu(desc->dptr), 1024 pkt_len, DMA_FROM_DEVICE); 1025 1026 skb = napi_build_skb(rx_addr, info->rx_buffer_size); 1027 if (unlikely(!skb)) { 1028 stats->rx_errors++; 1029 page_pool_put_page(priv->rx_pool[q], 1030 rx_buff->page, 0, true); 1031 break; 1032 } 1033 skb_mark_for_recycle(skb); 1034 1035 ravb_rx_rcar_hwstamp(priv, q, desc, skb); 1036 1037 skb_put(skb, pkt_len); 1038 skb->protocol = eth_type_trans(skb, ndev); 1039 if (ndev->features & NETIF_F_RXCSUM) 1040 ravb_rx_csum(skb); 1041 napi_gro_receive(&priv->napi[q], skb); 1042 rx_packets++; 1043 stats->rx_bytes += pkt_len; 1044 1045 /* Mark this RX buffer as consumed. */ 1046 rx_buff->page = NULL; 1047 } 1048 } 1049 1050 /* Refill the RX ring buffers. */ 1051 priv->dirty_rx[q] += ravb_rx_ring_refill(ndev, q, 1052 priv->cur_rx[q] - priv->dirty_rx[q], 1053 GFP_ATOMIC); 1054 1055 stats->rx_packets += rx_packets; 1056 return rx_packets; 1057 } 1058 1059 /* Packet receive function for Ethernet AVB */ 1060 static int ravb_rx(struct net_device *ndev, int budget, int q) 1061 { 1062 struct ravb_private *priv = netdev_priv(ndev); 1063 const struct ravb_hw_info *info = priv->info; 1064 1065 return info->receive(ndev, budget, q); 1066 } 1067 1068 static void ravb_rcv_snd_disable(struct net_device *ndev) 1069 { 1070 /* Disable TX and RX */ 1071 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 1072 } 1073 1074 static void ravb_rcv_snd_enable(struct net_device *ndev) 1075 { 1076 /* Enable TX and RX */ 1077 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 1078 } 1079 1080 /* function for waiting dma process finished */ 1081 static int ravb_stop_dma(struct net_device *ndev) 1082 { 1083 struct ravb_private *priv = netdev_priv(ndev); 1084 const struct ravb_hw_info *info = priv->info; 1085 int error; 1086 1087 /* Wait for stopping the hardware TX process */ 1088 error = ravb_wait(ndev, TCCR, info->tccr_mask, 0); 1089 1090 if (error) 1091 return error; 1092 1093 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 1094 0); 1095 if (error) 1096 return error; 1097 1098 /* Stop the E-MAC's RX/TX processes. */ 1099 ravb_rcv_snd_disable(ndev); 1100 1101 /* Wait for stopping the RX DMA process */ 1102 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 1103 if (error) 1104 return error; 1105 1106 /* Stop AVB-DMAC process */ 1107 return ravb_set_opmode(ndev, CCC_OPC_CONFIG); 1108 } 1109 1110 /* E-MAC interrupt handler */ 1111 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 1112 { 1113 struct ravb_private *priv = netdev_priv(ndev); 1114 u32 ecsr, psr; 1115 1116 ecsr = ravb_read(ndev, ECSR); 1117 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 1118 1119 if (ecsr & ECSR_MPD) 1120 pm_wakeup_event(&priv->pdev->dev, 0); 1121 if (ecsr & ECSR_ICD) 1122 ndev->stats.tx_carrier_errors++; 1123 if (ecsr & ECSR_LCHNG) { 1124 /* Link changed */ 1125 if (priv->no_avb_link) 1126 return; 1127 psr = ravb_read(ndev, PSR); 1128 if (priv->avb_link_active_low) 1129 psr ^= PSR_LMON; 1130 if (!(psr & PSR_LMON)) { 1131 /* DIsable RX and TX */ 1132 ravb_rcv_snd_disable(ndev); 1133 } else { 1134 /* Enable RX and TX */ 1135 ravb_rcv_snd_enable(ndev); 1136 } 1137 } 1138 } 1139 1140 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 1141 { 1142 struct net_device *ndev = dev_id; 1143 struct ravb_private *priv = netdev_priv(ndev); 1144 struct device *dev = &priv->pdev->dev; 1145 irqreturn_t result = IRQ_HANDLED; 1146 1147 pm_runtime_get_noresume(dev); 1148 1149 if (unlikely(!pm_runtime_active(dev))) { 1150 result = IRQ_NONE; 1151 goto out_rpm_put; 1152 } 1153 1154 spin_lock(&priv->lock); 1155 ravb_emac_interrupt_unlocked(ndev); 1156 spin_unlock(&priv->lock); 1157 1158 out_rpm_put: 1159 pm_runtime_put_noidle(dev); 1160 return result; 1161 } 1162 1163 /* Error interrupt handler */ 1164 static void ravb_error_interrupt(struct net_device *ndev) 1165 { 1166 struct ravb_private *priv = netdev_priv(ndev); 1167 u32 eis, ris2; 1168 1169 eis = ravb_read(ndev, EIS); 1170 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS); 1171 if (eis & EIS_QFS) { 1172 ris2 = ravb_read(ndev, RIS2); 1173 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_QFF1 | RIS2_RFFF | RIS2_RESERVED), 1174 RIS2); 1175 1176 /* Receive Descriptor Empty int */ 1177 if (ris2 & RIS2_QFF0) 1178 priv->stats[RAVB_BE].rx_over_errors++; 1179 1180 /* Receive Descriptor Empty int */ 1181 if (ris2 & RIS2_QFF1) 1182 priv->stats[RAVB_NC].rx_over_errors++; 1183 1184 /* Receive FIFO Overflow int */ 1185 if (ris2 & RIS2_RFFF) 1186 priv->rx_fifo_errors++; 1187 } 1188 } 1189 1190 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 1191 { 1192 struct ravb_private *priv = netdev_priv(ndev); 1193 const struct ravb_hw_info *info = priv->info; 1194 u32 ris0 = ravb_read(ndev, RIS0); 1195 u32 ric0 = ravb_read(ndev, RIC0); 1196 u32 tis = ravb_read(ndev, TIS); 1197 u32 tic = ravb_read(ndev, TIC); 1198 1199 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 1200 if (napi_schedule_prep(&priv->napi[q])) { 1201 /* Mask RX and TX interrupts */ 1202 if (!info->irq_en_dis) { 1203 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 1204 ravb_write(ndev, tic & ~BIT(q), TIC); 1205 } else { 1206 ravb_write(ndev, BIT(q), RID0); 1207 ravb_write(ndev, BIT(q), TID); 1208 } 1209 __napi_schedule(&priv->napi[q]); 1210 } else { 1211 netdev_warn(ndev, 1212 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 1213 ris0, ric0); 1214 netdev_warn(ndev, 1215 " tx status 0x%08x, tx mask 0x%08x.\n", 1216 tis, tic); 1217 } 1218 return true; 1219 } 1220 return false; 1221 } 1222 1223 static bool ravb_timestamp_interrupt(struct net_device *ndev) 1224 { 1225 u32 tis = ravb_read(ndev, TIS); 1226 1227 if (tis & TIS_TFUF) { 1228 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS); 1229 ravb_get_tx_tstamp(ndev); 1230 return true; 1231 } 1232 return false; 1233 } 1234 1235 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 1236 { 1237 struct net_device *ndev = dev_id; 1238 struct ravb_private *priv = netdev_priv(ndev); 1239 const struct ravb_hw_info *info = priv->info; 1240 struct device *dev = &priv->pdev->dev; 1241 irqreturn_t result = IRQ_NONE; 1242 u32 iss; 1243 1244 pm_runtime_get_noresume(dev); 1245 1246 if (unlikely(!pm_runtime_active(dev))) 1247 goto out_rpm_put; 1248 1249 spin_lock(&priv->lock); 1250 /* Get interrupt status */ 1251 iss = ravb_read(ndev, ISS); 1252 1253 /* Received and transmitted interrupts */ 1254 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 1255 int q; 1256 1257 /* Timestamp updated */ 1258 if (ravb_timestamp_interrupt(ndev)) 1259 result = IRQ_HANDLED; 1260 1261 /* Network control and best effort queue RX/TX */ 1262 if (info->nc_queues) { 1263 for (q = RAVB_NC; q >= RAVB_BE; q--) { 1264 if (ravb_queue_interrupt(ndev, q)) 1265 result = IRQ_HANDLED; 1266 } 1267 } else { 1268 if (ravb_queue_interrupt(ndev, RAVB_BE)) 1269 result = IRQ_HANDLED; 1270 } 1271 } 1272 1273 /* E-MAC status summary */ 1274 if (iss & ISS_MS) { 1275 ravb_emac_interrupt_unlocked(ndev); 1276 result = IRQ_HANDLED; 1277 } 1278 1279 /* Error status summary */ 1280 if (iss & ISS_ES) { 1281 ravb_error_interrupt(ndev); 1282 result = IRQ_HANDLED; 1283 } 1284 1285 /* gPTP interrupt status summary */ 1286 if (iss & ISS_CGIS) { 1287 ravb_ptp_interrupt(ndev); 1288 result = IRQ_HANDLED; 1289 } 1290 1291 spin_unlock(&priv->lock); 1292 1293 out_rpm_put: 1294 pm_runtime_put_noidle(dev); 1295 return result; 1296 } 1297 1298 /* Timestamp/Error/gPTP interrupt handler */ 1299 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 1300 { 1301 struct net_device *ndev = dev_id; 1302 struct ravb_private *priv = netdev_priv(ndev); 1303 struct device *dev = &priv->pdev->dev; 1304 irqreturn_t result = IRQ_NONE; 1305 u32 iss; 1306 1307 pm_runtime_get_noresume(dev); 1308 1309 if (unlikely(!pm_runtime_active(dev))) 1310 goto out_rpm_put; 1311 1312 spin_lock(&priv->lock); 1313 /* Get interrupt status */ 1314 iss = ravb_read(ndev, ISS); 1315 1316 /* Timestamp updated */ 1317 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 1318 result = IRQ_HANDLED; 1319 1320 /* Error status summary */ 1321 if (iss & ISS_ES) { 1322 ravb_error_interrupt(ndev); 1323 result = IRQ_HANDLED; 1324 } 1325 1326 /* gPTP interrupt status summary */ 1327 if (iss & ISS_CGIS) { 1328 ravb_ptp_interrupt(ndev); 1329 result = IRQ_HANDLED; 1330 } 1331 1332 spin_unlock(&priv->lock); 1333 1334 out_rpm_put: 1335 pm_runtime_put_noidle(dev); 1336 return result; 1337 } 1338 1339 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 1340 { 1341 struct net_device *ndev = dev_id; 1342 struct ravb_private *priv = netdev_priv(ndev); 1343 struct device *dev = &priv->pdev->dev; 1344 irqreturn_t result = IRQ_NONE; 1345 1346 pm_runtime_get_noresume(dev); 1347 1348 if (unlikely(!pm_runtime_active(dev))) 1349 goto out_rpm_put; 1350 1351 spin_lock(&priv->lock); 1352 1353 /* Network control/Best effort queue RX/TX */ 1354 if (ravb_queue_interrupt(ndev, q)) 1355 result = IRQ_HANDLED; 1356 1357 spin_unlock(&priv->lock); 1358 1359 out_rpm_put: 1360 pm_runtime_put_noidle(dev); 1361 return result; 1362 } 1363 1364 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 1365 { 1366 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 1367 } 1368 1369 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 1370 { 1371 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 1372 } 1373 1374 static int ravb_poll(struct napi_struct *napi, int budget) 1375 { 1376 struct net_device *ndev = napi->dev; 1377 struct ravb_private *priv = netdev_priv(ndev); 1378 const struct ravb_hw_info *info = priv->info; 1379 unsigned long flags; 1380 int q = napi - priv->napi; 1381 int mask = BIT(q); 1382 int work_done; 1383 1384 /* Processing RX Descriptor Ring */ 1385 /* Clear RX interrupt */ 1386 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0); 1387 work_done = ravb_rx(ndev, budget, q); 1388 1389 /* Processing TX Descriptor Ring */ 1390 spin_lock_irqsave(&priv->lock, flags); 1391 /* Clear TX interrupt */ 1392 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS); 1393 ravb_tx_free(ndev, q, true); 1394 netif_wake_subqueue(ndev, q); 1395 spin_unlock_irqrestore(&priv->lock, flags); 1396 1397 /* Receive error message handling */ 1398 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 1399 if (info->nc_queues) 1400 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 1401 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 1402 ndev->stats.rx_over_errors = priv->rx_over_errors; 1403 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 1404 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 1405 1406 if (work_done < budget && napi_complete_done(napi, work_done)) { 1407 /* Re-enable RX/TX interrupts */ 1408 spin_lock_irqsave(&priv->lock, flags); 1409 if (!info->irq_en_dis) { 1410 ravb_modify(ndev, RIC0, mask, mask); 1411 ravb_modify(ndev, TIC, mask, mask); 1412 } else { 1413 ravb_write(ndev, mask, RIE0); 1414 ravb_write(ndev, mask, TIE); 1415 } 1416 spin_unlock_irqrestore(&priv->lock, flags); 1417 } 1418 1419 return work_done; 1420 } 1421 1422 static void ravb_set_duplex_gbeth(struct net_device *ndev) 1423 { 1424 struct ravb_private *priv = netdev_priv(ndev); 1425 1426 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex > 0 ? ECMR_DM : 0); 1427 } 1428 1429 /* PHY state control function */ 1430 static void ravb_adjust_link(struct net_device *ndev) 1431 { 1432 struct ravb_private *priv = netdev_priv(ndev); 1433 const struct ravb_hw_info *info = priv->info; 1434 struct phy_device *phydev = ndev->phydev; 1435 bool new_state = false; 1436 unsigned long flags; 1437 1438 spin_lock_irqsave(&priv->lock, flags); 1439 1440 /* Disable TX and RX right over here, if E-MAC change is ignored */ 1441 if (priv->no_avb_link) 1442 ravb_rcv_snd_disable(ndev); 1443 1444 if (phydev->link) { 1445 if (info->half_duplex && phydev->duplex != priv->duplex) { 1446 new_state = true; 1447 priv->duplex = phydev->duplex; 1448 ravb_set_duplex_gbeth(ndev); 1449 } 1450 1451 if (phydev->speed != priv->speed) { 1452 new_state = true; 1453 priv->speed = phydev->speed; 1454 info->set_rate(ndev); 1455 } 1456 if (!priv->link) { 1457 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 1458 new_state = true; 1459 priv->link = phydev->link; 1460 } 1461 } else if (priv->link) { 1462 new_state = true; 1463 priv->link = 0; 1464 priv->speed = 0; 1465 if (info->half_duplex) 1466 priv->duplex = -1; 1467 } 1468 1469 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1470 if (priv->no_avb_link && phydev->link) 1471 ravb_rcv_snd_enable(ndev); 1472 1473 spin_unlock_irqrestore(&priv->lock, flags); 1474 1475 if (new_state && netif_msg_link(priv)) 1476 phy_print_status(phydev); 1477 } 1478 1479 /* PHY init function */ 1480 static int ravb_phy_init(struct net_device *ndev) 1481 { 1482 struct device_node *np = ndev->dev.parent->of_node; 1483 struct ravb_private *priv = netdev_priv(ndev); 1484 const struct ravb_hw_info *info = priv->info; 1485 struct phy_device *phydev; 1486 struct device_node *pn; 1487 phy_interface_t iface; 1488 int err; 1489 1490 priv->link = 0; 1491 priv->speed = 0; 1492 priv->duplex = -1; 1493 1494 /* Try connecting to PHY */ 1495 pn = of_parse_phandle(np, "phy-handle", 0); 1496 if (!pn) { 1497 /* In the case of a fixed PHY, the DT node associated 1498 * to the PHY is the Ethernet MAC DT node. 1499 */ 1500 if (of_phy_is_fixed_link(np)) { 1501 err = of_phy_register_fixed_link(np); 1502 if (err) 1503 return err; 1504 } 1505 pn = of_node_get(np); 1506 } 1507 1508 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII 1509 : priv->phy_interface; 1510 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface); 1511 of_node_put(pn); 1512 if (!phydev) { 1513 netdev_err(ndev, "failed to connect PHY\n"); 1514 err = -ENOENT; 1515 goto err_deregister_fixed_link; 1516 } 1517 1518 if (!info->half_duplex) { 1519 /* 10BASE, Pause and Asym Pause is not supported */ 1520 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1521 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1522 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT); 1523 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 1524 1525 /* Half Duplex is not supported */ 1526 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1527 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1528 } 1529 1530 phy_attached_info(phydev); 1531 1532 return 0; 1533 1534 err_deregister_fixed_link: 1535 if (of_phy_is_fixed_link(np)) 1536 of_phy_deregister_fixed_link(np); 1537 1538 return err; 1539 } 1540 1541 /* PHY control start function */ 1542 static int ravb_phy_start(struct net_device *ndev) 1543 { 1544 int error; 1545 1546 error = ravb_phy_init(ndev); 1547 if (error) 1548 return error; 1549 1550 phy_start(ndev->phydev); 1551 1552 return 0; 1553 } 1554 1555 static u32 ravb_get_msglevel(struct net_device *ndev) 1556 { 1557 struct ravb_private *priv = netdev_priv(ndev); 1558 1559 return priv->msg_enable; 1560 } 1561 1562 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1563 { 1564 struct ravb_private *priv = netdev_priv(ndev); 1565 1566 priv->msg_enable = value; 1567 } 1568 1569 static const char ravb_gstrings_stats_gbeth[][ETH_GSTRING_LEN] = { 1570 "rx_queue_0_current", 1571 "tx_queue_0_current", 1572 "rx_queue_0_dirty", 1573 "tx_queue_0_dirty", 1574 "rx_queue_0_packets", 1575 "tx_queue_0_packets", 1576 "rx_queue_0_bytes", 1577 "tx_queue_0_bytes", 1578 "rx_queue_0_mcast_packets", 1579 "rx_queue_0_errors", 1580 "rx_queue_0_crc_errors", 1581 "rx_queue_0_frame_errors", 1582 "rx_queue_0_length_errors", 1583 "rx_queue_0_csum_offload_errors", 1584 "rx_queue_0_over_errors", 1585 }; 1586 1587 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1588 "rx_queue_0_current", 1589 "tx_queue_0_current", 1590 "rx_queue_0_dirty", 1591 "tx_queue_0_dirty", 1592 "rx_queue_0_packets", 1593 "tx_queue_0_packets", 1594 "rx_queue_0_bytes", 1595 "tx_queue_0_bytes", 1596 "rx_queue_0_mcast_packets", 1597 "rx_queue_0_errors", 1598 "rx_queue_0_crc_errors", 1599 "rx_queue_0_frame_errors", 1600 "rx_queue_0_length_errors", 1601 "rx_queue_0_missed_errors", 1602 "rx_queue_0_over_errors", 1603 1604 "rx_queue_1_current", 1605 "tx_queue_1_current", 1606 "rx_queue_1_dirty", 1607 "tx_queue_1_dirty", 1608 "rx_queue_1_packets", 1609 "tx_queue_1_packets", 1610 "rx_queue_1_bytes", 1611 "tx_queue_1_bytes", 1612 "rx_queue_1_mcast_packets", 1613 "rx_queue_1_errors", 1614 "rx_queue_1_crc_errors", 1615 "rx_queue_1_frame_errors", 1616 "rx_queue_1_length_errors", 1617 "rx_queue_1_missed_errors", 1618 "rx_queue_1_over_errors", 1619 }; 1620 1621 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1622 { 1623 struct ravb_private *priv = netdev_priv(netdev); 1624 const struct ravb_hw_info *info = priv->info; 1625 1626 switch (sset) { 1627 case ETH_SS_STATS: 1628 return info->stats_len; 1629 default: 1630 return -EOPNOTSUPP; 1631 } 1632 } 1633 1634 static void ravb_get_ethtool_stats(struct net_device *ndev, 1635 struct ethtool_stats *estats, u64 *data) 1636 { 1637 struct ravb_private *priv = netdev_priv(ndev); 1638 const struct ravb_hw_info *info = priv->info; 1639 int num_rx_q; 1640 int i = 0; 1641 int q; 1642 1643 num_rx_q = info->nc_queues ? NUM_RX_QUEUE : 1; 1644 /* Device-specific stats */ 1645 for (q = RAVB_BE; q < num_rx_q; q++) { 1646 struct net_device_stats *stats = &priv->stats[q]; 1647 1648 data[i++] = priv->cur_rx[q]; 1649 data[i++] = priv->cur_tx[q]; 1650 data[i++] = priv->dirty_rx[q]; 1651 data[i++] = priv->dirty_tx[q]; 1652 data[i++] = stats->rx_packets; 1653 data[i++] = stats->tx_packets; 1654 data[i++] = stats->rx_bytes; 1655 data[i++] = stats->tx_bytes; 1656 data[i++] = stats->multicast; 1657 data[i++] = stats->rx_errors; 1658 data[i++] = stats->rx_crc_errors; 1659 data[i++] = stats->rx_frame_errors; 1660 data[i++] = stats->rx_length_errors; 1661 data[i++] = stats->rx_missed_errors; 1662 data[i++] = stats->rx_over_errors; 1663 } 1664 } 1665 1666 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1667 { 1668 struct ravb_private *priv = netdev_priv(ndev); 1669 const struct ravb_hw_info *info = priv->info; 1670 1671 switch (stringset) { 1672 case ETH_SS_STATS: 1673 memcpy(data, info->gstrings_stats, info->gstrings_size); 1674 break; 1675 } 1676 } 1677 1678 static void ravb_get_ringparam(struct net_device *ndev, 1679 struct ethtool_ringparam *ring, 1680 struct kernel_ethtool_ringparam *kernel_ring, 1681 struct netlink_ext_ack *extack) 1682 { 1683 struct ravb_private *priv = netdev_priv(ndev); 1684 1685 ring->rx_max_pending = BE_RX_RING_MAX; 1686 ring->tx_max_pending = BE_TX_RING_MAX; 1687 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1688 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1689 } 1690 1691 static int ravb_set_ringparam(struct net_device *ndev, 1692 struct ethtool_ringparam *ring, 1693 struct kernel_ethtool_ringparam *kernel_ring, 1694 struct netlink_ext_ack *extack) 1695 { 1696 struct ravb_private *priv = netdev_priv(ndev); 1697 const struct ravb_hw_info *info = priv->info; 1698 int error; 1699 1700 if (ring->tx_pending > BE_TX_RING_MAX || 1701 ring->rx_pending > BE_RX_RING_MAX || 1702 ring->tx_pending < BE_TX_RING_MIN || 1703 ring->rx_pending < BE_RX_RING_MIN) 1704 return -EINVAL; 1705 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1706 return -EINVAL; 1707 1708 if (netif_running(ndev)) { 1709 netif_device_detach(ndev); 1710 /* Stop PTP Clock driver */ 1711 if (info->gptp) 1712 ravb_ptp_stop(ndev); 1713 /* Wait for DMA stopping */ 1714 error = ravb_stop_dma(ndev); 1715 if (error) { 1716 netdev_err(ndev, 1717 "cannot set ringparam! Any AVB processes are still running?\n"); 1718 return error; 1719 } 1720 synchronize_irq(ndev->irq); 1721 1722 /* Free all the skb's in the RX queue and the DMA buffers. */ 1723 ravb_ring_free(ndev, RAVB_BE); 1724 if (info->nc_queues) 1725 ravb_ring_free(ndev, RAVB_NC); 1726 } 1727 1728 /* Set new parameters */ 1729 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1730 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1731 1732 if (netif_running(ndev)) { 1733 error = ravb_dmac_init(ndev); 1734 if (error) { 1735 netdev_err(ndev, 1736 "%s: ravb_dmac_init() failed, error %d\n", 1737 __func__, error); 1738 return error; 1739 } 1740 1741 ravb_emac_init(ndev); 1742 1743 /* Initialise PTP Clock driver */ 1744 if (info->gptp) 1745 ravb_ptp_init(ndev, priv->pdev); 1746 1747 netif_device_attach(ndev); 1748 } 1749 1750 return 0; 1751 } 1752 1753 static int ravb_get_ts_info(struct net_device *ndev, 1754 struct kernel_ethtool_ts_info *info) 1755 { 1756 struct ravb_private *priv = netdev_priv(ndev); 1757 const struct ravb_hw_info *hw_info = priv->info; 1758 1759 if (hw_info->gptp || hw_info->ccc_gac) { 1760 info->so_timestamping = 1761 SOF_TIMESTAMPING_TX_SOFTWARE | 1762 SOF_TIMESTAMPING_TX_HARDWARE | 1763 SOF_TIMESTAMPING_RX_HARDWARE | 1764 SOF_TIMESTAMPING_RAW_HARDWARE; 1765 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1766 info->rx_filters = 1767 (1 << HWTSTAMP_FILTER_NONE) | 1768 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1769 (1 << HWTSTAMP_FILTER_ALL); 1770 info->phc_index = ptp_clock_index(priv->ptp.clock); 1771 } 1772 1773 return 0; 1774 } 1775 1776 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1777 { 1778 struct ravb_private *priv = netdev_priv(ndev); 1779 1780 wol->supported = WAKE_MAGIC; 1781 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1782 } 1783 1784 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1785 { 1786 struct ravb_private *priv = netdev_priv(ndev); 1787 const struct ravb_hw_info *info = priv->info; 1788 1789 if (!info->magic_pkt || (wol->wolopts & ~WAKE_MAGIC)) 1790 return -EOPNOTSUPP; 1791 1792 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1793 1794 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1795 1796 return 0; 1797 } 1798 1799 static const struct ethtool_ops ravb_ethtool_ops = { 1800 .nway_reset = phy_ethtool_nway_reset, 1801 .get_msglevel = ravb_get_msglevel, 1802 .set_msglevel = ravb_set_msglevel, 1803 .get_link = ethtool_op_get_link, 1804 .get_strings = ravb_get_strings, 1805 .get_ethtool_stats = ravb_get_ethtool_stats, 1806 .get_sset_count = ravb_get_sset_count, 1807 .get_ringparam = ravb_get_ringparam, 1808 .set_ringparam = ravb_set_ringparam, 1809 .get_ts_info = ravb_get_ts_info, 1810 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1811 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1812 .get_wol = ravb_get_wol, 1813 .set_wol = ravb_set_wol, 1814 }; 1815 1816 static int ravb_set_config_mode(struct net_device *ndev) 1817 { 1818 struct ravb_private *priv = netdev_priv(ndev); 1819 const struct ravb_hw_info *info = priv->info; 1820 int error; 1821 1822 if (info->gptp) { 1823 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 1824 if (error) 1825 return error; 1826 /* Set CSEL value */ 1827 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 1828 } else if (info->ccc_gac) { 1829 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG | CCC_GAC | CCC_CSEL_HPB); 1830 } else { 1831 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 1832 } 1833 1834 return error; 1835 } 1836 1837 static void ravb_set_gti(struct net_device *ndev) 1838 { 1839 struct ravb_private *priv = netdev_priv(ndev); 1840 const struct ravb_hw_info *info = priv->info; 1841 1842 if (!(info->gptp || info->ccc_gac)) 1843 return; 1844 1845 ravb_write(ndev, priv->gti_tiv, GTI); 1846 1847 /* Request GTI loading */ 1848 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 1849 } 1850 1851 static int ravb_compute_gti(struct net_device *ndev) 1852 { 1853 struct ravb_private *priv = netdev_priv(ndev); 1854 const struct ravb_hw_info *info = priv->info; 1855 struct device *dev = ndev->dev.parent; 1856 unsigned long rate; 1857 u64 inc; 1858 1859 if (!(info->gptp || info->ccc_gac)) 1860 return 0; 1861 1862 if (info->gptp_ref_clk) 1863 rate = clk_get_rate(priv->gptp_clk); 1864 else 1865 rate = clk_get_rate(priv->clk); 1866 if (!rate) 1867 return -EINVAL; 1868 1869 inc = div64_ul(1000000000ULL << 20, rate); 1870 1871 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 1872 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 1873 inc, GTI_TIV_MIN, GTI_TIV_MAX); 1874 return -EINVAL; 1875 } 1876 priv->gti_tiv = inc; 1877 1878 return 0; 1879 } 1880 1881 /* Set tx and rx clock internal delay modes */ 1882 static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev) 1883 { 1884 struct ravb_private *priv = netdev_priv(ndev); 1885 bool explicit_delay = false; 1886 u32 delay; 1887 1888 if (!priv->info->internal_delay) 1889 return; 1890 1891 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) { 1892 /* Valid values are 0 and 1800, according to DT bindings */ 1893 priv->rxcidm = !!delay; 1894 explicit_delay = true; 1895 } 1896 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) { 1897 /* Valid values are 0 and 2000, according to DT bindings */ 1898 priv->txcidm = !!delay; 1899 explicit_delay = true; 1900 } 1901 1902 if (explicit_delay) 1903 return; 1904 1905 /* Fall back to legacy rgmii-*id behavior */ 1906 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1907 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) { 1908 priv->rxcidm = 1; 1909 priv->rgmii_override = 1; 1910 } 1911 1912 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1913 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) { 1914 priv->txcidm = 1; 1915 priv->rgmii_override = 1; 1916 } 1917 } 1918 1919 static void ravb_set_delay_mode(struct net_device *ndev) 1920 { 1921 struct ravb_private *priv = netdev_priv(ndev); 1922 u32 set = 0; 1923 1924 if (!priv->info->internal_delay) 1925 return; 1926 1927 if (priv->rxcidm) 1928 set |= APSR_RDM; 1929 if (priv->txcidm) 1930 set |= APSR_TDM; 1931 ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set); 1932 } 1933 1934 /* Network device open function for Ethernet AVB */ 1935 static int ravb_open(struct net_device *ndev) 1936 { 1937 struct ravb_private *priv = netdev_priv(ndev); 1938 const struct ravb_hw_info *info = priv->info; 1939 struct device *dev = &priv->pdev->dev; 1940 int error; 1941 1942 napi_enable(&priv->napi[RAVB_BE]); 1943 if (info->nc_queues) 1944 napi_enable(&priv->napi[RAVB_NC]); 1945 1946 error = pm_runtime_resume_and_get(dev); 1947 if (error < 0) 1948 goto out_napi_off; 1949 1950 /* Set AVB config mode */ 1951 error = ravb_set_config_mode(ndev); 1952 if (error) 1953 goto out_rpm_put; 1954 1955 ravb_set_delay_mode(ndev); 1956 ravb_write(ndev, priv->desc_bat_dma, DBAT); 1957 1958 /* Device init */ 1959 error = ravb_dmac_init(ndev); 1960 if (error) 1961 goto out_set_reset; 1962 1963 ravb_emac_init(ndev); 1964 1965 ravb_set_gti(ndev); 1966 1967 /* Initialise PTP Clock driver */ 1968 if (info->gptp || info->ccc_gac) 1969 ravb_ptp_init(ndev, priv->pdev); 1970 1971 /* PHY control start */ 1972 error = ravb_phy_start(ndev); 1973 if (error) 1974 goto out_ptp_stop; 1975 1976 netif_tx_start_all_queues(ndev); 1977 1978 return 0; 1979 1980 out_ptp_stop: 1981 /* Stop PTP Clock driver */ 1982 if (info->gptp || info->ccc_gac) 1983 ravb_ptp_stop(ndev); 1984 ravb_stop_dma(ndev); 1985 out_set_reset: 1986 ravb_set_opmode(ndev, CCC_OPC_RESET); 1987 out_rpm_put: 1988 pm_runtime_put_autosuspend(dev); 1989 out_napi_off: 1990 if (info->nc_queues) 1991 napi_disable(&priv->napi[RAVB_NC]); 1992 napi_disable(&priv->napi[RAVB_BE]); 1993 return error; 1994 } 1995 1996 /* Timeout function for Ethernet AVB */ 1997 static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1998 { 1999 struct ravb_private *priv = netdev_priv(ndev); 2000 2001 netif_err(priv, tx_err, ndev, 2002 "transmit timed out, status %08x, resetting...\n", 2003 ravb_read(ndev, ISS)); 2004 2005 /* tx_errors count up */ 2006 ndev->stats.tx_errors++; 2007 2008 schedule_work(&priv->work); 2009 } 2010 2011 static void ravb_tx_timeout_work(struct work_struct *work) 2012 { 2013 struct ravb_private *priv = container_of(work, struct ravb_private, 2014 work); 2015 const struct ravb_hw_info *info = priv->info; 2016 struct net_device *ndev = priv->ndev; 2017 int error; 2018 2019 if (!rtnl_trylock()) { 2020 usleep_range(1000, 2000); 2021 schedule_work(&priv->work); 2022 return; 2023 } 2024 2025 netif_tx_stop_all_queues(ndev); 2026 2027 /* Stop PTP Clock driver */ 2028 if (info->gptp) 2029 ravb_ptp_stop(ndev); 2030 2031 /* Wait for DMA stopping */ 2032 if (ravb_stop_dma(ndev)) { 2033 /* If ravb_stop_dma() fails, the hardware is still operating 2034 * for TX and/or RX. So, this should not call the following 2035 * functions because ravb_dmac_init() is possible to fail too. 2036 * Also, this should not retry ravb_stop_dma() again and again 2037 * here because it's possible to wait forever. So, this just 2038 * re-enables the TX and RX and skip the following 2039 * re-initialization procedure. 2040 */ 2041 ravb_rcv_snd_enable(ndev); 2042 goto out; 2043 } 2044 2045 ravb_ring_free(ndev, RAVB_BE); 2046 if (info->nc_queues) 2047 ravb_ring_free(ndev, RAVB_NC); 2048 2049 /* Device init */ 2050 error = ravb_dmac_init(ndev); 2051 if (error) { 2052 /* If ravb_dmac_init() fails, descriptors are freed. So, this 2053 * should return here to avoid re-enabling the TX and RX in 2054 * ravb_emac_init(). 2055 */ 2056 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n", 2057 __func__, error); 2058 goto out_unlock; 2059 } 2060 ravb_emac_init(ndev); 2061 2062 out: 2063 /* Initialise PTP Clock driver */ 2064 if (info->gptp) 2065 ravb_ptp_init(ndev, priv->pdev); 2066 2067 netif_tx_start_all_queues(ndev); 2068 2069 out_unlock: 2070 rtnl_unlock(); 2071 } 2072 2073 static bool ravb_can_tx_csum_gbeth(struct sk_buff *skb) 2074 { 2075 u16 net_protocol = ntohs(skb->protocol); 2076 u8 inner_protocol; 2077 2078 /* GbEth IP can calculate the checksum if: 2079 * - there are zero or one VLAN headers with TPID=0x8100 2080 * - the network protocol is IPv4 or IPv6 2081 * - the transport protocol is TCP, UDP or ICMP 2082 * - the packet is not fragmented 2083 */ 2084 2085 if (net_protocol == ETH_P_8021Q) { 2086 struct vlan_hdr vhdr, *vh; 2087 2088 vh = skb_header_pointer(skb, ETH_HLEN, sizeof(vhdr), &vhdr); 2089 if (!vh) 2090 return false; 2091 2092 net_protocol = ntohs(vh->h_vlan_encapsulated_proto); 2093 } 2094 2095 switch (net_protocol) { 2096 case ETH_P_IP: 2097 inner_protocol = ip_hdr(skb)->protocol; 2098 break; 2099 case ETH_P_IPV6: 2100 inner_protocol = ipv6_hdr(skb)->nexthdr; 2101 break; 2102 default: 2103 return false; 2104 } 2105 2106 switch (inner_protocol) { 2107 case IPPROTO_TCP: 2108 case IPPROTO_UDP: 2109 return true; 2110 default: 2111 return false; 2112 } 2113 } 2114 2115 /* Packet transmit function for Ethernet AVB */ 2116 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 2117 { 2118 struct ravb_private *priv = netdev_priv(ndev); 2119 const struct ravb_hw_info *info = priv->info; 2120 unsigned int num_tx_desc = priv->num_tx_desc; 2121 u16 q = skb_get_queue_mapping(skb); 2122 struct ravb_tstamp_skb *ts_skb; 2123 struct ravb_tx_desc *desc; 2124 unsigned long flags; 2125 dma_addr_t dma_addr; 2126 void *buffer; 2127 u32 entry; 2128 u32 len; 2129 2130 if (skb->ip_summed == CHECKSUM_PARTIAL && !ravb_can_tx_csum_gbeth(skb)) 2131 skb_checksum_help(skb); 2132 2133 spin_lock_irqsave(&priv->lock, flags); 2134 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 2135 num_tx_desc) { 2136 netif_err(priv, tx_queued, ndev, 2137 "still transmitting with the full ring!\n"); 2138 netif_stop_subqueue(ndev, q); 2139 spin_unlock_irqrestore(&priv->lock, flags); 2140 return NETDEV_TX_BUSY; 2141 } 2142 2143 if (skb_put_padto(skb, ETH_ZLEN)) 2144 goto exit; 2145 2146 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc); 2147 priv->tx_skb[q][entry / num_tx_desc] = skb; 2148 2149 if (num_tx_desc > 1) { 2150 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 2151 entry / num_tx_desc * DPTR_ALIGN; 2152 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 2153 2154 /* Zero length DMA descriptors are problematic as they seem 2155 * to terminate DMA transfers. Avoid them by simply using a 2156 * length of DPTR_ALIGN (4) when skb data is aligned to 2157 * DPTR_ALIGN. 2158 * 2159 * As skb is guaranteed to have at least ETH_ZLEN (60) 2160 * bytes of data by the call to skb_put_padto() above this 2161 * is safe with respect to both the length of the first DMA 2162 * descriptor (len) overflowing the available data and the 2163 * length of the second DMA descriptor (skb->len - len) 2164 * being negative. 2165 */ 2166 if (len == 0) 2167 len = DPTR_ALIGN; 2168 2169 memcpy(buffer, skb->data, len); 2170 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 2171 DMA_TO_DEVICE); 2172 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2173 goto drop; 2174 2175 desc = &priv->tx_ring[q][entry]; 2176 desc->ds_tagl = cpu_to_le16(len); 2177 desc->dptr = cpu_to_le32(dma_addr); 2178 2179 buffer = skb->data + len; 2180 len = skb->len - len; 2181 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 2182 DMA_TO_DEVICE); 2183 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2184 goto unmap; 2185 2186 desc++; 2187 } else { 2188 desc = &priv->tx_ring[q][entry]; 2189 len = skb->len; 2190 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, 2191 DMA_TO_DEVICE); 2192 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2193 goto drop; 2194 } 2195 desc->ds_tagl = cpu_to_le16(len); 2196 desc->dptr = cpu_to_le32(dma_addr); 2197 2198 /* TX timestamp required */ 2199 if (info->gptp || info->ccc_gac) { 2200 if (q == RAVB_NC) { 2201 ts_skb = kmalloc_obj(*ts_skb, GFP_ATOMIC); 2202 if (!ts_skb) { 2203 if (num_tx_desc > 1) { 2204 desc--; 2205 dma_unmap_single(ndev->dev.parent, dma_addr, 2206 len, DMA_TO_DEVICE); 2207 } 2208 goto unmap; 2209 } 2210 ts_skb->skb = skb_get(skb); 2211 ts_skb->tag = priv->ts_skb_tag++; 2212 priv->ts_skb_tag &= 0x3ff; 2213 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 2214 2215 /* TAG and timestamp required flag */ 2216 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2217 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 2218 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12); 2219 } 2220 2221 skb_tx_timestamp(skb); 2222 } 2223 2224 if (num_tx_desc > 1) { 2225 desc->die_dt = DT_FEND; 2226 desc--; 2227 /* When using multi-descriptors, DT_FEND needs to get written 2228 * before DT_FSTART, but the compiler may reorder the memory 2229 * writes in an attempt to optimize the code. 2230 * Use a dma_wmb() barrier to make sure DT_FEND and DT_FSTART 2231 * are written exactly in the order shown in the code. 2232 * This is particularly important for cases where the DMA engine 2233 * is already running when we are running this code. If the DMA 2234 * sees DT_FSTART without the corresponding DT_FEND it will enter 2235 * an error condition. 2236 */ 2237 dma_wmb(); 2238 desc->die_dt = DT_FSTART; 2239 } else { 2240 /* Descriptor type must be set after all the above writes */ 2241 dma_wmb(); 2242 desc->die_dt = DT_FSINGLE; 2243 } 2244 2245 /* Before ringing the doorbell we need to make sure that the latest 2246 * writes have been committed to memory, otherwise it could delay 2247 * things until the doorbell is rang again. 2248 * This is in replacement of the read operation mentioned in the HW 2249 * manuals. 2250 */ 2251 dma_wmb(); 2252 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 2253 2254 priv->cur_tx[q] += num_tx_desc; 2255 if (priv->cur_tx[q] - priv->dirty_tx[q] > 2256 (priv->num_tx_ring[q] - 1) * num_tx_desc && 2257 !ravb_tx_free(ndev, q, true)) 2258 netif_stop_subqueue(ndev, q); 2259 2260 exit: 2261 spin_unlock_irqrestore(&priv->lock, flags); 2262 return NETDEV_TX_OK; 2263 2264 unmap: 2265 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 2266 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 2267 drop: 2268 dev_kfree_skb_any(skb); 2269 priv->tx_skb[q][entry / num_tx_desc] = NULL; 2270 goto exit; 2271 } 2272 2273 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 2274 struct net_device *sb_dev) 2275 { 2276 /* If skb needs TX timestamp, it is handled in network control queue */ 2277 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 2278 RAVB_BE; 2279 2280 } 2281 2282 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 2283 { 2284 struct ravb_private *priv = netdev_priv(ndev); 2285 const struct ravb_hw_info *info = priv->info; 2286 struct net_device_stats *nstats, *stats0, *stats1; 2287 struct device *dev = &priv->pdev->dev; 2288 2289 nstats = &ndev->stats; 2290 2291 pm_runtime_get_noresume(dev); 2292 2293 if (!pm_runtime_active(dev)) 2294 goto out_rpm_put; 2295 2296 stats0 = &priv->stats[RAVB_BE]; 2297 2298 if (info->tx_counters) { 2299 nstats->tx_dropped += ravb_read(ndev, TROCR); 2300 ravb_write(ndev, 0, TROCR); /* (write clear) */ 2301 } 2302 2303 if (info->carrier_counters) { 2304 nstats->collisions += ravb_read(ndev, CXR41); 2305 ravb_write(ndev, 0, CXR41); /* (write clear) */ 2306 nstats->tx_carrier_errors += ravb_read(ndev, CXR42); 2307 ravb_write(ndev, 0, CXR42); /* (write clear) */ 2308 } 2309 2310 nstats->rx_packets = stats0->rx_packets; 2311 nstats->tx_packets = stats0->tx_packets; 2312 nstats->rx_bytes = stats0->rx_bytes; 2313 nstats->tx_bytes = stats0->tx_bytes; 2314 nstats->multicast = stats0->multicast; 2315 nstats->rx_errors = stats0->rx_errors; 2316 nstats->rx_crc_errors = stats0->rx_crc_errors; 2317 nstats->rx_frame_errors = stats0->rx_frame_errors; 2318 nstats->rx_length_errors = stats0->rx_length_errors; 2319 nstats->rx_missed_errors = stats0->rx_missed_errors; 2320 nstats->rx_over_errors = stats0->rx_over_errors; 2321 if (info->nc_queues) { 2322 stats1 = &priv->stats[RAVB_NC]; 2323 2324 nstats->rx_packets += stats1->rx_packets; 2325 nstats->tx_packets += stats1->tx_packets; 2326 nstats->rx_bytes += stats1->rx_bytes; 2327 nstats->tx_bytes += stats1->tx_bytes; 2328 nstats->multicast += stats1->multicast; 2329 nstats->rx_errors += stats1->rx_errors; 2330 nstats->rx_crc_errors += stats1->rx_crc_errors; 2331 nstats->rx_frame_errors += stats1->rx_frame_errors; 2332 nstats->rx_length_errors += stats1->rx_length_errors; 2333 nstats->rx_missed_errors += stats1->rx_missed_errors; 2334 nstats->rx_over_errors += stats1->rx_over_errors; 2335 } 2336 2337 out_rpm_put: 2338 pm_runtime_put_noidle(dev); 2339 return nstats; 2340 } 2341 2342 /* Update promiscuous bit */ 2343 static void ravb_set_rx_mode(struct net_device *ndev) 2344 { 2345 struct ravb_private *priv = netdev_priv(ndev); 2346 unsigned long flags; 2347 2348 spin_lock_irqsave(&priv->lock, flags); 2349 ravb_modify(ndev, ECMR, ECMR_PRM, 2350 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 2351 spin_unlock_irqrestore(&priv->lock, flags); 2352 } 2353 2354 /* Device close function for Ethernet AVB */ 2355 static int ravb_close(struct net_device *ndev) 2356 { 2357 struct device_node *np = ndev->dev.parent->of_node; 2358 struct ravb_private *priv = netdev_priv(ndev); 2359 const struct ravb_hw_info *info = priv->info; 2360 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 2361 struct device *dev = &priv->pdev->dev; 2362 int error; 2363 2364 netif_tx_stop_all_queues(ndev); 2365 2366 /* Disable interrupts by clearing the interrupt masks. */ 2367 ravb_write(ndev, 0, RIC0); 2368 ravb_write(ndev, 0, RIC2); 2369 ravb_write(ndev, 0, TIC); 2370 2371 /* PHY disconnect */ 2372 if (ndev->phydev) { 2373 phy_stop(ndev->phydev); 2374 phy_disconnect(ndev->phydev); 2375 if (of_phy_is_fixed_link(np)) 2376 of_phy_deregister_fixed_link(np); 2377 } 2378 2379 /* Stop PTP Clock driver */ 2380 if (info->gptp || info->ccc_gac) 2381 ravb_ptp_stop(ndev); 2382 2383 /* Set the config mode to stop the AVB-DMAC's processes */ 2384 if (ravb_stop_dma(ndev) < 0) 2385 netdev_err(ndev, 2386 "device will be stopped after h/w processes are done.\n"); 2387 2388 /* Clear the timestamp list */ 2389 if (info->gptp || info->ccc_gac) { 2390 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 2391 list_del(&ts_skb->list); 2392 kfree_skb(ts_skb->skb); 2393 kfree(ts_skb); 2394 } 2395 } 2396 2397 cancel_work_sync(&priv->work); 2398 2399 if (info->nc_queues) 2400 napi_disable(&priv->napi[RAVB_NC]); 2401 napi_disable(&priv->napi[RAVB_BE]); 2402 2403 /* Free all the skb's in the RX queue and the DMA buffers. */ 2404 ravb_ring_free(ndev, RAVB_BE); 2405 if (info->nc_queues) 2406 ravb_ring_free(ndev, RAVB_NC); 2407 2408 /* Update statistics. */ 2409 ravb_get_stats(ndev); 2410 2411 /* Set reset mode. */ 2412 error = ravb_set_opmode(ndev, CCC_OPC_RESET); 2413 if (error) 2414 return error; 2415 2416 pm_runtime_put_autosuspend(dev); 2417 2418 return 0; 2419 } 2420 2421 static int ravb_hwtstamp_get(struct net_device *ndev, 2422 struct kernel_hwtstamp_config *config) 2423 { 2424 struct ravb_private *priv = netdev_priv(ndev); 2425 2426 config->flags = 0; 2427 config->tx_type = priv->tstamp_tx_ctrl; 2428 config->rx_filter = priv->tstamp_rx_ctrl; 2429 2430 return 0; 2431 } 2432 2433 /* Control hardware time stamping */ 2434 static int ravb_hwtstamp_set(struct net_device *ndev, 2435 struct kernel_hwtstamp_config *config, 2436 struct netlink_ext_ack *extack) 2437 { 2438 struct ravb_private *priv = netdev_priv(ndev); 2439 enum hwtstamp_rx_filters tstamp_rx_ctrl; 2440 enum hwtstamp_tx_types tstamp_tx_ctrl; 2441 2442 switch (config->tx_type) { 2443 case HWTSTAMP_TX_OFF: 2444 case HWTSTAMP_TX_ON: 2445 tstamp_tx_ctrl = config->tx_type; 2446 break; 2447 default: 2448 return -ERANGE; 2449 } 2450 2451 switch (config->rx_filter) { 2452 case HWTSTAMP_FILTER_NONE: 2453 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2454 tstamp_rx_ctrl = config->rx_filter; 2455 break; 2456 default: 2457 config->rx_filter = HWTSTAMP_FILTER_ALL; 2458 tstamp_rx_ctrl = HWTSTAMP_FILTER_ALL; 2459 } 2460 2461 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 2462 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 2463 2464 return 0; 2465 } 2466 2467 static int ravb_change_mtu(struct net_device *ndev, int new_mtu) 2468 { 2469 struct ravb_private *priv = netdev_priv(ndev); 2470 2471 WRITE_ONCE(ndev->mtu, new_mtu); 2472 2473 if (netif_running(ndev)) { 2474 synchronize_irq(priv->emac_irq); 2475 ravb_emac_init(ndev); 2476 } 2477 2478 netdev_update_features(ndev); 2479 2480 return 0; 2481 } 2482 2483 static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 2484 { 2485 struct ravb_private *priv = netdev_priv(ndev); 2486 unsigned long flags; 2487 2488 spin_lock_irqsave(&priv->lock, flags); 2489 2490 /* Disable TX and RX */ 2491 ravb_rcv_snd_disable(ndev); 2492 2493 /* Modify RX Checksum setting */ 2494 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 2495 2496 /* Enable TX and RX */ 2497 ravb_rcv_snd_enable(ndev); 2498 2499 spin_unlock_irqrestore(&priv->lock, flags); 2500 } 2501 2502 static int ravb_endisable_csum_gbeth(struct net_device *ndev, enum ravb_reg reg, 2503 u32 val, u32 mask) 2504 { 2505 u32 csr0 = CSR0_TPE | CSR0_RPE; 2506 int ret; 2507 2508 ravb_write(ndev, csr0 & ~mask, CSR0); 2509 ret = ravb_wait(ndev, CSR0, mask, 0); 2510 if (!ret) 2511 ravb_write(ndev, val, reg); 2512 2513 ravb_write(ndev, csr0, CSR0); 2514 2515 return ret; 2516 } 2517 2518 static int ravb_set_features_gbeth(struct net_device *ndev, 2519 netdev_features_t features) 2520 { 2521 netdev_features_t changed = ndev->features ^ features; 2522 struct ravb_private *priv = netdev_priv(ndev); 2523 unsigned long flags; 2524 int ret = 0; 2525 u32 val; 2526 2527 spin_lock_irqsave(&priv->lock, flags); 2528 if (changed & NETIF_F_RXCSUM) { 2529 if (features & NETIF_F_RXCSUM) 2530 val = CSR2_CSUM_ENABLE; 2531 else 2532 val = 0; 2533 2534 ret = ravb_endisable_csum_gbeth(ndev, CSR2, val, CSR0_RPE); 2535 if (ret) 2536 goto done; 2537 } 2538 2539 if (changed & NETIF_F_HW_CSUM) { 2540 if (features & NETIF_F_HW_CSUM) 2541 val = CSR1_CSUM_ENABLE; 2542 else 2543 val = 0; 2544 2545 ret = ravb_endisable_csum_gbeth(ndev, CSR1, val, CSR0_TPE); 2546 if (ret) 2547 goto done; 2548 } 2549 2550 done: 2551 spin_unlock_irqrestore(&priv->lock, flags); 2552 2553 return ret; 2554 } 2555 2556 static int ravb_set_features_rcar(struct net_device *ndev, 2557 netdev_features_t features) 2558 { 2559 netdev_features_t changed = ndev->features ^ features; 2560 2561 if (changed & NETIF_F_RXCSUM) 2562 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 2563 2564 return 0; 2565 } 2566 2567 static int ravb_set_features(struct net_device *ndev, 2568 netdev_features_t features) 2569 { 2570 struct ravb_private *priv = netdev_priv(ndev); 2571 const struct ravb_hw_info *info = priv->info; 2572 struct device *dev = &priv->pdev->dev; 2573 int ret; 2574 2575 pm_runtime_get_noresume(dev); 2576 2577 if (pm_runtime_active(dev)) 2578 ret = info->set_feature(ndev, features); 2579 else 2580 ret = 0; 2581 2582 pm_runtime_put_noidle(dev); 2583 2584 if (ret) 2585 return ret; 2586 2587 ndev->features = features; 2588 2589 return 0; 2590 } 2591 2592 static const struct net_device_ops ravb_netdev_ops = { 2593 .ndo_open = ravb_open, 2594 .ndo_stop = ravb_close, 2595 .ndo_start_xmit = ravb_start_xmit, 2596 .ndo_select_queue = ravb_select_queue, 2597 .ndo_get_stats = ravb_get_stats, 2598 .ndo_set_rx_mode = ravb_set_rx_mode, 2599 .ndo_tx_timeout = ravb_tx_timeout, 2600 .ndo_eth_ioctl = phy_do_ioctl_running, 2601 .ndo_change_mtu = ravb_change_mtu, 2602 .ndo_validate_addr = eth_validate_addr, 2603 .ndo_set_mac_address = eth_mac_addr, 2604 .ndo_set_features = ravb_set_features, 2605 .ndo_hwtstamp_get = ravb_hwtstamp_get, 2606 .ndo_hwtstamp_set = ravb_hwtstamp_set, 2607 }; 2608 2609 /* MDIO bus init function */ 2610 static int ravb_mdio_init(struct ravb_private *priv) 2611 { 2612 struct platform_device *pdev = priv->pdev; 2613 struct device *dev = &pdev->dev; 2614 struct device_node *mdio_node; 2615 struct phy_device *phydev; 2616 struct device_node *pn; 2617 int error; 2618 2619 /* Bitbang init */ 2620 priv->mdiobb.ops = &bb_ops; 2621 2622 /* MII controller setting */ 2623 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 2624 if (!priv->mii_bus) 2625 return -ENOMEM; 2626 2627 /* Hook up MII support for ethtool */ 2628 priv->mii_bus->name = "ravb_mii"; 2629 priv->mii_bus->parent = dev; 2630 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2631 pdev->name, pdev->id); 2632 2633 /* Register MDIO bus */ 2634 mdio_node = of_get_child_by_name(dev->of_node, "mdio"); 2635 if (!mdio_node) { 2636 /* backwards compatibility for DT lacking mdio subnode */ 2637 mdio_node = of_node_get(dev->of_node); 2638 } 2639 error = of_mdiobus_register(priv->mii_bus, mdio_node); 2640 of_node_put(mdio_node); 2641 if (error) 2642 goto out_free_bus; 2643 2644 pn = of_parse_phandle(dev->of_node, "phy-handle", 0); 2645 phydev = of_phy_find_device(pn); 2646 if (phydev) { 2647 phydev->mac_managed_pm = true; 2648 put_device(&phydev->mdio.dev); 2649 } 2650 of_node_put(pn); 2651 2652 return 0; 2653 2654 out_free_bus: 2655 free_mdio_bitbang(priv->mii_bus); 2656 return error; 2657 } 2658 2659 /* MDIO bus release function */ 2660 static int ravb_mdio_release(struct ravb_private *priv) 2661 { 2662 /* Unregister mdio bus */ 2663 mdiobus_unregister(priv->mii_bus); 2664 2665 /* Free bitbang info */ 2666 free_mdio_bitbang(priv->mii_bus); 2667 2668 return 0; 2669 } 2670 2671 static const struct ravb_hw_info ravb_gen2_hw_info = { 2672 .receive = ravb_rx_rcar, 2673 .set_rate = ravb_set_rate_rcar, 2674 .set_feature = ravb_set_features_rcar, 2675 .dmac_init = ravb_dmac_init_rcar, 2676 .emac_init = ravb_emac_init_rcar, 2677 .gstrings_stats = ravb_gstrings_stats, 2678 .gstrings_size = sizeof(ravb_gstrings_stats), 2679 .net_hw_features = NETIF_F_RXCSUM, 2680 .net_features = NETIF_F_RXCSUM, 2681 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2682 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2683 .tx_max_frame_size = SZ_2K, 2684 .rx_max_frame_size = SZ_2K, 2685 .rx_buffer_size = SZ_2K + 2686 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), 2687 .rx_desc_size = sizeof(struct ravb_ex_rx_desc), 2688 .dbat_entry_num = 22, 2689 .aligned_tx = 1, 2690 .gptp = 1, 2691 .nc_queues = 1, 2692 .magic_pkt = 1, 2693 }; 2694 2695 static const struct ravb_hw_info ravb_gen3_hw_info = { 2696 .receive = ravb_rx_rcar, 2697 .set_rate = ravb_set_rate_rcar, 2698 .set_feature = ravb_set_features_rcar, 2699 .dmac_init = ravb_dmac_init_rcar, 2700 .emac_init = ravb_emac_init_rcar, 2701 .gstrings_stats = ravb_gstrings_stats, 2702 .gstrings_size = sizeof(ravb_gstrings_stats), 2703 .net_hw_features = NETIF_F_RXCSUM, 2704 .net_features = NETIF_F_RXCSUM, 2705 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2706 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2707 .tx_max_frame_size = SZ_2K, 2708 .rx_max_frame_size = SZ_2K, 2709 .rx_buffer_size = SZ_2K + 2710 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), 2711 .rx_desc_size = sizeof(struct ravb_ex_rx_desc), 2712 .dbat_entry_num = 22, 2713 .internal_delay = 1, 2714 .tx_counters = 1, 2715 .multi_irqs = 1, 2716 .irq_en_dis = 1, 2717 .ccc_gac = 1, 2718 .nc_queues = 1, 2719 .magic_pkt = 1, 2720 }; 2721 2722 static const struct ravb_hw_info ravb_gen4_hw_info = { 2723 .receive = ravb_rx_rcar, 2724 .set_rate = ravb_set_rate_rcar, 2725 .set_feature = ravb_set_features_rcar, 2726 .dmac_init = ravb_dmac_init_rcar, 2727 .emac_init = ravb_emac_init_rcar_gen4, 2728 .gstrings_stats = ravb_gstrings_stats, 2729 .gstrings_size = sizeof(ravb_gstrings_stats), 2730 .net_hw_features = NETIF_F_RXCSUM, 2731 .net_features = NETIF_F_RXCSUM, 2732 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2733 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2734 .tx_max_frame_size = SZ_2K, 2735 .rx_max_frame_size = SZ_2K, 2736 .rx_buffer_size = SZ_2K + 2737 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), 2738 .rx_desc_size = sizeof(struct ravb_ex_rx_desc), 2739 .dbat_entry_num = 22, 2740 .internal_delay = 1, 2741 .tx_counters = 1, 2742 .multi_irqs = 1, 2743 .irq_en_dis = 1, 2744 .ccc_gac = 1, 2745 .nc_queues = 1, 2746 .magic_pkt = 1, 2747 }; 2748 2749 static const struct ravb_hw_info ravb_rzv2m_hw_info = { 2750 .receive = ravb_rx_rcar, 2751 .set_rate = ravb_set_rate_rcar, 2752 .set_feature = ravb_set_features_rcar, 2753 .dmac_init = ravb_dmac_init_rcar, 2754 .emac_init = ravb_emac_init_rcar, 2755 .gstrings_stats = ravb_gstrings_stats, 2756 .gstrings_size = sizeof(ravb_gstrings_stats), 2757 .net_hw_features = NETIF_F_RXCSUM, 2758 .net_features = NETIF_F_RXCSUM, 2759 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2760 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2761 .tx_max_frame_size = SZ_2K, 2762 .rx_max_frame_size = SZ_2K, 2763 .rx_buffer_size = SZ_2K + 2764 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), 2765 .rx_desc_size = sizeof(struct ravb_ex_rx_desc), 2766 .dbat_entry_num = 22, 2767 .multi_irqs = 1, 2768 .err_mgmt_irqs = 1, 2769 .gptp = 1, 2770 .gptp_ref_clk = 1, 2771 .nc_queues = 1, 2772 .magic_pkt = 1, 2773 }; 2774 2775 static const struct ravb_hw_info gbeth_hw_info = { 2776 .receive = ravb_rx_gbeth, 2777 .set_rate = ravb_set_rate_gbeth, 2778 .set_feature = ravb_set_features_gbeth, 2779 .dmac_init = ravb_dmac_init_gbeth, 2780 .emac_init = ravb_emac_init_gbeth, 2781 .gstrings_stats = ravb_gstrings_stats_gbeth, 2782 .gstrings_size = sizeof(ravb_gstrings_stats_gbeth), 2783 .net_hw_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM, 2784 .net_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM, 2785 .vlan_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM, 2786 .stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth), 2787 .tccr_mask = TCCR_TSRQ0, 2788 .tx_max_frame_size = 1522, 2789 .rx_max_frame_size = SZ_8K, 2790 .rx_buffer_size = SZ_2K, 2791 .rx_desc_size = sizeof(struct ravb_rx_desc), 2792 .dbat_entry_num = 2, 2793 .aligned_tx = 1, 2794 .coalesce_irqs = 1, 2795 .tx_counters = 1, 2796 .carrier_counters = 1, 2797 .half_duplex = 1, 2798 }; 2799 2800 static const struct of_device_id ravb_match_table[] = { 2801 { .compatible = "renesas,etheravb-r8a7790", .data = &ravb_gen2_hw_info }, 2802 { .compatible = "renesas,etheravb-r8a7794", .data = &ravb_gen2_hw_info }, 2803 { .compatible = "renesas,etheravb-rcar-gen2", .data = &ravb_gen2_hw_info }, 2804 { .compatible = "renesas,etheravb-r8a7795", .data = &ravb_gen3_hw_info }, 2805 { .compatible = "renesas,etheravb-rcar-gen3", .data = &ravb_gen3_hw_info }, 2806 { .compatible = "renesas,etheravb-rcar-gen4", .data = &ravb_gen4_hw_info }, 2807 { .compatible = "renesas,etheravb-rzv2m", .data = &ravb_rzv2m_hw_info }, 2808 { .compatible = "renesas,rzg2l-gbeth", .data = &gbeth_hw_info }, 2809 { } 2810 }; 2811 MODULE_DEVICE_TABLE(of, ravb_match_table); 2812 2813 static int ravb_setup_irq(struct ravb_private *priv, const char *irq_name, 2814 const char *ch, int *irq, irq_handler_t handler) 2815 { 2816 struct platform_device *pdev = priv->pdev; 2817 struct net_device *ndev = priv->ndev; 2818 struct device *dev = &pdev->dev; 2819 const char *devname = dev_name(dev); 2820 unsigned long flags; 2821 int error, irq_num; 2822 2823 if (irq_name) { 2824 devname = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", devname, ch); 2825 if (!devname) 2826 return -ENOMEM; 2827 2828 irq_num = platform_get_irq_byname(pdev, irq_name); 2829 flags = 0; 2830 } else { 2831 irq_num = platform_get_irq(pdev, 0); 2832 flags = IRQF_SHARED; 2833 } 2834 if (irq_num < 0) 2835 return irq_num; 2836 2837 if (irq) 2838 *irq = irq_num; 2839 2840 error = devm_request_irq(dev, irq_num, handler, flags, devname, ndev); 2841 if (error) 2842 netdev_err(ndev, "cannot request IRQ %s\n", devname); 2843 2844 return error; 2845 } 2846 2847 static int ravb_setup_irqs(struct ravb_private *priv) 2848 { 2849 const struct ravb_hw_info *info = priv->info; 2850 struct net_device *ndev = priv->ndev; 2851 const char *irq_name, *emac_irq_name; 2852 int error; 2853 2854 if (!info->multi_irqs) 2855 return ravb_setup_irq(priv, NULL, NULL, &ndev->irq, ravb_interrupt); 2856 2857 if (info->err_mgmt_irqs) { 2858 irq_name = "dia"; 2859 emac_irq_name = "line3"; 2860 } else { 2861 irq_name = "ch22"; 2862 emac_irq_name = "ch24"; 2863 } 2864 2865 error = ravb_setup_irq(priv, irq_name, "ch22:multi", &ndev->irq, ravb_multi_interrupt); 2866 if (error) 2867 return error; 2868 2869 error = ravb_setup_irq(priv, emac_irq_name, "ch24:emac", &priv->emac_irq, 2870 ravb_emac_interrupt); 2871 if (error) 2872 return error; 2873 2874 if (info->err_mgmt_irqs) { 2875 error = ravb_setup_irq(priv, "err_a", "err_a", NULL, ravb_multi_interrupt); 2876 if (error) 2877 return error; 2878 2879 error = ravb_setup_irq(priv, "mgmt_a", "mgmt_a", NULL, ravb_multi_interrupt); 2880 if (error) 2881 return error; 2882 } 2883 2884 error = ravb_setup_irq(priv, "ch0", "ch0:rx_be", NULL, ravb_be_interrupt); 2885 if (error) 2886 return error; 2887 2888 error = ravb_setup_irq(priv, "ch1", "ch1:rx_nc", NULL, ravb_nc_interrupt); 2889 if (error) 2890 return error; 2891 2892 error = ravb_setup_irq(priv, "ch18", "ch18:tx_be", NULL, ravb_be_interrupt); 2893 if (error) 2894 return error; 2895 2896 return ravb_setup_irq(priv, "ch19", "ch19:tx_nc", NULL, ravb_nc_interrupt); 2897 } 2898 2899 static int ravb_probe(struct platform_device *pdev) 2900 { 2901 struct device_node *np = pdev->dev.of_node; 2902 const struct ravb_hw_info *info; 2903 struct reset_control *rstc; 2904 struct ravb_private *priv; 2905 struct net_device *ndev; 2906 struct resource *res; 2907 int error, q; 2908 2909 if (!np) { 2910 dev_err(&pdev->dev, 2911 "this driver is required to be instantiated from device tree\n"); 2912 return -EINVAL; 2913 } 2914 2915 rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 2916 if (IS_ERR(rstc)) 2917 return dev_err_probe(&pdev->dev, PTR_ERR(rstc), 2918 "failed to get cpg reset\n"); 2919 2920 info = of_device_get_match_data(&pdev->dev); 2921 2922 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 2923 info->nc_queues ? NUM_TX_QUEUE : 1, 2924 info->nc_queues ? NUM_RX_QUEUE : 1); 2925 if (!ndev) 2926 return -ENOMEM; 2927 2928 ndev->features = info->net_features; 2929 ndev->hw_features = info->net_hw_features; 2930 ndev->vlan_features = info->vlan_features; 2931 2932 error = reset_control_deassert(rstc); 2933 if (error) 2934 goto out_free_netdev; 2935 2936 SET_NETDEV_DEV(ndev, &pdev->dev); 2937 2938 priv = netdev_priv(ndev); 2939 priv->info = info; 2940 priv->rstc = rstc; 2941 priv->ndev = ndev; 2942 priv->pdev = pdev; 2943 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2944 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2945 if (info->nc_queues) { 2946 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2947 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2948 } 2949 2950 error = ravb_setup_irqs(priv); 2951 if (error) 2952 goto out_reset_assert; 2953 2954 priv->clk = devm_clk_get(&pdev->dev, NULL); 2955 if (IS_ERR(priv->clk)) { 2956 error = PTR_ERR(priv->clk); 2957 goto out_reset_assert; 2958 } 2959 2960 if (info->gptp_ref_clk) { 2961 priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp"); 2962 if (IS_ERR(priv->gptp_clk)) { 2963 error = PTR_ERR(priv->gptp_clk); 2964 goto out_reset_assert; 2965 } 2966 } 2967 2968 priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk"); 2969 if (IS_ERR(priv->refclk)) { 2970 error = PTR_ERR(priv->refclk); 2971 goto out_reset_assert; 2972 } 2973 clk_prepare(priv->refclk); 2974 2975 platform_set_drvdata(pdev, ndev); 2976 pm_runtime_set_autosuspend_delay(&pdev->dev, 100); 2977 pm_runtime_use_autosuspend(&pdev->dev); 2978 pm_runtime_enable(&pdev->dev); 2979 error = pm_runtime_resume_and_get(&pdev->dev); 2980 if (error < 0) 2981 goto out_rpm_disable; 2982 2983 priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2984 if (IS_ERR(priv->addr)) { 2985 error = PTR_ERR(priv->addr); 2986 goto out_rpm_put; 2987 } 2988 2989 /* The Ether-specific entries in the device structure. */ 2990 ndev->base_addr = res->start; 2991 2992 spin_lock_init(&priv->lock); 2993 INIT_WORK(&priv->work, ravb_tx_timeout_work); 2994 2995 error = of_get_phy_mode(np, &priv->phy_interface); 2996 if (error && error != -ENODEV) 2997 goto out_rpm_put; 2998 2999 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 3000 priv->avb_link_active_low = 3001 of_property_read_bool(np, "renesas,ether-link-active-low"); 3002 3003 ndev->max_mtu = info->tx_max_frame_size - 3004 (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 3005 ndev->min_mtu = ETH_MIN_MTU; 3006 3007 /* FIXME: R-Car Gen2 has 4byte alignment restriction for tx buffer 3008 * Use two descriptor to handle such situation. First descriptor to 3009 * handle aligned data buffer and second descriptor to handle the 3010 * overflow data because of alignment. 3011 */ 3012 priv->num_tx_desc = info->aligned_tx ? 2 : 1; 3013 3014 /* Set function */ 3015 ndev->netdev_ops = &ravb_netdev_ops; 3016 ndev->ethtool_ops = &ravb_ethtool_ops; 3017 3018 error = ravb_compute_gti(ndev); 3019 if (error) 3020 goto out_rpm_put; 3021 3022 ravb_parse_delay_mode(np, ndev); 3023 3024 /* Allocate descriptor base address table */ 3025 priv->desc_bat_size = sizeof(struct ravb_desc) * info->dbat_entry_num; 3026 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 3027 &priv->desc_bat_dma, GFP_KERNEL); 3028 if (!priv->desc_bat) { 3029 dev_err(&pdev->dev, 3030 "Cannot allocate desc base address table (size %d bytes)\n", 3031 priv->desc_bat_size); 3032 error = -ENOMEM; 3033 goto out_rpm_put; 3034 } 3035 for (q = RAVB_BE; q < info->dbat_entry_num; q++) 3036 priv->desc_bat[q].die_dt = DT_EOS; 3037 3038 /* Initialise HW timestamp list */ 3039 INIT_LIST_HEAD(&priv->ts_skb_list); 3040 3041 /* Debug message level */ 3042 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 3043 3044 /* Set config mode as this is needed for PHY initialization. */ 3045 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 3046 if (error) 3047 goto out_rpm_put; 3048 3049 /* Read and set MAC address */ 3050 ravb_read_mac_address(np, ndev); 3051 if (!is_valid_ether_addr(ndev->dev_addr)) { 3052 dev_warn(&pdev->dev, 3053 "no valid MAC address supplied, using a random one\n"); 3054 eth_hw_addr_random(ndev); 3055 } 3056 3057 /* MDIO bus init */ 3058 error = ravb_mdio_init(priv); 3059 if (error) { 3060 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 3061 goto out_reset_mode; 3062 } 3063 3064 /* Undo previous switch to config opmode. */ 3065 error = ravb_set_opmode(ndev, CCC_OPC_RESET); 3066 if (error) 3067 goto out_mdio_release; 3068 3069 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll); 3070 if (info->nc_queues) 3071 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll); 3072 3073 if (info->coalesce_irqs) { 3074 netdev_sw_irq_coalesce_default_on(ndev); 3075 if (num_present_cpus() == 1) 3076 netif_threaded_enable(ndev); 3077 } 3078 3079 /* Network device register */ 3080 error = register_netdev(ndev); 3081 if (error) 3082 goto out_napi_del; 3083 3084 device_set_wakeup_capable(&pdev->dev, 1); 3085 3086 /* Print device information */ 3087 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 3088 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 3089 3090 pm_runtime_put_autosuspend(&pdev->dev); 3091 3092 return 0; 3093 3094 out_napi_del: 3095 if (info->nc_queues) 3096 netif_napi_del(&priv->napi[RAVB_NC]); 3097 3098 netif_napi_del(&priv->napi[RAVB_BE]); 3099 out_mdio_release: 3100 ravb_mdio_release(priv); 3101 out_reset_mode: 3102 ravb_set_opmode(ndev, CCC_OPC_RESET); 3103 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 3104 priv->desc_bat_dma); 3105 out_rpm_put: 3106 pm_runtime_put(&pdev->dev); 3107 out_rpm_disable: 3108 pm_runtime_disable(&pdev->dev); 3109 pm_runtime_dont_use_autosuspend(&pdev->dev); 3110 clk_unprepare(priv->refclk); 3111 out_reset_assert: 3112 reset_control_assert(rstc); 3113 out_free_netdev: 3114 free_netdev(ndev); 3115 return error; 3116 } 3117 3118 static void ravb_remove(struct platform_device *pdev) 3119 { 3120 struct net_device *ndev = platform_get_drvdata(pdev); 3121 struct ravb_private *priv = netdev_priv(ndev); 3122 const struct ravb_hw_info *info = priv->info; 3123 struct device *dev = &priv->pdev->dev; 3124 int error; 3125 3126 error = pm_runtime_resume_and_get(dev); 3127 if (error < 0) 3128 return; 3129 3130 unregister_netdev(ndev); 3131 if (info->nc_queues) 3132 netif_napi_del(&priv->napi[RAVB_NC]); 3133 netif_napi_del(&priv->napi[RAVB_BE]); 3134 3135 ravb_mdio_release(priv); 3136 3137 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 3138 priv->desc_bat_dma); 3139 3140 pm_runtime_put_sync_suspend(&pdev->dev); 3141 pm_runtime_disable(&pdev->dev); 3142 pm_runtime_dont_use_autosuspend(dev); 3143 clk_unprepare(priv->refclk); 3144 reset_control_assert(priv->rstc); 3145 free_netdev(ndev); 3146 platform_set_drvdata(pdev, NULL); 3147 } 3148 3149 static int ravb_wol_setup(struct net_device *ndev) 3150 { 3151 struct ravb_private *priv = netdev_priv(ndev); 3152 const struct ravb_hw_info *info = priv->info; 3153 3154 /* Disable interrupts by clearing the interrupt masks. */ 3155 ravb_write(ndev, 0, RIC0); 3156 ravb_write(ndev, 0, RIC2); 3157 ravb_write(ndev, 0, TIC); 3158 3159 /* Only allow ECI interrupts */ 3160 synchronize_irq(priv->emac_irq); 3161 if (info->nc_queues) 3162 napi_disable(&priv->napi[RAVB_NC]); 3163 napi_disable(&priv->napi[RAVB_BE]); 3164 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 3165 3166 /* Enable MagicPacket */ 3167 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 3168 3169 if (priv->info->ccc_gac) 3170 ravb_ptp_stop(ndev); 3171 3172 return enable_irq_wake(priv->emac_irq); 3173 } 3174 3175 static int ravb_wol_restore(struct net_device *ndev) 3176 { 3177 struct ravb_private *priv = netdev_priv(ndev); 3178 const struct ravb_hw_info *info = priv->info; 3179 int error; 3180 3181 /* Set reset mode to rearm the WoL logic. */ 3182 error = ravb_set_opmode(ndev, CCC_OPC_RESET); 3183 if (error) 3184 return error; 3185 3186 /* Set AVB config mode. */ 3187 error = ravb_set_config_mode(ndev); 3188 if (error) 3189 return error; 3190 3191 if (priv->info->ccc_gac) 3192 ravb_ptp_init(ndev, priv->pdev); 3193 3194 if (info->nc_queues) 3195 napi_enable(&priv->napi[RAVB_NC]); 3196 napi_enable(&priv->napi[RAVB_BE]); 3197 3198 /* Disable MagicPacket */ 3199 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 3200 3201 ravb_close(ndev); 3202 3203 return disable_irq_wake(priv->emac_irq); 3204 } 3205 3206 static int ravb_suspend(struct device *dev) 3207 { 3208 struct net_device *ndev = dev_get_drvdata(dev); 3209 struct ravb_private *priv = netdev_priv(ndev); 3210 int ret; 3211 3212 if (!netif_running(ndev)) 3213 goto reset_assert; 3214 3215 netif_device_detach(ndev); 3216 3217 rtnl_lock(); 3218 if (priv->wol_enabled) { 3219 ret = ravb_wol_setup(ndev); 3220 rtnl_unlock(); 3221 return ret; 3222 } 3223 3224 ret = ravb_close(ndev); 3225 rtnl_unlock(); 3226 if (ret) 3227 return ret; 3228 3229 ret = pm_runtime_force_suspend(&priv->pdev->dev); 3230 if (ret) 3231 return ret; 3232 3233 reset_assert: 3234 return reset_control_assert(priv->rstc); 3235 } 3236 3237 static int ravb_resume(struct device *dev) 3238 { 3239 struct net_device *ndev = dev_get_drvdata(dev); 3240 struct ravb_private *priv = netdev_priv(ndev); 3241 int ret; 3242 3243 ret = reset_control_deassert(priv->rstc); 3244 if (ret) 3245 return ret; 3246 3247 if (!netif_running(ndev)) 3248 return 0; 3249 3250 rtnl_lock(); 3251 /* If WoL is enabled restore the interface. */ 3252 if (priv->wol_enabled) 3253 ret = ravb_wol_restore(ndev); 3254 else 3255 ret = pm_runtime_force_resume(dev); 3256 if (ret) { 3257 rtnl_unlock(); 3258 return ret; 3259 } 3260 3261 /* Reopening the interface will restore the device to the working state. */ 3262 ret = ravb_open(ndev); 3263 rtnl_unlock(); 3264 if (ret < 0) 3265 goto out_rpm_put; 3266 3267 ravb_set_rx_mode(ndev); 3268 netif_device_attach(ndev); 3269 3270 return 0; 3271 3272 out_rpm_put: 3273 if (!priv->wol_enabled) 3274 pm_runtime_put_autosuspend(dev); 3275 3276 return ret; 3277 } 3278 3279 static int ravb_runtime_suspend(struct device *dev) 3280 { 3281 struct net_device *ndev = dev_get_drvdata(dev); 3282 struct ravb_private *priv = netdev_priv(ndev); 3283 3284 clk_disable(priv->refclk); 3285 3286 return 0; 3287 } 3288 3289 static int ravb_runtime_resume(struct device *dev) 3290 { 3291 struct net_device *ndev = dev_get_drvdata(dev); 3292 struct ravb_private *priv = netdev_priv(ndev); 3293 3294 return clk_enable(priv->refclk); 3295 } 3296 3297 static const struct dev_pm_ops ravb_dev_pm_ops = { 3298 SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 3299 RUNTIME_PM_OPS(ravb_runtime_suspend, ravb_runtime_resume, NULL) 3300 }; 3301 3302 static struct platform_driver ravb_driver = { 3303 .probe = ravb_probe, 3304 .remove = ravb_remove, 3305 .driver = { 3306 .name = "ravb", 3307 .pm = pm_ptr(&ravb_dev_pm_ops), 3308 .of_match_table = ravb_match_table, 3309 }, 3310 }; 3311 3312 module_platform_driver(ravb_driver); 3313 3314 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 3315 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 3316 MODULE_LICENSE("GPL v2"); 3317