1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet AVB device driver 3 * 4 * Copyright (C) 2014-2019 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * Based on the SuperH Ethernet driver 9 */ 10 11 #include <linux/cache.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_vlan.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/module.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/of.h> 24 #include <linux/of_mdio.h> 25 #include <linux/of_net.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/slab.h> 29 #include <linux/spinlock.h> 30 #include <linux/reset.h> 31 #include <linux/math64.h> 32 #include <net/ip.h> 33 34 #include "ravb.h" 35 36 #define RAVB_DEF_MSG_ENABLE \ 37 (NETIF_MSG_LINK | \ 38 NETIF_MSG_TIMER | \ 39 NETIF_MSG_RX_ERR | \ 40 NETIF_MSG_TX_ERR) 41 42 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 43 u32 set) 44 { 45 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 46 } 47 48 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 49 { 50 int i; 51 52 for (i = 0; i < 10000; i++) { 53 if ((ravb_read(ndev, reg) & mask) == value) 54 return 0; 55 udelay(10); 56 } 57 return -ETIMEDOUT; 58 } 59 60 static int ravb_set_opmode(struct net_device *ndev, u32 opmode) 61 { 62 u32 csr_ops = 1U << (opmode & CCC_OPC); 63 u32 ccc_mask = CCC_OPC; 64 int error; 65 66 /* If gPTP active in config mode is supported it needs to be configured 67 * along with CSEL and operating mode in the same access. This is a 68 * hardware limitation. 69 */ 70 if (opmode & CCC_GAC) 71 ccc_mask |= CCC_GAC | CCC_CSEL; 72 73 /* Set operating mode */ 74 ravb_modify(ndev, CCC, ccc_mask, opmode); 75 /* Check if the operating mode is changed to the requested one */ 76 error = ravb_wait(ndev, CSR, CSR_OPS, csr_ops); 77 if (error) { 78 netdev_err(ndev, "failed to switch device to requested mode (%u)\n", 79 opmode & CCC_OPC); 80 } 81 82 return error; 83 } 84 85 static void ravb_set_rate_gbeth(struct net_device *ndev) 86 { 87 struct ravb_private *priv = netdev_priv(ndev); 88 89 switch (priv->speed) { 90 case 10: /* 10BASE */ 91 ravb_write(ndev, GBETH_GECMR_SPEED_10, GECMR); 92 break; 93 case 100: /* 100BASE */ 94 ravb_write(ndev, GBETH_GECMR_SPEED_100, GECMR); 95 break; 96 case 1000: /* 1000BASE */ 97 ravb_write(ndev, GBETH_GECMR_SPEED_1000, GECMR); 98 break; 99 } 100 } 101 102 static void ravb_set_rate_rcar(struct net_device *ndev) 103 { 104 struct ravb_private *priv = netdev_priv(ndev); 105 106 switch (priv->speed) { 107 case 100: /* 100BASE */ 108 ravb_write(ndev, GECMR_SPEED_100, GECMR); 109 break; 110 case 1000: /* 1000BASE */ 111 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 112 break; 113 } 114 } 115 116 static struct sk_buff * 117 ravb_alloc_skb(struct net_device *ndev, const struct ravb_hw_info *info, 118 gfp_t gfp_mask) 119 { 120 struct sk_buff *skb; 121 u32 reserve; 122 123 skb = __netdev_alloc_skb(ndev, info->rx_max_frame_size + RAVB_ALIGN - 1, 124 gfp_mask); 125 if (!skb) 126 return NULL; 127 128 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 129 if (reserve) 130 skb_reserve(skb, RAVB_ALIGN - reserve); 131 132 return skb; 133 } 134 135 /* Get MAC address from the MAC address registers 136 * 137 * Ethernet AVB device doesn't have ROM for MAC address. 138 * This function gets the MAC address that was used by a bootloader. 139 */ 140 static void ravb_read_mac_address(struct device_node *np, 141 struct net_device *ndev) 142 { 143 int ret; 144 145 ret = of_get_ethdev_address(np, ndev); 146 if (ret) { 147 u32 mahr = ravb_read(ndev, MAHR); 148 u32 malr = ravb_read(ndev, MALR); 149 u8 addr[ETH_ALEN]; 150 151 addr[0] = (mahr >> 24) & 0xFF; 152 addr[1] = (mahr >> 16) & 0xFF; 153 addr[2] = (mahr >> 8) & 0xFF; 154 addr[3] = (mahr >> 0) & 0xFF; 155 addr[4] = (malr >> 8) & 0xFF; 156 addr[5] = (malr >> 0) & 0xFF; 157 eth_hw_addr_set(ndev, addr); 158 } 159 } 160 161 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 162 { 163 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 164 mdiobb); 165 166 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 167 } 168 169 /* MDC pin control */ 170 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 171 { 172 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 173 } 174 175 /* Data I/O pin control */ 176 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 177 { 178 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 179 } 180 181 /* Set data bit */ 182 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 183 { 184 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 185 } 186 187 /* Get data bit */ 188 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 189 { 190 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 191 mdiobb); 192 193 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 194 } 195 196 /* MDIO bus control struct */ 197 static const struct mdiobb_ops bb_ops = { 198 .owner = THIS_MODULE, 199 .set_mdc = ravb_set_mdc, 200 .set_mdio_dir = ravb_set_mdio_dir, 201 .set_mdio_data = ravb_set_mdio_data, 202 .get_mdio_data = ravb_get_mdio_data, 203 }; 204 205 static struct ravb_rx_desc * 206 ravb_rx_get_desc(struct ravb_private *priv, unsigned int q, 207 unsigned int i) 208 { 209 return priv->rx_ring[q].raw + priv->info->rx_desc_size * i; 210 } 211 212 /* Free TX skb function for AVB-IP */ 213 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 214 { 215 struct ravb_private *priv = netdev_priv(ndev); 216 struct net_device_stats *stats = &priv->stats[q]; 217 unsigned int num_tx_desc = priv->num_tx_desc; 218 struct ravb_tx_desc *desc; 219 unsigned int entry; 220 int free_num = 0; 221 u32 size; 222 223 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 224 bool txed; 225 226 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 227 num_tx_desc); 228 desc = &priv->tx_ring[q][entry]; 229 txed = desc->die_dt == DT_FEMPTY; 230 if (free_txed_only && !txed) 231 break; 232 /* Descriptor type must be checked before all other reads */ 233 dma_rmb(); 234 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 235 /* Free the original skb. */ 236 if (priv->tx_skb[q][entry / num_tx_desc]) { 237 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 238 size, DMA_TO_DEVICE); 239 /* Last packet descriptor? */ 240 if (entry % num_tx_desc == num_tx_desc - 1) { 241 entry /= num_tx_desc; 242 dev_kfree_skb_any(priv->tx_skb[q][entry]); 243 priv->tx_skb[q][entry] = NULL; 244 if (txed) 245 stats->tx_packets++; 246 } 247 free_num++; 248 } 249 if (txed) 250 stats->tx_bytes += size; 251 desc->die_dt = DT_EEMPTY; 252 } 253 return free_num; 254 } 255 256 static void ravb_rx_ring_free(struct net_device *ndev, int q) 257 { 258 struct ravb_private *priv = netdev_priv(ndev); 259 unsigned int ring_size; 260 unsigned int i; 261 262 if (!priv->rx_ring[q].raw) 263 return; 264 265 for (i = 0; i < priv->num_rx_ring[q]; i++) { 266 struct ravb_rx_desc *desc = ravb_rx_get_desc(priv, q, i); 267 268 if (!dma_mapping_error(ndev->dev.parent, 269 le32_to_cpu(desc->dptr))) 270 dma_unmap_single(ndev->dev.parent, 271 le32_to_cpu(desc->dptr), 272 priv->info->rx_max_frame_size, 273 DMA_FROM_DEVICE); 274 } 275 ring_size = priv->info->rx_desc_size * (priv->num_rx_ring[q] + 1); 276 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q].raw, 277 priv->rx_desc_dma[q]); 278 priv->rx_ring[q].raw = NULL; 279 } 280 281 /* Free skb's and DMA buffers for Ethernet AVB */ 282 static void ravb_ring_free(struct net_device *ndev, int q) 283 { 284 struct ravb_private *priv = netdev_priv(ndev); 285 unsigned int num_tx_desc = priv->num_tx_desc; 286 unsigned int ring_size; 287 unsigned int i; 288 289 ravb_rx_ring_free(ndev, q); 290 291 if (priv->tx_ring[q]) { 292 ravb_tx_free(ndev, q, false); 293 294 ring_size = sizeof(struct ravb_tx_desc) * 295 (priv->num_tx_ring[q] * num_tx_desc + 1); 296 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 297 priv->tx_desc_dma[q]); 298 priv->tx_ring[q] = NULL; 299 } 300 301 /* Free RX skb ringbuffer */ 302 if (priv->rx_skb[q]) { 303 for (i = 0; i < priv->num_rx_ring[q]; i++) 304 dev_kfree_skb(priv->rx_skb[q][i]); 305 } 306 kfree(priv->rx_skb[q]); 307 priv->rx_skb[q] = NULL; 308 309 /* Free aligned TX buffers */ 310 kfree(priv->tx_align[q]); 311 priv->tx_align[q] = NULL; 312 313 /* Free TX skb ringbuffer. 314 * SKBs are freed by ravb_tx_free() call above. 315 */ 316 kfree(priv->tx_skb[q]); 317 priv->tx_skb[q] = NULL; 318 } 319 320 static void ravb_rx_ring_format(struct net_device *ndev, int q) 321 { 322 struct ravb_private *priv = netdev_priv(ndev); 323 struct ravb_rx_desc *rx_desc; 324 unsigned int rx_ring_size; 325 dma_addr_t dma_addr; 326 unsigned int i; 327 328 rx_ring_size = priv->info->rx_desc_size * priv->num_rx_ring[q]; 329 memset(priv->rx_ring[q].raw, 0, rx_ring_size); 330 /* Build RX ring buffer */ 331 for (i = 0; i < priv->num_rx_ring[q]; i++) { 332 /* RX descriptor */ 333 rx_desc = ravb_rx_get_desc(priv, q, i); 334 rx_desc->ds_cc = cpu_to_le16(priv->info->rx_max_desc_use); 335 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 336 priv->info->rx_max_frame_size, 337 DMA_FROM_DEVICE); 338 /* We just set the data size to 0 for a failed mapping which 339 * should prevent DMA from happening... 340 */ 341 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 342 rx_desc->ds_cc = cpu_to_le16(0); 343 rx_desc->dptr = cpu_to_le32(dma_addr); 344 rx_desc->die_dt = DT_FEMPTY; 345 } 346 rx_desc = ravb_rx_get_desc(priv, q, i); 347 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 348 rx_desc->die_dt = DT_LINKFIX; /* type */ 349 } 350 351 /* Format skb and descriptor buffer for Ethernet AVB */ 352 static void ravb_ring_format(struct net_device *ndev, int q) 353 { 354 struct ravb_private *priv = netdev_priv(ndev); 355 unsigned int num_tx_desc = priv->num_tx_desc; 356 struct ravb_tx_desc *tx_desc; 357 struct ravb_desc *desc; 358 unsigned int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 359 num_tx_desc; 360 unsigned int i; 361 362 priv->cur_rx[q] = 0; 363 priv->cur_tx[q] = 0; 364 priv->dirty_rx[q] = 0; 365 priv->dirty_tx[q] = 0; 366 367 ravb_rx_ring_format(ndev, q); 368 369 memset(priv->tx_ring[q], 0, tx_ring_size); 370 /* Build TX ring buffer */ 371 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 372 i++, tx_desc++) { 373 tx_desc->die_dt = DT_EEMPTY; 374 if (num_tx_desc > 1) { 375 tx_desc++; 376 tx_desc->die_dt = DT_EEMPTY; 377 } 378 } 379 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 380 tx_desc->die_dt = DT_LINKFIX; /* type */ 381 382 /* RX descriptor base address for best effort */ 383 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 384 desc->die_dt = DT_LINKFIX; /* type */ 385 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 386 387 /* TX descriptor base address for best effort */ 388 desc = &priv->desc_bat[q]; 389 desc->die_dt = DT_LINKFIX; /* type */ 390 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 391 } 392 393 static void *ravb_alloc_rx_desc(struct net_device *ndev, int q) 394 { 395 struct ravb_private *priv = netdev_priv(ndev); 396 unsigned int ring_size; 397 398 ring_size = priv->info->rx_desc_size * (priv->num_rx_ring[q] + 1); 399 400 priv->rx_ring[q].raw = dma_alloc_coherent(ndev->dev.parent, ring_size, 401 &priv->rx_desc_dma[q], 402 GFP_KERNEL); 403 404 return priv->rx_ring[q].raw; 405 } 406 407 /* Init skb and descriptor buffer for Ethernet AVB */ 408 static int ravb_ring_init(struct net_device *ndev, int q) 409 { 410 struct ravb_private *priv = netdev_priv(ndev); 411 const struct ravb_hw_info *info = priv->info; 412 unsigned int num_tx_desc = priv->num_tx_desc; 413 unsigned int ring_size; 414 struct sk_buff *skb; 415 unsigned int i; 416 417 /* Allocate RX and TX skb rings */ 418 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 419 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 420 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 421 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 422 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 423 goto error; 424 425 for (i = 0; i < priv->num_rx_ring[q]; i++) { 426 skb = ravb_alloc_skb(ndev, info, GFP_KERNEL); 427 if (!skb) 428 goto error; 429 priv->rx_skb[q][i] = skb; 430 } 431 432 if (num_tx_desc > 1) { 433 /* Allocate rings for the aligned buffers */ 434 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 435 DPTR_ALIGN - 1, GFP_KERNEL); 436 if (!priv->tx_align[q]) 437 goto error; 438 } 439 440 /* Allocate all RX descriptors. */ 441 if (!ravb_alloc_rx_desc(ndev, q)) 442 goto error; 443 444 priv->dirty_rx[q] = 0; 445 446 /* Allocate all TX descriptors. */ 447 ring_size = sizeof(struct ravb_tx_desc) * 448 (priv->num_tx_ring[q] * num_tx_desc + 1); 449 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 450 &priv->tx_desc_dma[q], 451 GFP_KERNEL); 452 if (!priv->tx_ring[q]) 453 goto error; 454 455 return 0; 456 457 error: 458 ravb_ring_free(ndev, q); 459 460 return -ENOMEM; 461 } 462 463 static void ravb_csum_init_gbeth(struct net_device *ndev) 464 { 465 bool tx_enable = ndev->features & NETIF_F_HW_CSUM; 466 bool rx_enable = ndev->features & NETIF_F_RXCSUM; 467 468 if (!(tx_enable || rx_enable)) 469 goto done; 470 471 ravb_write(ndev, 0, CSR0); 472 if (ravb_wait(ndev, CSR0, CSR0_TPE | CSR0_RPE, 0)) { 473 netdev_err(ndev, "Timeout enabling hardware checksum\n"); 474 475 if (tx_enable) 476 ndev->features &= ~NETIF_F_HW_CSUM; 477 478 if (rx_enable) 479 ndev->features &= ~NETIF_F_RXCSUM; 480 } else { 481 if (tx_enable) 482 ravb_write(ndev, CSR1_TIP4 | CSR1_TTCP4 | CSR1_TUDP4, CSR1); 483 484 if (rx_enable) 485 ravb_write(ndev, CSR2_RIP4 | CSR2_RTCP4 | CSR2_RUDP4 | CSR2_RICMP4, 486 CSR2); 487 } 488 489 done: 490 ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0); 491 } 492 493 static void ravb_emac_init_gbeth(struct net_device *ndev) 494 { 495 struct ravb_private *priv = netdev_priv(ndev); 496 497 if (priv->phy_interface == PHY_INTERFACE_MODE_MII) { 498 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35); 499 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0); 500 } else { 501 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_RGMII, CXR35); 502 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 503 CXR31_SEL_LINK0); 504 } 505 506 /* Receive frame limit set register */ 507 ravb_write(ndev, priv->info->rx_max_frame_size + ETH_FCS_LEN, RFLR); 508 509 /* EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through */ 510 ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) | 511 ECMR_TE | ECMR_RE | ECMR_RCPT | 512 ECMR_TXF | ECMR_RXF, ECMR); 513 514 ravb_set_rate_gbeth(ndev); 515 516 /* Set MAC address */ 517 ravb_write(ndev, 518 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 519 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 520 ravb_write(ndev, (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 521 522 /* E-MAC status register clear */ 523 ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR); 524 525 ravb_csum_init_gbeth(ndev); 526 527 /* E-MAC interrupt enable register */ 528 ravb_write(ndev, ECSIPR_ICDIP, ECSIPR); 529 } 530 531 static void ravb_emac_init_rcar(struct net_device *ndev) 532 { 533 /* Receive frame limit set register */ 534 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 535 536 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 537 ravb_write(ndev, ECMR_ZPF | ECMR_DM | 538 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 539 ECMR_TE | ECMR_RE, ECMR); 540 541 ravb_set_rate_rcar(ndev); 542 543 /* Set MAC address */ 544 ravb_write(ndev, 545 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 546 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 547 ravb_write(ndev, 548 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 549 550 /* E-MAC status register clear */ 551 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 552 553 /* E-MAC interrupt enable register */ 554 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 555 } 556 557 /* E-MAC init function */ 558 static void ravb_emac_init(struct net_device *ndev) 559 { 560 struct ravb_private *priv = netdev_priv(ndev); 561 const struct ravb_hw_info *info = priv->info; 562 563 info->emac_init(ndev); 564 } 565 566 static int ravb_dmac_init_gbeth(struct net_device *ndev) 567 { 568 struct ravb_private *priv = netdev_priv(ndev); 569 int error; 570 571 error = ravb_ring_init(ndev, RAVB_BE); 572 if (error) 573 return error; 574 575 /* Descriptor format */ 576 ravb_ring_format(ndev, RAVB_BE); 577 578 /* Set DMAC RX */ 579 ravb_write(ndev, 0x60000000, RCR); 580 581 /* Set Max Frame Length (RTC) */ 582 ravb_write(ndev, 0x7ffc0000 | priv->info->rx_max_frame_size, RTC); 583 584 /* Set FIFO size */ 585 ravb_write(ndev, 0x00222200, TGC); 586 587 ravb_write(ndev, 0, TCCR); 588 589 /* Frame receive */ 590 ravb_write(ndev, RIC0_FRE0, RIC0); 591 /* Disable FIFO full warning */ 592 ravb_write(ndev, 0x0, RIC1); 593 /* Receive FIFO full error, descriptor empty */ 594 ravb_write(ndev, RIC2_QFE0 | RIC2_RFFE, RIC2); 595 596 ravb_write(ndev, TIC_FTE0, TIC); 597 598 return 0; 599 } 600 601 static int ravb_dmac_init_rcar(struct net_device *ndev) 602 { 603 struct ravb_private *priv = netdev_priv(ndev); 604 const struct ravb_hw_info *info = priv->info; 605 int error; 606 607 error = ravb_ring_init(ndev, RAVB_BE); 608 if (error) 609 return error; 610 error = ravb_ring_init(ndev, RAVB_NC); 611 if (error) { 612 ravb_ring_free(ndev, RAVB_BE); 613 return error; 614 } 615 616 /* Descriptor format */ 617 ravb_ring_format(ndev, RAVB_BE); 618 ravb_ring_format(ndev, RAVB_NC); 619 620 /* Set AVB RX */ 621 ravb_write(ndev, 622 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 623 624 /* Set FIFO size */ 625 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC); 626 627 /* Timestamp enable */ 628 ravb_write(ndev, TCCR_TFEN, TCCR); 629 630 /* Interrupt init: */ 631 if (info->multi_irqs) { 632 /* Clear DIL.DPLx */ 633 ravb_write(ndev, 0, DIL); 634 /* Set queue specific interrupt */ 635 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 636 } 637 /* Frame receive */ 638 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 639 /* Disable FIFO full warning */ 640 ravb_write(ndev, 0, RIC1); 641 /* Receive FIFO full error, descriptor empty */ 642 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 643 /* Frame transmitted, timestamp FIFO updated */ 644 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 645 646 return 0; 647 } 648 649 /* Device init function for Ethernet AVB */ 650 static int ravb_dmac_init(struct net_device *ndev) 651 { 652 struct ravb_private *priv = netdev_priv(ndev); 653 const struct ravb_hw_info *info = priv->info; 654 int error; 655 656 /* Set CONFIG mode */ 657 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 658 if (error) 659 return error; 660 661 error = info->dmac_init(ndev); 662 if (error) 663 return error; 664 665 /* Setting the control will start the AVB-DMAC process. */ 666 return ravb_set_opmode(ndev, CCC_OPC_OPERATION); 667 } 668 669 static void ravb_get_tx_tstamp(struct net_device *ndev) 670 { 671 struct ravb_private *priv = netdev_priv(ndev); 672 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 673 struct skb_shared_hwtstamps shhwtstamps; 674 struct sk_buff *skb; 675 struct timespec64 ts; 676 u16 tag, tfa_tag; 677 int count; 678 u32 tfa2; 679 680 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 681 while (count--) { 682 tfa2 = ravb_read(ndev, TFA2); 683 tfa_tag = (tfa2 & TFA2_TST) >> 16; 684 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 685 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 686 ravb_read(ndev, TFA1); 687 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 688 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 689 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 690 list) { 691 skb = ts_skb->skb; 692 tag = ts_skb->tag; 693 list_del(&ts_skb->list); 694 kfree(ts_skb); 695 if (tag == tfa_tag) { 696 skb_tstamp_tx(skb, &shhwtstamps); 697 dev_consume_skb_any(skb); 698 break; 699 } else { 700 dev_kfree_skb_any(skb); 701 } 702 } 703 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 704 } 705 } 706 707 static void ravb_rx_csum_gbeth(struct sk_buff *skb) 708 { 709 __wsum csum_ip_hdr, csum_proto; 710 u8 *hw_csum; 711 712 /* The hardware checksum status is contained in sizeof(__sum16) * 2 = 4 713 * bytes appended to packet data. First 2 bytes is ip header checksum 714 * and last 2 bytes is protocol checksum. 715 */ 716 if (unlikely(skb->len < sizeof(__sum16) * 2)) 717 return; 718 719 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); 720 csum_proto = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 721 722 hw_csum -= sizeof(__sum16); 723 csum_ip_hdr = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 724 skb_trim(skb, skb->len - 2 * sizeof(__sum16)); 725 726 /* TODO: IPV6 Rx checksum */ 727 if (skb->protocol == htons(ETH_P_IP) && !csum_ip_hdr && !csum_proto) 728 skb->ip_summed = CHECKSUM_UNNECESSARY; 729 } 730 731 static void ravb_rx_csum(struct sk_buff *skb) 732 { 733 u8 *hw_csum; 734 735 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes 736 * appended to packet data 737 */ 738 if (unlikely(skb->len < sizeof(__sum16))) 739 return; 740 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); 741 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 742 skb->ip_summed = CHECKSUM_COMPLETE; 743 skb_trim(skb, skb->len - sizeof(__sum16)); 744 } 745 746 static struct sk_buff *ravb_get_skb_gbeth(struct net_device *ndev, int entry, 747 struct ravb_rx_desc *desc) 748 { 749 struct ravb_private *priv = netdev_priv(ndev); 750 struct sk_buff *skb; 751 752 skb = priv->rx_skb[RAVB_BE][entry]; 753 priv->rx_skb[RAVB_BE][entry] = NULL; 754 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 755 ALIGN(priv->info->rx_max_frame_size, 16), 756 DMA_FROM_DEVICE); 757 758 return skb; 759 } 760 761 /* Packet receive function for Gigabit Ethernet */ 762 static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q) 763 { 764 struct ravb_private *priv = netdev_priv(ndev); 765 const struct ravb_hw_info *info = priv->info; 766 struct net_device_stats *stats; 767 struct ravb_rx_desc *desc; 768 struct sk_buff *skb; 769 dma_addr_t dma_addr; 770 int rx_packets = 0; 771 u8 desc_status; 772 u16 pkt_len; 773 u8 die_dt; 774 int entry; 775 int limit; 776 int i; 777 778 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 779 limit = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q]; 780 stats = &priv->stats[q]; 781 782 desc = &priv->rx_ring[q].desc[entry]; 783 for (i = 0; i < limit && rx_packets < *quota && desc->die_dt != DT_FEMPTY; i++) { 784 /* Descriptor type must be checked before all other reads */ 785 dma_rmb(); 786 desc_status = desc->msc; 787 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 788 789 /* We use 0-byte descriptors to mark the DMA mapping errors */ 790 if (!pkt_len) 791 continue; 792 793 if (desc_status & MSC_MC) 794 stats->multicast++; 795 796 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | MSC_CEEF)) { 797 stats->rx_errors++; 798 if (desc_status & MSC_CRC) 799 stats->rx_crc_errors++; 800 if (desc_status & MSC_RFE) 801 stats->rx_frame_errors++; 802 if (desc_status & (MSC_RTLF | MSC_RTSF)) 803 stats->rx_length_errors++; 804 if (desc_status & MSC_CEEF) 805 stats->rx_missed_errors++; 806 } else { 807 die_dt = desc->die_dt & 0xF0; 808 switch (die_dt) { 809 case DT_FSINGLE: 810 skb = ravb_get_skb_gbeth(ndev, entry, desc); 811 skb_put(skb, pkt_len); 812 skb->protocol = eth_type_trans(skb, ndev); 813 if (ndev->features & NETIF_F_RXCSUM) 814 ravb_rx_csum_gbeth(skb); 815 napi_gro_receive(&priv->napi[q], skb); 816 rx_packets++; 817 stats->rx_bytes += pkt_len; 818 break; 819 case DT_FSTART: 820 priv->rx_1st_skb = ravb_get_skb_gbeth(ndev, entry, desc); 821 skb_put(priv->rx_1st_skb, pkt_len); 822 break; 823 case DT_FMID: 824 skb = ravb_get_skb_gbeth(ndev, entry, desc); 825 skb_copy_to_linear_data_offset(priv->rx_1st_skb, 826 priv->rx_1st_skb->len, 827 skb->data, 828 pkt_len); 829 skb_put(priv->rx_1st_skb, pkt_len); 830 dev_kfree_skb(skb); 831 break; 832 case DT_FEND: 833 skb = ravb_get_skb_gbeth(ndev, entry, desc); 834 skb_copy_to_linear_data_offset(priv->rx_1st_skb, 835 priv->rx_1st_skb->len, 836 skb->data, 837 pkt_len); 838 skb_put(priv->rx_1st_skb, pkt_len); 839 dev_kfree_skb(skb); 840 priv->rx_1st_skb->protocol = 841 eth_type_trans(priv->rx_1st_skb, ndev); 842 if (ndev->features & NETIF_F_RXCSUM) 843 ravb_rx_csum_gbeth(skb); 844 napi_gro_receive(&priv->napi[q], 845 priv->rx_1st_skb); 846 rx_packets++; 847 stats->rx_bytes += pkt_len; 848 break; 849 } 850 } 851 852 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 853 desc = &priv->rx_ring[q].desc[entry]; 854 } 855 856 /* Refill the RX ring buffers. */ 857 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 858 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 859 desc = &priv->rx_ring[q].desc[entry]; 860 desc->ds_cc = cpu_to_le16(priv->info->rx_max_desc_use); 861 862 if (!priv->rx_skb[q][entry]) { 863 skb = ravb_alloc_skb(ndev, info, GFP_ATOMIC); 864 if (!skb) 865 break; 866 dma_addr = dma_map_single(ndev->dev.parent, 867 skb->data, 868 priv->info->rx_max_frame_size, 869 DMA_FROM_DEVICE); 870 skb_checksum_none_assert(skb); 871 /* We just set the data size to 0 for a failed mapping 872 * which should prevent DMA from happening... 873 */ 874 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 875 desc->ds_cc = cpu_to_le16(0); 876 desc->dptr = cpu_to_le32(dma_addr); 877 priv->rx_skb[q][entry] = skb; 878 } 879 /* Descriptor type must be set after all the above writes */ 880 dma_wmb(); 881 desc->die_dt = DT_FEMPTY; 882 } 883 884 stats->rx_packets += rx_packets; 885 *quota -= rx_packets; 886 return *quota == 0; 887 } 888 889 /* Packet receive function for Ethernet AVB */ 890 static bool ravb_rx_rcar(struct net_device *ndev, int *quota, int q) 891 { 892 struct ravb_private *priv = netdev_priv(ndev); 893 const struct ravb_hw_info *info = priv->info; 894 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 895 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 896 priv->cur_rx[q]; 897 struct net_device_stats *stats = &priv->stats[q]; 898 struct ravb_ex_rx_desc *desc; 899 struct sk_buff *skb; 900 dma_addr_t dma_addr; 901 struct timespec64 ts; 902 u8 desc_status; 903 u16 pkt_len; 904 int limit; 905 906 boguscnt = min(boguscnt, *quota); 907 limit = boguscnt; 908 desc = &priv->rx_ring[q].ex_desc[entry]; 909 while (desc->die_dt != DT_FEMPTY) { 910 /* Descriptor type must be checked before all other reads */ 911 dma_rmb(); 912 desc_status = desc->msc; 913 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 914 915 if (--boguscnt < 0) 916 break; 917 918 /* We use 0-byte descriptors to mark the DMA mapping errors */ 919 if (!pkt_len) 920 continue; 921 922 if (desc_status & MSC_MC) 923 stats->multicast++; 924 925 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 926 MSC_CEEF)) { 927 stats->rx_errors++; 928 if (desc_status & MSC_CRC) 929 stats->rx_crc_errors++; 930 if (desc_status & MSC_RFE) 931 stats->rx_frame_errors++; 932 if (desc_status & (MSC_RTLF | MSC_RTSF)) 933 stats->rx_length_errors++; 934 if (desc_status & MSC_CEEF) 935 stats->rx_missed_errors++; 936 } else { 937 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 938 939 skb = priv->rx_skb[q][entry]; 940 priv->rx_skb[q][entry] = NULL; 941 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 942 priv->info->rx_max_frame_size, 943 DMA_FROM_DEVICE); 944 get_ts &= (q == RAVB_NC) ? 945 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 946 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 947 if (get_ts) { 948 struct skb_shared_hwtstamps *shhwtstamps; 949 950 shhwtstamps = skb_hwtstamps(skb); 951 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 952 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 953 32) | le32_to_cpu(desc->ts_sl); 954 ts.tv_nsec = le32_to_cpu(desc->ts_n); 955 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 956 } 957 958 skb_put(skb, pkt_len); 959 skb->protocol = eth_type_trans(skb, ndev); 960 if (ndev->features & NETIF_F_RXCSUM) 961 ravb_rx_csum(skb); 962 napi_gro_receive(&priv->napi[q], skb); 963 stats->rx_packets++; 964 stats->rx_bytes += pkt_len; 965 } 966 967 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 968 desc = &priv->rx_ring[q].ex_desc[entry]; 969 } 970 971 /* Refill the RX ring buffers. */ 972 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 973 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 974 desc = &priv->rx_ring[q].ex_desc[entry]; 975 desc->ds_cc = cpu_to_le16(priv->info->rx_max_desc_use); 976 977 if (!priv->rx_skb[q][entry]) { 978 skb = ravb_alloc_skb(ndev, info, GFP_ATOMIC); 979 if (!skb) 980 break; /* Better luck next round. */ 981 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 982 priv->info->rx_max_frame_size, 983 DMA_FROM_DEVICE); 984 skb_checksum_none_assert(skb); 985 /* We just set the data size to 0 for a failed mapping 986 * which should prevent DMA from happening... 987 */ 988 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 989 desc->ds_cc = cpu_to_le16(0); 990 desc->dptr = cpu_to_le32(dma_addr); 991 priv->rx_skb[q][entry] = skb; 992 } 993 /* Descriptor type must be set after all the above writes */ 994 dma_wmb(); 995 desc->die_dt = DT_FEMPTY; 996 } 997 998 *quota -= limit - (++boguscnt); 999 1000 return boguscnt <= 0; 1001 } 1002 1003 /* Packet receive function for Ethernet AVB */ 1004 static bool ravb_rx(struct net_device *ndev, int *quota, int q) 1005 { 1006 struct ravb_private *priv = netdev_priv(ndev); 1007 const struct ravb_hw_info *info = priv->info; 1008 1009 return info->receive(ndev, quota, q); 1010 } 1011 1012 static void ravb_rcv_snd_disable(struct net_device *ndev) 1013 { 1014 /* Disable TX and RX */ 1015 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 1016 } 1017 1018 static void ravb_rcv_snd_enable(struct net_device *ndev) 1019 { 1020 /* Enable TX and RX */ 1021 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 1022 } 1023 1024 /* function for waiting dma process finished */ 1025 static int ravb_stop_dma(struct net_device *ndev) 1026 { 1027 struct ravb_private *priv = netdev_priv(ndev); 1028 const struct ravb_hw_info *info = priv->info; 1029 int error; 1030 1031 /* Wait for stopping the hardware TX process */ 1032 error = ravb_wait(ndev, TCCR, info->tccr_mask, 0); 1033 1034 if (error) 1035 return error; 1036 1037 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 1038 0); 1039 if (error) 1040 return error; 1041 1042 /* Stop the E-MAC's RX/TX processes. */ 1043 ravb_rcv_snd_disable(ndev); 1044 1045 /* Wait for stopping the RX DMA process */ 1046 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 1047 if (error) 1048 return error; 1049 1050 /* Stop AVB-DMAC process */ 1051 return ravb_set_opmode(ndev, CCC_OPC_CONFIG); 1052 } 1053 1054 /* E-MAC interrupt handler */ 1055 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 1056 { 1057 struct ravb_private *priv = netdev_priv(ndev); 1058 u32 ecsr, psr; 1059 1060 ecsr = ravb_read(ndev, ECSR); 1061 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 1062 1063 if (ecsr & ECSR_MPD) 1064 pm_wakeup_event(&priv->pdev->dev, 0); 1065 if (ecsr & ECSR_ICD) 1066 ndev->stats.tx_carrier_errors++; 1067 if (ecsr & ECSR_LCHNG) { 1068 /* Link changed */ 1069 if (priv->no_avb_link) 1070 return; 1071 psr = ravb_read(ndev, PSR); 1072 if (priv->avb_link_active_low) 1073 psr ^= PSR_LMON; 1074 if (!(psr & PSR_LMON)) { 1075 /* DIsable RX and TX */ 1076 ravb_rcv_snd_disable(ndev); 1077 } else { 1078 /* Enable RX and TX */ 1079 ravb_rcv_snd_enable(ndev); 1080 } 1081 } 1082 } 1083 1084 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 1085 { 1086 struct net_device *ndev = dev_id; 1087 struct ravb_private *priv = netdev_priv(ndev); 1088 struct device *dev = &priv->pdev->dev; 1089 irqreturn_t result = IRQ_HANDLED; 1090 1091 pm_runtime_get_noresume(dev); 1092 1093 if (unlikely(!pm_runtime_active(dev))) { 1094 result = IRQ_NONE; 1095 goto out_rpm_put; 1096 } 1097 1098 spin_lock(&priv->lock); 1099 ravb_emac_interrupt_unlocked(ndev); 1100 spin_unlock(&priv->lock); 1101 1102 out_rpm_put: 1103 pm_runtime_put_noidle(dev); 1104 return result; 1105 } 1106 1107 /* Error interrupt handler */ 1108 static void ravb_error_interrupt(struct net_device *ndev) 1109 { 1110 struct ravb_private *priv = netdev_priv(ndev); 1111 u32 eis, ris2; 1112 1113 eis = ravb_read(ndev, EIS); 1114 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS); 1115 if (eis & EIS_QFS) { 1116 ris2 = ravb_read(ndev, RIS2); 1117 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_QFF1 | RIS2_RFFF | RIS2_RESERVED), 1118 RIS2); 1119 1120 /* Receive Descriptor Empty int */ 1121 if (ris2 & RIS2_QFF0) 1122 priv->stats[RAVB_BE].rx_over_errors++; 1123 1124 /* Receive Descriptor Empty int */ 1125 if (ris2 & RIS2_QFF1) 1126 priv->stats[RAVB_NC].rx_over_errors++; 1127 1128 /* Receive FIFO Overflow int */ 1129 if (ris2 & RIS2_RFFF) 1130 priv->rx_fifo_errors++; 1131 } 1132 } 1133 1134 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 1135 { 1136 struct ravb_private *priv = netdev_priv(ndev); 1137 const struct ravb_hw_info *info = priv->info; 1138 u32 ris0 = ravb_read(ndev, RIS0); 1139 u32 ric0 = ravb_read(ndev, RIC0); 1140 u32 tis = ravb_read(ndev, TIS); 1141 u32 tic = ravb_read(ndev, TIC); 1142 1143 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 1144 if (napi_schedule_prep(&priv->napi[q])) { 1145 /* Mask RX and TX interrupts */ 1146 if (!info->irq_en_dis) { 1147 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 1148 ravb_write(ndev, tic & ~BIT(q), TIC); 1149 } else { 1150 ravb_write(ndev, BIT(q), RID0); 1151 ravb_write(ndev, BIT(q), TID); 1152 } 1153 __napi_schedule(&priv->napi[q]); 1154 } else { 1155 netdev_warn(ndev, 1156 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 1157 ris0, ric0); 1158 netdev_warn(ndev, 1159 " tx status 0x%08x, tx mask 0x%08x.\n", 1160 tis, tic); 1161 } 1162 return true; 1163 } 1164 return false; 1165 } 1166 1167 static bool ravb_timestamp_interrupt(struct net_device *ndev) 1168 { 1169 u32 tis = ravb_read(ndev, TIS); 1170 1171 if (tis & TIS_TFUF) { 1172 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS); 1173 ravb_get_tx_tstamp(ndev); 1174 return true; 1175 } 1176 return false; 1177 } 1178 1179 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 1180 { 1181 struct net_device *ndev = dev_id; 1182 struct ravb_private *priv = netdev_priv(ndev); 1183 const struct ravb_hw_info *info = priv->info; 1184 struct device *dev = &priv->pdev->dev; 1185 irqreturn_t result = IRQ_NONE; 1186 u32 iss; 1187 1188 pm_runtime_get_noresume(dev); 1189 1190 if (unlikely(!pm_runtime_active(dev))) 1191 goto out_rpm_put; 1192 1193 spin_lock(&priv->lock); 1194 /* Get interrupt status */ 1195 iss = ravb_read(ndev, ISS); 1196 1197 /* Received and transmitted interrupts */ 1198 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 1199 int q; 1200 1201 /* Timestamp updated */ 1202 if (ravb_timestamp_interrupt(ndev)) 1203 result = IRQ_HANDLED; 1204 1205 /* Network control and best effort queue RX/TX */ 1206 if (info->nc_queues) { 1207 for (q = RAVB_NC; q >= RAVB_BE; q--) { 1208 if (ravb_queue_interrupt(ndev, q)) 1209 result = IRQ_HANDLED; 1210 } 1211 } else { 1212 if (ravb_queue_interrupt(ndev, RAVB_BE)) 1213 result = IRQ_HANDLED; 1214 } 1215 } 1216 1217 /* E-MAC status summary */ 1218 if (iss & ISS_MS) { 1219 ravb_emac_interrupt_unlocked(ndev); 1220 result = IRQ_HANDLED; 1221 } 1222 1223 /* Error status summary */ 1224 if (iss & ISS_ES) { 1225 ravb_error_interrupt(ndev); 1226 result = IRQ_HANDLED; 1227 } 1228 1229 /* gPTP interrupt status summary */ 1230 if (iss & ISS_CGIS) { 1231 ravb_ptp_interrupt(ndev); 1232 result = IRQ_HANDLED; 1233 } 1234 1235 spin_unlock(&priv->lock); 1236 1237 out_rpm_put: 1238 pm_runtime_put_noidle(dev); 1239 return result; 1240 } 1241 1242 /* Timestamp/Error/gPTP interrupt handler */ 1243 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 1244 { 1245 struct net_device *ndev = dev_id; 1246 struct ravb_private *priv = netdev_priv(ndev); 1247 struct device *dev = &priv->pdev->dev; 1248 irqreturn_t result = IRQ_NONE; 1249 u32 iss; 1250 1251 pm_runtime_get_noresume(dev); 1252 1253 if (unlikely(!pm_runtime_active(dev))) 1254 goto out_rpm_put; 1255 1256 spin_lock(&priv->lock); 1257 /* Get interrupt status */ 1258 iss = ravb_read(ndev, ISS); 1259 1260 /* Timestamp updated */ 1261 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 1262 result = IRQ_HANDLED; 1263 1264 /* Error status summary */ 1265 if (iss & ISS_ES) { 1266 ravb_error_interrupt(ndev); 1267 result = IRQ_HANDLED; 1268 } 1269 1270 /* gPTP interrupt status summary */ 1271 if (iss & ISS_CGIS) { 1272 ravb_ptp_interrupt(ndev); 1273 result = IRQ_HANDLED; 1274 } 1275 1276 spin_unlock(&priv->lock); 1277 1278 out_rpm_put: 1279 pm_runtime_put_noidle(dev); 1280 return result; 1281 } 1282 1283 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 1284 { 1285 struct net_device *ndev = dev_id; 1286 struct ravb_private *priv = netdev_priv(ndev); 1287 struct device *dev = &priv->pdev->dev; 1288 irqreturn_t result = IRQ_NONE; 1289 1290 pm_runtime_get_noresume(dev); 1291 1292 if (unlikely(!pm_runtime_active(dev))) 1293 goto out_rpm_put; 1294 1295 spin_lock(&priv->lock); 1296 1297 /* Network control/Best effort queue RX/TX */ 1298 if (ravb_queue_interrupt(ndev, q)) 1299 result = IRQ_HANDLED; 1300 1301 spin_unlock(&priv->lock); 1302 1303 out_rpm_put: 1304 pm_runtime_put_noidle(dev); 1305 return result; 1306 } 1307 1308 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 1309 { 1310 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 1311 } 1312 1313 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 1314 { 1315 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 1316 } 1317 1318 static int ravb_poll(struct napi_struct *napi, int budget) 1319 { 1320 struct net_device *ndev = napi->dev; 1321 struct ravb_private *priv = netdev_priv(ndev); 1322 const struct ravb_hw_info *info = priv->info; 1323 unsigned long flags; 1324 int q = napi - priv->napi; 1325 int mask = BIT(q); 1326 int quota = budget; 1327 bool unmask; 1328 1329 /* Processing RX Descriptor Ring */ 1330 /* Clear RX interrupt */ 1331 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0); 1332 unmask = !ravb_rx(ndev, "a, q); 1333 1334 /* Processing TX Descriptor Ring */ 1335 spin_lock_irqsave(&priv->lock, flags); 1336 /* Clear TX interrupt */ 1337 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS); 1338 ravb_tx_free(ndev, q, true); 1339 netif_wake_subqueue(ndev, q); 1340 spin_unlock_irqrestore(&priv->lock, flags); 1341 1342 /* Receive error message handling */ 1343 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 1344 if (info->nc_queues) 1345 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 1346 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 1347 ndev->stats.rx_over_errors = priv->rx_over_errors; 1348 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 1349 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 1350 1351 if (!unmask) 1352 goto out; 1353 1354 napi_complete(napi); 1355 1356 /* Re-enable RX/TX interrupts */ 1357 spin_lock_irqsave(&priv->lock, flags); 1358 if (!info->irq_en_dis) { 1359 ravb_modify(ndev, RIC0, mask, mask); 1360 ravb_modify(ndev, TIC, mask, mask); 1361 } else { 1362 ravb_write(ndev, mask, RIE0); 1363 ravb_write(ndev, mask, TIE); 1364 } 1365 spin_unlock_irqrestore(&priv->lock, flags); 1366 1367 out: 1368 return budget - quota; 1369 } 1370 1371 static void ravb_set_duplex_gbeth(struct net_device *ndev) 1372 { 1373 struct ravb_private *priv = netdev_priv(ndev); 1374 1375 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex > 0 ? ECMR_DM : 0); 1376 } 1377 1378 /* PHY state control function */ 1379 static void ravb_adjust_link(struct net_device *ndev) 1380 { 1381 struct ravb_private *priv = netdev_priv(ndev); 1382 const struct ravb_hw_info *info = priv->info; 1383 struct phy_device *phydev = ndev->phydev; 1384 bool new_state = false; 1385 unsigned long flags; 1386 1387 spin_lock_irqsave(&priv->lock, flags); 1388 1389 /* Disable TX and RX right over here, if E-MAC change is ignored */ 1390 if (priv->no_avb_link) 1391 ravb_rcv_snd_disable(ndev); 1392 1393 if (phydev->link) { 1394 if (info->half_duplex && phydev->duplex != priv->duplex) { 1395 new_state = true; 1396 priv->duplex = phydev->duplex; 1397 ravb_set_duplex_gbeth(ndev); 1398 } 1399 1400 if (phydev->speed != priv->speed) { 1401 new_state = true; 1402 priv->speed = phydev->speed; 1403 info->set_rate(ndev); 1404 } 1405 if (!priv->link) { 1406 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 1407 new_state = true; 1408 priv->link = phydev->link; 1409 } 1410 } else if (priv->link) { 1411 new_state = true; 1412 priv->link = 0; 1413 priv->speed = 0; 1414 if (info->half_duplex) 1415 priv->duplex = -1; 1416 } 1417 1418 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1419 if (priv->no_avb_link && phydev->link) 1420 ravb_rcv_snd_enable(ndev); 1421 1422 spin_unlock_irqrestore(&priv->lock, flags); 1423 1424 if (new_state && netif_msg_link(priv)) 1425 phy_print_status(phydev); 1426 } 1427 1428 /* PHY init function */ 1429 static int ravb_phy_init(struct net_device *ndev) 1430 { 1431 struct device_node *np = ndev->dev.parent->of_node; 1432 struct ravb_private *priv = netdev_priv(ndev); 1433 const struct ravb_hw_info *info = priv->info; 1434 struct phy_device *phydev; 1435 struct device_node *pn; 1436 phy_interface_t iface; 1437 int err; 1438 1439 priv->link = 0; 1440 priv->speed = 0; 1441 priv->duplex = -1; 1442 1443 /* Try connecting to PHY */ 1444 pn = of_parse_phandle(np, "phy-handle", 0); 1445 if (!pn) { 1446 /* In the case of a fixed PHY, the DT node associated 1447 * to the PHY is the Ethernet MAC DT node. 1448 */ 1449 if (of_phy_is_fixed_link(np)) { 1450 err = of_phy_register_fixed_link(np); 1451 if (err) 1452 return err; 1453 } 1454 pn = of_node_get(np); 1455 } 1456 1457 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII 1458 : priv->phy_interface; 1459 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface); 1460 of_node_put(pn); 1461 if (!phydev) { 1462 netdev_err(ndev, "failed to connect PHY\n"); 1463 err = -ENOENT; 1464 goto err_deregister_fixed_link; 1465 } 1466 1467 if (!info->half_duplex) { 1468 /* 10BASE, Pause and Asym Pause is not supported */ 1469 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1470 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1471 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT); 1472 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 1473 1474 /* Half Duplex is not supported */ 1475 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1476 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1477 } 1478 1479 phy_attached_info(phydev); 1480 1481 return 0; 1482 1483 err_deregister_fixed_link: 1484 if (of_phy_is_fixed_link(np)) 1485 of_phy_deregister_fixed_link(np); 1486 1487 return err; 1488 } 1489 1490 /* PHY control start function */ 1491 static int ravb_phy_start(struct net_device *ndev) 1492 { 1493 int error; 1494 1495 error = ravb_phy_init(ndev); 1496 if (error) 1497 return error; 1498 1499 phy_start(ndev->phydev); 1500 1501 return 0; 1502 } 1503 1504 static u32 ravb_get_msglevel(struct net_device *ndev) 1505 { 1506 struct ravb_private *priv = netdev_priv(ndev); 1507 1508 return priv->msg_enable; 1509 } 1510 1511 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1512 { 1513 struct ravb_private *priv = netdev_priv(ndev); 1514 1515 priv->msg_enable = value; 1516 } 1517 1518 static const char ravb_gstrings_stats_gbeth[][ETH_GSTRING_LEN] = { 1519 "rx_queue_0_current", 1520 "tx_queue_0_current", 1521 "rx_queue_0_dirty", 1522 "tx_queue_0_dirty", 1523 "rx_queue_0_packets", 1524 "tx_queue_0_packets", 1525 "rx_queue_0_bytes", 1526 "tx_queue_0_bytes", 1527 "rx_queue_0_mcast_packets", 1528 "rx_queue_0_errors", 1529 "rx_queue_0_crc_errors", 1530 "rx_queue_0_frame_errors", 1531 "rx_queue_0_length_errors", 1532 "rx_queue_0_csum_offload_errors", 1533 "rx_queue_0_over_errors", 1534 }; 1535 1536 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1537 "rx_queue_0_current", 1538 "tx_queue_0_current", 1539 "rx_queue_0_dirty", 1540 "tx_queue_0_dirty", 1541 "rx_queue_0_packets", 1542 "tx_queue_0_packets", 1543 "rx_queue_0_bytes", 1544 "tx_queue_0_bytes", 1545 "rx_queue_0_mcast_packets", 1546 "rx_queue_0_errors", 1547 "rx_queue_0_crc_errors", 1548 "rx_queue_0_frame_errors", 1549 "rx_queue_0_length_errors", 1550 "rx_queue_0_missed_errors", 1551 "rx_queue_0_over_errors", 1552 1553 "rx_queue_1_current", 1554 "tx_queue_1_current", 1555 "rx_queue_1_dirty", 1556 "tx_queue_1_dirty", 1557 "rx_queue_1_packets", 1558 "tx_queue_1_packets", 1559 "rx_queue_1_bytes", 1560 "tx_queue_1_bytes", 1561 "rx_queue_1_mcast_packets", 1562 "rx_queue_1_errors", 1563 "rx_queue_1_crc_errors", 1564 "rx_queue_1_frame_errors", 1565 "rx_queue_1_length_errors", 1566 "rx_queue_1_missed_errors", 1567 "rx_queue_1_over_errors", 1568 }; 1569 1570 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1571 { 1572 struct ravb_private *priv = netdev_priv(netdev); 1573 const struct ravb_hw_info *info = priv->info; 1574 1575 switch (sset) { 1576 case ETH_SS_STATS: 1577 return info->stats_len; 1578 default: 1579 return -EOPNOTSUPP; 1580 } 1581 } 1582 1583 static void ravb_get_ethtool_stats(struct net_device *ndev, 1584 struct ethtool_stats *estats, u64 *data) 1585 { 1586 struct ravb_private *priv = netdev_priv(ndev); 1587 const struct ravb_hw_info *info = priv->info; 1588 int num_rx_q; 1589 int i = 0; 1590 int q; 1591 1592 num_rx_q = info->nc_queues ? NUM_RX_QUEUE : 1; 1593 /* Device-specific stats */ 1594 for (q = RAVB_BE; q < num_rx_q; q++) { 1595 struct net_device_stats *stats = &priv->stats[q]; 1596 1597 data[i++] = priv->cur_rx[q]; 1598 data[i++] = priv->cur_tx[q]; 1599 data[i++] = priv->dirty_rx[q]; 1600 data[i++] = priv->dirty_tx[q]; 1601 data[i++] = stats->rx_packets; 1602 data[i++] = stats->tx_packets; 1603 data[i++] = stats->rx_bytes; 1604 data[i++] = stats->tx_bytes; 1605 data[i++] = stats->multicast; 1606 data[i++] = stats->rx_errors; 1607 data[i++] = stats->rx_crc_errors; 1608 data[i++] = stats->rx_frame_errors; 1609 data[i++] = stats->rx_length_errors; 1610 data[i++] = stats->rx_missed_errors; 1611 data[i++] = stats->rx_over_errors; 1612 } 1613 } 1614 1615 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1616 { 1617 struct ravb_private *priv = netdev_priv(ndev); 1618 const struct ravb_hw_info *info = priv->info; 1619 1620 switch (stringset) { 1621 case ETH_SS_STATS: 1622 memcpy(data, info->gstrings_stats, info->gstrings_size); 1623 break; 1624 } 1625 } 1626 1627 static void ravb_get_ringparam(struct net_device *ndev, 1628 struct ethtool_ringparam *ring, 1629 struct kernel_ethtool_ringparam *kernel_ring, 1630 struct netlink_ext_ack *extack) 1631 { 1632 struct ravb_private *priv = netdev_priv(ndev); 1633 1634 ring->rx_max_pending = BE_RX_RING_MAX; 1635 ring->tx_max_pending = BE_TX_RING_MAX; 1636 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1637 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1638 } 1639 1640 static int ravb_set_ringparam(struct net_device *ndev, 1641 struct ethtool_ringparam *ring, 1642 struct kernel_ethtool_ringparam *kernel_ring, 1643 struct netlink_ext_ack *extack) 1644 { 1645 struct ravb_private *priv = netdev_priv(ndev); 1646 const struct ravb_hw_info *info = priv->info; 1647 int error; 1648 1649 if (ring->tx_pending > BE_TX_RING_MAX || 1650 ring->rx_pending > BE_RX_RING_MAX || 1651 ring->tx_pending < BE_TX_RING_MIN || 1652 ring->rx_pending < BE_RX_RING_MIN) 1653 return -EINVAL; 1654 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1655 return -EINVAL; 1656 1657 if (netif_running(ndev)) { 1658 netif_device_detach(ndev); 1659 /* Stop PTP Clock driver */ 1660 if (info->gptp) 1661 ravb_ptp_stop(ndev); 1662 /* Wait for DMA stopping */ 1663 error = ravb_stop_dma(ndev); 1664 if (error) { 1665 netdev_err(ndev, 1666 "cannot set ringparam! Any AVB processes are still running?\n"); 1667 return error; 1668 } 1669 synchronize_irq(ndev->irq); 1670 1671 /* Free all the skb's in the RX queue and the DMA buffers. */ 1672 ravb_ring_free(ndev, RAVB_BE); 1673 if (info->nc_queues) 1674 ravb_ring_free(ndev, RAVB_NC); 1675 } 1676 1677 /* Set new parameters */ 1678 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1679 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1680 1681 if (netif_running(ndev)) { 1682 error = ravb_dmac_init(ndev); 1683 if (error) { 1684 netdev_err(ndev, 1685 "%s: ravb_dmac_init() failed, error %d\n", 1686 __func__, error); 1687 return error; 1688 } 1689 1690 ravb_emac_init(ndev); 1691 1692 /* Initialise PTP Clock driver */ 1693 if (info->gptp) 1694 ravb_ptp_init(ndev, priv->pdev); 1695 1696 netif_device_attach(ndev); 1697 } 1698 1699 return 0; 1700 } 1701 1702 static int ravb_get_ts_info(struct net_device *ndev, 1703 struct ethtool_ts_info *info) 1704 { 1705 struct ravb_private *priv = netdev_priv(ndev); 1706 const struct ravb_hw_info *hw_info = priv->info; 1707 1708 info->so_timestamping = 1709 SOF_TIMESTAMPING_TX_SOFTWARE | 1710 SOF_TIMESTAMPING_RX_SOFTWARE | 1711 SOF_TIMESTAMPING_SOFTWARE | 1712 SOF_TIMESTAMPING_TX_HARDWARE | 1713 SOF_TIMESTAMPING_RX_HARDWARE | 1714 SOF_TIMESTAMPING_RAW_HARDWARE; 1715 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1716 info->rx_filters = 1717 (1 << HWTSTAMP_FILTER_NONE) | 1718 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1719 (1 << HWTSTAMP_FILTER_ALL); 1720 if (hw_info->gptp || hw_info->ccc_gac) 1721 info->phc_index = ptp_clock_index(priv->ptp.clock); 1722 1723 return 0; 1724 } 1725 1726 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1727 { 1728 struct ravb_private *priv = netdev_priv(ndev); 1729 1730 wol->supported = WAKE_MAGIC; 1731 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1732 } 1733 1734 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1735 { 1736 struct ravb_private *priv = netdev_priv(ndev); 1737 const struct ravb_hw_info *info = priv->info; 1738 1739 if (!info->magic_pkt || (wol->wolopts & ~WAKE_MAGIC)) 1740 return -EOPNOTSUPP; 1741 1742 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1743 1744 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1745 1746 return 0; 1747 } 1748 1749 static const struct ethtool_ops ravb_ethtool_ops = { 1750 .nway_reset = phy_ethtool_nway_reset, 1751 .get_msglevel = ravb_get_msglevel, 1752 .set_msglevel = ravb_set_msglevel, 1753 .get_link = ethtool_op_get_link, 1754 .get_strings = ravb_get_strings, 1755 .get_ethtool_stats = ravb_get_ethtool_stats, 1756 .get_sset_count = ravb_get_sset_count, 1757 .get_ringparam = ravb_get_ringparam, 1758 .set_ringparam = ravb_set_ringparam, 1759 .get_ts_info = ravb_get_ts_info, 1760 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1761 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1762 .get_wol = ravb_get_wol, 1763 .set_wol = ravb_set_wol, 1764 }; 1765 1766 static int ravb_set_config_mode(struct net_device *ndev) 1767 { 1768 struct ravb_private *priv = netdev_priv(ndev); 1769 const struct ravb_hw_info *info = priv->info; 1770 int error; 1771 1772 if (info->gptp) { 1773 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 1774 if (error) 1775 return error; 1776 /* Set CSEL value */ 1777 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 1778 } else if (info->ccc_gac) { 1779 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG | CCC_GAC | CCC_CSEL_HPB); 1780 } else { 1781 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 1782 } 1783 1784 return error; 1785 } 1786 1787 static void ravb_set_gti(struct net_device *ndev) 1788 { 1789 struct ravb_private *priv = netdev_priv(ndev); 1790 const struct ravb_hw_info *info = priv->info; 1791 1792 if (!(info->gptp || info->ccc_gac)) 1793 return; 1794 1795 ravb_write(ndev, priv->gti_tiv, GTI); 1796 1797 /* Request GTI loading */ 1798 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 1799 } 1800 1801 static int ravb_compute_gti(struct net_device *ndev) 1802 { 1803 struct ravb_private *priv = netdev_priv(ndev); 1804 const struct ravb_hw_info *info = priv->info; 1805 struct device *dev = ndev->dev.parent; 1806 unsigned long rate; 1807 u64 inc; 1808 1809 if (!(info->gptp || info->ccc_gac)) 1810 return 0; 1811 1812 if (info->gptp_ref_clk) 1813 rate = clk_get_rate(priv->gptp_clk); 1814 else 1815 rate = clk_get_rate(priv->clk); 1816 if (!rate) 1817 return -EINVAL; 1818 1819 inc = div64_ul(1000000000ULL << 20, rate); 1820 1821 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 1822 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 1823 inc, GTI_TIV_MIN, GTI_TIV_MAX); 1824 return -EINVAL; 1825 } 1826 priv->gti_tiv = inc; 1827 1828 return 0; 1829 } 1830 1831 /* Set tx and rx clock internal delay modes */ 1832 static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev) 1833 { 1834 struct ravb_private *priv = netdev_priv(ndev); 1835 bool explicit_delay = false; 1836 u32 delay; 1837 1838 if (!priv->info->internal_delay) 1839 return; 1840 1841 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) { 1842 /* Valid values are 0 and 1800, according to DT bindings */ 1843 priv->rxcidm = !!delay; 1844 explicit_delay = true; 1845 } 1846 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) { 1847 /* Valid values are 0 and 2000, according to DT bindings */ 1848 priv->txcidm = !!delay; 1849 explicit_delay = true; 1850 } 1851 1852 if (explicit_delay) 1853 return; 1854 1855 /* Fall back to legacy rgmii-*id behavior */ 1856 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1857 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) { 1858 priv->rxcidm = 1; 1859 priv->rgmii_override = 1; 1860 } 1861 1862 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1863 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) { 1864 priv->txcidm = 1; 1865 priv->rgmii_override = 1; 1866 } 1867 } 1868 1869 static void ravb_set_delay_mode(struct net_device *ndev) 1870 { 1871 struct ravb_private *priv = netdev_priv(ndev); 1872 u32 set = 0; 1873 1874 if (!priv->info->internal_delay) 1875 return; 1876 1877 if (priv->rxcidm) 1878 set |= APSR_RDM; 1879 if (priv->txcidm) 1880 set |= APSR_TDM; 1881 ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set); 1882 } 1883 1884 /* Network device open function for Ethernet AVB */ 1885 static int ravb_open(struct net_device *ndev) 1886 { 1887 struct ravb_private *priv = netdev_priv(ndev); 1888 const struct ravb_hw_info *info = priv->info; 1889 struct device *dev = &priv->pdev->dev; 1890 int error; 1891 1892 napi_enable(&priv->napi[RAVB_BE]); 1893 if (info->nc_queues) 1894 napi_enable(&priv->napi[RAVB_NC]); 1895 1896 error = pm_runtime_resume_and_get(dev); 1897 if (error < 0) 1898 goto out_napi_off; 1899 1900 /* Set AVB config mode */ 1901 error = ravb_set_config_mode(ndev); 1902 if (error) 1903 goto out_rpm_put; 1904 1905 ravb_set_delay_mode(ndev); 1906 ravb_write(ndev, priv->desc_bat_dma, DBAT); 1907 1908 /* Device init */ 1909 error = ravb_dmac_init(ndev); 1910 if (error) 1911 goto out_set_reset; 1912 1913 ravb_emac_init(ndev); 1914 1915 ravb_set_gti(ndev); 1916 1917 /* Initialise PTP Clock driver */ 1918 if (info->gptp || info->ccc_gac) 1919 ravb_ptp_init(ndev, priv->pdev); 1920 1921 /* PHY control start */ 1922 error = ravb_phy_start(ndev); 1923 if (error) 1924 goto out_ptp_stop; 1925 1926 netif_tx_start_all_queues(ndev); 1927 1928 return 0; 1929 1930 out_ptp_stop: 1931 /* Stop PTP Clock driver */ 1932 if (info->gptp || info->ccc_gac) 1933 ravb_ptp_stop(ndev); 1934 ravb_stop_dma(ndev); 1935 out_set_reset: 1936 ravb_set_opmode(ndev, CCC_OPC_RESET); 1937 out_rpm_put: 1938 pm_runtime_mark_last_busy(dev); 1939 pm_runtime_put_autosuspend(dev); 1940 out_napi_off: 1941 if (info->nc_queues) 1942 napi_disable(&priv->napi[RAVB_NC]); 1943 napi_disable(&priv->napi[RAVB_BE]); 1944 return error; 1945 } 1946 1947 /* Timeout function for Ethernet AVB */ 1948 static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1949 { 1950 struct ravb_private *priv = netdev_priv(ndev); 1951 1952 netif_err(priv, tx_err, ndev, 1953 "transmit timed out, status %08x, resetting...\n", 1954 ravb_read(ndev, ISS)); 1955 1956 /* tx_errors count up */ 1957 ndev->stats.tx_errors++; 1958 1959 schedule_work(&priv->work); 1960 } 1961 1962 static void ravb_tx_timeout_work(struct work_struct *work) 1963 { 1964 struct ravb_private *priv = container_of(work, struct ravb_private, 1965 work); 1966 const struct ravb_hw_info *info = priv->info; 1967 struct net_device *ndev = priv->ndev; 1968 int error; 1969 1970 if (!rtnl_trylock()) { 1971 usleep_range(1000, 2000); 1972 schedule_work(&priv->work); 1973 return; 1974 } 1975 1976 netif_tx_stop_all_queues(ndev); 1977 1978 /* Stop PTP Clock driver */ 1979 if (info->gptp) 1980 ravb_ptp_stop(ndev); 1981 1982 /* Wait for DMA stopping */ 1983 if (ravb_stop_dma(ndev)) { 1984 /* If ravb_stop_dma() fails, the hardware is still operating 1985 * for TX and/or RX. So, this should not call the following 1986 * functions because ravb_dmac_init() is possible to fail too. 1987 * Also, this should not retry ravb_stop_dma() again and again 1988 * here because it's possible to wait forever. So, this just 1989 * re-enables the TX and RX and skip the following 1990 * re-initialization procedure. 1991 */ 1992 ravb_rcv_snd_enable(ndev); 1993 goto out; 1994 } 1995 1996 ravb_ring_free(ndev, RAVB_BE); 1997 if (info->nc_queues) 1998 ravb_ring_free(ndev, RAVB_NC); 1999 2000 /* Device init */ 2001 error = ravb_dmac_init(ndev); 2002 if (error) { 2003 /* If ravb_dmac_init() fails, descriptors are freed. So, this 2004 * should return here to avoid re-enabling the TX and RX in 2005 * ravb_emac_init(). 2006 */ 2007 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n", 2008 __func__, error); 2009 goto out_unlock; 2010 } 2011 ravb_emac_init(ndev); 2012 2013 out: 2014 /* Initialise PTP Clock driver */ 2015 if (info->gptp) 2016 ravb_ptp_init(ndev, priv->pdev); 2017 2018 netif_tx_start_all_queues(ndev); 2019 2020 out_unlock: 2021 rtnl_unlock(); 2022 } 2023 2024 static bool ravb_can_tx_csum_gbeth(struct sk_buff *skb) 2025 { 2026 struct iphdr *ip = ip_hdr(skb); 2027 2028 /* TODO: Need to add support for VLAN tag 802.1Q */ 2029 if (skb_vlan_tag_present(skb)) 2030 return false; 2031 2032 /* TODO: Need to add hardware checksum for IPv6 */ 2033 if (skb->protocol != htons(ETH_P_IP)) 2034 return false; 2035 2036 switch (ip->protocol) { 2037 case IPPROTO_TCP: 2038 break; 2039 case IPPROTO_UDP: 2040 /* If the checksum value in the UDP header field is 0, TOE does 2041 * not calculate checksum for UDP part of this frame as it is 2042 * optional function as per standards. 2043 */ 2044 if (udp_hdr(skb)->check == 0) 2045 return false; 2046 break; 2047 default: 2048 return false; 2049 } 2050 2051 return true; 2052 } 2053 2054 /* Packet transmit function for Ethernet AVB */ 2055 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 2056 { 2057 struct ravb_private *priv = netdev_priv(ndev); 2058 const struct ravb_hw_info *info = priv->info; 2059 unsigned int num_tx_desc = priv->num_tx_desc; 2060 u16 q = skb_get_queue_mapping(skb); 2061 struct ravb_tstamp_skb *ts_skb; 2062 struct ravb_tx_desc *desc; 2063 unsigned long flags; 2064 dma_addr_t dma_addr; 2065 void *buffer; 2066 u32 entry; 2067 u32 len; 2068 2069 if (skb->ip_summed == CHECKSUM_PARTIAL && !ravb_can_tx_csum_gbeth(skb)) 2070 skb_checksum_help(skb); 2071 2072 spin_lock_irqsave(&priv->lock, flags); 2073 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 2074 num_tx_desc) { 2075 netif_err(priv, tx_queued, ndev, 2076 "still transmitting with the full ring!\n"); 2077 netif_stop_subqueue(ndev, q); 2078 spin_unlock_irqrestore(&priv->lock, flags); 2079 return NETDEV_TX_BUSY; 2080 } 2081 2082 if (skb_put_padto(skb, ETH_ZLEN)) 2083 goto exit; 2084 2085 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc); 2086 priv->tx_skb[q][entry / num_tx_desc] = skb; 2087 2088 if (num_tx_desc > 1) { 2089 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 2090 entry / num_tx_desc * DPTR_ALIGN; 2091 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 2092 2093 /* Zero length DMA descriptors are problematic as they seem 2094 * to terminate DMA transfers. Avoid them by simply using a 2095 * length of DPTR_ALIGN (4) when skb data is aligned to 2096 * DPTR_ALIGN. 2097 * 2098 * As skb is guaranteed to have at least ETH_ZLEN (60) 2099 * bytes of data by the call to skb_put_padto() above this 2100 * is safe with respect to both the length of the first DMA 2101 * descriptor (len) overflowing the available data and the 2102 * length of the second DMA descriptor (skb->len - len) 2103 * being negative. 2104 */ 2105 if (len == 0) 2106 len = DPTR_ALIGN; 2107 2108 memcpy(buffer, skb->data, len); 2109 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 2110 DMA_TO_DEVICE); 2111 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2112 goto drop; 2113 2114 desc = &priv->tx_ring[q][entry]; 2115 desc->ds_tagl = cpu_to_le16(len); 2116 desc->dptr = cpu_to_le32(dma_addr); 2117 2118 buffer = skb->data + len; 2119 len = skb->len - len; 2120 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 2121 DMA_TO_DEVICE); 2122 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2123 goto unmap; 2124 2125 desc++; 2126 } else { 2127 desc = &priv->tx_ring[q][entry]; 2128 len = skb->len; 2129 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, 2130 DMA_TO_DEVICE); 2131 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2132 goto drop; 2133 } 2134 desc->ds_tagl = cpu_to_le16(len); 2135 desc->dptr = cpu_to_le32(dma_addr); 2136 2137 /* TX timestamp required */ 2138 if (info->gptp || info->ccc_gac) { 2139 if (q == RAVB_NC) { 2140 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 2141 if (!ts_skb) { 2142 if (num_tx_desc > 1) { 2143 desc--; 2144 dma_unmap_single(ndev->dev.parent, dma_addr, 2145 len, DMA_TO_DEVICE); 2146 } 2147 goto unmap; 2148 } 2149 ts_skb->skb = skb_get(skb); 2150 ts_skb->tag = priv->ts_skb_tag++; 2151 priv->ts_skb_tag &= 0x3ff; 2152 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 2153 2154 /* TAG and timestamp required flag */ 2155 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2156 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 2157 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12); 2158 } 2159 2160 skb_tx_timestamp(skb); 2161 } 2162 /* Descriptor type must be set after all the above writes */ 2163 dma_wmb(); 2164 if (num_tx_desc > 1) { 2165 desc->die_dt = DT_FEND; 2166 desc--; 2167 desc->die_dt = DT_FSTART; 2168 } else { 2169 desc->die_dt = DT_FSINGLE; 2170 } 2171 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 2172 2173 priv->cur_tx[q] += num_tx_desc; 2174 if (priv->cur_tx[q] - priv->dirty_tx[q] > 2175 (priv->num_tx_ring[q] - 1) * num_tx_desc && 2176 !ravb_tx_free(ndev, q, true)) 2177 netif_stop_subqueue(ndev, q); 2178 2179 exit: 2180 spin_unlock_irqrestore(&priv->lock, flags); 2181 return NETDEV_TX_OK; 2182 2183 unmap: 2184 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 2185 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 2186 drop: 2187 dev_kfree_skb_any(skb); 2188 priv->tx_skb[q][entry / num_tx_desc] = NULL; 2189 goto exit; 2190 } 2191 2192 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 2193 struct net_device *sb_dev) 2194 { 2195 /* If skb needs TX timestamp, it is handled in network control queue */ 2196 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 2197 RAVB_BE; 2198 2199 } 2200 2201 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 2202 { 2203 struct ravb_private *priv = netdev_priv(ndev); 2204 const struct ravb_hw_info *info = priv->info; 2205 struct net_device_stats *nstats, *stats0, *stats1; 2206 struct device *dev = &priv->pdev->dev; 2207 2208 nstats = &ndev->stats; 2209 2210 pm_runtime_get_noresume(dev); 2211 2212 if (!pm_runtime_active(dev)) 2213 goto out_rpm_put; 2214 2215 stats0 = &priv->stats[RAVB_BE]; 2216 2217 if (info->tx_counters) { 2218 nstats->tx_dropped += ravb_read(ndev, TROCR); 2219 ravb_write(ndev, 0, TROCR); /* (write clear) */ 2220 } 2221 2222 if (info->carrier_counters) { 2223 nstats->collisions += ravb_read(ndev, CXR41); 2224 ravb_write(ndev, 0, CXR41); /* (write clear) */ 2225 nstats->tx_carrier_errors += ravb_read(ndev, CXR42); 2226 ravb_write(ndev, 0, CXR42); /* (write clear) */ 2227 } 2228 2229 nstats->rx_packets = stats0->rx_packets; 2230 nstats->tx_packets = stats0->tx_packets; 2231 nstats->rx_bytes = stats0->rx_bytes; 2232 nstats->tx_bytes = stats0->tx_bytes; 2233 nstats->multicast = stats0->multicast; 2234 nstats->rx_errors = stats0->rx_errors; 2235 nstats->rx_crc_errors = stats0->rx_crc_errors; 2236 nstats->rx_frame_errors = stats0->rx_frame_errors; 2237 nstats->rx_length_errors = stats0->rx_length_errors; 2238 nstats->rx_missed_errors = stats0->rx_missed_errors; 2239 nstats->rx_over_errors = stats0->rx_over_errors; 2240 if (info->nc_queues) { 2241 stats1 = &priv->stats[RAVB_NC]; 2242 2243 nstats->rx_packets += stats1->rx_packets; 2244 nstats->tx_packets += stats1->tx_packets; 2245 nstats->rx_bytes += stats1->rx_bytes; 2246 nstats->tx_bytes += stats1->tx_bytes; 2247 nstats->multicast += stats1->multicast; 2248 nstats->rx_errors += stats1->rx_errors; 2249 nstats->rx_crc_errors += stats1->rx_crc_errors; 2250 nstats->rx_frame_errors += stats1->rx_frame_errors; 2251 nstats->rx_length_errors += stats1->rx_length_errors; 2252 nstats->rx_missed_errors += stats1->rx_missed_errors; 2253 nstats->rx_over_errors += stats1->rx_over_errors; 2254 } 2255 2256 out_rpm_put: 2257 pm_runtime_put_noidle(dev); 2258 return nstats; 2259 } 2260 2261 /* Update promiscuous bit */ 2262 static void ravb_set_rx_mode(struct net_device *ndev) 2263 { 2264 struct ravb_private *priv = netdev_priv(ndev); 2265 unsigned long flags; 2266 2267 spin_lock_irqsave(&priv->lock, flags); 2268 ravb_modify(ndev, ECMR, ECMR_PRM, 2269 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 2270 spin_unlock_irqrestore(&priv->lock, flags); 2271 } 2272 2273 /* Device close function for Ethernet AVB */ 2274 static int ravb_close(struct net_device *ndev) 2275 { 2276 struct device_node *np = ndev->dev.parent->of_node; 2277 struct ravb_private *priv = netdev_priv(ndev); 2278 const struct ravb_hw_info *info = priv->info; 2279 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 2280 struct device *dev = &priv->pdev->dev; 2281 int error; 2282 2283 netif_tx_stop_all_queues(ndev); 2284 2285 /* Disable interrupts by clearing the interrupt masks. */ 2286 ravb_write(ndev, 0, RIC0); 2287 ravb_write(ndev, 0, RIC2); 2288 ravb_write(ndev, 0, TIC); 2289 2290 /* PHY disconnect */ 2291 if (ndev->phydev) { 2292 phy_stop(ndev->phydev); 2293 phy_disconnect(ndev->phydev); 2294 if (of_phy_is_fixed_link(np)) 2295 of_phy_deregister_fixed_link(np); 2296 } 2297 2298 /* Stop PTP Clock driver */ 2299 if (info->gptp || info->ccc_gac) 2300 ravb_ptp_stop(ndev); 2301 2302 /* Set the config mode to stop the AVB-DMAC's processes */ 2303 if (ravb_stop_dma(ndev) < 0) 2304 netdev_err(ndev, 2305 "device will be stopped after h/w processes are done.\n"); 2306 2307 /* Clear the timestamp list */ 2308 if (info->gptp || info->ccc_gac) { 2309 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 2310 list_del(&ts_skb->list); 2311 kfree_skb(ts_skb->skb); 2312 kfree(ts_skb); 2313 } 2314 } 2315 2316 cancel_work_sync(&priv->work); 2317 2318 if (info->nc_queues) 2319 napi_disable(&priv->napi[RAVB_NC]); 2320 napi_disable(&priv->napi[RAVB_BE]); 2321 2322 /* Free all the skb's in the RX queue and the DMA buffers. */ 2323 ravb_ring_free(ndev, RAVB_BE); 2324 if (info->nc_queues) 2325 ravb_ring_free(ndev, RAVB_NC); 2326 2327 /* Update statistics. */ 2328 ravb_get_stats(ndev); 2329 2330 /* Set reset mode. */ 2331 error = ravb_set_opmode(ndev, CCC_OPC_RESET); 2332 if (error) 2333 return error; 2334 2335 pm_runtime_mark_last_busy(dev); 2336 pm_runtime_put_autosuspend(dev); 2337 2338 return 0; 2339 } 2340 2341 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 2342 { 2343 struct ravb_private *priv = netdev_priv(ndev); 2344 struct hwtstamp_config config; 2345 2346 config.flags = 0; 2347 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 2348 HWTSTAMP_TX_OFF; 2349 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) { 2350 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT: 2351 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 2352 break; 2353 case RAVB_RXTSTAMP_TYPE_ALL: 2354 config.rx_filter = HWTSTAMP_FILTER_ALL; 2355 break; 2356 default: 2357 config.rx_filter = HWTSTAMP_FILTER_NONE; 2358 } 2359 2360 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2361 -EFAULT : 0; 2362 } 2363 2364 /* Control hardware time stamping */ 2365 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 2366 { 2367 struct ravb_private *priv = netdev_priv(ndev); 2368 struct hwtstamp_config config; 2369 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 2370 u32 tstamp_tx_ctrl; 2371 2372 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 2373 return -EFAULT; 2374 2375 switch (config.tx_type) { 2376 case HWTSTAMP_TX_OFF: 2377 tstamp_tx_ctrl = 0; 2378 break; 2379 case HWTSTAMP_TX_ON: 2380 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 2381 break; 2382 default: 2383 return -ERANGE; 2384 } 2385 2386 switch (config.rx_filter) { 2387 case HWTSTAMP_FILTER_NONE: 2388 tstamp_rx_ctrl = 0; 2389 break; 2390 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2391 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 2392 break; 2393 default: 2394 config.rx_filter = HWTSTAMP_FILTER_ALL; 2395 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 2396 } 2397 2398 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 2399 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 2400 2401 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2402 -EFAULT : 0; 2403 } 2404 2405 /* ioctl to device function */ 2406 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 2407 { 2408 struct phy_device *phydev = ndev->phydev; 2409 2410 if (!netif_running(ndev)) 2411 return -EINVAL; 2412 2413 if (!phydev) 2414 return -ENODEV; 2415 2416 switch (cmd) { 2417 case SIOCGHWTSTAMP: 2418 return ravb_hwtstamp_get(ndev, req); 2419 case SIOCSHWTSTAMP: 2420 return ravb_hwtstamp_set(ndev, req); 2421 } 2422 2423 return phy_mii_ioctl(phydev, req, cmd); 2424 } 2425 2426 static int ravb_change_mtu(struct net_device *ndev, int new_mtu) 2427 { 2428 struct ravb_private *priv = netdev_priv(ndev); 2429 2430 ndev->mtu = new_mtu; 2431 2432 if (netif_running(ndev)) { 2433 synchronize_irq(priv->emac_irq); 2434 ravb_emac_init(ndev); 2435 } 2436 2437 netdev_update_features(ndev); 2438 2439 return 0; 2440 } 2441 2442 static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 2443 { 2444 struct ravb_private *priv = netdev_priv(ndev); 2445 unsigned long flags; 2446 2447 spin_lock_irqsave(&priv->lock, flags); 2448 2449 /* Disable TX and RX */ 2450 ravb_rcv_snd_disable(ndev); 2451 2452 /* Modify RX Checksum setting */ 2453 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 2454 2455 /* Enable TX and RX */ 2456 ravb_rcv_snd_enable(ndev); 2457 2458 spin_unlock_irqrestore(&priv->lock, flags); 2459 } 2460 2461 static int ravb_endisable_csum_gbeth(struct net_device *ndev, enum ravb_reg reg, 2462 u32 val, u32 mask) 2463 { 2464 u32 csr0 = CSR0_TPE | CSR0_RPE; 2465 int ret; 2466 2467 ravb_write(ndev, csr0 & ~mask, CSR0); 2468 ret = ravb_wait(ndev, CSR0, mask, 0); 2469 if (!ret) 2470 ravb_write(ndev, val, reg); 2471 2472 ravb_write(ndev, csr0, CSR0); 2473 2474 return ret; 2475 } 2476 2477 static int ravb_set_features_gbeth(struct net_device *ndev, 2478 netdev_features_t features) 2479 { 2480 netdev_features_t changed = ndev->features ^ features; 2481 struct ravb_private *priv = netdev_priv(ndev); 2482 unsigned long flags; 2483 int ret = 0; 2484 u32 val; 2485 2486 spin_lock_irqsave(&priv->lock, flags); 2487 if (changed & NETIF_F_RXCSUM) { 2488 if (features & NETIF_F_RXCSUM) 2489 val = CSR2_RIP4 | CSR2_RTCP4 | CSR2_RUDP4 | CSR2_RICMP4; 2490 else 2491 val = 0; 2492 2493 ret = ravb_endisable_csum_gbeth(ndev, CSR2, val, CSR0_RPE); 2494 if (ret) 2495 goto done; 2496 } 2497 2498 if (changed & NETIF_F_HW_CSUM) { 2499 if (features & NETIF_F_HW_CSUM) 2500 val = CSR1_TIP4 | CSR1_TTCP4 | CSR1_TUDP4; 2501 else 2502 val = 0; 2503 2504 ret = ravb_endisable_csum_gbeth(ndev, CSR1, val, CSR0_TPE); 2505 if (ret) 2506 goto done; 2507 } 2508 2509 done: 2510 spin_unlock_irqrestore(&priv->lock, flags); 2511 2512 return ret; 2513 } 2514 2515 static int ravb_set_features_rcar(struct net_device *ndev, 2516 netdev_features_t features) 2517 { 2518 netdev_features_t changed = ndev->features ^ features; 2519 2520 if (changed & NETIF_F_RXCSUM) 2521 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 2522 2523 return 0; 2524 } 2525 2526 static int ravb_set_features(struct net_device *ndev, 2527 netdev_features_t features) 2528 { 2529 struct ravb_private *priv = netdev_priv(ndev); 2530 const struct ravb_hw_info *info = priv->info; 2531 struct device *dev = &priv->pdev->dev; 2532 int ret; 2533 2534 pm_runtime_get_noresume(dev); 2535 2536 if (pm_runtime_active(dev)) 2537 ret = info->set_feature(ndev, features); 2538 else 2539 ret = 0; 2540 2541 pm_runtime_put_noidle(dev); 2542 2543 if (ret) 2544 return ret; 2545 2546 ndev->features = features; 2547 2548 return 0; 2549 } 2550 2551 static const struct net_device_ops ravb_netdev_ops = { 2552 .ndo_open = ravb_open, 2553 .ndo_stop = ravb_close, 2554 .ndo_start_xmit = ravb_start_xmit, 2555 .ndo_select_queue = ravb_select_queue, 2556 .ndo_get_stats = ravb_get_stats, 2557 .ndo_set_rx_mode = ravb_set_rx_mode, 2558 .ndo_tx_timeout = ravb_tx_timeout, 2559 .ndo_eth_ioctl = ravb_do_ioctl, 2560 .ndo_change_mtu = ravb_change_mtu, 2561 .ndo_validate_addr = eth_validate_addr, 2562 .ndo_set_mac_address = eth_mac_addr, 2563 .ndo_set_features = ravb_set_features, 2564 }; 2565 2566 /* MDIO bus init function */ 2567 static int ravb_mdio_init(struct ravb_private *priv) 2568 { 2569 struct platform_device *pdev = priv->pdev; 2570 struct device *dev = &pdev->dev; 2571 struct phy_device *phydev; 2572 struct device_node *pn; 2573 int error; 2574 2575 /* Bitbang init */ 2576 priv->mdiobb.ops = &bb_ops; 2577 2578 /* MII controller setting */ 2579 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 2580 if (!priv->mii_bus) 2581 return -ENOMEM; 2582 2583 /* Hook up MII support for ethtool */ 2584 priv->mii_bus->name = "ravb_mii"; 2585 priv->mii_bus->parent = dev; 2586 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2587 pdev->name, pdev->id); 2588 2589 /* Register MDIO bus */ 2590 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 2591 if (error) 2592 goto out_free_bus; 2593 2594 pn = of_parse_phandle(dev->of_node, "phy-handle", 0); 2595 phydev = of_phy_find_device(pn); 2596 if (phydev) { 2597 phydev->mac_managed_pm = true; 2598 put_device(&phydev->mdio.dev); 2599 } 2600 of_node_put(pn); 2601 2602 return 0; 2603 2604 out_free_bus: 2605 free_mdio_bitbang(priv->mii_bus); 2606 return error; 2607 } 2608 2609 /* MDIO bus release function */ 2610 static int ravb_mdio_release(struct ravb_private *priv) 2611 { 2612 /* Unregister mdio bus */ 2613 mdiobus_unregister(priv->mii_bus); 2614 2615 /* Free bitbang info */ 2616 free_mdio_bitbang(priv->mii_bus); 2617 2618 return 0; 2619 } 2620 2621 static const struct ravb_hw_info ravb_gen3_hw_info = { 2622 .receive = ravb_rx_rcar, 2623 .set_rate = ravb_set_rate_rcar, 2624 .set_feature = ravb_set_features_rcar, 2625 .dmac_init = ravb_dmac_init_rcar, 2626 .emac_init = ravb_emac_init_rcar, 2627 .gstrings_stats = ravb_gstrings_stats, 2628 .gstrings_size = sizeof(ravb_gstrings_stats), 2629 .net_hw_features = NETIF_F_RXCSUM, 2630 .net_features = NETIF_F_RXCSUM, 2631 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2632 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2633 .rx_max_frame_size = SZ_2K, 2634 .rx_max_desc_use = SZ_2K - ETH_FCS_LEN + sizeof(__sum16), 2635 .rx_desc_size = sizeof(struct ravb_ex_rx_desc), 2636 .internal_delay = 1, 2637 .tx_counters = 1, 2638 .multi_irqs = 1, 2639 .irq_en_dis = 1, 2640 .ccc_gac = 1, 2641 .nc_queues = 1, 2642 .magic_pkt = 1, 2643 }; 2644 2645 static const struct ravb_hw_info ravb_gen2_hw_info = { 2646 .receive = ravb_rx_rcar, 2647 .set_rate = ravb_set_rate_rcar, 2648 .set_feature = ravb_set_features_rcar, 2649 .dmac_init = ravb_dmac_init_rcar, 2650 .emac_init = ravb_emac_init_rcar, 2651 .gstrings_stats = ravb_gstrings_stats, 2652 .gstrings_size = sizeof(ravb_gstrings_stats), 2653 .net_hw_features = NETIF_F_RXCSUM, 2654 .net_features = NETIF_F_RXCSUM, 2655 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2656 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2657 .rx_max_frame_size = SZ_2K, 2658 .rx_max_desc_use = SZ_2K - ETH_FCS_LEN + sizeof(__sum16), 2659 .rx_desc_size = sizeof(struct ravb_ex_rx_desc), 2660 .aligned_tx = 1, 2661 .gptp = 1, 2662 .nc_queues = 1, 2663 .magic_pkt = 1, 2664 }; 2665 2666 static const struct ravb_hw_info ravb_rzv2m_hw_info = { 2667 .receive = ravb_rx_rcar, 2668 .set_rate = ravb_set_rate_rcar, 2669 .set_feature = ravb_set_features_rcar, 2670 .dmac_init = ravb_dmac_init_rcar, 2671 .emac_init = ravb_emac_init_rcar, 2672 .gstrings_stats = ravb_gstrings_stats, 2673 .gstrings_size = sizeof(ravb_gstrings_stats), 2674 .net_hw_features = NETIF_F_RXCSUM, 2675 .net_features = NETIF_F_RXCSUM, 2676 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2677 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2678 .rx_max_frame_size = SZ_2K, 2679 .rx_max_desc_use = SZ_2K - ETH_FCS_LEN + sizeof(__sum16), 2680 .rx_desc_size = sizeof(struct ravb_ex_rx_desc), 2681 .multi_irqs = 1, 2682 .err_mgmt_irqs = 1, 2683 .gptp = 1, 2684 .gptp_ref_clk = 1, 2685 .nc_queues = 1, 2686 .magic_pkt = 1, 2687 }; 2688 2689 static const struct ravb_hw_info gbeth_hw_info = { 2690 .receive = ravb_rx_gbeth, 2691 .set_rate = ravb_set_rate_gbeth, 2692 .set_feature = ravb_set_features_gbeth, 2693 .dmac_init = ravb_dmac_init_gbeth, 2694 .emac_init = ravb_emac_init_gbeth, 2695 .gstrings_stats = ravb_gstrings_stats_gbeth, 2696 .gstrings_size = sizeof(ravb_gstrings_stats_gbeth), 2697 .net_hw_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM, 2698 .net_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM, 2699 .stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth), 2700 .tccr_mask = TCCR_TSRQ0, 2701 .rx_max_frame_size = SZ_8K, 2702 .rx_max_desc_use = 4080, 2703 .rx_desc_size = sizeof(struct ravb_rx_desc), 2704 .aligned_tx = 1, 2705 .tx_counters = 1, 2706 .carrier_counters = 1, 2707 .half_duplex = 1, 2708 }; 2709 2710 static const struct of_device_id ravb_match_table[] = { 2711 { .compatible = "renesas,etheravb-r8a7790", .data = &ravb_gen2_hw_info }, 2712 { .compatible = "renesas,etheravb-r8a7794", .data = &ravb_gen2_hw_info }, 2713 { .compatible = "renesas,etheravb-rcar-gen2", .data = &ravb_gen2_hw_info }, 2714 { .compatible = "renesas,etheravb-r8a7795", .data = &ravb_gen3_hw_info }, 2715 { .compatible = "renesas,etheravb-rcar-gen3", .data = &ravb_gen3_hw_info }, 2716 { .compatible = "renesas,etheravb-rcar-gen4", .data = &ravb_gen3_hw_info }, 2717 { .compatible = "renesas,etheravb-rzv2m", .data = &ravb_rzv2m_hw_info }, 2718 { .compatible = "renesas,rzg2l-gbeth", .data = &gbeth_hw_info }, 2719 { } 2720 }; 2721 MODULE_DEVICE_TABLE(of, ravb_match_table); 2722 2723 static int ravb_setup_irq(struct ravb_private *priv, const char *irq_name, 2724 const char *ch, int *irq, irq_handler_t handler) 2725 { 2726 struct platform_device *pdev = priv->pdev; 2727 struct net_device *ndev = priv->ndev; 2728 struct device *dev = &pdev->dev; 2729 const char *dev_name; 2730 unsigned long flags; 2731 int error, irq_num; 2732 2733 if (irq_name) { 2734 dev_name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); 2735 if (!dev_name) 2736 return -ENOMEM; 2737 2738 irq_num = platform_get_irq_byname(pdev, irq_name); 2739 flags = 0; 2740 } else { 2741 dev_name = ndev->name; 2742 irq_num = platform_get_irq(pdev, 0); 2743 flags = IRQF_SHARED; 2744 } 2745 if (irq_num < 0) 2746 return irq_num; 2747 2748 if (irq) 2749 *irq = irq_num; 2750 2751 error = devm_request_irq(dev, irq_num, handler, flags, dev_name, ndev); 2752 if (error) 2753 netdev_err(ndev, "cannot request IRQ %s\n", dev_name); 2754 2755 return error; 2756 } 2757 2758 static int ravb_setup_irqs(struct ravb_private *priv) 2759 { 2760 const struct ravb_hw_info *info = priv->info; 2761 struct net_device *ndev = priv->ndev; 2762 const char *irq_name, *emac_irq_name; 2763 int error; 2764 2765 if (!info->multi_irqs) 2766 return ravb_setup_irq(priv, NULL, NULL, &ndev->irq, ravb_interrupt); 2767 2768 if (info->err_mgmt_irqs) { 2769 irq_name = "dia"; 2770 emac_irq_name = "line3"; 2771 } else { 2772 irq_name = "ch22"; 2773 emac_irq_name = "ch24"; 2774 } 2775 2776 error = ravb_setup_irq(priv, irq_name, "ch22:multi", &ndev->irq, ravb_multi_interrupt); 2777 if (error) 2778 return error; 2779 2780 error = ravb_setup_irq(priv, emac_irq_name, "ch24:emac", &priv->emac_irq, 2781 ravb_emac_interrupt); 2782 if (error) 2783 return error; 2784 2785 if (info->err_mgmt_irqs) { 2786 error = ravb_setup_irq(priv, "err_a", "err_a", NULL, ravb_multi_interrupt); 2787 if (error) 2788 return error; 2789 2790 error = ravb_setup_irq(priv, "mgmt_a", "mgmt_a", NULL, ravb_multi_interrupt); 2791 if (error) 2792 return error; 2793 } 2794 2795 error = ravb_setup_irq(priv, "ch0", "ch0:rx_be", NULL, ravb_be_interrupt); 2796 if (error) 2797 return error; 2798 2799 error = ravb_setup_irq(priv, "ch1", "ch1:rx_nc", NULL, ravb_nc_interrupt); 2800 if (error) 2801 return error; 2802 2803 error = ravb_setup_irq(priv, "ch18", "ch18:tx_be", NULL, ravb_be_interrupt); 2804 if (error) 2805 return error; 2806 2807 return ravb_setup_irq(priv, "ch19", "ch19:tx_nc", NULL, ravb_nc_interrupt); 2808 } 2809 2810 static int ravb_probe(struct platform_device *pdev) 2811 { 2812 struct device_node *np = pdev->dev.of_node; 2813 const struct ravb_hw_info *info; 2814 struct reset_control *rstc; 2815 struct ravb_private *priv; 2816 struct net_device *ndev; 2817 struct resource *res; 2818 int error, q; 2819 2820 if (!np) { 2821 dev_err(&pdev->dev, 2822 "this driver is required to be instantiated from device tree\n"); 2823 return -EINVAL; 2824 } 2825 2826 rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 2827 if (IS_ERR(rstc)) 2828 return dev_err_probe(&pdev->dev, PTR_ERR(rstc), 2829 "failed to get cpg reset\n"); 2830 2831 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 2832 NUM_TX_QUEUE, NUM_RX_QUEUE); 2833 if (!ndev) 2834 return -ENOMEM; 2835 2836 info = of_device_get_match_data(&pdev->dev); 2837 2838 ndev->features = info->net_features; 2839 ndev->hw_features = info->net_hw_features; 2840 2841 error = reset_control_deassert(rstc); 2842 if (error) 2843 goto out_free_netdev; 2844 2845 SET_NETDEV_DEV(ndev, &pdev->dev); 2846 2847 priv = netdev_priv(ndev); 2848 priv->info = info; 2849 priv->rstc = rstc; 2850 priv->ndev = ndev; 2851 priv->pdev = pdev; 2852 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2853 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2854 if (info->nc_queues) { 2855 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2856 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2857 } 2858 2859 error = ravb_setup_irqs(priv); 2860 if (error) 2861 goto out_reset_assert; 2862 2863 priv->clk = devm_clk_get(&pdev->dev, NULL); 2864 if (IS_ERR(priv->clk)) { 2865 error = PTR_ERR(priv->clk); 2866 goto out_reset_assert; 2867 } 2868 2869 if (info->gptp_ref_clk) { 2870 priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp"); 2871 if (IS_ERR(priv->gptp_clk)) { 2872 error = PTR_ERR(priv->gptp_clk); 2873 goto out_reset_assert; 2874 } 2875 } 2876 2877 priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk"); 2878 if (IS_ERR(priv->refclk)) { 2879 error = PTR_ERR(priv->refclk); 2880 goto out_reset_assert; 2881 } 2882 clk_prepare(priv->refclk); 2883 2884 platform_set_drvdata(pdev, ndev); 2885 pm_runtime_set_autosuspend_delay(&pdev->dev, 100); 2886 pm_runtime_use_autosuspend(&pdev->dev); 2887 pm_runtime_enable(&pdev->dev); 2888 error = pm_runtime_resume_and_get(&pdev->dev); 2889 if (error < 0) 2890 goto out_rpm_disable; 2891 2892 priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2893 if (IS_ERR(priv->addr)) { 2894 error = PTR_ERR(priv->addr); 2895 goto out_rpm_put; 2896 } 2897 2898 /* The Ether-specific entries in the device structure. */ 2899 ndev->base_addr = res->start; 2900 2901 spin_lock_init(&priv->lock); 2902 INIT_WORK(&priv->work, ravb_tx_timeout_work); 2903 2904 error = of_get_phy_mode(np, &priv->phy_interface); 2905 if (error && error != -ENODEV) 2906 goto out_rpm_put; 2907 2908 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 2909 priv->avb_link_active_low = 2910 of_property_read_bool(np, "renesas,ether-link-active-low"); 2911 2912 ndev->max_mtu = info->rx_max_frame_size - 2913 (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 2914 ndev->min_mtu = ETH_MIN_MTU; 2915 2916 /* FIXME: R-Car Gen2 has 4byte alignment restriction for tx buffer 2917 * Use two descriptor to handle such situation. First descriptor to 2918 * handle aligned data buffer and second descriptor to handle the 2919 * overflow data because of alignment. 2920 */ 2921 priv->num_tx_desc = info->aligned_tx ? 2 : 1; 2922 2923 /* Set function */ 2924 ndev->netdev_ops = &ravb_netdev_ops; 2925 ndev->ethtool_ops = &ravb_ethtool_ops; 2926 2927 error = ravb_compute_gti(ndev); 2928 if (error) 2929 goto out_rpm_put; 2930 2931 ravb_parse_delay_mode(np, ndev); 2932 2933 /* Allocate descriptor base address table */ 2934 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 2935 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 2936 &priv->desc_bat_dma, GFP_KERNEL); 2937 if (!priv->desc_bat) { 2938 dev_err(&pdev->dev, 2939 "Cannot allocate desc base address table (size %d bytes)\n", 2940 priv->desc_bat_size); 2941 error = -ENOMEM; 2942 goto out_rpm_put; 2943 } 2944 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 2945 priv->desc_bat[q].die_dt = DT_EOS; 2946 2947 /* Initialise HW timestamp list */ 2948 INIT_LIST_HEAD(&priv->ts_skb_list); 2949 2950 /* Debug message level */ 2951 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 2952 2953 /* Set config mode as this is needed for PHY initialization. */ 2954 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 2955 if (error) 2956 goto out_rpm_put; 2957 2958 /* Read and set MAC address */ 2959 ravb_read_mac_address(np, ndev); 2960 if (!is_valid_ether_addr(ndev->dev_addr)) { 2961 dev_warn(&pdev->dev, 2962 "no valid MAC address supplied, using a random one\n"); 2963 eth_hw_addr_random(ndev); 2964 } 2965 2966 /* MDIO bus init */ 2967 error = ravb_mdio_init(priv); 2968 if (error) { 2969 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 2970 goto out_reset_mode; 2971 } 2972 2973 /* Undo previous switch to config opmode. */ 2974 error = ravb_set_opmode(ndev, CCC_OPC_RESET); 2975 if (error) 2976 goto out_mdio_release; 2977 2978 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll); 2979 if (info->nc_queues) 2980 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll); 2981 2982 /* Network device register */ 2983 error = register_netdev(ndev); 2984 if (error) 2985 goto out_napi_del; 2986 2987 device_set_wakeup_capable(&pdev->dev, 1); 2988 2989 /* Print device information */ 2990 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 2991 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2992 2993 pm_runtime_mark_last_busy(&pdev->dev); 2994 pm_runtime_put_autosuspend(&pdev->dev); 2995 2996 return 0; 2997 2998 out_napi_del: 2999 if (info->nc_queues) 3000 netif_napi_del(&priv->napi[RAVB_NC]); 3001 3002 netif_napi_del(&priv->napi[RAVB_BE]); 3003 out_mdio_release: 3004 ravb_mdio_release(priv); 3005 out_reset_mode: 3006 ravb_set_opmode(ndev, CCC_OPC_RESET); 3007 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 3008 priv->desc_bat_dma); 3009 out_rpm_put: 3010 pm_runtime_put(&pdev->dev); 3011 out_rpm_disable: 3012 pm_runtime_disable(&pdev->dev); 3013 pm_runtime_dont_use_autosuspend(&pdev->dev); 3014 clk_unprepare(priv->refclk); 3015 out_reset_assert: 3016 reset_control_assert(rstc); 3017 out_free_netdev: 3018 free_netdev(ndev); 3019 return error; 3020 } 3021 3022 static void ravb_remove(struct platform_device *pdev) 3023 { 3024 struct net_device *ndev = platform_get_drvdata(pdev); 3025 struct ravb_private *priv = netdev_priv(ndev); 3026 const struct ravb_hw_info *info = priv->info; 3027 struct device *dev = &priv->pdev->dev; 3028 int error; 3029 3030 error = pm_runtime_resume_and_get(dev); 3031 if (error < 0) 3032 return; 3033 3034 unregister_netdev(ndev); 3035 if (info->nc_queues) 3036 netif_napi_del(&priv->napi[RAVB_NC]); 3037 netif_napi_del(&priv->napi[RAVB_BE]); 3038 3039 ravb_mdio_release(priv); 3040 3041 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 3042 priv->desc_bat_dma); 3043 3044 pm_runtime_put_sync_suspend(&pdev->dev); 3045 pm_runtime_disable(&pdev->dev); 3046 pm_runtime_dont_use_autosuspend(dev); 3047 clk_unprepare(priv->refclk); 3048 reset_control_assert(priv->rstc); 3049 free_netdev(ndev); 3050 platform_set_drvdata(pdev, NULL); 3051 } 3052 3053 static int ravb_wol_setup(struct net_device *ndev) 3054 { 3055 struct ravb_private *priv = netdev_priv(ndev); 3056 const struct ravb_hw_info *info = priv->info; 3057 3058 /* Disable interrupts by clearing the interrupt masks. */ 3059 ravb_write(ndev, 0, RIC0); 3060 ravb_write(ndev, 0, RIC2); 3061 ravb_write(ndev, 0, TIC); 3062 3063 /* Only allow ECI interrupts */ 3064 synchronize_irq(priv->emac_irq); 3065 if (info->nc_queues) 3066 napi_disable(&priv->napi[RAVB_NC]); 3067 napi_disable(&priv->napi[RAVB_BE]); 3068 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 3069 3070 /* Enable MagicPacket */ 3071 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 3072 3073 if (priv->info->ccc_gac) 3074 ravb_ptp_stop(ndev); 3075 3076 return enable_irq_wake(priv->emac_irq); 3077 } 3078 3079 static int ravb_wol_restore(struct net_device *ndev) 3080 { 3081 struct ravb_private *priv = netdev_priv(ndev); 3082 const struct ravb_hw_info *info = priv->info; 3083 int error; 3084 3085 /* Set reset mode to rearm the WoL logic. */ 3086 error = ravb_set_opmode(ndev, CCC_OPC_RESET); 3087 if (error) 3088 return error; 3089 3090 /* Set AVB config mode. */ 3091 error = ravb_set_config_mode(ndev); 3092 if (error) 3093 return error; 3094 3095 if (priv->info->ccc_gac) 3096 ravb_ptp_init(ndev, priv->pdev); 3097 3098 if (info->nc_queues) 3099 napi_enable(&priv->napi[RAVB_NC]); 3100 napi_enable(&priv->napi[RAVB_BE]); 3101 3102 /* Disable MagicPacket */ 3103 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 3104 3105 ravb_close(ndev); 3106 3107 return disable_irq_wake(priv->emac_irq); 3108 } 3109 3110 static int ravb_suspend(struct device *dev) 3111 { 3112 struct net_device *ndev = dev_get_drvdata(dev); 3113 struct ravb_private *priv = netdev_priv(ndev); 3114 int ret; 3115 3116 if (!netif_running(ndev)) 3117 goto reset_assert; 3118 3119 netif_device_detach(ndev); 3120 3121 if (priv->wol_enabled) 3122 return ravb_wol_setup(ndev); 3123 3124 ret = ravb_close(ndev); 3125 if (ret) 3126 return ret; 3127 3128 ret = pm_runtime_force_suspend(&priv->pdev->dev); 3129 if (ret) 3130 return ret; 3131 3132 reset_assert: 3133 return reset_control_assert(priv->rstc); 3134 } 3135 3136 static int ravb_resume(struct device *dev) 3137 { 3138 struct net_device *ndev = dev_get_drvdata(dev); 3139 struct ravb_private *priv = netdev_priv(ndev); 3140 int ret; 3141 3142 ret = reset_control_deassert(priv->rstc); 3143 if (ret) 3144 return ret; 3145 3146 if (!netif_running(ndev)) 3147 return 0; 3148 3149 /* If WoL is enabled restore the interface. */ 3150 if (priv->wol_enabled) { 3151 ret = ravb_wol_restore(ndev); 3152 if (ret) 3153 return ret; 3154 } else { 3155 ret = pm_runtime_force_resume(dev); 3156 if (ret) 3157 return ret; 3158 } 3159 3160 /* Reopening the interface will restore the device to the working state. */ 3161 ret = ravb_open(ndev); 3162 if (ret < 0) 3163 goto out_rpm_put; 3164 3165 ravb_set_rx_mode(ndev); 3166 netif_device_attach(ndev); 3167 3168 return 0; 3169 3170 out_rpm_put: 3171 if (!priv->wol_enabled) { 3172 pm_runtime_mark_last_busy(dev); 3173 pm_runtime_put_autosuspend(dev); 3174 } 3175 3176 return ret; 3177 } 3178 3179 static int ravb_runtime_suspend(struct device *dev) 3180 { 3181 struct net_device *ndev = dev_get_drvdata(dev); 3182 struct ravb_private *priv = netdev_priv(ndev); 3183 3184 clk_disable(priv->refclk); 3185 3186 return 0; 3187 } 3188 3189 static int ravb_runtime_resume(struct device *dev) 3190 { 3191 struct net_device *ndev = dev_get_drvdata(dev); 3192 struct ravb_private *priv = netdev_priv(ndev); 3193 3194 return clk_enable(priv->refclk); 3195 } 3196 3197 static const struct dev_pm_ops ravb_dev_pm_ops = { 3198 SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 3199 RUNTIME_PM_OPS(ravb_runtime_suspend, ravb_runtime_resume, NULL) 3200 }; 3201 3202 static struct platform_driver ravb_driver = { 3203 .probe = ravb_probe, 3204 .remove_new = ravb_remove, 3205 .driver = { 3206 .name = "ravb", 3207 .pm = pm_ptr(&ravb_dev_pm_ops), 3208 .of_match_table = ravb_match_table, 3209 }, 3210 }; 3211 3212 module_platform_driver(ravb_driver); 3213 3214 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 3215 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 3216 MODULE_LICENSE("GPL v2"); 3217