1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet AVB device driver 3 * 4 * Copyright (C) 2014-2015 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * Based on the SuperH Ethernet driver 9 */ 10 11 #include <linux/cache.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_vlan.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/module.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/of_irq.h> 26 #include <linux/of_mdio.h> 27 #include <linux/of_net.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/slab.h> 30 #include <linux/spinlock.h> 31 #include <linux/sys_soc.h> 32 33 #include <asm/div64.h> 34 35 #include "ravb.h" 36 37 #define RAVB_DEF_MSG_ENABLE \ 38 (NETIF_MSG_LINK | \ 39 NETIF_MSG_TIMER | \ 40 NETIF_MSG_RX_ERR | \ 41 NETIF_MSG_TX_ERR) 42 43 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = { 44 "ch0", /* RAVB_BE */ 45 "ch1", /* RAVB_NC */ 46 }; 47 48 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = { 49 "ch18", /* RAVB_BE */ 50 "ch19", /* RAVB_NC */ 51 }; 52 53 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 54 u32 set) 55 { 56 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 57 } 58 59 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 60 { 61 int i; 62 63 for (i = 0; i < 10000; i++) { 64 if ((ravb_read(ndev, reg) & mask) == value) 65 return 0; 66 udelay(10); 67 } 68 return -ETIMEDOUT; 69 } 70 71 static int ravb_config(struct net_device *ndev) 72 { 73 int error; 74 75 /* Set config mode */ 76 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 77 /* Check if the operating mode is changed to the config mode */ 78 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); 79 if (error) 80 netdev_err(ndev, "failed to switch device to config mode\n"); 81 82 return error; 83 } 84 85 static void ravb_set_duplex(struct net_device *ndev) 86 { 87 struct ravb_private *priv = netdev_priv(ndev); 88 89 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex ? ECMR_DM : 0); 90 } 91 92 static void ravb_set_rate(struct net_device *ndev) 93 { 94 struct ravb_private *priv = netdev_priv(ndev); 95 96 switch (priv->speed) { 97 case 100: /* 100BASE */ 98 ravb_write(ndev, GECMR_SPEED_100, GECMR); 99 break; 100 case 1000: /* 1000BASE */ 101 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 102 break; 103 } 104 } 105 106 static void ravb_set_buffer_align(struct sk_buff *skb) 107 { 108 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 109 110 if (reserve) 111 skb_reserve(skb, RAVB_ALIGN - reserve); 112 } 113 114 /* Get MAC address from the MAC address registers 115 * 116 * Ethernet AVB device doesn't have ROM for MAC address. 117 * This function gets the MAC address that was used by a bootloader. 118 */ 119 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac) 120 { 121 if (mac) { 122 ether_addr_copy(ndev->dev_addr, mac); 123 } else { 124 u32 mahr = ravb_read(ndev, MAHR); 125 u32 malr = ravb_read(ndev, MALR); 126 127 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 128 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 129 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 130 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 131 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 132 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 133 } 134 } 135 136 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 137 { 138 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 139 mdiobb); 140 141 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 142 } 143 144 /* MDC pin control */ 145 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 146 { 147 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 148 } 149 150 /* Data I/O pin control */ 151 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 152 { 153 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 154 } 155 156 /* Set data bit */ 157 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 158 { 159 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 160 } 161 162 /* Get data bit */ 163 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 164 { 165 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 166 mdiobb); 167 168 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 169 } 170 171 /* MDIO bus control struct */ 172 static struct mdiobb_ops bb_ops = { 173 .owner = THIS_MODULE, 174 .set_mdc = ravb_set_mdc, 175 .set_mdio_dir = ravb_set_mdio_dir, 176 .set_mdio_data = ravb_set_mdio_data, 177 .get_mdio_data = ravb_get_mdio_data, 178 }; 179 180 /* Free TX skb function for AVB-IP */ 181 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 182 { 183 struct ravb_private *priv = netdev_priv(ndev); 184 struct net_device_stats *stats = &priv->stats[q]; 185 struct ravb_tx_desc *desc; 186 int free_num = 0; 187 int entry; 188 u32 size; 189 190 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 191 bool txed; 192 193 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 194 NUM_TX_DESC); 195 desc = &priv->tx_ring[q][entry]; 196 txed = desc->die_dt == DT_FEMPTY; 197 if (free_txed_only && !txed) 198 break; 199 /* Descriptor type must be checked before all other reads */ 200 dma_rmb(); 201 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 202 /* Free the original skb. */ 203 if (priv->tx_skb[q][entry / NUM_TX_DESC]) { 204 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 205 size, DMA_TO_DEVICE); 206 /* Last packet descriptor? */ 207 if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) { 208 entry /= NUM_TX_DESC; 209 dev_kfree_skb_any(priv->tx_skb[q][entry]); 210 priv->tx_skb[q][entry] = NULL; 211 if (txed) 212 stats->tx_packets++; 213 } 214 free_num++; 215 } 216 if (txed) 217 stats->tx_bytes += size; 218 desc->die_dt = DT_EEMPTY; 219 } 220 return free_num; 221 } 222 223 /* Free skb's and DMA buffers for Ethernet AVB */ 224 static void ravb_ring_free(struct net_device *ndev, int q) 225 { 226 struct ravb_private *priv = netdev_priv(ndev); 227 int ring_size; 228 int i; 229 230 if (priv->rx_ring[q]) { 231 for (i = 0; i < priv->num_rx_ring[q]; i++) { 232 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i]; 233 234 if (!dma_mapping_error(ndev->dev.parent, 235 le32_to_cpu(desc->dptr))) 236 dma_unmap_single(ndev->dev.parent, 237 le32_to_cpu(desc->dptr), 238 priv->rx_buf_sz, 239 DMA_FROM_DEVICE); 240 } 241 ring_size = sizeof(struct ravb_ex_rx_desc) * 242 (priv->num_rx_ring[q] + 1); 243 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], 244 priv->rx_desc_dma[q]); 245 priv->rx_ring[q] = NULL; 246 } 247 248 if (priv->tx_ring[q]) { 249 ravb_tx_free(ndev, q, false); 250 251 ring_size = sizeof(struct ravb_tx_desc) * 252 (priv->num_tx_ring[q] * NUM_TX_DESC + 1); 253 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 254 priv->tx_desc_dma[q]); 255 priv->tx_ring[q] = NULL; 256 } 257 258 /* Free RX skb ringbuffer */ 259 if (priv->rx_skb[q]) { 260 for (i = 0; i < priv->num_rx_ring[q]; i++) 261 dev_kfree_skb(priv->rx_skb[q][i]); 262 } 263 kfree(priv->rx_skb[q]); 264 priv->rx_skb[q] = NULL; 265 266 /* Free aligned TX buffers */ 267 kfree(priv->tx_align[q]); 268 priv->tx_align[q] = NULL; 269 270 /* Free TX skb ringbuffer. 271 * SKBs are freed by ravb_tx_free() call above. 272 */ 273 kfree(priv->tx_skb[q]); 274 priv->tx_skb[q] = NULL; 275 } 276 277 /* Format skb and descriptor buffer for Ethernet AVB */ 278 static void ravb_ring_format(struct net_device *ndev, int q) 279 { 280 struct ravb_private *priv = netdev_priv(ndev); 281 struct ravb_ex_rx_desc *rx_desc; 282 struct ravb_tx_desc *tx_desc; 283 struct ravb_desc *desc; 284 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 285 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 286 NUM_TX_DESC; 287 dma_addr_t dma_addr; 288 int i; 289 290 priv->cur_rx[q] = 0; 291 priv->cur_tx[q] = 0; 292 priv->dirty_rx[q] = 0; 293 priv->dirty_tx[q] = 0; 294 295 memset(priv->rx_ring[q], 0, rx_ring_size); 296 /* Build RX ring buffer */ 297 for (i = 0; i < priv->num_rx_ring[q]; i++) { 298 /* RX descriptor */ 299 rx_desc = &priv->rx_ring[q][i]; 300 rx_desc->ds_cc = cpu_to_le16(priv->rx_buf_sz); 301 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 302 priv->rx_buf_sz, 303 DMA_FROM_DEVICE); 304 /* We just set the data size to 0 for a failed mapping which 305 * should prevent DMA from happening... 306 */ 307 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 308 rx_desc->ds_cc = cpu_to_le16(0); 309 rx_desc->dptr = cpu_to_le32(dma_addr); 310 rx_desc->die_dt = DT_FEMPTY; 311 } 312 rx_desc = &priv->rx_ring[q][i]; 313 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 314 rx_desc->die_dt = DT_LINKFIX; /* type */ 315 316 memset(priv->tx_ring[q], 0, tx_ring_size); 317 /* Build TX ring buffer */ 318 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 319 i++, tx_desc++) { 320 tx_desc->die_dt = DT_EEMPTY; 321 tx_desc++; 322 tx_desc->die_dt = DT_EEMPTY; 323 } 324 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 325 tx_desc->die_dt = DT_LINKFIX; /* type */ 326 327 /* RX descriptor base address for best effort */ 328 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 329 desc->die_dt = DT_LINKFIX; /* type */ 330 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 331 332 /* TX descriptor base address for best effort */ 333 desc = &priv->desc_bat[q]; 334 desc->die_dt = DT_LINKFIX; /* type */ 335 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 336 } 337 338 /* Init skb and descriptor buffer for Ethernet AVB */ 339 static int ravb_ring_init(struct net_device *ndev, int q) 340 { 341 struct ravb_private *priv = netdev_priv(ndev); 342 struct sk_buff *skb; 343 int ring_size; 344 int i; 345 346 priv->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : ndev->mtu) + 347 ETH_HLEN + VLAN_HLEN; 348 349 /* Allocate RX and TX skb rings */ 350 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 351 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 352 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 353 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 354 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 355 goto error; 356 357 for (i = 0; i < priv->num_rx_ring[q]; i++) { 358 skb = netdev_alloc_skb(ndev, priv->rx_buf_sz + RAVB_ALIGN - 1); 359 if (!skb) 360 goto error; 361 ravb_set_buffer_align(skb); 362 priv->rx_skb[q][i] = skb; 363 } 364 365 /* Allocate rings for the aligned buffers */ 366 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 367 DPTR_ALIGN - 1, GFP_KERNEL); 368 if (!priv->tx_align[q]) 369 goto error; 370 371 /* Allocate all RX descriptors. */ 372 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); 373 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 374 &priv->rx_desc_dma[q], 375 GFP_KERNEL); 376 if (!priv->rx_ring[q]) 377 goto error; 378 379 priv->dirty_rx[q] = 0; 380 381 /* Allocate all TX descriptors. */ 382 ring_size = sizeof(struct ravb_tx_desc) * 383 (priv->num_tx_ring[q] * NUM_TX_DESC + 1); 384 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 385 &priv->tx_desc_dma[q], 386 GFP_KERNEL); 387 if (!priv->tx_ring[q]) 388 goto error; 389 390 return 0; 391 392 error: 393 ravb_ring_free(ndev, q); 394 395 return -ENOMEM; 396 } 397 398 /* E-MAC init function */ 399 static void ravb_emac_init(struct net_device *ndev) 400 { 401 struct ravb_private *priv = netdev_priv(ndev); 402 403 /* Receive frame limit set register */ 404 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 405 406 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 407 ravb_write(ndev, ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) | 408 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 409 ECMR_TE | ECMR_RE, ECMR); 410 411 ravb_set_rate(ndev); 412 413 /* Set MAC address */ 414 ravb_write(ndev, 415 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 416 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 417 ravb_write(ndev, 418 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 419 420 /* E-MAC status register clear */ 421 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 422 423 /* E-MAC interrupt enable register */ 424 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 425 } 426 427 /* Device init function for Ethernet AVB */ 428 static int ravb_dmac_init(struct net_device *ndev) 429 { 430 struct ravb_private *priv = netdev_priv(ndev); 431 int error; 432 433 /* Set CONFIG mode */ 434 error = ravb_config(ndev); 435 if (error) 436 return error; 437 438 error = ravb_ring_init(ndev, RAVB_BE); 439 if (error) 440 return error; 441 error = ravb_ring_init(ndev, RAVB_NC); 442 if (error) { 443 ravb_ring_free(ndev, RAVB_BE); 444 return error; 445 } 446 447 /* Descriptor format */ 448 ravb_ring_format(ndev, RAVB_BE); 449 ravb_ring_format(ndev, RAVB_NC); 450 451 #if defined(__LITTLE_ENDIAN) 452 ravb_modify(ndev, CCC, CCC_BOC, 0); 453 #else 454 ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC); 455 #endif 456 457 /* Set AVB RX */ 458 ravb_write(ndev, 459 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 460 461 /* Set FIFO size */ 462 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC); 463 464 /* Timestamp enable */ 465 ravb_write(ndev, TCCR_TFEN, TCCR); 466 467 /* Interrupt init: */ 468 if (priv->chip_id == RCAR_GEN3) { 469 /* Clear DIL.DPLx */ 470 ravb_write(ndev, 0, DIL); 471 /* Set queue specific interrupt */ 472 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 473 } 474 /* Frame receive */ 475 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 476 /* Disable FIFO full warning */ 477 ravb_write(ndev, 0, RIC1); 478 /* Receive FIFO full error, descriptor empty */ 479 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 480 /* Frame transmitted, timestamp FIFO updated */ 481 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 482 483 /* Setting the control will start the AVB-DMAC process. */ 484 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION); 485 486 return 0; 487 } 488 489 static void ravb_get_tx_tstamp(struct net_device *ndev) 490 { 491 struct ravb_private *priv = netdev_priv(ndev); 492 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 493 struct skb_shared_hwtstamps shhwtstamps; 494 struct sk_buff *skb; 495 struct timespec64 ts; 496 u16 tag, tfa_tag; 497 int count; 498 u32 tfa2; 499 500 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 501 while (count--) { 502 tfa2 = ravb_read(ndev, TFA2); 503 tfa_tag = (tfa2 & TFA2_TST) >> 16; 504 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 505 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 506 ravb_read(ndev, TFA1); 507 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 508 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 509 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 510 list) { 511 skb = ts_skb->skb; 512 tag = ts_skb->tag; 513 list_del(&ts_skb->list); 514 kfree(ts_skb); 515 if (tag == tfa_tag) { 516 skb_tstamp_tx(skb, &shhwtstamps); 517 break; 518 } 519 } 520 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 521 } 522 } 523 524 static void ravb_rx_csum(struct sk_buff *skb) 525 { 526 u8 *hw_csum; 527 528 /* The hardware checksum is 2 bytes appended to packet data */ 529 if (unlikely(skb->len < 2)) 530 return; 531 hw_csum = skb_tail_pointer(skb) - 2; 532 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 533 skb->ip_summed = CHECKSUM_COMPLETE; 534 skb_trim(skb, skb->len - 2); 535 } 536 537 /* Packet receive function for Ethernet AVB */ 538 static bool ravb_rx(struct net_device *ndev, int *quota, int q) 539 { 540 struct ravb_private *priv = netdev_priv(ndev); 541 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 542 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 543 priv->cur_rx[q]; 544 struct net_device_stats *stats = &priv->stats[q]; 545 struct ravb_ex_rx_desc *desc; 546 struct sk_buff *skb; 547 dma_addr_t dma_addr; 548 struct timespec64 ts; 549 u8 desc_status; 550 u16 pkt_len; 551 int limit; 552 553 boguscnt = min(boguscnt, *quota); 554 limit = boguscnt; 555 desc = &priv->rx_ring[q][entry]; 556 while (desc->die_dt != DT_FEMPTY) { 557 /* Descriptor type must be checked before all other reads */ 558 dma_rmb(); 559 desc_status = desc->msc; 560 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 561 562 if (--boguscnt < 0) 563 break; 564 565 /* We use 0-byte descriptors to mark the DMA mapping errors */ 566 if (!pkt_len) 567 continue; 568 569 if (desc_status & MSC_MC) 570 stats->multicast++; 571 572 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 573 MSC_CEEF)) { 574 stats->rx_errors++; 575 if (desc_status & MSC_CRC) 576 stats->rx_crc_errors++; 577 if (desc_status & MSC_RFE) 578 stats->rx_frame_errors++; 579 if (desc_status & (MSC_RTLF | MSC_RTSF)) 580 stats->rx_length_errors++; 581 if (desc_status & MSC_CEEF) 582 stats->rx_missed_errors++; 583 } else { 584 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 585 586 skb = priv->rx_skb[q][entry]; 587 priv->rx_skb[q][entry] = NULL; 588 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 589 priv->rx_buf_sz, 590 DMA_FROM_DEVICE); 591 get_ts &= (q == RAVB_NC) ? 592 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 593 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 594 if (get_ts) { 595 struct skb_shared_hwtstamps *shhwtstamps; 596 597 shhwtstamps = skb_hwtstamps(skb); 598 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 599 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 600 32) | le32_to_cpu(desc->ts_sl); 601 ts.tv_nsec = le32_to_cpu(desc->ts_n); 602 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 603 } 604 605 skb_put(skb, pkt_len); 606 skb->protocol = eth_type_trans(skb, ndev); 607 if (ndev->features & NETIF_F_RXCSUM) 608 ravb_rx_csum(skb); 609 napi_gro_receive(&priv->napi[q], skb); 610 stats->rx_packets++; 611 stats->rx_bytes += pkt_len; 612 } 613 614 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 615 desc = &priv->rx_ring[q][entry]; 616 } 617 618 /* Refill the RX ring buffers. */ 619 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 620 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 621 desc = &priv->rx_ring[q][entry]; 622 desc->ds_cc = cpu_to_le16(priv->rx_buf_sz); 623 624 if (!priv->rx_skb[q][entry]) { 625 skb = netdev_alloc_skb(ndev, 626 priv->rx_buf_sz + 627 RAVB_ALIGN - 1); 628 if (!skb) 629 break; /* Better luck next round. */ 630 ravb_set_buffer_align(skb); 631 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 632 le16_to_cpu(desc->ds_cc), 633 DMA_FROM_DEVICE); 634 skb_checksum_none_assert(skb); 635 /* We just set the data size to 0 for a failed mapping 636 * which should prevent DMA from happening... 637 */ 638 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 639 desc->ds_cc = cpu_to_le16(0); 640 desc->dptr = cpu_to_le32(dma_addr); 641 priv->rx_skb[q][entry] = skb; 642 } 643 /* Descriptor type must be set after all the above writes */ 644 dma_wmb(); 645 desc->die_dt = DT_FEMPTY; 646 } 647 648 *quota -= limit - (++boguscnt); 649 650 return boguscnt <= 0; 651 } 652 653 static void ravb_rcv_snd_disable(struct net_device *ndev) 654 { 655 /* Disable TX and RX */ 656 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 657 } 658 659 static void ravb_rcv_snd_enable(struct net_device *ndev) 660 { 661 /* Enable TX and RX */ 662 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 663 } 664 665 /* function for waiting dma process finished */ 666 static int ravb_stop_dma(struct net_device *ndev) 667 { 668 int error; 669 670 /* Wait for stopping the hardware TX process */ 671 error = ravb_wait(ndev, TCCR, 672 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0); 673 if (error) 674 return error; 675 676 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 677 0); 678 if (error) 679 return error; 680 681 /* Stop the E-MAC's RX/TX processes. */ 682 ravb_rcv_snd_disable(ndev); 683 684 /* Wait for stopping the RX DMA process */ 685 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 686 if (error) 687 return error; 688 689 /* Stop AVB-DMAC process */ 690 return ravb_config(ndev); 691 } 692 693 /* E-MAC interrupt handler */ 694 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 695 { 696 struct ravb_private *priv = netdev_priv(ndev); 697 u32 ecsr, psr; 698 699 ecsr = ravb_read(ndev, ECSR); 700 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 701 702 if (ecsr & ECSR_MPD) 703 pm_wakeup_event(&priv->pdev->dev, 0); 704 if (ecsr & ECSR_ICD) 705 ndev->stats.tx_carrier_errors++; 706 if (ecsr & ECSR_LCHNG) { 707 /* Link changed */ 708 if (priv->no_avb_link) 709 return; 710 psr = ravb_read(ndev, PSR); 711 if (priv->avb_link_active_low) 712 psr ^= PSR_LMON; 713 if (!(psr & PSR_LMON)) { 714 /* DIsable RX and TX */ 715 ravb_rcv_snd_disable(ndev); 716 } else { 717 /* Enable RX and TX */ 718 ravb_rcv_snd_enable(ndev); 719 } 720 } 721 } 722 723 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 724 { 725 struct net_device *ndev = dev_id; 726 struct ravb_private *priv = netdev_priv(ndev); 727 728 spin_lock(&priv->lock); 729 ravb_emac_interrupt_unlocked(ndev); 730 mmiowb(); 731 spin_unlock(&priv->lock); 732 return IRQ_HANDLED; 733 } 734 735 /* Error interrupt handler */ 736 static void ravb_error_interrupt(struct net_device *ndev) 737 { 738 struct ravb_private *priv = netdev_priv(ndev); 739 u32 eis, ris2; 740 741 eis = ravb_read(ndev, EIS); 742 ravb_write(ndev, ~EIS_QFS, EIS); 743 if (eis & EIS_QFS) { 744 ris2 = ravb_read(ndev, RIS2); 745 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2); 746 747 /* Receive Descriptor Empty int */ 748 if (ris2 & RIS2_QFF0) 749 priv->stats[RAVB_BE].rx_over_errors++; 750 751 /* Receive Descriptor Empty int */ 752 if (ris2 & RIS2_QFF1) 753 priv->stats[RAVB_NC].rx_over_errors++; 754 755 /* Receive FIFO Overflow int */ 756 if (ris2 & RIS2_RFFF) 757 priv->rx_fifo_errors++; 758 } 759 } 760 761 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 762 { 763 struct ravb_private *priv = netdev_priv(ndev); 764 u32 ris0 = ravb_read(ndev, RIS0); 765 u32 ric0 = ravb_read(ndev, RIC0); 766 u32 tis = ravb_read(ndev, TIS); 767 u32 tic = ravb_read(ndev, TIC); 768 769 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 770 if (napi_schedule_prep(&priv->napi[q])) { 771 /* Mask RX and TX interrupts */ 772 if (priv->chip_id == RCAR_GEN2) { 773 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 774 ravb_write(ndev, tic & ~BIT(q), TIC); 775 } else { 776 ravb_write(ndev, BIT(q), RID0); 777 ravb_write(ndev, BIT(q), TID); 778 } 779 __napi_schedule(&priv->napi[q]); 780 } else { 781 netdev_warn(ndev, 782 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 783 ris0, ric0); 784 netdev_warn(ndev, 785 " tx status 0x%08x, tx mask 0x%08x.\n", 786 tis, tic); 787 } 788 return true; 789 } 790 return false; 791 } 792 793 static bool ravb_timestamp_interrupt(struct net_device *ndev) 794 { 795 u32 tis = ravb_read(ndev, TIS); 796 797 if (tis & TIS_TFUF) { 798 ravb_write(ndev, ~TIS_TFUF, TIS); 799 ravb_get_tx_tstamp(ndev); 800 return true; 801 } 802 return false; 803 } 804 805 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 806 { 807 struct net_device *ndev = dev_id; 808 struct ravb_private *priv = netdev_priv(ndev); 809 irqreturn_t result = IRQ_NONE; 810 u32 iss; 811 812 spin_lock(&priv->lock); 813 /* Get interrupt status */ 814 iss = ravb_read(ndev, ISS); 815 816 /* Received and transmitted interrupts */ 817 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 818 int q; 819 820 /* Timestamp updated */ 821 if (ravb_timestamp_interrupt(ndev)) 822 result = IRQ_HANDLED; 823 824 /* Network control and best effort queue RX/TX */ 825 for (q = RAVB_NC; q >= RAVB_BE; q--) { 826 if (ravb_queue_interrupt(ndev, q)) 827 result = IRQ_HANDLED; 828 } 829 } 830 831 /* E-MAC status summary */ 832 if (iss & ISS_MS) { 833 ravb_emac_interrupt_unlocked(ndev); 834 result = IRQ_HANDLED; 835 } 836 837 /* Error status summary */ 838 if (iss & ISS_ES) { 839 ravb_error_interrupt(ndev); 840 result = IRQ_HANDLED; 841 } 842 843 /* gPTP interrupt status summary */ 844 if (iss & ISS_CGIS) { 845 ravb_ptp_interrupt(ndev); 846 result = IRQ_HANDLED; 847 } 848 849 mmiowb(); 850 spin_unlock(&priv->lock); 851 return result; 852 } 853 854 /* Timestamp/Error/gPTP interrupt handler */ 855 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 856 { 857 struct net_device *ndev = dev_id; 858 struct ravb_private *priv = netdev_priv(ndev); 859 irqreturn_t result = IRQ_NONE; 860 u32 iss; 861 862 spin_lock(&priv->lock); 863 /* Get interrupt status */ 864 iss = ravb_read(ndev, ISS); 865 866 /* Timestamp updated */ 867 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 868 result = IRQ_HANDLED; 869 870 /* Error status summary */ 871 if (iss & ISS_ES) { 872 ravb_error_interrupt(ndev); 873 result = IRQ_HANDLED; 874 } 875 876 /* gPTP interrupt status summary */ 877 if (iss & ISS_CGIS) { 878 ravb_ptp_interrupt(ndev); 879 result = IRQ_HANDLED; 880 } 881 882 mmiowb(); 883 spin_unlock(&priv->lock); 884 return result; 885 } 886 887 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 888 { 889 struct net_device *ndev = dev_id; 890 struct ravb_private *priv = netdev_priv(ndev); 891 irqreturn_t result = IRQ_NONE; 892 893 spin_lock(&priv->lock); 894 895 /* Network control/Best effort queue RX/TX */ 896 if (ravb_queue_interrupt(ndev, q)) 897 result = IRQ_HANDLED; 898 899 mmiowb(); 900 spin_unlock(&priv->lock); 901 return result; 902 } 903 904 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 905 { 906 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 907 } 908 909 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 910 { 911 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 912 } 913 914 static int ravb_poll(struct napi_struct *napi, int budget) 915 { 916 struct net_device *ndev = napi->dev; 917 struct ravb_private *priv = netdev_priv(ndev); 918 unsigned long flags; 919 int q = napi - priv->napi; 920 int mask = BIT(q); 921 int quota = budget; 922 u32 ris0, tis; 923 924 for (;;) { 925 tis = ravb_read(ndev, TIS); 926 ris0 = ravb_read(ndev, RIS0); 927 if (!((ris0 & mask) || (tis & mask))) 928 break; 929 930 /* Processing RX Descriptor Ring */ 931 if (ris0 & mask) { 932 /* Clear RX interrupt */ 933 ravb_write(ndev, ~mask, RIS0); 934 if (ravb_rx(ndev, "a, q)) 935 goto out; 936 } 937 /* Processing TX Descriptor Ring */ 938 if (tis & mask) { 939 spin_lock_irqsave(&priv->lock, flags); 940 /* Clear TX interrupt */ 941 ravb_write(ndev, ~mask, TIS); 942 ravb_tx_free(ndev, q, true); 943 netif_wake_subqueue(ndev, q); 944 mmiowb(); 945 spin_unlock_irqrestore(&priv->lock, flags); 946 } 947 } 948 949 napi_complete(napi); 950 951 /* Re-enable RX/TX interrupts */ 952 spin_lock_irqsave(&priv->lock, flags); 953 if (priv->chip_id == RCAR_GEN2) { 954 ravb_modify(ndev, RIC0, mask, mask); 955 ravb_modify(ndev, TIC, mask, mask); 956 } else { 957 ravb_write(ndev, mask, RIE0); 958 ravb_write(ndev, mask, TIE); 959 } 960 mmiowb(); 961 spin_unlock_irqrestore(&priv->lock, flags); 962 963 /* Receive error message handling */ 964 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 965 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 966 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 967 ndev->stats.rx_over_errors = priv->rx_over_errors; 968 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 969 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 970 out: 971 return budget - quota; 972 } 973 974 /* PHY state control function */ 975 static void ravb_adjust_link(struct net_device *ndev) 976 { 977 struct ravb_private *priv = netdev_priv(ndev); 978 struct phy_device *phydev = ndev->phydev; 979 bool new_state = false; 980 unsigned long flags; 981 982 spin_lock_irqsave(&priv->lock, flags); 983 984 /* Disable TX and RX right over here, if E-MAC change is ignored */ 985 if (priv->no_avb_link) 986 ravb_rcv_snd_disable(ndev); 987 988 if (phydev->link) { 989 if (phydev->duplex != priv->duplex) { 990 new_state = true; 991 priv->duplex = phydev->duplex; 992 ravb_set_duplex(ndev); 993 } 994 995 if (phydev->speed != priv->speed) { 996 new_state = true; 997 priv->speed = phydev->speed; 998 ravb_set_rate(ndev); 999 } 1000 if (!priv->link) { 1001 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 1002 new_state = true; 1003 priv->link = phydev->link; 1004 } 1005 } else if (priv->link) { 1006 new_state = true; 1007 priv->link = 0; 1008 priv->speed = 0; 1009 priv->duplex = -1; 1010 } 1011 1012 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1013 if (priv->no_avb_link && phydev->link) 1014 ravb_rcv_snd_enable(ndev); 1015 1016 mmiowb(); 1017 spin_unlock_irqrestore(&priv->lock, flags); 1018 1019 if (new_state && netif_msg_link(priv)) 1020 phy_print_status(phydev); 1021 } 1022 1023 static const struct soc_device_attribute r8a7795es10[] = { 1024 { .soc_id = "r8a7795", .revision = "ES1.0", }, 1025 { /* sentinel */ } 1026 }; 1027 1028 /* PHY init function */ 1029 static int ravb_phy_init(struct net_device *ndev) 1030 { 1031 struct device_node *np = ndev->dev.parent->of_node; 1032 struct ravb_private *priv = netdev_priv(ndev); 1033 struct phy_device *phydev; 1034 struct device_node *pn; 1035 int err; 1036 1037 priv->link = 0; 1038 priv->speed = 0; 1039 priv->duplex = -1; 1040 1041 /* Try connecting to PHY */ 1042 pn = of_parse_phandle(np, "phy-handle", 0); 1043 if (!pn) { 1044 /* In the case of a fixed PHY, the DT node associated 1045 * to the PHY is the Ethernet MAC DT node. 1046 */ 1047 if (of_phy_is_fixed_link(np)) { 1048 err = of_phy_register_fixed_link(np); 1049 if (err) 1050 return err; 1051 } 1052 pn = of_node_get(np); 1053 } 1054 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, 1055 priv->phy_interface); 1056 of_node_put(pn); 1057 if (!phydev) { 1058 netdev_err(ndev, "failed to connect PHY\n"); 1059 err = -ENOENT; 1060 goto err_deregister_fixed_link; 1061 } 1062 1063 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0 1064 * at this time. 1065 */ 1066 if (soc_device_match(r8a7795es10)) { 1067 err = phy_set_max_speed(phydev, SPEED_100); 1068 if (err) { 1069 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n"); 1070 goto err_phy_disconnect; 1071 } 1072 1073 netdev_info(ndev, "limited PHY to 100Mbit/s\n"); 1074 } 1075 1076 /* 10BASE is not supported */ 1077 phydev->supported &= ~PHY_10BT_FEATURES; 1078 1079 phy_attached_info(phydev); 1080 1081 return 0; 1082 1083 err_phy_disconnect: 1084 phy_disconnect(phydev); 1085 err_deregister_fixed_link: 1086 if (of_phy_is_fixed_link(np)) 1087 of_phy_deregister_fixed_link(np); 1088 1089 return err; 1090 } 1091 1092 /* PHY control start function */ 1093 static int ravb_phy_start(struct net_device *ndev) 1094 { 1095 int error; 1096 1097 error = ravb_phy_init(ndev); 1098 if (error) 1099 return error; 1100 1101 phy_start(ndev->phydev); 1102 1103 return 0; 1104 } 1105 1106 static u32 ravb_get_msglevel(struct net_device *ndev) 1107 { 1108 struct ravb_private *priv = netdev_priv(ndev); 1109 1110 return priv->msg_enable; 1111 } 1112 1113 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1114 { 1115 struct ravb_private *priv = netdev_priv(ndev); 1116 1117 priv->msg_enable = value; 1118 } 1119 1120 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1121 "rx_queue_0_current", 1122 "tx_queue_0_current", 1123 "rx_queue_0_dirty", 1124 "tx_queue_0_dirty", 1125 "rx_queue_0_packets", 1126 "tx_queue_0_packets", 1127 "rx_queue_0_bytes", 1128 "tx_queue_0_bytes", 1129 "rx_queue_0_mcast_packets", 1130 "rx_queue_0_errors", 1131 "rx_queue_0_crc_errors", 1132 "rx_queue_0_frame_errors", 1133 "rx_queue_0_length_errors", 1134 "rx_queue_0_missed_errors", 1135 "rx_queue_0_over_errors", 1136 1137 "rx_queue_1_current", 1138 "tx_queue_1_current", 1139 "rx_queue_1_dirty", 1140 "tx_queue_1_dirty", 1141 "rx_queue_1_packets", 1142 "tx_queue_1_packets", 1143 "rx_queue_1_bytes", 1144 "tx_queue_1_bytes", 1145 "rx_queue_1_mcast_packets", 1146 "rx_queue_1_errors", 1147 "rx_queue_1_crc_errors", 1148 "rx_queue_1_frame_errors", 1149 "rx_queue_1_length_errors", 1150 "rx_queue_1_missed_errors", 1151 "rx_queue_1_over_errors", 1152 }; 1153 1154 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats) 1155 1156 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1157 { 1158 switch (sset) { 1159 case ETH_SS_STATS: 1160 return RAVB_STATS_LEN; 1161 default: 1162 return -EOPNOTSUPP; 1163 } 1164 } 1165 1166 static void ravb_get_ethtool_stats(struct net_device *ndev, 1167 struct ethtool_stats *estats, u64 *data) 1168 { 1169 struct ravb_private *priv = netdev_priv(ndev); 1170 int i = 0; 1171 int q; 1172 1173 /* Device-specific stats */ 1174 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) { 1175 struct net_device_stats *stats = &priv->stats[q]; 1176 1177 data[i++] = priv->cur_rx[q]; 1178 data[i++] = priv->cur_tx[q]; 1179 data[i++] = priv->dirty_rx[q]; 1180 data[i++] = priv->dirty_tx[q]; 1181 data[i++] = stats->rx_packets; 1182 data[i++] = stats->tx_packets; 1183 data[i++] = stats->rx_bytes; 1184 data[i++] = stats->tx_bytes; 1185 data[i++] = stats->multicast; 1186 data[i++] = stats->rx_errors; 1187 data[i++] = stats->rx_crc_errors; 1188 data[i++] = stats->rx_frame_errors; 1189 data[i++] = stats->rx_length_errors; 1190 data[i++] = stats->rx_missed_errors; 1191 data[i++] = stats->rx_over_errors; 1192 } 1193 } 1194 1195 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1196 { 1197 switch (stringset) { 1198 case ETH_SS_STATS: 1199 memcpy(data, ravb_gstrings_stats, sizeof(ravb_gstrings_stats)); 1200 break; 1201 } 1202 } 1203 1204 static void ravb_get_ringparam(struct net_device *ndev, 1205 struct ethtool_ringparam *ring) 1206 { 1207 struct ravb_private *priv = netdev_priv(ndev); 1208 1209 ring->rx_max_pending = BE_RX_RING_MAX; 1210 ring->tx_max_pending = BE_TX_RING_MAX; 1211 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1212 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1213 } 1214 1215 static int ravb_set_ringparam(struct net_device *ndev, 1216 struct ethtool_ringparam *ring) 1217 { 1218 struct ravb_private *priv = netdev_priv(ndev); 1219 int error; 1220 1221 if (ring->tx_pending > BE_TX_RING_MAX || 1222 ring->rx_pending > BE_RX_RING_MAX || 1223 ring->tx_pending < BE_TX_RING_MIN || 1224 ring->rx_pending < BE_RX_RING_MIN) 1225 return -EINVAL; 1226 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1227 return -EINVAL; 1228 1229 if (netif_running(ndev)) { 1230 netif_device_detach(ndev); 1231 /* Stop PTP Clock driver */ 1232 if (priv->chip_id == RCAR_GEN2) 1233 ravb_ptp_stop(ndev); 1234 /* Wait for DMA stopping */ 1235 error = ravb_stop_dma(ndev); 1236 if (error) { 1237 netdev_err(ndev, 1238 "cannot set ringparam! Any AVB processes are still running?\n"); 1239 return error; 1240 } 1241 synchronize_irq(ndev->irq); 1242 1243 /* Free all the skb's in the RX queue and the DMA buffers. */ 1244 ravb_ring_free(ndev, RAVB_BE); 1245 ravb_ring_free(ndev, RAVB_NC); 1246 } 1247 1248 /* Set new parameters */ 1249 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1250 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1251 1252 if (netif_running(ndev)) { 1253 error = ravb_dmac_init(ndev); 1254 if (error) { 1255 netdev_err(ndev, 1256 "%s: ravb_dmac_init() failed, error %d\n", 1257 __func__, error); 1258 return error; 1259 } 1260 1261 ravb_emac_init(ndev); 1262 1263 /* Initialise PTP Clock driver */ 1264 if (priv->chip_id == RCAR_GEN2) 1265 ravb_ptp_init(ndev, priv->pdev); 1266 1267 netif_device_attach(ndev); 1268 } 1269 1270 return 0; 1271 } 1272 1273 static int ravb_get_ts_info(struct net_device *ndev, 1274 struct ethtool_ts_info *info) 1275 { 1276 struct ravb_private *priv = netdev_priv(ndev); 1277 1278 info->so_timestamping = 1279 SOF_TIMESTAMPING_TX_SOFTWARE | 1280 SOF_TIMESTAMPING_RX_SOFTWARE | 1281 SOF_TIMESTAMPING_SOFTWARE | 1282 SOF_TIMESTAMPING_TX_HARDWARE | 1283 SOF_TIMESTAMPING_RX_HARDWARE | 1284 SOF_TIMESTAMPING_RAW_HARDWARE; 1285 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1286 info->rx_filters = 1287 (1 << HWTSTAMP_FILTER_NONE) | 1288 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1289 (1 << HWTSTAMP_FILTER_ALL); 1290 info->phc_index = ptp_clock_index(priv->ptp.clock); 1291 1292 return 0; 1293 } 1294 1295 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1296 { 1297 struct ravb_private *priv = netdev_priv(ndev); 1298 1299 wol->supported = WAKE_MAGIC; 1300 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1301 } 1302 1303 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1304 { 1305 struct ravb_private *priv = netdev_priv(ndev); 1306 1307 if (wol->wolopts & ~WAKE_MAGIC) 1308 return -EOPNOTSUPP; 1309 1310 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1311 1312 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1313 1314 return 0; 1315 } 1316 1317 static const struct ethtool_ops ravb_ethtool_ops = { 1318 .nway_reset = phy_ethtool_nway_reset, 1319 .get_msglevel = ravb_get_msglevel, 1320 .set_msglevel = ravb_set_msglevel, 1321 .get_link = ethtool_op_get_link, 1322 .get_strings = ravb_get_strings, 1323 .get_ethtool_stats = ravb_get_ethtool_stats, 1324 .get_sset_count = ravb_get_sset_count, 1325 .get_ringparam = ravb_get_ringparam, 1326 .set_ringparam = ravb_set_ringparam, 1327 .get_ts_info = ravb_get_ts_info, 1328 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1329 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1330 .get_wol = ravb_get_wol, 1331 .set_wol = ravb_set_wol, 1332 }; 1333 1334 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler, 1335 struct net_device *ndev, struct device *dev, 1336 const char *ch) 1337 { 1338 char *name; 1339 int error; 1340 1341 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); 1342 if (!name) 1343 return -ENOMEM; 1344 error = request_irq(irq, handler, 0, name, ndev); 1345 if (error) 1346 netdev_err(ndev, "cannot request IRQ %s\n", name); 1347 1348 return error; 1349 } 1350 1351 /* Network device open function for Ethernet AVB */ 1352 static int ravb_open(struct net_device *ndev) 1353 { 1354 struct ravb_private *priv = netdev_priv(ndev); 1355 struct platform_device *pdev = priv->pdev; 1356 struct device *dev = &pdev->dev; 1357 int error; 1358 1359 napi_enable(&priv->napi[RAVB_BE]); 1360 napi_enable(&priv->napi[RAVB_NC]); 1361 1362 if (priv->chip_id == RCAR_GEN2) { 1363 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, 1364 ndev->name, ndev); 1365 if (error) { 1366 netdev_err(ndev, "cannot request IRQ\n"); 1367 goto out_napi_off; 1368 } 1369 } else { 1370 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev, 1371 dev, "ch22:multi"); 1372 if (error) 1373 goto out_napi_off; 1374 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev, 1375 dev, "ch24:emac"); 1376 if (error) 1377 goto out_free_irq; 1378 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt, 1379 ndev, dev, "ch0:rx_be"); 1380 if (error) 1381 goto out_free_irq_emac; 1382 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt, 1383 ndev, dev, "ch18:tx_be"); 1384 if (error) 1385 goto out_free_irq_be_rx; 1386 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt, 1387 ndev, dev, "ch1:rx_nc"); 1388 if (error) 1389 goto out_free_irq_be_tx; 1390 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt, 1391 ndev, dev, "ch19:tx_nc"); 1392 if (error) 1393 goto out_free_irq_nc_rx; 1394 } 1395 1396 /* Device init */ 1397 error = ravb_dmac_init(ndev); 1398 if (error) 1399 goto out_free_irq_nc_tx; 1400 ravb_emac_init(ndev); 1401 1402 /* Initialise PTP Clock driver */ 1403 if (priv->chip_id == RCAR_GEN2) 1404 ravb_ptp_init(ndev, priv->pdev); 1405 1406 netif_tx_start_all_queues(ndev); 1407 1408 /* PHY control start */ 1409 error = ravb_phy_start(ndev); 1410 if (error) 1411 goto out_ptp_stop; 1412 1413 return 0; 1414 1415 out_ptp_stop: 1416 /* Stop PTP Clock driver */ 1417 if (priv->chip_id == RCAR_GEN2) 1418 ravb_ptp_stop(ndev); 1419 out_free_irq_nc_tx: 1420 if (priv->chip_id == RCAR_GEN2) 1421 goto out_free_irq; 1422 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1423 out_free_irq_nc_rx: 1424 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1425 out_free_irq_be_tx: 1426 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1427 out_free_irq_be_rx: 1428 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1429 out_free_irq_emac: 1430 free_irq(priv->emac_irq, ndev); 1431 out_free_irq: 1432 free_irq(ndev->irq, ndev); 1433 out_napi_off: 1434 napi_disable(&priv->napi[RAVB_NC]); 1435 napi_disable(&priv->napi[RAVB_BE]); 1436 return error; 1437 } 1438 1439 /* Timeout function for Ethernet AVB */ 1440 static void ravb_tx_timeout(struct net_device *ndev) 1441 { 1442 struct ravb_private *priv = netdev_priv(ndev); 1443 1444 netif_err(priv, tx_err, ndev, 1445 "transmit timed out, status %08x, resetting...\n", 1446 ravb_read(ndev, ISS)); 1447 1448 /* tx_errors count up */ 1449 ndev->stats.tx_errors++; 1450 1451 schedule_work(&priv->work); 1452 } 1453 1454 static void ravb_tx_timeout_work(struct work_struct *work) 1455 { 1456 struct ravb_private *priv = container_of(work, struct ravb_private, 1457 work); 1458 struct net_device *ndev = priv->ndev; 1459 1460 netif_tx_stop_all_queues(ndev); 1461 1462 /* Stop PTP Clock driver */ 1463 if (priv->chip_id == RCAR_GEN2) 1464 ravb_ptp_stop(ndev); 1465 1466 /* Wait for DMA stopping */ 1467 ravb_stop_dma(ndev); 1468 1469 ravb_ring_free(ndev, RAVB_BE); 1470 ravb_ring_free(ndev, RAVB_NC); 1471 1472 /* Device init */ 1473 ravb_dmac_init(ndev); 1474 ravb_emac_init(ndev); 1475 1476 /* Initialise PTP Clock driver */ 1477 if (priv->chip_id == RCAR_GEN2) 1478 ravb_ptp_init(ndev, priv->pdev); 1479 1480 netif_tx_start_all_queues(ndev); 1481 } 1482 1483 /* Packet transmit function for Ethernet AVB */ 1484 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1485 { 1486 struct ravb_private *priv = netdev_priv(ndev); 1487 u16 q = skb_get_queue_mapping(skb); 1488 struct ravb_tstamp_skb *ts_skb; 1489 struct ravb_tx_desc *desc; 1490 unsigned long flags; 1491 u32 dma_addr; 1492 void *buffer; 1493 u32 entry; 1494 u32 len; 1495 1496 spin_lock_irqsave(&priv->lock, flags); 1497 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 1498 NUM_TX_DESC) { 1499 netif_err(priv, tx_queued, ndev, 1500 "still transmitting with the full ring!\n"); 1501 netif_stop_subqueue(ndev, q); 1502 spin_unlock_irqrestore(&priv->lock, flags); 1503 return NETDEV_TX_BUSY; 1504 } 1505 1506 if (skb_put_padto(skb, ETH_ZLEN)) 1507 goto exit; 1508 1509 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC); 1510 priv->tx_skb[q][entry / NUM_TX_DESC] = skb; 1511 1512 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 1513 entry / NUM_TX_DESC * DPTR_ALIGN; 1514 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 1515 /* Zero length DMA descriptors are problematic as they seem to 1516 * terminate DMA transfers. Avoid them by simply using a length of 1517 * DPTR_ALIGN (4) when skb data is aligned to DPTR_ALIGN. 1518 * 1519 * As skb is guaranteed to have at least ETH_ZLEN (60) bytes of 1520 * data by the call to skb_put_padto() above this is safe with 1521 * respect to both the length of the first DMA descriptor (len) 1522 * overflowing the available data and the length of the second DMA 1523 * descriptor (skb->len - len) being negative. 1524 */ 1525 if (len == 0) 1526 len = DPTR_ALIGN; 1527 1528 memcpy(buffer, skb->data, len); 1529 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE); 1530 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1531 goto drop; 1532 1533 desc = &priv->tx_ring[q][entry]; 1534 desc->ds_tagl = cpu_to_le16(len); 1535 desc->dptr = cpu_to_le32(dma_addr); 1536 1537 buffer = skb->data + len; 1538 len = skb->len - len; 1539 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE); 1540 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1541 goto unmap; 1542 1543 desc++; 1544 desc->ds_tagl = cpu_to_le16(len); 1545 desc->dptr = cpu_to_le32(dma_addr); 1546 1547 /* TX timestamp required */ 1548 if (q == RAVB_NC) { 1549 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 1550 if (!ts_skb) { 1551 desc--; 1552 dma_unmap_single(ndev->dev.parent, dma_addr, len, 1553 DMA_TO_DEVICE); 1554 goto unmap; 1555 } 1556 ts_skb->skb = skb; 1557 ts_skb->tag = priv->ts_skb_tag++; 1558 priv->ts_skb_tag &= 0x3ff; 1559 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 1560 1561 /* TAG and timestamp required flag */ 1562 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1563 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 1564 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12); 1565 } 1566 1567 skb_tx_timestamp(skb); 1568 /* Descriptor type must be set after all the above writes */ 1569 dma_wmb(); 1570 desc->die_dt = DT_FEND; 1571 desc--; 1572 desc->die_dt = DT_FSTART; 1573 1574 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 1575 1576 priv->cur_tx[q] += NUM_TX_DESC; 1577 if (priv->cur_tx[q] - priv->dirty_tx[q] > 1578 (priv->num_tx_ring[q] - 1) * NUM_TX_DESC && 1579 !ravb_tx_free(ndev, q, true)) 1580 netif_stop_subqueue(ndev, q); 1581 1582 exit: 1583 mmiowb(); 1584 spin_unlock_irqrestore(&priv->lock, flags); 1585 return NETDEV_TX_OK; 1586 1587 unmap: 1588 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 1589 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 1590 drop: 1591 dev_kfree_skb_any(skb); 1592 priv->tx_skb[q][entry / NUM_TX_DESC] = NULL; 1593 goto exit; 1594 } 1595 1596 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 1597 struct net_device *sb_dev, 1598 select_queue_fallback_t fallback) 1599 { 1600 /* If skb needs TX timestamp, it is handled in network control queue */ 1601 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 1602 RAVB_BE; 1603 1604 } 1605 1606 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 1607 { 1608 struct ravb_private *priv = netdev_priv(ndev); 1609 struct net_device_stats *nstats, *stats0, *stats1; 1610 1611 nstats = &ndev->stats; 1612 stats0 = &priv->stats[RAVB_BE]; 1613 stats1 = &priv->stats[RAVB_NC]; 1614 1615 nstats->tx_dropped += ravb_read(ndev, TROCR); 1616 ravb_write(ndev, 0, TROCR); /* (write clear) */ 1617 nstats->collisions += ravb_read(ndev, CDCR); 1618 ravb_write(ndev, 0, CDCR); /* (write clear) */ 1619 nstats->tx_carrier_errors += ravb_read(ndev, LCCR); 1620 ravb_write(ndev, 0, LCCR); /* (write clear) */ 1621 1622 nstats->tx_carrier_errors += ravb_read(ndev, CERCR); 1623 ravb_write(ndev, 0, CERCR); /* (write clear) */ 1624 nstats->tx_carrier_errors += ravb_read(ndev, CEECR); 1625 ravb_write(ndev, 0, CEECR); /* (write clear) */ 1626 1627 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets; 1628 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets; 1629 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes; 1630 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes; 1631 nstats->multicast = stats0->multicast + stats1->multicast; 1632 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors; 1633 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors; 1634 nstats->rx_frame_errors = 1635 stats0->rx_frame_errors + stats1->rx_frame_errors; 1636 nstats->rx_length_errors = 1637 stats0->rx_length_errors + stats1->rx_length_errors; 1638 nstats->rx_missed_errors = 1639 stats0->rx_missed_errors + stats1->rx_missed_errors; 1640 nstats->rx_over_errors = 1641 stats0->rx_over_errors + stats1->rx_over_errors; 1642 1643 return nstats; 1644 } 1645 1646 /* Update promiscuous bit */ 1647 static void ravb_set_rx_mode(struct net_device *ndev) 1648 { 1649 struct ravb_private *priv = netdev_priv(ndev); 1650 unsigned long flags; 1651 1652 spin_lock_irqsave(&priv->lock, flags); 1653 ravb_modify(ndev, ECMR, ECMR_PRM, 1654 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 1655 mmiowb(); 1656 spin_unlock_irqrestore(&priv->lock, flags); 1657 } 1658 1659 /* Device close function for Ethernet AVB */ 1660 static int ravb_close(struct net_device *ndev) 1661 { 1662 struct device_node *np = ndev->dev.parent->of_node; 1663 struct ravb_private *priv = netdev_priv(ndev); 1664 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 1665 1666 netif_tx_stop_all_queues(ndev); 1667 1668 /* Disable interrupts by clearing the interrupt masks. */ 1669 ravb_write(ndev, 0, RIC0); 1670 ravb_write(ndev, 0, RIC2); 1671 ravb_write(ndev, 0, TIC); 1672 1673 /* Stop PTP Clock driver */ 1674 if (priv->chip_id == RCAR_GEN2) 1675 ravb_ptp_stop(ndev); 1676 1677 /* Set the config mode to stop the AVB-DMAC's processes */ 1678 if (ravb_stop_dma(ndev) < 0) 1679 netdev_err(ndev, 1680 "device will be stopped after h/w processes are done.\n"); 1681 1682 /* Clear the timestamp list */ 1683 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 1684 list_del(&ts_skb->list); 1685 kfree(ts_skb); 1686 } 1687 1688 /* PHY disconnect */ 1689 if (ndev->phydev) { 1690 phy_stop(ndev->phydev); 1691 phy_disconnect(ndev->phydev); 1692 if (of_phy_is_fixed_link(np)) 1693 of_phy_deregister_fixed_link(np); 1694 } 1695 1696 if (priv->chip_id != RCAR_GEN2) { 1697 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1698 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1699 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1700 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1701 free_irq(priv->emac_irq, ndev); 1702 } 1703 free_irq(ndev->irq, ndev); 1704 1705 napi_disable(&priv->napi[RAVB_NC]); 1706 napi_disable(&priv->napi[RAVB_BE]); 1707 1708 /* Free all the skb's in the RX queue and the DMA buffers. */ 1709 ravb_ring_free(ndev, RAVB_BE); 1710 ravb_ring_free(ndev, RAVB_NC); 1711 1712 return 0; 1713 } 1714 1715 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 1716 { 1717 struct ravb_private *priv = netdev_priv(ndev); 1718 struct hwtstamp_config config; 1719 1720 config.flags = 0; 1721 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 1722 HWTSTAMP_TX_OFF; 1723 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT) 1724 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1725 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL) 1726 config.rx_filter = HWTSTAMP_FILTER_ALL; 1727 else 1728 config.rx_filter = HWTSTAMP_FILTER_NONE; 1729 1730 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1731 -EFAULT : 0; 1732 } 1733 1734 /* Control hardware time stamping */ 1735 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 1736 { 1737 struct ravb_private *priv = netdev_priv(ndev); 1738 struct hwtstamp_config config; 1739 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 1740 u32 tstamp_tx_ctrl; 1741 1742 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 1743 return -EFAULT; 1744 1745 /* Reserved for future extensions */ 1746 if (config.flags) 1747 return -EINVAL; 1748 1749 switch (config.tx_type) { 1750 case HWTSTAMP_TX_OFF: 1751 tstamp_tx_ctrl = 0; 1752 break; 1753 case HWTSTAMP_TX_ON: 1754 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 1755 break; 1756 default: 1757 return -ERANGE; 1758 } 1759 1760 switch (config.rx_filter) { 1761 case HWTSTAMP_FILTER_NONE: 1762 tstamp_rx_ctrl = 0; 1763 break; 1764 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1765 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 1766 break; 1767 default: 1768 config.rx_filter = HWTSTAMP_FILTER_ALL; 1769 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 1770 } 1771 1772 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 1773 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 1774 1775 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1776 -EFAULT : 0; 1777 } 1778 1779 /* ioctl to device function */ 1780 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 1781 { 1782 struct phy_device *phydev = ndev->phydev; 1783 1784 if (!netif_running(ndev)) 1785 return -EINVAL; 1786 1787 if (!phydev) 1788 return -ENODEV; 1789 1790 switch (cmd) { 1791 case SIOCGHWTSTAMP: 1792 return ravb_hwtstamp_get(ndev, req); 1793 case SIOCSHWTSTAMP: 1794 return ravb_hwtstamp_set(ndev, req); 1795 } 1796 1797 return phy_mii_ioctl(phydev, req, cmd); 1798 } 1799 1800 static int ravb_change_mtu(struct net_device *ndev, int new_mtu) 1801 { 1802 if (netif_running(ndev)) 1803 return -EBUSY; 1804 1805 ndev->mtu = new_mtu; 1806 netdev_update_features(ndev); 1807 1808 return 0; 1809 } 1810 1811 static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 1812 { 1813 struct ravb_private *priv = netdev_priv(ndev); 1814 unsigned long flags; 1815 1816 spin_lock_irqsave(&priv->lock, flags); 1817 1818 /* Disable TX and RX */ 1819 ravb_rcv_snd_disable(ndev); 1820 1821 /* Modify RX Checksum setting */ 1822 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 1823 1824 /* Enable TX and RX */ 1825 ravb_rcv_snd_enable(ndev); 1826 1827 spin_unlock_irqrestore(&priv->lock, flags); 1828 } 1829 1830 static int ravb_set_features(struct net_device *ndev, 1831 netdev_features_t features) 1832 { 1833 netdev_features_t changed = ndev->features ^ features; 1834 1835 if (changed & NETIF_F_RXCSUM) 1836 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 1837 1838 ndev->features = features; 1839 1840 return 0; 1841 } 1842 1843 static const struct net_device_ops ravb_netdev_ops = { 1844 .ndo_open = ravb_open, 1845 .ndo_stop = ravb_close, 1846 .ndo_start_xmit = ravb_start_xmit, 1847 .ndo_select_queue = ravb_select_queue, 1848 .ndo_get_stats = ravb_get_stats, 1849 .ndo_set_rx_mode = ravb_set_rx_mode, 1850 .ndo_tx_timeout = ravb_tx_timeout, 1851 .ndo_do_ioctl = ravb_do_ioctl, 1852 .ndo_change_mtu = ravb_change_mtu, 1853 .ndo_validate_addr = eth_validate_addr, 1854 .ndo_set_mac_address = eth_mac_addr, 1855 .ndo_set_features = ravb_set_features, 1856 }; 1857 1858 /* MDIO bus init function */ 1859 static int ravb_mdio_init(struct ravb_private *priv) 1860 { 1861 struct platform_device *pdev = priv->pdev; 1862 struct device *dev = &pdev->dev; 1863 int error; 1864 1865 /* Bitbang init */ 1866 priv->mdiobb.ops = &bb_ops; 1867 1868 /* MII controller setting */ 1869 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 1870 if (!priv->mii_bus) 1871 return -ENOMEM; 1872 1873 /* Hook up MII support for ethtool */ 1874 priv->mii_bus->name = "ravb_mii"; 1875 priv->mii_bus->parent = dev; 1876 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1877 pdev->name, pdev->id); 1878 1879 /* Register MDIO bus */ 1880 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 1881 if (error) 1882 goto out_free_bus; 1883 1884 return 0; 1885 1886 out_free_bus: 1887 free_mdio_bitbang(priv->mii_bus); 1888 return error; 1889 } 1890 1891 /* MDIO bus release function */ 1892 static int ravb_mdio_release(struct ravb_private *priv) 1893 { 1894 /* Unregister mdio bus */ 1895 mdiobus_unregister(priv->mii_bus); 1896 1897 /* Free bitbang info */ 1898 free_mdio_bitbang(priv->mii_bus); 1899 1900 return 0; 1901 } 1902 1903 static const struct of_device_id ravb_match_table[] = { 1904 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 }, 1905 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 }, 1906 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 }, 1907 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 }, 1908 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 }, 1909 { } 1910 }; 1911 MODULE_DEVICE_TABLE(of, ravb_match_table); 1912 1913 static int ravb_set_gti(struct net_device *ndev) 1914 { 1915 struct ravb_private *priv = netdev_priv(ndev); 1916 struct device *dev = ndev->dev.parent; 1917 unsigned long rate; 1918 uint64_t inc; 1919 1920 rate = clk_get_rate(priv->clk); 1921 if (!rate) 1922 return -EINVAL; 1923 1924 inc = 1000000000ULL << 20; 1925 do_div(inc, rate); 1926 1927 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 1928 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 1929 inc, GTI_TIV_MIN, GTI_TIV_MAX); 1930 return -EINVAL; 1931 } 1932 1933 ravb_write(ndev, inc, GTI); 1934 1935 return 0; 1936 } 1937 1938 static void ravb_set_config_mode(struct net_device *ndev) 1939 { 1940 struct ravb_private *priv = netdev_priv(ndev); 1941 1942 if (priv->chip_id == RCAR_GEN2) { 1943 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 1944 /* Set CSEL value */ 1945 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 1946 } else { 1947 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG | 1948 CCC_GAC | CCC_CSEL_HPB); 1949 } 1950 } 1951 1952 /* Set tx and rx clock internal delay modes */ 1953 static void ravb_set_delay_mode(struct net_device *ndev) 1954 { 1955 struct ravb_private *priv = netdev_priv(ndev); 1956 int set = 0; 1957 1958 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1959 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) 1960 set |= APSR_DM_RDM; 1961 1962 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1963 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) 1964 set |= APSR_DM_TDM; 1965 1966 ravb_modify(ndev, APSR, APSR_DM, set); 1967 } 1968 1969 static int ravb_probe(struct platform_device *pdev) 1970 { 1971 struct device_node *np = pdev->dev.of_node; 1972 struct ravb_private *priv; 1973 enum ravb_chip_id chip_id; 1974 struct net_device *ndev; 1975 int error, irq, q; 1976 struct resource *res; 1977 int i; 1978 1979 if (!np) { 1980 dev_err(&pdev->dev, 1981 "this driver is required to be instantiated from device tree\n"); 1982 return -EINVAL; 1983 } 1984 1985 /* Get base address */ 1986 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1987 if (!res) { 1988 dev_err(&pdev->dev, "invalid resource\n"); 1989 return -EINVAL; 1990 } 1991 1992 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 1993 NUM_TX_QUEUE, NUM_RX_QUEUE); 1994 if (!ndev) 1995 return -ENOMEM; 1996 1997 ndev->features = NETIF_F_RXCSUM; 1998 ndev->hw_features = NETIF_F_RXCSUM; 1999 2000 pm_runtime_enable(&pdev->dev); 2001 pm_runtime_get_sync(&pdev->dev); 2002 2003 /* The Ether-specific entries in the device structure. */ 2004 ndev->base_addr = res->start; 2005 2006 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev); 2007 2008 if (chip_id == RCAR_GEN3) 2009 irq = platform_get_irq_byname(pdev, "ch22"); 2010 else 2011 irq = platform_get_irq(pdev, 0); 2012 if (irq < 0) { 2013 error = irq; 2014 goto out_release; 2015 } 2016 ndev->irq = irq; 2017 2018 SET_NETDEV_DEV(ndev, &pdev->dev); 2019 2020 priv = netdev_priv(ndev); 2021 priv->ndev = ndev; 2022 priv->pdev = pdev; 2023 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2024 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2025 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2026 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2027 priv->addr = devm_ioremap_resource(&pdev->dev, res); 2028 if (IS_ERR(priv->addr)) { 2029 error = PTR_ERR(priv->addr); 2030 goto out_release; 2031 } 2032 2033 spin_lock_init(&priv->lock); 2034 INIT_WORK(&priv->work, ravb_tx_timeout_work); 2035 2036 priv->phy_interface = of_get_phy_mode(np); 2037 2038 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 2039 priv->avb_link_active_low = 2040 of_property_read_bool(np, "renesas,ether-link-active-low"); 2041 2042 if (chip_id == RCAR_GEN3) { 2043 irq = platform_get_irq_byname(pdev, "ch24"); 2044 if (irq < 0) { 2045 error = irq; 2046 goto out_release; 2047 } 2048 priv->emac_irq = irq; 2049 for (i = 0; i < NUM_RX_QUEUE; i++) { 2050 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); 2051 if (irq < 0) { 2052 error = irq; 2053 goto out_release; 2054 } 2055 priv->rx_irqs[i] = irq; 2056 } 2057 for (i = 0; i < NUM_TX_QUEUE; i++) { 2058 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); 2059 if (irq < 0) { 2060 error = irq; 2061 goto out_release; 2062 } 2063 priv->tx_irqs[i] = irq; 2064 } 2065 } 2066 2067 priv->chip_id = chip_id; 2068 2069 priv->clk = devm_clk_get(&pdev->dev, NULL); 2070 if (IS_ERR(priv->clk)) { 2071 error = PTR_ERR(priv->clk); 2072 goto out_release; 2073 } 2074 2075 ndev->max_mtu = 2048 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 2076 ndev->min_mtu = ETH_MIN_MTU; 2077 2078 /* Set function */ 2079 ndev->netdev_ops = &ravb_netdev_ops; 2080 ndev->ethtool_ops = &ravb_ethtool_ops; 2081 2082 /* Set AVB config mode */ 2083 ravb_set_config_mode(ndev); 2084 2085 /* Set GTI value */ 2086 error = ravb_set_gti(ndev); 2087 if (error) 2088 goto out_release; 2089 2090 /* Request GTI loading */ 2091 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2092 2093 if (priv->chip_id != RCAR_GEN2) 2094 ravb_set_delay_mode(ndev); 2095 2096 /* Allocate descriptor base address table */ 2097 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 2098 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 2099 &priv->desc_bat_dma, GFP_KERNEL); 2100 if (!priv->desc_bat) { 2101 dev_err(&pdev->dev, 2102 "Cannot allocate desc base address table (size %d bytes)\n", 2103 priv->desc_bat_size); 2104 error = -ENOMEM; 2105 goto out_release; 2106 } 2107 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 2108 priv->desc_bat[q].die_dt = DT_EOS; 2109 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2110 2111 /* Initialise HW timestamp list */ 2112 INIT_LIST_HEAD(&priv->ts_skb_list); 2113 2114 /* Initialise PTP Clock driver */ 2115 if (chip_id != RCAR_GEN2) 2116 ravb_ptp_init(ndev, pdev); 2117 2118 /* Debug message level */ 2119 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 2120 2121 /* Read and set MAC address */ 2122 ravb_read_mac_address(ndev, of_get_mac_address(np)); 2123 if (!is_valid_ether_addr(ndev->dev_addr)) { 2124 dev_warn(&pdev->dev, 2125 "no valid MAC address supplied, using a random one\n"); 2126 eth_hw_addr_random(ndev); 2127 } 2128 2129 /* MDIO bus init */ 2130 error = ravb_mdio_init(priv); 2131 if (error) { 2132 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 2133 goto out_dma_free; 2134 } 2135 2136 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64); 2137 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64); 2138 2139 /* Network device register */ 2140 error = register_netdev(ndev); 2141 if (error) 2142 goto out_napi_del; 2143 2144 device_set_wakeup_capable(&pdev->dev, 1); 2145 2146 /* Print device information */ 2147 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 2148 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2149 2150 platform_set_drvdata(pdev, ndev); 2151 2152 return 0; 2153 2154 out_napi_del: 2155 netif_napi_del(&priv->napi[RAVB_NC]); 2156 netif_napi_del(&priv->napi[RAVB_BE]); 2157 ravb_mdio_release(priv); 2158 out_dma_free: 2159 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2160 priv->desc_bat_dma); 2161 2162 /* Stop PTP Clock driver */ 2163 if (chip_id != RCAR_GEN2) 2164 ravb_ptp_stop(ndev); 2165 out_release: 2166 free_netdev(ndev); 2167 2168 pm_runtime_put(&pdev->dev); 2169 pm_runtime_disable(&pdev->dev); 2170 return error; 2171 } 2172 2173 static int ravb_remove(struct platform_device *pdev) 2174 { 2175 struct net_device *ndev = platform_get_drvdata(pdev); 2176 struct ravb_private *priv = netdev_priv(ndev); 2177 2178 /* Stop PTP Clock driver */ 2179 if (priv->chip_id != RCAR_GEN2) 2180 ravb_ptp_stop(ndev); 2181 2182 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2183 priv->desc_bat_dma); 2184 /* Set reset mode */ 2185 ravb_write(ndev, CCC_OPC_RESET, CCC); 2186 pm_runtime_put_sync(&pdev->dev); 2187 unregister_netdev(ndev); 2188 netif_napi_del(&priv->napi[RAVB_NC]); 2189 netif_napi_del(&priv->napi[RAVB_BE]); 2190 ravb_mdio_release(priv); 2191 pm_runtime_disable(&pdev->dev); 2192 free_netdev(ndev); 2193 platform_set_drvdata(pdev, NULL); 2194 2195 return 0; 2196 } 2197 2198 static int ravb_wol_setup(struct net_device *ndev) 2199 { 2200 struct ravb_private *priv = netdev_priv(ndev); 2201 2202 /* Disable interrupts by clearing the interrupt masks. */ 2203 ravb_write(ndev, 0, RIC0); 2204 ravb_write(ndev, 0, RIC2); 2205 ravb_write(ndev, 0, TIC); 2206 2207 /* Only allow ECI interrupts */ 2208 synchronize_irq(priv->emac_irq); 2209 napi_disable(&priv->napi[RAVB_NC]); 2210 napi_disable(&priv->napi[RAVB_BE]); 2211 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 2212 2213 /* Enable MagicPacket */ 2214 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 2215 2216 return enable_irq_wake(priv->emac_irq); 2217 } 2218 2219 static int ravb_wol_restore(struct net_device *ndev) 2220 { 2221 struct ravb_private *priv = netdev_priv(ndev); 2222 int ret; 2223 2224 napi_enable(&priv->napi[RAVB_NC]); 2225 napi_enable(&priv->napi[RAVB_BE]); 2226 2227 /* Disable MagicPacket */ 2228 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 2229 2230 ret = ravb_close(ndev); 2231 if (ret < 0) 2232 return ret; 2233 2234 return disable_irq_wake(priv->emac_irq); 2235 } 2236 2237 static int __maybe_unused ravb_suspend(struct device *dev) 2238 { 2239 struct net_device *ndev = dev_get_drvdata(dev); 2240 struct ravb_private *priv = netdev_priv(ndev); 2241 int ret; 2242 2243 if (!netif_running(ndev)) 2244 return 0; 2245 2246 netif_device_detach(ndev); 2247 2248 if (priv->wol_enabled) 2249 ret = ravb_wol_setup(ndev); 2250 else 2251 ret = ravb_close(ndev); 2252 2253 return ret; 2254 } 2255 2256 static int __maybe_unused ravb_resume(struct device *dev) 2257 { 2258 struct net_device *ndev = dev_get_drvdata(dev); 2259 struct ravb_private *priv = netdev_priv(ndev); 2260 int ret = 0; 2261 2262 /* If WoL is enabled set reset mode to rearm the WoL logic */ 2263 if (priv->wol_enabled) 2264 ravb_write(ndev, CCC_OPC_RESET, CCC); 2265 2266 /* All register have been reset to default values. 2267 * Restore all registers which where setup at probe time and 2268 * reopen device if it was running before system suspended. 2269 */ 2270 2271 /* Set AVB config mode */ 2272 ravb_set_config_mode(ndev); 2273 2274 /* Set GTI value */ 2275 ret = ravb_set_gti(ndev); 2276 if (ret) 2277 return ret; 2278 2279 /* Request GTI loading */ 2280 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2281 2282 if (priv->chip_id != RCAR_GEN2) 2283 ravb_set_delay_mode(ndev); 2284 2285 /* Restore descriptor base address table */ 2286 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2287 2288 if (netif_running(ndev)) { 2289 if (priv->wol_enabled) { 2290 ret = ravb_wol_restore(ndev); 2291 if (ret) 2292 return ret; 2293 } 2294 ret = ravb_open(ndev); 2295 if (ret < 0) 2296 return ret; 2297 netif_device_attach(ndev); 2298 } 2299 2300 return ret; 2301 } 2302 2303 static int __maybe_unused ravb_runtime_nop(struct device *dev) 2304 { 2305 /* Runtime PM callback shared between ->runtime_suspend() 2306 * and ->runtime_resume(). Simply returns success. 2307 * 2308 * This driver re-initializes all registers after 2309 * pm_runtime_get_sync() anyway so there is no need 2310 * to save and restore registers here. 2311 */ 2312 return 0; 2313 } 2314 2315 static const struct dev_pm_ops ravb_dev_pm_ops = { 2316 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 2317 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL) 2318 }; 2319 2320 static struct platform_driver ravb_driver = { 2321 .probe = ravb_probe, 2322 .remove = ravb_remove, 2323 .driver = { 2324 .name = "ravb", 2325 .pm = &ravb_dev_pm_ops, 2326 .of_match_table = ravb_match_table, 2327 }, 2328 }; 2329 2330 module_platform_driver(ravb_driver); 2331 2332 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 2333 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 2334 MODULE_LICENSE("GPL v2"); 2335