1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet AVB device driver 3 * 4 * Copyright (C) 2014-2019 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * Based on the SuperH Ethernet driver 9 */ 10 11 #include <linux/cache.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_vlan.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/module.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/of.h> 24 #include <linux/of_mdio.h> 25 #include <linux/of_net.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/slab.h> 29 #include <linux/spinlock.h> 30 #include <linux/reset.h> 31 #include <linux/math64.h> 32 33 #include "ravb.h" 34 35 #define RAVB_DEF_MSG_ENABLE \ 36 (NETIF_MSG_LINK | \ 37 NETIF_MSG_TIMER | \ 38 NETIF_MSG_RX_ERR | \ 39 NETIF_MSG_TX_ERR) 40 41 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = { 42 "ch0", /* RAVB_BE */ 43 "ch1", /* RAVB_NC */ 44 }; 45 46 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = { 47 "ch18", /* RAVB_BE */ 48 "ch19", /* RAVB_NC */ 49 }; 50 51 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 52 u32 set) 53 { 54 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 55 } 56 57 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 58 { 59 int i; 60 61 for (i = 0; i < 10000; i++) { 62 if ((ravb_read(ndev, reg) & mask) == value) 63 return 0; 64 udelay(10); 65 } 66 return -ETIMEDOUT; 67 } 68 69 static int ravb_set_opmode(struct net_device *ndev, u32 opmode) 70 { 71 u32 csr_ops = 1U << (opmode & CCC_OPC); 72 u32 ccc_mask = CCC_OPC; 73 int error; 74 75 /* If gPTP active in config mode is supported it needs to be configured 76 * along with CSEL and operating mode in the same access. This is a 77 * hardware limitation. 78 */ 79 if (opmode & CCC_GAC) 80 ccc_mask |= CCC_GAC | CCC_CSEL; 81 82 /* Set operating mode */ 83 ravb_modify(ndev, CCC, ccc_mask, opmode); 84 /* Check if the operating mode is changed to the requested one */ 85 error = ravb_wait(ndev, CSR, CSR_OPS, csr_ops); 86 if (error) { 87 netdev_err(ndev, "failed to switch device to requested mode (%u)\n", 88 opmode & CCC_OPC); 89 } 90 91 return error; 92 } 93 94 static void ravb_set_rate_gbeth(struct net_device *ndev) 95 { 96 struct ravb_private *priv = netdev_priv(ndev); 97 98 switch (priv->speed) { 99 case 10: /* 10BASE */ 100 ravb_write(ndev, GBETH_GECMR_SPEED_10, GECMR); 101 break; 102 case 100: /* 100BASE */ 103 ravb_write(ndev, GBETH_GECMR_SPEED_100, GECMR); 104 break; 105 case 1000: /* 1000BASE */ 106 ravb_write(ndev, GBETH_GECMR_SPEED_1000, GECMR); 107 break; 108 } 109 } 110 111 static void ravb_set_rate_rcar(struct net_device *ndev) 112 { 113 struct ravb_private *priv = netdev_priv(ndev); 114 115 switch (priv->speed) { 116 case 100: /* 100BASE */ 117 ravb_write(ndev, GECMR_SPEED_100, GECMR); 118 break; 119 case 1000: /* 1000BASE */ 120 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 121 break; 122 } 123 } 124 125 static void ravb_set_buffer_align(struct sk_buff *skb) 126 { 127 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 128 129 if (reserve) 130 skb_reserve(skb, RAVB_ALIGN - reserve); 131 } 132 133 /* Get MAC address from the MAC address registers 134 * 135 * Ethernet AVB device doesn't have ROM for MAC address. 136 * This function gets the MAC address that was used by a bootloader. 137 */ 138 static void ravb_read_mac_address(struct device_node *np, 139 struct net_device *ndev) 140 { 141 int ret; 142 143 ret = of_get_ethdev_address(np, ndev); 144 if (ret) { 145 u32 mahr = ravb_read(ndev, MAHR); 146 u32 malr = ravb_read(ndev, MALR); 147 u8 addr[ETH_ALEN]; 148 149 addr[0] = (mahr >> 24) & 0xFF; 150 addr[1] = (mahr >> 16) & 0xFF; 151 addr[2] = (mahr >> 8) & 0xFF; 152 addr[3] = (mahr >> 0) & 0xFF; 153 addr[4] = (malr >> 8) & 0xFF; 154 addr[5] = (malr >> 0) & 0xFF; 155 eth_hw_addr_set(ndev, addr); 156 } 157 } 158 159 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 160 { 161 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 162 mdiobb); 163 164 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 165 } 166 167 /* MDC pin control */ 168 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 169 { 170 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 171 } 172 173 /* Data I/O pin control */ 174 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 175 { 176 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 177 } 178 179 /* Set data bit */ 180 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 181 { 182 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 183 } 184 185 /* Get data bit */ 186 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 187 { 188 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 189 mdiobb); 190 191 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 192 } 193 194 /* MDIO bus control struct */ 195 static const struct mdiobb_ops bb_ops = { 196 .owner = THIS_MODULE, 197 .set_mdc = ravb_set_mdc, 198 .set_mdio_dir = ravb_set_mdio_dir, 199 .set_mdio_data = ravb_set_mdio_data, 200 .get_mdio_data = ravb_get_mdio_data, 201 }; 202 203 /* Free TX skb function for AVB-IP */ 204 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 205 { 206 struct ravb_private *priv = netdev_priv(ndev); 207 struct net_device_stats *stats = &priv->stats[q]; 208 unsigned int num_tx_desc = priv->num_tx_desc; 209 struct ravb_tx_desc *desc; 210 unsigned int entry; 211 int free_num = 0; 212 u32 size; 213 214 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 215 bool txed; 216 217 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 218 num_tx_desc); 219 desc = &priv->tx_ring[q][entry]; 220 txed = desc->die_dt == DT_FEMPTY; 221 if (free_txed_only && !txed) 222 break; 223 /* Descriptor type must be checked before all other reads */ 224 dma_rmb(); 225 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 226 /* Free the original skb. */ 227 if (priv->tx_skb[q][entry / num_tx_desc]) { 228 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 229 size, DMA_TO_DEVICE); 230 /* Last packet descriptor? */ 231 if (entry % num_tx_desc == num_tx_desc - 1) { 232 entry /= num_tx_desc; 233 dev_kfree_skb_any(priv->tx_skb[q][entry]); 234 priv->tx_skb[q][entry] = NULL; 235 if (txed) 236 stats->tx_packets++; 237 } 238 free_num++; 239 } 240 if (txed) 241 stats->tx_bytes += size; 242 desc->die_dt = DT_EEMPTY; 243 } 244 return free_num; 245 } 246 247 static void ravb_rx_ring_free_gbeth(struct net_device *ndev, int q) 248 { 249 struct ravb_private *priv = netdev_priv(ndev); 250 unsigned int ring_size; 251 unsigned int i; 252 253 if (!priv->gbeth_rx_ring) 254 return; 255 256 for (i = 0; i < priv->num_rx_ring[q]; i++) { 257 struct ravb_rx_desc *desc = &priv->gbeth_rx_ring[i]; 258 259 if (!dma_mapping_error(ndev->dev.parent, 260 le32_to_cpu(desc->dptr))) 261 dma_unmap_single(ndev->dev.parent, 262 le32_to_cpu(desc->dptr), 263 GBETH_RX_BUFF_MAX, 264 DMA_FROM_DEVICE); 265 } 266 ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1); 267 dma_free_coherent(ndev->dev.parent, ring_size, priv->gbeth_rx_ring, 268 priv->rx_desc_dma[q]); 269 priv->gbeth_rx_ring = NULL; 270 } 271 272 static void ravb_rx_ring_free_rcar(struct net_device *ndev, int q) 273 { 274 struct ravb_private *priv = netdev_priv(ndev); 275 unsigned int ring_size; 276 unsigned int i; 277 278 if (!priv->rx_ring[q]) 279 return; 280 281 for (i = 0; i < priv->num_rx_ring[q]; i++) { 282 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i]; 283 284 if (!dma_mapping_error(ndev->dev.parent, 285 le32_to_cpu(desc->dptr))) 286 dma_unmap_single(ndev->dev.parent, 287 le32_to_cpu(desc->dptr), 288 RX_BUF_SZ, 289 DMA_FROM_DEVICE); 290 } 291 ring_size = sizeof(struct ravb_ex_rx_desc) * 292 (priv->num_rx_ring[q] + 1); 293 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], 294 priv->rx_desc_dma[q]); 295 priv->rx_ring[q] = NULL; 296 } 297 298 /* Free skb's and DMA buffers for Ethernet AVB */ 299 static void ravb_ring_free(struct net_device *ndev, int q) 300 { 301 struct ravb_private *priv = netdev_priv(ndev); 302 const struct ravb_hw_info *info = priv->info; 303 unsigned int num_tx_desc = priv->num_tx_desc; 304 unsigned int ring_size; 305 unsigned int i; 306 307 info->rx_ring_free(ndev, q); 308 309 if (priv->tx_ring[q]) { 310 ravb_tx_free(ndev, q, false); 311 312 ring_size = sizeof(struct ravb_tx_desc) * 313 (priv->num_tx_ring[q] * num_tx_desc + 1); 314 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 315 priv->tx_desc_dma[q]); 316 priv->tx_ring[q] = NULL; 317 } 318 319 /* Free RX skb ringbuffer */ 320 if (priv->rx_skb[q]) { 321 for (i = 0; i < priv->num_rx_ring[q]; i++) 322 dev_kfree_skb(priv->rx_skb[q][i]); 323 } 324 kfree(priv->rx_skb[q]); 325 priv->rx_skb[q] = NULL; 326 327 /* Free aligned TX buffers */ 328 kfree(priv->tx_align[q]); 329 priv->tx_align[q] = NULL; 330 331 /* Free TX skb ringbuffer. 332 * SKBs are freed by ravb_tx_free() call above. 333 */ 334 kfree(priv->tx_skb[q]); 335 priv->tx_skb[q] = NULL; 336 } 337 338 static void ravb_rx_ring_format_gbeth(struct net_device *ndev, int q) 339 { 340 struct ravb_private *priv = netdev_priv(ndev); 341 struct ravb_rx_desc *rx_desc; 342 unsigned int rx_ring_size; 343 dma_addr_t dma_addr; 344 unsigned int i; 345 346 rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 347 memset(priv->gbeth_rx_ring, 0, rx_ring_size); 348 /* Build RX ring buffer */ 349 for (i = 0; i < priv->num_rx_ring[q]; i++) { 350 /* RX descriptor */ 351 rx_desc = &priv->gbeth_rx_ring[i]; 352 rx_desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE); 353 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 354 GBETH_RX_BUFF_MAX, 355 DMA_FROM_DEVICE); 356 /* We just set the data size to 0 for a failed mapping which 357 * should prevent DMA from happening... 358 */ 359 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 360 rx_desc->ds_cc = cpu_to_le16(0); 361 rx_desc->dptr = cpu_to_le32(dma_addr); 362 rx_desc->die_dt = DT_FEMPTY; 363 } 364 rx_desc = &priv->gbeth_rx_ring[i]; 365 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 366 rx_desc->die_dt = DT_LINKFIX; /* type */ 367 } 368 369 static void ravb_rx_ring_format_rcar(struct net_device *ndev, int q) 370 { 371 struct ravb_private *priv = netdev_priv(ndev); 372 struct ravb_ex_rx_desc *rx_desc; 373 unsigned int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 374 dma_addr_t dma_addr; 375 unsigned int i; 376 377 memset(priv->rx_ring[q], 0, rx_ring_size); 378 /* Build RX ring buffer */ 379 for (i = 0; i < priv->num_rx_ring[q]; i++) { 380 /* RX descriptor */ 381 rx_desc = &priv->rx_ring[q][i]; 382 rx_desc->ds_cc = cpu_to_le16(RX_BUF_SZ); 383 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 384 RX_BUF_SZ, 385 DMA_FROM_DEVICE); 386 /* We just set the data size to 0 for a failed mapping which 387 * should prevent DMA from happening... 388 */ 389 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 390 rx_desc->ds_cc = cpu_to_le16(0); 391 rx_desc->dptr = cpu_to_le32(dma_addr); 392 rx_desc->die_dt = DT_FEMPTY; 393 } 394 rx_desc = &priv->rx_ring[q][i]; 395 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 396 rx_desc->die_dt = DT_LINKFIX; /* type */ 397 } 398 399 /* Format skb and descriptor buffer for Ethernet AVB */ 400 static void ravb_ring_format(struct net_device *ndev, int q) 401 { 402 struct ravb_private *priv = netdev_priv(ndev); 403 const struct ravb_hw_info *info = priv->info; 404 unsigned int num_tx_desc = priv->num_tx_desc; 405 struct ravb_tx_desc *tx_desc; 406 struct ravb_desc *desc; 407 unsigned int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 408 num_tx_desc; 409 unsigned int i; 410 411 priv->cur_rx[q] = 0; 412 priv->cur_tx[q] = 0; 413 priv->dirty_rx[q] = 0; 414 priv->dirty_tx[q] = 0; 415 416 info->rx_ring_format(ndev, q); 417 418 memset(priv->tx_ring[q], 0, tx_ring_size); 419 /* Build TX ring buffer */ 420 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 421 i++, tx_desc++) { 422 tx_desc->die_dt = DT_EEMPTY; 423 if (num_tx_desc > 1) { 424 tx_desc++; 425 tx_desc->die_dt = DT_EEMPTY; 426 } 427 } 428 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 429 tx_desc->die_dt = DT_LINKFIX; /* type */ 430 431 /* RX descriptor base address for best effort */ 432 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 433 desc->die_dt = DT_LINKFIX; /* type */ 434 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 435 436 /* TX descriptor base address for best effort */ 437 desc = &priv->desc_bat[q]; 438 desc->die_dt = DT_LINKFIX; /* type */ 439 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 440 } 441 442 static void *ravb_alloc_rx_desc_gbeth(struct net_device *ndev, int q) 443 { 444 struct ravb_private *priv = netdev_priv(ndev); 445 unsigned int ring_size; 446 447 ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1); 448 449 priv->gbeth_rx_ring = dma_alloc_coherent(ndev->dev.parent, ring_size, 450 &priv->rx_desc_dma[q], 451 GFP_KERNEL); 452 return priv->gbeth_rx_ring; 453 } 454 455 static void *ravb_alloc_rx_desc_rcar(struct net_device *ndev, int q) 456 { 457 struct ravb_private *priv = netdev_priv(ndev); 458 unsigned int ring_size; 459 460 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); 461 462 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 463 &priv->rx_desc_dma[q], 464 GFP_KERNEL); 465 return priv->rx_ring[q]; 466 } 467 468 /* Init skb and descriptor buffer for Ethernet AVB */ 469 static int ravb_ring_init(struct net_device *ndev, int q) 470 { 471 struct ravb_private *priv = netdev_priv(ndev); 472 const struct ravb_hw_info *info = priv->info; 473 unsigned int num_tx_desc = priv->num_tx_desc; 474 unsigned int ring_size; 475 struct sk_buff *skb; 476 unsigned int i; 477 478 /* Allocate RX and TX skb rings */ 479 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 480 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 481 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 482 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 483 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 484 goto error; 485 486 for (i = 0; i < priv->num_rx_ring[q]; i++) { 487 skb = __netdev_alloc_skb(ndev, info->max_rx_len, GFP_KERNEL); 488 if (!skb) 489 goto error; 490 ravb_set_buffer_align(skb); 491 priv->rx_skb[q][i] = skb; 492 } 493 494 if (num_tx_desc > 1) { 495 /* Allocate rings for the aligned buffers */ 496 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 497 DPTR_ALIGN - 1, GFP_KERNEL); 498 if (!priv->tx_align[q]) 499 goto error; 500 } 501 502 /* Allocate all RX descriptors. */ 503 if (!info->alloc_rx_desc(ndev, q)) 504 goto error; 505 506 priv->dirty_rx[q] = 0; 507 508 /* Allocate all TX descriptors. */ 509 ring_size = sizeof(struct ravb_tx_desc) * 510 (priv->num_tx_ring[q] * num_tx_desc + 1); 511 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 512 &priv->tx_desc_dma[q], 513 GFP_KERNEL); 514 if (!priv->tx_ring[q]) 515 goto error; 516 517 return 0; 518 519 error: 520 ravb_ring_free(ndev, q); 521 522 return -ENOMEM; 523 } 524 525 static void ravb_emac_init_gbeth(struct net_device *ndev) 526 { 527 struct ravb_private *priv = netdev_priv(ndev); 528 529 if (priv->phy_interface == PHY_INTERFACE_MODE_MII) { 530 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35); 531 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0); 532 } else { 533 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_RGMII, CXR35); 534 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 535 CXR31_SEL_LINK0); 536 } 537 538 /* Receive frame limit set register */ 539 ravb_write(ndev, GBETH_RX_BUFF_MAX + ETH_FCS_LEN, RFLR); 540 541 /* EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through */ 542 ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) | 543 ECMR_TE | ECMR_RE | ECMR_RCPT | 544 ECMR_TXF | ECMR_RXF, ECMR); 545 546 ravb_set_rate_gbeth(ndev); 547 548 /* Set MAC address */ 549 ravb_write(ndev, 550 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 551 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 552 ravb_write(ndev, (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 553 554 /* E-MAC status register clear */ 555 ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR); 556 ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0); 557 558 /* E-MAC interrupt enable register */ 559 ravb_write(ndev, ECSIPR_ICDIP, ECSIPR); 560 } 561 562 static void ravb_emac_init_rcar(struct net_device *ndev) 563 { 564 /* Receive frame limit set register */ 565 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 566 567 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 568 ravb_write(ndev, ECMR_ZPF | ECMR_DM | 569 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 570 ECMR_TE | ECMR_RE, ECMR); 571 572 ravb_set_rate_rcar(ndev); 573 574 /* Set MAC address */ 575 ravb_write(ndev, 576 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 577 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 578 ravb_write(ndev, 579 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 580 581 /* E-MAC status register clear */ 582 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 583 584 /* E-MAC interrupt enable register */ 585 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 586 } 587 588 /* E-MAC init function */ 589 static void ravb_emac_init(struct net_device *ndev) 590 { 591 struct ravb_private *priv = netdev_priv(ndev); 592 const struct ravb_hw_info *info = priv->info; 593 594 info->emac_init(ndev); 595 } 596 597 static int ravb_dmac_init_gbeth(struct net_device *ndev) 598 { 599 int error; 600 601 error = ravb_ring_init(ndev, RAVB_BE); 602 if (error) 603 return error; 604 605 /* Descriptor format */ 606 ravb_ring_format(ndev, RAVB_BE); 607 608 /* Set DMAC RX */ 609 ravb_write(ndev, 0x60000000, RCR); 610 611 /* Set Max Frame Length (RTC) */ 612 ravb_write(ndev, 0x7ffc0000 | GBETH_RX_BUFF_MAX, RTC); 613 614 /* Set FIFO size */ 615 ravb_write(ndev, 0x00222200, TGC); 616 617 ravb_write(ndev, 0, TCCR); 618 619 /* Frame receive */ 620 ravb_write(ndev, RIC0_FRE0, RIC0); 621 /* Disable FIFO full warning */ 622 ravb_write(ndev, 0x0, RIC1); 623 /* Receive FIFO full error, descriptor empty */ 624 ravb_write(ndev, RIC2_QFE0 | RIC2_RFFE, RIC2); 625 626 ravb_write(ndev, TIC_FTE0, TIC); 627 628 return 0; 629 } 630 631 static int ravb_dmac_init_rcar(struct net_device *ndev) 632 { 633 struct ravb_private *priv = netdev_priv(ndev); 634 const struct ravb_hw_info *info = priv->info; 635 int error; 636 637 error = ravb_ring_init(ndev, RAVB_BE); 638 if (error) 639 return error; 640 error = ravb_ring_init(ndev, RAVB_NC); 641 if (error) { 642 ravb_ring_free(ndev, RAVB_BE); 643 return error; 644 } 645 646 /* Descriptor format */ 647 ravb_ring_format(ndev, RAVB_BE); 648 ravb_ring_format(ndev, RAVB_NC); 649 650 /* Set AVB RX */ 651 ravb_write(ndev, 652 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 653 654 /* Set FIFO size */ 655 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC); 656 657 /* Timestamp enable */ 658 ravb_write(ndev, TCCR_TFEN, TCCR); 659 660 /* Interrupt init: */ 661 if (info->multi_irqs) { 662 /* Clear DIL.DPLx */ 663 ravb_write(ndev, 0, DIL); 664 /* Set queue specific interrupt */ 665 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 666 } 667 /* Frame receive */ 668 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 669 /* Disable FIFO full warning */ 670 ravb_write(ndev, 0, RIC1); 671 /* Receive FIFO full error, descriptor empty */ 672 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 673 /* Frame transmitted, timestamp FIFO updated */ 674 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 675 676 return 0; 677 } 678 679 /* Device init function for Ethernet AVB */ 680 static int ravb_dmac_init(struct net_device *ndev) 681 { 682 struct ravb_private *priv = netdev_priv(ndev); 683 const struct ravb_hw_info *info = priv->info; 684 int error; 685 686 /* Set CONFIG mode */ 687 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 688 if (error) 689 return error; 690 691 error = info->dmac_init(ndev); 692 if (error) 693 return error; 694 695 /* Setting the control will start the AVB-DMAC process. */ 696 return ravb_set_opmode(ndev, CCC_OPC_OPERATION); 697 } 698 699 static void ravb_get_tx_tstamp(struct net_device *ndev) 700 { 701 struct ravb_private *priv = netdev_priv(ndev); 702 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 703 struct skb_shared_hwtstamps shhwtstamps; 704 struct sk_buff *skb; 705 struct timespec64 ts; 706 u16 tag, tfa_tag; 707 int count; 708 u32 tfa2; 709 710 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 711 while (count--) { 712 tfa2 = ravb_read(ndev, TFA2); 713 tfa_tag = (tfa2 & TFA2_TST) >> 16; 714 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 715 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 716 ravb_read(ndev, TFA1); 717 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 718 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 719 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 720 list) { 721 skb = ts_skb->skb; 722 tag = ts_skb->tag; 723 list_del(&ts_skb->list); 724 kfree(ts_skb); 725 if (tag == tfa_tag) { 726 skb_tstamp_tx(skb, &shhwtstamps); 727 dev_consume_skb_any(skb); 728 break; 729 } else { 730 dev_kfree_skb_any(skb); 731 } 732 } 733 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 734 } 735 } 736 737 static void ravb_rx_csum(struct sk_buff *skb) 738 { 739 u8 *hw_csum; 740 741 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes 742 * appended to packet data 743 */ 744 if (unlikely(skb->len < sizeof(__sum16))) 745 return; 746 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); 747 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 748 skb->ip_summed = CHECKSUM_COMPLETE; 749 skb_trim(skb, skb->len - sizeof(__sum16)); 750 } 751 752 static struct sk_buff *ravb_get_skb_gbeth(struct net_device *ndev, int entry, 753 struct ravb_rx_desc *desc) 754 { 755 struct ravb_private *priv = netdev_priv(ndev); 756 struct sk_buff *skb; 757 758 skb = priv->rx_skb[RAVB_BE][entry]; 759 priv->rx_skb[RAVB_BE][entry] = NULL; 760 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 761 ALIGN(GBETH_RX_BUFF_MAX, 16), DMA_FROM_DEVICE); 762 763 return skb; 764 } 765 766 /* Packet receive function for Gigabit Ethernet */ 767 static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q) 768 { 769 struct ravb_private *priv = netdev_priv(ndev); 770 const struct ravb_hw_info *info = priv->info; 771 struct net_device_stats *stats; 772 struct ravb_rx_desc *desc; 773 struct sk_buff *skb; 774 dma_addr_t dma_addr; 775 int rx_packets = 0; 776 u8 desc_status; 777 u16 pkt_len; 778 u8 die_dt; 779 int entry; 780 int limit; 781 int i; 782 783 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 784 limit = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q]; 785 stats = &priv->stats[q]; 786 787 desc = &priv->gbeth_rx_ring[entry]; 788 for (i = 0; i < limit && rx_packets < *quota && desc->die_dt != DT_FEMPTY; i++) { 789 /* Descriptor type must be checked before all other reads */ 790 dma_rmb(); 791 desc_status = desc->msc; 792 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 793 794 /* We use 0-byte descriptors to mark the DMA mapping errors */ 795 if (!pkt_len) 796 continue; 797 798 if (desc_status & MSC_MC) 799 stats->multicast++; 800 801 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | MSC_CEEF)) { 802 stats->rx_errors++; 803 if (desc_status & MSC_CRC) 804 stats->rx_crc_errors++; 805 if (desc_status & MSC_RFE) 806 stats->rx_frame_errors++; 807 if (desc_status & (MSC_RTLF | MSC_RTSF)) 808 stats->rx_length_errors++; 809 if (desc_status & MSC_CEEF) 810 stats->rx_missed_errors++; 811 } else { 812 die_dt = desc->die_dt & 0xF0; 813 switch (die_dt) { 814 case DT_FSINGLE: 815 skb = ravb_get_skb_gbeth(ndev, entry, desc); 816 skb_put(skb, pkt_len); 817 skb->protocol = eth_type_trans(skb, ndev); 818 napi_gro_receive(&priv->napi[q], skb); 819 rx_packets++; 820 stats->rx_bytes += pkt_len; 821 break; 822 case DT_FSTART: 823 priv->rx_1st_skb = ravb_get_skb_gbeth(ndev, entry, desc); 824 skb_put(priv->rx_1st_skb, pkt_len); 825 break; 826 case DT_FMID: 827 skb = ravb_get_skb_gbeth(ndev, entry, desc); 828 skb_copy_to_linear_data_offset(priv->rx_1st_skb, 829 priv->rx_1st_skb->len, 830 skb->data, 831 pkt_len); 832 skb_put(priv->rx_1st_skb, pkt_len); 833 dev_kfree_skb(skb); 834 break; 835 case DT_FEND: 836 skb = ravb_get_skb_gbeth(ndev, entry, desc); 837 skb_copy_to_linear_data_offset(priv->rx_1st_skb, 838 priv->rx_1st_skb->len, 839 skb->data, 840 pkt_len); 841 skb_put(priv->rx_1st_skb, pkt_len); 842 dev_kfree_skb(skb); 843 priv->rx_1st_skb->protocol = 844 eth_type_trans(priv->rx_1st_skb, ndev); 845 napi_gro_receive(&priv->napi[q], 846 priv->rx_1st_skb); 847 rx_packets++; 848 stats->rx_bytes += pkt_len; 849 break; 850 } 851 } 852 853 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 854 desc = &priv->gbeth_rx_ring[entry]; 855 } 856 857 /* Refill the RX ring buffers. */ 858 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 859 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 860 desc = &priv->gbeth_rx_ring[entry]; 861 desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE); 862 863 if (!priv->rx_skb[q][entry]) { 864 skb = netdev_alloc_skb(ndev, info->max_rx_len); 865 if (!skb) 866 break; 867 ravb_set_buffer_align(skb); 868 dma_addr = dma_map_single(ndev->dev.parent, 869 skb->data, 870 GBETH_RX_BUFF_MAX, 871 DMA_FROM_DEVICE); 872 skb_checksum_none_assert(skb); 873 /* We just set the data size to 0 for a failed mapping 874 * which should prevent DMA from happening... 875 */ 876 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 877 desc->ds_cc = cpu_to_le16(0); 878 desc->dptr = cpu_to_le32(dma_addr); 879 priv->rx_skb[q][entry] = skb; 880 } 881 /* Descriptor type must be set after all the above writes */ 882 dma_wmb(); 883 desc->die_dt = DT_FEMPTY; 884 } 885 886 stats->rx_packets += rx_packets; 887 *quota -= rx_packets; 888 return *quota == 0; 889 } 890 891 /* Packet receive function for Ethernet AVB */ 892 static bool ravb_rx_rcar(struct net_device *ndev, int *quota, int q) 893 { 894 struct ravb_private *priv = netdev_priv(ndev); 895 const struct ravb_hw_info *info = priv->info; 896 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 897 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 898 priv->cur_rx[q]; 899 struct net_device_stats *stats = &priv->stats[q]; 900 struct ravb_ex_rx_desc *desc; 901 struct sk_buff *skb; 902 dma_addr_t dma_addr; 903 struct timespec64 ts; 904 u8 desc_status; 905 u16 pkt_len; 906 int limit; 907 908 boguscnt = min(boguscnt, *quota); 909 limit = boguscnt; 910 desc = &priv->rx_ring[q][entry]; 911 while (desc->die_dt != DT_FEMPTY) { 912 /* Descriptor type must be checked before all other reads */ 913 dma_rmb(); 914 desc_status = desc->msc; 915 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 916 917 if (--boguscnt < 0) 918 break; 919 920 /* We use 0-byte descriptors to mark the DMA mapping errors */ 921 if (!pkt_len) 922 continue; 923 924 if (desc_status & MSC_MC) 925 stats->multicast++; 926 927 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 928 MSC_CEEF)) { 929 stats->rx_errors++; 930 if (desc_status & MSC_CRC) 931 stats->rx_crc_errors++; 932 if (desc_status & MSC_RFE) 933 stats->rx_frame_errors++; 934 if (desc_status & (MSC_RTLF | MSC_RTSF)) 935 stats->rx_length_errors++; 936 if (desc_status & MSC_CEEF) 937 stats->rx_missed_errors++; 938 } else { 939 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 940 941 skb = priv->rx_skb[q][entry]; 942 priv->rx_skb[q][entry] = NULL; 943 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 944 RX_BUF_SZ, 945 DMA_FROM_DEVICE); 946 get_ts &= (q == RAVB_NC) ? 947 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 948 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 949 if (get_ts) { 950 struct skb_shared_hwtstamps *shhwtstamps; 951 952 shhwtstamps = skb_hwtstamps(skb); 953 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 954 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 955 32) | le32_to_cpu(desc->ts_sl); 956 ts.tv_nsec = le32_to_cpu(desc->ts_n); 957 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 958 } 959 960 skb_put(skb, pkt_len); 961 skb->protocol = eth_type_trans(skb, ndev); 962 if (ndev->features & NETIF_F_RXCSUM) 963 ravb_rx_csum(skb); 964 napi_gro_receive(&priv->napi[q], skb); 965 stats->rx_packets++; 966 stats->rx_bytes += pkt_len; 967 } 968 969 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 970 desc = &priv->rx_ring[q][entry]; 971 } 972 973 /* Refill the RX ring buffers. */ 974 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 975 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 976 desc = &priv->rx_ring[q][entry]; 977 desc->ds_cc = cpu_to_le16(RX_BUF_SZ); 978 979 if (!priv->rx_skb[q][entry]) { 980 skb = netdev_alloc_skb(ndev, info->max_rx_len); 981 if (!skb) 982 break; /* Better luck next round. */ 983 ravb_set_buffer_align(skb); 984 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 985 le16_to_cpu(desc->ds_cc), 986 DMA_FROM_DEVICE); 987 skb_checksum_none_assert(skb); 988 /* We just set the data size to 0 for a failed mapping 989 * which should prevent DMA from happening... 990 */ 991 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 992 desc->ds_cc = cpu_to_le16(0); 993 desc->dptr = cpu_to_le32(dma_addr); 994 priv->rx_skb[q][entry] = skb; 995 } 996 /* Descriptor type must be set after all the above writes */ 997 dma_wmb(); 998 desc->die_dt = DT_FEMPTY; 999 } 1000 1001 *quota -= limit - (++boguscnt); 1002 1003 return boguscnt <= 0; 1004 } 1005 1006 /* Packet receive function for Ethernet AVB */ 1007 static bool ravb_rx(struct net_device *ndev, int *quota, int q) 1008 { 1009 struct ravb_private *priv = netdev_priv(ndev); 1010 const struct ravb_hw_info *info = priv->info; 1011 1012 return info->receive(ndev, quota, q); 1013 } 1014 1015 static void ravb_rcv_snd_disable(struct net_device *ndev) 1016 { 1017 /* Disable TX and RX */ 1018 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 1019 } 1020 1021 static void ravb_rcv_snd_enable(struct net_device *ndev) 1022 { 1023 /* Enable TX and RX */ 1024 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 1025 } 1026 1027 /* function for waiting dma process finished */ 1028 static int ravb_stop_dma(struct net_device *ndev) 1029 { 1030 struct ravb_private *priv = netdev_priv(ndev); 1031 const struct ravb_hw_info *info = priv->info; 1032 int error; 1033 1034 /* Wait for stopping the hardware TX process */ 1035 error = ravb_wait(ndev, TCCR, info->tccr_mask, 0); 1036 1037 if (error) 1038 return error; 1039 1040 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 1041 0); 1042 if (error) 1043 return error; 1044 1045 /* Stop the E-MAC's RX/TX processes. */ 1046 ravb_rcv_snd_disable(ndev); 1047 1048 /* Wait for stopping the RX DMA process */ 1049 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 1050 if (error) 1051 return error; 1052 1053 /* Stop AVB-DMAC process */ 1054 return ravb_set_opmode(ndev, CCC_OPC_CONFIG); 1055 } 1056 1057 /* E-MAC interrupt handler */ 1058 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 1059 { 1060 struct ravb_private *priv = netdev_priv(ndev); 1061 u32 ecsr, psr; 1062 1063 ecsr = ravb_read(ndev, ECSR); 1064 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 1065 1066 if (ecsr & ECSR_MPD) 1067 pm_wakeup_event(&priv->pdev->dev, 0); 1068 if (ecsr & ECSR_ICD) 1069 ndev->stats.tx_carrier_errors++; 1070 if (ecsr & ECSR_LCHNG) { 1071 /* Link changed */ 1072 if (priv->no_avb_link) 1073 return; 1074 psr = ravb_read(ndev, PSR); 1075 if (priv->avb_link_active_low) 1076 psr ^= PSR_LMON; 1077 if (!(psr & PSR_LMON)) { 1078 /* DIsable RX and TX */ 1079 ravb_rcv_snd_disable(ndev); 1080 } else { 1081 /* Enable RX and TX */ 1082 ravb_rcv_snd_enable(ndev); 1083 } 1084 } 1085 } 1086 1087 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 1088 { 1089 struct net_device *ndev = dev_id; 1090 struct ravb_private *priv = netdev_priv(ndev); 1091 1092 spin_lock(&priv->lock); 1093 ravb_emac_interrupt_unlocked(ndev); 1094 spin_unlock(&priv->lock); 1095 return IRQ_HANDLED; 1096 } 1097 1098 /* Error interrupt handler */ 1099 static void ravb_error_interrupt(struct net_device *ndev) 1100 { 1101 struct ravb_private *priv = netdev_priv(ndev); 1102 u32 eis, ris2; 1103 1104 eis = ravb_read(ndev, EIS); 1105 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS); 1106 if (eis & EIS_QFS) { 1107 ris2 = ravb_read(ndev, RIS2); 1108 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_QFF1 | RIS2_RFFF | RIS2_RESERVED), 1109 RIS2); 1110 1111 /* Receive Descriptor Empty int */ 1112 if (ris2 & RIS2_QFF0) 1113 priv->stats[RAVB_BE].rx_over_errors++; 1114 1115 /* Receive Descriptor Empty int */ 1116 if (ris2 & RIS2_QFF1) 1117 priv->stats[RAVB_NC].rx_over_errors++; 1118 1119 /* Receive FIFO Overflow int */ 1120 if (ris2 & RIS2_RFFF) 1121 priv->rx_fifo_errors++; 1122 } 1123 } 1124 1125 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 1126 { 1127 struct ravb_private *priv = netdev_priv(ndev); 1128 const struct ravb_hw_info *info = priv->info; 1129 u32 ris0 = ravb_read(ndev, RIS0); 1130 u32 ric0 = ravb_read(ndev, RIC0); 1131 u32 tis = ravb_read(ndev, TIS); 1132 u32 tic = ravb_read(ndev, TIC); 1133 1134 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 1135 if (napi_schedule_prep(&priv->napi[q])) { 1136 /* Mask RX and TX interrupts */ 1137 if (!info->irq_en_dis) { 1138 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 1139 ravb_write(ndev, tic & ~BIT(q), TIC); 1140 } else { 1141 ravb_write(ndev, BIT(q), RID0); 1142 ravb_write(ndev, BIT(q), TID); 1143 } 1144 __napi_schedule(&priv->napi[q]); 1145 } else { 1146 netdev_warn(ndev, 1147 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 1148 ris0, ric0); 1149 netdev_warn(ndev, 1150 " tx status 0x%08x, tx mask 0x%08x.\n", 1151 tis, tic); 1152 } 1153 return true; 1154 } 1155 return false; 1156 } 1157 1158 static bool ravb_timestamp_interrupt(struct net_device *ndev) 1159 { 1160 u32 tis = ravb_read(ndev, TIS); 1161 1162 if (tis & TIS_TFUF) { 1163 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS); 1164 ravb_get_tx_tstamp(ndev); 1165 return true; 1166 } 1167 return false; 1168 } 1169 1170 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 1171 { 1172 struct net_device *ndev = dev_id; 1173 struct ravb_private *priv = netdev_priv(ndev); 1174 const struct ravb_hw_info *info = priv->info; 1175 irqreturn_t result = IRQ_NONE; 1176 u32 iss; 1177 1178 spin_lock(&priv->lock); 1179 /* Get interrupt status */ 1180 iss = ravb_read(ndev, ISS); 1181 1182 /* Received and transmitted interrupts */ 1183 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 1184 int q; 1185 1186 /* Timestamp updated */ 1187 if (ravb_timestamp_interrupt(ndev)) 1188 result = IRQ_HANDLED; 1189 1190 /* Network control and best effort queue RX/TX */ 1191 if (info->nc_queues) { 1192 for (q = RAVB_NC; q >= RAVB_BE; q--) { 1193 if (ravb_queue_interrupt(ndev, q)) 1194 result = IRQ_HANDLED; 1195 } 1196 } else { 1197 if (ravb_queue_interrupt(ndev, RAVB_BE)) 1198 result = IRQ_HANDLED; 1199 } 1200 } 1201 1202 /* E-MAC status summary */ 1203 if (iss & ISS_MS) { 1204 ravb_emac_interrupt_unlocked(ndev); 1205 result = IRQ_HANDLED; 1206 } 1207 1208 /* Error status summary */ 1209 if (iss & ISS_ES) { 1210 ravb_error_interrupt(ndev); 1211 result = IRQ_HANDLED; 1212 } 1213 1214 /* gPTP interrupt status summary */ 1215 if (iss & ISS_CGIS) { 1216 ravb_ptp_interrupt(ndev); 1217 result = IRQ_HANDLED; 1218 } 1219 1220 spin_unlock(&priv->lock); 1221 return result; 1222 } 1223 1224 /* Timestamp/Error/gPTP interrupt handler */ 1225 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 1226 { 1227 struct net_device *ndev = dev_id; 1228 struct ravb_private *priv = netdev_priv(ndev); 1229 irqreturn_t result = IRQ_NONE; 1230 u32 iss; 1231 1232 spin_lock(&priv->lock); 1233 /* Get interrupt status */ 1234 iss = ravb_read(ndev, ISS); 1235 1236 /* Timestamp updated */ 1237 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 1238 result = IRQ_HANDLED; 1239 1240 /* Error status summary */ 1241 if (iss & ISS_ES) { 1242 ravb_error_interrupt(ndev); 1243 result = IRQ_HANDLED; 1244 } 1245 1246 /* gPTP interrupt status summary */ 1247 if (iss & ISS_CGIS) { 1248 ravb_ptp_interrupt(ndev); 1249 result = IRQ_HANDLED; 1250 } 1251 1252 spin_unlock(&priv->lock); 1253 return result; 1254 } 1255 1256 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 1257 { 1258 struct net_device *ndev = dev_id; 1259 struct ravb_private *priv = netdev_priv(ndev); 1260 irqreturn_t result = IRQ_NONE; 1261 1262 spin_lock(&priv->lock); 1263 1264 /* Network control/Best effort queue RX/TX */ 1265 if (ravb_queue_interrupt(ndev, q)) 1266 result = IRQ_HANDLED; 1267 1268 spin_unlock(&priv->lock); 1269 return result; 1270 } 1271 1272 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 1273 { 1274 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 1275 } 1276 1277 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 1278 { 1279 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 1280 } 1281 1282 static int ravb_poll(struct napi_struct *napi, int budget) 1283 { 1284 struct net_device *ndev = napi->dev; 1285 struct ravb_private *priv = netdev_priv(ndev); 1286 const struct ravb_hw_info *info = priv->info; 1287 bool gptp = info->gptp || info->ccc_gac; 1288 struct ravb_rx_desc *desc; 1289 unsigned long flags; 1290 int q = napi - priv->napi; 1291 int mask = BIT(q); 1292 int quota = budget; 1293 unsigned int entry; 1294 1295 if (!gptp) { 1296 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 1297 desc = &priv->gbeth_rx_ring[entry]; 1298 } 1299 /* Processing RX Descriptor Ring */ 1300 /* Clear RX interrupt */ 1301 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0); 1302 if (gptp || desc->die_dt != DT_FEMPTY) { 1303 if (ravb_rx(ndev, "a, q)) 1304 goto out; 1305 } 1306 1307 /* Processing TX Descriptor Ring */ 1308 spin_lock_irqsave(&priv->lock, flags); 1309 /* Clear TX interrupt */ 1310 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS); 1311 ravb_tx_free(ndev, q, true); 1312 netif_wake_subqueue(ndev, q); 1313 spin_unlock_irqrestore(&priv->lock, flags); 1314 1315 napi_complete(napi); 1316 1317 /* Re-enable RX/TX interrupts */ 1318 spin_lock_irqsave(&priv->lock, flags); 1319 if (!info->irq_en_dis) { 1320 ravb_modify(ndev, RIC0, mask, mask); 1321 ravb_modify(ndev, TIC, mask, mask); 1322 } else { 1323 ravb_write(ndev, mask, RIE0); 1324 ravb_write(ndev, mask, TIE); 1325 } 1326 spin_unlock_irqrestore(&priv->lock, flags); 1327 1328 /* Receive error message handling */ 1329 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 1330 if (info->nc_queues) 1331 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 1332 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 1333 ndev->stats.rx_over_errors = priv->rx_over_errors; 1334 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 1335 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 1336 out: 1337 return budget - quota; 1338 } 1339 1340 static void ravb_set_duplex_gbeth(struct net_device *ndev) 1341 { 1342 struct ravb_private *priv = netdev_priv(ndev); 1343 1344 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex > 0 ? ECMR_DM : 0); 1345 } 1346 1347 /* PHY state control function */ 1348 static void ravb_adjust_link(struct net_device *ndev) 1349 { 1350 struct ravb_private *priv = netdev_priv(ndev); 1351 const struct ravb_hw_info *info = priv->info; 1352 struct phy_device *phydev = ndev->phydev; 1353 bool new_state = false; 1354 unsigned long flags; 1355 1356 spin_lock_irqsave(&priv->lock, flags); 1357 1358 /* Disable TX and RX right over here, if E-MAC change is ignored */ 1359 if (priv->no_avb_link) 1360 ravb_rcv_snd_disable(ndev); 1361 1362 if (phydev->link) { 1363 if (info->half_duplex && phydev->duplex != priv->duplex) { 1364 new_state = true; 1365 priv->duplex = phydev->duplex; 1366 ravb_set_duplex_gbeth(ndev); 1367 } 1368 1369 if (phydev->speed != priv->speed) { 1370 new_state = true; 1371 priv->speed = phydev->speed; 1372 info->set_rate(ndev); 1373 } 1374 if (!priv->link) { 1375 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 1376 new_state = true; 1377 priv->link = phydev->link; 1378 } 1379 } else if (priv->link) { 1380 new_state = true; 1381 priv->link = 0; 1382 priv->speed = 0; 1383 if (info->half_duplex) 1384 priv->duplex = -1; 1385 } 1386 1387 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1388 if (priv->no_avb_link && phydev->link) 1389 ravb_rcv_snd_enable(ndev); 1390 1391 spin_unlock_irqrestore(&priv->lock, flags); 1392 1393 if (new_state && netif_msg_link(priv)) 1394 phy_print_status(phydev); 1395 } 1396 1397 /* PHY init function */ 1398 static int ravb_phy_init(struct net_device *ndev) 1399 { 1400 struct device_node *np = ndev->dev.parent->of_node; 1401 struct ravb_private *priv = netdev_priv(ndev); 1402 const struct ravb_hw_info *info = priv->info; 1403 struct phy_device *phydev; 1404 struct device_node *pn; 1405 phy_interface_t iface; 1406 int err; 1407 1408 priv->link = 0; 1409 priv->speed = 0; 1410 priv->duplex = -1; 1411 1412 /* Try connecting to PHY */ 1413 pn = of_parse_phandle(np, "phy-handle", 0); 1414 if (!pn) { 1415 /* In the case of a fixed PHY, the DT node associated 1416 * to the PHY is the Ethernet MAC DT node. 1417 */ 1418 if (of_phy_is_fixed_link(np)) { 1419 err = of_phy_register_fixed_link(np); 1420 if (err) 1421 return err; 1422 } 1423 pn = of_node_get(np); 1424 } 1425 1426 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII 1427 : priv->phy_interface; 1428 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface); 1429 of_node_put(pn); 1430 if (!phydev) { 1431 netdev_err(ndev, "failed to connect PHY\n"); 1432 err = -ENOENT; 1433 goto err_deregister_fixed_link; 1434 } 1435 1436 if (!info->half_duplex) { 1437 /* 10BASE, Pause and Asym Pause is not supported */ 1438 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1439 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1440 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT); 1441 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 1442 1443 /* Half Duplex is not supported */ 1444 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1445 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1446 } 1447 1448 phy_attached_info(phydev); 1449 1450 return 0; 1451 1452 err_deregister_fixed_link: 1453 if (of_phy_is_fixed_link(np)) 1454 of_phy_deregister_fixed_link(np); 1455 1456 return err; 1457 } 1458 1459 /* PHY control start function */ 1460 static int ravb_phy_start(struct net_device *ndev) 1461 { 1462 int error; 1463 1464 error = ravb_phy_init(ndev); 1465 if (error) 1466 return error; 1467 1468 phy_start(ndev->phydev); 1469 1470 return 0; 1471 } 1472 1473 static u32 ravb_get_msglevel(struct net_device *ndev) 1474 { 1475 struct ravb_private *priv = netdev_priv(ndev); 1476 1477 return priv->msg_enable; 1478 } 1479 1480 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1481 { 1482 struct ravb_private *priv = netdev_priv(ndev); 1483 1484 priv->msg_enable = value; 1485 } 1486 1487 static const char ravb_gstrings_stats_gbeth[][ETH_GSTRING_LEN] = { 1488 "rx_queue_0_current", 1489 "tx_queue_0_current", 1490 "rx_queue_0_dirty", 1491 "tx_queue_0_dirty", 1492 "rx_queue_0_packets", 1493 "tx_queue_0_packets", 1494 "rx_queue_0_bytes", 1495 "tx_queue_0_bytes", 1496 "rx_queue_0_mcast_packets", 1497 "rx_queue_0_errors", 1498 "rx_queue_0_crc_errors", 1499 "rx_queue_0_frame_errors", 1500 "rx_queue_0_length_errors", 1501 "rx_queue_0_csum_offload_errors", 1502 "rx_queue_0_over_errors", 1503 }; 1504 1505 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1506 "rx_queue_0_current", 1507 "tx_queue_0_current", 1508 "rx_queue_0_dirty", 1509 "tx_queue_0_dirty", 1510 "rx_queue_0_packets", 1511 "tx_queue_0_packets", 1512 "rx_queue_0_bytes", 1513 "tx_queue_0_bytes", 1514 "rx_queue_0_mcast_packets", 1515 "rx_queue_0_errors", 1516 "rx_queue_0_crc_errors", 1517 "rx_queue_0_frame_errors", 1518 "rx_queue_0_length_errors", 1519 "rx_queue_0_missed_errors", 1520 "rx_queue_0_over_errors", 1521 1522 "rx_queue_1_current", 1523 "tx_queue_1_current", 1524 "rx_queue_1_dirty", 1525 "tx_queue_1_dirty", 1526 "rx_queue_1_packets", 1527 "tx_queue_1_packets", 1528 "rx_queue_1_bytes", 1529 "tx_queue_1_bytes", 1530 "rx_queue_1_mcast_packets", 1531 "rx_queue_1_errors", 1532 "rx_queue_1_crc_errors", 1533 "rx_queue_1_frame_errors", 1534 "rx_queue_1_length_errors", 1535 "rx_queue_1_missed_errors", 1536 "rx_queue_1_over_errors", 1537 }; 1538 1539 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1540 { 1541 struct ravb_private *priv = netdev_priv(netdev); 1542 const struct ravb_hw_info *info = priv->info; 1543 1544 switch (sset) { 1545 case ETH_SS_STATS: 1546 return info->stats_len; 1547 default: 1548 return -EOPNOTSUPP; 1549 } 1550 } 1551 1552 static void ravb_get_ethtool_stats(struct net_device *ndev, 1553 struct ethtool_stats *estats, u64 *data) 1554 { 1555 struct ravb_private *priv = netdev_priv(ndev); 1556 const struct ravb_hw_info *info = priv->info; 1557 int num_rx_q; 1558 int i = 0; 1559 int q; 1560 1561 num_rx_q = info->nc_queues ? NUM_RX_QUEUE : 1; 1562 /* Device-specific stats */ 1563 for (q = RAVB_BE; q < num_rx_q; q++) { 1564 struct net_device_stats *stats = &priv->stats[q]; 1565 1566 data[i++] = priv->cur_rx[q]; 1567 data[i++] = priv->cur_tx[q]; 1568 data[i++] = priv->dirty_rx[q]; 1569 data[i++] = priv->dirty_tx[q]; 1570 data[i++] = stats->rx_packets; 1571 data[i++] = stats->tx_packets; 1572 data[i++] = stats->rx_bytes; 1573 data[i++] = stats->tx_bytes; 1574 data[i++] = stats->multicast; 1575 data[i++] = stats->rx_errors; 1576 data[i++] = stats->rx_crc_errors; 1577 data[i++] = stats->rx_frame_errors; 1578 data[i++] = stats->rx_length_errors; 1579 data[i++] = stats->rx_missed_errors; 1580 data[i++] = stats->rx_over_errors; 1581 } 1582 } 1583 1584 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1585 { 1586 struct ravb_private *priv = netdev_priv(ndev); 1587 const struct ravb_hw_info *info = priv->info; 1588 1589 switch (stringset) { 1590 case ETH_SS_STATS: 1591 memcpy(data, info->gstrings_stats, info->gstrings_size); 1592 break; 1593 } 1594 } 1595 1596 static void ravb_get_ringparam(struct net_device *ndev, 1597 struct ethtool_ringparam *ring, 1598 struct kernel_ethtool_ringparam *kernel_ring, 1599 struct netlink_ext_ack *extack) 1600 { 1601 struct ravb_private *priv = netdev_priv(ndev); 1602 1603 ring->rx_max_pending = BE_RX_RING_MAX; 1604 ring->tx_max_pending = BE_TX_RING_MAX; 1605 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1606 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1607 } 1608 1609 static int ravb_set_ringparam(struct net_device *ndev, 1610 struct ethtool_ringparam *ring, 1611 struct kernel_ethtool_ringparam *kernel_ring, 1612 struct netlink_ext_ack *extack) 1613 { 1614 struct ravb_private *priv = netdev_priv(ndev); 1615 const struct ravb_hw_info *info = priv->info; 1616 int error; 1617 1618 if (ring->tx_pending > BE_TX_RING_MAX || 1619 ring->rx_pending > BE_RX_RING_MAX || 1620 ring->tx_pending < BE_TX_RING_MIN || 1621 ring->rx_pending < BE_RX_RING_MIN) 1622 return -EINVAL; 1623 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1624 return -EINVAL; 1625 1626 if (netif_running(ndev)) { 1627 netif_device_detach(ndev); 1628 /* Stop PTP Clock driver */ 1629 if (info->gptp) 1630 ravb_ptp_stop(ndev); 1631 /* Wait for DMA stopping */ 1632 error = ravb_stop_dma(ndev); 1633 if (error) { 1634 netdev_err(ndev, 1635 "cannot set ringparam! Any AVB processes are still running?\n"); 1636 return error; 1637 } 1638 synchronize_irq(ndev->irq); 1639 1640 /* Free all the skb's in the RX queue and the DMA buffers. */ 1641 ravb_ring_free(ndev, RAVB_BE); 1642 if (info->nc_queues) 1643 ravb_ring_free(ndev, RAVB_NC); 1644 } 1645 1646 /* Set new parameters */ 1647 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1648 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1649 1650 if (netif_running(ndev)) { 1651 error = ravb_dmac_init(ndev); 1652 if (error) { 1653 netdev_err(ndev, 1654 "%s: ravb_dmac_init() failed, error %d\n", 1655 __func__, error); 1656 return error; 1657 } 1658 1659 ravb_emac_init(ndev); 1660 1661 /* Initialise PTP Clock driver */ 1662 if (info->gptp) 1663 ravb_ptp_init(ndev, priv->pdev); 1664 1665 netif_device_attach(ndev); 1666 } 1667 1668 return 0; 1669 } 1670 1671 static int ravb_get_ts_info(struct net_device *ndev, 1672 struct ethtool_ts_info *info) 1673 { 1674 struct ravb_private *priv = netdev_priv(ndev); 1675 const struct ravb_hw_info *hw_info = priv->info; 1676 1677 info->so_timestamping = 1678 SOF_TIMESTAMPING_TX_SOFTWARE | 1679 SOF_TIMESTAMPING_RX_SOFTWARE | 1680 SOF_TIMESTAMPING_SOFTWARE | 1681 SOF_TIMESTAMPING_TX_HARDWARE | 1682 SOF_TIMESTAMPING_RX_HARDWARE | 1683 SOF_TIMESTAMPING_RAW_HARDWARE; 1684 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1685 info->rx_filters = 1686 (1 << HWTSTAMP_FILTER_NONE) | 1687 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1688 (1 << HWTSTAMP_FILTER_ALL); 1689 if (hw_info->gptp || hw_info->ccc_gac) 1690 info->phc_index = ptp_clock_index(priv->ptp.clock); 1691 1692 return 0; 1693 } 1694 1695 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1696 { 1697 struct ravb_private *priv = netdev_priv(ndev); 1698 1699 wol->supported = WAKE_MAGIC; 1700 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1701 } 1702 1703 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1704 { 1705 struct ravb_private *priv = netdev_priv(ndev); 1706 const struct ravb_hw_info *info = priv->info; 1707 1708 if (!info->magic_pkt || (wol->wolopts & ~WAKE_MAGIC)) 1709 return -EOPNOTSUPP; 1710 1711 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1712 1713 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1714 1715 return 0; 1716 } 1717 1718 static const struct ethtool_ops ravb_ethtool_ops = { 1719 .nway_reset = phy_ethtool_nway_reset, 1720 .get_msglevel = ravb_get_msglevel, 1721 .set_msglevel = ravb_set_msglevel, 1722 .get_link = ethtool_op_get_link, 1723 .get_strings = ravb_get_strings, 1724 .get_ethtool_stats = ravb_get_ethtool_stats, 1725 .get_sset_count = ravb_get_sset_count, 1726 .get_ringparam = ravb_get_ringparam, 1727 .set_ringparam = ravb_set_ringparam, 1728 .get_ts_info = ravb_get_ts_info, 1729 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1730 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1731 .get_wol = ravb_get_wol, 1732 .set_wol = ravb_set_wol, 1733 }; 1734 1735 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler, 1736 struct net_device *ndev, struct device *dev, 1737 const char *ch) 1738 { 1739 char *name; 1740 int error; 1741 1742 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); 1743 if (!name) 1744 return -ENOMEM; 1745 error = request_irq(irq, handler, 0, name, ndev); 1746 if (error) 1747 netdev_err(ndev, "cannot request IRQ %s\n", name); 1748 1749 return error; 1750 } 1751 1752 /* Network device open function for Ethernet AVB */ 1753 static int ravb_open(struct net_device *ndev) 1754 { 1755 struct ravb_private *priv = netdev_priv(ndev); 1756 const struct ravb_hw_info *info = priv->info; 1757 struct platform_device *pdev = priv->pdev; 1758 struct device *dev = &pdev->dev; 1759 int error; 1760 1761 napi_enable(&priv->napi[RAVB_BE]); 1762 if (info->nc_queues) 1763 napi_enable(&priv->napi[RAVB_NC]); 1764 1765 if (!info->multi_irqs) { 1766 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, 1767 ndev->name, ndev); 1768 if (error) { 1769 netdev_err(ndev, "cannot request IRQ\n"); 1770 goto out_napi_off; 1771 } 1772 } else { 1773 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev, 1774 dev, "ch22:multi"); 1775 if (error) 1776 goto out_napi_off; 1777 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev, 1778 dev, "ch24:emac"); 1779 if (error) 1780 goto out_free_irq; 1781 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt, 1782 ndev, dev, "ch0:rx_be"); 1783 if (error) 1784 goto out_free_irq_emac; 1785 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt, 1786 ndev, dev, "ch18:tx_be"); 1787 if (error) 1788 goto out_free_irq_be_rx; 1789 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt, 1790 ndev, dev, "ch1:rx_nc"); 1791 if (error) 1792 goto out_free_irq_be_tx; 1793 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt, 1794 ndev, dev, "ch19:tx_nc"); 1795 if (error) 1796 goto out_free_irq_nc_rx; 1797 1798 if (info->err_mgmt_irqs) { 1799 error = ravb_hook_irq(priv->erra_irq, ravb_multi_interrupt, 1800 ndev, dev, "err_a"); 1801 if (error) 1802 goto out_free_irq_nc_tx; 1803 error = ravb_hook_irq(priv->mgmta_irq, ravb_multi_interrupt, 1804 ndev, dev, "mgmt_a"); 1805 if (error) 1806 goto out_free_irq_erra; 1807 } 1808 } 1809 1810 /* Device init */ 1811 error = ravb_dmac_init(ndev); 1812 if (error) 1813 goto out_free_irq_mgmta; 1814 ravb_emac_init(ndev); 1815 1816 /* Initialise PTP Clock driver */ 1817 if (info->gptp) 1818 ravb_ptp_init(ndev, priv->pdev); 1819 1820 /* PHY control start */ 1821 error = ravb_phy_start(ndev); 1822 if (error) 1823 goto out_ptp_stop; 1824 1825 netif_tx_start_all_queues(ndev); 1826 1827 return 0; 1828 1829 out_ptp_stop: 1830 /* Stop PTP Clock driver */ 1831 if (info->gptp) 1832 ravb_ptp_stop(ndev); 1833 ravb_stop_dma(ndev); 1834 out_free_irq_mgmta: 1835 if (!info->multi_irqs) 1836 goto out_free_irq; 1837 if (info->err_mgmt_irqs) 1838 free_irq(priv->mgmta_irq, ndev); 1839 out_free_irq_erra: 1840 if (info->err_mgmt_irqs) 1841 free_irq(priv->erra_irq, ndev); 1842 out_free_irq_nc_tx: 1843 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1844 out_free_irq_nc_rx: 1845 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1846 out_free_irq_be_tx: 1847 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1848 out_free_irq_be_rx: 1849 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1850 out_free_irq_emac: 1851 free_irq(priv->emac_irq, ndev); 1852 out_free_irq: 1853 free_irq(ndev->irq, ndev); 1854 out_napi_off: 1855 if (info->nc_queues) 1856 napi_disable(&priv->napi[RAVB_NC]); 1857 napi_disable(&priv->napi[RAVB_BE]); 1858 return error; 1859 } 1860 1861 /* Timeout function for Ethernet AVB */ 1862 static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1863 { 1864 struct ravb_private *priv = netdev_priv(ndev); 1865 1866 netif_err(priv, tx_err, ndev, 1867 "transmit timed out, status %08x, resetting...\n", 1868 ravb_read(ndev, ISS)); 1869 1870 /* tx_errors count up */ 1871 ndev->stats.tx_errors++; 1872 1873 schedule_work(&priv->work); 1874 } 1875 1876 static void ravb_tx_timeout_work(struct work_struct *work) 1877 { 1878 struct ravb_private *priv = container_of(work, struct ravb_private, 1879 work); 1880 const struct ravb_hw_info *info = priv->info; 1881 struct net_device *ndev = priv->ndev; 1882 int error; 1883 1884 if (!rtnl_trylock()) { 1885 usleep_range(1000, 2000); 1886 schedule_work(&priv->work); 1887 return; 1888 } 1889 1890 netif_tx_stop_all_queues(ndev); 1891 1892 /* Stop PTP Clock driver */ 1893 if (info->gptp) 1894 ravb_ptp_stop(ndev); 1895 1896 /* Wait for DMA stopping */ 1897 if (ravb_stop_dma(ndev)) { 1898 /* If ravb_stop_dma() fails, the hardware is still operating 1899 * for TX and/or RX. So, this should not call the following 1900 * functions because ravb_dmac_init() is possible to fail too. 1901 * Also, this should not retry ravb_stop_dma() again and again 1902 * here because it's possible to wait forever. So, this just 1903 * re-enables the TX and RX and skip the following 1904 * re-initialization procedure. 1905 */ 1906 ravb_rcv_snd_enable(ndev); 1907 goto out; 1908 } 1909 1910 ravb_ring_free(ndev, RAVB_BE); 1911 if (info->nc_queues) 1912 ravb_ring_free(ndev, RAVB_NC); 1913 1914 /* Device init */ 1915 error = ravb_dmac_init(ndev); 1916 if (error) { 1917 /* If ravb_dmac_init() fails, descriptors are freed. So, this 1918 * should return here to avoid re-enabling the TX and RX in 1919 * ravb_emac_init(). 1920 */ 1921 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n", 1922 __func__, error); 1923 goto out_unlock; 1924 } 1925 ravb_emac_init(ndev); 1926 1927 out: 1928 /* Initialise PTP Clock driver */ 1929 if (info->gptp) 1930 ravb_ptp_init(ndev, priv->pdev); 1931 1932 netif_tx_start_all_queues(ndev); 1933 1934 out_unlock: 1935 rtnl_unlock(); 1936 } 1937 1938 /* Packet transmit function for Ethernet AVB */ 1939 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1940 { 1941 struct ravb_private *priv = netdev_priv(ndev); 1942 const struct ravb_hw_info *info = priv->info; 1943 unsigned int num_tx_desc = priv->num_tx_desc; 1944 u16 q = skb_get_queue_mapping(skb); 1945 struct ravb_tstamp_skb *ts_skb; 1946 struct ravb_tx_desc *desc; 1947 unsigned long flags; 1948 dma_addr_t dma_addr; 1949 void *buffer; 1950 u32 entry; 1951 u32 len; 1952 1953 spin_lock_irqsave(&priv->lock, flags); 1954 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 1955 num_tx_desc) { 1956 netif_err(priv, tx_queued, ndev, 1957 "still transmitting with the full ring!\n"); 1958 netif_stop_subqueue(ndev, q); 1959 spin_unlock_irqrestore(&priv->lock, flags); 1960 return NETDEV_TX_BUSY; 1961 } 1962 1963 if (skb_put_padto(skb, ETH_ZLEN)) 1964 goto exit; 1965 1966 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc); 1967 priv->tx_skb[q][entry / num_tx_desc] = skb; 1968 1969 if (num_tx_desc > 1) { 1970 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 1971 entry / num_tx_desc * DPTR_ALIGN; 1972 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 1973 1974 /* Zero length DMA descriptors are problematic as they seem 1975 * to terminate DMA transfers. Avoid them by simply using a 1976 * length of DPTR_ALIGN (4) when skb data is aligned to 1977 * DPTR_ALIGN. 1978 * 1979 * As skb is guaranteed to have at least ETH_ZLEN (60) 1980 * bytes of data by the call to skb_put_padto() above this 1981 * is safe with respect to both the length of the first DMA 1982 * descriptor (len) overflowing the available data and the 1983 * length of the second DMA descriptor (skb->len - len) 1984 * being negative. 1985 */ 1986 if (len == 0) 1987 len = DPTR_ALIGN; 1988 1989 memcpy(buffer, skb->data, len); 1990 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1991 DMA_TO_DEVICE); 1992 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1993 goto drop; 1994 1995 desc = &priv->tx_ring[q][entry]; 1996 desc->ds_tagl = cpu_to_le16(len); 1997 desc->dptr = cpu_to_le32(dma_addr); 1998 1999 buffer = skb->data + len; 2000 len = skb->len - len; 2001 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 2002 DMA_TO_DEVICE); 2003 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2004 goto unmap; 2005 2006 desc++; 2007 } else { 2008 desc = &priv->tx_ring[q][entry]; 2009 len = skb->len; 2010 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, 2011 DMA_TO_DEVICE); 2012 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2013 goto drop; 2014 } 2015 desc->ds_tagl = cpu_to_le16(len); 2016 desc->dptr = cpu_to_le32(dma_addr); 2017 2018 /* TX timestamp required */ 2019 if (info->gptp || info->ccc_gac) { 2020 if (q == RAVB_NC) { 2021 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 2022 if (!ts_skb) { 2023 if (num_tx_desc > 1) { 2024 desc--; 2025 dma_unmap_single(ndev->dev.parent, dma_addr, 2026 len, DMA_TO_DEVICE); 2027 } 2028 goto unmap; 2029 } 2030 ts_skb->skb = skb_get(skb); 2031 ts_skb->tag = priv->ts_skb_tag++; 2032 priv->ts_skb_tag &= 0x3ff; 2033 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 2034 2035 /* TAG and timestamp required flag */ 2036 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2037 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 2038 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12); 2039 } 2040 2041 skb_tx_timestamp(skb); 2042 } 2043 /* Descriptor type must be set after all the above writes */ 2044 dma_wmb(); 2045 if (num_tx_desc > 1) { 2046 desc->die_dt = DT_FEND; 2047 desc--; 2048 desc->die_dt = DT_FSTART; 2049 } else { 2050 desc->die_dt = DT_FSINGLE; 2051 } 2052 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 2053 2054 priv->cur_tx[q] += num_tx_desc; 2055 if (priv->cur_tx[q] - priv->dirty_tx[q] > 2056 (priv->num_tx_ring[q] - 1) * num_tx_desc && 2057 !ravb_tx_free(ndev, q, true)) 2058 netif_stop_subqueue(ndev, q); 2059 2060 exit: 2061 spin_unlock_irqrestore(&priv->lock, flags); 2062 return NETDEV_TX_OK; 2063 2064 unmap: 2065 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 2066 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 2067 drop: 2068 dev_kfree_skb_any(skb); 2069 priv->tx_skb[q][entry / num_tx_desc] = NULL; 2070 goto exit; 2071 } 2072 2073 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 2074 struct net_device *sb_dev) 2075 { 2076 /* If skb needs TX timestamp, it is handled in network control queue */ 2077 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 2078 RAVB_BE; 2079 2080 } 2081 2082 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 2083 { 2084 struct ravb_private *priv = netdev_priv(ndev); 2085 const struct ravb_hw_info *info = priv->info; 2086 struct net_device_stats *nstats, *stats0, *stats1; 2087 2088 nstats = &ndev->stats; 2089 stats0 = &priv->stats[RAVB_BE]; 2090 2091 if (info->tx_counters) { 2092 nstats->tx_dropped += ravb_read(ndev, TROCR); 2093 ravb_write(ndev, 0, TROCR); /* (write clear) */ 2094 } 2095 2096 if (info->carrier_counters) { 2097 nstats->collisions += ravb_read(ndev, CXR41); 2098 ravb_write(ndev, 0, CXR41); /* (write clear) */ 2099 nstats->tx_carrier_errors += ravb_read(ndev, CXR42); 2100 ravb_write(ndev, 0, CXR42); /* (write clear) */ 2101 } 2102 2103 nstats->rx_packets = stats0->rx_packets; 2104 nstats->tx_packets = stats0->tx_packets; 2105 nstats->rx_bytes = stats0->rx_bytes; 2106 nstats->tx_bytes = stats0->tx_bytes; 2107 nstats->multicast = stats0->multicast; 2108 nstats->rx_errors = stats0->rx_errors; 2109 nstats->rx_crc_errors = stats0->rx_crc_errors; 2110 nstats->rx_frame_errors = stats0->rx_frame_errors; 2111 nstats->rx_length_errors = stats0->rx_length_errors; 2112 nstats->rx_missed_errors = stats0->rx_missed_errors; 2113 nstats->rx_over_errors = stats0->rx_over_errors; 2114 if (info->nc_queues) { 2115 stats1 = &priv->stats[RAVB_NC]; 2116 2117 nstats->rx_packets += stats1->rx_packets; 2118 nstats->tx_packets += stats1->tx_packets; 2119 nstats->rx_bytes += stats1->rx_bytes; 2120 nstats->tx_bytes += stats1->tx_bytes; 2121 nstats->multicast += stats1->multicast; 2122 nstats->rx_errors += stats1->rx_errors; 2123 nstats->rx_crc_errors += stats1->rx_crc_errors; 2124 nstats->rx_frame_errors += stats1->rx_frame_errors; 2125 nstats->rx_length_errors += stats1->rx_length_errors; 2126 nstats->rx_missed_errors += stats1->rx_missed_errors; 2127 nstats->rx_over_errors += stats1->rx_over_errors; 2128 } 2129 2130 return nstats; 2131 } 2132 2133 /* Update promiscuous bit */ 2134 static void ravb_set_rx_mode(struct net_device *ndev) 2135 { 2136 struct ravb_private *priv = netdev_priv(ndev); 2137 unsigned long flags; 2138 2139 spin_lock_irqsave(&priv->lock, flags); 2140 ravb_modify(ndev, ECMR, ECMR_PRM, 2141 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 2142 spin_unlock_irqrestore(&priv->lock, flags); 2143 } 2144 2145 /* Device close function for Ethernet AVB */ 2146 static int ravb_close(struct net_device *ndev) 2147 { 2148 struct device_node *np = ndev->dev.parent->of_node; 2149 struct ravb_private *priv = netdev_priv(ndev); 2150 const struct ravb_hw_info *info = priv->info; 2151 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 2152 2153 netif_tx_stop_all_queues(ndev); 2154 2155 /* Disable interrupts by clearing the interrupt masks. */ 2156 ravb_write(ndev, 0, RIC0); 2157 ravb_write(ndev, 0, RIC2); 2158 ravb_write(ndev, 0, TIC); 2159 2160 /* Stop PTP Clock driver */ 2161 if (info->gptp) 2162 ravb_ptp_stop(ndev); 2163 2164 /* Set the config mode to stop the AVB-DMAC's processes */ 2165 if (ravb_stop_dma(ndev) < 0) 2166 netdev_err(ndev, 2167 "device will be stopped after h/w processes are done.\n"); 2168 2169 /* Clear the timestamp list */ 2170 if (info->gptp || info->ccc_gac) { 2171 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 2172 list_del(&ts_skb->list); 2173 kfree_skb(ts_skb->skb); 2174 kfree(ts_skb); 2175 } 2176 } 2177 2178 /* PHY disconnect */ 2179 if (ndev->phydev) { 2180 phy_stop(ndev->phydev); 2181 phy_disconnect(ndev->phydev); 2182 if (of_phy_is_fixed_link(np)) 2183 of_phy_deregister_fixed_link(np); 2184 } 2185 2186 cancel_work_sync(&priv->work); 2187 2188 if (info->multi_irqs) { 2189 free_irq(priv->tx_irqs[RAVB_NC], ndev); 2190 free_irq(priv->rx_irqs[RAVB_NC], ndev); 2191 free_irq(priv->tx_irqs[RAVB_BE], ndev); 2192 free_irq(priv->rx_irqs[RAVB_BE], ndev); 2193 free_irq(priv->emac_irq, ndev); 2194 if (info->err_mgmt_irqs) { 2195 free_irq(priv->erra_irq, ndev); 2196 free_irq(priv->mgmta_irq, ndev); 2197 } 2198 } 2199 free_irq(ndev->irq, ndev); 2200 2201 if (info->nc_queues) 2202 napi_disable(&priv->napi[RAVB_NC]); 2203 napi_disable(&priv->napi[RAVB_BE]); 2204 2205 /* Free all the skb's in the RX queue and the DMA buffers. */ 2206 ravb_ring_free(ndev, RAVB_BE); 2207 if (info->nc_queues) 2208 ravb_ring_free(ndev, RAVB_NC); 2209 2210 return 0; 2211 } 2212 2213 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 2214 { 2215 struct ravb_private *priv = netdev_priv(ndev); 2216 struct hwtstamp_config config; 2217 2218 config.flags = 0; 2219 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 2220 HWTSTAMP_TX_OFF; 2221 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) { 2222 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT: 2223 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 2224 break; 2225 case RAVB_RXTSTAMP_TYPE_ALL: 2226 config.rx_filter = HWTSTAMP_FILTER_ALL; 2227 break; 2228 default: 2229 config.rx_filter = HWTSTAMP_FILTER_NONE; 2230 } 2231 2232 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2233 -EFAULT : 0; 2234 } 2235 2236 /* Control hardware time stamping */ 2237 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 2238 { 2239 struct ravb_private *priv = netdev_priv(ndev); 2240 struct hwtstamp_config config; 2241 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 2242 u32 tstamp_tx_ctrl; 2243 2244 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 2245 return -EFAULT; 2246 2247 switch (config.tx_type) { 2248 case HWTSTAMP_TX_OFF: 2249 tstamp_tx_ctrl = 0; 2250 break; 2251 case HWTSTAMP_TX_ON: 2252 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 2253 break; 2254 default: 2255 return -ERANGE; 2256 } 2257 2258 switch (config.rx_filter) { 2259 case HWTSTAMP_FILTER_NONE: 2260 tstamp_rx_ctrl = 0; 2261 break; 2262 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2263 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 2264 break; 2265 default: 2266 config.rx_filter = HWTSTAMP_FILTER_ALL; 2267 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 2268 } 2269 2270 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 2271 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 2272 2273 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2274 -EFAULT : 0; 2275 } 2276 2277 /* ioctl to device function */ 2278 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 2279 { 2280 struct phy_device *phydev = ndev->phydev; 2281 2282 if (!netif_running(ndev)) 2283 return -EINVAL; 2284 2285 if (!phydev) 2286 return -ENODEV; 2287 2288 switch (cmd) { 2289 case SIOCGHWTSTAMP: 2290 return ravb_hwtstamp_get(ndev, req); 2291 case SIOCSHWTSTAMP: 2292 return ravb_hwtstamp_set(ndev, req); 2293 } 2294 2295 return phy_mii_ioctl(phydev, req, cmd); 2296 } 2297 2298 static int ravb_change_mtu(struct net_device *ndev, int new_mtu) 2299 { 2300 struct ravb_private *priv = netdev_priv(ndev); 2301 2302 ndev->mtu = new_mtu; 2303 2304 if (netif_running(ndev)) { 2305 synchronize_irq(priv->emac_irq); 2306 ravb_emac_init(ndev); 2307 } 2308 2309 netdev_update_features(ndev); 2310 2311 return 0; 2312 } 2313 2314 static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 2315 { 2316 struct ravb_private *priv = netdev_priv(ndev); 2317 unsigned long flags; 2318 2319 spin_lock_irqsave(&priv->lock, flags); 2320 2321 /* Disable TX and RX */ 2322 ravb_rcv_snd_disable(ndev); 2323 2324 /* Modify RX Checksum setting */ 2325 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 2326 2327 /* Enable TX and RX */ 2328 ravb_rcv_snd_enable(ndev); 2329 2330 spin_unlock_irqrestore(&priv->lock, flags); 2331 } 2332 2333 static int ravb_set_features_gbeth(struct net_device *ndev, 2334 netdev_features_t features) 2335 { 2336 /* Place holder */ 2337 return 0; 2338 } 2339 2340 static int ravb_set_features_rcar(struct net_device *ndev, 2341 netdev_features_t features) 2342 { 2343 netdev_features_t changed = ndev->features ^ features; 2344 2345 if (changed & NETIF_F_RXCSUM) 2346 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 2347 2348 ndev->features = features; 2349 2350 return 0; 2351 } 2352 2353 static int ravb_set_features(struct net_device *ndev, 2354 netdev_features_t features) 2355 { 2356 struct ravb_private *priv = netdev_priv(ndev); 2357 const struct ravb_hw_info *info = priv->info; 2358 2359 return info->set_feature(ndev, features); 2360 } 2361 2362 static const struct net_device_ops ravb_netdev_ops = { 2363 .ndo_open = ravb_open, 2364 .ndo_stop = ravb_close, 2365 .ndo_start_xmit = ravb_start_xmit, 2366 .ndo_select_queue = ravb_select_queue, 2367 .ndo_get_stats = ravb_get_stats, 2368 .ndo_set_rx_mode = ravb_set_rx_mode, 2369 .ndo_tx_timeout = ravb_tx_timeout, 2370 .ndo_eth_ioctl = ravb_do_ioctl, 2371 .ndo_change_mtu = ravb_change_mtu, 2372 .ndo_validate_addr = eth_validate_addr, 2373 .ndo_set_mac_address = eth_mac_addr, 2374 .ndo_set_features = ravb_set_features, 2375 }; 2376 2377 /* MDIO bus init function */ 2378 static int ravb_mdio_init(struct ravb_private *priv) 2379 { 2380 struct platform_device *pdev = priv->pdev; 2381 struct device *dev = &pdev->dev; 2382 struct phy_device *phydev; 2383 struct device_node *pn; 2384 int error; 2385 2386 /* Bitbang init */ 2387 priv->mdiobb.ops = &bb_ops; 2388 2389 /* MII controller setting */ 2390 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 2391 if (!priv->mii_bus) 2392 return -ENOMEM; 2393 2394 /* Hook up MII support for ethtool */ 2395 priv->mii_bus->name = "ravb_mii"; 2396 priv->mii_bus->parent = dev; 2397 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2398 pdev->name, pdev->id); 2399 2400 /* Register MDIO bus */ 2401 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 2402 if (error) 2403 goto out_free_bus; 2404 2405 pn = of_parse_phandle(dev->of_node, "phy-handle", 0); 2406 phydev = of_phy_find_device(pn); 2407 if (phydev) { 2408 phydev->mac_managed_pm = true; 2409 put_device(&phydev->mdio.dev); 2410 } 2411 of_node_put(pn); 2412 2413 return 0; 2414 2415 out_free_bus: 2416 free_mdio_bitbang(priv->mii_bus); 2417 return error; 2418 } 2419 2420 /* MDIO bus release function */ 2421 static int ravb_mdio_release(struct ravb_private *priv) 2422 { 2423 /* Unregister mdio bus */ 2424 mdiobus_unregister(priv->mii_bus); 2425 2426 /* Free bitbang info */ 2427 free_mdio_bitbang(priv->mii_bus); 2428 2429 return 0; 2430 } 2431 2432 static const struct ravb_hw_info ravb_gen3_hw_info = { 2433 .rx_ring_free = ravb_rx_ring_free_rcar, 2434 .rx_ring_format = ravb_rx_ring_format_rcar, 2435 .alloc_rx_desc = ravb_alloc_rx_desc_rcar, 2436 .receive = ravb_rx_rcar, 2437 .set_rate = ravb_set_rate_rcar, 2438 .set_feature = ravb_set_features_rcar, 2439 .dmac_init = ravb_dmac_init_rcar, 2440 .emac_init = ravb_emac_init_rcar, 2441 .gstrings_stats = ravb_gstrings_stats, 2442 .gstrings_size = sizeof(ravb_gstrings_stats), 2443 .net_hw_features = NETIF_F_RXCSUM, 2444 .net_features = NETIF_F_RXCSUM, 2445 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2446 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 2447 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2448 .rx_max_buf_size = SZ_2K, 2449 .internal_delay = 1, 2450 .tx_counters = 1, 2451 .multi_irqs = 1, 2452 .irq_en_dis = 1, 2453 .ccc_gac = 1, 2454 .nc_queues = 1, 2455 .magic_pkt = 1, 2456 }; 2457 2458 static const struct ravb_hw_info ravb_gen2_hw_info = { 2459 .rx_ring_free = ravb_rx_ring_free_rcar, 2460 .rx_ring_format = ravb_rx_ring_format_rcar, 2461 .alloc_rx_desc = ravb_alloc_rx_desc_rcar, 2462 .receive = ravb_rx_rcar, 2463 .set_rate = ravb_set_rate_rcar, 2464 .set_feature = ravb_set_features_rcar, 2465 .dmac_init = ravb_dmac_init_rcar, 2466 .emac_init = ravb_emac_init_rcar, 2467 .gstrings_stats = ravb_gstrings_stats, 2468 .gstrings_size = sizeof(ravb_gstrings_stats), 2469 .net_hw_features = NETIF_F_RXCSUM, 2470 .net_features = NETIF_F_RXCSUM, 2471 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2472 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 2473 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2474 .rx_max_buf_size = SZ_2K, 2475 .aligned_tx = 1, 2476 .gptp = 1, 2477 .nc_queues = 1, 2478 .magic_pkt = 1, 2479 }; 2480 2481 static const struct ravb_hw_info ravb_rzv2m_hw_info = { 2482 .rx_ring_free = ravb_rx_ring_free_rcar, 2483 .rx_ring_format = ravb_rx_ring_format_rcar, 2484 .alloc_rx_desc = ravb_alloc_rx_desc_rcar, 2485 .receive = ravb_rx_rcar, 2486 .set_rate = ravb_set_rate_rcar, 2487 .set_feature = ravb_set_features_rcar, 2488 .dmac_init = ravb_dmac_init_rcar, 2489 .emac_init = ravb_emac_init_rcar, 2490 .gstrings_stats = ravb_gstrings_stats, 2491 .gstrings_size = sizeof(ravb_gstrings_stats), 2492 .net_hw_features = NETIF_F_RXCSUM, 2493 .net_features = NETIF_F_RXCSUM, 2494 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2495 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 2496 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2497 .rx_max_buf_size = SZ_2K, 2498 .multi_irqs = 1, 2499 .err_mgmt_irqs = 1, 2500 .gptp = 1, 2501 .gptp_ref_clk = 1, 2502 .nc_queues = 1, 2503 .magic_pkt = 1, 2504 }; 2505 2506 static const struct ravb_hw_info gbeth_hw_info = { 2507 .rx_ring_free = ravb_rx_ring_free_gbeth, 2508 .rx_ring_format = ravb_rx_ring_format_gbeth, 2509 .alloc_rx_desc = ravb_alloc_rx_desc_gbeth, 2510 .receive = ravb_rx_gbeth, 2511 .set_rate = ravb_set_rate_gbeth, 2512 .set_feature = ravb_set_features_gbeth, 2513 .dmac_init = ravb_dmac_init_gbeth, 2514 .emac_init = ravb_emac_init_gbeth, 2515 .gstrings_stats = ravb_gstrings_stats_gbeth, 2516 .gstrings_size = sizeof(ravb_gstrings_stats_gbeth), 2517 .stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth), 2518 .max_rx_len = ALIGN(GBETH_RX_BUFF_MAX, RAVB_ALIGN), 2519 .tccr_mask = TCCR_TSRQ0, 2520 .rx_max_buf_size = SZ_8K, 2521 .aligned_tx = 1, 2522 .tx_counters = 1, 2523 .carrier_counters = 1, 2524 .half_duplex = 1, 2525 }; 2526 2527 static const struct of_device_id ravb_match_table[] = { 2528 { .compatible = "renesas,etheravb-r8a7790", .data = &ravb_gen2_hw_info }, 2529 { .compatible = "renesas,etheravb-r8a7794", .data = &ravb_gen2_hw_info }, 2530 { .compatible = "renesas,etheravb-rcar-gen2", .data = &ravb_gen2_hw_info }, 2531 { .compatible = "renesas,etheravb-r8a7795", .data = &ravb_gen3_hw_info }, 2532 { .compatible = "renesas,etheravb-rcar-gen3", .data = &ravb_gen3_hw_info }, 2533 { .compatible = "renesas,etheravb-rcar-gen4", .data = &ravb_gen3_hw_info }, 2534 { .compatible = "renesas,etheravb-rzv2m", .data = &ravb_rzv2m_hw_info }, 2535 { .compatible = "renesas,rzg2l-gbeth", .data = &gbeth_hw_info }, 2536 { } 2537 }; 2538 MODULE_DEVICE_TABLE(of, ravb_match_table); 2539 2540 static int ravb_set_gti(struct net_device *ndev) 2541 { 2542 struct ravb_private *priv = netdev_priv(ndev); 2543 const struct ravb_hw_info *info = priv->info; 2544 struct device *dev = ndev->dev.parent; 2545 unsigned long rate; 2546 uint64_t inc; 2547 2548 if (info->gptp_ref_clk) 2549 rate = clk_get_rate(priv->gptp_clk); 2550 else 2551 rate = clk_get_rate(priv->clk); 2552 if (!rate) 2553 return -EINVAL; 2554 2555 inc = div64_ul(1000000000ULL << 20, rate); 2556 2557 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 2558 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 2559 inc, GTI_TIV_MIN, GTI_TIV_MAX); 2560 return -EINVAL; 2561 } 2562 2563 ravb_write(ndev, inc, GTI); 2564 2565 return 0; 2566 } 2567 2568 static int ravb_set_config_mode(struct net_device *ndev) 2569 { 2570 struct ravb_private *priv = netdev_priv(ndev); 2571 const struct ravb_hw_info *info = priv->info; 2572 int error; 2573 2574 if (info->gptp) { 2575 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 2576 if (error) 2577 return error; 2578 /* Set CSEL value */ 2579 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 2580 } else if (info->ccc_gac) { 2581 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG | CCC_GAC | CCC_CSEL_HPB); 2582 } else { 2583 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 2584 } 2585 2586 return error; 2587 } 2588 2589 /* Set tx and rx clock internal delay modes */ 2590 static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev) 2591 { 2592 struct ravb_private *priv = netdev_priv(ndev); 2593 bool explicit_delay = false; 2594 u32 delay; 2595 2596 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) { 2597 /* Valid values are 0 and 1800, according to DT bindings */ 2598 priv->rxcidm = !!delay; 2599 explicit_delay = true; 2600 } 2601 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) { 2602 /* Valid values are 0 and 2000, according to DT bindings */ 2603 priv->txcidm = !!delay; 2604 explicit_delay = true; 2605 } 2606 2607 if (explicit_delay) 2608 return; 2609 2610 /* Fall back to legacy rgmii-*id behavior */ 2611 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 2612 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) { 2613 priv->rxcidm = 1; 2614 priv->rgmii_override = 1; 2615 } 2616 2617 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 2618 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) { 2619 priv->txcidm = 1; 2620 priv->rgmii_override = 1; 2621 } 2622 } 2623 2624 static void ravb_set_delay_mode(struct net_device *ndev) 2625 { 2626 struct ravb_private *priv = netdev_priv(ndev); 2627 u32 set = 0; 2628 2629 if (priv->rxcidm) 2630 set |= APSR_RDM; 2631 if (priv->txcidm) 2632 set |= APSR_TDM; 2633 ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set); 2634 } 2635 2636 static int ravb_probe(struct platform_device *pdev) 2637 { 2638 struct device_node *np = pdev->dev.of_node; 2639 const struct ravb_hw_info *info; 2640 struct reset_control *rstc; 2641 struct ravb_private *priv; 2642 struct net_device *ndev; 2643 int error, irq, q; 2644 struct resource *res; 2645 int i; 2646 2647 if (!np) { 2648 dev_err(&pdev->dev, 2649 "this driver is required to be instantiated from device tree\n"); 2650 return -EINVAL; 2651 } 2652 2653 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 2654 if (IS_ERR(rstc)) 2655 return dev_err_probe(&pdev->dev, PTR_ERR(rstc), 2656 "failed to get cpg reset\n"); 2657 2658 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 2659 NUM_TX_QUEUE, NUM_RX_QUEUE); 2660 if (!ndev) 2661 return -ENOMEM; 2662 2663 info = of_device_get_match_data(&pdev->dev); 2664 2665 ndev->features = info->net_features; 2666 ndev->hw_features = info->net_hw_features; 2667 2668 error = reset_control_deassert(rstc); 2669 if (error) 2670 goto out_free_netdev; 2671 2672 pm_runtime_enable(&pdev->dev); 2673 error = pm_runtime_resume_and_get(&pdev->dev); 2674 if (error < 0) 2675 goto out_rpm_disable; 2676 2677 if (info->multi_irqs) { 2678 if (info->err_mgmt_irqs) 2679 irq = platform_get_irq_byname(pdev, "dia"); 2680 else 2681 irq = platform_get_irq_byname(pdev, "ch22"); 2682 } else { 2683 irq = platform_get_irq(pdev, 0); 2684 } 2685 if (irq < 0) { 2686 error = irq; 2687 goto out_release; 2688 } 2689 ndev->irq = irq; 2690 2691 SET_NETDEV_DEV(ndev, &pdev->dev); 2692 2693 priv = netdev_priv(ndev); 2694 priv->info = info; 2695 priv->rstc = rstc; 2696 priv->ndev = ndev; 2697 priv->pdev = pdev; 2698 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2699 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2700 if (info->nc_queues) { 2701 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2702 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2703 } 2704 2705 priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2706 if (IS_ERR(priv->addr)) { 2707 error = PTR_ERR(priv->addr); 2708 goto out_release; 2709 } 2710 2711 /* The Ether-specific entries in the device structure. */ 2712 ndev->base_addr = res->start; 2713 2714 spin_lock_init(&priv->lock); 2715 INIT_WORK(&priv->work, ravb_tx_timeout_work); 2716 2717 error = of_get_phy_mode(np, &priv->phy_interface); 2718 if (error && error != -ENODEV) 2719 goto out_release; 2720 2721 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 2722 priv->avb_link_active_low = 2723 of_property_read_bool(np, "renesas,ether-link-active-low"); 2724 2725 if (info->multi_irqs) { 2726 if (info->err_mgmt_irqs) 2727 irq = platform_get_irq_byname(pdev, "line3"); 2728 else 2729 irq = platform_get_irq_byname(pdev, "ch24"); 2730 if (irq < 0) { 2731 error = irq; 2732 goto out_release; 2733 } 2734 priv->emac_irq = irq; 2735 for (i = 0; i < NUM_RX_QUEUE; i++) { 2736 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); 2737 if (irq < 0) { 2738 error = irq; 2739 goto out_release; 2740 } 2741 priv->rx_irqs[i] = irq; 2742 } 2743 for (i = 0; i < NUM_TX_QUEUE; i++) { 2744 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); 2745 if (irq < 0) { 2746 error = irq; 2747 goto out_release; 2748 } 2749 priv->tx_irqs[i] = irq; 2750 } 2751 2752 if (info->err_mgmt_irqs) { 2753 irq = platform_get_irq_byname(pdev, "err_a"); 2754 if (irq < 0) { 2755 error = irq; 2756 goto out_release; 2757 } 2758 priv->erra_irq = irq; 2759 2760 irq = platform_get_irq_byname(pdev, "mgmt_a"); 2761 if (irq < 0) { 2762 error = irq; 2763 goto out_release; 2764 } 2765 priv->mgmta_irq = irq; 2766 } 2767 } 2768 2769 priv->clk = devm_clk_get(&pdev->dev, NULL); 2770 if (IS_ERR(priv->clk)) { 2771 error = PTR_ERR(priv->clk); 2772 goto out_release; 2773 } 2774 2775 priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk"); 2776 if (IS_ERR(priv->refclk)) { 2777 error = PTR_ERR(priv->refclk); 2778 goto out_release; 2779 } 2780 clk_prepare_enable(priv->refclk); 2781 2782 if (info->gptp_ref_clk) { 2783 priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp"); 2784 if (IS_ERR(priv->gptp_clk)) { 2785 error = PTR_ERR(priv->gptp_clk); 2786 goto out_disable_refclk; 2787 } 2788 clk_prepare_enable(priv->gptp_clk); 2789 } 2790 2791 ndev->max_mtu = info->rx_max_buf_size - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 2792 ndev->min_mtu = ETH_MIN_MTU; 2793 2794 /* FIXME: R-Car Gen2 has 4byte alignment restriction for tx buffer 2795 * Use two descriptor to handle such situation. First descriptor to 2796 * handle aligned data buffer and second descriptor to handle the 2797 * overflow data because of alignment. 2798 */ 2799 priv->num_tx_desc = info->aligned_tx ? 2 : 1; 2800 2801 /* Set function */ 2802 ndev->netdev_ops = &ravb_netdev_ops; 2803 ndev->ethtool_ops = &ravb_ethtool_ops; 2804 2805 /* Set AVB config mode */ 2806 error = ravb_set_config_mode(ndev); 2807 if (error) 2808 goto out_disable_gptp_clk; 2809 2810 if (info->gptp || info->ccc_gac) { 2811 /* Set GTI value */ 2812 error = ravb_set_gti(ndev); 2813 if (error) 2814 goto out_disable_gptp_clk; 2815 2816 /* Request GTI loading */ 2817 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2818 } 2819 2820 if (info->internal_delay) { 2821 ravb_parse_delay_mode(np, ndev); 2822 ravb_set_delay_mode(ndev); 2823 } 2824 2825 /* Allocate descriptor base address table */ 2826 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 2827 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 2828 &priv->desc_bat_dma, GFP_KERNEL); 2829 if (!priv->desc_bat) { 2830 dev_err(&pdev->dev, 2831 "Cannot allocate desc base address table (size %d bytes)\n", 2832 priv->desc_bat_size); 2833 error = -ENOMEM; 2834 goto out_disable_gptp_clk; 2835 } 2836 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 2837 priv->desc_bat[q].die_dt = DT_EOS; 2838 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2839 2840 /* Initialise HW timestamp list */ 2841 INIT_LIST_HEAD(&priv->ts_skb_list); 2842 2843 /* Initialise PTP Clock driver */ 2844 if (info->ccc_gac) 2845 ravb_ptp_init(ndev, pdev); 2846 2847 /* Debug message level */ 2848 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 2849 2850 /* Read and set MAC address */ 2851 ravb_read_mac_address(np, ndev); 2852 if (!is_valid_ether_addr(ndev->dev_addr)) { 2853 dev_warn(&pdev->dev, 2854 "no valid MAC address supplied, using a random one\n"); 2855 eth_hw_addr_random(ndev); 2856 } 2857 2858 /* MDIO bus init */ 2859 error = ravb_mdio_init(priv); 2860 if (error) { 2861 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 2862 goto out_dma_free; 2863 } 2864 2865 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll); 2866 if (info->nc_queues) 2867 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll); 2868 2869 /* Network device register */ 2870 error = register_netdev(ndev); 2871 if (error) 2872 goto out_napi_del; 2873 2874 device_set_wakeup_capable(&pdev->dev, 1); 2875 2876 /* Print device information */ 2877 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 2878 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2879 2880 platform_set_drvdata(pdev, ndev); 2881 2882 return 0; 2883 2884 out_napi_del: 2885 if (info->nc_queues) 2886 netif_napi_del(&priv->napi[RAVB_NC]); 2887 2888 netif_napi_del(&priv->napi[RAVB_BE]); 2889 ravb_mdio_release(priv); 2890 out_dma_free: 2891 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2892 priv->desc_bat_dma); 2893 2894 /* Stop PTP Clock driver */ 2895 if (info->ccc_gac) 2896 ravb_ptp_stop(ndev); 2897 out_disable_gptp_clk: 2898 clk_disable_unprepare(priv->gptp_clk); 2899 out_disable_refclk: 2900 clk_disable_unprepare(priv->refclk); 2901 out_release: 2902 pm_runtime_put(&pdev->dev); 2903 out_rpm_disable: 2904 pm_runtime_disable(&pdev->dev); 2905 reset_control_assert(rstc); 2906 out_free_netdev: 2907 free_netdev(ndev); 2908 return error; 2909 } 2910 2911 static void ravb_remove(struct platform_device *pdev) 2912 { 2913 struct net_device *ndev = platform_get_drvdata(pdev); 2914 struct ravb_private *priv = netdev_priv(ndev); 2915 const struct ravb_hw_info *info = priv->info; 2916 2917 unregister_netdev(ndev); 2918 if (info->nc_queues) 2919 netif_napi_del(&priv->napi[RAVB_NC]); 2920 netif_napi_del(&priv->napi[RAVB_BE]); 2921 2922 ravb_mdio_release(priv); 2923 2924 /* Stop PTP Clock driver */ 2925 if (info->ccc_gac) 2926 ravb_ptp_stop(ndev); 2927 2928 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2929 priv->desc_bat_dma); 2930 2931 ravb_set_opmode(ndev, CCC_OPC_RESET); 2932 2933 clk_disable_unprepare(priv->gptp_clk); 2934 clk_disable_unprepare(priv->refclk); 2935 2936 pm_runtime_put_sync(&pdev->dev); 2937 pm_runtime_disable(&pdev->dev); 2938 reset_control_assert(priv->rstc); 2939 free_netdev(ndev); 2940 platform_set_drvdata(pdev, NULL); 2941 } 2942 2943 static int ravb_wol_setup(struct net_device *ndev) 2944 { 2945 struct ravb_private *priv = netdev_priv(ndev); 2946 const struct ravb_hw_info *info = priv->info; 2947 2948 /* Disable interrupts by clearing the interrupt masks. */ 2949 ravb_write(ndev, 0, RIC0); 2950 ravb_write(ndev, 0, RIC2); 2951 ravb_write(ndev, 0, TIC); 2952 2953 /* Only allow ECI interrupts */ 2954 synchronize_irq(priv->emac_irq); 2955 if (info->nc_queues) 2956 napi_disable(&priv->napi[RAVB_NC]); 2957 napi_disable(&priv->napi[RAVB_BE]); 2958 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 2959 2960 /* Enable MagicPacket */ 2961 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 2962 2963 return enable_irq_wake(priv->emac_irq); 2964 } 2965 2966 static int ravb_wol_restore(struct net_device *ndev) 2967 { 2968 struct ravb_private *priv = netdev_priv(ndev); 2969 const struct ravb_hw_info *info = priv->info; 2970 2971 if (info->nc_queues) 2972 napi_enable(&priv->napi[RAVB_NC]); 2973 napi_enable(&priv->napi[RAVB_BE]); 2974 2975 /* Disable MagicPacket */ 2976 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 2977 2978 ravb_close(ndev); 2979 2980 return disable_irq_wake(priv->emac_irq); 2981 } 2982 2983 static int __maybe_unused ravb_suspend(struct device *dev) 2984 { 2985 struct net_device *ndev = dev_get_drvdata(dev); 2986 struct ravb_private *priv = netdev_priv(ndev); 2987 int ret; 2988 2989 if (!netif_running(ndev)) 2990 return 0; 2991 2992 netif_device_detach(ndev); 2993 2994 if (priv->wol_enabled) 2995 ret = ravb_wol_setup(ndev); 2996 else 2997 ret = ravb_close(ndev); 2998 2999 if (priv->info->ccc_gac) 3000 ravb_ptp_stop(ndev); 3001 3002 return ret; 3003 } 3004 3005 static int __maybe_unused ravb_resume(struct device *dev) 3006 { 3007 struct net_device *ndev = dev_get_drvdata(dev); 3008 struct ravb_private *priv = netdev_priv(ndev); 3009 const struct ravb_hw_info *info = priv->info; 3010 int ret = 0; 3011 3012 /* If WoL is enabled set reset mode to rearm the WoL logic */ 3013 if (priv->wol_enabled) { 3014 ret = ravb_set_opmode(ndev, CCC_OPC_RESET); 3015 if (ret) 3016 return ret; 3017 } 3018 3019 /* All register have been reset to default values. 3020 * Restore all registers which where setup at probe time and 3021 * reopen device if it was running before system suspended. 3022 */ 3023 3024 /* Set AVB config mode */ 3025 ret = ravb_set_config_mode(ndev); 3026 if (ret) 3027 return ret; 3028 3029 if (info->gptp || info->ccc_gac) { 3030 /* Set GTI value */ 3031 ret = ravb_set_gti(ndev); 3032 if (ret) 3033 return ret; 3034 3035 /* Request GTI loading */ 3036 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 3037 } 3038 3039 if (info->internal_delay) 3040 ravb_set_delay_mode(ndev); 3041 3042 /* Restore descriptor base address table */ 3043 ravb_write(ndev, priv->desc_bat_dma, DBAT); 3044 3045 if (priv->info->ccc_gac) 3046 ravb_ptp_init(ndev, priv->pdev); 3047 3048 if (netif_running(ndev)) { 3049 if (priv->wol_enabled) { 3050 ret = ravb_wol_restore(ndev); 3051 if (ret) 3052 return ret; 3053 } 3054 ret = ravb_open(ndev); 3055 if (ret < 0) 3056 return ret; 3057 ravb_set_rx_mode(ndev); 3058 netif_device_attach(ndev); 3059 } 3060 3061 return ret; 3062 } 3063 3064 static int __maybe_unused ravb_runtime_nop(struct device *dev) 3065 { 3066 /* Runtime PM callback shared between ->runtime_suspend() 3067 * and ->runtime_resume(). Simply returns success. 3068 * 3069 * This driver re-initializes all registers after 3070 * pm_runtime_get_sync() anyway so there is no need 3071 * to save and restore registers here. 3072 */ 3073 return 0; 3074 } 3075 3076 static const struct dev_pm_ops ravb_dev_pm_ops = { 3077 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 3078 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL) 3079 }; 3080 3081 static struct platform_driver ravb_driver = { 3082 .probe = ravb_probe, 3083 .remove_new = ravb_remove, 3084 .driver = { 3085 .name = "ravb", 3086 .pm = &ravb_dev_pm_ops, 3087 .of_match_table = ravb_match_table, 3088 }, 3089 }; 3090 3091 module_platform_driver(ravb_driver); 3092 3093 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 3094 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 3095 MODULE_LICENSE("GPL v2"); 3096