1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet AVB device driver 3 * 4 * Copyright (C) 2014-2019 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * Based on the SuperH Ethernet driver 9 */ 10 11 #include <linux/cache.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_vlan.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/module.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/of.h> 24 #include <linux/of_mdio.h> 25 #include <linux/of_net.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/slab.h> 29 #include <linux/spinlock.h> 30 #include <linux/reset.h> 31 #include <linux/math64.h> 32 #include <net/ip.h> 33 #include <net/page_pool/helpers.h> 34 35 #include "ravb.h" 36 37 #define RAVB_DEF_MSG_ENABLE \ 38 (NETIF_MSG_LINK | \ 39 NETIF_MSG_TIMER | \ 40 NETIF_MSG_RX_ERR | \ 41 NETIF_MSG_TX_ERR) 42 43 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 44 u32 set) 45 { 46 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 47 } 48 49 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 50 { 51 int i; 52 53 for (i = 0; i < 10000; i++) { 54 if ((ravb_read(ndev, reg) & mask) == value) 55 return 0; 56 udelay(10); 57 } 58 return -ETIMEDOUT; 59 } 60 61 static int ravb_set_opmode(struct net_device *ndev, u32 opmode) 62 { 63 u32 csr_ops = 1U << (opmode & CCC_OPC); 64 u32 ccc_mask = CCC_OPC; 65 int error; 66 67 /* If gPTP active in config mode is supported it needs to be configured 68 * along with CSEL and operating mode in the same access. This is a 69 * hardware limitation. 70 */ 71 if (opmode & CCC_GAC) 72 ccc_mask |= CCC_GAC | CCC_CSEL; 73 74 /* Set operating mode */ 75 ravb_modify(ndev, CCC, ccc_mask, opmode); 76 /* Check if the operating mode is changed to the requested one */ 77 error = ravb_wait(ndev, CSR, CSR_OPS, csr_ops); 78 if (error) { 79 netdev_err(ndev, "failed to switch device to requested mode (%u)\n", 80 opmode & CCC_OPC); 81 } 82 83 return error; 84 } 85 86 static void ravb_set_rate_gbeth(struct net_device *ndev) 87 { 88 struct ravb_private *priv = netdev_priv(ndev); 89 90 switch (priv->speed) { 91 case 10: /* 10BASE */ 92 ravb_write(ndev, GBETH_GECMR_SPEED_10, GECMR); 93 break; 94 case 100: /* 100BASE */ 95 ravb_write(ndev, GBETH_GECMR_SPEED_100, GECMR); 96 break; 97 case 1000: /* 1000BASE */ 98 ravb_write(ndev, GBETH_GECMR_SPEED_1000, GECMR); 99 break; 100 } 101 } 102 103 static void ravb_set_rate_rcar(struct net_device *ndev) 104 { 105 struct ravb_private *priv = netdev_priv(ndev); 106 107 switch (priv->speed) { 108 case 100: /* 100BASE */ 109 ravb_write(ndev, GECMR_SPEED_100, GECMR); 110 break; 111 case 1000: /* 1000BASE */ 112 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 113 break; 114 } 115 } 116 117 /* Get MAC address from the MAC address registers 118 * 119 * Ethernet AVB device doesn't have ROM for MAC address. 120 * This function gets the MAC address that was used by a bootloader. 121 */ 122 static void ravb_read_mac_address(struct device_node *np, 123 struct net_device *ndev) 124 { 125 int ret; 126 127 ret = of_get_ethdev_address(np, ndev); 128 if (ret) { 129 u32 mahr = ravb_read(ndev, MAHR); 130 u32 malr = ravb_read(ndev, MALR); 131 u8 addr[ETH_ALEN]; 132 133 addr[0] = (mahr >> 24) & 0xFF; 134 addr[1] = (mahr >> 16) & 0xFF; 135 addr[2] = (mahr >> 8) & 0xFF; 136 addr[3] = (mahr >> 0) & 0xFF; 137 addr[4] = (malr >> 8) & 0xFF; 138 addr[5] = (malr >> 0) & 0xFF; 139 eth_hw_addr_set(ndev, addr); 140 } 141 } 142 143 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 144 { 145 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 146 mdiobb); 147 148 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 149 } 150 151 /* MDC pin control */ 152 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 153 { 154 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 155 } 156 157 /* Data I/O pin control */ 158 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 159 { 160 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 161 } 162 163 /* Set data bit */ 164 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 165 { 166 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 167 } 168 169 /* Get data bit */ 170 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 171 { 172 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 173 mdiobb); 174 175 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 176 } 177 178 /* MDIO bus control struct */ 179 static const struct mdiobb_ops bb_ops = { 180 .owner = THIS_MODULE, 181 .set_mdc = ravb_set_mdc, 182 .set_mdio_dir = ravb_set_mdio_dir, 183 .set_mdio_data = ravb_set_mdio_data, 184 .get_mdio_data = ravb_get_mdio_data, 185 }; 186 187 static struct ravb_rx_desc * 188 ravb_rx_get_desc(struct ravb_private *priv, unsigned int q, 189 unsigned int i) 190 { 191 return priv->rx_ring[q].raw + priv->info->rx_desc_size * i; 192 } 193 194 /* Free TX skb function for AVB-IP */ 195 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 196 { 197 struct ravb_private *priv = netdev_priv(ndev); 198 struct net_device_stats *stats = &priv->stats[q]; 199 unsigned int num_tx_desc = priv->num_tx_desc; 200 struct ravb_tx_desc *desc; 201 unsigned int entry; 202 int free_num = 0; 203 u32 size; 204 205 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 206 bool txed; 207 208 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 209 num_tx_desc); 210 desc = &priv->tx_ring[q][entry]; 211 txed = desc->die_dt == DT_FEMPTY; 212 if (free_txed_only && !txed) 213 break; 214 /* Descriptor type must be checked before all other reads */ 215 dma_rmb(); 216 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 217 /* Free the original skb. */ 218 if (priv->tx_skb[q][entry / num_tx_desc]) { 219 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 220 size, DMA_TO_DEVICE); 221 /* Last packet descriptor? */ 222 if (entry % num_tx_desc == num_tx_desc - 1) { 223 entry /= num_tx_desc; 224 dev_kfree_skb_any(priv->tx_skb[q][entry]); 225 priv->tx_skb[q][entry] = NULL; 226 if (txed) 227 stats->tx_packets++; 228 } 229 free_num++; 230 } 231 if (txed) 232 stats->tx_bytes += size; 233 desc->die_dt = DT_EEMPTY; 234 } 235 return free_num; 236 } 237 238 static void ravb_rx_ring_free(struct net_device *ndev, int q) 239 { 240 struct ravb_private *priv = netdev_priv(ndev); 241 unsigned int ring_size; 242 243 if (!priv->rx_ring[q].raw) 244 return; 245 246 ring_size = priv->info->rx_desc_size * (priv->num_rx_ring[q] + 1); 247 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q].raw, 248 priv->rx_desc_dma[q]); 249 priv->rx_ring[q].raw = NULL; 250 } 251 252 /* Free skb's and DMA buffers for Ethernet AVB */ 253 static void ravb_ring_free(struct net_device *ndev, int q) 254 { 255 struct ravb_private *priv = netdev_priv(ndev); 256 unsigned int num_tx_desc = priv->num_tx_desc; 257 unsigned int ring_size; 258 unsigned int i; 259 260 ravb_rx_ring_free(ndev, q); 261 262 if (priv->tx_ring[q]) { 263 ravb_tx_free(ndev, q, false); 264 265 ring_size = sizeof(struct ravb_tx_desc) * 266 (priv->num_tx_ring[q] * num_tx_desc + 1); 267 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 268 priv->tx_desc_dma[q]); 269 priv->tx_ring[q] = NULL; 270 } 271 272 /* Free RX buffers */ 273 for (i = 0; i < priv->num_rx_ring[q]; i++) { 274 if (priv->rx_buffers[q][i].page) 275 page_pool_put_page(priv->rx_pool[q], 276 priv->rx_buffers[q][i].page, 277 0, true); 278 } 279 kfree(priv->rx_buffers[q]); 280 priv->rx_buffers[q] = NULL; 281 page_pool_destroy(priv->rx_pool[q]); 282 283 /* Free aligned TX buffers */ 284 kfree(priv->tx_align[q]); 285 priv->tx_align[q] = NULL; 286 287 /* Free TX skb ringbuffer. 288 * SKBs are freed by ravb_tx_free() call above. 289 */ 290 kfree(priv->tx_skb[q]); 291 priv->tx_skb[q] = NULL; 292 } 293 294 static int 295 ravb_alloc_rx_buffer(struct net_device *ndev, int q, u32 entry, gfp_t gfp_mask, 296 struct ravb_rx_desc *rx_desc) 297 { 298 struct ravb_private *priv = netdev_priv(ndev); 299 const struct ravb_hw_info *info = priv->info; 300 struct ravb_rx_buffer *rx_buff; 301 dma_addr_t dma_addr; 302 unsigned int size; 303 304 rx_buff = &priv->rx_buffers[q][entry]; 305 size = info->rx_buffer_size; 306 rx_buff->page = page_pool_alloc(priv->rx_pool[q], &rx_buff->offset, 307 &size, gfp_mask); 308 if (unlikely(!rx_buff->page)) { 309 /* We just set the data size to 0 for a failed mapping which 310 * should prevent DMA from happening... 311 */ 312 rx_desc->ds_cc = cpu_to_le16(0); 313 return -ENOMEM; 314 } 315 316 dma_addr = page_pool_get_dma_addr(rx_buff->page) + rx_buff->offset; 317 dma_sync_single_for_device(ndev->dev.parent, dma_addr, 318 info->rx_buffer_size, DMA_FROM_DEVICE); 319 rx_desc->dptr = cpu_to_le32(dma_addr); 320 321 /* The end of the RX buffer is used to store skb shared data, so we need 322 * to ensure that the hardware leaves enough space for this. 323 */ 324 rx_desc->ds_cc = cpu_to_le16(info->rx_buffer_size - 325 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) - 326 ETH_FCS_LEN + sizeof(__sum16)); 327 return 0; 328 } 329 330 static u32 331 ravb_rx_ring_refill(struct net_device *ndev, int q, u32 count, gfp_t gfp_mask) 332 { 333 struct ravb_private *priv = netdev_priv(ndev); 334 struct ravb_rx_desc *rx_desc; 335 u32 i, entry; 336 337 for (i = 0; i < count; i++) { 338 entry = (priv->dirty_rx[q] + i) % priv->num_rx_ring[q]; 339 rx_desc = ravb_rx_get_desc(priv, q, entry); 340 341 if (!priv->rx_buffers[q][entry].page) { 342 if (unlikely(ravb_alloc_rx_buffer(ndev, q, entry, 343 gfp_mask, rx_desc))) 344 break; 345 } 346 /* Descriptor type must be set after all the above writes */ 347 dma_wmb(); 348 rx_desc->die_dt = DT_FEMPTY; 349 } 350 351 return i; 352 } 353 354 /* Format skb and descriptor buffer for Ethernet AVB */ 355 static void ravb_ring_format(struct net_device *ndev, int q) 356 { 357 struct ravb_private *priv = netdev_priv(ndev); 358 unsigned int num_tx_desc = priv->num_tx_desc; 359 struct ravb_rx_desc *rx_desc; 360 struct ravb_tx_desc *tx_desc; 361 struct ravb_desc *desc; 362 unsigned int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 363 num_tx_desc; 364 unsigned int i; 365 366 priv->cur_rx[q] = 0; 367 priv->cur_tx[q] = 0; 368 priv->dirty_rx[q] = 0; 369 priv->dirty_tx[q] = 0; 370 371 /* Regular RX descriptors have already been initialized by 372 * ravb_rx_ring_refill(), we just need to initialize the final link 373 * descriptor. 374 */ 375 rx_desc = ravb_rx_get_desc(priv, q, priv->num_rx_ring[q]); 376 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 377 rx_desc->die_dt = DT_LINKFIX; /* type */ 378 379 memset(priv->tx_ring[q], 0, tx_ring_size); 380 /* Build TX ring buffer */ 381 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 382 i++, tx_desc++) { 383 tx_desc->die_dt = DT_EEMPTY; 384 if (num_tx_desc > 1) { 385 tx_desc++; 386 tx_desc->die_dt = DT_EEMPTY; 387 } 388 } 389 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 390 tx_desc->die_dt = DT_LINKFIX; /* type */ 391 392 /* RX descriptor base address for best effort */ 393 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 394 desc->die_dt = DT_LINKFIX; /* type */ 395 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 396 397 /* TX descriptor base address for best effort */ 398 desc = &priv->desc_bat[q]; 399 desc->die_dt = DT_LINKFIX; /* type */ 400 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 401 } 402 403 static void *ravb_alloc_rx_desc(struct net_device *ndev, int q) 404 { 405 struct ravb_private *priv = netdev_priv(ndev); 406 unsigned int ring_size; 407 408 ring_size = priv->info->rx_desc_size * (priv->num_rx_ring[q] + 1); 409 410 priv->rx_ring[q].raw = dma_alloc_coherent(ndev->dev.parent, ring_size, 411 &priv->rx_desc_dma[q], 412 GFP_KERNEL); 413 414 return priv->rx_ring[q].raw; 415 } 416 417 /* Init skb and descriptor buffer for Ethernet AVB */ 418 static int ravb_ring_init(struct net_device *ndev, int q) 419 { 420 struct ravb_private *priv = netdev_priv(ndev); 421 unsigned int num_tx_desc = priv->num_tx_desc; 422 struct page_pool_params params = { 423 .order = 0, 424 .flags = PP_FLAG_DMA_MAP, 425 .pool_size = priv->num_rx_ring[q], 426 .nid = NUMA_NO_NODE, 427 .dev = ndev->dev.parent, 428 .dma_dir = DMA_FROM_DEVICE, 429 }; 430 unsigned int ring_size; 431 u32 num_filled; 432 433 /* Allocate RX page pool and buffers */ 434 priv->rx_pool[q] = page_pool_create(¶ms); 435 if (IS_ERR(priv->rx_pool[q])) 436 goto error; 437 438 /* Allocate RX buffers */ 439 priv->rx_buffers[q] = kcalloc(priv->num_rx_ring[q], 440 sizeof(*priv->rx_buffers[q]), GFP_KERNEL); 441 if (!priv->rx_buffers[q]) 442 goto error; 443 444 /* Allocate TX skb rings */ 445 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 446 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 447 if (!priv->tx_skb[q]) 448 goto error; 449 450 /* Allocate all RX descriptors. */ 451 if (!ravb_alloc_rx_desc(ndev, q)) 452 goto error; 453 454 /* Populate RX ring buffer. */ 455 priv->dirty_rx[q] = 0; 456 ring_size = priv->info->rx_desc_size * priv->num_rx_ring[q]; 457 memset(priv->rx_ring[q].raw, 0, ring_size); 458 num_filled = ravb_rx_ring_refill(ndev, q, priv->num_rx_ring[q], 459 GFP_KERNEL); 460 if (num_filled != priv->num_rx_ring[q]) 461 goto error; 462 463 if (num_tx_desc > 1) { 464 /* Allocate rings for the aligned buffers */ 465 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 466 DPTR_ALIGN - 1, GFP_KERNEL); 467 if (!priv->tx_align[q]) 468 goto error; 469 } 470 471 /* Allocate all TX descriptors. */ 472 ring_size = sizeof(struct ravb_tx_desc) * 473 (priv->num_tx_ring[q] * num_tx_desc + 1); 474 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 475 &priv->tx_desc_dma[q], 476 GFP_KERNEL); 477 if (!priv->tx_ring[q]) 478 goto error; 479 480 return 0; 481 482 error: 483 ravb_ring_free(ndev, q); 484 485 return -ENOMEM; 486 } 487 488 static void ravb_csum_init_gbeth(struct net_device *ndev) 489 { 490 bool tx_enable = ndev->features & NETIF_F_HW_CSUM; 491 bool rx_enable = ndev->features & NETIF_F_RXCSUM; 492 493 if (!(tx_enable || rx_enable)) 494 goto done; 495 496 ravb_write(ndev, 0, CSR0); 497 if (ravb_wait(ndev, CSR0, CSR0_TPE | CSR0_RPE, 0)) { 498 netdev_err(ndev, "Timeout enabling hardware checksum\n"); 499 500 if (tx_enable) 501 ndev->features &= ~NETIF_F_HW_CSUM; 502 503 if (rx_enable) 504 ndev->features &= ~NETIF_F_RXCSUM; 505 } else { 506 if (tx_enable) 507 ravb_write(ndev, CSR1_TIP4 | CSR1_TTCP4 | CSR1_TUDP4, CSR1); 508 509 if (rx_enable) 510 ravb_write(ndev, CSR2_RIP4 | CSR2_RTCP4 | CSR2_RUDP4 | CSR2_RICMP4, 511 CSR2); 512 } 513 514 done: 515 ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0); 516 } 517 518 static void ravb_emac_init_gbeth(struct net_device *ndev) 519 { 520 struct ravb_private *priv = netdev_priv(ndev); 521 522 if (priv->phy_interface == PHY_INTERFACE_MODE_MII) { 523 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35); 524 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0); 525 } else { 526 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_RGMII, CXR35); 527 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 528 CXR31_SEL_LINK0); 529 } 530 531 /* Receive frame limit set register */ 532 ravb_write(ndev, priv->info->rx_max_frame_size + ETH_FCS_LEN, RFLR); 533 534 /* EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through */ 535 ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) | 536 ECMR_TE | ECMR_RE | ECMR_RCPT | 537 ECMR_TXF | ECMR_RXF, ECMR); 538 539 ravb_set_rate_gbeth(ndev); 540 541 /* Set MAC address */ 542 ravb_write(ndev, 543 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 544 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 545 ravb_write(ndev, (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 546 547 /* E-MAC status register clear */ 548 ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR); 549 550 ravb_csum_init_gbeth(ndev); 551 552 /* E-MAC interrupt enable register */ 553 ravb_write(ndev, ECSIPR_ICDIP, ECSIPR); 554 } 555 556 static void ravb_emac_init_rcar(struct net_device *ndev) 557 { 558 /* Receive frame limit set register */ 559 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 560 561 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 562 ravb_write(ndev, ECMR_ZPF | ECMR_DM | 563 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 564 ECMR_TE | ECMR_RE, ECMR); 565 566 ravb_set_rate_rcar(ndev); 567 568 /* Set MAC address */ 569 ravb_write(ndev, 570 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 571 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 572 ravb_write(ndev, 573 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 574 575 /* E-MAC status register clear */ 576 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 577 578 /* E-MAC interrupt enable register */ 579 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 580 } 581 582 static void ravb_emac_init_rcar_gen4(struct net_device *ndev) 583 { 584 struct ravb_private *priv = netdev_priv(ndev); 585 bool mii = priv->phy_interface == PHY_INTERFACE_MODE_MII; 586 587 ravb_modify(ndev, APSR, APSR_MIISELECT, mii ? APSR_MIISELECT : 0); 588 589 ravb_emac_init_rcar(ndev); 590 } 591 592 /* E-MAC init function */ 593 static void ravb_emac_init(struct net_device *ndev) 594 { 595 struct ravb_private *priv = netdev_priv(ndev); 596 const struct ravb_hw_info *info = priv->info; 597 598 info->emac_init(ndev); 599 } 600 601 static int ravb_dmac_init_gbeth(struct net_device *ndev) 602 { 603 struct ravb_private *priv = netdev_priv(ndev); 604 int error; 605 606 error = ravb_ring_init(ndev, RAVB_BE); 607 if (error) 608 return error; 609 610 /* Descriptor format */ 611 ravb_ring_format(ndev, RAVB_BE); 612 613 /* Set DMAC RX */ 614 ravb_write(ndev, 0x60000000, RCR); 615 616 /* Set Max Frame Length (RTC) */ 617 ravb_write(ndev, 0x7ffc0000 | priv->info->rx_max_frame_size, RTC); 618 619 /* Set FIFO size */ 620 ravb_write(ndev, 0x00222200, TGC); 621 622 ravb_write(ndev, 0, TCCR); 623 624 /* Frame receive */ 625 ravb_write(ndev, RIC0_FRE0, RIC0); 626 /* Disable FIFO full warning */ 627 ravb_write(ndev, 0x0, RIC1); 628 /* Receive FIFO full error, descriptor empty */ 629 ravb_write(ndev, RIC2_QFE0 | RIC2_RFFE, RIC2); 630 631 ravb_write(ndev, TIC_FTE0, TIC); 632 633 return 0; 634 } 635 636 static int ravb_dmac_init_rcar(struct net_device *ndev) 637 { 638 struct ravb_private *priv = netdev_priv(ndev); 639 const struct ravb_hw_info *info = priv->info; 640 int error; 641 642 error = ravb_ring_init(ndev, RAVB_BE); 643 if (error) 644 return error; 645 error = ravb_ring_init(ndev, RAVB_NC); 646 if (error) { 647 ravb_ring_free(ndev, RAVB_BE); 648 return error; 649 } 650 651 /* Descriptor format */ 652 ravb_ring_format(ndev, RAVB_BE); 653 ravb_ring_format(ndev, RAVB_NC); 654 655 /* Set AVB RX */ 656 ravb_write(ndev, 657 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 658 659 /* Set FIFO size */ 660 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC); 661 662 /* Timestamp enable */ 663 ravb_write(ndev, TCCR_TFEN, TCCR); 664 665 /* Interrupt init: */ 666 if (info->multi_irqs) { 667 /* Clear DIL.DPLx */ 668 ravb_write(ndev, 0, DIL); 669 /* Set queue specific interrupt */ 670 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 671 } 672 /* Frame receive */ 673 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 674 /* Disable FIFO full warning */ 675 ravb_write(ndev, 0, RIC1); 676 /* Receive FIFO full error, descriptor empty */ 677 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 678 /* Frame transmitted, timestamp FIFO updated */ 679 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 680 681 return 0; 682 } 683 684 /* Device init function for Ethernet AVB */ 685 static int ravb_dmac_init(struct net_device *ndev) 686 { 687 struct ravb_private *priv = netdev_priv(ndev); 688 const struct ravb_hw_info *info = priv->info; 689 int error; 690 691 /* Set CONFIG mode */ 692 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 693 if (error) 694 return error; 695 696 error = info->dmac_init(ndev); 697 if (error) 698 return error; 699 700 /* Setting the control will start the AVB-DMAC process. */ 701 return ravb_set_opmode(ndev, CCC_OPC_OPERATION); 702 } 703 704 static void ravb_get_tx_tstamp(struct net_device *ndev) 705 { 706 struct ravb_private *priv = netdev_priv(ndev); 707 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 708 struct skb_shared_hwtstamps shhwtstamps; 709 struct sk_buff *skb; 710 struct timespec64 ts; 711 u16 tag, tfa_tag; 712 int count; 713 u32 tfa2; 714 715 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 716 while (count--) { 717 tfa2 = ravb_read(ndev, TFA2); 718 tfa_tag = (tfa2 & TFA2_TST) >> 16; 719 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 720 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 721 ravb_read(ndev, TFA1); 722 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 723 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 724 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 725 list) { 726 skb = ts_skb->skb; 727 tag = ts_skb->tag; 728 list_del(&ts_skb->list); 729 kfree(ts_skb); 730 if (tag == tfa_tag) { 731 skb_tstamp_tx(skb, &shhwtstamps); 732 dev_consume_skb_any(skb); 733 break; 734 } else { 735 dev_kfree_skb_any(skb); 736 } 737 } 738 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 739 } 740 } 741 742 static void ravb_rx_csum_gbeth(struct sk_buff *skb) 743 { 744 struct skb_shared_info *shinfo = skb_shinfo(skb); 745 __wsum csum_ip_hdr, csum_proto; 746 skb_frag_t *last_frag; 747 u8 *hw_csum; 748 749 /* The hardware checksum status is contained in sizeof(__sum16) * 2 = 4 750 * bytes appended to packet data. First 2 bytes is ip header checksum 751 * and last 2 bytes is protocol checksum. 752 */ 753 if (unlikely(skb->len < sizeof(__sum16) * 2)) 754 return; 755 756 if (skb_is_nonlinear(skb)) { 757 last_frag = &shinfo->frags[shinfo->nr_frags - 1]; 758 hw_csum = skb_frag_address(last_frag) + 759 skb_frag_size(last_frag); 760 } else { 761 hw_csum = skb_tail_pointer(skb); 762 } 763 764 hw_csum -= sizeof(__sum16); 765 csum_proto = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 766 767 hw_csum -= sizeof(__sum16); 768 csum_ip_hdr = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 769 770 if (skb_is_nonlinear(skb)) 771 skb_frag_size_sub(last_frag, 2 * sizeof(__sum16)); 772 else 773 skb_trim(skb, skb->len - 2 * sizeof(__sum16)); 774 775 /* TODO: IPV6 Rx checksum */ 776 if (skb->protocol == htons(ETH_P_IP) && !csum_ip_hdr && !csum_proto) 777 skb->ip_summed = CHECKSUM_UNNECESSARY; 778 } 779 780 static void ravb_rx_csum(struct sk_buff *skb) 781 { 782 u8 *hw_csum; 783 784 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes 785 * appended to packet data 786 */ 787 if (unlikely(skb->len < sizeof(__sum16))) 788 return; 789 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); 790 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 791 skb->ip_summed = CHECKSUM_COMPLETE; 792 skb_trim(skb, skb->len - sizeof(__sum16)); 793 } 794 795 /* Packet receive function for Gigabit Ethernet */ 796 static int ravb_rx_gbeth(struct net_device *ndev, int budget, int q) 797 { 798 struct ravb_private *priv = netdev_priv(ndev); 799 const struct ravb_hw_info *info = priv->info; 800 struct net_device_stats *stats; 801 struct ravb_rx_desc *desc; 802 struct sk_buff *skb; 803 int rx_packets = 0; 804 u8 desc_status; 805 u16 desc_len; 806 u8 die_dt; 807 int entry; 808 int limit; 809 int i; 810 811 limit = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q]; 812 stats = &priv->stats[q]; 813 814 for (i = 0; i < limit; i++, priv->cur_rx[q]++) { 815 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 816 desc = &priv->rx_ring[q].desc[entry]; 817 if (rx_packets == budget || desc->die_dt == DT_FEMPTY) 818 break; 819 820 /* Descriptor type must be checked before all other reads */ 821 dma_rmb(); 822 desc_status = desc->msc; 823 desc_len = le16_to_cpu(desc->ds_cc) & RX_DS; 824 825 /* We use 0-byte descriptors to mark the DMA mapping errors */ 826 if (!desc_len) 827 continue; 828 829 if (desc_status & MSC_MC) 830 stats->multicast++; 831 832 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | MSC_CEEF)) { 833 stats->rx_errors++; 834 if (desc_status & MSC_CRC) 835 stats->rx_crc_errors++; 836 if (desc_status & MSC_RFE) 837 stats->rx_frame_errors++; 838 if (desc_status & (MSC_RTLF | MSC_RTSF)) 839 stats->rx_length_errors++; 840 if (desc_status & MSC_CEEF) 841 stats->rx_missed_errors++; 842 } else { 843 struct ravb_rx_buffer *rx_buff; 844 void *rx_addr; 845 846 rx_buff = &priv->rx_buffers[q][entry]; 847 rx_addr = page_address(rx_buff->page) + rx_buff->offset; 848 die_dt = desc->die_dt & 0xF0; 849 dma_sync_single_for_cpu(ndev->dev.parent, 850 le32_to_cpu(desc->dptr), 851 desc_len, DMA_FROM_DEVICE); 852 853 switch (die_dt) { 854 case DT_FSINGLE: 855 case DT_FSTART: 856 /* Start of packet: Set initial data length. */ 857 skb = napi_build_skb(rx_addr, 858 info->rx_buffer_size); 859 if (unlikely(!skb)) { 860 stats->rx_errors++; 861 page_pool_put_page(priv->rx_pool[q], 862 rx_buff->page, 0, 863 true); 864 goto refill; 865 } 866 skb_mark_for_recycle(skb); 867 skb_put(skb, desc_len); 868 869 /* Save this skb if the packet spans multiple 870 * descriptors. 871 */ 872 if (die_dt == DT_FSTART) 873 priv->rx_1st_skb = skb; 874 break; 875 876 case DT_FMID: 877 case DT_FEND: 878 /* Continuing a packet: Add this buffer as an RX 879 * frag. 880 */ 881 882 /* rx_1st_skb will be NULL if napi_build_skb() 883 * failed for the first descriptor of a 884 * multi-descriptor packet. 885 */ 886 if (unlikely(!priv->rx_1st_skb)) { 887 stats->rx_errors++; 888 page_pool_put_page(priv->rx_pool[q], 889 rx_buff->page, 0, 890 true); 891 892 /* We may find a DT_FSINGLE or DT_FSTART 893 * descriptor in the queue which we can 894 * process, so don't give up yet. 895 */ 896 continue; 897 } 898 skb_add_rx_frag(priv->rx_1st_skb, 899 skb_shinfo(priv->rx_1st_skb)->nr_frags, 900 rx_buff->page, rx_buff->offset, 901 desc_len, info->rx_buffer_size); 902 903 /* Set skb to point at the whole packet so that 904 * we only need one code path for finishing a 905 * packet. 906 */ 907 skb = priv->rx_1st_skb; 908 } 909 910 switch (die_dt) { 911 case DT_FSINGLE: 912 case DT_FEND: 913 /* Finishing a packet: Determine protocol & 914 * checksum, hand off to NAPI and update our 915 * stats. 916 */ 917 skb->protocol = eth_type_trans(skb, ndev); 918 if (ndev->features & NETIF_F_RXCSUM) 919 ravb_rx_csum_gbeth(skb); 920 stats->rx_bytes += skb->len; 921 napi_gro_receive(&priv->napi[q], skb); 922 rx_packets++; 923 924 /* Clear rx_1st_skb so that it will only be 925 * non-NULL when valid. 926 */ 927 priv->rx_1st_skb = NULL; 928 } 929 930 /* Mark this RX buffer as consumed. */ 931 rx_buff->page = NULL; 932 } 933 } 934 935 refill: 936 /* Refill the RX ring buffers. */ 937 priv->dirty_rx[q] += ravb_rx_ring_refill(ndev, q, 938 priv->cur_rx[q] - priv->dirty_rx[q], 939 GFP_ATOMIC); 940 941 stats->rx_packets += rx_packets; 942 return rx_packets; 943 } 944 945 /* Packet receive function for Ethernet AVB */ 946 static int ravb_rx_rcar(struct net_device *ndev, int budget, int q) 947 { 948 struct ravb_private *priv = netdev_priv(ndev); 949 const struct ravb_hw_info *info = priv->info; 950 struct net_device_stats *stats = &priv->stats[q]; 951 struct ravb_ex_rx_desc *desc; 952 unsigned int limit, i; 953 struct sk_buff *skb; 954 struct timespec64 ts; 955 int rx_packets = 0; 956 u8 desc_status; 957 u16 pkt_len; 958 int entry; 959 960 limit = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q]; 961 for (i = 0; i < limit; i++, priv->cur_rx[q]++) { 962 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 963 desc = &priv->rx_ring[q].ex_desc[entry]; 964 if (rx_packets == budget || desc->die_dt == DT_FEMPTY) 965 break; 966 967 /* Descriptor type must be checked before all other reads */ 968 dma_rmb(); 969 desc_status = desc->msc; 970 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 971 972 /* We use 0-byte descriptors to mark the DMA mapping errors */ 973 if (!pkt_len) 974 continue; 975 976 if (desc_status & MSC_MC) 977 stats->multicast++; 978 979 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 980 MSC_CEEF)) { 981 stats->rx_errors++; 982 if (desc_status & MSC_CRC) 983 stats->rx_crc_errors++; 984 if (desc_status & MSC_RFE) 985 stats->rx_frame_errors++; 986 if (desc_status & (MSC_RTLF | MSC_RTSF)) 987 stats->rx_length_errors++; 988 if (desc_status & MSC_CEEF) 989 stats->rx_missed_errors++; 990 } else { 991 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 992 struct ravb_rx_buffer *rx_buff; 993 void *rx_addr; 994 995 rx_buff = &priv->rx_buffers[q][entry]; 996 rx_addr = page_address(rx_buff->page) + rx_buff->offset; 997 dma_sync_single_for_cpu(ndev->dev.parent, 998 le32_to_cpu(desc->dptr), 999 pkt_len, DMA_FROM_DEVICE); 1000 1001 skb = napi_build_skb(rx_addr, info->rx_buffer_size); 1002 if (unlikely(!skb)) { 1003 stats->rx_errors++; 1004 page_pool_put_page(priv->rx_pool[q], 1005 rx_buff->page, 0, true); 1006 break; 1007 } 1008 skb_mark_for_recycle(skb); 1009 get_ts &= (q == RAVB_NC) ? 1010 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 1011 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 1012 if (get_ts) { 1013 struct skb_shared_hwtstamps *shhwtstamps; 1014 1015 shhwtstamps = skb_hwtstamps(skb); 1016 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 1017 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 1018 32) | le32_to_cpu(desc->ts_sl); 1019 ts.tv_nsec = le32_to_cpu(desc->ts_n); 1020 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 1021 } 1022 1023 skb_put(skb, pkt_len); 1024 skb->protocol = eth_type_trans(skb, ndev); 1025 if (ndev->features & NETIF_F_RXCSUM) 1026 ravb_rx_csum(skb); 1027 napi_gro_receive(&priv->napi[q], skb); 1028 rx_packets++; 1029 stats->rx_bytes += pkt_len; 1030 1031 /* Mark this RX buffer as consumed. */ 1032 rx_buff->page = NULL; 1033 } 1034 } 1035 1036 /* Refill the RX ring buffers. */ 1037 priv->dirty_rx[q] += ravb_rx_ring_refill(ndev, q, 1038 priv->cur_rx[q] - priv->dirty_rx[q], 1039 GFP_ATOMIC); 1040 1041 stats->rx_packets += rx_packets; 1042 return rx_packets; 1043 } 1044 1045 /* Packet receive function for Ethernet AVB */ 1046 static int ravb_rx(struct net_device *ndev, int budget, int q) 1047 { 1048 struct ravb_private *priv = netdev_priv(ndev); 1049 const struct ravb_hw_info *info = priv->info; 1050 1051 return info->receive(ndev, budget, q); 1052 } 1053 1054 static void ravb_rcv_snd_disable(struct net_device *ndev) 1055 { 1056 /* Disable TX and RX */ 1057 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 1058 } 1059 1060 static void ravb_rcv_snd_enable(struct net_device *ndev) 1061 { 1062 /* Enable TX and RX */ 1063 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 1064 } 1065 1066 /* function for waiting dma process finished */ 1067 static int ravb_stop_dma(struct net_device *ndev) 1068 { 1069 struct ravb_private *priv = netdev_priv(ndev); 1070 const struct ravb_hw_info *info = priv->info; 1071 int error; 1072 1073 /* Wait for stopping the hardware TX process */ 1074 error = ravb_wait(ndev, TCCR, info->tccr_mask, 0); 1075 1076 if (error) 1077 return error; 1078 1079 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 1080 0); 1081 if (error) 1082 return error; 1083 1084 /* Stop the E-MAC's RX/TX processes. */ 1085 ravb_rcv_snd_disable(ndev); 1086 1087 /* Wait for stopping the RX DMA process */ 1088 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 1089 if (error) 1090 return error; 1091 1092 /* Stop AVB-DMAC process */ 1093 return ravb_set_opmode(ndev, CCC_OPC_CONFIG); 1094 } 1095 1096 /* E-MAC interrupt handler */ 1097 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 1098 { 1099 struct ravb_private *priv = netdev_priv(ndev); 1100 u32 ecsr, psr; 1101 1102 ecsr = ravb_read(ndev, ECSR); 1103 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 1104 1105 if (ecsr & ECSR_MPD) 1106 pm_wakeup_event(&priv->pdev->dev, 0); 1107 if (ecsr & ECSR_ICD) 1108 ndev->stats.tx_carrier_errors++; 1109 if (ecsr & ECSR_LCHNG) { 1110 /* Link changed */ 1111 if (priv->no_avb_link) 1112 return; 1113 psr = ravb_read(ndev, PSR); 1114 if (priv->avb_link_active_low) 1115 psr ^= PSR_LMON; 1116 if (!(psr & PSR_LMON)) { 1117 /* DIsable RX and TX */ 1118 ravb_rcv_snd_disable(ndev); 1119 } else { 1120 /* Enable RX and TX */ 1121 ravb_rcv_snd_enable(ndev); 1122 } 1123 } 1124 } 1125 1126 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 1127 { 1128 struct net_device *ndev = dev_id; 1129 struct ravb_private *priv = netdev_priv(ndev); 1130 struct device *dev = &priv->pdev->dev; 1131 irqreturn_t result = IRQ_HANDLED; 1132 1133 pm_runtime_get_noresume(dev); 1134 1135 if (unlikely(!pm_runtime_active(dev))) { 1136 result = IRQ_NONE; 1137 goto out_rpm_put; 1138 } 1139 1140 spin_lock(&priv->lock); 1141 ravb_emac_interrupt_unlocked(ndev); 1142 spin_unlock(&priv->lock); 1143 1144 out_rpm_put: 1145 pm_runtime_put_noidle(dev); 1146 return result; 1147 } 1148 1149 /* Error interrupt handler */ 1150 static void ravb_error_interrupt(struct net_device *ndev) 1151 { 1152 struct ravb_private *priv = netdev_priv(ndev); 1153 u32 eis, ris2; 1154 1155 eis = ravb_read(ndev, EIS); 1156 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS); 1157 if (eis & EIS_QFS) { 1158 ris2 = ravb_read(ndev, RIS2); 1159 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_QFF1 | RIS2_RFFF | RIS2_RESERVED), 1160 RIS2); 1161 1162 /* Receive Descriptor Empty int */ 1163 if (ris2 & RIS2_QFF0) 1164 priv->stats[RAVB_BE].rx_over_errors++; 1165 1166 /* Receive Descriptor Empty int */ 1167 if (ris2 & RIS2_QFF1) 1168 priv->stats[RAVB_NC].rx_over_errors++; 1169 1170 /* Receive FIFO Overflow int */ 1171 if (ris2 & RIS2_RFFF) 1172 priv->rx_fifo_errors++; 1173 } 1174 } 1175 1176 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 1177 { 1178 struct ravb_private *priv = netdev_priv(ndev); 1179 const struct ravb_hw_info *info = priv->info; 1180 u32 ris0 = ravb_read(ndev, RIS0); 1181 u32 ric0 = ravb_read(ndev, RIC0); 1182 u32 tis = ravb_read(ndev, TIS); 1183 u32 tic = ravb_read(ndev, TIC); 1184 1185 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 1186 if (napi_schedule_prep(&priv->napi[q])) { 1187 /* Mask RX and TX interrupts */ 1188 if (!info->irq_en_dis) { 1189 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 1190 ravb_write(ndev, tic & ~BIT(q), TIC); 1191 } else { 1192 ravb_write(ndev, BIT(q), RID0); 1193 ravb_write(ndev, BIT(q), TID); 1194 } 1195 __napi_schedule(&priv->napi[q]); 1196 } else { 1197 netdev_warn(ndev, 1198 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 1199 ris0, ric0); 1200 netdev_warn(ndev, 1201 " tx status 0x%08x, tx mask 0x%08x.\n", 1202 tis, tic); 1203 } 1204 return true; 1205 } 1206 return false; 1207 } 1208 1209 static bool ravb_timestamp_interrupt(struct net_device *ndev) 1210 { 1211 u32 tis = ravb_read(ndev, TIS); 1212 1213 if (tis & TIS_TFUF) { 1214 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS); 1215 ravb_get_tx_tstamp(ndev); 1216 return true; 1217 } 1218 return false; 1219 } 1220 1221 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 1222 { 1223 struct net_device *ndev = dev_id; 1224 struct ravb_private *priv = netdev_priv(ndev); 1225 const struct ravb_hw_info *info = priv->info; 1226 struct device *dev = &priv->pdev->dev; 1227 irqreturn_t result = IRQ_NONE; 1228 u32 iss; 1229 1230 pm_runtime_get_noresume(dev); 1231 1232 if (unlikely(!pm_runtime_active(dev))) 1233 goto out_rpm_put; 1234 1235 spin_lock(&priv->lock); 1236 /* Get interrupt status */ 1237 iss = ravb_read(ndev, ISS); 1238 1239 /* Received and transmitted interrupts */ 1240 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 1241 int q; 1242 1243 /* Timestamp updated */ 1244 if (ravb_timestamp_interrupt(ndev)) 1245 result = IRQ_HANDLED; 1246 1247 /* Network control and best effort queue RX/TX */ 1248 if (info->nc_queues) { 1249 for (q = RAVB_NC; q >= RAVB_BE; q--) { 1250 if (ravb_queue_interrupt(ndev, q)) 1251 result = IRQ_HANDLED; 1252 } 1253 } else { 1254 if (ravb_queue_interrupt(ndev, RAVB_BE)) 1255 result = IRQ_HANDLED; 1256 } 1257 } 1258 1259 /* E-MAC status summary */ 1260 if (iss & ISS_MS) { 1261 ravb_emac_interrupt_unlocked(ndev); 1262 result = IRQ_HANDLED; 1263 } 1264 1265 /* Error status summary */ 1266 if (iss & ISS_ES) { 1267 ravb_error_interrupt(ndev); 1268 result = IRQ_HANDLED; 1269 } 1270 1271 /* gPTP interrupt status summary */ 1272 if (iss & ISS_CGIS) { 1273 ravb_ptp_interrupt(ndev); 1274 result = IRQ_HANDLED; 1275 } 1276 1277 spin_unlock(&priv->lock); 1278 1279 out_rpm_put: 1280 pm_runtime_put_noidle(dev); 1281 return result; 1282 } 1283 1284 /* Timestamp/Error/gPTP interrupt handler */ 1285 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 1286 { 1287 struct net_device *ndev = dev_id; 1288 struct ravb_private *priv = netdev_priv(ndev); 1289 struct device *dev = &priv->pdev->dev; 1290 irqreturn_t result = IRQ_NONE; 1291 u32 iss; 1292 1293 pm_runtime_get_noresume(dev); 1294 1295 if (unlikely(!pm_runtime_active(dev))) 1296 goto out_rpm_put; 1297 1298 spin_lock(&priv->lock); 1299 /* Get interrupt status */ 1300 iss = ravb_read(ndev, ISS); 1301 1302 /* Timestamp updated */ 1303 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 1304 result = IRQ_HANDLED; 1305 1306 /* Error status summary */ 1307 if (iss & ISS_ES) { 1308 ravb_error_interrupt(ndev); 1309 result = IRQ_HANDLED; 1310 } 1311 1312 /* gPTP interrupt status summary */ 1313 if (iss & ISS_CGIS) { 1314 ravb_ptp_interrupt(ndev); 1315 result = IRQ_HANDLED; 1316 } 1317 1318 spin_unlock(&priv->lock); 1319 1320 out_rpm_put: 1321 pm_runtime_put_noidle(dev); 1322 return result; 1323 } 1324 1325 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 1326 { 1327 struct net_device *ndev = dev_id; 1328 struct ravb_private *priv = netdev_priv(ndev); 1329 struct device *dev = &priv->pdev->dev; 1330 irqreturn_t result = IRQ_NONE; 1331 1332 pm_runtime_get_noresume(dev); 1333 1334 if (unlikely(!pm_runtime_active(dev))) 1335 goto out_rpm_put; 1336 1337 spin_lock(&priv->lock); 1338 1339 /* Network control/Best effort queue RX/TX */ 1340 if (ravb_queue_interrupt(ndev, q)) 1341 result = IRQ_HANDLED; 1342 1343 spin_unlock(&priv->lock); 1344 1345 out_rpm_put: 1346 pm_runtime_put_noidle(dev); 1347 return result; 1348 } 1349 1350 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 1351 { 1352 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 1353 } 1354 1355 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 1356 { 1357 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 1358 } 1359 1360 static int ravb_poll(struct napi_struct *napi, int budget) 1361 { 1362 struct net_device *ndev = napi->dev; 1363 struct ravb_private *priv = netdev_priv(ndev); 1364 const struct ravb_hw_info *info = priv->info; 1365 unsigned long flags; 1366 int q = napi - priv->napi; 1367 int mask = BIT(q); 1368 int work_done; 1369 1370 /* Processing RX Descriptor Ring */ 1371 /* Clear RX interrupt */ 1372 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0); 1373 work_done = ravb_rx(ndev, budget, q); 1374 1375 /* Processing TX Descriptor Ring */ 1376 spin_lock_irqsave(&priv->lock, flags); 1377 /* Clear TX interrupt */ 1378 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS); 1379 ravb_tx_free(ndev, q, true); 1380 netif_wake_subqueue(ndev, q); 1381 spin_unlock_irqrestore(&priv->lock, flags); 1382 1383 /* Receive error message handling */ 1384 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 1385 if (info->nc_queues) 1386 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 1387 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 1388 ndev->stats.rx_over_errors = priv->rx_over_errors; 1389 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 1390 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 1391 1392 if (work_done < budget && napi_complete_done(napi, work_done)) { 1393 /* Re-enable RX/TX interrupts */ 1394 spin_lock_irqsave(&priv->lock, flags); 1395 if (!info->irq_en_dis) { 1396 ravb_modify(ndev, RIC0, mask, mask); 1397 ravb_modify(ndev, TIC, mask, mask); 1398 } else { 1399 ravb_write(ndev, mask, RIE0); 1400 ravb_write(ndev, mask, TIE); 1401 } 1402 spin_unlock_irqrestore(&priv->lock, flags); 1403 } 1404 1405 return work_done; 1406 } 1407 1408 static void ravb_set_duplex_gbeth(struct net_device *ndev) 1409 { 1410 struct ravb_private *priv = netdev_priv(ndev); 1411 1412 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex > 0 ? ECMR_DM : 0); 1413 } 1414 1415 /* PHY state control function */ 1416 static void ravb_adjust_link(struct net_device *ndev) 1417 { 1418 struct ravb_private *priv = netdev_priv(ndev); 1419 const struct ravb_hw_info *info = priv->info; 1420 struct phy_device *phydev = ndev->phydev; 1421 bool new_state = false; 1422 unsigned long flags; 1423 1424 spin_lock_irqsave(&priv->lock, flags); 1425 1426 /* Disable TX and RX right over here, if E-MAC change is ignored */ 1427 if (priv->no_avb_link) 1428 ravb_rcv_snd_disable(ndev); 1429 1430 if (phydev->link) { 1431 if (info->half_duplex && phydev->duplex != priv->duplex) { 1432 new_state = true; 1433 priv->duplex = phydev->duplex; 1434 ravb_set_duplex_gbeth(ndev); 1435 } 1436 1437 if (phydev->speed != priv->speed) { 1438 new_state = true; 1439 priv->speed = phydev->speed; 1440 info->set_rate(ndev); 1441 } 1442 if (!priv->link) { 1443 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 1444 new_state = true; 1445 priv->link = phydev->link; 1446 } 1447 } else if (priv->link) { 1448 new_state = true; 1449 priv->link = 0; 1450 priv->speed = 0; 1451 if (info->half_duplex) 1452 priv->duplex = -1; 1453 } 1454 1455 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1456 if (priv->no_avb_link && phydev->link) 1457 ravb_rcv_snd_enable(ndev); 1458 1459 spin_unlock_irqrestore(&priv->lock, flags); 1460 1461 if (new_state && netif_msg_link(priv)) 1462 phy_print_status(phydev); 1463 } 1464 1465 /* PHY init function */ 1466 static int ravb_phy_init(struct net_device *ndev) 1467 { 1468 struct device_node *np = ndev->dev.parent->of_node; 1469 struct ravb_private *priv = netdev_priv(ndev); 1470 const struct ravb_hw_info *info = priv->info; 1471 struct phy_device *phydev; 1472 struct device_node *pn; 1473 phy_interface_t iface; 1474 int err; 1475 1476 priv->link = 0; 1477 priv->speed = 0; 1478 priv->duplex = -1; 1479 1480 /* Try connecting to PHY */ 1481 pn = of_parse_phandle(np, "phy-handle", 0); 1482 if (!pn) { 1483 /* In the case of a fixed PHY, the DT node associated 1484 * to the PHY is the Ethernet MAC DT node. 1485 */ 1486 if (of_phy_is_fixed_link(np)) { 1487 err = of_phy_register_fixed_link(np); 1488 if (err) 1489 return err; 1490 } 1491 pn = of_node_get(np); 1492 } 1493 1494 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII 1495 : priv->phy_interface; 1496 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface); 1497 of_node_put(pn); 1498 if (!phydev) { 1499 netdev_err(ndev, "failed to connect PHY\n"); 1500 err = -ENOENT; 1501 goto err_deregister_fixed_link; 1502 } 1503 1504 if (!info->half_duplex) { 1505 /* 10BASE, Pause and Asym Pause is not supported */ 1506 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1507 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1508 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT); 1509 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 1510 1511 /* Half Duplex is not supported */ 1512 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1513 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1514 } 1515 1516 phy_attached_info(phydev); 1517 1518 return 0; 1519 1520 err_deregister_fixed_link: 1521 if (of_phy_is_fixed_link(np)) 1522 of_phy_deregister_fixed_link(np); 1523 1524 return err; 1525 } 1526 1527 /* PHY control start function */ 1528 static int ravb_phy_start(struct net_device *ndev) 1529 { 1530 int error; 1531 1532 error = ravb_phy_init(ndev); 1533 if (error) 1534 return error; 1535 1536 phy_start(ndev->phydev); 1537 1538 return 0; 1539 } 1540 1541 static u32 ravb_get_msglevel(struct net_device *ndev) 1542 { 1543 struct ravb_private *priv = netdev_priv(ndev); 1544 1545 return priv->msg_enable; 1546 } 1547 1548 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1549 { 1550 struct ravb_private *priv = netdev_priv(ndev); 1551 1552 priv->msg_enable = value; 1553 } 1554 1555 static const char ravb_gstrings_stats_gbeth[][ETH_GSTRING_LEN] = { 1556 "rx_queue_0_current", 1557 "tx_queue_0_current", 1558 "rx_queue_0_dirty", 1559 "tx_queue_0_dirty", 1560 "rx_queue_0_packets", 1561 "tx_queue_0_packets", 1562 "rx_queue_0_bytes", 1563 "tx_queue_0_bytes", 1564 "rx_queue_0_mcast_packets", 1565 "rx_queue_0_errors", 1566 "rx_queue_0_crc_errors", 1567 "rx_queue_0_frame_errors", 1568 "rx_queue_0_length_errors", 1569 "rx_queue_0_csum_offload_errors", 1570 "rx_queue_0_over_errors", 1571 }; 1572 1573 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1574 "rx_queue_0_current", 1575 "tx_queue_0_current", 1576 "rx_queue_0_dirty", 1577 "tx_queue_0_dirty", 1578 "rx_queue_0_packets", 1579 "tx_queue_0_packets", 1580 "rx_queue_0_bytes", 1581 "tx_queue_0_bytes", 1582 "rx_queue_0_mcast_packets", 1583 "rx_queue_0_errors", 1584 "rx_queue_0_crc_errors", 1585 "rx_queue_0_frame_errors", 1586 "rx_queue_0_length_errors", 1587 "rx_queue_0_missed_errors", 1588 "rx_queue_0_over_errors", 1589 1590 "rx_queue_1_current", 1591 "tx_queue_1_current", 1592 "rx_queue_1_dirty", 1593 "tx_queue_1_dirty", 1594 "rx_queue_1_packets", 1595 "tx_queue_1_packets", 1596 "rx_queue_1_bytes", 1597 "tx_queue_1_bytes", 1598 "rx_queue_1_mcast_packets", 1599 "rx_queue_1_errors", 1600 "rx_queue_1_crc_errors", 1601 "rx_queue_1_frame_errors", 1602 "rx_queue_1_length_errors", 1603 "rx_queue_1_missed_errors", 1604 "rx_queue_1_over_errors", 1605 }; 1606 1607 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1608 { 1609 struct ravb_private *priv = netdev_priv(netdev); 1610 const struct ravb_hw_info *info = priv->info; 1611 1612 switch (sset) { 1613 case ETH_SS_STATS: 1614 return info->stats_len; 1615 default: 1616 return -EOPNOTSUPP; 1617 } 1618 } 1619 1620 static void ravb_get_ethtool_stats(struct net_device *ndev, 1621 struct ethtool_stats *estats, u64 *data) 1622 { 1623 struct ravb_private *priv = netdev_priv(ndev); 1624 const struct ravb_hw_info *info = priv->info; 1625 int num_rx_q; 1626 int i = 0; 1627 int q; 1628 1629 num_rx_q = info->nc_queues ? NUM_RX_QUEUE : 1; 1630 /* Device-specific stats */ 1631 for (q = RAVB_BE; q < num_rx_q; q++) { 1632 struct net_device_stats *stats = &priv->stats[q]; 1633 1634 data[i++] = priv->cur_rx[q]; 1635 data[i++] = priv->cur_tx[q]; 1636 data[i++] = priv->dirty_rx[q]; 1637 data[i++] = priv->dirty_tx[q]; 1638 data[i++] = stats->rx_packets; 1639 data[i++] = stats->tx_packets; 1640 data[i++] = stats->rx_bytes; 1641 data[i++] = stats->tx_bytes; 1642 data[i++] = stats->multicast; 1643 data[i++] = stats->rx_errors; 1644 data[i++] = stats->rx_crc_errors; 1645 data[i++] = stats->rx_frame_errors; 1646 data[i++] = stats->rx_length_errors; 1647 data[i++] = stats->rx_missed_errors; 1648 data[i++] = stats->rx_over_errors; 1649 } 1650 } 1651 1652 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1653 { 1654 struct ravb_private *priv = netdev_priv(ndev); 1655 const struct ravb_hw_info *info = priv->info; 1656 1657 switch (stringset) { 1658 case ETH_SS_STATS: 1659 memcpy(data, info->gstrings_stats, info->gstrings_size); 1660 break; 1661 } 1662 } 1663 1664 static void ravb_get_ringparam(struct net_device *ndev, 1665 struct ethtool_ringparam *ring, 1666 struct kernel_ethtool_ringparam *kernel_ring, 1667 struct netlink_ext_ack *extack) 1668 { 1669 struct ravb_private *priv = netdev_priv(ndev); 1670 1671 ring->rx_max_pending = BE_RX_RING_MAX; 1672 ring->tx_max_pending = BE_TX_RING_MAX; 1673 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1674 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1675 } 1676 1677 static int ravb_set_ringparam(struct net_device *ndev, 1678 struct ethtool_ringparam *ring, 1679 struct kernel_ethtool_ringparam *kernel_ring, 1680 struct netlink_ext_ack *extack) 1681 { 1682 struct ravb_private *priv = netdev_priv(ndev); 1683 const struct ravb_hw_info *info = priv->info; 1684 int error; 1685 1686 if (ring->tx_pending > BE_TX_RING_MAX || 1687 ring->rx_pending > BE_RX_RING_MAX || 1688 ring->tx_pending < BE_TX_RING_MIN || 1689 ring->rx_pending < BE_RX_RING_MIN) 1690 return -EINVAL; 1691 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1692 return -EINVAL; 1693 1694 if (netif_running(ndev)) { 1695 netif_device_detach(ndev); 1696 /* Stop PTP Clock driver */ 1697 if (info->gptp) 1698 ravb_ptp_stop(ndev); 1699 /* Wait for DMA stopping */ 1700 error = ravb_stop_dma(ndev); 1701 if (error) { 1702 netdev_err(ndev, 1703 "cannot set ringparam! Any AVB processes are still running?\n"); 1704 return error; 1705 } 1706 synchronize_irq(ndev->irq); 1707 1708 /* Free all the skb's in the RX queue and the DMA buffers. */ 1709 ravb_ring_free(ndev, RAVB_BE); 1710 if (info->nc_queues) 1711 ravb_ring_free(ndev, RAVB_NC); 1712 } 1713 1714 /* Set new parameters */ 1715 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1716 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1717 1718 if (netif_running(ndev)) { 1719 error = ravb_dmac_init(ndev); 1720 if (error) { 1721 netdev_err(ndev, 1722 "%s: ravb_dmac_init() failed, error %d\n", 1723 __func__, error); 1724 return error; 1725 } 1726 1727 ravb_emac_init(ndev); 1728 1729 /* Initialise PTP Clock driver */ 1730 if (info->gptp) 1731 ravb_ptp_init(ndev, priv->pdev); 1732 1733 netif_device_attach(ndev); 1734 } 1735 1736 return 0; 1737 } 1738 1739 static int ravb_get_ts_info(struct net_device *ndev, 1740 struct kernel_ethtool_ts_info *info) 1741 { 1742 struct ravb_private *priv = netdev_priv(ndev); 1743 const struct ravb_hw_info *hw_info = priv->info; 1744 1745 info->so_timestamping = 1746 SOF_TIMESTAMPING_TX_SOFTWARE | 1747 SOF_TIMESTAMPING_RX_SOFTWARE | 1748 SOF_TIMESTAMPING_SOFTWARE | 1749 SOF_TIMESTAMPING_TX_HARDWARE | 1750 SOF_TIMESTAMPING_RX_HARDWARE | 1751 SOF_TIMESTAMPING_RAW_HARDWARE; 1752 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1753 info->rx_filters = 1754 (1 << HWTSTAMP_FILTER_NONE) | 1755 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1756 (1 << HWTSTAMP_FILTER_ALL); 1757 if (hw_info->gptp || hw_info->ccc_gac) 1758 info->phc_index = ptp_clock_index(priv->ptp.clock); 1759 1760 return 0; 1761 } 1762 1763 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1764 { 1765 struct ravb_private *priv = netdev_priv(ndev); 1766 1767 wol->supported = WAKE_MAGIC; 1768 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1769 } 1770 1771 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1772 { 1773 struct ravb_private *priv = netdev_priv(ndev); 1774 const struct ravb_hw_info *info = priv->info; 1775 1776 if (!info->magic_pkt || (wol->wolopts & ~WAKE_MAGIC)) 1777 return -EOPNOTSUPP; 1778 1779 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1780 1781 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1782 1783 return 0; 1784 } 1785 1786 static const struct ethtool_ops ravb_ethtool_ops = { 1787 .nway_reset = phy_ethtool_nway_reset, 1788 .get_msglevel = ravb_get_msglevel, 1789 .set_msglevel = ravb_set_msglevel, 1790 .get_link = ethtool_op_get_link, 1791 .get_strings = ravb_get_strings, 1792 .get_ethtool_stats = ravb_get_ethtool_stats, 1793 .get_sset_count = ravb_get_sset_count, 1794 .get_ringparam = ravb_get_ringparam, 1795 .set_ringparam = ravb_set_ringparam, 1796 .get_ts_info = ravb_get_ts_info, 1797 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1798 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1799 .get_wol = ravb_get_wol, 1800 .set_wol = ravb_set_wol, 1801 }; 1802 1803 static int ravb_set_config_mode(struct net_device *ndev) 1804 { 1805 struct ravb_private *priv = netdev_priv(ndev); 1806 const struct ravb_hw_info *info = priv->info; 1807 int error; 1808 1809 if (info->gptp) { 1810 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 1811 if (error) 1812 return error; 1813 /* Set CSEL value */ 1814 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 1815 } else if (info->ccc_gac) { 1816 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG | CCC_GAC | CCC_CSEL_HPB); 1817 } else { 1818 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 1819 } 1820 1821 return error; 1822 } 1823 1824 static void ravb_set_gti(struct net_device *ndev) 1825 { 1826 struct ravb_private *priv = netdev_priv(ndev); 1827 const struct ravb_hw_info *info = priv->info; 1828 1829 if (!(info->gptp || info->ccc_gac)) 1830 return; 1831 1832 ravb_write(ndev, priv->gti_tiv, GTI); 1833 1834 /* Request GTI loading */ 1835 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 1836 } 1837 1838 static int ravb_compute_gti(struct net_device *ndev) 1839 { 1840 struct ravb_private *priv = netdev_priv(ndev); 1841 const struct ravb_hw_info *info = priv->info; 1842 struct device *dev = ndev->dev.parent; 1843 unsigned long rate; 1844 u64 inc; 1845 1846 if (!(info->gptp || info->ccc_gac)) 1847 return 0; 1848 1849 if (info->gptp_ref_clk) 1850 rate = clk_get_rate(priv->gptp_clk); 1851 else 1852 rate = clk_get_rate(priv->clk); 1853 if (!rate) 1854 return -EINVAL; 1855 1856 inc = div64_ul(1000000000ULL << 20, rate); 1857 1858 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 1859 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 1860 inc, GTI_TIV_MIN, GTI_TIV_MAX); 1861 return -EINVAL; 1862 } 1863 priv->gti_tiv = inc; 1864 1865 return 0; 1866 } 1867 1868 /* Set tx and rx clock internal delay modes */ 1869 static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev) 1870 { 1871 struct ravb_private *priv = netdev_priv(ndev); 1872 bool explicit_delay = false; 1873 u32 delay; 1874 1875 if (!priv->info->internal_delay) 1876 return; 1877 1878 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) { 1879 /* Valid values are 0 and 1800, according to DT bindings */ 1880 priv->rxcidm = !!delay; 1881 explicit_delay = true; 1882 } 1883 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) { 1884 /* Valid values are 0 and 2000, according to DT bindings */ 1885 priv->txcidm = !!delay; 1886 explicit_delay = true; 1887 } 1888 1889 if (explicit_delay) 1890 return; 1891 1892 /* Fall back to legacy rgmii-*id behavior */ 1893 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1894 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) { 1895 priv->rxcidm = 1; 1896 priv->rgmii_override = 1; 1897 } 1898 1899 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1900 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) { 1901 priv->txcidm = 1; 1902 priv->rgmii_override = 1; 1903 } 1904 } 1905 1906 static void ravb_set_delay_mode(struct net_device *ndev) 1907 { 1908 struct ravb_private *priv = netdev_priv(ndev); 1909 u32 set = 0; 1910 1911 if (!priv->info->internal_delay) 1912 return; 1913 1914 if (priv->rxcidm) 1915 set |= APSR_RDM; 1916 if (priv->txcidm) 1917 set |= APSR_TDM; 1918 ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set); 1919 } 1920 1921 /* Network device open function for Ethernet AVB */ 1922 static int ravb_open(struct net_device *ndev) 1923 { 1924 struct ravb_private *priv = netdev_priv(ndev); 1925 const struct ravb_hw_info *info = priv->info; 1926 struct device *dev = &priv->pdev->dev; 1927 int error; 1928 1929 napi_enable(&priv->napi[RAVB_BE]); 1930 if (info->nc_queues) 1931 napi_enable(&priv->napi[RAVB_NC]); 1932 1933 error = pm_runtime_resume_and_get(dev); 1934 if (error < 0) 1935 goto out_napi_off; 1936 1937 /* Set AVB config mode */ 1938 error = ravb_set_config_mode(ndev); 1939 if (error) 1940 goto out_rpm_put; 1941 1942 ravb_set_delay_mode(ndev); 1943 ravb_write(ndev, priv->desc_bat_dma, DBAT); 1944 1945 /* Device init */ 1946 error = ravb_dmac_init(ndev); 1947 if (error) 1948 goto out_set_reset; 1949 1950 ravb_emac_init(ndev); 1951 1952 ravb_set_gti(ndev); 1953 1954 /* Initialise PTP Clock driver */ 1955 if (info->gptp || info->ccc_gac) 1956 ravb_ptp_init(ndev, priv->pdev); 1957 1958 /* PHY control start */ 1959 error = ravb_phy_start(ndev); 1960 if (error) 1961 goto out_ptp_stop; 1962 1963 netif_tx_start_all_queues(ndev); 1964 1965 return 0; 1966 1967 out_ptp_stop: 1968 /* Stop PTP Clock driver */ 1969 if (info->gptp || info->ccc_gac) 1970 ravb_ptp_stop(ndev); 1971 ravb_stop_dma(ndev); 1972 out_set_reset: 1973 ravb_set_opmode(ndev, CCC_OPC_RESET); 1974 out_rpm_put: 1975 pm_runtime_mark_last_busy(dev); 1976 pm_runtime_put_autosuspend(dev); 1977 out_napi_off: 1978 if (info->nc_queues) 1979 napi_disable(&priv->napi[RAVB_NC]); 1980 napi_disable(&priv->napi[RAVB_BE]); 1981 return error; 1982 } 1983 1984 /* Timeout function for Ethernet AVB */ 1985 static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1986 { 1987 struct ravb_private *priv = netdev_priv(ndev); 1988 1989 netif_err(priv, tx_err, ndev, 1990 "transmit timed out, status %08x, resetting...\n", 1991 ravb_read(ndev, ISS)); 1992 1993 /* tx_errors count up */ 1994 ndev->stats.tx_errors++; 1995 1996 schedule_work(&priv->work); 1997 } 1998 1999 static void ravb_tx_timeout_work(struct work_struct *work) 2000 { 2001 struct ravb_private *priv = container_of(work, struct ravb_private, 2002 work); 2003 const struct ravb_hw_info *info = priv->info; 2004 struct net_device *ndev = priv->ndev; 2005 int error; 2006 2007 if (!rtnl_trylock()) { 2008 usleep_range(1000, 2000); 2009 schedule_work(&priv->work); 2010 return; 2011 } 2012 2013 netif_tx_stop_all_queues(ndev); 2014 2015 /* Stop PTP Clock driver */ 2016 if (info->gptp) 2017 ravb_ptp_stop(ndev); 2018 2019 /* Wait for DMA stopping */ 2020 if (ravb_stop_dma(ndev)) { 2021 /* If ravb_stop_dma() fails, the hardware is still operating 2022 * for TX and/or RX. So, this should not call the following 2023 * functions because ravb_dmac_init() is possible to fail too. 2024 * Also, this should not retry ravb_stop_dma() again and again 2025 * here because it's possible to wait forever. So, this just 2026 * re-enables the TX and RX and skip the following 2027 * re-initialization procedure. 2028 */ 2029 ravb_rcv_snd_enable(ndev); 2030 goto out; 2031 } 2032 2033 ravb_ring_free(ndev, RAVB_BE); 2034 if (info->nc_queues) 2035 ravb_ring_free(ndev, RAVB_NC); 2036 2037 /* Device init */ 2038 error = ravb_dmac_init(ndev); 2039 if (error) { 2040 /* If ravb_dmac_init() fails, descriptors are freed. So, this 2041 * should return here to avoid re-enabling the TX and RX in 2042 * ravb_emac_init(). 2043 */ 2044 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n", 2045 __func__, error); 2046 goto out_unlock; 2047 } 2048 ravb_emac_init(ndev); 2049 2050 out: 2051 /* Initialise PTP Clock driver */ 2052 if (info->gptp) 2053 ravb_ptp_init(ndev, priv->pdev); 2054 2055 netif_tx_start_all_queues(ndev); 2056 2057 out_unlock: 2058 rtnl_unlock(); 2059 } 2060 2061 static bool ravb_can_tx_csum_gbeth(struct sk_buff *skb) 2062 { 2063 struct iphdr *ip = ip_hdr(skb); 2064 2065 /* TODO: Need to add support for VLAN tag 802.1Q */ 2066 if (skb_vlan_tag_present(skb)) 2067 return false; 2068 2069 /* TODO: Need to add hardware checksum for IPv6 */ 2070 if (skb->protocol != htons(ETH_P_IP)) 2071 return false; 2072 2073 switch (ip->protocol) { 2074 case IPPROTO_TCP: 2075 break; 2076 case IPPROTO_UDP: 2077 /* If the checksum value in the UDP header field is 0, TOE does 2078 * not calculate checksum for UDP part of this frame as it is 2079 * optional function as per standards. 2080 */ 2081 if (udp_hdr(skb)->check == 0) 2082 return false; 2083 break; 2084 default: 2085 return false; 2086 } 2087 2088 return true; 2089 } 2090 2091 /* Packet transmit function for Ethernet AVB */ 2092 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 2093 { 2094 struct ravb_private *priv = netdev_priv(ndev); 2095 const struct ravb_hw_info *info = priv->info; 2096 unsigned int num_tx_desc = priv->num_tx_desc; 2097 u16 q = skb_get_queue_mapping(skb); 2098 struct ravb_tstamp_skb *ts_skb; 2099 struct ravb_tx_desc *desc; 2100 unsigned long flags; 2101 dma_addr_t dma_addr; 2102 void *buffer; 2103 u32 entry; 2104 u32 len; 2105 2106 if (skb->ip_summed == CHECKSUM_PARTIAL && !ravb_can_tx_csum_gbeth(skb)) 2107 skb_checksum_help(skb); 2108 2109 spin_lock_irqsave(&priv->lock, flags); 2110 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 2111 num_tx_desc) { 2112 netif_err(priv, tx_queued, ndev, 2113 "still transmitting with the full ring!\n"); 2114 netif_stop_subqueue(ndev, q); 2115 spin_unlock_irqrestore(&priv->lock, flags); 2116 return NETDEV_TX_BUSY; 2117 } 2118 2119 if (skb_put_padto(skb, ETH_ZLEN)) 2120 goto exit; 2121 2122 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc); 2123 priv->tx_skb[q][entry / num_tx_desc] = skb; 2124 2125 if (num_tx_desc > 1) { 2126 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 2127 entry / num_tx_desc * DPTR_ALIGN; 2128 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 2129 2130 /* Zero length DMA descriptors are problematic as they seem 2131 * to terminate DMA transfers. Avoid them by simply using a 2132 * length of DPTR_ALIGN (4) when skb data is aligned to 2133 * DPTR_ALIGN. 2134 * 2135 * As skb is guaranteed to have at least ETH_ZLEN (60) 2136 * bytes of data by the call to skb_put_padto() above this 2137 * is safe with respect to both the length of the first DMA 2138 * descriptor (len) overflowing the available data and the 2139 * length of the second DMA descriptor (skb->len - len) 2140 * being negative. 2141 */ 2142 if (len == 0) 2143 len = DPTR_ALIGN; 2144 2145 memcpy(buffer, skb->data, len); 2146 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 2147 DMA_TO_DEVICE); 2148 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2149 goto drop; 2150 2151 desc = &priv->tx_ring[q][entry]; 2152 desc->ds_tagl = cpu_to_le16(len); 2153 desc->dptr = cpu_to_le32(dma_addr); 2154 2155 buffer = skb->data + len; 2156 len = skb->len - len; 2157 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 2158 DMA_TO_DEVICE); 2159 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2160 goto unmap; 2161 2162 desc++; 2163 } else { 2164 desc = &priv->tx_ring[q][entry]; 2165 len = skb->len; 2166 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, 2167 DMA_TO_DEVICE); 2168 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2169 goto drop; 2170 } 2171 desc->ds_tagl = cpu_to_le16(len); 2172 desc->dptr = cpu_to_le32(dma_addr); 2173 2174 /* TX timestamp required */ 2175 if (info->gptp || info->ccc_gac) { 2176 if (q == RAVB_NC) { 2177 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 2178 if (!ts_skb) { 2179 if (num_tx_desc > 1) { 2180 desc--; 2181 dma_unmap_single(ndev->dev.parent, dma_addr, 2182 len, DMA_TO_DEVICE); 2183 } 2184 goto unmap; 2185 } 2186 ts_skb->skb = skb_get(skb); 2187 ts_skb->tag = priv->ts_skb_tag++; 2188 priv->ts_skb_tag &= 0x3ff; 2189 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 2190 2191 /* TAG and timestamp required flag */ 2192 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2193 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 2194 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12); 2195 } 2196 2197 skb_tx_timestamp(skb); 2198 } 2199 /* Descriptor type must be set after all the above writes */ 2200 dma_wmb(); 2201 if (num_tx_desc > 1) { 2202 desc->die_dt = DT_FEND; 2203 desc--; 2204 desc->die_dt = DT_FSTART; 2205 } else { 2206 desc->die_dt = DT_FSINGLE; 2207 } 2208 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 2209 2210 priv->cur_tx[q] += num_tx_desc; 2211 if (priv->cur_tx[q] - priv->dirty_tx[q] > 2212 (priv->num_tx_ring[q] - 1) * num_tx_desc && 2213 !ravb_tx_free(ndev, q, true)) 2214 netif_stop_subqueue(ndev, q); 2215 2216 exit: 2217 spin_unlock_irqrestore(&priv->lock, flags); 2218 return NETDEV_TX_OK; 2219 2220 unmap: 2221 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 2222 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 2223 drop: 2224 dev_kfree_skb_any(skb); 2225 priv->tx_skb[q][entry / num_tx_desc] = NULL; 2226 goto exit; 2227 } 2228 2229 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 2230 struct net_device *sb_dev) 2231 { 2232 /* If skb needs TX timestamp, it is handled in network control queue */ 2233 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 2234 RAVB_BE; 2235 2236 } 2237 2238 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 2239 { 2240 struct ravb_private *priv = netdev_priv(ndev); 2241 const struct ravb_hw_info *info = priv->info; 2242 struct net_device_stats *nstats, *stats0, *stats1; 2243 struct device *dev = &priv->pdev->dev; 2244 2245 nstats = &ndev->stats; 2246 2247 pm_runtime_get_noresume(dev); 2248 2249 if (!pm_runtime_active(dev)) 2250 goto out_rpm_put; 2251 2252 stats0 = &priv->stats[RAVB_BE]; 2253 2254 if (info->tx_counters) { 2255 nstats->tx_dropped += ravb_read(ndev, TROCR); 2256 ravb_write(ndev, 0, TROCR); /* (write clear) */ 2257 } 2258 2259 if (info->carrier_counters) { 2260 nstats->collisions += ravb_read(ndev, CXR41); 2261 ravb_write(ndev, 0, CXR41); /* (write clear) */ 2262 nstats->tx_carrier_errors += ravb_read(ndev, CXR42); 2263 ravb_write(ndev, 0, CXR42); /* (write clear) */ 2264 } 2265 2266 nstats->rx_packets = stats0->rx_packets; 2267 nstats->tx_packets = stats0->tx_packets; 2268 nstats->rx_bytes = stats0->rx_bytes; 2269 nstats->tx_bytes = stats0->tx_bytes; 2270 nstats->multicast = stats0->multicast; 2271 nstats->rx_errors = stats0->rx_errors; 2272 nstats->rx_crc_errors = stats0->rx_crc_errors; 2273 nstats->rx_frame_errors = stats0->rx_frame_errors; 2274 nstats->rx_length_errors = stats0->rx_length_errors; 2275 nstats->rx_missed_errors = stats0->rx_missed_errors; 2276 nstats->rx_over_errors = stats0->rx_over_errors; 2277 if (info->nc_queues) { 2278 stats1 = &priv->stats[RAVB_NC]; 2279 2280 nstats->rx_packets += stats1->rx_packets; 2281 nstats->tx_packets += stats1->tx_packets; 2282 nstats->rx_bytes += stats1->rx_bytes; 2283 nstats->tx_bytes += stats1->tx_bytes; 2284 nstats->multicast += stats1->multicast; 2285 nstats->rx_errors += stats1->rx_errors; 2286 nstats->rx_crc_errors += stats1->rx_crc_errors; 2287 nstats->rx_frame_errors += stats1->rx_frame_errors; 2288 nstats->rx_length_errors += stats1->rx_length_errors; 2289 nstats->rx_missed_errors += stats1->rx_missed_errors; 2290 nstats->rx_over_errors += stats1->rx_over_errors; 2291 } 2292 2293 out_rpm_put: 2294 pm_runtime_put_noidle(dev); 2295 return nstats; 2296 } 2297 2298 /* Update promiscuous bit */ 2299 static void ravb_set_rx_mode(struct net_device *ndev) 2300 { 2301 struct ravb_private *priv = netdev_priv(ndev); 2302 unsigned long flags; 2303 2304 spin_lock_irqsave(&priv->lock, flags); 2305 ravb_modify(ndev, ECMR, ECMR_PRM, 2306 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 2307 spin_unlock_irqrestore(&priv->lock, flags); 2308 } 2309 2310 /* Device close function for Ethernet AVB */ 2311 static int ravb_close(struct net_device *ndev) 2312 { 2313 struct device_node *np = ndev->dev.parent->of_node; 2314 struct ravb_private *priv = netdev_priv(ndev); 2315 const struct ravb_hw_info *info = priv->info; 2316 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 2317 struct device *dev = &priv->pdev->dev; 2318 int error; 2319 2320 netif_tx_stop_all_queues(ndev); 2321 2322 /* Disable interrupts by clearing the interrupt masks. */ 2323 ravb_write(ndev, 0, RIC0); 2324 ravb_write(ndev, 0, RIC2); 2325 ravb_write(ndev, 0, TIC); 2326 2327 /* PHY disconnect */ 2328 if (ndev->phydev) { 2329 phy_stop(ndev->phydev); 2330 phy_disconnect(ndev->phydev); 2331 if (of_phy_is_fixed_link(np)) 2332 of_phy_deregister_fixed_link(np); 2333 } 2334 2335 /* Stop PTP Clock driver */ 2336 if (info->gptp || info->ccc_gac) 2337 ravb_ptp_stop(ndev); 2338 2339 /* Set the config mode to stop the AVB-DMAC's processes */ 2340 if (ravb_stop_dma(ndev) < 0) 2341 netdev_err(ndev, 2342 "device will be stopped after h/w processes are done.\n"); 2343 2344 /* Clear the timestamp list */ 2345 if (info->gptp || info->ccc_gac) { 2346 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 2347 list_del(&ts_skb->list); 2348 kfree_skb(ts_skb->skb); 2349 kfree(ts_skb); 2350 } 2351 } 2352 2353 cancel_work_sync(&priv->work); 2354 2355 if (info->nc_queues) 2356 napi_disable(&priv->napi[RAVB_NC]); 2357 napi_disable(&priv->napi[RAVB_BE]); 2358 2359 /* Free all the skb's in the RX queue and the DMA buffers. */ 2360 ravb_ring_free(ndev, RAVB_BE); 2361 if (info->nc_queues) 2362 ravb_ring_free(ndev, RAVB_NC); 2363 2364 /* Update statistics. */ 2365 ravb_get_stats(ndev); 2366 2367 /* Set reset mode. */ 2368 error = ravb_set_opmode(ndev, CCC_OPC_RESET); 2369 if (error) 2370 return error; 2371 2372 pm_runtime_mark_last_busy(dev); 2373 pm_runtime_put_autosuspend(dev); 2374 2375 return 0; 2376 } 2377 2378 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 2379 { 2380 struct ravb_private *priv = netdev_priv(ndev); 2381 struct hwtstamp_config config; 2382 2383 config.flags = 0; 2384 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 2385 HWTSTAMP_TX_OFF; 2386 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) { 2387 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT: 2388 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 2389 break; 2390 case RAVB_RXTSTAMP_TYPE_ALL: 2391 config.rx_filter = HWTSTAMP_FILTER_ALL; 2392 break; 2393 default: 2394 config.rx_filter = HWTSTAMP_FILTER_NONE; 2395 } 2396 2397 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2398 -EFAULT : 0; 2399 } 2400 2401 /* Control hardware time stamping */ 2402 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 2403 { 2404 struct ravb_private *priv = netdev_priv(ndev); 2405 struct hwtstamp_config config; 2406 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 2407 u32 tstamp_tx_ctrl; 2408 2409 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 2410 return -EFAULT; 2411 2412 switch (config.tx_type) { 2413 case HWTSTAMP_TX_OFF: 2414 tstamp_tx_ctrl = 0; 2415 break; 2416 case HWTSTAMP_TX_ON: 2417 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 2418 break; 2419 default: 2420 return -ERANGE; 2421 } 2422 2423 switch (config.rx_filter) { 2424 case HWTSTAMP_FILTER_NONE: 2425 tstamp_rx_ctrl = 0; 2426 break; 2427 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2428 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 2429 break; 2430 default: 2431 config.rx_filter = HWTSTAMP_FILTER_ALL; 2432 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 2433 } 2434 2435 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 2436 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 2437 2438 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2439 -EFAULT : 0; 2440 } 2441 2442 /* ioctl to device function */ 2443 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 2444 { 2445 struct phy_device *phydev = ndev->phydev; 2446 2447 if (!netif_running(ndev)) 2448 return -EINVAL; 2449 2450 if (!phydev) 2451 return -ENODEV; 2452 2453 switch (cmd) { 2454 case SIOCGHWTSTAMP: 2455 return ravb_hwtstamp_get(ndev, req); 2456 case SIOCSHWTSTAMP: 2457 return ravb_hwtstamp_set(ndev, req); 2458 } 2459 2460 return phy_mii_ioctl(phydev, req, cmd); 2461 } 2462 2463 static int ravb_change_mtu(struct net_device *ndev, int new_mtu) 2464 { 2465 struct ravb_private *priv = netdev_priv(ndev); 2466 2467 WRITE_ONCE(ndev->mtu, new_mtu); 2468 2469 if (netif_running(ndev)) { 2470 synchronize_irq(priv->emac_irq); 2471 ravb_emac_init(ndev); 2472 } 2473 2474 netdev_update_features(ndev); 2475 2476 return 0; 2477 } 2478 2479 static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 2480 { 2481 struct ravb_private *priv = netdev_priv(ndev); 2482 unsigned long flags; 2483 2484 spin_lock_irqsave(&priv->lock, flags); 2485 2486 /* Disable TX and RX */ 2487 ravb_rcv_snd_disable(ndev); 2488 2489 /* Modify RX Checksum setting */ 2490 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 2491 2492 /* Enable TX and RX */ 2493 ravb_rcv_snd_enable(ndev); 2494 2495 spin_unlock_irqrestore(&priv->lock, flags); 2496 } 2497 2498 static int ravb_endisable_csum_gbeth(struct net_device *ndev, enum ravb_reg reg, 2499 u32 val, u32 mask) 2500 { 2501 u32 csr0 = CSR0_TPE | CSR0_RPE; 2502 int ret; 2503 2504 ravb_write(ndev, csr0 & ~mask, CSR0); 2505 ret = ravb_wait(ndev, CSR0, mask, 0); 2506 if (!ret) 2507 ravb_write(ndev, val, reg); 2508 2509 ravb_write(ndev, csr0, CSR0); 2510 2511 return ret; 2512 } 2513 2514 static int ravb_set_features_gbeth(struct net_device *ndev, 2515 netdev_features_t features) 2516 { 2517 netdev_features_t changed = ndev->features ^ features; 2518 struct ravb_private *priv = netdev_priv(ndev); 2519 unsigned long flags; 2520 int ret = 0; 2521 u32 val; 2522 2523 spin_lock_irqsave(&priv->lock, flags); 2524 if (changed & NETIF_F_RXCSUM) { 2525 if (features & NETIF_F_RXCSUM) 2526 val = CSR2_RIP4 | CSR2_RTCP4 | CSR2_RUDP4 | CSR2_RICMP4; 2527 else 2528 val = 0; 2529 2530 ret = ravb_endisable_csum_gbeth(ndev, CSR2, val, CSR0_RPE); 2531 if (ret) 2532 goto done; 2533 } 2534 2535 if (changed & NETIF_F_HW_CSUM) { 2536 if (features & NETIF_F_HW_CSUM) 2537 val = CSR1_TIP4 | CSR1_TTCP4 | CSR1_TUDP4; 2538 else 2539 val = 0; 2540 2541 ret = ravb_endisable_csum_gbeth(ndev, CSR1, val, CSR0_TPE); 2542 if (ret) 2543 goto done; 2544 } 2545 2546 done: 2547 spin_unlock_irqrestore(&priv->lock, flags); 2548 2549 return ret; 2550 } 2551 2552 static int ravb_set_features_rcar(struct net_device *ndev, 2553 netdev_features_t features) 2554 { 2555 netdev_features_t changed = ndev->features ^ features; 2556 2557 if (changed & NETIF_F_RXCSUM) 2558 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 2559 2560 return 0; 2561 } 2562 2563 static int ravb_set_features(struct net_device *ndev, 2564 netdev_features_t features) 2565 { 2566 struct ravb_private *priv = netdev_priv(ndev); 2567 const struct ravb_hw_info *info = priv->info; 2568 struct device *dev = &priv->pdev->dev; 2569 int ret; 2570 2571 pm_runtime_get_noresume(dev); 2572 2573 if (pm_runtime_active(dev)) 2574 ret = info->set_feature(ndev, features); 2575 else 2576 ret = 0; 2577 2578 pm_runtime_put_noidle(dev); 2579 2580 if (ret) 2581 return ret; 2582 2583 ndev->features = features; 2584 2585 return 0; 2586 } 2587 2588 static const struct net_device_ops ravb_netdev_ops = { 2589 .ndo_open = ravb_open, 2590 .ndo_stop = ravb_close, 2591 .ndo_start_xmit = ravb_start_xmit, 2592 .ndo_select_queue = ravb_select_queue, 2593 .ndo_get_stats = ravb_get_stats, 2594 .ndo_set_rx_mode = ravb_set_rx_mode, 2595 .ndo_tx_timeout = ravb_tx_timeout, 2596 .ndo_eth_ioctl = ravb_do_ioctl, 2597 .ndo_change_mtu = ravb_change_mtu, 2598 .ndo_validate_addr = eth_validate_addr, 2599 .ndo_set_mac_address = eth_mac_addr, 2600 .ndo_set_features = ravb_set_features, 2601 }; 2602 2603 /* MDIO bus init function */ 2604 static int ravb_mdio_init(struct ravb_private *priv) 2605 { 2606 struct platform_device *pdev = priv->pdev; 2607 struct device *dev = &pdev->dev; 2608 struct device_node *mdio_node; 2609 struct phy_device *phydev; 2610 struct device_node *pn; 2611 int error; 2612 2613 /* Bitbang init */ 2614 priv->mdiobb.ops = &bb_ops; 2615 2616 /* MII controller setting */ 2617 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 2618 if (!priv->mii_bus) 2619 return -ENOMEM; 2620 2621 /* Hook up MII support for ethtool */ 2622 priv->mii_bus->name = "ravb_mii"; 2623 priv->mii_bus->parent = dev; 2624 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2625 pdev->name, pdev->id); 2626 2627 /* Register MDIO bus */ 2628 mdio_node = of_get_child_by_name(dev->of_node, "mdio"); 2629 if (!mdio_node) { 2630 /* backwards compatibility for DT lacking mdio subnode */ 2631 mdio_node = of_node_get(dev->of_node); 2632 } 2633 error = of_mdiobus_register(priv->mii_bus, mdio_node); 2634 of_node_put(mdio_node); 2635 if (error) 2636 goto out_free_bus; 2637 2638 pn = of_parse_phandle(dev->of_node, "phy-handle", 0); 2639 phydev = of_phy_find_device(pn); 2640 if (phydev) { 2641 phydev->mac_managed_pm = true; 2642 put_device(&phydev->mdio.dev); 2643 } 2644 of_node_put(pn); 2645 2646 return 0; 2647 2648 out_free_bus: 2649 free_mdio_bitbang(priv->mii_bus); 2650 return error; 2651 } 2652 2653 /* MDIO bus release function */ 2654 static int ravb_mdio_release(struct ravb_private *priv) 2655 { 2656 /* Unregister mdio bus */ 2657 mdiobus_unregister(priv->mii_bus); 2658 2659 /* Free bitbang info */ 2660 free_mdio_bitbang(priv->mii_bus); 2661 2662 return 0; 2663 } 2664 2665 static const struct ravb_hw_info ravb_gen2_hw_info = { 2666 .receive = ravb_rx_rcar, 2667 .set_rate = ravb_set_rate_rcar, 2668 .set_feature = ravb_set_features_rcar, 2669 .dmac_init = ravb_dmac_init_rcar, 2670 .emac_init = ravb_emac_init_rcar, 2671 .gstrings_stats = ravb_gstrings_stats, 2672 .gstrings_size = sizeof(ravb_gstrings_stats), 2673 .net_hw_features = NETIF_F_RXCSUM, 2674 .net_features = NETIF_F_RXCSUM, 2675 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2676 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2677 .rx_max_frame_size = SZ_2K, 2678 .rx_buffer_size = SZ_2K + 2679 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), 2680 .rx_desc_size = sizeof(struct ravb_ex_rx_desc), 2681 .aligned_tx = 1, 2682 .gptp = 1, 2683 .nc_queues = 1, 2684 .magic_pkt = 1, 2685 }; 2686 2687 static const struct ravb_hw_info ravb_gen3_hw_info = { 2688 .receive = ravb_rx_rcar, 2689 .set_rate = ravb_set_rate_rcar, 2690 .set_feature = ravb_set_features_rcar, 2691 .dmac_init = ravb_dmac_init_rcar, 2692 .emac_init = ravb_emac_init_rcar, 2693 .gstrings_stats = ravb_gstrings_stats, 2694 .gstrings_size = sizeof(ravb_gstrings_stats), 2695 .net_hw_features = NETIF_F_RXCSUM, 2696 .net_features = NETIF_F_RXCSUM, 2697 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2698 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2699 .rx_max_frame_size = SZ_2K, 2700 .rx_buffer_size = SZ_2K + 2701 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), 2702 .rx_desc_size = sizeof(struct ravb_ex_rx_desc), 2703 .internal_delay = 1, 2704 .tx_counters = 1, 2705 .multi_irqs = 1, 2706 .irq_en_dis = 1, 2707 .ccc_gac = 1, 2708 .nc_queues = 1, 2709 .magic_pkt = 1, 2710 }; 2711 2712 static const struct ravb_hw_info ravb_gen4_hw_info = { 2713 .receive = ravb_rx_rcar, 2714 .set_rate = ravb_set_rate_rcar, 2715 .set_feature = ravb_set_features_rcar, 2716 .dmac_init = ravb_dmac_init_rcar, 2717 .emac_init = ravb_emac_init_rcar_gen4, 2718 .gstrings_stats = ravb_gstrings_stats, 2719 .gstrings_size = sizeof(ravb_gstrings_stats), 2720 .net_hw_features = NETIF_F_RXCSUM, 2721 .net_features = NETIF_F_RXCSUM, 2722 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2723 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2724 .rx_max_frame_size = SZ_2K, 2725 .rx_buffer_size = SZ_2K + 2726 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), 2727 .rx_desc_size = sizeof(struct ravb_ex_rx_desc), 2728 .internal_delay = 1, 2729 .tx_counters = 1, 2730 .multi_irqs = 1, 2731 .irq_en_dis = 1, 2732 .ccc_gac = 1, 2733 .nc_queues = 1, 2734 .magic_pkt = 1, 2735 }; 2736 2737 static const struct ravb_hw_info ravb_rzv2m_hw_info = { 2738 .receive = ravb_rx_rcar, 2739 .set_rate = ravb_set_rate_rcar, 2740 .set_feature = ravb_set_features_rcar, 2741 .dmac_init = ravb_dmac_init_rcar, 2742 .emac_init = ravb_emac_init_rcar, 2743 .gstrings_stats = ravb_gstrings_stats, 2744 .gstrings_size = sizeof(ravb_gstrings_stats), 2745 .net_hw_features = NETIF_F_RXCSUM, 2746 .net_features = NETIF_F_RXCSUM, 2747 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2748 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2749 .rx_max_frame_size = SZ_2K, 2750 .rx_buffer_size = SZ_2K + 2751 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), 2752 .rx_desc_size = sizeof(struct ravb_ex_rx_desc), 2753 .multi_irqs = 1, 2754 .err_mgmt_irqs = 1, 2755 .gptp = 1, 2756 .gptp_ref_clk = 1, 2757 .nc_queues = 1, 2758 .magic_pkt = 1, 2759 }; 2760 2761 static const struct ravb_hw_info gbeth_hw_info = { 2762 .receive = ravb_rx_gbeth, 2763 .set_rate = ravb_set_rate_gbeth, 2764 .set_feature = ravb_set_features_gbeth, 2765 .dmac_init = ravb_dmac_init_gbeth, 2766 .emac_init = ravb_emac_init_gbeth, 2767 .gstrings_stats = ravb_gstrings_stats_gbeth, 2768 .gstrings_size = sizeof(ravb_gstrings_stats_gbeth), 2769 .net_hw_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM, 2770 .net_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM, 2771 .stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth), 2772 .tccr_mask = TCCR_TSRQ0, 2773 .rx_max_frame_size = SZ_8K, 2774 .rx_buffer_size = SZ_2K, 2775 .rx_desc_size = sizeof(struct ravb_rx_desc), 2776 .aligned_tx = 1, 2777 .coalesce_irqs = 1, 2778 .tx_counters = 1, 2779 .carrier_counters = 1, 2780 .half_duplex = 1, 2781 }; 2782 2783 static const struct of_device_id ravb_match_table[] = { 2784 { .compatible = "renesas,etheravb-r8a7790", .data = &ravb_gen2_hw_info }, 2785 { .compatible = "renesas,etheravb-r8a7794", .data = &ravb_gen2_hw_info }, 2786 { .compatible = "renesas,etheravb-rcar-gen2", .data = &ravb_gen2_hw_info }, 2787 { .compatible = "renesas,etheravb-r8a7795", .data = &ravb_gen3_hw_info }, 2788 { .compatible = "renesas,etheravb-rcar-gen3", .data = &ravb_gen3_hw_info }, 2789 { .compatible = "renesas,etheravb-rcar-gen4", .data = &ravb_gen4_hw_info }, 2790 { .compatible = "renesas,etheravb-rzv2m", .data = &ravb_rzv2m_hw_info }, 2791 { .compatible = "renesas,rzg2l-gbeth", .data = &gbeth_hw_info }, 2792 { } 2793 }; 2794 MODULE_DEVICE_TABLE(of, ravb_match_table); 2795 2796 static int ravb_setup_irq(struct ravb_private *priv, const char *irq_name, 2797 const char *ch, int *irq, irq_handler_t handler) 2798 { 2799 struct platform_device *pdev = priv->pdev; 2800 struct net_device *ndev = priv->ndev; 2801 struct device *dev = &pdev->dev; 2802 const char *devname = dev_name(dev); 2803 unsigned long flags; 2804 int error, irq_num; 2805 2806 if (irq_name) { 2807 devname = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", devname, ch); 2808 if (!devname) 2809 return -ENOMEM; 2810 2811 irq_num = platform_get_irq_byname(pdev, irq_name); 2812 flags = 0; 2813 } else { 2814 irq_num = platform_get_irq(pdev, 0); 2815 flags = IRQF_SHARED; 2816 } 2817 if (irq_num < 0) 2818 return irq_num; 2819 2820 if (irq) 2821 *irq = irq_num; 2822 2823 error = devm_request_irq(dev, irq_num, handler, flags, devname, ndev); 2824 if (error) 2825 netdev_err(ndev, "cannot request IRQ %s\n", devname); 2826 2827 return error; 2828 } 2829 2830 static int ravb_setup_irqs(struct ravb_private *priv) 2831 { 2832 const struct ravb_hw_info *info = priv->info; 2833 struct net_device *ndev = priv->ndev; 2834 const char *irq_name, *emac_irq_name; 2835 int error; 2836 2837 if (!info->multi_irqs) 2838 return ravb_setup_irq(priv, NULL, NULL, &ndev->irq, ravb_interrupt); 2839 2840 if (info->err_mgmt_irqs) { 2841 irq_name = "dia"; 2842 emac_irq_name = "line3"; 2843 } else { 2844 irq_name = "ch22"; 2845 emac_irq_name = "ch24"; 2846 } 2847 2848 error = ravb_setup_irq(priv, irq_name, "ch22:multi", &ndev->irq, ravb_multi_interrupt); 2849 if (error) 2850 return error; 2851 2852 error = ravb_setup_irq(priv, emac_irq_name, "ch24:emac", &priv->emac_irq, 2853 ravb_emac_interrupt); 2854 if (error) 2855 return error; 2856 2857 if (info->err_mgmt_irqs) { 2858 error = ravb_setup_irq(priv, "err_a", "err_a", NULL, ravb_multi_interrupt); 2859 if (error) 2860 return error; 2861 2862 error = ravb_setup_irq(priv, "mgmt_a", "mgmt_a", NULL, ravb_multi_interrupt); 2863 if (error) 2864 return error; 2865 } 2866 2867 error = ravb_setup_irq(priv, "ch0", "ch0:rx_be", NULL, ravb_be_interrupt); 2868 if (error) 2869 return error; 2870 2871 error = ravb_setup_irq(priv, "ch1", "ch1:rx_nc", NULL, ravb_nc_interrupt); 2872 if (error) 2873 return error; 2874 2875 error = ravb_setup_irq(priv, "ch18", "ch18:tx_be", NULL, ravb_be_interrupt); 2876 if (error) 2877 return error; 2878 2879 return ravb_setup_irq(priv, "ch19", "ch19:tx_nc", NULL, ravb_nc_interrupt); 2880 } 2881 2882 static int ravb_probe(struct platform_device *pdev) 2883 { 2884 struct device_node *np = pdev->dev.of_node; 2885 const struct ravb_hw_info *info; 2886 struct reset_control *rstc; 2887 struct ravb_private *priv; 2888 struct net_device *ndev; 2889 struct resource *res; 2890 int error, q; 2891 2892 if (!np) { 2893 dev_err(&pdev->dev, 2894 "this driver is required to be instantiated from device tree\n"); 2895 return -EINVAL; 2896 } 2897 2898 rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 2899 if (IS_ERR(rstc)) 2900 return dev_err_probe(&pdev->dev, PTR_ERR(rstc), 2901 "failed to get cpg reset\n"); 2902 2903 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 2904 NUM_TX_QUEUE, NUM_RX_QUEUE); 2905 if (!ndev) 2906 return -ENOMEM; 2907 2908 info = of_device_get_match_data(&pdev->dev); 2909 2910 ndev->features = info->net_features; 2911 ndev->hw_features = info->net_hw_features; 2912 2913 error = reset_control_deassert(rstc); 2914 if (error) 2915 goto out_free_netdev; 2916 2917 SET_NETDEV_DEV(ndev, &pdev->dev); 2918 2919 priv = netdev_priv(ndev); 2920 priv->info = info; 2921 priv->rstc = rstc; 2922 priv->ndev = ndev; 2923 priv->pdev = pdev; 2924 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2925 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2926 if (info->nc_queues) { 2927 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2928 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2929 } 2930 2931 error = ravb_setup_irqs(priv); 2932 if (error) 2933 goto out_reset_assert; 2934 2935 priv->clk = devm_clk_get(&pdev->dev, NULL); 2936 if (IS_ERR(priv->clk)) { 2937 error = PTR_ERR(priv->clk); 2938 goto out_reset_assert; 2939 } 2940 2941 if (info->gptp_ref_clk) { 2942 priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp"); 2943 if (IS_ERR(priv->gptp_clk)) { 2944 error = PTR_ERR(priv->gptp_clk); 2945 goto out_reset_assert; 2946 } 2947 } 2948 2949 priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk"); 2950 if (IS_ERR(priv->refclk)) { 2951 error = PTR_ERR(priv->refclk); 2952 goto out_reset_assert; 2953 } 2954 clk_prepare(priv->refclk); 2955 2956 platform_set_drvdata(pdev, ndev); 2957 pm_runtime_set_autosuspend_delay(&pdev->dev, 100); 2958 pm_runtime_use_autosuspend(&pdev->dev); 2959 pm_runtime_enable(&pdev->dev); 2960 error = pm_runtime_resume_and_get(&pdev->dev); 2961 if (error < 0) 2962 goto out_rpm_disable; 2963 2964 priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2965 if (IS_ERR(priv->addr)) { 2966 error = PTR_ERR(priv->addr); 2967 goto out_rpm_put; 2968 } 2969 2970 /* The Ether-specific entries in the device structure. */ 2971 ndev->base_addr = res->start; 2972 2973 spin_lock_init(&priv->lock); 2974 INIT_WORK(&priv->work, ravb_tx_timeout_work); 2975 2976 error = of_get_phy_mode(np, &priv->phy_interface); 2977 if (error && error != -ENODEV) 2978 goto out_rpm_put; 2979 2980 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 2981 priv->avb_link_active_low = 2982 of_property_read_bool(np, "renesas,ether-link-active-low"); 2983 2984 ndev->max_mtu = info->rx_max_frame_size - 2985 (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 2986 ndev->min_mtu = ETH_MIN_MTU; 2987 2988 /* FIXME: R-Car Gen2 has 4byte alignment restriction for tx buffer 2989 * Use two descriptor to handle such situation. First descriptor to 2990 * handle aligned data buffer and second descriptor to handle the 2991 * overflow data because of alignment. 2992 */ 2993 priv->num_tx_desc = info->aligned_tx ? 2 : 1; 2994 2995 /* Set function */ 2996 ndev->netdev_ops = &ravb_netdev_ops; 2997 ndev->ethtool_ops = &ravb_ethtool_ops; 2998 2999 error = ravb_compute_gti(ndev); 3000 if (error) 3001 goto out_rpm_put; 3002 3003 ravb_parse_delay_mode(np, ndev); 3004 3005 /* Allocate descriptor base address table */ 3006 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 3007 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 3008 &priv->desc_bat_dma, GFP_KERNEL); 3009 if (!priv->desc_bat) { 3010 dev_err(&pdev->dev, 3011 "Cannot allocate desc base address table (size %d bytes)\n", 3012 priv->desc_bat_size); 3013 error = -ENOMEM; 3014 goto out_rpm_put; 3015 } 3016 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 3017 priv->desc_bat[q].die_dt = DT_EOS; 3018 3019 /* Initialise HW timestamp list */ 3020 INIT_LIST_HEAD(&priv->ts_skb_list); 3021 3022 /* Debug message level */ 3023 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 3024 3025 /* Set config mode as this is needed for PHY initialization. */ 3026 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 3027 if (error) 3028 goto out_rpm_put; 3029 3030 /* Read and set MAC address */ 3031 ravb_read_mac_address(np, ndev); 3032 if (!is_valid_ether_addr(ndev->dev_addr)) { 3033 dev_warn(&pdev->dev, 3034 "no valid MAC address supplied, using a random one\n"); 3035 eth_hw_addr_random(ndev); 3036 } 3037 3038 /* MDIO bus init */ 3039 error = ravb_mdio_init(priv); 3040 if (error) { 3041 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 3042 goto out_reset_mode; 3043 } 3044 3045 /* Undo previous switch to config opmode. */ 3046 error = ravb_set_opmode(ndev, CCC_OPC_RESET); 3047 if (error) 3048 goto out_mdio_release; 3049 3050 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll); 3051 if (info->nc_queues) 3052 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll); 3053 3054 if (info->coalesce_irqs) { 3055 netdev_sw_irq_coalesce_default_on(ndev); 3056 if (num_present_cpus() == 1) 3057 dev_set_threaded(ndev, true); 3058 } 3059 3060 /* Network device register */ 3061 error = register_netdev(ndev); 3062 if (error) 3063 goto out_napi_del; 3064 3065 device_set_wakeup_capable(&pdev->dev, 1); 3066 3067 /* Print device information */ 3068 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 3069 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 3070 3071 pm_runtime_mark_last_busy(&pdev->dev); 3072 pm_runtime_put_autosuspend(&pdev->dev); 3073 3074 return 0; 3075 3076 out_napi_del: 3077 if (info->nc_queues) 3078 netif_napi_del(&priv->napi[RAVB_NC]); 3079 3080 netif_napi_del(&priv->napi[RAVB_BE]); 3081 out_mdio_release: 3082 ravb_mdio_release(priv); 3083 out_reset_mode: 3084 ravb_set_opmode(ndev, CCC_OPC_RESET); 3085 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 3086 priv->desc_bat_dma); 3087 out_rpm_put: 3088 pm_runtime_put(&pdev->dev); 3089 out_rpm_disable: 3090 pm_runtime_disable(&pdev->dev); 3091 pm_runtime_dont_use_autosuspend(&pdev->dev); 3092 clk_unprepare(priv->refclk); 3093 out_reset_assert: 3094 reset_control_assert(rstc); 3095 out_free_netdev: 3096 free_netdev(ndev); 3097 return error; 3098 } 3099 3100 static void ravb_remove(struct platform_device *pdev) 3101 { 3102 struct net_device *ndev = platform_get_drvdata(pdev); 3103 struct ravb_private *priv = netdev_priv(ndev); 3104 const struct ravb_hw_info *info = priv->info; 3105 struct device *dev = &priv->pdev->dev; 3106 int error; 3107 3108 error = pm_runtime_resume_and_get(dev); 3109 if (error < 0) 3110 return; 3111 3112 unregister_netdev(ndev); 3113 if (info->nc_queues) 3114 netif_napi_del(&priv->napi[RAVB_NC]); 3115 netif_napi_del(&priv->napi[RAVB_BE]); 3116 3117 ravb_mdio_release(priv); 3118 3119 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 3120 priv->desc_bat_dma); 3121 3122 pm_runtime_put_sync_suspend(&pdev->dev); 3123 pm_runtime_disable(&pdev->dev); 3124 pm_runtime_dont_use_autosuspend(dev); 3125 clk_unprepare(priv->refclk); 3126 reset_control_assert(priv->rstc); 3127 free_netdev(ndev); 3128 platform_set_drvdata(pdev, NULL); 3129 } 3130 3131 static int ravb_wol_setup(struct net_device *ndev) 3132 { 3133 struct ravb_private *priv = netdev_priv(ndev); 3134 const struct ravb_hw_info *info = priv->info; 3135 3136 /* Disable interrupts by clearing the interrupt masks. */ 3137 ravb_write(ndev, 0, RIC0); 3138 ravb_write(ndev, 0, RIC2); 3139 ravb_write(ndev, 0, TIC); 3140 3141 /* Only allow ECI interrupts */ 3142 synchronize_irq(priv->emac_irq); 3143 if (info->nc_queues) 3144 napi_disable(&priv->napi[RAVB_NC]); 3145 napi_disable(&priv->napi[RAVB_BE]); 3146 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 3147 3148 /* Enable MagicPacket */ 3149 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 3150 3151 if (priv->info->ccc_gac) 3152 ravb_ptp_stop(ndev); 3153 3154 return enable_irq_wake(priv->emac_irq); 3155 } 3156 3157 static int ravb_wol_restore(struct net_device *ndev) 3158 { 3159 struct ravb_private *priv = netdev_priv(ndev); 3160 const struct ravb_hw_info *info = priv->info; 3161 int error; 3162 3163 /* Set reset mode to rearm the WoL logic. */ 3164 error = ravb_set_opmode(ndev, CCC_OPC_RESET); 3165 if (error) 3166 return error; 3167 3168 /* Set AVB config mode. */ 3169 error = ravb_set_config_mode(ndev); 3170 if (error) 3171 return error; 3172 3173 if (priv->info->ccc_gac) 3174 ravb_ptp_init(ndev, priv->pdev); 3175 3176 if (info->nc_queues) 3177 napi_enable(&priv->napi[RAVB_NC]); 3178 napi_enable(&priv->napi[RAVB_BE]); 3179 3180 /* Disable MagicPacket */ 3181 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 3182 3183 ravb_close(ndev); 3184 3185 return disable_irq_wake(priv->emac_irq); 3186 } 3187 3188 static int ravb_suspend(struct device *dev) 3189 { 3190 struct net_device *ndev = dev_get_drvdata(dev); 3191 struct ravb_private *priv = netdev_priv(ndev); 3192 int ret; 3193 3194 if (!netif_running(ndev)) 3195 goto reset_assert; 3196 3197 netif_device_detach(ndev); 3198 3199 if (priv->wol_enabled) 3200 return ravb_wol_setup(ndev); 3201 3202 ret = ravb_close(ndev); 3203 if (ret) 3204 return ret; 3205 3206 ret = pm_runtime_force_suspend(&priv->pdev->dev); 3207 if (ret) 3208 return ret; 3209 3210 reset_assert: 3211 return reset_control_assert(priv->rstc); 3212 } 3213 3214 static int ravb_resume(struct device *dev) 3215 { 3216 struct net_device *ndev = dev_get_drvdata(dev); 3217 struct ravb_private *priv = netdev_priv(ndev); 3218 int ret; 3219 3220 ret = reset_control_deassert(priv->rstc); 3221 if (ret) 3222 return ret; 3223 3224 if (!netif_running(ndev)) 3225 return 0; 3226 3227 /* If WoL is enabled restore the interface. */ 3228 if (priv->wol_enabled) { 3229 ret = ravb_wol_restore(ndev); 3230 if (ret) 3231 return ret; 3232 } else { 3233 ret = pm_runtime_force_resume(dev); 3234 if (ret) 3235 return ret; 3236 } 3237 3238 /* Reopening the interface will restore the device to the working state. */ 3239 ret = ravb_open(ndev); 3240 if (ret < 0) 3241 goto out_rpm_put; 3242 3243 ravb_set_rx_mode(ndev); 3244 netif_device_attach(ndev); 3245 3246 return 0; 3247 3248 out_rpm_put: 3249 if (!priv->wol_enabled) { 3250 pm_runtime_mark_last_busy(dev); 3251 pm_runtime_put_autosuspend(dev); 3252 } 3253 3254 return ret; 3255 } 3256 3257 static int ravb_runtime_suspend(struct device *dev) 3258 { 3259 struct net_device *ndev = dev_get_drvdata(dev); 3260 struct ravb_private *priv = netdev_priv(ndev); 3261 3262 clk_disable(priv->refclk); 3263 3264 return 0; 3265 } 3266 3267 static int ravb_runtime_resume(struct device *dev) 3268 { 3269 struct net_device *ndev = dev_get_drvdata(dev); 3270 struct ravb_private *priv = netdev_priv(ndev); 3271 3272 return clk_enable(priv->refclk); 3273 } 3274 3275 static const struct dev_pm_ops ravb_dev_pm_ops = { 3276 SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 3277 RUNTIME_PM_OPS(ravb_runtime_suspend, ravb_runtime_resume, NULL) 3278 }; 3279 3280 static struct platform_driver ravb_driver = { 3281 .probe = ravb_probe, 3282 .remove_new = ravb_remove, 3283 .driver = { 3284 .name = "ravb", 3285 .pm = pm_ptr(&ravb_dev_pm_ops), 3286 .of_match_table = ravb_match_table, 3287 }, 3288 }; 3289 3290 module_platform_driver(ravb_driver); 3291 3292 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 3293 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 3294 MODULE_LICENSE("GPL v2"); 3295