1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet AVB device driver 3 * 4 * Copyright (C) 2014-2019 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * Based on the SuperH Ethernet driver 9 */ 10 11 #include <linux/cache.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_vlan.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/module.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/of_irq.h> 26 #include <linux/of_mdio.h> 27 #include <linux/of_net.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/slab.h> 30 #include <linux/spinlock.h> 31 #include <linux/sys_soc.h> 32 33 #include <asm/div64.h> 34 35 #include "ravb.h" 36 37 #define RAVB_DEF_MSG_ENABLE \ 38 (NETIF_MSG_LINK | \ 39 NETIF_MSG_TIMER | \ 40 NETIF_MSG_RX_ERR | \ 41 NETIF_MSG_TX_ERR) 42 43 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = { 44 "ch0", /* RAVB_BE */ 45 "ch1", /* RAVB_NC */ 46 }; 47 48 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = { 49 "ch18", /* RAVB_BE */ 50 "ch19", /* RAVB_NC */ 51 }; 52 53 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 54 u32 set) 55 { 56 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 57 } 58 59 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 60 { 61 int i; 62 63 for (i = 0; i < 10000; i++) { 64 if ((ravb_read(ndev, reg) & mask) == value) 65 return 0; 66 udelay(10); 67 } 68 return -ETIMEDOUT; 69 } 70 71 static int ravb_config(struct net_device *ndev) 72 { 73 int error; 74 75 /* Set config mode */ 76 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 77 /* Check if the operating mode is changed to the config mode */ 78 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); 79 if (error) 80 netdev_err(ndev, "failed to switch device to config mode\n"); 81 82 return error; 83 } 84 85 static void ravb_set_rate(struct net_device *ndev) 86 { 87 struct ravb_private *priv = netdev_priv(ndev); 88 89 switch (priv->speed) { 90 case 100: /* 100BASE */ 91 ravb_write(ndev, GECMR_SPEED_100, GECMR); 92 break; 93 case 1000: /* 1000BASE */ 94 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 95 break; 96 } 97 } 98 99 static void ravb_set_buffer_align(struct sk_buff *skb) 100 { 101 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 102 103 if (reserve) 104 skb_reserve(skb, RAVB_ALIGN - reserve); 105 } 106 107 /* Get MAC address from the MAC address registers 108 * 109 * Ethernet AVB device doesn't have ROM for MAC address. 110 * This function gets the MAC address that was used by a bootloader. 111 */ 112 static void ravb_read_mac_address(struct device_node *np, 113 struct net_device *ndev) 114 { 115 int ret; 116 117 ret = of_get_mac_address(np, ndev->dev_addr); 118 if (ret) { 119 u32 mahr = ravb_read(ndev, MAHR); 120 u32 malr = ravb_read(ndev, MALR); 121 122 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 123 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 124 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 125 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 126 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 127 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 128 } 129 } 130 131 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 132 { 133 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 134 mdiobb); 135 136 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 137 } 138 139 /* MDC pin control */ 140 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 141 { 142 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 143 } 144 145 /* Data I/O pin control */ 146 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 147 { 148 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 149 } 150 151 /* Set data bit */ 152 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 153 { 154 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 155 } 156 157 /* Get data bit */ 158 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 159 { 160 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 161 mdiobb); 162 163 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 164 } 165 166 /* MDIO bus control struct */ 167 static const struct mdiobb_ops bb_ops = { 168 .owner = THIS_MODULE, 169 .set_mdc = ravb_set_mdc, 170 .set_mdio_dir = ravb_set_mdio_dir, 171 .set_mdio_data = ravb_set_mdio_data, 172 .get_mdio_data = ravb_get_mdio_data, 173 }; 174 175 /* Free TX skb function for AVB-IP */ 176 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 177 { 178 struct ravb_private *priv = netdev_priv(ndev); 179 struct net_device_stats *stats = &priv->stats[q]; 180 unsigned int num_tx_desc = priv->num_tx_desc; 181 struct ravb_tx_desc *desc; 182 unsigned int entry; 183 int free_num = 0; 184 u32 size; 185 186 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 187 bool txed; 188 189 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 190 num_tx_desc); 191 desc = &priv->tx_ring[q][entry]; 192 txed = desc->die_dt == DT_FEMPTY; 193 if (free_txed_only && !txed) 194 break; 195 /* Descriptor type must be checked before all other reads */ 196 dma_rmb(); 197 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 198 /* Free the original skb. */ 199 if (priv->tx_skb[q][entry / num_tx_desc]) { 200 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 201 size, DMA_TO_DEVICE); 202 /* Last packet descriptor? */ 203 if (entry % num_tx_desc == num_tx_desc - 1) { 204 entry /= num_tx_desc; 205 dev_kfree_skb_any(priv->tx_skb[q][entry]); 206 priv->tx_skb[q][entry] = NULL; 207 if (txed) 208 stats->tx_packets++; 209 } 210 free_num++; 211 } 212 if (txed) 213 stats->tx_bytes += size; 214 desc->die_dt = DT_EEMPTY; 215 } 216 return free_num; 217 } 218 219 /* Free skb's and DMA buffers for Ethernet AVB */ 220 static void ravb_ring_free(struct net_device *ndev, int q) 221 { 222 struct ravb_private *priv = netdev_priv(ndev); 223 unsigned int num_tx_desc = priv->num_tx_desc; 224 unsigned int ring_size; 225 unsigned int i; 226 227 if (priv->rx_ring[q]) { 228 for (i = 0; i < priv->num_rx_ring[q]; i++) { 229 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i]; 230 231 if (!dma_mapping_error(ndev->dev.parent, 232 le32_to_cpu(desc->dptr))) 233 dma_unmap_single(ndev->dev.parent, 234 le32_to_cpu(desc->dptr), 235 RX_BUF_SZ, 236 DMA_FROM_DEVICE); 237 } 238 ring_size = sizeof(struct ravb_ex_rx_desc) * 239 (priv->num_rx_ring[q] + 1); 240 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], 241 priv->rx_desc_dma[q]); 242 priv->rx_ring[q] = NULL; 243 } 244 245 if (priv->tx_ring[q]) { 246 ravb_tx_free(ndev, q, false); 247 248 ring_size = sizeof(struct ravb_tx_desc) * 249 (priv->num_tx_ring[q] * num_tx_desc + 1); 250 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 251 priv->tx_desc_dma[q]); 252 priv->tx_ring[q] = NULL; 253 } 254 255 /* Free RX skb ringbuffer */ 256 if (priv->rx_skb[q]) { 257 for (i = 0; i < priv->num_rx_ring[q]; i++) 258 dev_kfree_skb(priv->rx_skb[q][i]); 259 } 260 kfree(priv->rx_skb[q]); 261 priv->rx_skb[q] = NULL; 262 263 /* Free aligned TX buffers */ 264 kfree(priv->tx_align[q]); 265 priv->tx_align[q] = NULL; 266 267 /* Free TX skb ringbuffer. 268 * SKBs are freed by ravb_tx_free() call above. 269 */ 270 kfree(priv->tx_skb[q]); 271 priv->tx_skb[q] = NULL; 272 } 273 274 /* Format skb and descriptor buffer for Ethernet AVB */ 275 static void ravb_ring_format(struct net_device *ndev, int q) 276 { 277 struct ravb_private *priv = netdev_priv(ndev); 278 unsigned int num_tx_desc = priv->num_tx_desc; 279 struct ravb_ex_rx_desc *rx_desc; 280 struct ravb_tx_desc *tx_desc; 281 struct ravb_desc *desc; 282 unsigned int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 283 unsigned int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 284 num_tx_desc; 285 dma_addr_t dma_addr; 286 unsigned int i; 287 288 priv->cur_rx[q] = 0; 289 priv->cur_tx[q] = 0; 290 priv->dirty_rx[q] = 0; 291 priv->dirty_tx[q] = 0; 292 293 memset(priv->rx_ring[q], 0, rx_ring_size); 294 /* Build RX ring buffer */ 295 for (i = 0; i < priv->num_rx_ring[q]; i++) { 296 /* RX descriptor */ 297 rx_desc = &priv->rx_ring[q][i]; 298 rx_desc->ds_cc = cpu_to_le16(RX_BUF_SZ); 299 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 300 RX_BUF_SZ, 301 DMA_FROM_DEVICE); 302 /* We just set the data size to 0 for a failed mapping which 303 * should prevent DMA from happening... 304 */ 305 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 306 rx_desc->ds_cc = cpu_to_le16(0); 307 rx_desc->dptr = cpu_to_le32(dma_addr); 308 rx_desc->die_dt = DT_FEMPTY; 309 } 310 rx_desc = &priv->rx_ring[q][i]; 311 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 312 rx_desc->die_dt = DT_LINKFIX; /* type */ 313 314 memset(priv->tx_ring[q], 0, tx_ring_size); 315 /* Build TX ring buffer */ 316 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 317 i++, tx_desc++) { 318 tx_desc->die_dt = DT_EEMPTY; 319 if (num_tx_desc > 1) { 320 tx_desc++; 321 tx_desc->die_dt = DT_EEMPTY; 322 } 323 } 324 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 325 tx_desc->die_dt = DT_LINKFIX; /* type */ 326 327 /* RX descriptor base address for best effort */ 328 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 329 desc->die_dt = DT_LINKFIX; /* type */ 330 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 331 332 /* TX descriptor base address for best effort */ 333 desc = &priv->desc_bat[q]; 334 desc->die_dt = DT_LINKFIX; /* type */ 335 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 336 } 337 338 /* Init skb and descriptor buffer for Ethernet AVB */ 339 static int ravb_ring_init(struct net_device *ndev, int q) 340 { 341 struct ravb_private *priv = netdev_priv(ndev); 342 const struct ravb_hw_info *info = priv->info; 343 unsigned int num_tx_desc = priv->num_tx_desc; 344 unsigned int ring_size; 345 struct sk_buff *skb; 346 unsigned int i; 347 348 /* Allocate RX and TX skb rings */ 349 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 350 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 351 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 352 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 353 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 354 goto error; 355 356 for (i = 0; i < priv->num_rx_ring[q]; i++) { 357 skb = netdev_alloc_skb(ndev, info->max_rx_len); 358 if (!skb) 359 goto error; 360 ravb_set_buffer_align(skb); 361 priv->rx_skb[q][i] = skb; 362 } 363 364 if (num_tx_desc > 1) { 365 /* Allocate rings for the aligned buffers */ 366 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 367 DPTR_ALIGN - 1, GFP_KERNEL); 368 if (!priv->tx_align[q]) 369 goto error; 370 } 371 372 /* Allocate all RX descriptors. */ 373 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); 374 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 375 &priv->rx_desc_dma[q], 376 GFP_KERNEL); 377 if (!priv->rx_ring[q]) 378 goto error; 379 380 priv->dirty_rx[q] = 0; 381 382 /* Allocate all TX descriptors. */ 383 ring_size = sizeof(struct ravb_tx_desc) * 384 (priv->num_tx_ring[q] * num_tx_desc + 1); 385 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 386 &priv->tx_desc_dma[q], 387 GFP_KERNEL); 388 if (!priv->tx_ring[q]) 389 goto error; 390 391 return 0; 392 393 error: 394 ravb_ring_free(ndev, q); 395 396 return -ENOMEM; 397 } 398 399 /* E-MAC init function */ 400 static void ravb_emac_init(struct net_device *ndev) 401 { 402 /* Receive frame limit set register */ 403 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 404 405 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 406 ravb_write(ndev, ECMR_ZPF | ECMR_DM | 407 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 408 ECMR_TE | ECMR_RE, ECMR); 409 410 ravb_set_rate(ndev); 411 412 /* Set MAC address */ 413 ravb_write(ndev, 414 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 415 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 416 ravb_write(ndev, 417 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 418 419 /* E-MAC status register clear */ 420 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 421 422 /* E-MAC interrupt enable register */ 423 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 424 } 425 426 /* Device init function for Ethernet AVB */ 427 static int ravb_dmac_init(struct net_device *ndev) 428 { 429 struct ravb_private *priv = netdev_priv(ndev); 430 int error; 431 432 /* Set CONFIG mode */ 433 error = ravb_config(ndev); 434 if (error) 435 return error; 436 437 error = ravb_ring_init(ndev, RAVB_BE); 438 if (error) 439 return error; 440 error = ravb_ring_init(ndev, RAVB_NC); 441 if (error) { 442 ravb_ring_free(ndev, RAVB_BE); 443 return error; 444 } 445 446 /* Descriptor format */ 447 ravb_ring_format(ndev, RAVB_BE); 448 ravb_ring_format(ndev, RAVB_NC); 449 450 /* Set AVB RX */ 451 ravb_write(ndev, 452 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 453 454 /* Set FIFO size */ 455 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC); 456 457 /* Timestamp enable */ 458 ravb_write(ndev, TCCR_TFEN, TCCR); 459 460 /* Interrupt init: */ 461 if (priv->chip_id == RCAR_GEN3) { 462 /* Clear DIL.DPLx */ 463 ravb_write(ndev, 0, DIL); 464 /* Set queue specific interrupt */ 465 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 466 } 467 /* Frame receive */ 468 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 469 /* Disable FIFO full warning */ 470 ravb_write(ndev, 0, RIC1); 471 /* Receive FIFO full error, descriptor empty */ 472 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 473 /* Frame transmitted, timestamp FIFO updated */ 474 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 475 476 /* Setting the control will start the AVB-DMAC process. */ 477 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION); 478 479 return 0; 480 } 481 482 static void ravb_get_tx_tstamp(struct net_device *ndev) 483 { 484 struct ravb_private *priv = netdev_priv(ndev); 485 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 486 struct skb_shared_hwtstamps shhwtstamps; 487 struct sk_buff *skb; 488 struct timespec64 ts; 489 u16 tag, tfa_tag; 490 int count; 491 u32 tfa2; 492 493 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 494 while (count--) { 495 tfa2 = ravb_read(ndev, TFA2); 496 tfa_tag = (tfa2 & TFA2_TST) >> 16; 497 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 498 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 499 ravb_read(ndev, TFA1); 500 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 501 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 502 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 503 list) { 504 skb = ts_skb->skb; 505 tag = ts_skb->tag; 506 list_del(&ts_skb->list); 507 kfree(ts_skb); 508 if (tag == tfa_tag) { 509 skb_tstamp_tx(skb, &shhwtstamps); 510 dev_consume_skb_any(skb); 511 break; 512 } else { 513 dev_kfree_skb_any(skb); 514 } 515 } 516 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 517 } 518 } 519 520 static void ravb_rx_csum(struct sk_buff *skb) 521 { 522 u8 *hw_csum; 523 524 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes 525 * appended to packet data 526 */ 527 if (unlikely(skb->len < sizeof(__sum16))) 528 return; 529 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); 530 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 531 skb->ip_summed = CHECKSUM_COMPLETE; 532 skb_trim(skb, skb->len - sizeof(__sum16)); 533 } 534 535 /* Packet receive function for Ethernet AVB */ 536 static bool ravb_rx(struct net_device *ndev, int *quota, int q) 537 { 538 struct ravb_private *priv = netdev_priv(ndev); 539 const struct ravb_hw_info *info = priv->info; 540 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 541 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 542 priv->cur_rx[q]; 543 struct net_device_stats *stats = &priv->stats[q]; 544 struct ravb_ex_rx_desc *desc; 545 struct sk_buff *skb; 546 dma_addr_t dma_addr; 547 struct timespec64 ts; 548 u8 desc_status; 549 u16 pkt_len; 550 int limit; 551 552 boguscnt = min(boguscnt, *quota); 553 limit = boguscnt; 554 desc = &priv->rx_ring[q][entry]; 555 while (desc->die_dt != DT_FEMPTY) { 556 /* Descriptor type must be checked before all other reads */ 557 dma_rmb(); 558 desc_status = desc->msc; 559 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 560 561 if (--boguscnt < 0) 562 break; 563 564 /* We use 0-byte descriptors to mark the DMA mapping errors */ 565 if (!pkt_len) 566 continue; 567 568 if (desc_status & MSC_MC) 569 stats->multicast++; 570 571 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 572 MSC_CEEF)) { 573 stats->rx_errors++; 574 if (desc_status & MSC_CRC) 575 stats->rx_crc_errors++; 576 if (desc_status & MSC_RFE) 577 stats->rx_frame_errors++; 578 if (desc_status & (MSC_RTLF | MSC_RTSF)) 579 stats->rx_length_errors++; 580 if (desc_status & MSC_CEEF) 581 stats->rx_missed_errors++; 582 } else { 583 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 584 585 skb = priv->rx_skb[q][entry]; 586 priv->rx_skb[q][entry] = NULL; 587 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 588 RX_BUF_SZ, 589 DMA_FROM_DEVICE); 590 get_ts &= (q == RAVB_NC) ? 591 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 592 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 593 if (get_ts) { 594 struct skb_shared_hwtstamps *shhwtstamps; 595 596 shhwtstamps = skb_hwtstamps(skb); 597 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 598 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 599 32) | le32_to_cpu(desc->ts_sl); 600 ts.tv_nsec = le32_to_cpu(desc->ts_n); 601 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 602 } 603 604 skb_put(skb, pkt_len); 605 skb->protocol = eth_type_trans(skb, ndev); 606 if (ndev->features & NETIF_F_RXCSUM) 607 ravb_rx_csum(skb); 608 napi_gro_receive(&priv->napi[q], skb); 609 stats->rx_packets++; 610 stats->rx_bytes += pkt_len; 611 } 612 613 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 614 desc = &priv->rx_ring[q][entry]; 615 } 616 617 /* Refill the RX ring buffers. */ 618 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 619 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 620 desc = &priv->rx_ring[q][entry]; 621 desc->ds_cc = cpu_to_le16(RX_BUF_SZ); 622 623 if (!priv->rx_skb[q][entry]) { 624 skb = netdev_alloc_skb(ndev, info->max_rx_len); 625 if (!skb) 626 break; /* Better luck next round. */ 627 ravb_set_buffer_align(skb); 628 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 629 le16_to_cpu(desc->ds_cc), 630 DMA_FROM_DEVICE); 631 skb_checksum_none_assert(skb); 632 /* We just set the data size to 0 for a failed mapping 633 * which should prevent DMA from happening... 634 */ 635 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 636 desc->ds_cc = cpu_to_le16(0); 637 desc->dptr = cpu_to_le32(dma_addr); 638 priv->rx_skb[q][entry] = skb; 639 } 640 /* Descriptor type must be set after all the above writes */ 641 dma_wmb(); 642 desc->die_dt = DT_FEMPTY; 643 } 644 645 *quota -= limit - (++boguscnt); 646 647 return boguscnt <= 0; 648 } 649 650 static void ravb_rcv_snd_disable(struct net_device *ndev) 651 { 652 /* Disable TX and RX */ 653 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 654 } 655 656 static void ravb_rcv_snd_enable(struct net_device *ndev) 657 { 658 /* Enable TX and RX */ 659 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 660 } 661 662 /* function for waiting dma process finished */ 663 static int ravb_stop_dma(struct net_device *ndev) 664 { 665 int error; 666 667 /* Wait for stopping the hardware TX process */ 668 error = ravb_wait(ndev, TCCR, 669 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0); 670 if (error) 671 return error; 672 673 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 674 0); 675 if (error) 676 return error; 677 678 /* Stop the E-MAC's RX/TX processes. */ 679 ravb_rcv_snd_disable(ndev); 680 681 /* Wait for stopping the RX DMA process */ 682 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 683 if (error) 684 return error; 685 686 /* Stop AVB-DMAC process */ 687 return ravb_config(ndev); 688 } 689 690 /* E-MAC interrupt handler */ 691 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 692 { 693 struct ravb_private *priv = netdev_priv(ndev); 694 u32 ecsr, psr; 695 696 ecsr = ravb_read(ndev, ECSR); 697 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 698 699 if (ecsr & ECSR_MPD) 700 pm_wakeup_event(&priv->pdev->dev, 0); 701 if (ecsr & ECSR_ICD) 702 ndev->stats.tx_carrier_errors++; 703 if (ecsr & ECSR_LCHNG) { 704 /* Link changed */ 705 if (priv->no_avb_link) 706 return; 707 psr = ravb_read(ndev, PSR); 708 if (priv->avb_link_active_low) 709 psr ^= PSR_LMON; 710 if (!(psr & PSR_LMON)) { 711 /* DIsable RX and TX */ 712 ravb_rcv_snd_disable(ndev); 713 } else { 714 /* Enable RX and TX */ 715 ravb_rcv_snd_enable(ndev); 716 } 717 } 718 } 719 720 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 721 { 722 struct net_device *ndev = dev_id; 723 struct ravb_private *priv = netdev_priv(ndev); 724 725 spin_lock(&priv->lock); 726 ravb_emac_interrupt_unlocked(ndev); 727 spin_unlock(&priv->lock); 728 return IRQ_HANDLED; 729 } 730 731 /* Error interrupt handler */ 732 static void ravb_error_interrupt(struct net_device *ndev) 733 { 734 struct ravb_private *priv = netdev_priv(ndev); 735 u32 eis, ris2; 736 737 eis = ravb_read(ndev, EIS); 738 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS); 739 if (eis & EIS_QFS) { 740 ris2 = ravb_read(ndev, RIS2); 741 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF | RIS2_RESERVED), 742 RIS2); 743 744 /* Receive Descriptor Empty int */ 745 if (ris2 & RIS2_QFF0) 746 priv->stats[RAVB_BE].rx_over_errors++; 747 748 /* Receive Descriptor Empty int */ 749 if (ris2 & RIS2_QFF1) 750 priv->stats[RAVB_NC].rx_over_errors++; 751 752 /* Receive FIFO Overflow int */ 753 if (ris2 & RIS2_RFFF) 754 priv->rx_fifo_errors++; 755 } 756 } 757 758 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 759 { 760 struct ravb_private *priv = netdev_priv(ndev); 761 u32 ris0 = ravb_read(ndev, RIS0); 762 u32 ric0 = ravb_read(ndev, RIC0); 763 u32 tis = ravb_read(ndev, TIS); 764 u32 tic = ravb_read(ndev, TIC); 765 766 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 767 if (napi_schedule_prep(&priv->napi[q])) { 768 /* Mask RX and TX interrupts */ 769 if (priv->chip_id == RCAR_GEN2) { 770 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 771 ravb_write(ndev, tic & ~BIT(q), TIC); 772 } else { 773 ravb_write(ndev, BIT(q), RID0); 774 ravb_write(ndev, BIT(q), TID); 775 } 776 __napi_schedule(&priv->napi[q]); 777 } else { 778 netdev_warn(ndev, 779 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 780 ris0, ric0); 781 netdev_warn(ndev, 782 " tx status 0x%08x, tx mask 0x%08x.\n", 783 tis, tic); 784 } 785 return true; 786 } 787 return false; 788 } 789 790 static bool ravb_timestamp_interrupt(struct net_device *ndev) 791 { 792 u32 tis = ravb_read(ndev, TIS); 793 794 if (tis & TIS_TFUF) { 795 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS); 796 ravb_get_tx_tstamp(ndev); 797 return true; 798 } 799 return false; 800 } 801 802 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 803 { 804 struct net_device *ndev = dev_id; 805 struct ravb_private *priv = netdev_priv(ndev); 806 irqreturn_t result = IRQ_NONE; 807 u32 iss; 808 809 spin_lock(&priv->lock); 810 /* Get interrupt status */ 811 iss = ravb_read(ndev, ISS); 812 813 /* Received and transmitted interrupts */ 814 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 815 int q; 816 817 /* Timestamp updated */ 818 if (ravb_timestamp_interrupt(ndev)) 819 result = IRQ_HANDLED; 820 821 /* Network control and best effort queue RX/TX */ 822 for (q = RAVB_NC; q >= RAVB_BE; q--) { 823 if (ravb_queue_interrupt(ndev, q)) 824 result = IRQ_HANDLED; 825 } 826 } 827 828 /* E-MAC status summary */ 829 if (iss & ISS_MS) { 830 ravb_emac_interrupt_unlocked(ndev); 831 result = IRQ_HANDLED; 832 } 833 834 /* Error status summary */ 835 if (iss & ISS_ES) { 836 ravb_error_interrupt(ndev); 837 result = IRQ_HANDLED; 838 } 839 840 /* gPTP interrupt status summary */ 841 if (iss & ISS_CGIS) { 842 ravb_ptp_interrupt(ndev); 843 result = IRQ_HANDLED; 844 } 845 846 spin_unlock(&priv->lock); 847 return result; 848 } 849 850 /* Timestamp/Error/gPTP interrupt handler */ 851 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 852 { 853 struct net_device *ndev = dev_id; 854 struct ravb_private *priv = netdev_priv(ndev); 855 irqreturn_t result = IRQ_NONE; 856 u32 iss; 857 858 spin_lock(&priv->lock); 859 /* Get interrupt status */ 860 iss = ravb_read(ndev, ISS); 861 862 /* Timestamp updated */ 863 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 864 result = IRQ_HANDLED; 865 866 /* Error status summary */ 867 if (iss & ISS_ES) { 868 ravb_error_interrupt(ndev); 869 result = IRQ_HANDLED; 870 } 871 872 /* gPTP interrupt status summary */ 873 if (iss & ISS_CGIS) { 874 ravb_ptp_interrupt(ndev); 875 result = IRQ_HANDLED; 876 } 877 878 spin_unlock(&priv->lock); 879 return result; 880 } 881 882 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 883 { 884 struct net_device *ndev = dev_id; 885 struct ravb_private *priv = netdev_priv(ndev); 886 irqreturn_t result = IRQ_NONE; 887 888 spin_lock(&priv->lock); 889 890 /* Network control/Best effort queue RX/TX */ 891 if (ravb_queue_interrupt(ndev, q)) 892 result = IRQ_HANDLED; 893 894 spin_unlock(&priv->lock); 895 return result; 896 } 897 898 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 899 { 900 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 901 } 902 903 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 904 { 905 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 906 } 907 908 static int ravb_poll(struct napi_struct *napi, int budget) 909 { 910 struct net_device *ndev = napi->dev; 911 struct ravb_private *priv = netdev_priv(ndev); 912 unsigned long flags; 913 int q = napi - priv->napi; 914 int mask = BIT(q); 915 int quota = budget; 916 917 /* Processing RX Descriptor Ring */ 918 /* Clear RX interrupt */ 919 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0); 920 if (ravb_rx(ndev, "a, q)) 921 goto out; 922 923 /* Processing TX Descriptor Ring */ 924 spin_lock_irqsave(&priv->lock, flags); 925 /* Clear TX interrupt */ 926 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS); 927 ravb_tx_free(ndev, q, true); 928 netif_wake_subqueue(ndev, q); 929 spin_unlock_irqrestore(&priv->lock, flags); 930 931 napi_complete(napi); 932 933 /* Re-enable RX/TX interrupts */ 934 spin_lock_irqsave(&priv->lock, flags); 935 if (priv->chip_id == RCAR_GEN2) { 936 ravb_modify(ndev, RIC0, mask, mask); 937 ravb_modify(ndev, TIC, mask, mask); 938 } else { 939 ravb_write(ndev, mask, RIE0); 940 ravb_write(ndev, mask, TIE); 941 } 942 spin_unlock_irqrestore(&priv->lock, flags); 943 944 /* Receive error message handling */ 945 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 946 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 947 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 948 ndev->stats.rx_over_errors = priv->rx_over_errors; 949 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 950 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 951 out: 952 return budget - quota; 953 } 954 955 /* PHY state control function */ 956 static void ravb_adjust_link(struct net_device *ndev) 957 { 958 struct ravb_private *priv = netdev_priv(ndev); 959 struct phy_device *phydev = ndev->phydev; 960 bool new_state = false; 961 unsigned long flags; 962 963 spin_lock_irqsave(&priv->lock, flags); 964 965 /* Disable TX and RX right over here, if E-MAC change is ignored */ 966 if (priv->no_avb_link) 967 ravb_rcv_snd_disable(ndev); 968 969 if (phydev->link) { 970 if (phydev->speed != priv->speed) { 971 new_state = true; 972 priv->speed = phydev->speed; 973 ravb_set_rate(ndev); 974 } 975 if (!priv->link) { 976 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 977 new_state = true; 978 priv->link = phydev->link; 979 } 980 } else if (priv->link) { 981 new_state = true; 982 priv->link = 0; 983 priv->speed = 0; 984 } 985 986 /* Enable TX and RX right over here, if E-MAC change is ignored */ 987 if (priv->no_avb_link && phydev->link) 988 ravb_rcv_snd_enable(ndev); 989 990 spin_unlock_irqrestore(&priv->lock, flags); 991 992 if (new_state && netif_msg_link(priv)) 993 phy_print_status(phydev); 994 } 995 996 static const struct soc_device_attribute r8a7795es10[] = { 997 { .soc_id = "r8a7795", .revision = "ES1.0", }, 998 { /* sentinel */ } 999 }; 1000 1001 /* PHY init function */ 1002 static int ravb_phy_init(struct net_device *ndev) 1003 { 1004 struct device_node *np = ndev->dev.parent->of_node; 1005 struct ravb_private *priv = netdev_priv(ndev); 1006 struct phy_device *phydev; 1007 struct device_node *pn; 1008 phy_interface_t iface; 1009 int err; 1010 1011 priv->link = 0; 1012 priv->speed = 0; 1013 1014 /* Try connecting to PHY */ 1015 pn = of_parse_phandle(np, "phy-handle", 0); 1016 if (!pn) { 1017 /* In the case of a fixed PHY, the DT node associated 1018 * to the PHY is the Ethernet MAC DT node. 1019 */ 1020 if (of_phy_is_fixed_link(np)) { 1021 err = of_phy_register_fixed_link(np); 1022 if (err) 1023 return err; 1024 } 1025 pn = of_node_get(np); 1026 } 1027 1028 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII 1029 : priv->phy_interface; 1030 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface); 1031 of_node_put(pn); 1032 if (!phydev) { 1033 netdev_err(ndev, "failed to connect PHY\n"); 1034 err = -ENOENT; 1035 goto err_deregister_fixed_link; 1036 } 1037 1038 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0 1039 * at this time. 1040 */ 1041 if (soc_device_match(r8a7795es10)) { 1042 err = phy_set_max_speed(phydev, SPEED_100); 1043 if (err) { 1044 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n"); 1045 goto err_phy_disconnect; 1046 } 1047 1048 netdev_info(ndev, "limited PHY to 100Mbit/s\n"); 1049 } 1050 1051 /* 10BASE, Pause and Asym Pause is not supported */ 1052 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1053 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1054 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT); 1055 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 1056 1057 /* Half Duplex is not supported */ 1058 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1059 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1060 1061 phy_attached_info(phydev); 1062 1063 return 0; 1064 1065 err_phy_disconnect: 1066 phy_disconnect(phydev); 1067 err_deregister_fixed_link: 1068 if (of_phy_is_fixed_link(np)) 1069 of_phy_deregister_fixed_link(np); 1070 1071 return err; 1072 } 1073 1074 /* PHY control start function */ 1075 static int ravb_phy_start(struct net_device *ndev) 1076 { 1077 int error; 1078 1079 error = ravb_phy_init(ndev); 1080 if (error) 1081 return error; 1082 1083 phy_start(ndev->phydev); 1084 1085 return 0; 1086 } 1087 1088 static u32 ravb_get_msglevel(struct net_device *ndev) 1089 { 1090 struct ravb_private *priv = netdev_priv(ndev); 1091 1092 return priv->msg_enable; 1093 } 1094 1095 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1096 { 1097 struct ravb_private *priv = netdev_priv(ndev); 1098 1099 priv->msg_enable = value; 1100 } 1101 1102 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1103 "rx_queue_0_current", 1104 "tx_queue_0_current", 1105 "rx_queue_0_dirty", 1106 "tx_queue_0_dirty", 1107 "rx_queue_0_packets", 1108 "tx_queue_0_packets", 1109 "rx_queue_0_bytes", 1110 "tx_queue_0_bytes", 1111 "rx_queue_0_mcast_packets", 1112 "rx_queue_0_errors", 1113 "rx_queue_0_crc_errors", 1114 "rx_queue_0_frame_errors", 1115 "rx_queue_0_length_errors", 1116 "rx_queue_0_missed_errors", 1117 "rx_queue_0_over_errors", 1118 1119 "rx_queue_1_current", 1120 "tx_queue_1_current", 1121 "rx_queue_1_dirty", 1122 "tx_queue_1_dirty", 1123 "rx_queue_1_packets", 1124 "tx_queue_1_packets", 1125 "rx_queue_1_bytes", 1126 "tx_queue_1_bytes", 1127 "rx_queue_1_mcast_packets", 1128 "rx_queue_1_errors", 1129 "rx_queue_1_crc_errors", 1130 "rx_queue_1_frame_errors", 1131 "rx_queue_1_length_errors", 1132 "rx_queue_1_missed_errors", 1133 "rx_queue_1_over_errors", 1134 }; 1135 1136 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1137 { 1138 struct ravb_private *priv = netdev_priv(netdev); 1139 const struct ravb_hw_info *info = priv->info; 1140 1141 switch (sset) { 1142 case ETH_SS_STATS: 1143 return info->stats_len; 1144 default: 1145 return -EOPNOTSUPP; 1146 } 1147 } 1148 1149 static void ravb_get_ethtool_stats(struct net_device *ndev, 1150 struct ethtool_stats *estats, u64 *data) 1151 { 1152 struct ravb_private *priv = netdev_priv(ndev); 1153 int i = 0; 1154 int q; 1155 1156 /* Device-specific stats */ 1157 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) { 1158 struct net_device_stats *stats = &priv->stats[q]; 1159 1160 data[i++] = priv->cur_rx[q]; 1161 data[i++] = priv->cur_tx[q]; 1162 data[i++] = priv->dirty_rx[q]; 1163 data[i++] = priv->dirty_tx[q]; 1164 data[i++] = stats->rx_packets; 1165 data[i++] = stats->tx_packets; 1166 data[i++] = stats->rx_bytes; 1167 data[i++] = stats->tx_bytes; 1168 data[i++] = stats->multicast; 1169 data[i++] = stats->rx_errors; 1170 data[i++] = stats->rx_crc_errors; 1171 data[i++] = stats->rx_frame_errors; 1172 data[i++] = stats->rx_length_errors; 1173 data[i++] = stats->rx_missed_errors; 1174 data[i++] = stats->rx_over_errors; 1175 } 1176 } 1177 1178 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1179 { 1180 struct ravb_private *priv = netdev_priv(ndev); 1181 const struct ravb_hw_info *info = priv->info; 1182 1183 switch (stringset) { 1184 case ETH_SS_STATS: 1185 memcpy(data, info->gstrings_stats, info->gstrings_size); 1186 break; 1187 } 1188 } 1189 1190 static void ravb_get_ringparam(struct net_device *ndev, 1191 struct ethtool_ringparam *ring) 1192 { 1193 struct ravb_private *priv = netdev_priv(ndev); 1194 1195 ring->rx_max_pending = BE_RX_RING_MAX; 1196 ring->tx_max_pending = BE_TX_RING_MAX; 1197 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1198 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1199 } 1200 1201 static int ravb_set_ringparam(struct net_device *ndev, 1202 struct ethtool_ringparam *ring) 1203 { 1204 struct ravb_private *priv = netdev_priv(ndev); 1205 int error; 1206 1207 if (ring->tx_pending > BE_TX_RING_MAX || 1208 ring->rx_pending > BE_RX_RING_MAX || 1209 ring->tx_pending < BE_TX_RING_MIN || 1210 ring->rx_pending < BE_RX_RING_MIN) 1211 return -EINVAL; 1212 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1213 return -EINVAL; 1214 1215 if (netif_running(ndev)) { 1216 netif_device_detach(ndev); 1217 /* Stop PTP Clock driver */ 1218 if (priv->chip_id == RCAR_GEN2) 1219 ravb_ptp_stop(ndev); 1220 /* Wait for DMA stopping */ 1221 error = ravb_stop_dma(ndev); 1222 if (error) { 1223 netdev_err(ndev, 1224 "cannot set ringparam! Any AVB processes are still running?\n"); 1225 return error; 1226 } 1227 synchronize_irq(ndev->irq); 1228 1229 /* Free all the skb's in the RX queue and the DMA buffers. */ 1230 ravb_ring_free(ndev, RAVB_BE); 1231 ravb_ring_free(ndev, RAVB_NC); 1232 } 1233 1234 /* Set new parameters */ 1235 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1236 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1237 1238 if (netif_running(ndev)) { 1239 error = ravb_dmac_init(ndev); 1240 if (error) { 1241 netdev_err(ndev, 1242 "%s: ravb_dmac_init() failed, error %d\n", 1243 __func__, error); 1244 return error; 1245 } 1246 1247 ravb_emac_init(ndev); 1248 1249 /* Initialise PTP Clock driver */ 1250 if (priv->chip_id == RCAR_GEN2) 1251 ravb_ptp_init(ndev, priv->pdev); 1252 1253 netif_device_attach(ndev); 1254 } 1255 1256 return 0; 1257 } 1258 1259 static int ravb_get_ts_info(struct net_device *ndev, 1260 struct ethtool_ts_info *info) 1261 { 1262 struct ravb_private *priv = netdev_priv(ndev); 1263 1264 info->so_timestamping = 1265 SOF_TIMESTAMPING_TX_SOFTWARE | 1266 SOF_TIMESTAMPING_RX_SOFTWARE | 1267 SOF_TIMESTAMPING_SOFTWARE | 1268 SOF_TIMESTAMPING_TX_HARDWARE | 1269 SOF_TIMESTAMPING_RX_HARDWARE | 1270 SOF_TIMESTAMPING_RAW_HARDWARE; 1271 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1272 info->rx_filters = 1273 (1 << HWTSTAMP_FILTER_NONE) | 1274 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1275 (1 << HWTSTAMP_FILTER_ALL); 1276 info->phc_index = ptp_clock_index(priv->ptp.clock); 1277 1278 return 0; 1279 } 1280 1281 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1282 { 1283 struct ravb_private *priv = netdev_priv(ndev); 1284 1285 wol->supported = WAKE_MAGIC; 1286 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1287 } 1288 1289 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1290 { 1291 struct ravb_private *priv = netdev_priv(ndev); 1292 1293 if (wol->wolopts & ~WAKE_MAGIC) 1294 return -EOPNOTSUPP; 1295 1296 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1297 1298 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1299 1300 return 0; 1301 } 1302 1303 static const struct ethtool_ops ravb_ethtool_ops = { 1304 .nway_reset = phy_ethtool_nway_reset, 1305 .get_msglevel = ravb_get_msglevel, 1306 .set_msglevel = ravb_set_msglevel, 1307 .get_link = ethtool_op_get_link, 1308 .get_strings = ravb_get_strings, 1309 .get_ethtool_stats = ravb_get_ethtool_stats, 1310 .get_sset_count = ravb_get_sset_count, 1311 .get_ringparam = ravb_get_ringparam, 1312 .set_ringparam = ravb_set_ringparam, 1313 .get_ts_info = ravb_get_ts_info, 1314 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1315 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1316 .get_wol = ravb_get_wol, 1317 .set_wol = ravb_set_wol, 1318 }; 1319 1320 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler, 1321 struct net_device *ndev, struct device *dev, 1322 const char *ch) 1323 { 1324 char *name; 1325 int error; 1326 1327 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); 1328 if (!name) 1329 return -ENOMEM; 1330 error = request_irq(irq, handler, 0, name, ndev); 1331 if (error) 1332 netdev_err(ndev, "cannot request IRQ %s\n", name); 1333 1334 return error; 1335 } 1336 1337 /* Network device open function for Ethernet AVB */ 1338 static int ravb_open(struct net_device *ndev) 1339 { 1340 struct ravb_private *priv = netdev_priv(ndev); 1341 struct platform_device *pdev = priv->pdev; 1342 struct device *dev = &pdev->dev; 1343 int error; 1344 1345 napi_enable(&priv->napi[RAVB_BE]); 1346 napi_enable(&priv->napi[RAVB_NC]); 1347 1348 if (priv->chip_id == RCAR_GEN2) { 1349 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, 1350 ndev->name, ndev); 1351 if (error) { 1352 netdev_err(ndev, "cannot request IRQ\n"); 1353 goto out_napi_off; 1354 } 1355 } else { 1356 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev, 1357 dev, "ch22:multi"); 1358 if (error) 1359 goto out_napi_off; 1360 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev, 1361 dev, "ch24:emac"); 1362 if (error) 1363 goto out_free_irq; 1364 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt, 1365 ndev, dev, "ch0:rx_be"); 1366 if (error) 1367 goto out_free_irq_emac; 1368 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt, 1369 ndev, dev, "ch18:tx_be"); 1370 if (error) 1371 goto out_free_irq_be_rx; 1372 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt, 1373 ndev, dev, "ch1:rx_nc"); 1374 if (error) 1375 goto out_free_irq_be_tx; 1376 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt, 1377 ndev, dev, "ch19:tx_nc"); 1378 if (error) 1379 goto out_free_irq_nc_rx; 1380 } 1381 1382 /* Device init */ 1383 error = ravb_dmac_init(ndev); 1384 if (error) 1385 goto out_free_irq_nc_tx; 1386 ravb_emac_init(ndev); 1387 1388 /* Initialise PTP Clock driver */ 1389 if (priv->chip_id == RCAR_GEN2) 1390 ravb_ptp_init(ndev, priv->pdev); 1391 1392 netif_tx_start_all_queues(ndev); 1393 1394 /* PHY control start */ 1395 error = ravb_phy_start(ndev); 1396 if (error) 1397 goto out_ptp_stop; 1398 1399 return 0; 1400 1401 out_ptp_stop: 1402 /* Stop PTP Clock driver */ 1403 if (priv->chip_id == RCAR_GEN2) 1404 ravb_ptp_stop(ndev); 1405 out_free_irq_nc_tx: 1406 if (priv->chip_id == RCAR_GEN2) 1407 goto out_free_irq; 1408 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1409 out_free_irq_nc_rx: 1410 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1411 out_free_irq_be_tx: 1412 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1413 out_free_irq_be_rx: 1414 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1415 out_free_irq_emac: 1416 free_irq(priv->emac_irq, ndev); 1417 out_free_irq: 1418 free_irq(ndev->irq, ndev); 1419 out_napi_off: 1420 napi_disable(&priv->napi[RAVB_NC]); 1421 napi_disable(&priv->napi[RAVB_BE]); 1422 return error; 1423 } 1424 1425 /* Timeout function for Ethernet AVB */ 1426 static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1427 { 1428 struct ravb_private *priv = netdev_priv(ndev); 1429 1430 netif_err(priv, tx_err, ndev, 1431 "transmit timed out, status %08x, resetting...\n", 1432 ravb_read(ndev, ISS)); 1433 1434 /* tx_errors count up */ 1435 ndev->stats.tx_errors++; 1436 1437 schedule_work(&priv->work); 1438 } 1439 1440 static void ravb_tx_timeout_work(struct work_struct *work) 1441 { 1442 struct ravb_private *priv = container_of(work, struct ravb_private, 1443 work); 1444 struct net_device *ndev = priv->ndev; 1445 int error; 1446 1447 netif_tx_stop_all_queues(ndev); 1448 1449 /* Stop PTP Clock driver */ 1450 if (priv->chip_id == RCAR_GEN2) 1451 ravb_ptp_stop(ndev); 1452 1453 /* Wait for DMA stopping */ 1454 if (ravb_stop_dma(ndev)) { 1455 /* If ravb_stop_dma() fails, the hardware is still operating 1456 * for TX and/or RX. So, this should not call the following 1457 * functions because ravb_dmac_init() is possible to fail too. 1458 * Also, this should not retry ravb_stop_dma() again and again 1459 * here because it's possible to wait forever. So, this just 1460 * re-enables the TX and RX and skip the following 1461 * re-initialization procedure. 1462 */ 1463 ravb_rcv_snd_enable(ndev); 1464 goto out; 1465 } 1466 1467 ravb_ring_free(ndev, RAVB_BE); 1468 ravb_ring_free(ndev, RAVB_NC); 1469 1470 /* Device init */ 1471 error = ravb_dmac_init(ndev); 1472 if (error) { 1473 /* If ravb_dmac_init() fails, descriptors are freed. So, this 1474 * should return here to avoid re-enabling the TX and RX in 1475 * ravb_emac_init(). 1476 */ 1477 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n", 1478 __func__, error); 1479 return; 1480 } 1481 ravb_emac_init(ndev); 1482 1483 out: 1484 /* Initialise PTP Clock driver */ 1485 if (priv->chip_id == RCAR_GEN2) 1486 ravb_ptp_init(ndev, priv->pdev); 1487 1488 netif_tx_start_all_queues(ndev); 1489 } 1490 1491 /* Packet transmit function for Ethernet AVB */ 1492 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1493 { 1494 struct ravb_private *priv = netdev_priv(ndev); 1495 unsigned int num_tx_desc = priv->num_tx_desc; 1496 u16 q = skb_get_queue_mapping(skb); 1497 struct ravb_tstamp_skb *ts_skb; 1498 struct ravb_tx_desc *desc; 1499 unsigned long flags; 1500 u32 dma_addr; 1501 void *buffer; 1502 u32 entry; 1503 u32 len; 1504 1505 spin_lock_irqsave(&priv->lock, flags); 1506 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 1507 num_tx_desc) { 1508 netif_err(priv, tx_queued, ndev, 1509 "still transmitting with the full ring!\n"); 1510 netif_stop_subqueue(ndev, q); 1511 spin_unlock_irqrestore(&priv->lock, flags); 1512 return NETDEV_TX_BUSY; 1513 } 1514 1515 if (skb_put_padto(skb, ETH_ZLEN)) 1516 goto exit; 1517 1518 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc); 1519 priv->tx_skb[q][entry / num_tx_desc] = skb; 1520 1521 if (num_tx_desc > 1) { 1522 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 1523 entry / num_tx_desc * DPTR_ALIGN; 1524 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 1525 1526 /* Zero length DMA descriptors are problematic as they seem 1527 * to terminate DMA transfers. Avoid them by simply using a 1528 * length of DPTR_ALIGN (4) when skb data is aligned to 1529 * DPTR_ALIGN. 1530 * 1531 * As skb is guaranteed to have at least ETH_ZLEN (60) 1532 * bytes of data by the call to skb_put_padto() above this 1533 * is safe with respect to both the length of the first DMA 1534 * descriptor (len) overflowing the available data and the 1535 * length of the second DMA descriptor (skb->len - len) 1536 * being negative. 1537 */ 1538 if (len == 0) 1539 len = DPTR_ALIGN; 1540 1541 memcpy(buffer, skb->data, len); 1542 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1543 DMA_TO_DEVICE); 1544 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1545 goto drop; 1546 1547 desc = &priv->tx_ring[q][entry]; 1548 desc->ds_tagl = cpu_to_le16(len); 1549 desc->dptr = cpu_to_le32(dma_addr); 1550 1551 buffer = skb->data + len; 1552 len = skb->len - len; 1553 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 1554 DMA_TO_DEVICE); 1555 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1556 goto unmap; 1557 1558 desc++; 1559 } else { 1560 desc = &priv->tx_ring[q][entry]; 1561 len = skb->len; 1562 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, 1563 DMA_TO_DEVICE); 1564 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1565 goto drop; 1566 } 1567 desc->ds_tagl = cpu_to_le16(len); 1568 desc->dptr = cpu_to_le32(dma_addr); 1569 1570 /* TX timestamp required */ 1571 if (q == RAVB_NC) { 1572 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 1573 if (!ts_skb) { 1574 if (num_tx_desc > 1) { 1575 desc--; 1576 dma_unmap_single(ndev->dev.parent, dma_addr, 1577 len, DMA_TO_DEVICE); 1578 } 1579 goto unmap; 1580 } 1581 ts_skb->skb = skb_get(skb); 1582 ts_skb->tag = priv->ts_skb_tag++; 1583 priv->ts_skb_tag &= 0x3ff; 1584 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 1585 1586 /* TAG and timestamp required flag */ 1587 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1588 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 1589 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12); 1590 } 1591 1592 skb_tx_timestamp(skb); 1593 /* Descriptor type must be set after all the above writes */ 1594 dma_wmb(); 1595 if (num_tx_desc > 1) { 1596 desc->die_dt = DT_FEND; 1597 desc--; 1598 desc->die_dt = DT_FSTART; 1599 } else { 1600 desc->die_dt = DT_FSINGLE; 1601 } 1602 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 1603 1604 priv->cur_tx[q] += num_tx_desc; 1605 if (priv->cur_tx[q] - priv->dirty_tx[q] > 1606 (priv->num_tx_ring[q] - 1) * num_tx_desc && 1607 !ravb_tx_free(ndev, q, true)) 1608 netif_stop_subqueue(ndev, q); 1609 1610 exit: 1611 spin_unlock_irqrestore(&priv->lock, flags); 1612 return NETDEV_TX_OK; 1613 1614 unmap: 1615 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 1616 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 1617 drop: 1618 dev_kfree_skb_any(skb); 1619 priv->tx_skb[q][entry / num_tx_desc] = NULL; 1620 goto exit; 1621 } 1622 1623 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 1624 struct net_device *sb_dev) 1625 { 1626 /* If skb needs TX timestamp, it is handled in network control queue */ 1627 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 1628 RAVB_BE; 1629 1630 } 1631 1632 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 1633 { 1634 struct ravb_private *priv = netdev_priv(ndev); 1635 const struct ravb_hw_info *info = priv->info; 1636 struct net_device_stats *nstats, *stats0, *stats1; 1637 1638 nstats = &ndev->stats; 1639 stats0 = &priv->stats[RAVB_BE]; 1640 stats1 = &priv->stats[RAVB_NC]; 1641 1642 if (info->tx_counters) { 1643 nstats->tx_dropped += ravb_read(ndev, TROCR); 1644 ravb_write(ndev, 0, TROCR); /* (write clear) */ 1645 } 1646 1647 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets; 1648 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets; 1649 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes; 1650 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes; 1651 nstats->multicast = stats0->multicast + stats1->multicast; 1652 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors; 1653 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors; 1654 nstats->rx_frame_errors = 1655 stats0->rx_frame_errors + stats1->rx_frame_errors; 1656 nstats->rx_length_errors = 1657 stats0->rx_length_errors + stats1->rx_length_errors; 1658 nstats->rx_missed_errors = 1659 stats0->rx_missed_errors + stats1->rx_missed_errors; 1660 nstats->rx_over_errors = 1661 stats0->rx_over_errors + stats1->rx_over_errors; 1662 1663 return nstats; 1664 } 1665 1666 /* Update promiscuous bit */ 1667 static void ravb_set_rx_mode(struct net_device *ndev) 1668 { 1669 struct ravb_private *priv = netdev_priv(ndev); 1670 unsigned long flags; 1671 1672 spin_lock_irqsave(&priv->lock, flags); 1673 ravb_modify(ndev, ECMR, ECMR_PRM, 1674 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 1675 spin_unlock_irqrestore(&priv->lock, flags); 1676 } 1677 1678 /* Device close function for Ethernet AVB */ 1679 static int ravb_close(struct net_device *ndev) 1680 { 1681 struct device_node *np = ndev->dev.parent->of_node; 1682 struct ravb_private *priv = netdev_priv(ndev); 1683 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 1684 1685 netif_tx_stop_all_queues(ndev); 1686 1687 /* Disable interrupts by clearing the interrupt masks. */ 1688 ravb_write(ndev, 0, RIC0); 1689 ravb_write(ndev, 0, RIC2); 1690 ravb_write(ndev, 0, TIC); 1691 1692 /* Stop PTP Clock driver */ 1693 if (priv->chip_id == RCAR_GEN2) 1694 ravb_ptp_stop(ndev); 1695 1696 /* Set the config mode to stop the AVB-DMAC's processes */ 1697 if (ravb_stop_dma(ndev) < 0) 1698 netdev_err(ndev, 1699 "device will be stopped after h/w processes are done.\n"); 1700 1701 /* Clear the timestamp list */ 1702 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 1703 list_del(&ts_skb->list); 1704 kfree_skb(ts_skb->skb); 1705 kfree(ts_skb); 1706 } 1707 1708 /* PHY disconnect */ 1709 if (ndev->phydev) { 1710 phy_stop(ndev->phydev); 1711 phy_disconnect(ndev->phydev); 1712 if (of_phy_is_fixed_link(np)) 1713 of_phy_deregister_fixed_link(np); 1714 } 1715 1716 if (priv->chip_id != RCAR_GEN2) { 1717 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1718 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1719 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1720 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1721 free_irq(priv->emac_irq, ndev); 1722 } 1723 free_irq(ndev->irq, ndev); 1724 1725 napi_disable(&priv->napi[RAVB_NC]); 1726 napi_disable(&priv->napi[RAVB_BE]); 1727 1728 /* Free all the skb's in the RX queue and the DMA buffers. */ 1729 ravb_ring_free(ndev, RAVB_BE); 1730 ravb_ring_free(ndev, RAVB_NC); 1731 1732 return 0; 1733 } 1734 1735 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 1736 { 1737 struct ravb_private *priv = netdev_priv(ndev); 1738 struct hwtstamp_config config; 1739 1740 config.flags = 0; 1741 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 1742 HWTSTAMP_TX_OFF; 1743 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) { 1744 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT: 1745 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1746 break; 1747 case RAVB_RXTSTAMP_TYPE_ALL: 1748 config.rx_filter = HWTSTAMP_FILTER_ALL; 1749 break; 1750 default: 1751 config.rx_filter = HWTSTAMP_FILTER_NONE; 1752 } 1753 1754 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1755 -EFAULT : 0; 1756 } 1757 1758 /* Control hardware time stamping */ 1759 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 1760 { 1761 struct ravb_private *priv = netdev_priv(ndev); 1762 struct hwtstamp_config config; 1763 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 1764 u32 tstamp_tx_ctrl; 1765 1766 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 1767 return -EFAULT; 1768 1769 /* Reserved for future extensions */ 1770 if (config.flags) 1771 return -EINVAL; 1772 1773 switch (config.tx_type) { 1774 case HWTSTAMP_TX_OFF: 1775 tstamp_tx_ctrl = 0; 1776 break; 1777 case HWTSTAMP_TX_ON: 1778 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 1779 break; 1780 default: 1781 return -ERANGE; 1782 } 1783 1784 switch (config.rx_filter) { 1785 case HWTSTAMP_FILTER_NONE: 1786 tstamp_rx_ctrl = 0; 1787 break; 1788 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1789 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 1790 break; 1791 default: 1792 config.rx_filter = HWTSTAMP_FILTER_ALL; 1793 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 1794 } 1795 1796 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 1797 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 1798 1799 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1800 -EFAULT : 0; 1801 } 1802 1803 /* ioctl to device function */ 1804 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 1805 { 1806 struct phy_device *phydev = ndev->phydev; 1807 1808 if (!netif_running(ndev)) 1809 return -EINVAL; 1810 1811 if (!phydev) 1812 return -ENODEV; 1813 1814 switch (cmd) { 1815 case SIOCGHWTSTAMP: 1816 return ravb_hwtstamp_get(ndev, req); 1817 case SIOCSHWTSTAMP: 1818 return ravb_hwtstamp_set(ndev, req); 1819 } 1820 1821 return phy_mii_ioctl(phydev, req, cmd); 1822 } 1823 1824 static int ravb_change_mtu(struct net_device *ndev, int new_mtu) 1825 { 1826 struct ravb_private *priv = netdev_priv(ndev); 1827 1828 ndev->mtu = new_mtu; 1829 1830 if (netif_running(ndev)) { 1831 synchronize_irq(priv->emac_irq); 1832 ravb_emac_init(ndev); 1833 } 1834 1835 netdev_update_features(ndev); 1836 1837 return 0; 1838 } 1839 1840 static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 1841 { 1842 struct ravb_private *priv = netdev_priv(ndev); 1843 unsigned long flags; 1844 1845 spin_lock_irqsave(&priv->lock, flags); 1846 1847 /* Disable TX and RX */ 1848 ravb_rcv_snd_disable(ndev); 1849 1850 /* Modify RX Checksum setting */ 1851 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 1852 1853 /* Enable TX and RX */ 1854 ravb_rcv_snd_enable(ndev); 1855 1856 spin_unlock_irqrestore(&priv->lock, flags); 1857 } 1858 1859 static int ravb_set_features(struct net_device *ndev, 1860 netdev_features_t features) 1861 { 1862 netdev_features_t changed = ndev->features ^ features; 1863 1864 if (changed & NETIF_F_RXCSUM) 1865 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 1866 1867 ndev->features = features; 1868 1869 return 0; 1870 } 1871 1872 static const struct net_device_ops ravb_netdev_ops = { 1873 .ndo_open = ravb_open, 1874 .ndo_stop = ravb_close, 1875 .ndo_start_xmit = ravb_start_xmit, 1876 .ndo_select_queue = ravb_select_queue, 1877 .ndo_get_stats = ravb_get_stats, 1878 .ndo_set_rx_mode = ravb_set_rx_mode, 1879 .ndo_tx_timeout = ravb_tx_timeout, 1880 .ndo_eth_ioctl = ravb_do_ioctl, 1881 .ndo_change_mtu = ravb_change_mtu, 1882 .ndo_validate_addr = eth_validate_addr, 1883 .ndo_set_mac_address = eth_mac_addr, 1884 .ndo_set_features = ravb_set_features, 1885 }; 1886 1887 /* MDIO bus init function */ 1888 static int ravb_mdio_init(struct ravb_private *priv) 1889 { 1890 struct platform_device *pdev = priv->pdev; 1891 struct device *dev = &pdev->dev; 1892 int error; 1893 1894 /* Bitbang init */ 1895 priv->mdiobb.ops = &bb_ops; 1896 1897 /* MII controller setting */ 1898 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 1899 if (!priv->mii_bus) 1900 return -ENOMEM; 1901 1902 /* Hook up MII support for ethtool */ 1903 priv->mii_bus->name = "ravb_mii"; 1904 priv->mii_bus->parent = dev; 1905 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1906 pdev->name, pdev->id); 1907 1908 /* Register MDIO bus */ 1909 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 1910 if (error) 1911 goto out_free_bus; 1912 1913 return 0; 1914 1915 out_free_bus: 1916 free_mdio_bitbang(priv->mii_bus); 1917 return error; 1918 } 1919 1920 /* MDIO bus release function */ 1921 static int ravb_mdio_release(struct ravb_private *priv) 1922 { 1923 /* Unregister mdio bus */ 1924 mdiobus_unregister(priv->mii_bus); 1925 1926 /* Free bitbang info */ 1927 free_mdio_bitbang(priv->mii_bus); 1928 1929 return 0; 1930 } 1931 1932 static const struct ravb_hw_info ravb_gen3_hw_info = { 1933 .gstrings_stats = ravb_gstrings_stats, 1934 .gstrings_size = sizeof(ravb_gstrings_stats), 1935 .net_hw_features = NETIF_F_RXCSUM, 1936 .net_features = NETIF_F_RXCSUM, 1937 .chip_id = RCAR_GEN3, 1938 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 1939 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 1940 .internal_delay = 1, 1941 .tx_counters = 1, 1942 }; 1943 1944 static const struct ravb_hw_info ravb_gen2_hw_info = { 1945 .gstrings_stats = ravb_gstrings_stats, 1946 .gstrings_size = sizeof(ravb_gstrings_stats), 1947 .net_hw_features = NETIF_F_RXCSUM, 1948 .net_features = NETIF_F_RXCSUM, 1949 .chip_id = RCAR_GEN2, 1950 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 1951 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 1952 .aligned_tx = 1, 1953 }; 1954 1955 static const struct of_device_id ravb_match_table[] = { 1956 { .compatible = "renesas,etheravb-r8a7790", .data = &ravb_gen2_hw_info }, 1957 { .compatible = "renesas,etheravb-r8a7794", .data = &ravb_gen2_hw_info }, 1958 { .compatible = "renesas,etheravb-rcar-gen2", .data = &ravb_gen2_hw_info }, 1959 { .compatible = "renesas,etheravb-r8a7795", .data = &ravb_gen3_hw_info }, 1960 { .compatible = "renesas,etheravb-rcar-gen3", .data = &ravb_gen3_hw_info }, 1961 { } 1962 }; 1963 MODULE_DEVICE_TABLE(of, ravb_match_table); 1964 1965 static int ravb_set_gti(struct net_device *ndev) 1966 { 1967 struct ravb_private *priv = netdev_priv(ndev); 1968 struct device *dev = ndev->dev.parent; 1969 unsigned long rate; 1970 uint64_t inc; 1971 1972 rate = clk_get_rate(priv->clk); 1973 if (!rate) 1974 return -EINVAL; 1975 1976 inc = 1000000000ULL << 20; 1977 do_div(inc, rate); 1978 1979 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 1980 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 1981 inc, GTI_TIV_MIN, GTI_TIV_MAX); 1982 return -EINVAL; 1983 } 1984 1985 ravb_write(ndev, inc, GTI); 1986 1987 return 0; 1988 } 1989 1990 static void ravb_set_config_mode(struct net_device *ndev) 1991 { 1992 struct ravb_private *priv = netdev_priv(ndev); 1993 1994 if (priv->chip_id == RCAR_GEN2) { 1995 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 1996 /* Set CSEL value */ 1997 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 1998 } else { 1999 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG | 2000 CCC_GAC | CCC_CSEL_HPB); 2001 } 2002 } 2003 2004 /* Set tx and rx clock internal delay modes */ 2005 static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev) 2006 { 2007 struct ravb_private *priv = netdev_priv(ndev); 2008 bool explicit_delay = false; 2009 u32 delay; 2010 2011 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) { 2012 /* Valid values are 0 and 1800, according to DT bindings */ 2013 priv->rxcidm = !!delay; 2014 explicit_delay = true; 2015 } 2016 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) { 2017 /* Valid values are 0 and 2000, according to DT bindings */ 2018 priv->txcidm = !!delay; 2019 explicit_delay = true; 2020 } 2021 2022 if (explicit_delay) 2023 return; 2024 2025 /* Fall back to legacy rgmii-*id behavior */ 2026 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 2027 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) { 2028 priv->rxcidm = 1; 2029 priv->rgmii_override = 1; 2030 } 2031 2032 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 2033 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) { 2034 priv->txcidm = 1; 2035 priv->rgmii_override = 1; 2036 } 2037 } 2038 2039 static void ravb_set_delay_mode(struct net_device *ndev) 2040 { 2041 struct ravb_private *priv = netdev_priv(ndev); 2042 u32 set = 0; 2043 2044 if (priv->rxcidm) 2045 set |= APSR_RDM; 2046 if (priv->txcidm) 2047 set |= APSR_TDM; 2048 ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set); 2049 } 2050 2051 static int ravb_probe(struct platform_device *pdev) 2052 { 2053 struct device_node *np = pdev->dev.of_node; 2054 const struct ravb_hw_info *info; 2055 struct ravb_private *priv; 2056 struct net_device *ndev; 2057 int error, irq, q; 2058 struct resource *res; 2059 int i; 2060 2061 if (!np) { 2062 dev_err(&pdev->dev, 2063 "this driver is required to be instantiated from device tree\n"); 2064 return -EINVAL; 2065 } 2066 2067 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 2068 NUM_TX_QUEUE, NUM_RX_QUEUE); 2069 if (!ndev) 2070 return -ENOMEM; 2071 2072 info = of_device_get_match_data(&pdev->dev); 2073 2074 ndev->features = info->net_features; 2075 ndev->hw_features = info->net_hw_features; 2076 2077 pm_runtime_enable(&pdev->dev); 2078 pm_runtime_get_sync(&pdev->dev); 2079 2080 if (info->chip_id == RCAR_GEN3) 2081 irq = platform_get_irq_byname(pdev, "ch22"); 2082 else 2083 irq = platform_get_irq(pdev, 0); 2084 if (irq < 0) { 2085 error = irq; 2086 goto out_release; 2087 } 2088 ndev->irq = irq; 2089 2090 SET_NETDEV_DEV(ndev, &pdev->dev); 2091 2092 priv = netdev_priv(ndev); 2093 priv->info = info; 2094 priv->ndev = ndev; 2095 priv->pdev = pdev; 2096 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2097 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2098 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2099 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2100 priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2101 if (IS_ERR(priv->addr)) { 2102 error = PTR_ERR(priv->addr); 2103 goto out_release; 2104 } 2105 2106 /* The Ether-specific entries in the device structure. */ 2107 ndev->base_addr = res->start; 2108 2109 spin_lock_init(&priv->lock); 2110 INIT_WORK(&priv->work, ravb_tx_timeout_work); 2111 2112 error = of_get_phy_mode(np, &priv->phy_interface); 2113 if (error && error != -ENODEV) 2114 goto out_release; 2115 2116 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 2117 priv->avb_link_active_low = 2118 of_property_read_bool(np, "renesas,ether-link-active-low"); 2119 2120 if (info->chip_id == RCAR_GEN3) { 2121 irq = platform_get_irq_byname(pdev, "ch24"); 2122 if (irq < 0) { 2123 error = irq; 2124 goto out_release; 2125 } 2126 priv->emac_irq = irq; 2127 for (i = 0; i < NUM_RX_QUEUE; i++) { 2128 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); 2129 if (irq < 0) { 2130 error = irq; 2131 goto out_release; 2132 } 2133 priv->rx_irqs[i] = irq; 2134 } 2135 for (i = 0; i < NUM_TX_QUEUE; i++) { 2136 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); 2137 if (irq < 0) { 2138 error = irq; 2139 goto out_release; 2140 } 2141 priv->tx_irqs[i] = irq; 2142 } 2143 } 2144 2145 priv->chip_id = info->chip_id; 2146 2147 priv->clk = devm_clk_get(&pdev->dev, NULL); 2148 if (IS_ERR(priv->clk)) { 2149 error = PTR_ERR(priv->clk); 2150 goto out_release; 2151 } 2152 2153 priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk"); 2154 if (IS_ERR(priv->refclk)) { 2155 error = PTR_ERR(priv->refclk); 2156 goto out_release; 2157 } 2158 clk_prepare_enable(priv->refclk); 2159 2160 ndev->max_mtu = 2048 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 2161 ndev->min_mtu = ETH_MIN_MTU; 2162 2163 priv->num_tx_desc = info->aligned_tx ? 2164 NUM_TX_DESC_GEN2 : NUM_TX_DESC_GEN3; 2165 2166 /* Set function */ 2167 ndev->netdev_ops = &ravb_netdev_ops; 2168 ndev->ethtool_ops = &ravb_ethtool_ops; 2169 2170 /* Set AVB config mode */ 2171 ravb_set_config_mode(ndev); 2172 2173 /* Set GTI value */ 2174 error = ravb_set_gti(ndev); 2175 if (error) 2176 goto out_disable_refclk; 2177 2178 /* Request GTI loading */ 2179 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2180 2181 if (info->internal_delay) { 2182 ravb_parse_delay_mode(np, ndev); 2183 ravb_set_delay_mode(ndev); 2184 } 2185 2186 /* Allocate descriptor base address table */ 2187 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 2188 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 2189 &priv->desc_bat_dma, GFP_KERNEL); 2190 if (!priv->desc_bat) { 2191 dev_err(&pdev->dev, 2192 "Cannot allocate desc base address table (size %d bytes)\n", 2193 priv->desc_bat_size); 2194 error = -ENOMEM; 2195 goto out_disable_refclk; 2196 } 2197 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 2198 priv->desc_bat[q].die_dt = DT_EOS; 2199 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2200 2201 /* Initialise HW timestamp list */ 2202 INIT_LIST_HEAD(&priv->ts_skb_list); 2203 2204 /* Initialise PTP Clock driver */ 2205 if (info->chip_id != RCAR_GEN2) 2206 ravb_ptp_init(ndev, pdev); 2207 2208 /* Debug message level */ 2209 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 2210 2211 /* Read and set MAC address */ 2212 ravb_read_mac_address(np, ndev); 2213 if (!is_valid_ether_addr(ndev->dev_addr)) { 2214 dev_warn(&pdev->dev, 2215 "no valid MAC address supplied, using a random one\n"); 2216 eth_hw_addr_random(ndev); 2217 } 2218 2219 /* MDIO bus init */ 2220 error = ravb_mdio_init(priv); 2221 if (error) { 2222 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 2223 goto out_dma_free; 2224 } 2225 2226 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64); 2227 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64); 2228 2229 /* Network device register */ 2230 error = register_netdev(ndev); 2231 if (error) 2232 goto out_napi_del; 2233 2234 device_set_wakeup_capable(&pdev->dev, 1); 2235 2236 /* Print device information */ 2237 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 2238 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2239 2240 platform_set_drvdata(pdev, ndev); 2241 2242 return 0; 2243 2244 out_napi_del: 2245 netif_napi_del(&priv->napi[RAVB_NC]); 2246 netif_napi_del(&priv->napi[RAVB_BE]); 2247 ravb_mdio_release(priv); 2248 out_dma_free: 2249 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2250 priv->desc_bat_dma); 2251 2252 /* Stop PTP Clock driver */ 2253 if (info->chip_id != RCAR_GEN2) 2254 ravb_ptp_stop(ndev); 2255 out_disable_refclk: 2256 clk_disable_unprepare(priv->refclk); 2257 out_release: 2258 free_netdev(ndev); 2259 2260 pm_runtime_put(&pdev->dev); 2261 pm_runtime_disable(&pdev->dev); 2262 return error; 2263 } 2264 2265 static int ravb_remove(struct platform_device *pdev) 2266 { 2267 struct net_device *ndev = platform_get_drvdata(pdev); 2268 struct ravb_private *priv = netdev_priv(ndev); 2269 2270 /* Stop PTP Clock driver */ 2271 if (priv->chip_id != RCAR_GEN2) 2272 ravb_ptp_stop(ndev); 2273 2274 clk_disable_unprepare(priv->refclk); 2275 2276 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2277 priv->desc_bat_dma); 2278 /* Set reset mode */ 2279 ravb_write(ndev, CCC_OPC_RESET, CCC); 2280 pm_runtime_put_sync(&pdev->dev); 2281 unregister_netdev(ndev); 2282 netif_napi_del(&priv->napi[RAVB_NC]); 2283 netif_napi_del(&priv->napi[RAVB_BE]); 2284 ravb_mdio_release(priv); 2285 pm_runtime_disable(&pdev->dev); 2286 free_netdev(ndev); 2287 platform_set_drvdata(pdev, NULL); 2288 2289 return 0; 2290 } 2291 2292 static int ravb_wol_setup(struct net_device *ndev) 2293 { 2294 struct ravb_private *priv = netdev_priv(ndev); 2295 2296 /* Disable interrupts by clearing the interrupt masks. */ 2297 ravb_write(ndev, 0, RIC0); 2298 ravb_write(ndev, 0, RIC2); 2299 ravb_write(ndev, 0, TIC); 2300 2301 /* Only allow ECI interrupts */ 2302 synchronize_irq(priv->emac_irq); 2303 napi_disable(&priv->napi[RAVB_NC]); 2304 napi_disable(&priv->napi[RAVB_BE]); 2305 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 2306 2307 /* Enable MagicPacket */ 2308 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 2309 2310 return enable_irq_wake(priv->emac_irq); 2311 } 2312 2313 static int ravb_wol_restore(struct net_device *ndev) 2314 { 2315 struct ravb_private *priv = netdev_priv(ndev); 2316 int ret; 2317 2318 napi_enable(&priv->napi[RAVB_NC]); 2319 napi_enable(&priv->napi[RAVB_BE]); 2320 2321 /* Disable MagicPacket */ 2322 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 2323 2324 ret = ravb_close(ndev); 2325 if (ret < 0) 2326 return ret; 2327 2328 return disable_irq_wake(priv->emac_irq); 2329 } 2330 2331 static int __maybe_unused ravb_suspend(struct device *dev) 2332 { 2333 struct net_device *ndev = dev_get_drvdata(dev); 2334 struct ravb_private *priv = netdev_priv(ndev); 2335 int ret; 2336 2337 if (!netif_running(ndev)) 2338 return 0; 2339 2340 netif_device_detach(ndev); 2341 2342 if (priv->wol_enabled) 2343 ret = ravb_wol_setup(ndev); 2344 else 2345 ret = ravb_close(ndev); 2346 2347 return ret; 2348 } 2349 2350 static int __maybe_unused ravb_resume(struct device *dev) 2351 { 2352 struct net_device *ndev = dev_get_drvdata(dev); 2353 struct ravb_private *priv = netdev_priv(ndev); 2354 const struct ravb_hw_info *info = priv->info; 2355 int ret = 0; 2356 2357 /* If WoL is enabled set reset mode to rearm the WoL logic */ 2358 if (priv->wol_enabled) 2359 ravb_write(ndev, CCC_OPC_RESET, CCC); 2360 2361 /* All register have been reset to default values. 2362 * Restore all registers which where setup at probe time and 2363 * reopen device if it was running before system suspended. 2364 */ 2365 2366 /* Set AVB config mode */ 2367 ravb_set_config_mode(ndev); 2368 2369 /* Set GTI value */ 2370 ret = ravb_set_gti(ndev); 2371 if (ret) 2372 return ret; 2373 2374 /* Request GTI loading */ 2375 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2376 2377 if (info->internal_delay) 2378 ravb_set_delay_mode(ndev); 2379 2380 /* Restore descriptor base address table */ 2381 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2382 2383 if (netif_running(ndev)) { 2384 if (priv->wol_enabled) { 2385 ret = ravb_wol_restore(ndev); 2386 if (ret) 2387 return ret; 2388 } 2389 ret = ravb_open(ndev); 2390 if (ret < 0) 2391 return ret; 2392 netif_device_attach(ndev); 2393 } 2394 2395 return ret; 2396 } 2397 2398 static int __maybe_unused ravb_runtime_nop(struct device *dev) 2399 { 2400 /* Runtime PM callback shared between ->runtime_suspend() 2401 * and ->runtime_resume(). Simply returns success. 2402 * 2403 * This driver re-initializes all registers after 2404 * pm_runtime_get_sync() anyway so there is no need 2405 * to save and restore registers here. 2406 */ 2407 return 0; 2408 } 2409 2410 static const struct dev_pm_ops ravb_dev_pm_ops = { 2411 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 2412 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL) 2413 }; 2414 2415 static struct platform_driver ravb_driver = { 2416 .probe = ravb_probe, 2417 .remove = ravb_remove, 2418 .driver = { 2419 .name = "ravb", 2420 .pm = &ravb_dev_pm_ops, 2421 .of_match_table = ravb_match_table, 2422 }, 2423 }; 2424 2425 module_platform_driver(ravb_driver); 2426 2427 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 2428 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 2429 MODULE_LICENSE("GPL v2"); 2430