1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet AVB device driver 3 * 4 * Copyright (C) 2014-2019 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * Based on the SuperH Ethernet driver 9 */ 10 11 #include <linux/cache.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_vlan.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/module.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/of.h> 24 #include <linux/of_mdio.h> 25 #include <linux/of_net.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/slab.h> 29 #include <linux/spinlock.h> 30 #include <linux/reset.h> 31 #include <linux/math64.h> 32 #include <net/ip.h> 33 #include <net/page_pool/helpers.h> 34 35 #include "ravb.h" 36 37 #define RAVB_DEF_MSG_ENABLE \ 38 (NETIF_MSG_LINK | \ 39 NETIF_MSG_TIMER | \ 40 NETIF_MSG_RX_ERR | \ 41 NETIF_MSG_TX_ERR) 42 43 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 44 u32 set) 45 { 46 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 47 } 48 49 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 50 { 51 int i; 52 53 for (i = 0; i < 10000; i++) { 54 if ((ravb_read(ndev, reg) & mask) == value) 55 return 0; 56 udelay(10); 57 } 58 return -ETIMEDOUT; 59 } 60 61 static int ravb_set_opmode(struct net_device *ndev, u32 opmode) 62 { 63 u32 csr_ops = 1U << (opmode & CCC_OPC); 64 u32 ccc_mask = CCC_OPC; 65 int error; 66 67 /* If gPTP active in config mode is supported it needs to be configured 68 * along with CSEL and operating mode in the same access. This is a 69 * hardware limitation. 70 */ 71 if (opmode & CCC_GAC) 72 ccc_mask |= CCC_GAC | CCC_CSEL; 73 74 /* Set operating mode */ 75 ravb_modify(ndev, CCC, ccc_mask, opmode); 76 /* Check if the operating mode is changed to the requested one */ 77 error = ravb_wait(ndev, CSR, CSR_OPS, csr_ops); 78 if (error) { 79 netdev_err(ndev, "failed to switch device to requested mode (%u)\n", 80 opmode & CCC_OPC); 81 } 82 83 return error; 84 } 85 86 static void ravb_set_rate_gbeth(struct net_device *ndev) 87 { 88 struct ravb_private *priv = netdev_priv(ndev); 89 90 switch (priv->speed) { 91 case 10: /* 10BASE */ 92 ravb_write(ndev, GBETH_GECMR_SPEED_10, GECMR); 93 break; 94 case 100: /* 100BASE */ 95 ravb_write(ndev, GBETH_GECMR_SPEED_100, GECMR); 96 break; 97 case 1000: /* 1000BASE */ 98 ravb_write(ndev, GBETH_GECMR_SPEED_1000, GECMR); 99 break; 100 } 101 } 102 103 static void ravb_set_rate_rcar(struct net_device *ndev) 104 { 105 struct ravb_private *priv = netdev_priv(ndev); 106 107 switch (priv->speed) { 108 case 100: /* 100BASE */ 109 ravb_write(ndev, GECMR_SPEED_100, GECMR); 110 break; 111 case 1000: /* 1000BASE */ 112 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 113 break; 114 } 115 } 116 117 /* Get MAC address from the MAC address registers 118 * 119 * Ethernet AVB device doesn't have ROM for MAC address. 120 * This function gets the MAC address that was used by a bootloader. 121 */ 122 static void ravb_read_mac_address(struct device_node *np, 123 struct net_device *ndev) 124 { 125 int ret; 126 127 ret = of_get_ethdev_address(np, ndev); 128 if (ret) { 129 u32 mahr = ravb_read(ndev, MAHR); 130 u32 malr = ravb_read(ndev, MALR); 131 u8 addr[ETH_ALEN]; 132 133 addr[0] = (mahr >> 24) & 0xFF; 134 addr[1] = (mahr >> 16) & 0xFF; 135 addr[2] = (mahr >> 8) & 0xFF; 136 addr[3] = (mahr >> 0) & 0xFF; 137 addr[4] = (malr >> 8) & 0xFF; 138 addr[5] = (malr >> 0) & 0xFF; 139 eth_hw_addr_set(ndev, addr); 140 } 141 } 142 143 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 144 { 145 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 146 mdiobb); 147 148 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 149 } 150 151 /* MDC pin control */ 152 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 153 { 154 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 155 } 156 157 /* Data I/O pin control */ 158 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 159 { 160 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 161 } 162 163 /* Set data bit */ 164 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 165 { 166 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 167 } 168 169 /* Get data bit */ 170 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 171 { 172 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 173 mdiobb); 174 175 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 176 } 177 178 /* MDIO bus control struct */ 179 static const struct mdiobb_ops bb_ops = { 180 .owner = THIS_MODULE, 181 .set_mdc = ravb_set_mdc, 182 .set_mdio_dir = ravb_set_mdio_dir, 183 .set_mdio_data = ravb_set_mdio_data, 184 .get_mdio_data = ravb_get_mdio_data, 185 }; 186 187 static struct ravb_rx_desc * 188 ravb_rx_get_desc(struct ravb_private *priv, unsigned int q, 189 unsigned int i) 190 { 191 return priv->rx_ring[q].raw + priv->info->rx_desc_size * i; 192 } 193 194 /* Free TX skb function for AVB-IP */ 195 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 196 { 197 struct ravb_private *priv = netdev_priv(ndev); 198 struct net_device_stats *stats = &priv->stats[q]; 199 unsigned int num_tx_desc = priv->num_tx_desc; 200 struct ravb_tx_desc *desc; 201 unsigned int entry; 202 int free_num = 0; 203 u32 size; 204 205 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 206 bool txed; 207 208 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 209 num_tx_desc); 210 desc = &priv->tx_ring[q][entry]; 211 txed = desc->die_dt == DT_FEMPTY; 212 if (free_txed_only && !txed) 213 break; 214 /* Descriptor type must be checked before all other reads */ 215 dma_rmb(); 216 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 217 /* Free the original skb. */ 218 if (priv->tx_skb[q][entry / num_tx_desc]) { 219 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 220 size, DMA_TO_DEVICE); 221 /* Last packet descriptor? */ 222 if (entry % num_tx_desc == num_tx_desc - 1) { 223 entry /= num_tx_desc; 224 dev_kfree_skb_any(priv->tx_skb[q][entry]); 225 priv->tx_skb[q][entry] = NULL; 226 if (txed) 227 stats->tx_packets++; 228 } 229 free_num++; 230 } 231 if (txed) 232 stats->tx_bytes += size; 233 desc->die_dt = DT_EEMPTY; 234 } 235 return free_num; 236 } 237 238 static void ravb_rx_ring_free(struct net_device *ndev, int q) 239 { 240 struct ravb_private *priv = netdev_priv(ndev); 241 unsigned int ring_size; 242 243 if (!priv->rx_ring[q].raw) 244 return; 245 246 ring_size = priv->info->rx_desc_size * (priv->num_rx_ring[q] + 1); 247 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q].raw, 248 priv->rx_desc_dma[q]); 249 priv->rx_ring[q].raw = NULL; 250 } 251 252 /* Free skb's and DMA buffers for Ethernet AVB */ 253 static void ravb_ring_free(struct net_device *ndev, int q) 254 { 255 struct ravb_private *priv = netdev_priv(ndev); 256 unsigned int num_tx_desc = priv->num_tx_desc; 257 unsigned int ring_size; 258 unsigned int i; 259 260 ravb_rx_ring_free(ndev, q); 261 262 if (priv->tx_ring[q]) { 263 ravb_tx_free(ndev, q, false); 264 265 ring_size = sizeof(struct ravb_tx_desc) * 266 (priv->num_tx_ring[q] * num_tx_desc + 1); 267 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 268 priv->tx_desc_dma[q]); 269 priv->tx_ring[q] = NULL; 270 } 271 272 /* Free RX buffers */ 273 for (i = 0; i < priv->num_rx_ring[q]; i++) { 274 if (priv->rx_buffers[q][i].page) 275 page_pool_put_page(priv->rx_pool[q], 276 priv->rx_buffers[q][i].page, 277 0, true); 278 } 279 kfree(priv->rx_buffers[q]); 280 priv->rx_buffers[q] = NULL; 281 page_pool_destroy(priv->rx_pool[q]); 282 283 /* Free aligned TX buffers */ 284 kfree(priv->tx_align[q]); 285 priv->tx_align[q] = NULL; 286 287 /* Free TX skb ringbuffer. 288 * SKBs are freed by ravb_tx_free() call above. 289 */ 290 kfree(priv->tx_skb[q]); 291 priv->tx_skb[q] = NULL; 292 } 293 294 static int 295 ravb_alloc_rx_buffer(struct net_device *ndev, int q, u32 entry, gfp_t gfp_mask, 296 struct ravb_rx_desc *rx_desc) 297 { 298 struct ravb_private *priv = netdev_priv(ndev); 299 const struct ravb_hw_info *info = priv->info; 300 struct ravb_rx_buffer *rx_buff; 301 dma_addr_t dma_addr; 302 unsigned int size; 303 304 rx_buff = &priv->rx_buffers[q][entry]; 305 size = info->rx_buffer_size; 306 rx_buff->page = page_pool_alloc(priv->rx_pool[q], &rx_buff->offset, 307 &size, gfp_mask); 308 if (unlikely(!rx_buff->page)) { 309 /* We just set the data size to 0 for a failed mapping which 310 * should prevent DMA from happening... 311 */ 312 rx_desc->ds_cc = cpu_to_le16(0); 313 return -ENOMEM; 314 } 315 316 dma_addr = page_pool_get_dma_addr(rx_buff->page) + rx_buff->offset; 317 dma_sync_single_for_device(ndev->dev.parent, dma_addr, 318 info->rx_buffer_size, DMA_FROM_DEVICE); 319 rx_desc->dptr = cpu_to_le32(dma_addr); 320 321 /* The end of the RX buffer is used to store skb shared data, so we need 322 * to ensure that the hardware leaves enough space for this. 323 */ 324 rx_desc->ds_cc = cpu_to_le16(info->rx_buffer_size - 325 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) - 326 ETH_FCS_LEN + sizeof(__sum16)); 327 return 0; 328 } 329 330 static u32 331 ravb_rx_ring_refill(struct net_device *ndev, int q, u32 count, gfp_t gfp_mask) 332 { 333 struct ravb_private *priv = netdev_priv(ndev); 334 struct ravb_rx_desc *rx_desc; 335 u32 i, entry; 336 337 for (i = 0; i < count; i++) { 338 entry = (priv->dirty_rx[q] + i) % priv->num_rx_ring[q]; 339 rx_desc = ravb_rx_get_desc(priv, q, entry); 340 341 if (!priv->rx_buffers[q][entry].page) { 342 if (unlikely(ravb_alloc_rx_buffer(ndev, q, entry, 343 gfp_mask, rx_desc))) 344 break; 345 } 346 /* Descriptor type must be set after all the above writes */ 347 dma_wmb(); 348 rx_desc->die_dt = DT_FEMPTY; 349 } 350 351 return i; 352 } 353 354 /* Format skb and descriptor buffer for Ethernet AVB */ 355 static void ravb_ring_format(struct net_device *ndev, int q) 356 { 357 struct ravb_private *priv = netdev_priv(ndev); 358 unsigned int num_tx_desc = priv->num_tx_desc; 359 struct ravb_rx_desc *rx_desc; 360 struct ravb_tx_desc *tx_desc; 361 struct ravb_desc *desc; 362 unsigned int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 363 num_tx_desc; 364 unsigned int i; 365 366 priv->cur_rx[q] = 0; 367 priv->cur_tx[q] = 0; 368 priv->dirty_rx[q] = 0; 369 priv->dirty_tx[q] = 0; 370 371 /* Regular RX descriptors have already been initialized by 372 * ravb_rx_ring_refill(), we just need to initialize the final link 373 * descriptor. 374 */ 375 rx_desc = ravb_rx_get_desc(priv, q, priv->num_rx_ring[q]); 376 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 377 rx_desc->die_dt = DT_LINKFIX; /* type */ 378 379 memset(priv->tx_ring[q], 0, tx_ring_size); 380 /* Build TX ring buffer */ 381 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 382 i++, tx_desc++) { 383 tx_desc->die_dt = DT_EEMPTY; 384 if (num_tx_desc > 1) { 385 tx_desc++; 386 tx_desc->die_dt = DT_EEMPTY; 387 } 388 } 389 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 390 tx_desc->die_dt = DT_LINKFIX; /* type */ 391 392 /* RX descriptor base address for best effort */ 393 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 394 desc->die_dt = DT_LINKFIX; /* type */ 395 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 396 397 /* TX descriptor base address for best effort */ 398 desc = &priv->desc_bat[q]; 399 desc->die_dt = DT_LINKFIX; /* type */ 400 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 401 } 402 403 static void *ravb_alloc_rx_desc(struct net_device *ndev, int q) 404 { 405 struct ravb_private *priv = netdev_priv(ndev); 406 unsigned int ring_size; 407 408 ring_size = priv->info->rx_desc_size * (priv->num_rx_ring[q] + 1); 409 410 priv->rx_ring[q].raw = dma_alloc_coherent(ndev->dev.parent, ring_size, 411 &priv->rx_desc_dma[q], 412 GFP_KERNEL); 413 414 return priv->rx_ring[q].raw; 415 } 416 417 /* Init skb and descriptor buffer for Ethernet AVB */ 418 static int ravb_ring_init(struct net_device *ndev, int q) 419 { 420 struct ravb_private *priv = netdev_priv(ndev); 421 unsigned int num_tx_desc = priv->num_tx_desc; 422 struct page_pool_params params = { 423 .order = 0, 424 .flags = PP_FLAG_DMA_MAP, 425 .pool_size = priv->num_rx_ring[q], 426 .nid = NUMA_NO_NODE, 427 .dev = ndev->dev.parent, 428 .dma_dir = DMA_FROM_DEVICE, 429 }; 430 unsigned int ring_size; 431 u32 num_filled; 432 433 /* Allocate RX page pool and buffers */ 434 priv->rx_pool[q] = page_pool_create(¶ms); 435 if (IS_ERR(priv->rx_pool[q])) 436 goto error; 437 438 /* Allocate RX buffers */ 439 priv->rx_buffers[q] = kcalloc(priv->num_rx_ring[q], 440 sizeof(*priv->rx_buffers[q]), GFP_KERNEL); 441 if (!priv->rx_buffers[q]) 442 goto error; 443 444 /* Allocate TX skb rings */ 445 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 446 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 447 if (!priv->tx_skb[q]) 448 goto error; 449 450 /* Allocate all RX descriptors. */ 451 if (!ravb_alloc_rx_desc(ndev, q)) 452 goto error; 453 454 /* Populate RX ring buffer. */ 455 priv->dirty_rx[q] = 0; 456 ring_size = priv->info->rx_desc_size * priv->num_rx_ring[q]; 457 memset(priv->rx_ring[q].raw, 0, ring_size); 458 num_filled = ravb_rx_ring_refill(ndev, q, priv->num_rx_ring[q], 459 GFP_KERNEL); 460 if (num_filled != priv->num_rx_ring[q]) 461 goto error; 462 463 if (num_tx_desc > 1) { 464 /* Allocate rings for the aligned buffers */ 465 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 466 DPTR_ALIGN - 1, GFP_KERNEL); 467 if (!priv->tx_align[q]) 468 goto error; 469 } 470 471 /* Allocate all TX descriptors. */ 472 ring_size = sizeof(struct ravb_tx_desc) * 473 (priv->num_tx_ring[q] * num_tx_desc + 1); 474 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 475 &priv->tx_desc_dma[q], 476 GFP_KERNEL); 477 if (!priv->tx_ring[q]) 478 goto error; 479 480 return 0; 481 482 error: 483 ravb_ring_free(ndev, q); 484 485 return -ENOMEM; 486 } 487 488 static void ravb_csum_init_gbeth(struct net_device *ndev) 489 { 490 bool tx_enable = ndev->features & NETIF_F_HW_CSUM; 491 bool rx_enable = ndev->features & NETIF_F_RXCSUM; 492 493 if (!(tx_enable || rx_enable)) 494 goto done; 495 496 ravb_write(ndev, 0, CSR0); 497 if (ravb_wait(ndev, CSR0, CSR0_TPE | CSR0_RPE, 0)) { 498 netdev_err(ndev, "Timeout enabling hardware checksum\n"); 499 500 if (tx_enable) 501 ndev->features &= ~NETIF_F_HW_CSUM; 502 503 if (rx_enable) 504 ndev->features &= ~NETIF_F_RXCSUM; 505 } else { 506 if (tx_enable) 507 ravb_write(ndev, CSR1_TIP4 | CSR1_TTCP4 | CSR1_TUDP4, CSR1); 508 509 if (rx_enable) 510 ravb_write(ndev, CSR2_RIP4 | CSR2_RTCP4 | CSR2_RUDP4 | CSR2_RICMP4, 511 CSR2); 512 } 513 514 done: 515 ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0); 516 } 517 518 static void ravb_emac_init_gbeth(struct net_device *ndev) 519 { 520 struct ravb_private *priv = netdev_priv(ndev); 521 522 if (priv->phy_interface == PHY_INTERFACE_MODE_MII) { 523 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35); 524 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0); 525 } else { 526 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_RGMII, CXR35); 527 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 528 CXR31_SEL_LINK0); 529 } 530 531 /* Receive frame limit set register */ 532 ravb_write(ndev, priv->info->rx_max_frame_size + ETH_FCS_LEN, RFLR); 533 534 /* EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through */ 535 ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) | 536 ECMR_TE | ECMR_RE | ECMR_RCPT | 537 ECMR_TXF | ECMR_RXF, ECMR); 538 539 ravb_set_rate_gbeth(ndev); 540 541 /* Set MAC address */ 542 ravb_write(ndev, 543 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 544 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 545 ravb_write(ndev, (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 546 547 /* E-MAC status register clear */ 548 ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR); 549 550 ravb_csum_init_gbeth(ndev); 551 552 /* E-MAC interrupt enable register */ 553 ravb_write(ndev, ECSIPR_ICDIP, ECSIPR); 554 } 555 556 static void ravb_emac_init_rcar(struct net_device *ndev) 557 { 558 struct ravb_private *priv = netdev_priv(ndev); 559 560 /* Set receive frame length 561 * 562 * The length set here describes the frame from the destination address 563 * up to and including the CRC data. However only the frame data, 564 * excluding the CRC, are transferred to memory. To allow for the 565 * largest frames add the CRC length to the maximum Rx descriptor size. 566 */ 567 ravb_write(ndev, priv->info->rx_max_frame_size + ETH_FCS_LEN, RFLR); 568 569 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 570 ravb_write(ndev, ECMR_ZPF | ECMR_DM | 571 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 572 ECMR_TE | ECMR_RE, ECMR); 573 574 ravb_set_rate_rcar(ndev); 575 576 /* Set MAC address */ 577 ravb_write(ndev, 578 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 579 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 580 ravb_write(ndev, 581 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 582 583 /* E-MAC status register clear */ 584 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 585 586 /* E-MAC interrupt enable register */ 587 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 588 } 589 590 static void ravb_emac_init_rcar_gen4(struct net_device *ndev) 591 { 592 struct ravb_private *priv = netdev_priv(ndev); 593 bool mii = priv->phy_interface == PHY_INTERFACE_MODE_MII; 594 595 ravb_modify(ndev, APSR, APSR_MIISELECT, mii ? APSR_MIISELECT : 0); 596 597 ravb_emac_init_rcar(ndev); 598 } 599 600 /* E-MAC init function */ 601 static void ravb_emac_init(struct net_device *ndev) 602 { 603 struct ravb_private *priv = netdev_priv(ndev); 604 const struct ravb_hw_info *info = priv->info; 605 606 info->emac_init(ndev); 607 } 608 609 static int ravb_dmac_init_gbeth(struct net_device *ndev) 610 { 611 struct ravb_private *priv = netdev_priv(ndev); 612 int error; 613 614 error = ravb_ring_init(ndev, RAVB_BE); 615 if (error) 616 return error; 617 618 /* Descriptor format */ 619 ravb_ring_format(ndev, RAVB_BE); 620 621 /* Set DMAC RX */ 622 ravb_write(ndev, 0x60000000, RCR); 623 624 /* Set Max Frame Length (RTC) */ 625 ravb_write(ndev, 0x7ffc0000 | priv->info->rx_max_frame_size, RTC); 626 627 /* Set FIFO size */ 628 ravb_write(ndev, 0x00222200, TGC); 629 630 ravb_write(ndev, 0, TCCR); 631 632 /* Frame receive */ 633 ravb_write(ndev, RIC0_FRE0, RIC0); 634 /* Disable FIFO full warning */ 635 ravb_write(ndev, 0x0, RIC1); 636 /* Receive FIFO full error, descriptor empty */ 637 ravb_write(ndev, RIC2_QFE0 | RIC2_RFFE, RIC2); 638 639 ravb_write(ndev, TIC_FTE0, TIC); 640 641 return 0; 642 } 643 644 static int ravb_dmac_init_rcar(struct net_device *ndev) 645 { 646 struct ravb_private *priv = netdev_priv(ndev); 647 const struct ravb_hw_info *info = priv->info; 648 int error; 649 650 error = ravb_ring_init(ndev, RAVB_BE); 651 if (error) 652 return error; 653 error = ravb_ring_init(ndev, RAVB_NC); 654 if (error) { 655 ravb_ring_free(ndev, RAVB_BE); 656 return error; 657 } 658 659 /* Descriptor format */ 660 ravb_ring_format(ndev, RAVB_BE); 661 ravb_ring_format(ndev, RAVB_NC); 662 663 /* Set AVB RX */ 664 ravb_write(ndev, 665 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 666 667 /* Set FIFO size */ 668 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC); 669 670 /* Timestamp enable */ 671 ravb_write(ndev, TCCR_TFEN, TCCR); 672 673 /* Interrupt init: */ 674 if (info->multi_irqs) { 675 /* Clear DIL.DPLx */ 676 ravb_write(ndev, 0, DIL); 677 /* Set queue specific interrupt */ 678 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 679 } 680 /* Frame receive */ 681 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 682 /* Disable FIFO full warning */ 683 ravb_write(ndev, 0, RIC1); 684 /* Receive FIFO full error, descriptor empty */ 685 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 686 /* Frame transmitted, timestamp FIFO updated */ 687 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 688 689 return 0; 690 } 691 692 /* Device init function for Ethernet AVB */ 693 static int ravb_dmac_init(struct net_device *ndev) 694 { 695 struct ravb_private *priv = netdev_priv(ndev); 696 const struct ravb_hw_info *info = priv->info; 697 int error; 698 699 /* Set CONFIG mode */ 700 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 701 if (error) 702 return error; 703 704 error = info->dmac_init(ndev); 705 if (error) 706 return error; 707 708 /* Setting the control will start the AVB-DMAC process. */ 709 return ravb_set_opmode(ndev, CCC_OPC_OPERATION); 710 } 711 712 static void ravb_get_tx_tstamp(struct net_device *ndev) 713 { 714 struct ravb_private *priv = netdev_priv(ndev); 715 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 716 struct skb_shared_hwtstamps shhwtstamps; 717 struct sk_buff *skb; 718 struct timespec64 ts; 719 u16 tag, tfa_tag; 720 int count; 721 u32 tfa2; 722 723 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 724 while (count--) { 725 tfa2 = ravb_read(ndev, TFA2); 726 tfa_tag = (tfa2 & TFA2_TST) >> 16; 727 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 728 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 729 ravb_read(ndev, TFA1); 730 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 731 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 732 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 733 list) { 734 skb = ts_skb->skb; 735 tag = ts_skb->tag; 736 list_del(&ts_skb->list); 737 kfree(ts_skb); 738 if (tag == tfa_tag) { 739 skb_tstamp_tx(skb, &shhwtstamps); 740 dev_consume_skb_any(skb); 741 break; 742 } else { 743 dev_kfree_skb_any(skb); 744 } 745 } 746 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 747 } 748 } 749 750 static void ravb_rx_csum_gbeth(struct sk_buff *skb) 751 { 752 struct skb_shared_info *shinfo = skb_shinfo(skb); 753 __wsum csum_ip_hdr, csum_proto; 754 skb_frag_t *last_frag; 755 u8 *hw_csum; 756 757 /* The hardware checksum status is contained in sizeof(__sum16) * 2 = 4 758 * bytes appended to packet data. First 2 bytes is ip header checksum 759 * and last 2 bytes is protocol checksum. 760 */ 761 if (unlikely(skb->len < sizeof(__sum16) * 2)) 762 return; 763 764 if (skb_is_nonlinear(skb)) { 765 last_frag = &shinfo->frags[shinfo->nr_frags - 1]; 766 hw_csum = skb_frag_address(last_frag) + 767 skb_frag_size(last_frag); 768 } else { 769 hw_csum = skb_tail_pointer(skb); 770 } 771 772 hw_csum -= sizeof(__sum16); 773 csum_proto = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 774 775 hw_csum -= sizeof(__sum16); 776 csum_ip_hdr = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 777 778 if (skb_is_nonlinear(skb)) 779 skb_frag_size_sub(last_frag, 2 * sizeof(__sum16)); 780 else 781 skb_trim(skb, skb->len - 2 * sizeof(__sum16)); 782 783 /* TODO: IPV6 Rx checksum */ 784 if (skb->protocol == htons(ETH_P_IP) && !csum_ip_hdr && !csum_proto) 785 skb->ip_summed = CHECKSUM_UNNECESSARY; 786 } 787 788 static void ravb_rx_csum(struct sk_buff *skb) 789 { 790 u8 *hw_csum; 791 792 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes 793 * appended to packet data 794 */ 795 if (unlikely(skb->len < sizeof(__sum16))) 796 return; 797 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); 798 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 799 skb->ip_summed = CHECKSUM_COMPLETE; 800 skb_trim(skb, skb->len - sizeof(__sum16)); 801 } 802 803 /* Packet receive function for Gigabit Ethernet */ 804 static int ravb_rx_gbeth(struct net_device *ndev, int budget, int q) 805 { 806 struct ravb_private *priv = netdev_priv(ndev); 807 const struct ravb_hw_info *info = priv->info; 808 struct net_device_stats *stats; 809 struct ravb_rx_desc *desc; 810 struct sk_buff *skb; 811 int rx_packets = 0; 812 u8 desc_status; 813 u16 desc_len; 814 u8 die_dt; 815 int entry; 816 int limit; 817 int i; 818 819 limit = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q]; 820 stats = &priv->stats[q]; 821 822 for (i = 0; i < limit; i++, priv->cur_rx[q]++) { 823 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 824 desc = &priv->rx_ring[q].desc[entry]; 825 if (rx_packets == budget || desc->die_dt == DT_FEMPTY) 826 break; 827 828 /* Descriptor type must be checked before all other reads */ 829 dma_rmb(); 830 desc_status = desc->msc; 831 desc_len = le16_to_cpu(desc->ds_cc) & RX_DS; 832 833 /* We use 0-byte descriptors to mark the DMA mapping errors */ 834 if (!desc_len) 835 continue; 836 837 if (desc_status & MSC_MC) 838 stats->multicast++; 839 840 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | MSC_CEEF)) { 841 stats->rx_errors++; 842 if (desc_status & MSC_CRC) 843 stats->rx_crc_errors++; 844 if (desc_status & MSC_RFE) 845 stats->rx_frame_errors++; 846 if (desc_status & (MSC_RTLF | MSC_RTSF)) 847 stats->rx_length_errors++; 848 if (desc_status & MSC_CEEF) 849 stats->rx_missed_errors++; 850 } else { 851 struct ravb_rx_buffer *rx_buff; 852 void *rx_addr; 853 854 rx_buff = &priv->rx_buffers[q][entry]; 855 rx_addr = page_address(rx_buff->page) + rx_buff->offset; 856 die_dt = desc->die_dt & 0xF0; 857 dma_sync_single_for_cpu(ndev->dev.parent, 858 le32_to_cpu(desc->dptr), 859 desc_len, DMA_FROM_DEVICE); 860 861 switch (die_dt) { 862 case DT_FSINGLE: 863 case DT_FSTART: 864 /* Start of packet: Set initial data length. */ 865 skb = napi_build_skb(rx_addr, 866 info->rx_buffer_size); 867 if (unlikely(!skb)) { 868 stats->rx_errors++; 869 page_pool_put_page(priv->rx_pool[q], 870 rx_buff->page, 0, 871 true); 872 goto refill; 873 } 874 skb_mark_for_recycle(skb); 875 skb_put(skb, desc_len); 876 877 /* Save this skb if the packet spans multiple 878 * descriptors. 879 */ 880 if (die_dt == DT_FSTART) 881 priv->rx_1st_skb = skb; 882 break; 883 884 case DT_FMID: 885 case DT_FEND: 886 /* Continuing a packet: Add this buffer as an RX 887 * frag. 888 */ 889 890 /* rx_1st_skb will be NULL if napi_build_skb() 891 * failed for the first descriptor of a 892 * multi-descriptor packet. 893 */ 894 if (unlikely(!priv->rx_1st_skb)) { 895 stats->rx_errors++; 896 page_pool_put_page(priv->rx_pool[q], 897 rx_buff->page, 0, 898 true); 899 900 /* We may find a DT_FSINGLE or DT_FSTART 901 * descriptor in the queue which we can 902 * process, so don't give up yet. 903 */ 904 continue; 905 } 906 skb_add_rx_frag(priv->rx_1st_skb, 907 skb_shinfo(priv->rx_1st_skb)->nr_frags, 908 rx_buff->page, rx_buff->offset, 909 desc_len, info->rx_buffer_size); 910 911 /* Set skb to point at the whole packet so that 912 * we only need one code path for finishing a 913 * packet. 914 */ 915 skb = priv->rx_1st_skb; 916 } 917 918 switch (die_dt) { 919 case DT_FSINGLE: 920 case DT_FEND: 921 /* Finishing a packet: Determine protocol & 922 * checksum, hand off to NAPI and update our 923 * stats. 924 */ 925 skb->protocol = eth_type_trans(skb, ndev); 926 if (ndev->features & NETIF_F_RXCSUM) 927 ravb_rx_csum_gbeth(skb); 928 stats->rx_bytes += skb->len; 929 napi_gro_receive(&priv->napi[q], skb); 930 rx_packets++; 931 932 /* Clear rx_1st_skb so that it will only be 933 * non-NULL when valid. 934 */ 935 priv->rx_1st_skb = NULL; 936 } 937 938 /* Mark this RX buffer as consumed. */ 939 rx_buff->page = NULL; 940 } 941 } 942 943 refill: 944 /* Refill the RX ring buffers. */ 945 priv->dirty_rx[q] += ravb_rx_ring_refill(ndev, q, 946 priv->cur_rx[q] - priv->dirty_rx[q], 947 GFP_ATOMIC); 948 949 stats->rx_packets += rx_packets; 950 return rx_packets; 951 } 952 953 /* Packet receive function for Ethernet AVB */ 954 static int ravb_rx_rcar(struct net_device *ndev, int budget, int q) 955 { 956 struct ravb_private *priv = netdev_priv(ndev); 957 const struct ravb_hw_info *info = priv->info; 958 struct net_device_stats *stats = &priv->stats[q]; 959 struct ravb_ex_rx_desc *desc; 960 unsigned int limit, i; 961 struct sk_buff *skb; 962 struct timespec64 ts; 963 int rx_packets = 0; 964 u8 desc_status; 965 u16 pkt_len; 966 int entry; 967 968 limit = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q]; 969 for (i = 0; i < limit; i++, priv->cur_rx[q]++) { 970 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 971 desc = &priv->rx_ring[q].ex_desc[entry]; 972 if (rx_packets == budget || desc->die_dt == DT_FEMPTY) 973 break; 974 975 /* Descriptor type must be checked before all other reads */ 976 dma_rmb(); 977 desc_status = desc->msc; 978 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 979 980 /* We use 0-byte descriptors to mark the DMA mapping errors */ 981 if (!pkt_len) 982 continue; 983 984 if (desc_status & MSC_MC) 985 stats->multicast++; 986 987 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 988 MSC_CEEF)) { 989 stats->rx_errors++; 990 if (desc_status & MSC_CRC) 991 stats->rx_crc_errors++; 992 if (desc_status & MSC_RFE) 993 stats->rx_frame_errors++; 994 if (desc_status & (MSC_RTLF | MSC_RTSF)) 995 stats->rx_length_errors++; 996 if (desc_status & MSC_CEEF) 997 stats->rx_missed_errors++; 998 } else { 999 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 1000 struct ravb_rx_buffer *rx_buff; 1001 void *rx_addr; 1002 1003 rx_buff = &priv->rx_buffers[q][entry]; 1004 rx_addr = page_address(rx_buff->page) + rx_buff->offset; 1005 dma_sync_single_for_cpu(ndev->dev.parent, 1006 le32_to_cpu(desc->dptr), 1007 pkt_len, DMA_FROM_DEVICE); 1008 1009 skb = napi_build_skb(rx_addr, info->rx_buffer_size); 1010 if (unlikely(!skb)) { 1011 stats->rx_errors++; 1012 page_pool_put_page(priv->rx_pool[q], 1013 rx_buff->page, 0, true); 1014 break; 1015 } 1016 skb_mark_for_recycle(skb); 1017 get_ts &= (q == RAVB_NC) ? 1018 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 1019 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 1020 if (get_ts) { 1021 struct skb_shared_hwtstamps *shhwtstamps; 1022 1023 shhwtstamps = skb_hwtstamps(skb); 1024 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 1025 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 1026 32) | le32_to_cpu(desc->ts_sl); 1027 ts.tv_nsec = le32_to_cpu(desc->ts_n); 1028 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 1029 } 1030 1031 skb_put(skb, pkt_len); 1032 skb->protocol = eth_type_trans(skb, ndev); 1033 if (ndev->features & NETIF_F_RXCSUM) 1034 ravb_rx_csum(skb); 1035 napi_gro_receive(&priv->napi[q], skb); 1036 rx_packets++; 1037 stats->rx_bytes += pkt_len; 1038 1039 /* Mark this RX buffer as consumed. */ 1040 rx_buff->page = NULL; 1041 } 1042 } 1043 1044 /* Refill the RX ring buffers. */ 1045 priv->dirty_rx[q] += ravb_rx_ring_refill(ndev, q, 1046 priv->cur_rx[q] - priv->dirty_rx[q], 1047 GFP_ATOMIC); 1048 1049 stats->rx_packets += rx_packets; 1050 return rx_packets; 1051 } 1052 1053 /* Packet receive function for Ethernet AVB */ 1054 static int ravb_rx(struct net_device *ndev, int budget, int q) 1055 { 1056 struct ravb_private *priv = netdev_priv(ndev); 1057 const struct ravb_hw_info *info = priv->info; 1058 1059 return info->receive(ndev, budget, q); 1060 } 1061 1062 static void ravb_rcv_snd_disable(struct net_device *ndev) 1063 { 1064 /* Disable TX and RX */ 1065 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 1066 } 1067 1068 static void ravb_rcv_snd_enable(struct net_device *ndev) 1069 { 1070 /* Enable TX and RX */ 1071 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 1072 } 1073 1074 /* function for waiting dma process finished */ 1075 static int ravb_stop_dma(struct net_device *ndev) 1076 { 1077 struct ravb_private *priv = netdev_priv(ndev); 1078 const struct ravb_hw_info *info = priv->info; 1079 int error; 1080 1081 /* Wait for stopping the hardware TX process */ 1082 error = ravb_wait(ndev, TCCR, info->tccr_mask, 0); 1083 1084 if (error) 1085 return error; 1086 1087 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 1088 0); 1089 if (error) 1090 return error; 1091 1092 /* Stop the E-MAC's RX/TX processes. */ 1093 ravb_rcv_snd_disable(ndev); 1094 1095 /* Wait for stopping the RX DMA process */ 1096 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 1097 if (error) 1098 return error; 1099 1100 /* Stop AVB-DMAC process */ 1101 return ravb_set_opmode(ndev, CCC_OPC_CONFIG); 1102 } 1103 1104 /* E-MAC interrupt handler */ 1105 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 1106 { 1107 struct ravb_private *priv = netdev_priv(ndev); 1108 u32 ecsr, psr; 1109 1110 ecsr = ravb_read(ndev, ECSR); 1111 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 1112 1113 if (ecsr & ECSR_MPD) 1114 pm_wakeup_event(&priv->pdev->dev, 0); 1115 if (ecsr & ECSR_ICD) 1116 ndev->stats.tx_carrier_errors++; 1117 if (ecsr & ECSR_LCHNG) { 1118 /* Link changed */ 1119 if (priv->no_avb_link) 1120 return; 1121 psr = ravb_read(ndev, PSR); 1122 if (priv->avb_link_active_low) 1123 psr ^= PSR_LMON; 1124 if (!(psr & PSR_LMON)) { 1125 /* DIsable RX and TX */ 1126 ravb_rcv_snd_disable(ndev); 1127 } else { 1128 /* Enable RX and TX */ 1129 ravb_rcv_snd_enable(ndev); 1130 } 1131 } 1132 } 1133 1134 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 1135 { 1136 struct net_device *ndev = dev_id; 1137 struct ravb_private *priv = netdev_priv(ndev); 1138 struct device *dev = &priv->pdev->dev; 1139 irqreturn_t result = IRQ_HANDLED; 1140 1141 pm_runtime_get_noresume(dev); 1142 1143 if (unlikely(!pm_runtime_active(dev))) { 1144 result = IRQ_NONE; 1145 goto out_rpm_put; 1146 } 1147 1148 spin_lock(&priv->lock); 1149 ravb_emac_interrupt_unlocked(ndev); 1150 spin_unlock(&priv->lock); 1151 1152 out_rpm_put: 1153 pm_runtime_put_noidle(dev); 1154 return result; 1155 } 1156 1157 /* Error interrupt handler */ 1158 static void ravb_error_interrupt(struct net_device *ndev) 1159 { 1160 struct ravb_private *priv = netdev_priv(ndev); 1161 u32 eis, ris2; 1162 1163 eis = ravb_read(ndev, EIS); 1164 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS); 1165 if (eis & EIS_QFS) { 1166 ris2 = ravb_read(ndev, RIS2); 1167 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_QFF1 | RIS2_RFFF | RIS2_RESERVED), 1168 RIS2); 1169 1170 /* Receive Descriptor Empty int */ 1171 if (ris2 & RIS2_QFF0) 1172 priv->stats[RAVB_BE].rx_over_errors++; 1173 1174 /* Receive Descriptor Empty int */ 1175 if (ris2 & RIS2_QFF1) 1176 priv->stats[RAVB_NC].rx_over_errors++; 1177 1178 /* Receive FIFO Overflow int */ 1179 if (ris2 & RIS2_RFFF) 1180 priv->rx_fifo_errors++; 1181 } 1182 } 1183 1184 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 1185 { 1186 struct ravb_private *priv = netdev_priv(ndev); 1187 const struct ravb_hw_info *info = priv->info; 1188 u32 ris0 = ravb_read(ndev, RIS0); 1189 u32 ric0 = ravb_read(ndev, RIC0); 1190 u32 tis = ravb_read(ndev, TIS); 1191 u32 tic = ravb_read(ndev, TIC); 1192 1193 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 1194 if (napi_schedule_prep(&priv->napi[q])) { 1195 /* Mask RX and TX interrupts */ 1196 if (!info->irq_en_dis) { 1197 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 1198 ravb_write(ndev, tic & ~BIT(q), TIC); 1199 } else { 1200 ravb_write(ndev, BIT(q), RID0); 1201 ravb_write(ndev, BIT(q), TID); 1202 } 1203 __napi_schedule(&priv->napi[q]); 1204 } else { 1205 netdev_warn(ndev, 1206 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 1207 ris0, ric0); 1208 netdev_warn(ndev, 1209 " tx status 0x%08x, tx mask 0x%08x.\n", 1210 tis, tic); 1211 } 1212 return true; 1213 } 1214 return false; 1215 } 1216 1217 static bool ravb_timestamp_interrupt(struct net_device *ndev) 1218 { 1219 u32 tis = ravb_read(ndev, TIS); 1220 1221 if (tis & TIS_TFUF) { 1222 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS); 1223 ravb_get_tx_tstamp(ndev); 1224 return true; 1225 } 1226 return false; 1227 } 1228 1229 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 1230 { 1231 struct net_device *ndev = dev_id; 1232 struct ravb_private *priv = netdev_priv(ndev); 1233 const struct ravb_hw_info *info = priv->info; 1234 struct device *dev = &priv->pdev->dev; 1235 irqreturn_t result = IRQ_NONE; 1236 u32 iss; 1237 1238 pm_runtime_get_noresume(dev); 1239 1240 if (unlikely(!pm_runtime_active(dev))) 1241 goto out_rpm_put; 1242 1243 spin_lock(&priv->lock); 1244 /* Get interrupt status */ 1245 iss = ravb_read(ndev, ISS); 1246 1247 /* Received and transmitted interrupts */ 1248 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 1249 int q; 1250 1251 /* Timestamp updated */ 1252 if (ravb_timestamp_interrupt(ndev)) 1253 result = IRQ_HANDLED; 1254 1255 /* Network control and best effort queue RX/TX */ 1256 if (info->nc_queues) { 1257 for (q = RAVB_NC; q >= RAVB_BE; q--) { 1258 if (ravb_queue_interrupt(ndev, q)) 1259 result = IRQ_HANDLED; 1260 } 1261 } else { 1262 if (ravb_queue_interrupt(ndev, RAVB_BE)) 1263 result = IRQ_HANDLED; 1264 } 1265 } 1266 1267 /* E-MAC status summary */ 1268 if (iss & ISS_MS) { 1269 ravb_emac_interrupt_unlocked(ndev); 1270 result = IRQ_HANDLED; 1271 } 1272 1273 /* Error status summary */ 1274 if (iss & ISS_ES) { 1275 ravb_error_interrupt(ndev); 1276 result = IRQ_HANDLED; 1277 } 1278 1279 /* gPTP interrupt status summary */ 1280 if (iss & ISS_CGIS) { 1281 ravb_ptp_interrupt(ndev); 1282 result = IRQ_HANDLED; 1283 } 1284 1285 spin_unlock(&priv->lock); 1286 1287 out_rpm_put: 1288 pm_runtime_put_noidle(dev); 1289 return result; 1290 } 1291 1292 /* Timestamp/Error/gPTP interrupt handler */ 1293 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 1294 { 1295 struct net_device *ndev = dev_id; 1296 struct ravb_private *priv = netdev_priv(ndev); 1297 struct device *dev = &priv->pdev->dev; 1298 irqreturn_t result = IRQ_NONE; 1299 u32 iss; 1300 1301 pm_runtime_get_noresume(dev); 1302 1303 if (unlikely(!pm_runtime_active(dev))) 1304 goto out_rpm_put; 1305 1306 spin_lock(&priv->lock); 1307 /* Get interrupt status */ 1308 iss = ravb_read(ndev, ISS); 1309 1310 /* Timestamp updated */ 1311 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 1312 result = IRQ_HANDLED; 1313 1314 /* Error status summary */ 1315 if (iss & ISS_ES) { 1316 ravb_error_interrupt(ndev); 1317 result = IRQ_HANDLED; 1318 } 1319 1320 /* gPTP interrupt status summary */ 1321 if (iss & ISS_CGIS) { 1322 ravb_ptp_interrupt(ndev); 1323 result = IRQ_HANDLED; 1324 } 1325 1326 spin_unlock(&priv->lock); 1327 1328 out_rpm_put: 1329 pm_runtime_put_noidle(dev); 1330 return result; 1331 } 1332 1333 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 1334 { 1335 struct net_device *ndev = dev_id; 1336 struct ravb_private *priv = netdev_priv(ndev); 1337 struct device *dev = &priv->pdev->dev; 1338 irqreturn_t result = IRQ_NONE; 1339 1340 pm_runtime_get_noresume(dev); 1341 1342 if (unlikely(!pm_runtime_active(dev))) 1343 goto out_rpm_put; 1344 1345 spin_lock(&priv->lock); 1346 1347 /* Network control/Best effort queue RX/TX */ 1348 if (ravb_queue_interrupt(ndev, q)) 1349 result = IRQ_HANDLED; 1350 1351 spin_unlock(&priv->lock); 1352 1353 out_rpm_put: 1354 pm_runtime_put_noidle(dev); 1355 return result; 1356 } 1357 1358 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 1359 { 1360 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 1361 } 1362 1363 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 1364 { 1365 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 1366 } 1367 1368 static int ravb_poll(struct napi_struct *napi, int budget) 1369 { 1370 struct net_device *ndev = napi->dev; 1371 struct ravb_private *priv = netdev_priv(ndev); 1372 const struct ravb_hw_info *info = priv->info; 1373 unsigned long flags; 1374 int q = napi - priv->napi; 1375 int mask = BIT(q); 1376 int work_done; 1377 1378 /* Processing RX Descriptor Ring */ 1379 /* Clear RX interrupt */ 1380 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0); 1381 work_done = ravb_rx(ndev, budget, q); 1382 1383 /* Processing TX Descriptor Ring */ 1384 spin_lock_irqsave(&priv->lock, flags); 1385 /* Clear TX interrupt */ 1386 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS); 1387 ravb_tx_free(ndev, q, true); 1388 netif_wake_subqueue(ndev, q); 1389 spin_unlock_irqrestore(&priv->lock, flags); 1390 1391 /* Receive error message handling */ 1392 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 1393 if (info->nc_queues) 1394 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 1395 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 1396 ndev->stats.rx_over_errors = priv->rx_over_errors; 1397 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 1398 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 1399 1400 if (work_done < budget && napi_complete_done(napi, work_done)) { 1401 /* Re-enable RX/TX interrupts */ 1402 spin_lock_irqsave(&priv->lock, flags); 1403 if (!info->irq_en_dis) { 1404 ravb_modify(ndev, RIC0, mask, mask); 1405 ravb_modify(ndev, TIC, mask, mask); 1406 } else { 1407 ravb_write(ndev, mask, RIE0); 1408 ravb_write(ndev, mask, TIE); 1409 } 1410 spin_unlock_irqrestore(&priv->lock, flags); 1411 } 1412 1413 return work_done; 1414 } 1415 1416 static void ravb_set_duplex_gbeth(struct net_device *ndev) 1417 { 1418 struct ravb_private *priv = netdev_priv(ndev); 1419 1420 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex > 0 ? ECMR_DM : 0); 1421 } 1422 1423 /* PHY state control function */ 1424 static void ravb_adjust_link(struct net_device *ndev) 1425 { 1426 struct ravb_private *priv = netdev_priv(ndev); 1427 const struct ravb_hw_info *info = priv->info; 1428 struct phy_device *phydev = ndev->phydev; 1429 bool new_state = false; 1430 unsigned long flags; 1431 1432 spin_lock_irqsave(&priv->lock, flags); 1433 1434 /* Disable TX and RX right over here, if E-MAC change is ignored */ 1435 if (priv->no_avb_link) 1436 ravb_rcv_snd_disable(ndev); 1437 1438 if (phydev->link) { 1439 if (info->half_duplex && phydev->duplex != priv->duplex) { 1440 new_state = true; 1441 priv->duplex = phydev->duplex; 1442 ravb_set_duplex_gbeth(ndev); 1443 } 1444 1445 if (phydev->speed != priv->speed) { 1446 new_state = true; 1447 priv->speed = phydev->speed; 1448 info->set_rate(ndev); 1449 } 1450 if (!priv->link) { 1451 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 1452 new_state = true; 1453 priv->link = phydev->link; 1454 } 1455 } else if (priv->link) { 1456 new_state = true; 1457 priv->link = 0; 1458 priv->speed = 0; 1459 if (info->half_duplex) 1460 priv->duplex = -1; 1461 } 1462 1463 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1464 if (priv->no_avb_link && phydev->link) 1465 ravb_rcv_snd_enable(ndev); 1466 1467 spin_unlock_irqrestore(&priv->lock, flags); 1468 1469 if (new_state && netif_msg_link(priv)) 1470 phy_print_status(phydev); 1471 } 1472 1473 /* PHY init function */ 1474 static int ravb_phy_init(struct net_device *ndev) 1475 { 1476 struct device_node *np = ndev->dev.parent->of_node; 1477 struct ravb_private *priv = netdev_priv(ndev); 1478 const struct ravb_hw_info *info = priv->info; 1479 struct phy_device *phydev; 1480 struct device_node *pn; 1481 phy_interface_t iface; 1482 int err; 1483 1484 priv->link = 0; 1485 priv->speed = 0; 1486 priv->duplex = -1; 1487 1488 /* Try connecting to PHY */ 1489 pn = of_parse_phandle(np, "phy-handle", 0); 1490 if (!pn) { 1491 /* In the case of a fixed PHY, the DT node associated 1492 * to the PHY is the Ethernet MAC DT node. 1493 */ 1494 if (of_phy_is_fixed_link(np)) { 1495 err = of_phy_register_fixed_link(np); 1496 if (err) 1497 return err; 1498 } 1499 pn = of_node_get(np); 1500 } 1501 1502 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII 1503 : priv->phy_interface; 1504 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface); 1505 of_node_put(pn); 1506 if (!phydev) { 1507 netdev_err(ndev, "failed to connect PHY\n"); 1508 err = -ENOENT; 1509 goto err_deregister_fixed_link; 1510 } 1511 1512 if (!info->half_duplex) { 1513 /* 10BASE, Pause and Asym Pause is not supported */ 1514 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1515 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1516 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT); 1517 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 1518 1519 /* Half Duplex is not supported */ 1520 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1521 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1522 } 1523 1524 phy_attached_info(phydev); 1525 1526 return 0; 1527 1528 err_deregister_fixed_link: 1529 if (of_phy_is_fixed_link(np)) 1530 of_phy_deregister_fixed_link(np); 1531 1532 return err; 1533 } 1534 1535 /* PHY control start function */ 1536 static int ravb_phy_start(struct net_device *ndev) 1537 { 1538 int error; 1539 1540 error = ravb_phy_init(ndev); 1541 if (error) 1542 return error; 1543 1544 phy_start(ndev->phydev); 1545 1546 return 0; 1547 } 1548 1549 static u32 ravb_get_msglevel(struct net_device *ndev) 1550 { 1551 struct ravb_private *priv = netdev_priv(ndev); 1552 1553 return priv->msg_enable; 1554 } 1555 1556 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1557 { 1558 struct ravb_private *priv = netdev_priv(ndev); 1559 1560 priv->msg_enable = value; 1561 } 1562 1563 static const char ravb_gstrings_stats_gbeth[][ETH_GSTRING_LEN] = { 1564 "rx_queue_0_current", 1565 "tx_queue_0_current", 1566 "rx_queue_0_dirty", 1567 "tx_queue_0_dirty", 1568 "rx_queue_0_packets", 1569 "tx_queue_0_packets", 1570 "rx_queue_0_bytes", 1571 "tx_queue_0_bytes", 1572 "rx_queue_0_mcast_packets", 1573 "rx_queue_0_errors", 1574 "rx_queue_0_crc_errors", 1575 "rx_queue_0_frame_errors", 1576 "rx_queue_0_length_errors", 1577 "rx_queue_0_csum_offload_errors", 1578 "rx_queue_0_over_errors", 1579 }; 1580 1581 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1582 "rx_queue_0_current", 1583 "tx_queue_0_current", 1584 "rx_queue_0_dirty", 1585 "tx_queue_0_dirty", 1586 "rx_queue_0_packets", 1587 "tx_queue_0_packets", 1588 "rx_queue_0_bytes", 1589 "tx_queue_0_bytes", 1590 "rx_queue_0_mcast_packets", 1591 "rx_queue_0_errors", 1592 "rx_queue_0_crc_errors", 1593 "rx_queue_0_frame_errors", 1594 "rx_queue_0_length_errors", 1595 "rx_queue_0_missed_errors", 1596 "rx_queue_0_over_errors", 1597 1598 "rx_queue_1_current", 1599 "tx_queue_1_current", 1600 "rx_queue_1_dirty", 1601 "tx_queue_1_dirty", 1602 "rx_queue_1_packets", 1603 "tx_queue_1_packets", 1604 "rx_queue_1_bytes", 1605 "tx_queue_1_bytes", 1606 "rx_queue_1_mcast_packets", 1607 "rx_queue_1_errors", 1608 "rx_queue_1_crc_errors", 1609 "rx_queue_1_frame_errors", 1610 "rx_queue_1_length_errors", 1611 "rx_queue_1_missed_errors", 1612 "rx_queue_1_over_errors", 1613 }; 1614 1615 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1616 { 1617 struct ravb_private *priv = netdev_priv(netdev); 1618 const struct ravb_hw_info *info = priv->info; 1619 1620 switch (sset) { 1621 case ETH_SS_STATS: 1622 return info->stats_len; 1623 default: 1624 return -EOPNOTSUPP; 1625 } 1626 } 1627 1628 static void ravb_get_ethtool_stats(struct net_device *ndev, 1629 struct ethtool_stats *estats, u64 *data) 1630 { 1631 struct ravb_private *priv = netdev_priv(ndev); 1632 const struct ravb_hw_info *info = priv->info; 1633 int num_rx_q; 1634 int i = 0; 1635 int q; 1636 1637 num_rx_q = info->nc_queues ? NUM_RX_QUEUE : 1; 1638 /* Device-specific stats */ 1639 for (q = RAVB_BE; q < num_rx_q; q++) { 1640 struct net_device_stats *stats = &priv->stats[q]; 1641 1642 data[i++] = priv->cur_rx[q]; 1643 data[i++] = priv->cur_tx[q]; 1644 data[i++] = priv->dirty_rx[q]; 1645 data[i++] = priv->dirty_tx[q]; 1646 data[i++] = stats->rx_packets; 1647 data[i++] = stats->tx_packets; 1648 data[i++] = stats->rx_bytes; 1649 data[i++] = stats->tx_bytes; 1650 data[i++] = stats->multicast; 1651 data[i++] = stats->rx_errors; 1652 data[i++] = stats->rx_crc_errors; 1653 data[i++] = stats->rx_frame_errors; 1654 data[i++] = stats->rx_length_errors; 1655 data[i++] = stats->rx_missed_errors; 1656 data[i++] = stats->rx_over_errors; 1657 } 1658 } 1659 1660 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1661 { 1662 struct ravb_private *priv = netdev_priv(ndev); 1663 const struct ravb_hw_info *info = priv->info; 1664 1665 switch (stringset) { 1666 case ETH_SS_STATS: 1667 memcpy(data, info->gstrings_stats, info->gstrings_size); 1668 break; 1669 } 1670 } 1671 1672 static void ravb_get_ringparam(struct net_device *ndev, 1673 struct ethtool_ringparam *ring, 1674 struct kernel_ethtool_ringparam *kernel_ring, 1675 struct netlink_ext_ack *extack) 1676 { 1677 struct ravb_private *priv = netdev_priv(ndev); 1678 1679 ring->rx_max_pending = BE_RX_RING_MAX; 1680 ring->tx_max_pending = BE_TX_RING_MAX; 1681 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1682 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1683 } 1684 1685 static int ravb_set_ringparam(struct net_device *ndev, 1686 struct ethtool_ringparam *ring, 1687 struct kernel_ethtool_ringparam *kernel_ring, 1688 struct netlink_ext_ack *extack) 1689 { 1690 struct ravb_private *priv = netdev_priv(ndev); 1691 const struct ravb_hw_info *info = priv->info; 1692 int error; 1693 1694 if (ring->tx_pending > BE_TX_RING_MAX || 1695 ring->rx_pending > BE_RX_RING_MAX || 1696 ring->tx_pending < BE_TX_RING_MIN || 1697 ring->rx_pending < BE_RX_RING_MIN) 1698 return -EINVAL; 1699 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1700 return -EINVAL; 1701 1702 if (netif_running(ndev)) { 1703 netif_device_detach(ndev); 1704 /* Stop PTP Clock driver */ 1705 if (info->gptp) 1706 ravb_ptp_stop(ndev); 1707 /* Wait for DMA stopping */ 1708 error = ravb_stop_dma(ndev); 1709 if (error) { 1710 netdev_err(ndev, 1711 "cannot set ringparam! Any AVB processes are still running?\n"); 1712 return error; 1713 } 1714 synchronize_irq(ndev->irq); 1715 1716 /* Free all the skb's in the RX queue and the DMA buffers. */ 1717 ravb_ring_free(ndev, RAVB_BE); 1718 if (info->nc_queues) 1719 ravb_ring_free(ndev, RAVB_NC); 1720 } 1721 1722 /* Set new parameters */ 1723 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1724 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1725 1726 if (netif_running(ndev)) { 1727 error = ravb_dmac_init(ndev); 1728 if (error) { 1729 netdev_err(ndev, 1730 "%s: ravb_dmac_init() failed, error %d\n", 1731 __func__, error); 1732 return error; 1733 } 1734 1735 ravb_emac_init(ndev); 1736 1737 /* Initialise PTP Clock driver */ 1738 if (info->gptp) 1739 ravb_ptp_init(ndev, priv->pdev); 1740 1741 netif_device_attach(ndev); 1742 } 1743 1744 return 0; 1745 } 1746 1747 static int ravb_get_ts_info(struct net_device *ndev, 1748 struct kernel_ethtool_ts_info *info) 1749 { 1750 struct ravb_private *priv = netdev_priv(ndev); 1751 const struct ravb_hw_info *hw_info = priv->info; 1752 1753 info->so_timestamping = 1754 SOF_TIMESTAMPING_TX_SOFTWARE | 1755 SOF_TIMESTAMPING_TX_HARDWARE | 1756 SOF_TIMESTAMPING_RX_HARDWARE | 1757 SOF_TIMESTAMPING_RAW_HARDWARE; 1758 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1759 info->rx_filters = 1760 (1 << HWTSTAMP_FILTER_NONE) | 1761 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1762 (1 << HWTSTAMP_FILTER_ALL); 1763 if (hw_info->gptp || hw_info->ccc_gac) 1764 info->phc_index = ptp_clock_index(priv->ptp.clock); 1765 else 1766 info->phc_index = 0; 1767 1768 return 0; 1769 } 1770 1771 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1772 { 1773 struct ravb_private *priv = netdev_priv(ndev); 1774 1775 wol->supported = WAKE_MAGIC; 1776 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1777 } 1778 1779 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1780 { 1781 struct ravb_private *priv = netdev_priv(ndev); 1782 const struct ravb_hw_info *info = priv->info; 1783 1784 if (!info->magic_pkt || (wol->wolopts & ~WAKE_MAGIC)) 1785 return -EOPNOTSUPP; 1786 1787 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1788 1789 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1790 1791 return 0; 1792 } 1793 1794 static const struct ethtool_ops ravb_ethtool_ops = { 1795 .nway_reset = phy_ethtool_nway_reset, 1796 .get_msglevel = ravb_get_msglevel, 1797 .set_msglevel = ravb_set_msglevel, 1798 .get_link = ethtool_op_get_link, 1799 .get_strings = ravb_get_strings, 1800 .get_ethtool_stats = ravb_get_ethtool_stats, 1801 .get_sset_count = ravb_get_sset_count, 1802 .get_ringparam = ravb_get_ringparam, 1803 .set_ringparam = ravb_set_ringparam, 1804 .get_ts_info = ravb_get_ts_info, 1805 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1806 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1807 .get_wol = ravb_get_wol, 1808 .set_wol = ravb_set_wol, 1809 }; 1810 1811 static int ravb_set_config_mode(struct net_device *ndev) 1812 { 1813 struct ravb_private *priv = netdev_priv(ndev); 1814 const struct ravb_hw_info *info = priv->info; 1815 int error; 1816 1817 if (info->gptp) { 1818 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 1819 if (error) 1820 return error; 1821 /* Set CSEL value */ 1822 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 1823 } else if (info->ccc_gac) { 1824 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG | CCC_GAC | CCC_CSEL_HPB); 1825 } else { 1826 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 1827 } 1828 1829 return error; 1830 } 1831 1832 static void ravb_set_gti(struct net_device *ndev) 1833 { 1834 struct ravb_private *priv = netdev_priv(ndev); 1835 const struct ravb_hw_info *info = priv->info; 1836 1837 if (!(info->gptp || info->ccc_gac)) 1838 return; 1839 1840 ravb_write(ndev, priv->gti_tiv, GTI); 1841 1842 /* Request GTI loading */ 1843 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 1844 } 1845 1846 static int ravb_compute_gti(struct net_device *ndev) 1847 { 1848 struct ravb_private *priv = netdev_priv(ndev); 1849 const struct ravb_hw_info *info = priv->info; 1850 struct device *dev = ndev->dev.parent; 1851 unsigned long rate; 1852 u64 inc; 1853 1854 if (!(info->gptp || info->ccc_gac)) 1855 return 0; 1856 1857 if (info->gptp_ref_clk) 1858 rate = clk_get_rate(priv->gptp_clk); 1859 else 1860 rate = clk_get_rate(priv->clk); 1861 if (!rate) 1862 return -EINVAL; 1863 1864 inc = div64_ul(1000000000ULL << 20, rate); 1865 1866 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 1867 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 1868 inc, GTI_TIV_MIN, GTI_TIV_MAX); 1869 return -EINVAL; 1870 } 1871 priv->gti_tiv = inc; 1872 1873 return 0; 1874 } 1875 1876 /* Set tx and rx clock internal delay modes */ 1877 static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev) 1878 { 1879 struct ravb_private *priv = netdev_priv(ndev); 1880 bool explicit_delay = false; 1881 u32 delay; 1882 1883 if (!priv->info->internal_delay) 1884 return; 1885 1886 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) { 1887 /* Valid values are 0 and 1800, according to DT bindings */ 1888 priv->rxcidm = !!delay; 1889 explicit_delay = true; 1890 } 1891 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) { 1892 /* Valid values are 0 and 2000, according to DT bindings */ 1893 priv->txcidm = !!delay; 1894 explicit_delay = true; 1895 } 1896 1897 if (explicit_delay) 1898 return; 1899 1900 /* Fall back to legacy rgmii-*id behavior */ 1901 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1902 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) { 1903 priv->rxcidm = 1; 1904 priv->rgmii_override = 1; 1905 } 1906 1907 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1908 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) { 1909 priv->txcidm = 1; 1910 priv->rgmii_override = 1; 1911 } 1912 } 1913 1914 static void ravb_set_delay_mode(struct net_device *ndev) 1915 { 1916 struct ravb_private *priv = netdev_priv(ndev); 1917 u32 set = 0; 1918 1919 if (!priv->info->internal_delay) 1920 return; 1921 1922 if (priv->rxcidm) 1923 set |= APSR_RDM; 1924 if (priv->txcidm) 1925 set |= APSR_TDM; 1926 ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set); 1927 } 1928 1929 /* Network device open function for Ethernet AVB */ 1930 static int ravb_open(struct net_device *ndev) 1931 { 1932 struct ravb_private *priv = netdev_priv(ndev); 1933 const struct ravb_hw_info *info = priv->info; 1934 struct device *dev = &priv->pdev->dev; 1935 int error; 1936 1937 napi_enable(&priv->napi[RAVB_BE]); 1938 if (info->nc_queues) 1939 napi_enable(&priv->napi[RAVB_NC]); 1940 1941 error = pm_runtime_resume_and_get(dev); 1942 if (error < 0) 1943 goto out_napi_off; 1944 1945 /* Set AVB config mode */ 1946 error = ravb_set_config_mode(ndev); 1947 if (error) 1948 goto out_rpm_put; 1949 1950 ravb_set_delay_mode(ndev); 1951 ravb_write(ndev, priv->desc_bat_dma, DBAT); 1952 1953 /* Device init */ 1954 error = ravb_dmac_init(ndev); 1955 if (error) 1956 goto out_set_reset; 1957 1958 ravb_emac_init(ndev); 1959 1960 ravb_set_gti(ndev); 1961 1962 /* Initialise PTP Clock driver */ 1963 if (info->gptp || info->ccc_gac) 1964 ravb_ptp_init(ndev, priv->pdev); 1965 1966 /* PHY control start */ 1967 error = ravb_phy_start(ndev); 1968 if (error) 1969 goto out_ptp_stop; 1970 1971 netif_tx_start_all_queues(ndev); 1972 1973 return 0; 1974 1975 out_ptp_stop: 1976 /* Stop PTP Clock driver */ 1977 if (info->gptp || info->ccc_gac) 1978 ravb_ptp_stop(ndev); 1979 ravb_stop_dma(ndev); 1980 out_set_reset: 1981 ravb_set_opmode(ndev, CCC_OPC_RESET); 1982 out_rpm_put: 1983 pm_runtime_mark_last_busy(dev); 1984 pm_runtime_put_autosuspend(dev); 1985 out_napi_off: 1986 if (info->nc_queues) 1987 napi_disable(&priv->napi[RAVB_NC]); 1988 napi_disable(&priv->napi[RAVB_BE]); 1989 return error; 1990 } 1991 1992 /* Timeout function for Ethernet AVB */ 1993 static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1994 { 1995 struct ravb_private *priv = netdev_priv(ndev); 1996 1997 netif_err(priv, tx_err, ndev, 1998 "transmit timed out, status %08x, resetting...\n", 1999 ravb_read(ndev, ISS)); 2000 2001 /* tx_errors count up */ 2002 ndev->stats.tx_errors++; 2003 2004 schedule_work(&priv->work); 2005 } 2006 2007 static void ravb_tx_timeout_work(struct work_struct *work) 2008 { 2009 struct ravb_private *priv = container_of(work, struct ravb_private, 2010 work); 2011 const struct ravb_hw_info *info = priv->info; 2012 struct net_device *ndev = priv->ndev; 2013 int error; 2014 2015 if (!rtnl_trylock()) { 2016 usleep_range(1000, 2000); 2017 schedule_work(&priv->work); 2018 return; 2019 } 2020 2021 netif_tx_stop_all_queues(ndev); 2022 2023 /* Stop PTP Clock driver */ 2024 if (info->gptp) 2025 ravb_ptp_stop(ndev); 2026 2027 /* Wait for DMA stopping */ 2028 if (ravb_stop_dma(ndev)) { 2029 /* If ravb_stop_dma() fails, the hardware is still operating 2030 * for TX and/or RX. So, this should not call the following 2031 * functions because ravb_dmac_init() is possible to fail too. 2032 * Also, this should not retry ravb_stop_dma() again and again 2033 * here because it's possible to wait forever. So, this just 2034 * re-enables the TX and RX and skip the following 2035 * re-initialization procedure. 2036 */ 2037 ravb_rcv_snd_enable(ndev); 2038 goto out; 2039 } 2040 2041 ravb_ring_free(ndev, RAVB_BE); 2042 if (info->nc_queues) 2043 ravb_ring_free(ndev, RAVB_NC); 2044 2045 /* Device init */ 2046 error = ravb_dmac_init(ndev); 2047 if (error) { 2048 /* If ravb_dmac_init() fails, descriptors are freed. So, this 2049 * should return here to avoid re-enabling the TX and RX in 2050 * ravb_emac_init(). 2051 */ 2052 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n", 2053 __func__, error); 2054 goto out_unlock; 2055 } 2056 ravb_emac_init(ndev); 2057 2058 out: 2059 /* Initialise PTP Clock driver */ 2060 if (info->gptp) 2061 ravb_ptp_init(ndev, priv->pdev); 2062 2063 netif_tx_start_all_queues(ndev); 2064 2065 out_unlock: 2066 rtnl_unlock(); 2067 } 2068 2069 static bool ravb_can_tx_csum_gbeth(struct sk_buff *skb) 2070 { 2071 struct iphdr *ip = ip_hdr(skb); 2072 2073 /* TODO: Need to add support for VLAN tag 802.1Q */ 2074 if (skb_vlan_tag_present(skb)) 2075 return false; 2076 2077 /* TODO: Need to add hardware checksum for IPv6 */ 2078 if (skb->protocol != htons(ETH_P_IP)) 2079 return false; 2080 2081 switch (ip->protocol) { 2082 case IPPROTO_TCP: 2083 break; 2084 case IPPROTO_UDP: 2085 /* If the checksum value in the UDP header field is 0, TOE does 2086 * not calculate checksum for UDP part of this frame as it is 2087 * optional function as per standards. 2088 */ 2089 if (udp_hdr(skb)->check == 0) 2090 return false; 2091 break; 2092 default: 2093 return false; 2094 } 2095 2096 return true; 2097 } 2098 2099 /* Packet transmit function for Ethernet AVB */ 2100 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 2101 { 2102 struct ravb_private *priv = netdev_priv(ndev); 2103 const struct ravb_hw_info *info = priv->info; 2104 unsigned int num_tx_desc = priv->num_tx_desc; 2105 u16 q = skb_get_queue_mapping(skb); 2106 struct ravb_tstamp_skb *ts_skb; 2107 struct ravb_tx_desc *desc; 2108 unsigned long flags; 2109 dma_addr_t dma_addr; 2110 void *buffer; 2111 u32 entry; 2112 u32 len; 2113 2114 if (skb->ip_summed == CHECKSUM_PARTIAL && !ravb_can_tx_csum_gbeth(skb)) 2115 skb_checksum_help(skb); 2116 2117 spin_lock_irqsave(&priv->lock, flags); 2118 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 2119 num_tx_desc) { 2120 netif_err(priv, tx_queued, ndev, 2121 "still transmitting with the full ring!\n"); 2122 netif_stop_subqueue(ndev, q); 2123 spin_unlock_irqrestore(&priv->lock, flags); 2124 return NETDEV_TX_BUSY; 2125 } 2126 2127 if (skb_put_padto(skb, ETH_ZLEN)) 2128 goto exit; 2129 2130 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc); 2131 priv->tx_skb[q][entry / num_tx_desc] = skb; 2132 2133 if (num_tx_desc > 1) { 2134 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 2135 entry / num_tx_desc * DPTR_ALIGN; 2136 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 2137 2138 /* Zero length DMA descriptors are problematic as they seem 2139 * to terminate DMA transfers. Avoid them by simply using a 2140 * length of DPTR_ALIGN (4) when skb data is aligned to 2141 * DPTR_ALIGN. 2142 * 2143 * As skb is guaranteed to have at least ETH_ZLEN (60) 2144 * bytes of data by the call to skb_put_padto() above this 2145 * is safe with respect to both the length of the first DMA 2146 * descriptor (len) overflowing the available data and the 2147 * length of the second DMA descriptor (skb->len - len) 2148 * being negative. 2149 */ 2150 if (len == 0) 2151 len = DPTR_ALIGN; 2152 2153 memcpy(buffer, skb->data, len); 2154 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 2155 DMA_TO_DEVICE); 2156 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2157 goto drop; 2158 2159 desc = &priv->tx_ring[q][entry]; 2160 desc->ds_tagl = cpu_to_le16(len); 2161 desc->dptr = cpu_to_le32(dma_addr); 2162 2163 buffer = skb->data + len; 2164 len = skb->len - len; 2165 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 2166 DMA_TO_DEVICE); 2167 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2168 goto unmap; 2169 2170 desc++; 2171 } else { 2172 desc = &priv->tx_ring[q][entry]; 2173 len = skb->len; 2174 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, 2175 DMA_TO_DEVICE); 2176 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2177 goto drop; 2178 } 2179 desc->ds_tagl = cpu_to_le16(len); 2180 desc->dptr = cpu_to_le32(dma_addr); 2181 2182 /* TX timestamp required */ 2183 if (info->gptp || info->ccc_gac) { 2184 if (q == RAVB_NC) { 2185 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 2186 if (!ts_skb) { 2187 if (num_tx_desc > 1) { 2188 desc--; 2189 dma_unmap_single(ndev->dev.parent, dma_addr, 2190 len, DMA_TO_DEVICE); 2191 } 2192 goto unmap; 2193 } 2194 ts_skb->skb = skb_get(skb); 2195 ts_skb->tag = priv->ts_skb_tag++; 2196 priv->ts_skb_tag &= 0x3ff; 2197 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 2198 2199 /* TAG and timestamp required flag */ 2200 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2201 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 2202 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12); 2203 } 2204 2205 skb_tx_timestamp(skb); 2206 } 2207 /* Descriptor type must be set after all the above writes */ 2208 dma_wmb(); 2209 if (num_tx_desc > 1) { 2210 desc->die_dt = DT_FEND; 2211 desc--; 2212 desc->die_dt = DT_FSTART; 2213 } else { 2214 desc->die_dt = DT_FSINGLE; 2215 } 2216 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 2217 2218 priv->cur_tx[q] += num_tx_desc; 2219 if (priv->cur_tx[q] - priv->dirty_tx[q] > 2220 (priv->num_tx_ring[q] - 1) * num_tx_desc && 2221 !ravb_tx_free(ndev, q, true)) 2222 netif_stop_subqueue(ndev, q); 2223 2224 exit: 2225 spin_unlock_irqrestore(&priv->lock, flags); 2226 return NETDEV_TX_OK; 2227 2228 unmap: 2229 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 2230 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 2231 drop: 2232 dev_kfree_skb_any(skb); 2233 priv->tx_skb[q][entry / num_tx_desc] = NULL; 2234 goto exit; 2235 } 2236 2237 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 2238 struct net_device *sb_dev) 2239 { 2240 /* If skb needs TX timestamp, it is handled in network control queue */ 2241 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 2242 RAVB_BE; 2243 2244 } 2245 2246 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 2247 { 2248 struct ravb_private *priv = netdev_priv(ndev); 2249 const struct ravb_hw_info *info = priv->info; 2250 struct net_device_stats *nstats, *stats0, *stats1; 2251 struct device *dev = &priv->pdev->dev; 2252 2253 nstats = &ndev->stats; 2254 2255 pm_runtime_get_noresume(dev); 2256 2257 if (!pm_runtime_active(dev)) 2258 goto out_rpm_put; 2259 2260 stats0 = &priv->stats[RAVB_BE]; 2261 2262 if (info->tx_counters) { 2263 nstats->tx_dropped += ravb_read(ndev, TROCR); 2264 ravb_write(ndev, 0, TROCR); /* (write clear) */ 2265 } 2266 2267 if (info->carrier_counters) { 2268 nstats->collisions += ravb_read(ndev, CXR41); 2269 ravb_write(ndev, 0, CXR41); /* (write clear) */ 2270 nstats->tx_carrier_errors += ravb_read(ndev, CXR42); 2271 ravb_write(ndev, 0, CXR42); /* (write clear) */ 2272 } 2273 2274 nstats->rx_packets = stats0->rx_packets; 2275 nstats->tx_packets = stats0->tx_packets; 2276 nstats->rx_bytes = stats0->rx_bytes; 2277 nstats->tx_bytes = stats0->tx_bytes; 2278 nstats->multicast = stats0->multicast; 2279 nstats->rx_errors = stats0->rx_errors; 2280 nstats->rx_crc_errors = stats0->rx_crc_errors; 2281 nstats->rx_frame_errors = stats0->rx_frame_errors; 2282 nstats->rx_length_errors = stats0->rx_length_errors; 2283 nstats->rx_missed_errors = stats0->rx_missed_errors; 2284 nstats->rx_over_errors = stats0->rx_over_errors; 2285 if (info->nc_queues) { 2286 stats1 = &priv->stats[RAVB_NC]; 2287 2288 nstats->rx_packets += stats1->rx_packets; 2289 nstats->tx_packets += stats1->tx_packets; 2290 nstats->rx_bytes += stats1->rx_bytes; 2291 nstats->tx_bytes += stats1->tx_bytes; 2292 nstats->multicast += stats1->multicast; 2293 nstats->rx_errors += stats1->rx_errors; 2294 nstats->rx_crc_errors += stats1->rx_crc_errors; 2295 nstats->rx_frame_errors += stats1->rx_frame_errors; 2296 nstats->rx_length_errors += stats1->rx_length_errors; 2297 nstats->rx_missed_errors += stats1->rx_missed_errors; 2298 nstats->rx_over_errors += stats1->rx_over_errors; 2299 } 2300 2301 out_rpm_put: 2302 pm_runtime_put_noidle(dev); 2303 return nstats; 2304 } 2305 2306 /* Update promiscuous bit */ 2307 static void ravb_set_rx_mode(struct net_device *ndev) 2308 { 2309 struct ravb_private *priv = netdev_priv(ndev); 2310 unsigned long flags; 2311 2312 spin_lock_irqsave(&priv->lock, flags); 2313 ravb_modify(ndev, ECMR, ECMR_PRM, 2314 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 2315 spin_unlock_irqrestore(&priv->lock, flags); 2316 } 2317 2318 /* Device close function for Ethernet AVB */ 2319 static int ravb_close(struct net_device *ndev) 2320 { 2321 struct device_node *np = ndev->dev.parent->of_node; 2322 struct ravb_private *priv = netdev_priv(ndev); 2323 const struct ravb_hw_info *info = priv->info; 2324 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 2325 struct device *dev = &priv->pdev->dev; 2326 int error; 2327 2328 netif_tx_stop_all_queues(ndev); 2329 2330 /* Disable interrupts by clearing the interrupt masks. */ 2331 ravb_write(ndev, 0, RIC0); 2332 ravb_write(ndev, 0, RIC2); 2333 ravb_write(ndev, 0, TIC); 2334 2335 /* PHY disconnect */ 2336 if (ndev->phydev) { 2337 phy_stop(ndev->phydev); 2338 phy_disconnect(ndev->phydev); 2339 if (of_phy_is_fixed_link(np)) 2340 of_phy_deregister_fixed_link(np); 2341 } 2342 2343 /* Stop PTP Clock driver */ 2344 if (info->gptp || info->ccc_gac) 2345 ravb_ptp_stop(ndev); 2346 2347 /* Set the config mode to stop the AVB-DMAC's processes */ 2348 if (ravb_stop_dma(ndev) < 0) 2349 netdev_err(ndev, 2350 "device will be stopped after h/w processes are done.\n"); 2351 2352 /* Clear the timestamp list */ 2353 if (info->gptp || info->ccc_gac) { 2354 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 2355 list_del(&ts_skb->list); 2356 kfree_skb(ts_skb->skb); 2357 kfree(ts_skb); 2358 } 2359 } 2360 2361 cancel_work_sync(&priv->work); 2362 2363 if (info->nc_queues) 2364 napi_disable(&priv->napi[RAVB_NC]); 2365 napi_disable(&priv->napi[RAVB_BE]); 2366 2367 /* Free all the skb's in the RX queue and the DMA buffers. */ 2368 ravb_ring_free(ndev, RAVB_BE); 2369 if (info->nc_queues) 2370 ravb_ring_free(ndev, RAVB_NC); 2371 2372 /* Update statistics. */ 2373 ravb_get_stats(ndev); 2374 2375 /* Set reset mode. */ 2376 error = ravb_set_opmode(ndev, CCC_OPC_RESET); 2377 if (error) 2378 return error; 2379 2380 pm_runtime_mark_last_busy(dev); 2381 pm_runtime_put_autosuspend(dev); 2382 2383 return 0; 2384 } 2385 2386 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 2387 { 2388 struct ravb_private *priv = netdev_priv(ndev); 2389 struct hwtstamp_config config; 2390 2391 config.flags = 0; 2392 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 2393 HWTSTAMP_TX_OFF; 2394 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) { 2395 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT: 2396 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 2397 break; 2398 case RAVB_RXTSTAMP_TYPE_ALL: 2399 config.rx_filter = HWTSTAMP_FILTER_ALL; 2400 break; 2401 default: 2402 config.rx_filter = HWTSTAMP_FILTER_NONE; 2403 } 2404 2405 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2406 -EFAULT : 0; 2407 } 2408 2409 /* Control hardware time stamping */ 2410 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 2411 { 2412 struct ravb_private *priv = netdev_priv(ndev); 2413 struct hwtstamp_config config; 2414 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 2415 u32 tstamp_tx_ctrl; 2416 2417 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 2418 return -EFAULT; 2419 2420 switch (config.tx_type) { 2421 case HWTSTAMP_TX_OFF: 2422 tstamp_tx_ctrl = 0; 2423 break; 2424 case HWTSTAMP_TX_ON: 2425 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 2426 break; 2427 default: 2428 return -ERANGE; 2429 } 2430 2431 switch (config.rx_filter) { 2432 case HWTSTAMP_FILTER_NONE: 2433 tstamp_rx_ctrl = 0; 2434 break; 2435 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2436 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 2437 break; 2438 default: 2439 config.rx_filter = HWTSTAMP_FILTER_ALL; 2440 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 2441 } 2442 2443 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 2444 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 2445 2446 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2447 -EFAULT : 0; 2448 } 2449 2450 /* ioctl to device function */ 2451 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 2452 { 2453 struct phy_device *phydev = ndev->phydev; 2454 2455 if (!netif_running(ndev)) 2456 return -EINVAL; 2457 2458 if (!phydev) 2459 return -ENODEV; 2460 2461 switch (cmd) { 2462 case SIOCGHWTSTAMP: 2463 return ravb_hwtstamp_get(ndev, req); 2464 case SIOCSHWTSTAMP: 2465 return ravb_hwtstamp_set(ndev, req); 2466 } 2467 2468 return phy_mii_ioctl(phydev, req, cmd); 2469 } 2470 2471 static int ravb_change_mtu(struct net_device *ndev, int new_mtu) 2472 { 2473 struct ravb_private *priv = netdev_priv(ndev); 2474 2475 WRITE_ONCE(ndev->mtu, new_mtu); 2476 2477 if (netif_running(ndev)) { 2478 synchronize_irq(priv->emac_irq); 2479 ravb_emac_init(ndev); 2480 } 2481 2482 netdev_update_features(ndev); 2483 2484 return 0; 2485 } 2486 2487 static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 2488 { 2489 struct ravb_private *priv = netdev_priv(ndev); 2490 unsigned long flags; 2491 2492 spin_lock_irqsave(&priv->lock, flags); 2493 2494 /* Disable TX and RX */ 2495 ravb_rcv_snd_disable(ndev); 2496 2497 /* Modify RX Checksum setting */ 2498 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 2499 2500 /* Enable TX and RX */ 2501 ravb_rcv_snd_enable(ndev); 2502 2503 spin_unlock_irqrestore(&priv->lock, flags); 2504 } 2505 2506 static int ravb_endisable_csum_gbeth(struct net_device *ndev, enum ravb_reg reg, 2507 u32 val, u32 mask) 2508 { 2509 u32 csr0 = CSR0_TPE | CSR0_RPE; 2510 int ret; 2511 2512 ravb_write(ndev, csr0 & ~mask, CSR0); 2513 ret = ravb_wait(ndev, CSR0, mask, 0); 2514 if (!ret) 2515 ravb_write(ndev, val, reg); 2516 2517 ravb_write(ndev, csr0, CSR0); 2518 2519 return ret; 2520 } 2521 2522 static int ravb_set_features_gbeth(struct net_device *ndev, 2523 netdev_features_t features) 2524 { 2525 netdev_features_t changed = ndev->features ^ features; 2526 struct ravb_private *priv = netdev_priv(ndev); 2527 unsigned long flags; 2528 int ret = 0; 2529 u32 val; 2530 2531 spin_lock_irqsave(&priv->lock, flags); 2532 if (changed & NETIF_F_RXCSUM) { 2533 if (features & NETIF_F_RXCSUM) 2534 val = CSR2_RIP4 | CSR2_RTCP4 | CSR2_RUDP4 | CSR2_RICMP4; 2535 else 2536 val = 0; 2537 2538 ret = ravb_endisable_csum_gbeth(ndev, CSR2, val, CSR0_RPE); 2539 if (ret) 2540 goto done; 2541 } 2542 2543 if (changed & NETIF_F_HW_CSUM) { 2544 if (features & NETIF_F_HW_CSUM) 2545 val = CSR1_TIP4 | CSR1_TTCP4 | CSR1_TUDP4; 2546 else 2547 val = 0; 2548 2549 ret = ravb_endisable_csum_gbeth(ndev, CSR1, val, CSR0_TPE); 2550 if (ret) 2551 goto done; 2552 } 2553 2554 done: 2555 spin_unlock_irqrestore(&priv->lock, flags); 2556 2557 return ret; 2558 } 2559 2560 static int ravb_set_features_rcar(struct net_device *ndev, 2561 netdev_features_t features) 2562 { 2563 netdev_features_t changed = ndev->features ^ features; 2564 2565 if (changed & NETIF_F_RXCSUM) 2566 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 2567 2568 return 0; 2569 } 2570 2571 static int ravb_set_features(struct net_device *ndev, 2572 netdev_features_t features) 2573 { 2574 struct ravb_private *priv = netdev_priv(ndev); 2575 const struct ravb_hw_info *info = priv->info; 2576 struct device *dev = &priv->pdev->dev; 2577 int ret; 2578 2579 pm_runtime_get_noresume(dev); 2580 2581 if (pm_runtime_active(dev)) 2582 ret = info->set_feature(ndev, features); 2583 else 2584 ret = 0; 2585 2586 pm_runtime_put_noidle(dev); 2587 2588 if (ret) 2589 return ret; 2590 2591 ndev->features = features; 2592 2593 return 0; 2594 } 2595 2596 static const struct net_device_ops ravb_netdev_ops = { 2597 .ndo_open = ravb_open, 2598 .ndo_stop = ravb_close, 2599 .ndo_start_xmit = ravb_start_xmit, 2600 .ndo_select_queue = ravb_select_queue, 2601 .ndo_get_stats = ravb_get_stats, 2602 .ndo_set_rx_mode = ravb_set_rx_mode, 2603 .ndo_tx_timeout = ravb_tx_timeout, 2604 .ndo_eth_ioctl = ravb_do_ioctl, 2605 .ndo_change_mtu = ravb_change_mtu, 2606 .ndo_validate_addr = eth_validate_addr, 2607 .ndo_set_mac_address = eth_mac_addr, 2608 .ndo_set_features = ravb_set_features, 2609 }; 2610 2611 /* MDIO bus init function */ 2612 static int ravb_mdio_init(struct ravb_private *priv) 2613 { 2614 struct platform_device *pdev = priv->pdev; 2615 struct device *dev = &pdev->dev; 2616 struct device_node *mdio_node; 2617 struct phy_device *phydev; 2618 struct device_node *pn; 2619 int error; 2620 2621 /* Bitbang init */ 2622 priv->mdiobb.ops = &bb_ops; 2623 2624 /* MII controller setting */ 2625 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 2626 if (!priv->mii_bus) 2627 return -ENOMEM; 2628 2629 /* Hook up MII support for ethtool */ 2630 priv->mii_bus->name = "ravb_mii"; 2631 priv->mii_bus->parent = dev; 2632 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2633 pdev->name, pdev->id); 2634 2635 /* Register MDIO bus */ 2636 mdio_node = of_get_child_by_name(dev->of_node, "mdio"); 2637 if (!mdio_node) { 2638 /* backwards compatibility for DT lacking mdio subnode */ 2639 mdio_node = of_node_get(dev->of_node); 2640 } 2641 error = of_mdiobus_register(priv->mii_bus, mdio_node); 2642 of_node_put(mdio_node); 2643 if (error) 2644 goto out_free_bus; 2645 2646 pn = of_parse_phandle(dev->of_node, "phy-handle", 0); 2647 phydev = of_phy_find_device(pn); 2648 if (phydev) { 2649 phydev->mac_managed_pm = true; 2650 put_device(&phydev->mdio.dev); 2651 } 2652 of_node_put(pn); 2653 2654 return 0; 2655 2656 out_free_bus: 2657 free_mdio_bitbang(priv->mii_bus); 2658 return error; 2659 } 2660 2661 /* MDIO bus release function */ 2662 static int ravb_mdio_release(struct ravb_private *priv) 2663 { 2664 /* Unregister mdio bus */ 2665 mdiobus_unregister(priv->mii_bus); 2666 2667 /* Free bitbang info */ 2668 free_mdio_bitbang(priv->mii_bus); 2669 2670 return 0; 2671 } 2672 2673 static const struct ravb_hw_info ravb_gen2_hw_info = { 2674 .receive = ravb_rx_rcar, 2675 .set_rate = ravb_set_rate_rcar, 2676 .set_feature = ravb_set_features_rcar, 2677 .dmac_init = ravb_dmac_init_rcar, 2678 .emac_init = ravb_emac_init_rcar, 2679 .gstrings_stats = ravb_gstrings_stats, 2680 .gstrings_size = sizeof(ravb_gstrings_stats), 2681 .net_hw_features = NETIF_F_RXCSUM, 2682 .net_features = NETIF_F_RXCSUM, 2683 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2684 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2685 .tx_max_frame_size = SZ_2K, 2686 .rx_max_frame_size = SZ_2K, 2687 .rx_buffer_size = SZ_2K + 2688 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), 2689 .rx_desc_size = sizeof(struct ravb_ex_rx_desc), 2690 .aligned_tx = 1, 2691 .gptp = 1, 2692 .nc_queues = 1, 2693 .magic_pkt = 1, 2694 }; 2695 2696 static const struct ravb_hw_info ravb_gen3_hw_info = { 2697 .receive = ravb_rx_rcar, 2698 .set_rate = ravb_set_rate_rcar, 2699 .set_feature = ravb_set_features_rcar, 2700 .dmac_init = ravb_dmac_init_rcar, 2701 .emac_init = ravb_emac_init_rcar, 2702 .gstrings_stats = ravb_gstrings_stats, 2703 .gstrings_size = sizeof(ravb_gstrings_stats), 2704 .net_hw_features = NETIF_F_RXCSUM, 2705 .net_features = NETIF_F_RXCSUM, 2706 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2707 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2708 .tx_max_frame_size = SZ_2K, 2709 .rx_max_frame_size = SZ_2K, 2710 .rx_buffer_size = SZ_2K + 2711 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), 2712 .rx_desc_size = sizeof(struct ravb_ex_rx_desc), 2713 .internal_delay = 1, 2714 .tx_counters = 1, 2715 .multi_irqs = 1, 2716 .irq_en_dis = 1, 2717 .ccc_gac = 1, 2718 .nc_queues = 1, 2719 .magic_pkt = 1, 2720 }; 2721 2722 static const struct ravb_hw_info ravb_gen4_hw_info = { 2723 .receive = ravb_rx_rcar, 2724 .set_rate = ravb_set_rate_rcar, 2725 .set_feature = ravb_set_features_rcar, 2726 .dmac_init = ravb_dmac_init_rcar, 2727 .emac_init = ravb_emac_init_rcar_gen4, 2728 .gstrings_stats = ravb_gstrings_stats, 2729 .gstrings_size = sizeof(ravb_gstrings_stats), 2730 .net_hw_features = NETIF_F_RXCSUM, 2731 .net_features = NETIF_F_RXCSUM, 2732 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2733 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2734 .tx_max_frame_size = SZ_2K, 2735 .rx_max_frame_size = SZ_2K, 2736 .rx_buffer_size = SZ_2K + 2737 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), 2738 .rx_desc_size = sizeof(struct ravb_ex_rx_desc), 2739 .internal_delay = 1, 2740 .tx_counters = 1, 2741 .multi_irqs = 1, 2742 .irq_en_dis = 1, 2743 .ccc_gac = 1, 2744 .nc_queues = 1, 2745 .magic_pkt = 1, 2746 }; 2747 2748 static const struct ravb_hw_info ravb_rzv2m_hw_info = { 2749 .receive = ravb_rx_rcar, 2750 .set_rate = ravb_set_rate_rcar, 2751 .set_feature = ravb_set_features_rcar, 2752 .dmac_init = ravb_dmac_init_rcar, 2753 .emac_init = ravb_emac_init_rcar, 2754 .gstrings_stats = ravb_gstrings_stats, 2755 .gstrings_size = sizeof(ravb_gstrings_stats), 2756 .net_hw_features = NETIF_F_RXCSUM, 2757 .net_features = NETIF_F_RXCSUM, 2758 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2759 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2760 .rx_max_frame_size = SZ_2K, 2761 .rx_buffer_size = SZ_2K + 2762 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), 2763 .rx_desc_size = sizeof(struct ravb_ex_rx_desc), 2764 .multi_irqs = 1, 2765 .err_mgmt_irqs = 1, 2766 .gptp = 1, 2767 .gptp_ref_clk = 1, 2768 .nc_queues = 1, 2769 .magic_pkt = 1, 2770 }; 2771 2772 static const struct ravb_hw_info gbeth_hw_info = { 2773 .receive = ravb_rx_gbeth, 2774 .set_rate = ravb_set_rate_gbeth, 2775 .set_feature = ravb_set_features_gbeth, 2776 .dmac_init = ravb_dmac_init_gbeth, 2777 .emac_init = ravb_emac_init_gbeth, 2778 .gstrings_stats = ravb_gstrings_stats_gbeth, 2779 .gstrings_size = sizeof(ravb_gstrings_stats_gbeth), 2780 .net_hw_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM, 2781 .net_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM, 2782 .stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth), 2783 .tccr_mask = TCCR_TSRQ0, 2784 .tx_max_frame_size = 1522, 2785 .rx_max_frame_size = SZ_8K, 2786 .rx_buffer_size = SZ_2K, 2787 .rx_desc_size = sizeof(struct ravb_rx_desc), 2788 .aligned_tx = 1, 2789 .coalesce_irqs = 1, 2790 .tx_counters = 1, 2791 .carrier_counters = 1, 2792 .half_duplex = 1, 2793 }; 2794 2795 static const struct of_device_id ravb_match_table[] = { 2796 { .compatible = "renesas,etheravb-r8a7790", .data = &ravb_gen2_hw_info }, 2797 { .compatible = "renesas,etheravb-r8a7794", .data = &ravb_gen2_hw_info }, 2798 { .compatible = "renesas,etheravb-rcar-gen2", .data = &ravb_gen2_hw_info }, 2799 { .compatible = "renesas,etheravb-r8a7795", .data = &ravb_gen3_hw_info }, 2800 { .compatible = "renesas,etheravb-rcar-gen3", .data = &ravb_gen3_hw_info }, 2801 { .compatible = "renesas,etheravb-rcar-gen4", .data = &ravb_gen4_hw_info }, 2802 { .compatible = "renesas,etheravb-rzv2m", .data = &ravb_rzv2m_hw_info }, 2803 { .compatible = "renesas,rzg2l-gbeth", .data = &gbeth_hw_info }, 2804 { } 2805 }; 2806 MODULE_DEVICE_TABLE(of, ravb_match_table); 2807 2808 static int ravb_setup_irq(struct ravb_private *priv, const char *irq_name, 2809 const char *ch, int *irq, irq_handler_t handler) 2810 { 2811 struct platform_device *pdev = priv->pdev; 2812 struct net_device *ndev = priv->ndev; 2813 struct device *dev = &pdev->dev; 2814 const char *devname = dev_name(dev); 2815 unsigned long flags; 2816 int error, irq_num; 2817 2818 if (irq_name) { 2819 devname = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", devname, ch); 2820 if (!devname) 2821 return -ENOMEM; 2822 2823 irq_num = platform_get_irq_byname(pdev, irq_name); 2824 flags = 0; 2825 } else { 2826 irq_num = platform_get_irq(pdev, 0); 2827 flags = IRQF_SHARED; 2828 } 2829 if (irq_num < 0) 2830 return irq_num; 2831 2832 if (irq) 2833 *irq = irq_num; 2834 2835 error = devm_request_irq(dev, irq_num, handler, flags, devname, ndev); 2836 if (error) 2837 netdev_err(ndev, "cannot request IRQ %s\n", devname); 2838 2839 return error; 2840 } 2841 2842 static int ravb_setup_irqs(struct ravb_private *priv) 2843 { 2844 const struct ravb_hw_info *info = priv->info; 2845 struct net_device *ndev = priv->ndev; 2846 const char *irq_name, *emac_irq_name; 2847 int error; 2848 2849 if (!info->multi_irqs) 2850 return ravb_setup_irq(priv, NULL, NULL, &ndev->irq, ravb_interrupt); 2851 2852 if (info->err_mgmt_irqs) { 2853 irq_name = "dia"; 2854 emac_irq_name = "line3"; 2855 } else { 2856 irq_name = "ch22"; 2857 emac_irq_name = "ch24"; 2858 } 2859 2860 error = ravb_setup_irq(priv, irq_name, "ch22:multi", &ndev->irq, ravb_multi_interrupt); 2861 if (error) 2862 return error; 2863 2864 error = ravb_setup_irq(priv, emac_irq_name, "ch24:emac", &priv->emac_irq, 2865 ravb_emac_interrupt); 2866 if (error) 2867 return error; 2868 2869 if (info->err_mgmt_irqs) { 2870 error = ravb_setup_irq(priv, "err_a", "err_a", NULL, ravb_multi_interrupt); 2871 if (error) 2872 return error; 2873 2874 error = ravb_setup_irq(priv, "mgmt_a", "mgmt_a", NULL, ravb_multi_interrupt); 2875 if (error) 2876 return error; 2877 } 2878 2879 error = ravb_setup_irq(priv, "ch0", "ch0:rx_be", NULL, ravb_be_interrupt); 2880 if (error) 2881 return error; 2882 2883 error = ravb_setup_irq(priv, "ch1", "ch1:rx_nc", NULL, ravb_nc_interrupt); 2884 if (error) 2885 return error; 2886 2887 error = ravb_setup_irq(priv, "ch18", "ch18:tx_be", NULL, ravb_be_interrupt); 2888 if (error) 2889 return error; 2890 2891 return ravb_setup_irq(priv, "ch19", "ch19:tx_nc", NULL, ravb_nc_interrupt); 2892 } 2893 2894 static int ravb_probe(struct platform_device *pdev) 2895 { 2896 struct device_node *np = pdev->dev.of_node; 2897 const struct ravb_hw_info *info; 2898 struct reset_control *rstc; 2899 struct ravb_private *priv; 2900 struct net_device *ndev; 2901 struct resource *res; 2902 int error, q; 2903 2904 if (!np) { 2905 dev_err(&pdev->dev, 2906 "this driver is required to be instantiated from device tree\n"); 2907 return -EINVAL; 2908 } 2909 2910 rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 2911 if (IS_ERR(rstc)) 2912 return dev_err_probe(&pdev->dev, PTR_ERR(rstc), 2913 "failed to get cpg reset\n"); 2914 2915 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 2916 NUM_TX_QUEUE, NUM_RX_QUEUE); 2917 if (!ndev) 2918 return -ENOMEM; 2919 2920 info = of_device_get_match_data(&pdev->dev); 2921 2922 ndev->features = info->net_features; 2923 ndev->hw_features = info->net_hw_features; 2924 2925 error = reset_control_deassert(rstc); 2926 if (error) 2927 goto out_free_netdev; 2928 2929 SET_NETDEV_DEV(ndev, &pdev->dev); 2930 2931 priv = netdev_priv(ndev); 2932 priv->info = info; 2933 priv->rstc = rstc; 2934 priv->ndev = ndev; 2935 priv->pdev = pdev; 2936 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2937 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2938 if (info->nc_queues) { 2939 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2940 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2941 } 2942 2943 error = ravb_setup_irqs(priv); 2944 if (error) 2945 goto out_reset_assert; 2946 2947 priv->clk = devm_clk_get(&pdev->dev, NULL); 2948 if (IS_ERR(priv->clk)) { 2949 error = PTR_ERR(priv->clk); 2950 goto out_reset_assert; 2951 } 2952 2953 if (info->gptp_ref_clk) { 2954 priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp"); 2955 if (IS_ERR(priv->gptp_clk)) { 2956 error = PTR_ERR(priv->gptp_clk); 2957 goto out_reset_assert; 2958 } 2959 } 2960 2961 priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk"); 2962 if (IS_ERR(priv->refclk)) { 2963 error = PTR_ERR(priv->refclk); 2964 goto out_reset_assert; 2965 } 2966 clk_prepare(priv->refclk); 2967 2968 platform_set_drvdata(pdev, ndev); 2969 pm_runtime_set_autosuspend_delay(&pdev->dev, 100); 2970 pm_runtime_use_autosuspend(&pdev->dev); 2971 pm_runtime_enable(&pdev->dev); 2972 error = pm_runtime_resume_and_get(&pdev->dev); 2973 if (error < 0) 2974 goto out_rpm_disable; 2975 2976 priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2977 if (IS_ERR(priv->addr)) { 2978 error = PTR_ERR(priv->addr); 2979 goto out_rpm_put; 2980 } 2981 2982 /* The Ether-specific entries in the device structure. */ 2983 ndev->base_addr = res->start; 2984 2985 spin_lock_init(&priv->lock); 2986 INIT_WORK(&priv->work, ravb_tx_timeout_work); 2987 2988 error = of_get_phy_mode(np, &priv->phy_interface); 2989 if (error && error != -ENODEV) 2990 goto out_rpm_put; 2991 2992 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 2993 priv->avb_link_active_low = 2994 of_property_read_bool(np, "renesas,ether-link-active-low"); 2995 2996 ndev->max_mtu = info->tx_max_frame_size - 2997 (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 2998 ndev->min_mtu = ETH_MIN_MTU; 2999 3000 /* FIXME: R-Car Gen2 has 4byte alignment restriction for tx buffer 3001 * Use two descriptor to handle such situation. First descriptor to 3002 * handle aligned data buffer and second descriptor to handle the 3003 * overflow data because of alignment. 3004 */ 3005 priv->num_tx_desc = info->aligned_tx ? 2 : 1; 3006 3007 /* Set function */ 3008 ndev->netdev_ops = &ravb_netdev_ops; 3009 ndev->ethtool_ops = &ravb_ethtool_ops; 3010 3011 error = ravb_compute_gti(ndev); 3012 if (error) 3013 goto out_rpm_put; 3014 3015 ravb_parse_delay_mode(np, ndev); 3016 3017 /* Allocate descriptor base address table */ 3018 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 3019 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 3020 &priv->desc_bat_dma, GFP_KERNEL); 3021 if (!priv->desc_bat) { 3022 dev_err(&pdev->dev, 3023 "Cannot allocate desc base address table (size %d bytes)\n", 3024 priv->desc_bat_size); 3025 error = -ENOMEM; 3026 goto out_rpm_put; 3027 } 3028 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 3029 priv->desc_bat[q].die_dt = DT_EOS; 3030 3031 /* Initialise HW timestamp list */ 3032 INIT_LIST_HEAD(&priv->ts_skb_list); 3033 3034 /* Debug message level */ 3035 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 3036 3037 /* Set config mode as this is needed for PHY initialization. */ 3038 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 3039 if (error) 3040 goto out_rpm_put; 3041 3042 /* Read and set MAC address */ 3043 ravb_read_mac_address(np, ndev); 3044 if (!is_valid_ether_addr(ndev->dev_addr)) { 3045 dev_warn(&pdev->dev, 3046 "no valid MAC address supplied, using a random one\n"); 3047 eth_hw_addr_random(ndev); 3048 } 3049 3050 /* MDIO bus init */ 3051 error = ravb_mdio_init(priv); 3052 if (error) { 3053 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 3054 goto out_reset_mode; 3055 } 3056 3057 /* Undo previous switch to config opmode. */ 3058 error = ravb_set_opmode(ndev, CCC_OPC_RESET); 3059 if (error) 3060 goto out_mdio_release; 3061 3062 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll); 3063 if (info->nc_queues) 3064 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll); 3065 3066 if (info->coalesce_irqs) { 3067 netdev_sw_irq_coalesce_default_on(ndev); 3068 if (num_present_cpus() == 1) 3069 dev_set_threaded(ndev, true); 3070 } 3071 3072 /* Network device register */ 3073 error = register_netdev(ndev); 3074 if (error) 3075 goto out_napi_del; 3076 3077 device_set_wakeup_capable(&pdev->dev, 1); 3078 3079 /* Print device information */ 3080 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 3081 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 3082 3083 pm_runtime_mark_last_busy(&pdev->dev); 3084 pm_runtime_put_autosuspend(&pdev->dev); 3085 3086 return 0; 3087 3088 out_napi_del: 3089 if (info->nc_queues) 3090 netif_napi_del(&priv->napi[RAVB_NC]); 3091 3092 netif_napi_del(&priv->napi[RAVB_BE]); 3093 out_mdio_release: 3094 ravb_mdio_release(priv); 3095 out_reset_mode: 3096 ravb_set_opmode(ndev, CCC_OPC_RESET); 3097 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 3098 priv->desc_bat_dma); 3099 out_rpm_put: 3100 pm_runtime_put(&pdev->dev); 3101 out_rpm_disable: 3102 pm_runtime_disable(&pdev->dev); 3103 pm_runtime_dont_use_autosuspend(&pdev->dev); 3104 clk_unprepare(priv->refclk); 3105 out_reset_assert: 3106 reset_control_assert(rstc); 3107 out_free_netdev: 3108 free_netdev(ndev); 3109 return error; 3110 } 3111 3112 static void ravb_remove(struct platform_device *pdev) 3113 { 3114 struct net_device *ndev = platform_get_drvdata(pdev); 3115 struct ravb_private *priv = netdev_priv(ndev); 3116 const struct ravb_hw_info *info = priv->info; 3117 struct device *dev = &priv->pdev->dev; 3118 int error; 3119 3120 error = pm_runtime_resume_and_get(dev); 3121 if (error < 0) 3122 return; 3123 3124 unregister_netdev(ndev); 3125 if (info->nc_queues) 3126 netif_napi_del(&priv->napi[RAVB_NC]); 3127 netif_napi_del(&priv->napi[RAVB_BE]); 3128 3129 ravb_mdio_release(priv); 3130 3131 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 3132 priv->desc_bat_dma); 3133 3134 pm_runtime_put_sync_suspend(&pdev->dev); 3135 pm_runtime_disable(&pdev->dev); 3136 pm_runtime_dont_use_autosuspend(dev); 3137 clk_unprepare(priv->refclk); 3138 reset_control_assert(priv->rstc); 3139 free_netdev(ndev); 3140 platform_set_drvdata(pdev, NULL); 3141 } 3142 3143 static int ravb_wol_setup(struct net_device *ndev) 3144 { 3145 struct ravb_private *priv = netdev_priv(ndev); 3146 const struct ravb_hw_info *info = priv->info; 3147 3148 /* Disable interrupts by clearing the interrupt masks. */ 3149 ravb_write(ndev, 0, RIC0); 3150 ravb_write(ndev, 0, RIC2); 3151 ravb_write(ndev, 0, TIC); 3152 3153 /* Only allow ECI interrupts */ 3154 synchronize_irq(priv->emac_irq); 3155 if (info->nc_queues) 3156 napi_disable(&priv->napi[RAVB_NC]); 3157 napi_disable(&priv->napi[RAVB_BE]); 3158 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 3159 3160 /* Enable MagicPacket */ 3161 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 3162 3163 if (priv->info->ccc_gac) 3164 ravb_ptp_stop(ndev); 3165 3166 return enable_irq_wake(priv->emac_irq); 3167 } 3168 3169 static int ravb_wol_restore(struct net_device *ndev) 3170 { 3171 struct ravb_private *priv = netdev_priv(ndev); 3172 const struct ravb_hw_info *info = priv->info; 3173 int error; 3174 3175 /* Set reset mode to rearm the WoL logic. */ 3176 error = ravb_set_opmode(ndev, CCC_OPC_RESET); 3177 if (error) 3178 return error; 3179 3180 /* Set AVB config mode. */ 3181 error = ravb_set_config_mode(ndev); 3182 if (error) 3183 return error; 3184 3185 if (priv->info->ccc_gac) 3186 ravb_ptp_init(ndev, priv->pdev); 3187 3188 if (info->nc_queues) 3189 napi_enable(&priv->napi[RAVB_NC]); 3190 napi_enable(&priv->napi[RAVB_BE]); 3191 3192 /* Disable MagicPacket */ 3193 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 3194 3195 ravb_close(ndev); 3196 3197 return disable_irq_wake(priv->emac_irq); 3198 } 3199 3200 static int ravb_suspend(struct device *dev) 3201 { 3202 struct net_device *ndev = dev_get_drvdata(dev); 3203 struct ravb_private *priv = netdev_priv(ndev); 3204 int ret; 3205 3206 if (!netif_running(ndev)) 3207 goto reset_assert; 3208 3209 netif_device_detach(ndev); 3210 3211 if (priv->wol_enabled) 3212 return ravb_wol_setup(ndev); 3213 3214 ret = ravb_close(ndev); 3215 if (ret) 3216 return ret; 3217 3218 ret = pm_runtime_force_suspend(&priv->pdev->dev); 3219 if (ret) 3220 return ret; 3221 3222 reset_assert: 3223 return reset_control_assert(priv->rstc); 3224 } 3225 3226 static int ravb_resume(struct device *dev) 3227 { 3228 struct net_device *ndev = dev_get_drvdata(dev); 3229 struct ravb_private *priv = netdev_priv(ndev); 3230 int ret; 3231 3232 ret = reset_control_deassert(priv->rstc); 3233 if (ret) 3234 return ret; 3235 3236 if (!netif_running(ndev)) 3237 return 0; 3238 3239 /* If WoL is enabled restore the interface. */ 3240 if (priv->wol_enabled) { 3241 ret = ravb_wol_restore(ndev); 3242 if (ret) 3243 return ret; 3244 } else { 3245 ret = pm_runtime_force_resume(dev); 3246 if (ret) 3247 return ret; 3248 } 3249 3250 /* Reopening the interface will restore the device to the working state. */ 3251 ret = ravb_open(ndev); 3252 if (ret < 0) 3253 goto out_rpm_put; 3254 3255 ravb_set_rx_mode(ndev); 3256 netif_device_attach(ndev); 3257 3258 return 0; 3259 3260 out_rpm_put: 3261 if (!priv->wol_enabled) { 3262 pm_runtime_mark_last_busy(dev); 3263 pm_runtime_put_autosuspend(dev); 3264 } 3265 3266 return ret; 3267 } 3268 3269 static int ravb_runtime_suspend(struct device *dev) 3270 { 3271 struct net_device *ndev = dev_get_drvdata(dev); 3272 struct ravb_private *priv = netdev_priv(ndev); 3273 3274 clk_disable(priv->refclk); 3275 3276 return 0; 3277 } 3278 3279 static int ravb_runtime_resume(struct device *dev) 3280 { 3281 struct net_device *ndev = dev_get_drvdata(dev); 3282 struct ravb_private *priv = netdev_priv(ndev); 3283 3284 return clk_enable(priv->refclk); 3285 } 3286 3287 static const struct dev_pm_ops ravb_dev_pm_ops = { 3288 SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 3289 RUNTIME_PM_OPS(ravb_runtime_suspend, ravb_runtime_resume, NULL) 3290 }; 3291 3292 static struct platform_driver ravb_driver = { 3293 .probe = ravb_probe, 3294 .remove_new = ravb_remove, 3295 .driver = { 3296 .name = "ravb", 3297 .pm = pm_ptr(&ravb_dev_pm_ops), 3298 .of_match_table = ravb_match_table, 3299 }, 3300 }; 3301 3302 module_platform_driver(ravb_driver); 3303 3304 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 3305 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 3306 MODULE_LICENSE("GPL v2"); 3307