1 /* Renesas Ethernet AVB device driver 2 * 3 * Copyright (C) 2014-2015 Renesas Electronics Corporation 4 * Copyright (C) 2015 Renesas Solutions Corp. 5 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 6 * 7 * Based on the SuperH Ethernet driver 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License version 2, 11 * as published by the Free Software Foundation. 12 */ 13 14 #include <linux/cache.h> 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/err.h> 19 #include <linux/etherdevice.h> 20 #include <linux/ethtool.h> 21 #include <linux/if_vlan.h> 22 #include <linux/kernel.h> 23 #include <linux/list.h> 24 #include <linux/module.h> 25 #include <linux/net_tstamp.h> 26 #include <linux/of.h> 27 #include <linux/of_device.h> 28 #include <linux/of_irq.h> 29 #include <linux/of_mdio.h> 30 #include <linux/of_net.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/slab.h> 33 #include <linux/spinlock.h> 34 35 #include <asm/div64.h> 36 37 #include "ravb.h" 38 39 #define RAVB_DEF_MSG_ENABLE \ 40 (NETIF_MSG_LINK | \ 41 NETIF_MSG_TIMER | \ 42 NETIF_MSG_RX_ERR | \ 43 NETIF_MSG_TX_ERR) 44 45 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = { 46 "ch0", /* RAVB_BE */ 47 "ch1", /* RAVB_NC */ 48 }; 49 50 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = { 51 "ch18", /* RAVB_BE */ 52 "ch19", /* RAVB_NC */ 53 }; 54 55 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 56 u32 set) 57 { 58 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 59 } 60 61 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 62 { 63 int i; 64 65 for (i = 0; i < 10000; i++) { 66 if ((ravb_read(ndev, reg) & mask) == value) 67 return 0; 68 udelay(10); 69 } 70 return -ETIMEDOUT; 71 } 72 73 static int ravb_config(struct net_device *ndev) 74 { 75 int error; 76 77 /* Set config mode */ 78 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 79 /* Check if the operating mode is changed to the config mode */ 80 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG); 81 if (error) 82 netdev_err(ndev, "failed to switch device to config mode\n"); 83 84 return error; 85 } 86 87 static void ravb_set_duplex(struct net_device *ndev) 88 { 89 struct ravb_private *priv = netdev_priv(ndev); 90 91 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex ? ECMR_DM : 0); 92 } 93 94 static void ravb_set_rate(struct net_device *ndev) 95 { 96 struct ravb_private *priv = netdev_priv(ndev); 97 98 switch (priv->speed) { 99 case 100: /* 100BASE */ 100 ravb_write(ndev, GECMR_SPEED_100, GECMR); 101 break; 102 case 1000: /* 1000BASE */ 103 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 104 break; 105 } 106 } 107 108 static void ravb_set_buffer_align(struct sk_buff *skb) 109 { 110 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 111 112 if (reserve) 113 skb_reserve(skb, RAVB_ALIGN - reserve); 114 } 115 116 /* Get MAC address from the MAC address registers 117 * 118 * Ethernet AVB device doesn't have ROM for MAC address. 119 * This function gets the MAC address that was used by a bootloader. 120 */ 121 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac) 122 { 123 if (mac) { 124 ether_addr_copy(ndev->dev_addr, mac); 125 } else { 126 u32 mahr = ravb_read(ndev, MAHR); 127 u32 malr = ravb_read(ndev, MALR); 128 129 ndev->dev_addr[0] = (mahr >> 24) & 0xFF; 130 ndev->dev_addr[1] = (mahr >> 16) & 0xFF; 131 ndev->dev_addr[2] = (mahr >> 8) & 0xFF; 132 ndev->dev_addr[3] = (mahr >> 0) & 0xFF; 133 ndev->dev_addr[4] = (malr >> 8) & 0xFF; 134 ndev->dev_addr[5] = (malr >> 0) & 0xFF; 135 } 136 } 137 138 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 139 { 140 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 141 mdiobb); 142 143 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 144 } 145 146 /* MDC pin control */ 147 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 148 { 149 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 150 } 151 152 /* Data I/O pin control */ 153 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 154 { 155 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 156 } 157 158 /* Set data bit */ 159 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 160 { 161 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 162 } 163 164 /* Get data bit */ 165 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 166 { 167 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 168 mdiobb); 169 170 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 171 } 172 173 /* MDIO bus control struct */ 174 static struct mdiobb_ops bb_ops = { 175 .owner = THIS_MODULE, 176 .set_mdc = ravb_set_mdc, 177 .set_mdio_dir = ravb_set_mdio_dir, 178 .set_mdio_data = ravb_set_mdio_data, 179 .get_mdio_data = ravb_get_mdio_data, 180 }; 181 182 /* Free skb's and DMA buffers for Ethernet AVB */ 183 static void ravb_ring_free(struct net_device *ndev, int q) 184 { 185 struct ravb_private *priv = netdev_priv(ndev); 186 int ring_size; 187 int i; 188 189 /* Free RX skb ringbuffer */ 190 if (priv->rx_skb[q]) { 191 for (i = 0; i < priv->num_rx_ring[q]; i++) 192 dev_kfree_skb(priv->rx_skb[q][i]); 193 } 194 kfree(priv->rx_skb[q]); 195 priv->rx_skb[q] = NULL; 196 197 /* Free TX skb ringbuffer */ 198 if (priv->tx_skb[q]) { 199 for (i = 0; i < priv->num_tx_ring[q]; i++) 200 dev_kfree_skb(priv->tx_skb[q][i]); 201 } 202 kfree(priv->tx_skb[q]); 203 priv->tx_skb[q] = NULL; 204 205 /* Free aligned TX buffers */ 206 kfree(priv->tx_align[q]); 207 priv->tx_align[q] = NULL; 208 209 if (priv->rx_ring[q]) { 210 ring_size = sizeof(struct ravb_ex_rx_desc) * 211 (priv->num_rx_ring[q] + 1); 212 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], 213 priv->rx_desc_dma[q]); 214 priv->rx_ring[q] = NULL; 215 } 216 217 if (priv->tx_ring[q]) { 218 ring_size = sizeof(struct ravb_tx_desc) * 219 (priv->num_tx_ring[q] * NUM_TX_DESC + 1); 220 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 221 priv->tx_desc_dma[q]); 222 priv->tx_ring[q] = NULL; 223 } 224 } 225 226 /* Format skb and descriptor buffer for Ethernet AVB */ 227 static void ravb_ring_format(struct net_device *ndev, int q) 228 { 229 struct ravb_private *priv = netdev_priv(ndev); 230 struct ravb_ex_rx_desc *rx_desc; 231 struct ravb_tx_desc *tx_desc; 232 struct ravb_desc *desc; 233 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 234 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 235 NUM_TX_DESC; 236 dma_addr_t dma_addr; 237 int i; 238 239 priv->cur_rx[q] = 0; 240 priv->cur_tx[q] = 0; 241 priv->dirty_rx[q] = 0; 242 priv->dirty_tx[q] = 0; 243 244 memset(priv->rx_ring[q], 0, rx_ring_size); 245 /* Build RX ring buffer */ 246 for (i = 0; i < priv->num_rx_ring[q]; i++) { 247 /* RX descriptor */ 248 rx_desc = &priv->rx_ring[q][i]; 249 rx_desc->ds_cc = cpu_to_le16(PKT_BUF_SZ); 250 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 251 PKT_BUF_SZ, 252 DMA_FROM_DEVICE); 253 /* We just set the data size to 0 for a failed mapping which 254 * should prevent DMA from happening... 255 */ 256 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 257 rx_desc->ds_cc = cpu_to_le16(0); 258 rx_desc->dptr = cpu_to_le32(dma_addr); 259 rx_desc->die_dt = DT_FEMPTY; 260 } 261 rx_desc = &priv->rx_ring[q][i]; 262 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 263 rx_desc->die_dt = DT_LINKFIX; /* type */ 264 265 memset(priv->tx_ring[q], 0, tx_ring_size); 266 /* Build TX ring buffer */ 267 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 268 i++, tx_desc++) { 269 tx_desc->die_dt = DT_EEMPTY; 270 tx_desc++; 271 tx_desc->die_dt = DT_EEMPTY; 272 } 273 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 274 tx_desc->die_dt = DT_LINKFIX; /* type */ 275 276 /* RX descriptor base address for best effort */ 277 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 278 desc->die_dt = DT_LINKFIX; /* type */ 279 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 280 281 /* TX descriptor base address for best effort */ 282 desc = &priv->desc_bat[q]; 283 desc->die_dt = DT_LINKFIX; /* type */ 284 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 285 } 286 287 /* Init skb and descriptor buffer for Ethernet AVB */ 288 static int ravb_ring_init(struct net_device *ndev, int q) 289 { 290 struct ravb_private *priv = netdev_priv(ndev); 291 struct sk_buff *skb; 292 int ring_size; 293 int i; 294 295 /* Allocate RX and TX skb rings */ 296 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 297 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 298 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 299 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 300 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 301 goto error; 302 303 for (i = 0; i < priv->num_rx_ring[q]; i++) { 304 skb = netdev_alloc_skb(ndev, PKT_BUF_SZ + RAVB_ALIGN - 1); 305 if (!skb) 306 goto error; 307 ravb_set_buffer_align(skb); 308 priv->rx_skb[q][i] = skb; 309 } 310 311 /* Allocate rings for the aligned buffers */ 312 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 313 DPTR_ALIGN - 1, GFP_KERNEL); 314 if (!priv->tx_align[q]) 315 goto error; 316 317 /* Allocate all RX descriptors. */ 318 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); 319 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 320 &priv->rx_desc_dma[q], 321 GFP_KERNEL); 322 if (!priv->rx_ring[q]) 323 goto error; 324 325 priv->dirty_rx[q] = 0; 326 327 /* Allocate all TX descriptors. */ 328 ring_size = sizeof(struct ravb_tx_desc) * 329 (priv->num_tx_ring[q] * NUM_TX_DESC + 1); 330 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 331 &priv->tx_desc_dma[q], 332 GFP_KERNEL); 333 if (!priv->tx_ring[q]) 334 goto error; 335 336 return 0; 337 338 error: 339 ravb_ring_free(ndev, q); 340 341 return -ENOMEM; 342 } 343 344 /* E-MAC init function */ 345 static void ravb_emac_init(struct net_device *ndev) 346 { 347 struct ravb_private *priv = netdev_priv(ndev); 348 349 /* Receive frame limit set register */ 350 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 351 352 /* PAUSE prohibition */ 353 ravb_write(ndev, ECMR_ZPF | (priv->duplex ? ECMR_DM : 0) | 354 ECMR_TE | ECMR_RE, ECMR); 355 356 ravb_set_rate(ndev); 357 358 /* Set MAC address */ 359 ravb_write(ndev, 360 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 361 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 362 ravb_write(ndev, 363 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 364 365 /* E-MAC status register clear */ 366 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 367 368 /* E-MAC interrupt enable register */ 369 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 370 } 371 372 /* Device init function for Ethernet AVB */ 373 static int ravb_dmac_init(struct net_device *ndev) 374 { 375 struct ravb_private *priv = netdev_priv(ndev); 376 int error; 377 378 /* Set CONFIG mode */ 379 error = ravb_config(ndev); 380 if (error) 381 return error; 382 383 error = ravb_ring_init(ndev, RAVB_BE); 384 if (error) 385 return error; 386 error = ravb_ring_init(ndev, RAVB_NC); 387 if (error) { 388 ravb_ring_free(ndev, RAVB_BE); 389 return error; 390 } 391 392 /* Descriptor format */ 393 ravb_ring_format(ndev, RAVB_BE); 394 ravb_ring_format(ndev, RAVB_NC); 395 396 #if defined(__LITTLE_ENDIAN) 397 ravb_modify(ndev, CCC, CCC_BOC, 0); 398 #else 399 ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC); 400 #endif 401 402 /* Set AVB RX */ 403 ravb_write(ndev, 404 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 405 406 /* Set FIFO size */ 407 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00222200, TGC); 408 409 /* Timestamp enable */ 410 ravb_write(ndev, TCCR_TFEN, TCCR); 411 412 /* Interrupt init: */ 413 if (priv->chip_id == RCAR_GEN3) { 414 /* Clear DIL.DPLx */ 415 ravb_write(ndev, 0, DIL); 416 /* Set queue specific interrupt */ 417 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 418 } 419 /* Frame receive */ 420 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 421 /* Disable FIFO full warning */ 422 ravb_write(ndev, 0, RIC1); 423 /* Receive FIFO full error, descriptor empty */ 424 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 425 /* Frame transmitted, timestamp FIFO updated */ 426 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 427 428 /* Setting the control will start the AVB-DMAC process. */ 429 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION); 430 431 return 0; 432 } 433 434 /* Free TX skb function for AVB-IP */ 435 static int ravb_tx_free(struct net_device *ndev, int q) 436 { 437 struct ravb_private *priv = netdev_priv(ndev); 438 struct net_device_stats *stats = &priv->stats[q]; 439 struct ravb_tx_desc *desc; 440 int free_num = 0; 441 int entry; 442 u32 size; 443 444 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 445 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 446 NUM_TX_DESC); 447 desc = &priv->tx_ring[q][entry]; 448 if (desc->die_dt != DT_FEMPTY) 449 break; 450 /* Descriptor type must be checked before all other reads */ 451 dma_rmb(); 452 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 453 /* Free the original skb. */ 454 if (priv->tx_skb[q][entry / NUM_TX_DESC]) { 455 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 456 size, DMA_TO_DEVICE); 457 /* Last packet descriptor? */ 458 if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) { 459 entry /= NUM_TX_DESC; 460 dev_kfree_skb_any(priv->tx_skb[q][entry]); 461 priv->tx_skb[q][entry] = NULL; 462 stats->tx_packets++; 463 } 464 free_num++; 465 } 466 stats->tx_bytes += size; 467 desc->die_dt = DT_EEMPTY; 468 } 469 return free_num; 470 } 471 472 static void ravb_get_tx_tstamp(struct net_device *ndev) 473 { 474 struct ravb_private *priv = netdev_priv(ndev); 475 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 476 struct skb_shared_hwtstamps shhwtstamps; 477 struct sk_buff *skb; 478 struct timespec64 ts; 479 u16 tag, tfa_tag; 480 int count; 481 u32 tfa2; 482 483 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 484 while (count--) { 485 tfa2 = ravb_read(ndev, TFA2); 486 tfa_tag = (tfa2 & TFA2_TST) >> 16; 487 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 488 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 489 ravb_read(ndev, TFA1); 490 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 491 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 492 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 493 list) { 494 skb = ts_skb->skb; 495 tag = ts_skb->tag; 496 list_del(&ts_skb->list); 497 kfree(ts_skb); 498 if (tag == tfa_tag) { 499 skb_tstamp_tx(skb, &shhwtstamps); 500 break; 501 } 502 } 503 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 504 } 505 } 506 507 /* Packet receive function for Ethernet AVB */ 508 static bool ravb_rx(struct net_device *ndev, int *quota, int q) 509 { 510 struct ravb_private *priv = netdev_priv(ndev); 511 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 512 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 513 priv->cur_rx[q]; 514 struct net_device_stats *stats = &priv->stats[q]; 515 struct ravb_ex_rx_desc *desc; 516 struct sk_buff *skb; 517 dma_addr_t dma_addr; 518 struct timespec64 ts; 519 u8 desc_status; 520 u16 pkt_len; 521 int limit; 522 523 boguscnt = min(boguscnt, *quota); 524 limit = boguscnt; 525 desc = &priv->rx_ring[q][entry]; 526 while (desc->die_dt != DT_FEMPTY) { 527 /* Descriptor type must be checked before all other reads */ 528 dma_rmb(); 529 desc_status = desc->msc; 530 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 531 532 if (--boguscnt < 0) 533 break; 534 535 /* We use 0-byte descriptors to mark the DMA mapping errors */ 536 if (!pkt_len) 537 continue; 538 539 if (desc_status & MSC_MC) 540 stats->multicast++; 541 542 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 543 MSC_CEEF)) { 544 stats->rx_errors++; 545 if (desc_status & MSC_CRC) 546 stats->rx_crc_errors++; 547 if (desc_status & MSC_RFE) 548 stats->rx_frame_errors++; 549 if (desc_status & (MSC_RTLF | MSC_RTSF)) 550 stats->rx_length_errors++; 551 if (desc_status & MSC_CEEF) 552 stats->rx_missed_errors++; 553 } else { 554 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 555 556 skb = priv->rx_skb[q][entry]; 557 priv->rx_skb[q][entry] = NULL; 558 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 559 PKT_BUF_SZ, 560 DMA_FROM_DEVICE); 561 get_ts &= (q == RAVB_NC) ? 562 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 563 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 564 if (get_ts) { 565 struct skb_shared_hwtstamps *shhwtstamps; 566 567 shhwtstamps = skb_hwtstamps(skb); 568 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 569 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 570 32) | le32_to_cpu(desc->ts_sl); 571 ts.tv_nsec = le32_to_cpu(desc->ts_n); 572 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 573 } 574 skb_put(skb, pkt_len); 575 skb->protocol = eth_type_trans(skb, ndev); 576 napi_gro_receive(&priv->napi[q], skb); 577 stats->rx_packets++; 578 stats->rx_bytes += pkt_len; 579 } 580 581 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 582 desc = &priv->rx_ring[q][entry]; 583 } 584 585 /* Refill the RX ring buffers. */ 586 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 587 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 588 desc = &priv->rx_ring[q][entry]; 589 desc->ds_cc = cpu_to_le16(PKT_BUF_SZ); 590 591 if (!priv->rx_skb[q][entry]) { 592 skb = netdev_alloc_skb(ndev, 593 PKT_BUF_SZ + RAVB_ALIGN - 1); 594 if (!skb) 595 break; /* Better luck next round. */ 596 ravb_set_buffer_align(skb); 597 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 598 le16_to_cpu(desc->ds_cc), 599 DMA_FROM_DEVICE); 600 skb_checksum_none_assert(skb); 601 /* We just set the data size to 0 for a failed mapping 602 * which should prevent DMA from happening... 603 */ 604 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 605 desc->ds_cc = cpu_to_le16(0); 606 desc->dptr = cpu_to_le32(dma_addr); 607 priv->rx_skb[q][entry] = skb; 608 } 609 /* Descriptor type must be set after all the above writes */ 610 dma_wmb(); 611 desc->die_dt = DT_FEMPTY; 612 } 613 614 *quota -= limit - (++boguscnt); 615 616 return boguscnt <= 0; 617 } 618 619 static void ravb_rcv_snd_disable(struct net_device *ndev) 620 { 621 /* Disable TX and RX */ 622 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 623 } 624 625 static void ravb_rcv_snd_enable(struct net_device *ndev) 626 { 627 /* Enable TX and RX */ 628 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 629 } 630 631 /* function for waiting dma process finished */ 632 static int ravb_stop_dma(struct net_device *ndev) 633 { 634 int error; 635 636 /* Wait for stopping the hardware TX process */ 637 error = ravb_wait(ndev, TCCR, 638 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0); 639 if (error) 640 return error; 641 642 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 643 0); 644 if (error) 645 return error; 646 647 /* Stop the E-MAC's RX/TX processes. */ 648 ravb_rcv_snd_disable(ndev); 649 650 /* Wait for stopping the RX DMA process */ 651 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 652 if (error) 653 return error; 654 655 /* Stop AVB-DMAC process */ 656 return ravb_config(ndev); 657 } 658 659 /* E-MAC interrupt handler */ 660 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 661 { 662 struct ravb_private *priv = netdev_priv(ndev); 663 u32 ecsr, psr; 664 665 ecsr = ravb_read(ndev, ECSR); 666 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 667 if (ecsr & ECSR_ICD) 668 ndev->stats.tx_carrier_errors++; 669 if (ecsr & ECSR_LCHNG) { 670 /* Link changed */ 671 if (priv->no_avb_link) 672 return; 673 psr = ravb_read(ndev, PSR); 674 if (priv->avb_link_active_low) 675 psr ^= PSR_LMON; 676 if (!(psr & PSR_LMON)) { 677 /* DIsable RX and TX */ 678 ravb_rcv_snd_disable(ndev); 679 } else { 680 /* Enable RX and TX */ 681 ravb_rcv_snd_enable(ndev); 682 } 683 } 684 } 685 686 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 687 { 688 struct net_device *ndev = dev_id; 689 struct ravb_private *priv = netdev_priv(ndev); 690 691 spin_lock(&priv->lock); 692 ravb_emac_interrupt_unlocked(ndev); 693 mmiowb(); 694 spin_unlock(&priv->lock); 695 return IRQ_HANDLED; 696 } 697 698 /* Error interrupt handler */ 699 static void ravb_error_interrupt(struct net_device *ndev) 700 { 701 struct ravb_private *priv = netdev_priv(ndev); 702 u32 eis, ris2; 703 704 eis = ravb_read(ndev, EIS); 705 ravb_write(ndev, ~EIS_QFS, EIS); 706 if (eis & EIS_QFS) { 707 ris2 = ravb_read(ndev, RIS2); 708 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF), RIS2); 709 710 /* Receive Descriptor Empty int */ 711 if (ris2 & RIS2_QFF0) 712 priv->stats[RAVB_BE].rx_over_errors++; 713 714 /* Receive Descriptor Empty int */ 715 if (ris2 & RIS2_QFF1) 716 priv->stats[RAVB_NC].rx_over_errors++; 717 718 /* Receive FIFO Overflow int */ 719 if (ris2 & RIS2_RFFF) 720 priv->rx_fifo_errors++; 721 } 722 } 723 724 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 725 { 726 struct ravb_private *priv = netdev_priv(ndev); 727 u32 ris0 = ravb_read(ndev, RIS0); 728 u32 ric0 = ravb_read(ndev, RIC0); 729 u32 tis = ravb_read(ndev, TIS); 730 u32 tic = ravb_read(ndev, TIC); 731 732 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 733 if (napi_schedule_prep(&priv->napi[q])) { 734 /* Mask RX and TX interrupts */ 735 if (priv->chip_id == RCAR_GEN2) { 736 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 737 ravb_write(ndev, tic & ~BIT(q), TIC); 738 } else { 739 ravb_write(ndev, BIT(q), RID0); 740 ravb_write(ndev, BIT(q), TID); 741 } 742 __napi_schedule(&priv->napi[q]); 743 } else { 744 netdev_warn(ndev, 745 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 746 ris0, ric0); 747 netdev_warn(ndev, 748 " tx status 0x%08x, tx mask 0x%08x.\n", 749 tis, tic); 750 } 751 return true; 752 } 753 return false; 754 } 755 756 static bool ravb_timestamp_interrupt(struct net_device *ndev) 757 { 758 u32 tis = ravb_read(ndev, TIS); 759 760 if (tis & TIS_TFUF) { 761 ravb_write(ndev, ~TIS_TFUF, TIS); 762 ravb_get_tx_tstamp(ndev); 763 return true; 764 } 765 return false; 766 } 767 768 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 769 { 770 struct net_device *ndev = dev_id; 771 struct ravb_private *priv = netdev_priv(ndev); 772 irqreturn_t result = IRQ_NONE; 773 u32 iss; 774 775 spin_lock(&priv->lock); 776 /* Get interrupt status */ 777 iss = ravb_read(ndev, ISS); 778 779 /* Received and transmitted interrupts */ 780 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 781 int q; 782 783 /* Timestamp updated */ 784 if (ravb_timestamp_interrupt(ndev)) 785 result = IRQ_HANDLED; 786 787 /* Network control and best effort queue RX/TX */ 788 for (q = RAVB_NC; q >= RAVB_BE; q--) { 789 if (ravb_queue_interrupt(ndev, q)) 790 result = IRQ_HANDLED; 791 } 792 } 793 794 /* E-MAC status summary */ 795 if (iss & ISS_MS) { 796 ravb_emac_interrupt_unlocked(ndev); 797 result = IRQ_HANDLED; 798 } 799 800 /* Error status summary */ 801 if (iss & ISS_ES) { 802 ravb_error_interrupt(ndev); 803 result = IRQ_HANDLED; 804 } 805 806 /* gPTP interrupt status summary */ 807 if (iss & ISS_CGIS) { 808 ravb_ptp_interrupt(ndev); 809 result = IRQ_HANDLED; 810 } 811 812 mmiowb(); 813 spin_unlock(&priv->lock); 814 return result; 815 } 816 817 /* Timestamp/Error/gPTP interrupt handler */ 818 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 819 { 820 struct net_device *ndev = dev_id; 821 struct ravb_private *priv = netdev_priv(ndev); 822 irqreturn_t result = IRQ_NONE; 823 u32 iss; 824 825 spin_lock(&priv->lock); 826 /* Get interrupt status */ 827 iss = ravb_read(ndev, ISS); 828 829 /* Timestamp updated */ 830 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 831 result = IRQ_HANDLED; 832 833 /* Error status summary */ 834 if (iss & ISS_ES) { 835 ravb_error_interrupt(ndev); 836 result = IRQ_HANDLED; 837 } 838 839 /* gPTP interrupt status summary */ 840 if (iss & ISS_CGIS) { 841 ravb_ptp_interrupt(ndev); 842 result = IRQ_HANDLED; 843 } 844 845 mmiowb(); 846 spin_unlock(&priv->lock); 847 return result; 848 } 849 850 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 851 { 852 struct net_device *ndev = dev_id; 853 struct ravb_private *priv = netdev_priv(ndev); 854 irqreturn_t result = IRQ_NONE; 855 856 spin_lock(&priv->lock); 857 858 /* Network control/Best effort queue RX/TX */ 859 if (ravb_queue_interrupt(ndev, q)) 860 result = IRQ_HANDLED; 861 862 mmiowb(); 863 spin_unlock(&priv->lock); 864 return result; 865 } 866 867 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 868 { 869 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 870 } 871 872 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 873 { 874 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 875 } 876 877 static int ravb_poll(struct napi_struct *napi, int budget) 878 { 879 struct net_device *ndev = napi->dev; 880 struct ravb_private *priv = netdev_priv(ndev); 881 unsigned long flags; 882 int q = napi - priv->napi; 883 int mask = BIT(q); 884 int quota = budget; 885 u32 ris0, tis; 886 887 for (;;) { 888 tis = ravb_read(ndev, TIS); 889 ris0 = ravb_read(ndev, RIS0); 890 if (!((ris0 & mask) || (tis & mask))) 891 break; 892 893 /* Processing RX Descriptor Ring */ 894 if (ris0 & mask) { 895 /* Clear RX interrupt */ 896 ravb_write(ndev, ~mask, RIS0); 897 if (ravb_rx(ndev, "a, q)) 898 goto out; 899 } 900 /* Processing TX Descriptor Ring */ 901 if (tis & mask) { 902 spin_lock_irqsave(&priv->lock, flags); 903 /* Clear TX interrupt */ 904 ravb_write(ndev, ~mask, TIS); 905 ravb_tx_free(ndev, q); 906 netif_wake_subqueue(ndev, q); 907 mmiowb(); 908 spin_unlock_irqrestore(&priv->lock, flags); 909 } 910 } 911 912 napi_complete(napi); 913 914 /* Re-enable RX/TX interrupts */ 915 spin_lock_irqsave(&priv->lock, flags); 916 if (priv->chip_id == RCAR_GEN2) { 917 ravb_modify(ndev, RIC0, mask, mask); 918 ravb_modify(ndev, TIC, mask, mask); 919 } else { 920 ravb_write(ndev, mask, RIE0); 921 ravb_write(ndev, mask, TIE); 922 } 923 mmiowb(); 924 spin_unlock_irqrestore(&priv->lock, flags); 925 926 /* Receive error message handling */ 927 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 928 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 929 if (priv->rx_over_errors != ndev->stats.rx_over_errors) { 930 ndev->stats.rx_over_errors = priv->rx_over_errors; 931 netif_err(priv, rx_err, ndev, "Receive Descriptor Empty\n"); 932 } 933 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) { 934 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 935 netif_err(priv, rx_err, ndev, "Receive FIFO Overflow\n"); 936 } 937 out: 938 return budget - quota; 939 } 940 941 /* PHY state control function */ 942 static void ravb_adjust_link(struct net_device *ndev) 943 { 944 struct ravb_private *priv = netdev_priv(ndev); 945 struct phy_device *phydev = ndev->phydev; 946 bool new_state = false; 947 948 if (phydev->link) { 949 if (phydev->duplex != priv->duplex) { 950 new_state = true; 951 priv->duplex = phydev->duplex; 952 ravb_set_duplex(ndev); 953 } 954 955 if (phydev->speed != priv->speed) { 956 new_state = true; 957 priv->speed = phydev->speed; 958 ravb_set_rate(ndev); 959 } 960 if (!priv->link) { 961 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 962 new_state = true; 963 priv->link = phydev->link; 964 if (priv->no_avb_link) 965 ravb_rcv_snd_enable(ndev); 966 } 967 } else if (priv->link) { 968 new_state = true; 969 priv->link = 0; 970 priv->speed = 0; 971 priv->duplex = -1; 972 if (priv->no_avb_link) 973 ravb_rcv_snd_disable(ndev); 974 } 975 976 if (new_state && netif_msg_link(priv)) 977 phy_print_status(phydev); 978 } 979 980 /* PHY init function */ 981 static int ravb_phy_init(struct net_device *ndev) 982 { 983 struct device_node *np = ndev->dev.parent->of_node; 984 struct ravb_private *priv = netdev_priv(ndev); 985 struct phy_device *phydev; 986 struct device_node *pn; 987 int err; 988 989 priv->link = 0; 990 priv->speed = 0; 991 priv->duplex = -1; 992 993 /* Try connecting to PHY */ 994 pn = of_parse_phandle(np, "phy-handle", 0); 995 if (!pn) { 996 /* In the case of a fixed PHY, the DT node associated 997 * to the PHY is the Ethernet MAC DT node. 998 */ 999 if (of_phy_is_fixed_link(np)) { 1000 err = of_phy_register_fixed_link(np); 1001 if (err) 1002 return err; 1003 } 1004 pn = of_node_get(np); 1005 } 1006 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, 1007 priv->phy_interface); 1008 of_node_put(pn); 1009 if (!phydev) { 1010 netdev_err(ndev, "failed to connect PHY\n"); 1011 err = -ENOENT; 1012 goto err_deregister_fixed_link; 1013 } 1014 1015 /* This driver only support 10/100Mbit speeds on Gen3 1016 * at this time. 1017 */ 1018 if (priv->chip_id == RCAR_GEN3) { 1019 err = phy_set_max_speed(phydev, SPEED_100); 1020 if (err) { 1021 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n"); 1022 goto err_phy_disconnect; 1023 } 1024 1025 netdev_info(ndev, "limited PHY to 100Mbit/s\n"); 1026 } 1027 1028 /* 10BASE is not supported */ 1029 phydev->supported &= ~PHY_10BT_FEATURES; 1030 1031 phy_attached_info(phydev); 1032 1033 return 0; 1034 1035 err_phy_disconnect: 1036 phy_disconnect(phydev); 1037 err_deregister_fixed_link: 1038 if (of_phy_is_fixed_link(np)) 1039 of_phy_deregister_fixed_link(np); 1040 1041 return err; 1042 } 1043 1044 /* PHY control start function */ 1045 static int ravb_phy_start(struct net_device *ndev) 1046 { 1047 int error; 1048 1049 error = ravb_phy_init(ndev); 1050 if (error) 1051 return error; 1052 1053 phy_start(ndev->phydev); 1054 1055 return 0; 1056 } 1057 1058 static int ravb_get_link_ksettings(struct net_device *ndev, 1059 struct ethtool_link_ksettings *cmd) 1060 { 1061 struct ravb_private *priv = netdev_priv(ndev); 1062 int error = -ENODEV; 1063 unsigned long flags; 1064 1065 if (ndev->phydev) { 1066 spin_lock_irqsave(&priv->lock, flags); 1067 error = phy_ethtool_ksettings_get(ndev->phydev, cmd); 1068 spin_unlock_irqrestore(&priv->lock, flags); 1069 } 1070 1071 return error; 1072 } 1073 1074 static int ravb_set_link_ksettings(struct net_device *ndev, 1075 const struct ethtool_link_ksettings *cmd) 1076 { 1077 struct ravb_private *priv = netdev_priv(ndev); 1078 unsigned long flags; 1079 int error; 1080 1081 if (!ndev->phydev) 1082 return -ENODEV; 1083 1084 spin_lock_irqsave(&priv->lock, flags); 1085 1086 /* Disable TX and RX */ 1087 ravb_rcv_snd_disable(ndev); 1088 1089 error = phy_ethtool_ksettings_set(ndev->phydev, cmd); 1090 if (error) 1091 goto error_exit; 1092 1093 if (cmd->base.duplex == DUPLEX_FULL) 1094 priv->duplex = 1; 1095 else 1096 priv->duplex = 0; 1097 1098 ravb_set_duplex(ndev); 1099 1100 error_exit: 1101 mdelay(1); 1102 1103 /* Enable TX and RX */ 1104 ravb_rcv_snd_enable(ndev); 1105 1106 mmiowb(); 1107 spin_unlock_irqrestore(&priv->lock, flags); 1108 1109 return error; 1110 } 1111 1112 static int ravb_nway_reset(struct net_device *ndev) 1113 { 1114 struct ravb_private *priv = netdev_priv(ndev); 1115 int error = -ENODEV; 1116 unsigned long flags; 1117 1118 if (ndev->phydev) { 1119 spin_lock_irqsave(&priv->lock, flags); 1120 error = phy_start_aneg(ndev->phydev); 1121 spin_unlock_irqrestore(&priv->lock, flags); 1122 } 1123 1124 return error; 1125 } 1126 1127 static u32 ravb_get_msglevel(struct net_device *ndev) 1128 { 1129 struct ravb_private *priv = netdev_priv(ndev); 1130 1131 return priv->msg_enable; 1132 } 1133 1134 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1135 { 1136 struct ravb_private *priv = netdev_priv(ndev); 1137 1138 priv->msg_enable = value; 1139 } 1140 1141 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1142 "rx_queue_0_current", 1143 "tx_queue_0_current", 1144 "rx_queue_0_dirty", 1145 "tx_queue_0_dirty", 1146 "rx_queue_0_packets", 1147 "tx_queue_0_packets", 1148 "rx_queue_0_bytes", 1149 "tx_queue_0_bytes", 1150 "rx_queue_0_mcast_packets", 1151 "rx_queue_0_errors", 1152 "rx_queue_0_crc_errors", 1153 "rx_queue_0_frame_errors", 1154 "rx_queue_0_length_errors", 1155 "rx_queue_0_missed_errors", 1156 "rx_queue_0_over_errors", 1157 1158 "rx_queue_1_current", 1159 "tx_queue_1_current", 1160 "rx_queue_1_dirty", 1161 "tx_queue_1_dirty", 1162 "rx_queue_1_packets", 1163 "tx_queue_1_packets", 1164 "rx_queue_1_bytes", 1165 "tx_queue_1_bytes", 1166 "rx_queue_1_mcast_packets", 1167 "rx_queue_1_errors", 1168 "rx_queue_1_crc_errors", 1169 "rx_queue_1_frame_errors", 1170 "rx_queue_1_length_errors", 1171 "rx_queue_1_missed_errors", 1172 "rx_queue_1_over_errors", 1173 }; 1174 1175 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats) 1176 1177 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1178 { 1179 switch (sset) { 1180 case ETH_SS_STATS: 1181 return RAVB_STATS_LEN; 1182 default: 1183 return -EOPNOTSUPP; 1184 } 1185 } 1186 1187 static void ravb_get_ethtool_stats(struct net_device *ndev, 1188 struct ethtool_stats *stats, u64 *data) 1189 { 1190 struct ravb_private *priv = netdev_priv(ndev); 1191 int i = 0; 1192 int q; 1193 1194 /* Device-specific stats */ 1195 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) { 1196 struct net_device_stats *stats = &priv->stats[q]; 1197 1198 data[i++] = priv->cur_rx[q]; 1199 data[i++] = priv->cur_tx[q]; 1200 data[i++] = priv->dirty_rx[q]; 1201 data[i++] = priv->dirty_tx[q]; 1202 data[i++] = stats->rx_packets; 1203 data[i++] = stats->tx_packets; 1204 data[i++] = stats->rx_bytes; 1205 data[i++] = stats->tx_bytes; 1206 data[i++] = stats->multicast; 1207 data[i++] = stats->rx_errors; 1208 data[i++] = stats->rx_crc_errors; 1209 data[i++] = stats->rx_frame_errors; 1210 data[i++] = stats->rx_length_errors; 1211 data[i++] = stats->rx_missed_errors; 1212 data[i++] = stats->rx_over_errors; 1213 } 1214 } 1215 1216 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1217 { 1218 switch (stringset) { 1219 case ETH_SS_STATS: 1220 memcpy(data, *ravb_gstrings_stats, sizeof(ravb_gstrings_stats)); 1221 break; 1222 } 1223 } 1224 1225 static void ravb_get_ringparam(struct net_device *ndev, 1226 struct ethtool_ringparam *ring) 1227 { 1228 struct ravb_private *priv = netdev_priv(ndev); 1229 1230 ring->rx_max_pending = BE_RX_RING_MAX; 1231 ring->tx_max_pending = BE_TX_RING_MAX; 1232 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1233 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1234 } 1235 1236 static int ravb_set_ringparam(struct net_device *ndev, 1237 struct ethtool_ringparam *ring) 1238 { 1239 struct ravb_private *priv = netdev_priv(ndev); 1240 int error; 1241 1242 if (ring->tx_pending > BE_TX_RING_MAX || 1243 ring->rx_pending > BE_RX_RING_MAX || 1244 ring->tx_pending < BE_TX_RING_MIN || 1245 ring->rx_pending < BE_RX_RING_MIN) 1246 return -EINVAL; 1247 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1248 return -EINVAL; 1249 1250 if (netif_running(ndev)) { 1251 netif_device_detach(ndev); 1252 /* Stop PTP Clock driver */ 1253 if (priv->chip_id == RCAR_GEN2) 1254 ravb_ptp_stop(ndev); 1255 /* Wait for DMA stopping */ 1256 error = ravb_stop_dma(ndev); 1257 if (error) { 1258 netdev_err(ndev, 1259 "cannot set ringparam! Any AVB processes are still running?\n"); 1260 return error; 1261 } 1262 synchronize_irq(ndev->irq); 1263 1264 /* Free all the skb's in the RX queue and the DMA buffers. */ 1265 ravb_ring_free(ndev, RAVB_BE); 1266 ravb_ring_free(ndev, RAVB_NC); 1267 } 1268 1269 /* Set new parameters */ 1270 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1271 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1272 1273 if (netif_running(ndev)) { 1274 error = ravb_dmac_init(ndev); 1275 if (error) { 1276 netdev_err(ndev, 1277 "%s: ravb_dmac_init() failed, error %d\n", 1278 __func__, error); 1279 return error; 1280 } 1281 1282 ravb_emac_init(ndev); 1283 1284 /* Initialise PTP Clock driver */ 1285 if (priv->chip_id == RCAR_GEN2) 1286 ravb_ptp_init(ndev, priv->pdev); 1287 1288 netif_device_attach(ndev); 1289 } 1290 1291 return 0; 1292 } 1293 1294 static int ravb_get_ts_info(struct net_device *ndev, 1295 struct ethtool_ts_info *info) 1296 { 1297 struct ravb_private *priv = netdev_priv(ndev); 1298 1299 info->so_timestamping = 1300 SOF_TIMESTAMPING_TX_SOFTWARE | 1301 SOF_TIMESTAMPING_RX_SOFTWARE | 1302 SOF_TIMESTAMPING_SOFTWARE | 1303 SOF_TIMESTAMPING_TX_HARDWARE | 1304 SOF_TIMESTAMPING_RX_HARDWARE | 1305 SOF_TIMESTAMPING_RAW_HARDWARE; 1306 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1307 info->rx_filters = 1308 (1 << HWTSTAMP_FILTER_NONE) | 1309 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1310 (1 << HWTSTAMP_FILTER_ALL); 1311 info->phc_index = ptp_clock_index(priv->ptp.clock); 1312 1313 return 0; 1314 } 1315 1316 static const struct ethtool_ops ravb_ethtool_ops = { 1317 .nway_reset = ravb_nway_reset, 1318 .get_msglevel = ravb_get_msglevel, 1319 .set_msglevel = ravb_set_msglevel, 1320 .get_link = ethtool_op_get_link, 1321 .get_strings = ravb_get_strings, 1322 .get_ethtool_stats = ravb_get_ethtool_stats, 1323 .get_sset_count = ravb_get_sset_count, 1324 .get_ringparam = ravb_get_ringparam, 1325 .set_ringparam = ravb_set_ringparam, 1326 .get_ts_info = ravb_get_ts_info, 1327 .get_link_ksettings = ravb_get_link_ksettings, 1328 .set_link_ksettings = ravb_set_link_ksettings, 1329 }; 1330 1331 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler, 1332 struct net_device *ndev, struct device *dev, 1333 const char *ch) 1334 { 1335 char *name; 1336 int error; 1337 1338 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); 1339 if (!name) 1340 return -ENOMEM; 1341 error = request_irq(irq, handler, 0, name, ndev); 1342 if (error) 1343 netdev_err(ndev, "cannot request IRQ %s\n", name); 1344 1345 return error; 1346 } 1347 1348 /* Network device open function for Ethernet AVB */ 1349 static int ravb_open(struct net_device *ndev) 1350 { 1351 struct ravb_private *priv = netdev_priv(ndev); 1352 struct platform_device *pdev = priv->pdev; 1353 struct device *dev = &pdev->dev; 1354 int error; 1355 1356 napi_enable(&priv->napi[RAVB_BE]); 1357 napi_enable(&priv->napi[RAVB_NC]); 1358 1359 if (priv->chip_id == RCAR_GEN2) { 1360 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED, 1361 ndev->name, ndev); 1362 if (error) { 1363 netdev_err(ndev, "cannot request IRQ\n"); 1364 goto out_napi_off; 1365 } 1366 } else { 1367 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev, 1368 dev, "ch22:multi"); 1369 if (error) 1370 goto out_napi_off; 1371 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev, 1372 dev, "ch24:emac"); 1373 if (error) 1374 goto out_free_irq; 1375 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt, 1376 ndev, dev, "ch0:rx_be"); 1377 if (error) 1378 goto out_free_irq_emac; 1379 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt, 1380 ndev, dev, "ch18:tx_be"); 1381 if (error) 1382 goto out_free_irq_be_rx; 1383 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt, 1384 ndev, dev, "ch1:rx_nc"); 1385 if (error) 1386 goto out_free_irq_be_tx; 1387 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt, 1388 ndev, dev, "ch19:tx_nc"); 1389 if (error) 1390 goto out_free_irq_nc_rx; 1391 } 1392 1393 /* Device init */ 1394 error = ravb_dmac_init(ndev); 1395 if (error) 1396 goto out_free_irq_nc_tx; 1397 ravb_emac_init(ndev); 1398 1399 /* Initialise PTP Clock driver */ 1400 if (priv->chip_id == RCAR_GEN2) 1401 ravb_ptp_init(ndev, priv->pdev); 1402 1403 netif_tx_start_all_queues(ndev); 1404 1405 /* PHY control start */ 1406 error = ravb_phy_start(ndev); 1407 if (error) 1408 goto out_ptp_stop; 1409 1410 return 0; 1411 1412 out_ptp_stop: 1413 /* Stop PTP Clock driver */ 1414 if (priv->chip_id == RCAR_GEN2) 1415 ravb_ptp_stop(ndev); 1416 out_free_irq_nc_tx: 1417 if (priv->chip_id == RCAR_GEN2) 1418 goto out_free_irq; 1419 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1420 out_free_irq_nc_rx: 1421 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1422 out_free_irq_be_tx: 1423 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1424 out_free_irq_be_rx: 1425 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1426 out_free_irq_emac: 1427 free_irq(priv->emac_irq, ndev); 1428 out_free_irq: 1429 free_irq(ndev->irq, ndev); 1430 out_napi_off: 1431 napi_disable(&priv->napi[RAVB_NC]); 1432 napi_disable(&priv->napi[RAVB_BE]); 1433 return error; 1434 } 1435 1436 /* Timeout function for Ethernet AVB */ 1437 static void ravb_tx_timeout(struct net_device *ndev) 1438 { 1439 struct ravb_private *priv = netdev_priv(ndev); 1440 1441 netif_err(priv, tx_err, ndev, 1442 "transmit timed out, status %08x, resetting...\n", 1443 ravb_read(ndev, ISS)); 1444 1445 /* tx_errors count up */ 1446 ndev->stats.tx_errors++; 1447 1448 schedule_work(&priv->work); 1449 } 1450 1451 static void ravb_tx_timeout_work(struct work_struct *work) 1452 { 1453 struct ravb_private *priv = container_of(work, struct ravb_private, 1454 work); 1455 struct net_device *ndev = priv->ndev; 1456 1457 netif_tx_stop_all_queues(ndev); 1458 1459 /* Stop PTP Clock driver */ 1460 if (priv->chip_id == RCAR_GEN2) 1461 ravb_ptp_stop(ndev); 1462 1463 /* Wait for DMA stopping */ 1464 ravb_stop_dma(ndev); 1465 1466 ravb_ring_free(ndev, RAVB_BE); 1467 ravb_ring_free(ndev, RAVB_NC); 1468 1469 /* Device init */ 1470 ravb_dmac_init(ndev); 1471 ravb_emac_init(ndev); 1472 1473 /* Initialise PTP Clock driver */ 1474 if (priv->chip_id == RCAR_GEN2) 1475 ravb_ptp_init(ndev, priv->pdev); 1476 1477 netif_tx_start_all_queues(ndev); 1478 } 1479 1480 /* Packet transmit function for Ethernet AVB */ 1481 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1482 { 1483 struct ravb_private *priv = netdev_priv(ndev); 1484 u16 q = skb_get_queue_mapping(skb); 1485 struct ravb_tstamp_skb *ts_skb; 1486 struct ravb_tx_desc *desc; 1487 unsigned long flags; 1488 u32 dma_addr; 1489 void *buffer; 1490 u32 entry; 1491 u32 len; 1492 1493 spin_lock_irqsave(&priv->lock, flags); 1494 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 1495 NUM_TX_DESC) { 1496 netif_err(priv, tx_queued, ndev, 1497 "still transmitting with the full ring!\n"); 1498 netif_stop_subqueue(ndev, q); 1499 spin_unlock_irqrestore(&priv->lock, flags); 1500 return NETDEV_TX_BUSY; 1501 } 1502 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC); 1503 priv->tx_skb[q][entry / NUM_TX_DESC] = skb; 1504 1505 if (skb_put_padto(skb, ETH_ZLEN)) 1506 goto drop; 1507 1508 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 1509 entry / NUM_TX_DESC * DPTR_ALIGN; 1510 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 1511 memcpy(buffer, skb->data, len); 1512 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE); 1513 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1514 goto drop; 1515 1516 desc = &priv->tx_ring[q][entry]; 1517 desc->ds_tagl = cpu_to_le16(len); 1518 desc->dptr = cpu_to_le32(dma_addr); 1519 1520 buffer = skb->data + len; 1521 len = skb->len - len; 1522 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE); 1523 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 1524 goto unmap; 1525 1526 desc++; 1527 desc->ds_tagl = cpu_to_le16(len); 1528 desc->dptr = cpu_to_le32(dma_addr); 1529 1530 /* TX timestamp required */ 1531 if (q == RAVB_NC) { 1532 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 1533 if (!ts_skb) { 1534 desc--; 1535 dma_unmap_single(ndev->dev.parent, dma_addr, len, 1536 DMA_TO_DEVICE); 1537 goto unmap; 1538 } 1539 ts_skb->skb = skb; 1540 ts_skb->tag = priv->ts_skb_tag++; 1541 priv->ts_skb_tag &= 0x3ff; 1542 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 1543 1544 /* TAG and timestamp required flag */ 1545 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1546 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 1547 desc->ds_tagl |= le16_to_cpu(ts_skb->tag << 12); 1548 } 1549 1550 skb_tx_timestamp(skb); 1551 /* Descriptor type must be set after all the above writes */ 1552 dma_wmb(); 1553 desc->die_dt = DT_FEND; 1554 desc--; 1555 desc->die_dt = DT_FSTART; 1556 1557 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 1558 1559 priv->cur_tx[q] += NUM_TX_DESC; 1560 if (priv->cur_tx[q] - priv->dirty_tx[q] > 1561 (priv->num_tx_ring[q] - 1) * NUM_TX_DESC && !ravb_tx_free(ndev, q)) 1562 netif_stop_subqueue(ndev, q); 1563 1564 exit: 1565 mmiowb(); 1566 spin_unlock_irqrestore(&priv->lock, flags); 1567 return NETDEV_TX_OK; 1568 1569 unmap: 1570 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 1571 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 1572 drop: 1573 dev_kfree_skb_any(skb); 1574 priv->tx_skb[q][entry / NUM_TX_DESC] = NULL; 1575 goto exit; 1576 } 1577 1578 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 1579 void *accel_priv, select_queue_fallback_t fallback) 1580 { 1581 /* If skb needs TX timestamp, it is handled in network control queue */ 1582 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 1583 RAVB_BE; 1584 1585 } 1586 1587 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 1588 { 1589 struct ravb_private *priv = netdev_priv(ndev); 1590 struct net_device_stats *nstats, *stats0, *stats1; 1591 1592 nstats = &ndev->stats; 1593 stats0 = &priv->stats[RAVB_BE]; 1594 stats1 = &priv->stats[RAVB_NC]; 1595 1596 nstats->tx_dropped += ravb_read(ndev, TROCR); 1597 ravb_write(ndev, 0, TROCR); /* (write clear) */ 1598 nstats->collisions += ravb_read(ndev, CDCR); 1599 ravb_write(ndev, 0, CDCR); /* (write clear) */ 1600 nstats->tx_carrier_errors += ravb_read(ndev, LCCR); 1601 ravb_write(ndev, 0, LCCR); /* (write clear) */ 1602 1603 nstats->tx_carrier_errors += ravb_read(ndev, CERCR); 1604 ravb_write(ndev, 0, CERCR); /* (write clear) */ 1605 nstats->tx_carrier_errors += ravb_read(ndev, CEECR); 1606 ravb_write(ndev, 0, CEECR); /* (write clear) */ 1607 1608 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets; 1609 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets; 1610 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes; 1611 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes; 1612 nstats->multicast = stats0->multicast + stats1->multicast; 1613 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors; 1614 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors; 1615 nstats->rx_frame_errors = 1616 stats0->rx_frame_errors + stats1->rx_frame_errors; 1617 nstats->rx_length_errors = 1618 stats0->rx_length_errors + stats1->rx_length_errors; 1619 nstats->rx_missed_errors = 1620 stats0->rx_missed_errors + stats1->rx_missed_errors; 1621 nstats->rx_over_errors = 1622 stats0->rx_over_errors + stats1->rx_over_errors; 1623 1624 return nstats; 1625 } 1626 1627 /* Update promiscuous bit */ 1628 static void ravb_set_rx_mode(struct net_device *ndev) 1629 { 1630 struct ravb_private *priv = netdev_priv(ndev); 1631 unsigned long flags; 1632 1633 spin_lock_irqsave(&priv->lock, flags); 1634 ravb_modify(ndev, ECMR, ECMR_PRM, 1635 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 1636 mmiowb(); 1637 spin_unlock_irqrestore(&priv->lock, flags); 1638 } 1639 1640 /* Device close function for Ethernet AVB */ 1641 static int ravb_close(struct net_device *ndev) 1642 { 1643 struct device_node *np = ndev->dev.parent->of_node; 1644 struct ravb_private *priv = netdev_priv(ndev); 1645 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 1646 1647 netif_tx_stop_all_queues(ndev); 1648 1649 /* Disable interrupts by clearing the interrupt masks. */ 1650 ravb_write(ndev, 0, RIC0); 1651 ravb_write(ndev, 0, RIC2); 1652 ravb_write(ndev, 0, TIC); 1653 1654 /* Stop PTP Clock driver */ 1655 if (priv->chip_id == RCAR_GEN2) 1656 ravb_ptp_stop(ndev); 1657 1658 /* Set the config mode to stop the AVB-DMAC's processes */ 1659 if (ravb_stop_dma(ndev) < 0) 1660 netdev_err(ndev, 1661 "device will be stopped after h/w processes are done.\n"); 1662 1663 /* Clear the timestamp list */ 1664 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 1665 list_del(&ts_skb->list); 1666 kfree(ts_skb); 1667 } 1668 1669 /* PHY disconnect */ 1670 if (ndev->phydev) { 1671 phy_stop(ndev->phydev); 1672 phy_disconnect(ndev->phydev); 1673 if (of_phy_is_fixed_link(np)) 1674 of_phy_deregister_fixed_link(np); 1675 } 1676 1677 if (priv->chip_id != RCAR_GEN2) { 1678 free_irq(priv->tx_irqs[RAVB_NC], ndev); 1679 free_irq(priv->rx_irqs[RAVB_NC], ndev); 1680 free_irq(priv->tx_irqs[RAVB_BE], ndev); 1681 free_irq(priv->rx_irqs[RAVB_BE], ndev); 1682 free_irq(priv->emac_irq, ndev); 1683 } 1684 free_irq(ndev->irq, ndev); 1685 1686 napi_disable(&priv->napi[RAVB_NC]); 1687 napi_disable(&priv->napi[RAVB_BE]); 1688 1689 /* Free all the skb's in the RX queue and the DMA buffers. */ 1690 ravb_ring_free(ndev, RAVB_BE); 1691 ravb_ring_free(ndev, RAVB_NC); 1692 1693 return 0; 1694 } 1695 1696 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 1697 { 1698 struct ravb_private *priv = netdev_priv(ndev); 1699 struct hwtstamp_config config; 1700 1701 config.flags = 0; 1702 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 1703 HWTSTAMP_TX_OFF; 1704 if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_V2_L2_EVENT) 1705 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 1706 else if (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE_ALL) 1707 config.rx_filter = HWTSTAMP_FILTER_ALL; 1708 else 1709 config.rx_filter = HWTSTAMP_FILTER_NONE; 1710 1711 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1712 -EFAULT : 0; 1713 } 1714 1715 /* Control hardware time stamping */ 1716 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 1717 { 1718 struct ravb_private *priv = netdev_priv(ndev); 1719 struct hwtstamp_config config; 1720 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 1721 u32 tstamp_tx_ctrl; 1722 1723 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 1724 return -EFAULT; 1725 1726 /* Reserved for future extensions */ 1727 if (config.flags) 1728 return -EINVAL; 1729 1730 switch (config.tx_type) { 1731 case HWTSTAMP_TX_OFF: 1732 tstamp_tx_ctrl = 0; 1733 break; 1734 case HWTSTAMP_TX_ON: 1735 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 1736 break; 1737 default: 1738 return -ERANGE; 1739 } 1740 1741 switch (config.rx_filter) { 1742 case HWTSTAMP_FILTER_NONE: 1743 tstamp_rx_ctrl = 0; 1744 break; 1745 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1746 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 1747 break; 1748 default: 1749 config.rx_filter = HWTSTAMP_FILTER_ALL; 1750 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 1751 } 1752 1753 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 1754 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 1755 1756 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 1757 -EFAULT : 0; 1758 } 1759 1760 /* ioctl to device function */ 1761 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 1762 { 1763 struct phy_device *phydev = ndev->phydev; 1764 1765 if (!netif_running(ndev)) 1766 return -EINVAL; 1767 1768 if (!phydev) 1769 return -ENODEV; 1770 1771 switch (cmd) { 1772 case SIOCGHWTSTAMP: 1773 return ravb_hwtstamp_get(ndev, req); 1774 case SIOCSHWTSTAMP: 1775 return ravb_hwtstamp_set(ndev, req); 1776 } 1777 1778 return phy_mii_ioctl(phydev, req, cmd); 1779 } 1780 1781 static const struct net_device_ops ravb_netdev_ops = { 1782 .ndo_open = ravb_open, 1783 .ndo_stop = ravb_close, 1784 .ndo_start_xmit = ravb_start_xmit, 1785 .ndo_select_queue = ravb_select_queue, 1786 .ndo_get_stats = ravb_get_stats, 1787 .ndo_set_rx_mode = ravb_set_rx_mode, 1788 .ndo_tx_timeout = ravb_tx_timeout, 1789 .ndo_do_ioctl = ravb_do_ioctl, 1790 .ndo_validate_addr = eth_validate_addr, 1791 .ndo_set_mac_address = eth_mac_addr, 1792 }; 1793 1794 /* MDIO bus init function */ 1795 static int ravb_mdio_init(struct ravb_private *priv) 1796 { 1797 struct platform_device *pdev = priv->pdev; 1798 struct device *dev = &pdev->dev; 1799 int error; 1800 1801 /* Bitbang init */ 1802 priv->mdiobb.ops = &bb_ops; 1803 1804 /* MII controller setting */ 1805 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 1806 if (!priv->mii_bus) 1807 return -ENOMEM; 1808 1809 /* Hook up MII support for ethtool */ 1810 priv->mii_bus->name = "ravb_mii"; 1811 priv->mii_bus->parent = dev; 1812 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1813 pdev->name, pdev->id); 1814 1815 /* Register MDIO bus */ 1816 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 1817 if (error) 1818 goto out_free_bus; 1819 1820 return 0; 1821 1822 out_free_bus: 1823 free_mdio_bitbang(priv->mii_bus); 1824 return error; 1825 } 1826 1827 /* MDIO bus release function */ 1828 static int ravb_mdio_release(struct ravb_private *priv) 1829 { 1830 /* Unregister mdio bus */ 1831 mdiobus_unregister(priv->mii_bus); 1832 1833 /* Free bitbang info */ 1834 free_mdio_bitbang(priv->mii_bus); 1835 1836 return 0; 1837 } 1838 1839 static const struct of_device_id ravb_match_table[] = { 1840 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 }, 1841 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 }, 1842 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 }, 1843 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 }, 1844 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 }, 1845 { } 1846 }; 1847 MODULE_DEVICE_TABLE(of, ravb_match_table); 1848 1849 static int ravb_set_gti(struct net_device *ndev) 1850 { 1851 1852 struct device *dev = ndev->dev.parent; 1853 struct device_node *np = dev->of_node; 1854 unsigned long rate; 1855 struct clk *clk; 1856 uint64_t inc; 1857 1858 clk = of_clk_get(np, 0); 1859 if (IS_ERR(clk)) { 1860 dev_err(dev, "could not get clock\n"); 1861 return PTR_ERR(clk); 1862 } 1863 1864 rate = clk_get_rate(clk); 1865 clk_put(clk); 1866 1867 if (!rate) 1868 return -EINVAL; 1869 1870 inc = 1000000000ULL << 20; 1871 do_div(inc, rate); 1872 1873 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 1874 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 1875 inc, GTI_TIV_MIN, GTI_TIV_MAX); 1876 return -EINVAL; 1877 } 1878 1879 ravb_write(ndev, inc, GTI); 1880 1881 return 0; 1882 } 1883 1884 static void ravb_set_config_mode(struct net_device *ndev) 1885 { 1886 struct ravb_private *priv = netdev_priv(ndev); 1887 1888 if (priv->chip_id == RCAR_GEN2) { 1889 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG); 1890 /* Set CSEL value */ 1891 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 1892 } else { 1893 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG | 1894 CCC_GAC | CCC_CSEL_HPB); 1895 } 1896 } 1897 1898 static int ravb_probe(struct platform_device *pdev) 1899 { 1900 struct device_node *np = pdev->dev.of_node; 1901 struct ravb_private *priv; 1902 enum ravb_chip_id chip_id; 1903 struct net_device *ndev; 1904 int error, irq, q; 1905 struct resource *res; 1906 int i; 1907 1908 if (!np) { 1909 dev_err(&pdev->dev, 1910 "this driver is required to be instantiated from device tree\n"); 1911 return -EINVAL; 1912 } 1913 1914 /* Get base address */ 1915 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1916 if (!res) { 1917 dev_err(&pdev->dev, "invalid resource\n"); 1918 return -EINVAL; 1919 } 1920 1921 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 1922 NUM_TX_QUEUE, NUM_RX_QUEUE); 1923 if (!ndev) 1924 return -ENOMEM; 1925 1926 pm_runtime_enable(&pdev->dev); 1927 pm_runtime_get_sync(&pdev->dev); 1928 1929 /* The Ether-specific entries in the device structure. */ 1930 ndev->base_addr = res->start; 1931 1932 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev); 1933 1934 if (chip_id == RCAR_GEN3) 1935 irq = platform_get_irq_byname(pdev, "ch22"); 1936 else 1937 irq = platform_get_irq(pdev, 0); 1938 if (irq < 0) { 1939 error = irq; 1940 goto out_release; 1941 } 1942 ndev->irq = irq; 1943 1944 SET_NETDEV_DEV(ndev, &pdev->dev); 1945 1946 priv = netdev_priv(ndev); 1947 priv->ndev = ndev; 1948 priv->pdev = pdev; 1949 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 1950 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 1951 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 1952 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 1953 priv->addr = devm_ioremap_resource(&pdev->dev, res); 1954 if (IS_ERR(priv->addr)) { 1955 error = PTR_ERR(priv->addr); 1956 goto out_release; 1957 } 1958 1959 spin_lock_init(&priv->lock); 1960 INIT_WORK(&priv->work, ravb_tx_timeout_work); 1961 1962 priv->phy_interface = of_get_phy_mode(np); 1963 1964 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 1965 priv->avb_link_active_low = 1966 of_property_read_bool(np, "renesas,ether-link-active-low"); 1967 1968 if (chip_id == RCAR_GEN3) { 1969 irq = platform_get_irq_byname(pdev, "ch24"); 1970 if (irq < 0) { 1971 error = irq; 1972 goto out_release; 1973 } 1974 priv->emac_irq = irq; 1975 for (i = 0; i < NUM_RX_QUEUE; i++) { 1976 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]); 1977 if (irq < 0) { 1978 error = irq; 1979 goto out_release; 1980 } 1981 priv->rx_irqs[i] = irq; 1982 } 1983 for (i = 0; i < NUM_TX_QUEUE; i++) { 1984 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]); 1985 if (irq < 0) { 1986 error = irq; 1987 goto out_release; 1988 } 1989 priv->tx_irqs[i] = irq; 1990 } 1991 } 1992 1993 priv->chip_id = chip_id; 1994 1995 /* Set function */ 1996 ndev->netdev_ops = &ravb_netdev_ops; 1997 ndev->ethtool_ops = &ravb_ethtool_ops; 1998 1999 /* Set AVB config mode */ 2000 ravb_set_config_mode(ndev); 2001 2002 /* Set GTI value */ 2003 error = ravb_set_gti(ndev); 2004 if (error) 2005 goto out_release; 2006 2007 /* Request GTI loading */ 2008 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2009 2010 /* Allocate descriptor base address table */ 2011 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 2012 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 2013 &priv->desc_bat_dma, GFP_KERNEL); 2014 if (!priv->desc_bat) { 2015 dev_err(&pdev->dev, 2016 "Cannot allocate desc base address table (size %d bytes)\n", 2017 priv->desc_bat_size); 2018 error = -ENOMEM; 2019 goto out_release; 2020 } 2021 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 2022 priv->desc_bat[q].die_dt = DT_EOS; 2023 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2024 2025 /* Initialise HW timestamp list */ 2026 INIT_LIST_HEAD(&priv->ts_skb_list); 2027 2028 /* Initialise PTP Clock driver */ 2029 if (chip_id != RCAR_GEN2) 2030 ravb_ptp_init(ndev, pdev); 2031 2032 /* Debug message level */ 2033 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 2034 2035 /* Read and set MAC address */ 2036 ravb_read_mac_address(ndev, of_get_mac_address(np)); 2037 if (!is_valid_ether_addr(ndev->dev_addr)) { 2038 dev_warn(&pdev->dev, 2039 "no valid MAC address supplied, using a random one\n"); 2040 eth_hw_addr_random(ndev); 2041 } 2042 2043 /* MDIO bus init */ 2044 error = ravb_mdio_init(priv); 2045 if (error) { 2046 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 2047 goto out_dma_free; 2048 } 2049 2050 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64); 2051 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64); 2052 2053 /* Network device register */ 2054 error = register_netdev(ndev); 2055 if (error) 2056 goto out_napi_del; 2057 2058 /* Print device information */ 2059 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 2060 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2061 2062 platform_set_drvdata(pdev, ndev); 2063 2064 return 0; 2065 2066 out_napi_del: 2067 netif_napi_del(&priv->napi[RAVB_NC]); 2068 netif_napi_del(&priv->napi[RAVB_BE]); 2069 ravb_mdio_release(priv); 2070 out_dma_free: 2071 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2072 priv->desc_bat_dma); 2073 2074 /* Stop PTP Clock driver */ 2075 if (chip_id != RCAR_GEN2) 2076 ravb_ptp_stop(ndev); 2077 out_release: 2078 if (ndev) 2079 free_netdev(ndev); 2080 2081 pm_runtime_put(&pdev->dev); 2082 pm_runtime_disable(&pdev->dev); 2083 return error; 2084 } 2085 2086 static int ravb_remove(struct platform_device *pdev) 2087 { 2088 struct net_device *ndev = platform_get_drvdata(pdev); 2089 struct ravb_private *priv = netdev_priv(ndev); 2090 2091 /* Stop PTP Clock driver */ 2092 if (priv->chip_id != RCAR_GEN2) 2093 ravb_ptp_stop(ndev); 2094 2095 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2096 priv->desc_bat_dma); 2097 /* Set reset mode */ 2098 ravb_write(ndev, CCC_OPC_RESET, CCC); 2099 pm_runtime_put_sync(&pdev->dev); 2100 unregister_netdev(ndev); 2101 netif_napi_del(&priv->napi[RAVB_NC]); 2102 netif_napi_del(&priv->napi[RAVB_BE]); 2103 ravb_mdio_release(priv); 2104 pm_runtime_disable(&pdev->dev); 2105 free_netdev(ndev); 2106 platform_set_drvdata(pdev, NULL); 2107 2108 return 0; 2109 } 2110 2111 static int __maybe_unused ravb_suspend(struct device *dev) 2112 { 2113 struct net_device *ndev = dev_get_drvdata(dev); 2114 int ret = 0; 2115 2116 if (netif_running(ndev)) { 2117 netif_device_detach(ndev); 2118 ret = ravb_close(ndev); 2119 } 2120 2121 return ret; 2122 } 2123 2124 static int __maybe_unused ravb_resume(struct device *dev) 2125 { 2126 struct net_device *ndev = dev_get_drvdata(dev); 2127 struct ravb_private *priv = netdev_priv(ndev); 2128 int ret = 0; 2129 2130 /* All register have been reset to default values. 2131 * Restore all registers which where setup at probe time and 2132 * reopen device if it was running before system suspended. 2133 */ 2134 2135 /* Set AVB config mode */ 2136 ravb_set_config_mode(ndev); 2137 2138 /* Set GTI value */ 2139 ret = ravb_set_gti(ndev); 2140 if (ret) 2141 return ret; 2142 2143 /* Request GTI loading */ 2144 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 2145 2146 /* Restore descriptor base address table */ 2147 ravb_write(ndev, priv->desc_bat_dma, DBAT); 2148 2149 if (netif_running(ndev)) { 2150 ret = ravb_open(ndev); 2151 if (ret < 0) 2152 return ret; 2153 netif_device_attach(ndev); 2154 } 2155 2156 return ret; 2157 } 2158 2159 static int __maybe_unused ravb_runtime_nop(struct device *dev) 2160 { 2161 /* Runtime PM callback shared between ->runtime_suspend() 2162 * and ->runtime_resume(). Simply returns success. 2163 * 2164 * This driver re-initializes all registers after 2165 * pm_runtime_get_sync() anyway so there is no need 2166 * to save and restore registers here. 2167 */ 2168 return 0; 2169 } 2170 2171 static const struct dev_pm_ops ravb_dev_pm_ops = { 2172 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 2173 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL) 2174 }; 2175 2176 static struct platform_driver ravb_driver = { 2177 .probe = ravb_probe, 2178 .remove = ravb_remove, 2179 .driver = { 2180 .name = "ravb", 2181 .pm = &ravb_dev_pm_ops, 2182 .of_match_table = ravb_match_table, 2183 }, 2184 }; 2185 2186 module_platform_driver(ravb_driver); 2187 2188 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 2189 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 2190 MODULE_LICENSE("GPL v2"); 2191