1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet AVB device driver 3 * 4 * Copyright (C) 2014-2019 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * Based on the SuperH Ethernet driver 9 */ 10 11 #include <linux/cache.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_vlan.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/module.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/of.h> 24 #include <linux/of_mdio.h> 25 #include <linux/of_net.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/slab.h> 29 #include <linux/spinlock.h> 30 #include <linux/reset.h> 31 #include <linux/math64.h> 32 #include <net/ip.h> 33 #include <net/page_pool/helpers.h> 34 35 #include "ravb.h" 36 37 #define RAVB_DEF_MSG_ENABLE \ 38 (NETIF_MSG_LINK | \ 39 NETIF_MSG_TIMER | \ 40 NETIF_MSG_RX_ERR | \ 41 NETIF_MSG_TX_ERR) 42 43 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 44 u32 set) 45 { 46 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 47 } 48 49 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 50 { 51 int i; 52 53 for (i = 0; i < 10000; i++) { 54 if ((ravb_read(ndev, reg) & mask) == value) 55 return 0; 56 udelay(10); 57 } 58 return -ETIMEDOUT; 59 } 60 61 static int ravb_set_opmode(struct net_device *ndev, u32 opmode) 62 { 63 u32 csr_ops = 1U << (opmode & CCC_OPC); 64 u32 ccc_mask = CCC_OPC; 65 int error; 66 67 /* If gPTP active in config mode is supported it needs to be configured 68 * along with CSEL and operating mode in the same access. This is a 69 * hardware limitation. 70 */ 71 if (opmode & CCC_GAC) 72 ccc_mask |= CCC_GAC | CCC_CSEL; 73 74 /* Set operating mode */ 75 ravb_modify(ndev, CCC, ccc_mask, opmode); 76 /* Check if the operating mode is changed to the requested one */ 77 error = ravb_wait(ndev, CSR, CSR_OPS, csr_ops); 78 if (error) { 79 netdev_err(ndev, "failed to switch device to requested mode (%u)\n", 80 opmode & CCC_OPC); 81 } 82 83 return error; 84 } 85 86 static void ravb_set_rate_gbeth(struct net_device *ndev) 87 { 88 struct ravb_private *priv = netdev_priv(ndev); 89 90 switch (priv->speed) { 91 case 10: /* 10BASE */ 92 ravb_write(ndev, GBETH_GECMR_SPEED_10, GECMR); 93 break; 94 case 100: /* 100BASE */ 95 ravb_write(ndev, GBETH_GECMR_SPEED_100, GECMR); 96 break; 97 case 1000: /* 1000BASE */ 98 ravb_write(ndev, GBETH_GECMR_SPEED_1000, GECMR); 99 break; 100 } 101 } 102 103 static void ravb_set_rate_rcar(struct net_device *ndev) 104 { 105 struct ravb_private *priv = netdev_priv(ndev); 106 107 switch (priv->speed) { 108 case 100: /* 100BASE */ 109 ravb_write(ndev, GECMR_SPEED_100, GECMR); 110 break; 111 case 1000: /* 1000BASE */ 112 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 113 break; 114 } 115 } 116 117 /* Get MAC address from the MAC address registers 118 * 119 * Ethernet AVB device doesn't have ROM for MAC address. 120 * This function gets the MAC address that was used by a bootloader. 121 */ 122 static void ravb_read_mac_address(struct device_node *np, 123 struct net_device *ndev) 124 { 125 int ret; 126 127 ret = of_get_ethdev_address(np, ndev); 128 if (ret) { 129 u32 mahr = ravb_read(ndev, MAHR); 130 u32 malr = ravb_read(ndev, MALR); 131 u8 addr[ETH_ALEN]; 132 133 addr[0] = (mahr >> 24) & 0xFF; 134 addr[1] = (mahr >> 16) & 0xFF; 135 addr[2] = (mahr >> 8) & 0xFF; 136 addr[3] = (mahr >> 0) & 0xFF; 137 addr[4] = (malr >> 8) & 0xFF; 138 addr[5] = (malr >> 0) & 0xFF; 139 eth_hw_addr_set(ndev, addr); 140 } 141 } 142 143 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 144 { 145 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 146 mdiobb); 147 148 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 149 } 150 151 /* MDC pin control */ 152 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 153 { 154 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 155 } 156 157 /* Data I/O pin control */ 158 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 159 { 160 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 161 } 162 163 /* Set data bit */ 164 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 165 { 166 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 167 } 168 169 /* Get data bit */ 170 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 171 { 172 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 173 mdiobb); 174 175 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 176 } 177 178 /* MDIO bus control struct */ 179 static const struct mdiobb_ops bb_ops = { 180 .owner = THIS_MODULE, 181 .set_mdc = ravb_set_mdc, 182 .set_mdio_dir = ravb_set_mdio_dir, 183 .set_mdio_data = ravb_set_mdio_data, 184 .get_mdio_data = ravb_get_mdio_data, 185 }; 186 187 static struct ravb_rx_desc * 188 ravb_rx_get_desc(struct ravb_private *priv, unsigned int q, 189 unsigned int i) 190 { 191 return priv->rx_ring[q].raw + priv->info->rx_desc_size * i; 192 } 193 194 /* Free TX skb function for AVB-IP */ 195 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 196 { 197 struct ravb_private *priv = netdev_priv(ndev); 198 struct net_device_stats *stats = &priv->stats[q]; 199 unsigned int num_tx_desc = priv->num_tx_desc; 200 struct ravb_tx_desc *desc; 201 unsigned int entry; 202 int free_num = 0; 203 u32 size; 204 205 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 206 bool txed; 207 208 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 209 num_tx_desc); 210 desc = &priv->tx_ring[q][entry]; 211 txed = desc->die_dt == DT_FEMPTY; 212 if (free_txed_only && !txed) 213 break; 214 /* Descriptor type must be checked before all other reads */ 215 dma_rmb(); 216 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 217 /* Free the original skb. */ 218 if (priv->tx_skb[q][entry / num_tx_desc]) { 219 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 220 size, DMA_TO_DEVICE); 221 /* Last packet descriptor? */ 222 if (entry % num_tx_desc == num_tx_desc - 1) { 223 entry /= num_tx_desc; 224 dev_kfree_skb_any(priv->tx_skb[q][entry]); 225 priv->tx_skb[q][entry] = NULL; 226 if (txed) 227 stats->tx_packets++; 228 } 229 free_num++; 230 } 231 if (txed) 232 stats->tx_bytes += size; 233 desc->die_dt = DT_EEMPTY; 234 } 235 return free_num; 236 } 237 238 static void ravb_rx_ring_free(struct net_device *ndev, int q) 239 { 240 struct ravb_private *priv = netdev_priv(ndev); 241 unsigned int ring_size; 242 243 if (!priv->rx_ring[q].raw) 244 return; 245 246 ring_size = priv->info->rx_desc_size * (priv->num_rx_ring[q] + 1); 247 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q].raw, 248 priv->rx_desc_dma[q]); 249 priv->rx_ring[q].raw = NULL; 250 } 251 252 /* Free skb's and DMA buffers for Ethernet AVB */ 253 static void ravb_ring_free(struct net_device *ndev, int q) 254 { 255 struct ravb_private *priv = netdev_priv(ndev); 256 unsigned int num_tx_desc = priv->num_tx_desc; 257 unsigned int ring_size; 258 unsigned int i; 259 260 ravb_rx_ring_free(ndev, q); 261 262 if (priv->tx_ring[q]) { 263 ravb_tx_free(ndev, q, false); 264 265 ring_size = sizeof(struct ravb_tx_desc) * 266 (priv->num_tx_ring[q] * num_tx_desc + 1); 267 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 268 priv->tx_desc_dma[q]); 269 priv->tx_ring[q] = NULL; 270 } 271 272 /* Free RX buffers */ 273 for (i = 0; i < priv->num_rx_ring[q]; i++) { 274 if (priv->rx_buffers[q][i].page) 275 page_pool_put_page(priv->rx_pool[q], 276 priv->rx_buffers[q][i].page, 277 0, true); 278 } 279 kfree(priv->rx_buffers[q]); 280 priv->rx_buffers[q] = NULL; 281 page_pool_destroy(priv->rx_pool[q]); 282 283 /* Free aligned TX buffers */ 284 kfree(priv->tx_align[q]); 285 priv->tx_align[q] = NULL; 286 287 /* Free TX skb ringbuffer. 288 * SKBs are freed by ravb_tx_free() call above. 289 */ 290 kfree(priv->tx_skb[q]); 291 priv->tx_skb[q] = NULL; 292 } 293 294 static int 295 ravb_alloc_rx_buffer(struct net_device *ndev, int q, u32 entry, gfp_t gfp_mask, 296 struct ravb_rx_desc *rx_desc) 297 { 298 struct ravb_private *priv = netdev_priv(ndev); 299 const struct ravb_hw_info *info = priv->info; 300 struct ravb_rx_buffer *rx_buff; 301 dma_addr_t dma_addr; 302 unsigned int size; 303 304 rx_buff = &priv->rx_buffers[q][entry]; 305 size = info->rx_buffer_size; 306 rx_buff->page = page_pool_alloc(priv->rx_pool[q], &rx_buff->offset, 307 &size, gfp_mask); 308 if (unlikely(!rx_buff->page)) { 309 /* We just set the data size to 0 for a failed mapping which 310 * should prevent DMA from happening... 311 */ 312 rx_desc->ds_cc = cpu_to_le16(0); 313 return -ENOMEM; 314 } 315 316 dma_addr = page_pool_get_dma_addr(rx_buff->page) + rx_buff->offset; 317 dma_sync_single_for_device(ndev->dev.parent, dma_addr, 318 info->rx_buffer_size, DMA_FROM_DEVICE); 319 rx_desc->dptr = cpu_to_le32(dma_addr); 320 321 /* The end of the RX buffer is used to store skb shared data, so we need 322 * to ensure that the hardware leaves enough space for this. 323 */ 324 rx_desc->ds_cc = cpu_to_le16(info->rx_buffer_size - 325 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) - 326 ETH_FCS_LEN + sizeof(__sum16)); 327 return 0; 328 } 329 330 static u32 331 ravb_rx_ring_refill(struct net_device *ndev, int q, u32 count, gfp_t gfp_mask) 332 { 333 struct ravb_private *priv = netdev_priv(ndev); 334 struct ravb_rx_desc *rx_desc; 335 u32 i, entry; 336 337 for (i = 0; i < count; i++) { 338 entry = (priv->dirty_rx[q] + i) % priv->num_rx_ring[q]; 339 rx_desc = ravb_rx_get_desc(priv, q, entry); 340 341 if (!priv->rx_buffers[q][entry].page) { 342 if (unlikely(ravb_alloc_rx_buffer(ndev, q, entry, 343 gfp_mask, rx_desc))) 344 break; 345 } 346 /* Descriptor type must be set after all the above writes */ 347 dma_wmb(); 348 rx_desc->die_dt = DT_FEMPTY; 349 } 350 351 return i; 352 } 353 354 /* Format skb and descriptor buffer for Ethernet AVB */ 355 static void ravb_ring_format(struct net_device *ndev, int q) 356 { 357 struct ravb_private *priv = netdev_priv(ndev); 358 unsigned int num_tx_desc = priv->num_tx_desc; 359 struct ravb_rx_desc *rx_desc; 360 struct ravb_tx_desc *tx_desc; 361 struct ravb_desc *desc; 362 unsigned int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 363 num_tx_desc; 364 unsigned int i; 365 366 priv->cur_rx[q] = 0; 367 priv->cur_tx[q] = 0; 368 priv->dirty_rx[q] = 0; 369 priv->dirty_tx[q] = 0; 370 371 /* Regular RX descriptors have already been initialized by 372 * ravb_rx_ring_refill(), we just need to initialize the final link 373 * descriptor. 374 */ 375 rx_desc = ravb_rx_get_desc(priv, q, priv->num_rx_ring[q]); 376 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 377 rx_desc->die_dt = DT_LINKFIX; /* type */ 378 379 memset(priv->tx_ring[q], 0, tx_ring_size); 380 /* Build TX ring buffer */ 381 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 382 i++, tx_desc++) { 383 tx_desc->die_dt = DT_EEMPTY; 384 if (num_tx_desc > 1) { 385 tx_desc++; 386 tx_desc->die_dt = DT_EEMPTY; 387 } 388 } 389 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 390 tx_desc->die_dt = DT_LINKFIX; /* type */ 391 392 /* RX descriptor base address for best effort */ 393 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 394 desc->die_dt = DT_LINKFIX; /* type */ 395 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 396 397 /* TX descriptor base address for best effort */ 398 desc = &priv->desc_bat[q]; 399 desc->die_dt = DT_LINKFIX; /* type */ 400 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 401 } 402 403 static void *ravb_alloc_rx_desc(struct net_device *ndev, int q) 404 { 405 struct ravb_private *priv = netdev_priv(ndev); 406 unsigned int ring_size; 407 408 ring_size = priv->info->rx_desc_size * (priv->num_rx_ring[q] + 1); 409 410 priv->rx_ring[q].raw = dma_alloc_coherent(ndev->dev.parent, ring_size, 411 &priv->rx_desc_dma[q], 412 GFP_KERNEL); 413 414 return priv->rx_ring[q].raw; 415 } 416 417 /* Init skb and descriptor buffer for Ethernet AVB */ 418 static int ravb_ring_init(struct net_device *ndev, int q) 419 { 420 struct ravb_private *priv = netdev_priv(ndev); 421 unsigned int num_tx_desc = priv->num_tx_desc; 422 struct page_pool_params params = { 423 .order = 0, 424 .flags = PP_FLAG_DMA_MAP, 425 .pool_size = priv->num_rx_ring[q], 426 .nid = NUMA_NO_NODE, 427 .dev = ndev->dev.parent, 428 .dma_dir = DMA_FROM_DEVICE, 429 }; 430 unsigned int ring_size; 431 u32 num_filled; 432 433 /* Allocate RX page pool and buffers */ 434 priv->rx_pool[q] = page_pool_create(¶ms); 435 if (IS_ERR(priv->rx_pool[q])) 436 goto error; 437 438 /* Allocate RX buffers */ 439 priv->rx_buffers[q] = kcalloc(priv->num_rx_ring[q], 440 sizeof(*priv->rx_buffers[q]), GFP_KERNEL); 441 if (!priv->rx_buffers[q]) 442 goto error; 443 444 /* Allocate TX skb rings */ 445 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 446 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 447 if (!priv->tx_skb[q]) 448 goto error; 449 450 /* Allocate all RX descriptors. */ 451 if (!ravb_alloc_rx_desc(ndev, q)) 452 goto error; 453 454 /* Populate RX ring buffer. */ 455 priv->dirty_rx[q] = 0; 456 ring_size = priv->info->rx_desc_size * priv->num_rx_ring[q]; 457 memset(priv->rx_ring[q].raw, 0, ring_size); 458 num_filled = ravb_rx_ring_refill(ndev, q, priv->num_rx_ring[q], 459 GFP_KERNEL); 460 if (num_filled != priv->num_rx_ring[q]) 461 goto error; 462 463 if (num_tx_desc > 1) { 464 /* Allocate rings for the aligned buffers */ 465 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 466 DPTR_ALIGN - 1, GFP_KERNEL); 467 if (!priv->tx_align[q]) 468 goto error; 469 } 470 471 /* Allocate all TX descriptors. */ 472 ring_size = sizeof(struct ravb_tx_desc) * 473 (priv->num_tx_ring[q] * num_tx_desc + 1); 474 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 475 &priv->tx_desc_dma[q], 476 GFP_KERNEL); 477 if (!priv->tx_ring[q]) 478 goto error; 479 480 return 0; 481 482 error: 483 ravb_ring_free(ndev, q); 484 485 return -ENOMEM; 486 } 487 488 static void ravb_csum_init_gbeth(struct net_device *ndev) 489 { 490 bool tx_enable = ndev->features & NETIF_F_HW_CSUM; 491 bool rx_enable = ndev->features & NETIF_F_RXCSUM; 492 493 if (!(tx_enable || rx_enable)) 494 goto done; 495 496 ravb_write(ndev, 0, CSR0); 497 if (ravb_wait(ndev, CSR0, CSR0_TPE | CSR0_RPE, 0)) { 498 netdev_err(ndev, "Timeout enabling hardware checksum\n"); 499 500 if (tx_enable) 501 ndev->features &= ~NETIF_F_HW_CSUM; 502 503 if (rx_enable) 504 ndev->features &= ~NETIF_F_RXCSUM; 505 } else { 506 if (tx_enable) 507 ravb_write(ndev, CSR1_TIP4 | CSR1_TTCP4 | CSR1_TUDP4, CSR1); 508 509 if (rx_enable) 510 ravb_write(ndev, CSR2_RIP4 | CSR2_RTCP4 | CSR2_RUDP4 | CSR2_RICMP4, 511 CSR2); 512 } 513 514 done: 515 ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0); 516 } 517 518 static void ravb_emac_init_gbeth(struct net_device *ndev) 519 { 520 struct ravb_private *priv = netdev_priv(ndev); 521 522 if (priv->phy_interface == PHY_INTERFACE_MODE_MII) { 523 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35); 524 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0); 525 } else { 526 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_RGMII, CXR35); 527 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 528 CXR31_SEL_LINK0); 529 } 530 531 /* Receive frame limit set register */ 532 ravb_write(ndev, priv->info->rx_max_frame_size + ETH_FCS_LEN, RFLR); 533 534 /* EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through */ 535 ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) | 536 ECMR_TE | ECMR_RE | ECMR_RCPT | 537 ECMR_TXF | ECMR_RXF, ECMR); 538 539 ravb_set_rate_gbeth(ndev); 540 541 /* Set MAC address */ 542 ravb_write(ndev, 543 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 544 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 545 ravb_write(ndev, (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 546 547 /* E-MAC status register clear */ 548 ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR); 549 550 ravb_csum_init_gbeth(ndev); 551 552 /* E-MAC interrupt enable register */ 553 ravb_write(ndev, ECSIPR_ICDIP, ECSIPR); 554 } 555 556 static void ravb_emac_init_rcar(struct net_device *ndev) 557 { 558 /* Receive frame limit set register */ 559 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 560 561 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 562 ravb_write(ndev, ECMR_ZPF | ECMR_DM | 563 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 564 ECMR_TE | ECMR_RE, ECMR); 565 566 ravb_set_rate_rcar(ndev); 567 568 /* Set MAC address */ 569 ravb_write(ndev, 570 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 571 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 572 ravb_write(ndev, 573 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 574 575 /* E-MAC status register clear */ 576 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 577 578 /* E-MAC interrupt enable register */ 579 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 580 } 581 582 /* E-MAC init function */ 583 static void ravb_emac_init(struct net_device *ndev) 584 { 585 struct ravb_private *priv = netdev_priv(ndev); 586 const struct ravb_hw_info *info = priv->info; 587 588 info->emac_init(ndev); 589 } 590 591 static int ravb_dmac_init_gbeth(struct net_device *ndev) 592 { 593 struct ravb_private *priv = netdev_priv(ndev); 594 int error; 595 596 error = ravb_ring_init(ndev, RAVB_BE); 597 if (error) 598 return error; 599 600 /* Descriptor format */ 601 ravb_ring_format(ndev, RAVB_BE); 602 603 /* Set DMAC RX */ 604 ravb_write(ndev, 0x60000000, RCR); 605 606 /* Set Max Frame Length (RTC) */ 607 ravb_write(ndev, 0x7ffc0000 | priv->info->rx_max_frame_size, RTC); 608 609 /* Set FIFO size */ 610 ravb_write(ndev, 0x00222200, TGC); 611 612 ravb_write(ndev, 0, TCCR); 613 614 /* Frame receive */ 615 ravb_write(ndev, RIC0_FRE0, RIC0); 616 /* Disable FIFO full warning */ 617 ravb_write(ndev, 0x0, RIC1); 618 /* Receive FIFO full error, descriptor empty */ 619 ravb_write(ndev, RIC2_QFE0 | RIC2_RFFE, RIC2); 620 621 ravb_write(ndev, TIC_FTE0, TIC); 622 623 return 0; 624 } 625 626 static int ravb_dmac_init_rcar(struct net_device *ndev) 627 { 628 struct ravb_private *priv = netdev_priv(ndev); 629 const struct ravb_hw_info *info = priv->info; 630 int error; 631 632 error = ravb_ring_init(ndev, RAVB_BE); 633 if (error) 634 return error; 635 error = ravb_ring_init(ndev, RAVB_NC); 636 if (error) { 637 ravb_ring_free(ndev, RAVB_BE); 638 return error; 639 } 640 641 /* Descriptor format */ 642 ravb_ring_format(ndev, RAVB_BE); 643 ravb_ring_format(ndev, RAVB_NC); 644 645 /* Set AVB RX */ 646 ravb_write(ndev, 647 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 648 649 /* Set FIFO size */ 650 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC); 651 652 /* Timestamp enable */ 653 ravb_write(ndev, TCCR_TFEN, TCCR); 654 655 /* Interrupt init: */ 656 if (info->multi_irqs) { 657 /* Clear DIL.DPLx */ 658 ravb_write(ndev, 0, DIL); 659 /* Set queue specific interrupt */ 660 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 661 } 662 /* Frame receive */ 663 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 664 /* Disable FIFO full warning */ 665 ravb_write(ndev, 0, RIC1); 666 /* Receive FIFO full error, descriptor empty */ 667 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 668 /* Frame transmitted, timestamp FIFO updated */ 669 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 670 671 return 0; 672 } 673 674 /* Device init function for Ethernet AVB */ 675 static int ravb_dmac_init(struct net_device *ndev) 676 { 677 struct ravb_private *priv = netdev_priv(ndev); 678 const struct ravb_hw_info *info = priv->info; 679 int error; 680 681 /* Set CONFIG mode */ 682 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 683 if (error) 684 return error; 685 686 error = info->dmac_init(ndev); 687 if (error) 688 return error; 689 690 /* Setting the control will start the AVB-DMAC process. */ 691 return ravb_set_opmode(ndev, CCC_OPC_OPERATION); 692 } 693 694 static void ravb_get_tx_tstamp(struct net_device *ndev) 695 { 696 struct ravb_private *priv = netdev_priv(ndev); 697 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 698 struct skb_shared_hwtstamps shhwtstamps; 699 struct sk_buff *skb; 700 struct timespec64 ts; 701 u16 tag, tfa_tag; 702 int count; 703 u32 tfa2; 704 705 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 706 while (count--) { 707 tfa2 = ravb_read(ndev, TFA2); 708 tfa_tag = (tfa2 & TFA2_TST) >> 16; 709 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 710 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 711 ravb_read(ndev, TFA1); 712 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 713 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 714 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 715 list) { 716 skb = ts_skb->skb; 717 tag = ts_skb->tag; 718 list_del(&ts_skb->list); 719 kfree(ts_skb); 720 if (tag == tfa_tag) { 721 skb_tstamp_tx(skb, &shhwtstamps); 722 dev_consume_skb_any(skb); 723 break; 724 } else { 725 dev_kfree_skb_any(skb); 726 } 727 } 728 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 729 } 730 } 731 732 static void ravb_rx_csum_gbeth(struct sk_buff *skb) 733 { 734 struct skb_shared_info *shinfo = skb_shinfo(skb); 735 __wsum csum_ip_hdr, csum_proto; 736 skb_frag_t *last_frag; 737 u8 *hw_csum; 738 739 /* The hardware checksum status is contained in sizeof(__sum16) * 2 = 4 740 * bytes appended to packet data. First 2 bytes is ip header checksum 741 * and last 2 bytes is protocol checksum. 742 */ 743 if (unlikely(skb->len < sizeof(__sum16) * 2)) 744 return; 745 746 if (skb_is_nonlinear(skb)) { 747 last_frag = &shinfo->frags[shinfo->nr_frags - 1]; 748 hw_csum = skb_frag_address(last_frag) + 749 skb_frag_size(last_frag); 750 } else { 751 hw_csum = skb_tail_pointer(skb); 752 } 753 754 hw_csum -= sizeof(__sum16); 755 csum_proto = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 756 757 hw_csum -= sizeof(__sum16); 758 csum_ip_hdr = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 759 760 if (skb_is_nonlinear(skb)) 761 skb_frag_size_sub(last_frag, 2 * sizeof(__sum16)); 762 else 763 skb_trim(skb, skb->len - 2 * sizeof(__sum16)); 764 765 /* TODO: IPV6 Rx checksum */ 766 if (skb->protocol == htons(ETH_P_IP) && !csum_ip_hdr && !csum_proto) 767 skb->ip_summed = CHECKSUM_UNNECESSARY; 768 } 769 770 static void ravb_rx_csum(struct sk_buff *skb) 771 { 772 u8 *hw_csum; 773 774 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes 775 * appended to packet data 776 */ 777 if (unlikely(skb->len < sizeof(__sum16))) 778 return; 779 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); 780 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 781 skb->ip_summed = CHECKSUM_COMPLETE; 782 skb_trim(skb, skb->len - sizeof(__sum16)); 783 } 784 785 /* Packet receive function for Gigabit Ethernet */ 786 static int ravb_rx_gbeth(struct net_device *ndev, int budget, int q) 787 { 788 struct ravb_private *priv = netdev_priv(ndev); 789 const struct ravb_hw_info *info = priv->info; 790 struct net_device_stats *stats; 791 struct ravb_rx_desc *desc; 792 struct sk_buff *skb; 793 int rx_packets = 0; 794 u8 desc_status; 795 u16 desc_len; 796 u8 die_dt; 797 int entry; 798 int limit; 799 int i; 800 801 limit = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q]; 802 stats = &priv->stats[q]; 803 804 for (i = 0; i < limit; i++, priv->cur_rx[q]++) { 805 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 806 desc = &priv->rx_ring[q].desc[entry]; 807 if (rx_packets == budget || desc->die_dt == DT_FEMPTY) 808 break; 809 810 /* Descriptor type must be checked before all other reads */ 811 dma_rmb(); 812 desc_status = desc->msc; 813 desc_len = le16_to_cpu(desc->ds_cc) & RX_DS; 814 815 /* We use 0-byte descriptors to mark the DMA mapping errors */ 816 if (!desc_len) 817 continue; 818 819 if (desc_status & MSC_MC) 820 stats->multicast++; 821 822 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | MSC_CEEF)) { 823 stats->rx_errors++; 824 if (desc_status & MSC_CRC) 825 stats->rx_crc_errors++; 826 if (desc_status & MSC_RFE) 827 stats->rx_frame_errors++; 828 if (desc_status & (MSC_RTLF | MSC_RTSF)) 829 stats->rx_length_errors++; 830 if (desc_status & MSC_CEEF) 831 stats->rx_missed_errors++; 832 } else { 833 struct ravb_rx_buffer *rx_buff; 834 void *rx_addr; 835 836 rx_buff = &priv->rx_buffers[q][entry]; 837 rx_addr = page_address(rx_buff->page) + rx_buff->offset; 838 die_dt = desc->die_dt & 0xF0; 839 dma_sync_single_for_cpu(ndev->dev.parent, 840 le32_to_cpu(desc->dptr), 841 desc_len, DMA_FROM_DEVICE); 842 843 switch (die_dt) { 844 case DT_FSINGLE: 845 case DT_FSTART: 846 /* Start of packet: Set initial data length. */ 847 skb = napi_build_skb(rx_addr, 848 info->rx_buffer_size); 849 if (unlikely(!skb)) { 850 stats->rx_errors++; 851 page_pool_put_page(priv->rx_pool[q], 852 rx_buff->page, 0, 853 true); 854 goto refill; 855 } 856 skb_mark_for_recycle(skb); 857 skb_put(skb, desc_len); 858 859 /* Save this skb if the packet spans multiple 860 * descriptors. 861 */ 862 if (die_dt == DT_FSTART) 863 priv->rx_1st_skb = skb; 864 break; 865 866 case DT_FMID: 867 case DT_FEND: 868 /* Continuing a packet: Add this buffer as an RX 869 * frag. 870 */ 871 872 /* rx_1st_skb will be NULL if napi_build_skb() 873 * failed for the first descriptor of a 874 * multi-descriptor packet. 875 */ 876 if (unlikely(!priv->rx_1st_skb)) { 877 stats->rx_errors++; 878 page_pool_put_page(priv->rx_pool[q], 879 rx_buff->page, 0, 880 true); 881 882 /* We may find a DT_FSINGLE or DT_FSTART 883 * descriptor in the queue which we can 884 * process, so don't give up yet. 885 */ 886 continue; 887 } 888 skb_add_rx_frag(priv->rx_1st_skb, 889 skb_shinfo(priv->rx_1st_skb)->nr_frags, 890 rx_buff->page, rx_buff->offset, 891 desc_len, info->rx_buffer_size); 892 893 /* Set skb to point at the whole packet so that 894 * we only need one code path for finishing a 895 * packet. 896 */ 897 skb = priv->rx_1st_skb; 898 } 899 900 switch (die_dt) { 901 case DT_FSINGLE: 902 case DT_FEND: 903 /* Finishing a packet: Determine protocol & 904 * checksum, hand off to NAPI and update our 905 * stats. 906 */ 907 skb->protocol = eth_type_trans(skb, ndev); 908 if (ndev->features & NETIF_F_RXCSUM) 909 ravb_rx_csum_gbeth(skb); 910 stats->rx_bytes += skb->len; 911 napi_gro_receive(&priv->napi[q], skb); 912 rx_packets++; 913 914 /* Clear rx_1st_skb so that it will only be 915 * non-NULL when valid. 916 */ 917 priv->rx_1st_skb = NULL; 918 } 919 920 /* Mark this RX buffer as consumed. */ 921 rx_buff->page = NULL; 922 } 923 } 924 925 refill: 926 /* Refill the RX ring buffers. */ 927 priv->dirty_rx[q] += ravb_rx_ring_refill(ndev, q, 928 priv->cur_rx[q] - priv->dirty_rx[q], 929 GFP_ATOMIC); 930 931 stats->rx_packets += rx_packets; 932 return rx_packets; 933 } 934 935 /* Packet receive function for Ethernet AVB */ 936 static int ravb_rx_rcar(struct net_device *ndev, int budget, int q) 937 { 938 struct ravb_private *priv = netdev_priv(ndev); 939 const struct ravb_hw_info *info = priv->info; 940 struct net_device_stats *stats = &priv->stats[q]; 941 struct ravb_ex_rx_desc *desc; 942 unsigned int limit, i; 943 struct sk_buff *skb; 944 struct timespec64 ts; 945 int rx_packets = 0; 946 u8 desc_status; 947 u16 pkt_len; 948 int entry; 949 950 limit = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q]; 951 for (i = 0; i < limit; i++, priv->cur_rx[q]++) { 952 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 953 desc = &priv->rx_ring[q].ex_desc[entry]; 954 if (rx_packets == budget || desc->die_dt == DT_FEMPTY) 955 break; 956 957 /* Descriptor type must be checked before all other reads */ 958 dma_rmb(); 959 desc_status = desc->msc; 960 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 961 962 /* We use 0-byte descriptors to mark the DMA mapping errors */ 963 if (!pkt_len) 964 continue; 965 966 if (desc_status & MSC_MC) 967 stats->multicast++; 968 969 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 970 MSC_CEEF)) { 971 stats->rx_errors++; 972 if (desc_status & MSC_CRC) 973 stats->rx_crc_errors++; 974 if (desc_status & MSC_RFE) 975 stats->rx_frame_errors++; 976 if (desc_status & (MSC_RTLF | MSC_RTSF)) 977 stats->rx_length_errors++; 978 if (desc_status & MSC_CEEF) 979 stats->rx_missed_errors++; 980 } else { 981 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 982 struct ravb_rx_buffer *rx_buff; 983 void *rx_addr; 984 985 rx_buff = &priv->rx_buffers[q][entry]; 986 rx_addr = page_address(rx_buff->page) + rx_buff->offset; 987 dma_sync_single_for_cpu(ndev->dev.parent, 988 le32_to_cpu(desc->dptr), 989 pkt_len, DMA_FROM_DEVICE); 990 991 skb = napi_build_skb(rx_addr, info->rx_buffer_size); 992 if (unlikely(!skb)) { 993 stats->rx_errors++; 994 page_pool_put_page(priv->rx_pool[q], 995 rx_buff->page, 0, true); 996 break; 997 } 998 skb_mark_for_recycle(skb); 999 get_ts &= (q == RAVB_NC) ? 1000 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 1001 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 1002 if (get_ts) { 1003 struct skb_shared_hwtstamps *shhwtstamps; 1004 1005 shhwtstamps = skb_hwtstamps(skb); 1006 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 1007 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 1008 32) | le32_to_cpu(desc->ts_sl); 1009 ts.tv_nsec = le32_to_cpu(desc->ts_n); 1010 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 1011 } 1012 1013 skb_put(skb, pkt_len); 1014 skb->protocol = eth_type_trans(skb, ndev); 1015 if (ndev->features & NETIF_F_RXCSUM) 1016 ravb_rx_csum(skb); 1017 napi_gro_receive(&priv->napi[q], skb); 1018 rx_packets++; 1019 stats->rx_bytes += pkt_len; 1020 1021 /* Mark this RX buffer as consumed. */ 1022 rx_buff->page = NULL; 1023 } 1024 } 1025 1026 /* Refill the RX ring buffers. */ 1027 priv->dirty_rx[q] += ravb_rx_ring_refill(ndev, q, 1028 priv->cur_rx[q] - priv->dirty_rx[q], 1029 GFP_ATOMIC); 1030 1031 stats->rx_packets += rx_packets; 1032 return rx_packets; 1033 } 1034 1035 /* Packet receive function for Ethernet AVB */ 1036 static int ravb_rx(struct net_device *ndev, int budget, int q) 1037 { 1038 struct ravb_private *priv = netdev_priv(ndev); 1039 const struct ravb_hw_info *info = priv->info; 1040 1041 return info->receive(ndev, budget, q); 1042 } 1043 1044 static void ravb_rcv_snd_disable(struct net_device *ndev) 1045 { 1046 /* Disable TX and RX */ 1047 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 1048 } 1049 1050 static void ravb_rcv_snd_enable(struct net_device *ndev) 1051 { 1052 /* Enable TX and RX */ 1053 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 1054 } 1055 1056 /* function for waiting dma process finished */ 1057 static int ravb_stop_dma(struct net_device *ndev) 1058 { 1059 struct ravb_private *priv = netdev_priv(ndev); 1060 const struct ravb_hw_info *info = priv->info; 1061 int error; 1062 1063 /* Wait for stopping the hardware TX process */ 1064 error = ravb_wait(ndev, TCCR, info->tccr_mask, 0); 1065 1066 if (error) 1067 return error; 1068 1069 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 1070 0); 1071 if (error) 1072 return error; 1073 1074 /* Stop the E-MAC's RX/TX processes. */ 1075 ravb_rcv_snd_disable(ndev); 1076 1077 /* Wait for stopping the RX DMA process */ 1078 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 1079 if (error) 1080 return error; 1081 1082 /* Stop AVB-DMAC process */ 1083 return ravb_set_opmode(ndev, CCC_OPC_CONFIG); 1084 } 1085 1086 /* E-MAC interrupt handler */ 1087 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 1088 { 1089 struct ravb_private *priv = netdev_priv(ndev); 1090 u32 ecsr, psr; 1091 1092 ecsr = ravb_read(ndev, ECSR); 1093 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 1094 1095 if (ecsr & ECSR_MPD) 1096 pm_wakeup_event(&priv->pdev->dev, 0); 1097 if (ecsr & ECSR_ICD) 1098 ndev->stats.tx_carrier_errors++; 1099 if (ecsr & ECSR_LCHNG) { 1100 /* Link changed */ 1101 if (priv->no_avb_link) 1102 return; 1103 psr = ravb_read(ndev, PSR); 1104 if (priv->avb_link_active_low) 1105 psr ^= PSR_LMON; 1106 if (!(psr & PSR_LMON)) { 1107 /* DIsable RX and TX */ 1108 ravb_rcv_snd_disable(ndev); 1109 } else { 1110 /* Enable RX and TX */ 1111 ravb_rcv_snd_enable(ndev); 1112 } 1113 } 1114 } 1115 1116 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 1117 { 1118 struct net_device *ndev = dev_id; 1119 struct ravb_private *priv = netdev_priv(ndev); 1120 struct device *dev = &priv->pdev->dev; 1121 irqreturn_t result = IRQ_HANDLED; 1122 1123 pm_runtime_get_noresume(dev); 1124 1125 if (unlikely(!pm_runtime_active(dev))) { 1126 result = IRQ_NONE; 1127 goto out_rpm_put; 1128 } 1129 1130 spin_lock(&priv->lock); 1131 ravb_emac_interrupt_unlocked(ndev); 1132 spin_unlock(&priv->lock); 1133 1134 out_rpm_put: 1135 pm_runtime_put_noidle(dev); 1136 return result; 1137 } 1138 1139 /* Error interrupt handler */ 1140 static void ravb_error_interrupt(struct net_device *ndev) 1141 { 1142 struct ravb_private *priv = netdev_priv(ndev); 1143 u32 eis, ris2; 1144 1145 eis = ravb_read(ndev, EIS); 1146 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS); 1147 if (eis & EIS_QFS) { 1148 ris2 = ravb_read(ndev, RIS2); 1149 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_QFF1 | RIS2_RFFF | RIS2_RESERVED), 1150 RIS2); 1151 1152 /* Receive Descriptor Empty int */ 1153 if (ris2 & RIS2_QFF0) 1154 priv->stats[RAVB_BE].rx_over_errors++; 1155 1156 /* Receive Descriptor Empty int */ 1157 if (ris2 & RIS2_QFF1) 1158 priv->stats[RAVB_NC].rx_over_errors++; 1159 1160 /* Receive FIFO Overflow int */ 1161 if (ris2 & RIS2_RFFF) 1162 priv->rx_fifo_errors++; 1163 } 1164 } 1165 1166 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 1167 { 1168 struct ravb_private *priv = netdev_priv(ndev); 1169 const struct ravb_hw_info *info = priv->info; 1170 u32 ris0 = ravb_read(ndev, RIS0); 1171 u32 ric0 = ravb_read(ndev, RIC0); 1172 u32 tis = ravb_read(ndev, TIS); 1173 u32 tic = ravb_read(ndev, TIC); 1174 1175 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 1176 if (napi_schedule_prep(&priv->napi[q])) { 1177 /* Mask RX and TX interrupts */ 1178 if (!info->irq_en_dis) { 1179 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 1180 ravb_write(ndev, tic & ~BIT(q), TIC); 1181 } else { 1182 ravb_write(ndev, BIT(q), RID0); 1183 ravb_write(ndev, BIT(q), TID); 1184 } 1185 __napi_schedule(&priv->napi[q]); 1186 } else { 1187 netdev_warn(ndev, 1188 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 1189 ris0, ric0); 1190 netdev_warn(ndev, 1191 " tx status 0x%08x, tx mask 0x%08x.\n", 1192 tis, tic); 1193 } 1194 return true; 1195 } 1196 return false; 1197 } 1198 1199 static bool ravb_timestamp_interrupt(struct net_device *ndev) 1200 { 1201 u32 tis = ravb_read(ndev, TIS); 1202 1203 if (tis & TIS_TFUF) { 1204 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS); 1205 ravb_get_tx_tstamp(ndev); 1206 return true; 1207 } 1208 return false; 1209 } 1210 1211 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 1212 { 1213 struct net_device *ndev = dev_id; 1214 struct ravb_private *priv = netdev_priv(ndev); 1215 const struct ravb_hw_info *info = priv->info; 1216 struct device *dev = &priv->pdev->dev; 1217 irqreturn_t result = IRQ_NONE; 1218 u32 iss; 1219 1220 pm_runtime_get_noresume(dev); 1221 1222 if (unlikely(!pm_runtime_active(dev))) 1223 goto out_rpm_put; 1224 1225 spin_lock(&priv->lock); 1226 /* Get interrupt status */ 1227 iss = ravb_read(ndev, ISS); 1228 1229 /* Received and transmitted interrupts */ 1230 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 1231 int q; 1232 1233 /* Timestamp updated */ 1234 if (ravb_timestamp_interrupt(ndev)) 1235 result = IRQ_HANDLED; 1236 1237 /* Network control and best effort queue RX/TX */ 1238 if (info->nc_queues) { 1239 for (q = RAVB_NC; q >= RAVB_BE; q--) { 1240 if (ravb_queue_interrupt(ndev, q)) 1241 result = IRQ_HANDLED; 1242 } 1243 } else { 1244 if (ravb_queue_interrupt(ndev, RAVB_BE)) 1245 result = IRQ_HANDLED; 1246 } 1247 } 1248 1249 /* E-MAC status summary */ 1250 if (iss & ISS_MS) { 1251 ravb_emac_interrupt_unlocked(ndev); 1252 result = IRQ_HANDLED; 1253 } 1254 1255 /* Error status summary */ 1256 if (iss & ISS_ES) { 1257 ravb_error_interrupt(ndev); 1258 result = IRQ_HANDLED; 1259 } 1260 1261 /* gPTP interrupt status summary */ 1262 if (iss & ISS_CGIS) { 1263 ravb_ptp_interrupt(ndev); 1264 result = IRQ_HANDLED; 1265 } 1266 1267 spin_unlock(&priv->lock); 1268 1269 out_rpm_put: 1270 pm_runtime_put_noidle(dev); 1271 return result; 1272 } 1273 1274 /* Timestamp/Error/gPTP interrupt handler */ 1275 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 1276 { 1277 struct net_device *ndev = dev_id; 1278 struct ravb_private *priv = netdev_priv(ndev); 1279 struct device *dev = &priv->pdev->dev; 1280 irqreturn_t result = IRQ_NONE; 1281 u32 iss; 1282 1283 pm_runtime_get_noresume(dev); 1284 1285 if (unlikely(!pm_runtime_active(dev))) 1286 goto out_rpm_put; 1287 1288 spin_lock(&priv->lock); 1289 /* Get interrupt status */ 1290 iss = ravb_read(ndev, ISS); 1291 1292 /* Timestamp updated */ 1293 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 1294 result = IRQ_HANDLED; 1295 1296 /* Error status summary */ 1297 if (iss & ISS_ES) { 1298 ravb_error_interrupt(ndev); 1299 result = IRQ_HANDLED; 1300 } 1301 1302 /* gPTP interrupt status summary */ 1303 if (iss & ISS_CGIS) { 1304 ravb_ptp_interrupt(ndev); 1305 result = IRQ_HANDLED; 1306 } 1307 1308 spin_unlock(&priv->lock); 1309 1310 out_rpm_put: 1311 pm_runtime_put_noidle(dev); 1312 return result; 1313 } 1314 1315 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 1316 { 1317 struct net_device *ndev = dev_id; 1318 struct ravb_private *priv = netdev_priv(ndev); 1319 struct device *dev = &priv->pdev->dev; 1320 irqreturn_t result = IRQ_NONE; 1321 1322 pm_runtime_get_noresume(dev); 1323 1324 if (unlikely(!pm_runtime_active(dev))) 1325 goto out_rpm_put; 1326 1327 spin_lock(&priv->lock); 1328 1329 /* Network control/Best effort queue RX/TX */ 1330 if (ravb_queue_interrupt(ndev, q)) 1331 result = IRQ_HANDLED; 1332 1333 spin_unlock(&priv->lock); 1334 1335 out_rpm_put: 1336 pm_runtime_put_noidle(dev); 1337 return result; 1338 } 1339 1340 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 1341 { 1342 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 1343 } 1344 1345 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 1346 { 1347 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 1348 } 1349 1350 static int ravb_poll(struct napi_struct *napi, int budget) 1351 { 1352 struct net_device *ndev = napi->dev; 1353 struct ravb_private *priv = netdev_priv(ndev); 1354 const struct ravb_hw_info *info = priv->info; 1355 unsigned long flags; 1356 int q = napi - priv->napi; 1357 int mask = BIT(q); 1358 int work_done; 1359 1360 /* Processing RX Descriptor Ring */ 1361 /* Clear RX interrupt */ 1362 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0); 1363 work_done = ravb_rx(ndev, budget, q); 1364 1365 /* Processing TX Descriptor Ring */ 1366 spin_lock_irqsave(&priv->lock, flags); 1367 /* Clear TX interrupt */ 1368 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS); 1369 ravb_tx_free(ndev, q, true); 1370 netif_wake_subqueue(ndev, q); 1371 spin_unlock_irqrestore(&priv->lock, flags); 1372 1373 /* Receive error message handling */ 1374 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 1375 if (info->nc_queues) 1376 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 1377 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 1378 ndev->stats.rx_over_errors = priv->rx_over_errors; 1379 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 1380 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 1381 1382 if (work_done < budget && napi_complete_done(napi, work_done)) { 1383 /* Re-enable RX/TX interrupts */ 1384 spin_lock_irqsave(&priv->lock, flags); 1385 if (!info->irq_en_dis) { 1386 ravb_modify(ndev, RIC0, mask, mask); 1387 ravb_modify(ndev, TIC, mask, mask); 1388 } else { 1389 ravb_write(ndev, mask, RIE0); 1390 ravb_write(ndev, mask, TIE); 1391 } 1392 spin_unlock_irqrestore(&priv->lock, flags); 1393 } 1394 1395 return work_done; 1396 } 1397 1398 static void ravb_set_duplex_gbeth(struct net_device *ndev) 1399 { 1400 struct ravb_private *priv = netdev_priv(ndev); 1401 1402 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex > 0 ? ECMR_DM : 0); 1403 } 1404 1405 /* PHY state control function */ 1406 static void ravb_adjust_link(struct net_device *ndev) 1407 { 1408 struct ravb_private *priv = netdev_priv(ndev); 1409 const struct ravb_hw_info *info = priv->info; 1410 struct phy_device *phydev = ndev->phydev; 1411 bool new_state = false; 1412 unsigned long flags; 1413 1414 spin_lock_irqsave(&priv->lock, flags); 1415 1416 /* Disable TX and RX right over here, if E-MAC change is ignored */ 1417 if (priv->no_avb_link) 1418 ravb_rcv_snd_disable(ndev); 1419 1420 if (phydev->link) { 1421 if (info->half_duplex && phydev->duplex != priv->duplex) { 1422 new_state = true; 1423 priv->duplex = phydev->duplex; 1424 ravb_set_duplex_gbeth(ndev); 1425 } 1426 1427 if (phydev->speed != priv->speed) { 1428 new_state = true; 1429 priv->speed = phydev->speed; 1430 info->set_rate(ndev); 1431 } 1432 if (!priv->link) { 1433 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 1434 new_state = true; 1435 priv->link = phydev->link; 1436 } 1437 } else if (priv->link) { 1438 new_state = true; 1439 priv->link = 0; 1440 priv->speed = 0; 1441 if (info->half_duplex) 1442 priv->duplex = -1; 1443 } 1444 1445 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1446 if (priv->no_avb_link && phydev->link) 1447 ravb_rcv_snd_enable(ndev); 1448 1449 spin_unlock_irqrestore(&priv->lock, flags); 1450 1451 if (new_state && netif_msg_link(priv)) 1452 phy_print_status(phydev); 1453 } 1454 1455 /* PHY init function */ 1456 static int ravb_phy_init(struct net_device *ndev) 1457 { 1458 struct device_node *np = ndev->dev.parent->of_node; 1459 struct ravb_private *priv = netdev_priv(ndev); 1460 const struct ravb_hw_info *info = priv->info; 1461 struct phy_device *phydev; 1462 struct device_node *pn; 1463 phy_interface_t iface; 1464 int err; 1465 1466 priv->link = 0; 1467 priv->speed = 0; 1468 priv->duplex = -1; 1469 1470 /* Try connecting to PHY */ 1471 pn = of_parse_phandle(np, "phy-handle", 0); 1472 if (!pn) { 1473 /* In the case of a fixed PHY, the DT node associated 1474 * to the PHY is the Ethernet MAC DT node. 1475 */ 1476 if (of_phy_is_fixed_link(np)) { 1477 err = of_phy_register_fixed_link(np); 1478 if (err) 1479 return err; 1480 } 1481 pn = of_node_get(np); 1482 } 1483 1484 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII 1485 : priv->phy_interface; 1486 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface); 1487 of_node_put(pn); 1488 if (!phydev) { 1489 netdev_err(ndev, "failed to connect PHY\n"); 1490 err = -ENOENT; 1491 goto err_deregister_fixed_link; 1492 } 1493 1494 if (!info->half_duplex) { 1495 /* 10BASE, Pause and Asym Pause is not supported */ 1496 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1497 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1498 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT); 1499 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 1500 1501 /* Half Duplex is not supported */ 1502 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1503 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1504 } 1505 1506 phy_attached_info(phydev); 1507 1508 return 0; 1509 1510 err_deregister_fixed_link: 1511 if (of_phy_is_fixed_link(np)) 1512 of_phy_deregister_fixed_link(np); 1513 1514 return err; 1515 } 1516 1517 /* PHY control start function */ 1518 static int ravb_phy_start(struct net_device *ndev) 1519 { 1520 int error; 1521 1522 error = ravb_phy_init(ndev); 1523 if (error) 1524 return error; 1525 1526 phy_start(ndev->phydev); 1527 1528 return 0; 1529 } 1530 1531 static u32 ravb_get_msglevel(struct net_device *ndev) 1532 { 1533 struct ravb_private *priv = netdev_priv(ndev); 1534 1535 return priv->msg_enable; 1536 } 1537 1538 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1539 { 1540 struct ravb_private *priv = netdev_priv(ndev); 1541 1542 priv->msg_enable = value; 1543 } 1544 1545 static const char ravb_gstrings_stats_gbeth[][ETH_GSTRING_LEN] = { 1546 "rx_queue_0_current", 1547 "tx_queue_0_current", 1548 "rx_queue_0_dirty", 1549 "tx_queue_0_dirty", 1550 "rx_queue_0_packets", 1551 "tx_queue_0_packets", 1552 "rx_queue_0_bytes", 1553 "tx_queue_0_bytes", 1554 "rx_queue_0_mcast_packets", 1555 "rx_queue_0_errors", 1556 "rx_queue_0_crc_errors", 1557 "rx_queue_0_frame_errors", 1558 "rx_queue_0_length_errors", 1559 "rx_queue_0_csum_offload_errors", 1560 "rx_queue_0_over_errors", 1561 }; 1562 1563 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1564 "rx_queue_0_current", 1565 "tx_queue_0_current", 1566 "rx_queue_0_dirty", 1567 "tx_queue_0_dirty", 1568 "rx_queue_0_packets", 1569 "tx_queue_0_packets", 1570 "rx_queue_0_bytes", 1571 "tx_queue_0_bytes", 1572 "rx_queue_0_mcast_packets", 1573 "rx_queue_0_errors", 1574 "rx_queue_0_crc_errors", 1575 "rx_queue_0_frame_errors", 1576 "rx_queue_0_length_errors", 1577 "rx_queue_0_missed_errors", 1578 "rx_queue_0_over_errors", 1579 1580 "rx_queue_1_current", 1581 "tx_queue_1_current", 1582 "rx_queue_1_dirty", 1583 "tx_queue_1_dirty", 1584 "rx_queue_1_packets", 1585 "tx_queue_1_packets", 1586 "rx_queue_1_bytes", 1587 "tx_queue_1_bytes", 1588 "rx_queue_1_mcast_packets", 1589 "rx_queue_1_errors", 1590 "rx_queue_1_crc_errors", 1591 "rx_queue_1_frame_errors", 1592 "rx_queue_1_length_errors", 1593 "rx_queue_1_missed_errors", 1594 "rx_queue_1_over_errors", 1595 }; 1596 1597 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1598 { 1599 struct ravb_private *priv = netdev_priv(netdev); 1600 const struct ravb_hw_info *info = priv->info; 1601 1602 switch (sset) { 1603 case ETH_SS_STATS: 1604 return info->stats_len; 1605 default: 1606 return -EOPNOTSUPP; 1607 } 1608 } 1609 1610 static void ravb_get_ethtool_stats(struct net_device *ndev, 1611 struct ethtool_stats *estats, u64 *data) 1612 { 1613 struct ravb_private *priv = netdev_priv(ndev); 1614 const struct ravb_hw_info *info = priv->info; 1615 int num_rx_q; 1616 int i = 0; 1617 int q; 1618 1619 num_rx_q = info->nc_queues ? NUM_RX_QUEUE : 1; 1620 /* Device-specific stats */ 1621 for (q = RAVB_BE; q < num_rx_q; q++) { 1622 struct net_device_stats *stats = &priv->stats[q]; 1623 1624 data[i++] = priv->cur_rx[q]; 1625 data[i++] = priv->cur_tx[q]; 1626 data[i++] = priv->dirty_rx[q]; 1627 data[i++] = priv->dirty_tx[q]; 1628 data[i++] = stats->rx_packets; 1629 data[i++] = stats->tx_packets; 1630 data[i++] = stats->rx_bytes; 1631 data[i++] = stats->tx_bytes; 1632 data[i++] = stats->multicast; 1633 data[i++] = stats->rx_errors; 1634 data[i++] = stats->rx_crc_errors; 1635 data[i++] = stats->rx_frame_errors; 1636 data[i++] = stats->rx_length_errors; 1637 data[i++] = stats->rx_missed_errors; 1638 data[i++] = stats->rx_over_errors; 1639 } 1640 } 1641 1642 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1643 { 1644 struct ravb_private *priv = netdev_priv(ndev); 1645 const struct ravb_hw_info *info = priv->info; 1646 1647 switch (stringset) { 1648 case ETH_SS_STATS: 1649 memcpy(data, info->gstrings_stats, info->gstrings_size); 1650 break; 1651 } 1652 } 1653 1654 static void ravb_get_ringparam(struct net_device *ndev, 1655 struct ethtool_ringparam *ring, 1656 struct kernel_ethtool_ringparam *kernel_ring, 1657 struct netlink_ext_ack *extack) 1658 { 1659 struct ravb_private *priv = netdev_priv(ndev); 1660 1661 ring->rx_max_pending = BE_RX_RING_MAX; 1662 ring->tx_max_pending = BE_TX_RING_MAX; 1663 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1664 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1665 } 1666 1667 static int ravb_set_ringparam(struct net_device *ndev, 1668 struct ethtool_ringparam *ring, 1669 struct kernel_ethtool_ringparam *kernel_ring, 1670 struct netlink_ext_ack *extack) 1671 { 1672 struct ravb_private *priv = netdev_priv(ndev); 1673 const struct ravb_hw_info *info = priv->info; 1674 int error; 1675 1676 if (ring->tx_pending > BE_TX_RING_MAX || 1677 ring->rx_pending > BE_RX_RING_MAX || 1678 ring->tx_pending < BE_TX_RING_MIN || 1679 ring->rx_pending < BE_RX_RING_MIN) 1680 return -EINVAL; 1681 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1682 return -EINVAL; 1683 1684 if (netif_running(ndev)) { 1685 netif_device_detach(ndev); 1686 /* Stop PTP Clock driver */ 1687 if (info->gptp) 1688 ravb_ptp_stop(ndev); 1689 /* Wait for DMA stopping */ 1690 error = ravb_stop_dma(ndev); 1691 if (error) { 1692 netdev_err(ndev, 1693 "cannot set ringparam! Any AVB processes are still running?\n"); 1694 return error; 1695 } 1696 synchronize_irq(ndev->irq); 1697 1698 /* Free all the skb's in the RX queue and the DMA buffers. */ 1699 ravb_ring_free(ndev, RAVB_BE); 1700 if (info->nc_queues) 1701 ravb_ring_free(ndev, RAVB_NC); 1702 } 1703 1704 /* Set new parameters */ 1705 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1706 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1707 1708 if (netif_running(ndev)) { 1709 error = ravb_dmac_init(ndev); 1710 if (error) { 1711 netdev_err(ndev, 1712 "%s: ravb_dmac_init() failed, error %d\n", 1713 __func__, error); 1714 return error; 1715 } 1716 1717 ravb_emac_init(ndev); 1718 1719 /* Initialise PTP Clock driver */ 1720 if (info->gptp) 1721 ravb_ptp_init(ndev, priv->pdev); 1722 1723 netif_device_attach(ndev); 1724 } 1725 1726 return 0; 1727 } 1728 1729 static int ravb_get_ts_info(struct net_device *ndev, 1730 struct ethtool_ts_info *info) 1731 { 1732 struct ravb_private *priv = netdev_priv(ndev); 1733 const struct ravb_hw_info *hw_info = priv->info; 1734 1735 info->so_timestamping = 1736 SOF_TIMESTAMPING_TX_SOFTWARE | 1737 SOF_TIMESTAMPING_RX_SOFTWARE | 1738 SOF_TIMESTAMPING_SOFTWARE | 1739 SOF_TIMESTAMPING_TX_HARDWARE | 1740 SOF_TIMESTAMPING_RX_HARDWARE | 1741 SOF_TIMESTAMPING_RAW_HARDWARE; 1742 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1743 info->rx_filters = 1744 (1 << HWTSTAMP_FILTER_NONE) | 1745 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1746 (1 << HWTSTAMP_FILTER_ALL); 1747 if (hw_info->gptp || hw_info->ccc_gac) 1748 info->phc_index = ptp_clock_index(priv->ptp.clock); 1749 1750 return 0; 1751 } 1752 1753 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1754 { 1755 struct ravb_private *priv = netdev_priv(ndev); 1756 1757 wol->supported = WAKE_MAGIC; 1758 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1759 } 1760 1761 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1762 { 1763 struct ravb_private *priv = netdev_priv(ndev); 1764 const struct ravb_hw_info *info = priv->info; 1765 1766 if (!info->magic_pkt || (wol->wolopts & ~WAKE_MAGIC)) 1767 return -EOPNOTSUPP; 1768 1769 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1770 1771 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1772 1773 return 0; 1774 } 1775 1776 static const struct ethtool_ops ravb_ethtool_ops = { 1777 .nway_reset = phy_ethtool_nway_reset, 1778 .get_msglevel = ravb_get_msglevel, 1779 .set_msglevel = ravb_set_msglevel, 1780 .get_link = ethtool_op_get_link, 1781 .get_strings = ravb_get_strings, 1782 .get_ethtool_stats = ravb_get_ethtool_stats, 1783 .get_sset_count = ravb_get_sset_count, 1784 .get_ringparam = ravb_get_ringparam, 1785 .set_ringparam = ravb_set_ringparam, 1786 .get_ts_info = ravb_get_ts_info, 1787 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1788 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1789 .get_wol = ravb_get_wol, 1790 .set_wol = ravb_set_wol, 1791 }; 1792 1793 static int ravb_set_config_mode(struct net_device *ndev) 1794 { 1795 struct ravb_private *priv = netdev_priv(ndev); 1796 const struct ravb_hw_info *info = priv->info; 1797 int error; 1798 1799 if (info->gptp) { 1800 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 1801 if (error) 1802 return error; 1803 /* Set CSEL value */ 1804 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 1805 } else if (info->ccc_gac) { 1806 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG | CCC_GAC | CCC_CSEL_HPB); 1807 } else { 1808 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 1809 } 1810 1811 return error; 1812 } 1813 1814 static void ravb_set_gti(struct net_device *ndev) 1815 { 1816 struct ravb_private *priv = netdev_priv(ndev); 1817 const struct ravb_hw_info *info = priv->info; 1818 1819 if (!(info->gptp || info->ccc_gac)) 1820 return; 1821 1822 ravb_write(ndev, priv->gti_tiv, GTI); 1823 1824 /* Request GTI loading */ 1825 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 1826 } 1827 1828 static int ravb_compute_gti(struct net_device *ndev) 1829 { 1830 struct ravb_private *priv = netdev_priv(ndev); 1831 const struct ravb_hw_info *info = priv->info; 1832 struct device *dev = ndev->dev.parent; 1833 unsigned long rate; 1834 u64 inc; 1835 1836 if (!(info->gptp || info->ccc_gac)) 1837 return 0; 1838 1839 if (info->gptp_ref_clk) 1840 rate = clk_get_rate(priv->gptp_clk); 1841 else 1842 rate = clk_get_rate(priv->clk); 1843 if (!rate) 1844 return -EINVAL; 1845 1846 inc = div64_ul(1000000000ULL << 20, rate); 1847 1848 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 1849 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 1850 inc, GTI_TIV_MIN, GTI_TIV_MAX); 1851 return -EINVAL; 1852 } 1853 priv->gti_tiv = inc; 1854 1855 return 0; 1856 } 1857 1858 /* Set tx and rx clock internal delay modes */ 1859 static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev) 1860 { 1861 struct ravb_private *priv = netdev_priv(ndev); 1862 bool explicit_delay = false; 1863 u32 delay; 1864 1865 if (!priv->info->internal_delay) 1866 return; 1867 1868 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) { 1869 /* Valid values are 0 and 1800, according to DT bindings */ 1870 priv->rxcidm = !!delay; 1871 explicit_delay = true; 1872 } 1873 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) { 1874 /* Valid values are 0 and 2000, according to DT bindings */ 1875 priv->txcidm = !!delay; 1876 explicit_delay = true; 1877 } 1878 1879 if (explicit_delay) 1880 return; 1881 1882 /* Fall back to legacy rgmii-*id behavior */ 1883 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1884 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) { 1885 priv->rxcidm = 1; 1886 priv->rgmii_override = 1; 1887 } 1888 1889 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1890 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) { 1891 priv->txcidm = 1; 1892 priv->rgmii_override = 1; 1893 } 1894 } 1895 1896 static void ravb_set_delay_mode(struct net_device *ndev) 1897 { 1898 struct ravb_private *priv = netdev_priv(ndev); 1899 u32 set = 0; 1900 1901 if (!priv->info->internal_delay) 1902 return; 1903 1904 if (priv->rxcidm) 1905 set |= APSR_RDM; 1906 if (priv->txcidm) 1907 set |= APSR_TDM; 1908 ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set); 1909 } 1910 1911 /* Network device open function for Ethernet AVB */ 1912 static int ravb_open(struct net_device *ndev) 1913 { 1914 struct ravb_private *priv = netdev_priv(ndev); 1915 const struct ravb_hw_info *info = priv->info; 1916 struct device *dev = &priv->pdev->dev; 1917 int error; 1918 1919 napi_enable(&priv->napi[RAVB_BE]); 1920 if (info->nc_queues) 1921 napi_enable(&priv->napi[RAVB_NC]); 1922 1923 error = pm_runtime_resume_and_get(dev); 1924 if (error < 0) 1925 goto out_napi_off; 1926 1927 /* Set AVB config mode */ 1928 error = ravb_set_config_mode(ndev); 1929 if (error) 1930 goto out_rpm_put; 1931 1932 ravb_set_delay_mode(ndev); 1933 ravb_write(ndev, priv->desc_bat_dma, DBAT); 1934 1935 /* Device init */ 1936 error = ravb_dmac_init(ndev); 1937 if (error) 1938 goto out_set_reset; 1939 1940 ravb_emac_init(ndev); 1941 1942 ravb_set_gti(ndev); 1943 1944 /* Initialise PTP Clock driver */ 1945 if (info->gptp || info->ccc_gac) 1946 ravb_ptp_init(ndev, priv->pdev); 1947 1948 /* PHY control start */ 1949 error = ravb_phy_start(ndev); 1950 if (error) 1951 goto out_ptp_stop; 1952 1953 netif_tx_start_all_queues(ndev); 1954 1955 return 0; 1956 1957 out_ptp_stop: 1958 /* Stop PTP Clock driver */ 1959 if (info->gptp || info->ccc_gac) 1960 ravb_ptp_stop(ndev); 1961 ravb_stop_dma(ndev); 1962 out_set_reset: 1963 ravb_set_opmode(ndev, CCC_OPC_RESET); 1964 out_rpm_put: 1965 pm_runtime_mark_last_busy(dev); 1966 pm_runtime_put_autosuspend(dev); 1967 out_napi_off: 1968 if (info->nc_queues) 1969 napi_disable(&priv->napi[RAVB_NC]); 1970 napi_disable(&priv->napi[RAVB_BE]); 1971 return error; 1972 } 1973 1974 /* Timeout function for Ethernet AVB */ 1975 static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1976 { 1977 struct ravb_private *priv = netdev_priv(ndev); 1978 1979 netif_err(priv, tx_err, ndev, 1980 "transmit timed out, status %08x, resetting...\n", 1981 ravb_read(ndev, ISS)); 1982 1983 /* tx_errors count up */ 1984 ndev->stats.tx_errors++; 1985 1986 schedule_work(&priv->work); 1987 } 1988 1989 static void ravb_tx_timeout_work(struct work_struct *work) 1990 { 1991 struct ravb_private *priv = container_of(work, struct ravb_private, 1992 work); 1993 const struct ravb_hw_info *info = priv->info; 1994 struct net_device *ndev = priv->ndev; 1995 int error; 1996 1997 if (!rtnl_trylock()) { 1998 usleep_range(1000, 2000); 1999 schedule_work(&priv->work); 2000 return; 2001 } 2002 2003 netif_tx_stop_all_queues(ndev); 2004 2005 /* Stop PTP Clock driver */ 2006 if (info->gptp) 2007 ravb_ptp_stop(ndev); 2008 2009 /* Wait for DMA stopping */ 2010 if (ravb_stop_dma(ndev)) { 2011 /* If ravb_stop_dma() fails, the hardware is still operating 2012 * for TX and/or RX. So, this should not call the following 2013 * functions because ravb_dmac_init() is possible to fail too. 2014 * Also, this should not retry ravb_stop_dma() again and again 2015 * here because it's possible to wait forever. So, this just 2016 * re-enables the TX and RX and skip the following 2017 * re-initialization procedure. 2018 */ 2019 ravb_rcv_snd_enable(ndev); 2020 goto out; 2021 } 2022 2023 ravb_ring_free(ndev, RAVB_BE); 2024 if (info->nc_queues) 2025 ravb_ring_free(ndev, RAVB_NC); 2026 2027 /* Device init */ 2028 error = ravb_dmac_init(ndev); 2029 if (error) { 2030 /* If ravb_dmac_init() fails, descriptors are freed. So, this 2031 * should return here to avoid re-enabling the TX and RX in 2032 * ravb_emac_init(). 2033 */ 2034 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n", 2035 __func__, error); 2036 goto out_unlock; 2037 } 2038 ravb_emac_init(ndev); 2039 2040 out: 2041 /* Initialise PTP Clock driver */ 2042 if (info->gptp) 2043 ravb_ptp_init(ndev, priv->pdev); 2044 2045 netif_tx_start_all_queues(ndev); 2046 2047 out_unlock: 2048 rtnl_unlock(); 2049 } 2050 2051 static bool ravb_can_tx_csum_gbeth(struct sk_buff *skb) 2052 { 2053 struct iphdr *ip = ip_hdr(skb); 2054 2055 /* TODO: Need to add support for VLAN tag 802.1Q */ 2056 if (skb_vlan_tag_present(skb)) 2057 return false; 2058 2059 /* TODO: Need to add hardware checksum for IPv6 */ 2060 if (skb->protocol != htons(ETH_P_IP)) 2061 return false; 2062 2063 switch (ip->protocol) { 2064 case IPPROTO_TCP: 2065 break; 2066 case IPPROTO_UDP: 2067 /* If the checksum value in the UDP header field is 0, TOE does 2068 * not calculate checksum for UDP part of this frame as it is 2069 * optional function as per standards. 2070 */ 2071 if (udp_hdr(skb)->check == 0) 2072 return false; 2073 break; 2074 default: 2075 return false; 2076 } 2077 2078 return true; 2079 } 2080 2081 /* Packet transmit function for Ethernet AVB */ 2082 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 2083 { 2084 struct ravb_private *priv = netdev_priv(ndev); 2085 const struct ravb_hw_info *info = priv->info; 2086 unsigned int num_tx_desc = priv->num_tx_desc; 2087 u16 q = skb_get_queue_mapping(skb); 2088 struct ravb_tstamp_skb *ts_skb; 2089 struct ravb_tx_desc *desc; 2090 unsigned long flags; 2091 dma_addr_t dma_addr; 2092 void *buffer; 2093 u32 entry; 2094 u32 len; 2095 2096 if (skb->ip_summed == CHECKSUM_PARTIAL && !ravb_can_tx_csum_gbeth(skb)) 2097 skb_checksum_help(skb); 2098 2099 spin_lock_irqsave(&priv->lock, flags); 2100 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 2101 num_tx_desc) { 2102 netif_err(priv, tx_queued, ndev, 2103 "still transmitting with the full ring!\n"); 2104 netif_stop_subqueue(ndev, q); 2105 spin_unlock_irqrestore(&priv->lock, flags); 2106 return NETDEV_TX_BUSY; 2107 } 2108 2109 if (skb_put_padto(skb, ETH_ZLEN)) 2110 goto exit; 2111 2112 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc); 2113 priv->tx_skb[q][entry / num_tx_desc] = skb; 2114 2115 if (num_tx_desc > 1) { 2116 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 2117 entry / num_tx_desc * DPTR_ALIGN; 2118 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 2119 2120 /* Zero length DMA descriptors are problematic as they seem 2121 * to terminate DMA transfers. Avoid them by simply using a 2122 * length of DPTR_ALIGN (4) when skb data is aligned to 2123 * DPTR_ALIGN. 2124 * 2125 * As skb is guaranteed to have at least ETH_ZLEN (60) 2126 * bytes of data by the call to skb_put_padto() above this 2127 * is safe with respect to both the length of the first DMA 2128 * descriptor (len) overflowing the available data and the 2129 * length of the second DMA descriptor (skb->len - len) 2130 * being negative. 2131 */ 2132 if (len == 0) 2133 len = DPTR_ALIGN; 2134 2135 memcpy(buffer, skb->data, len); 2136 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 2137 DMA_TO_DEVICE); 2138 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2139 goto drop; 2140 2141 desc = &priv->tx_ring[q][entry]; 2142 desc->ds_tagl = cpu_to_le16(len); 2143 desc->dptr = cpu_to_le32(dma_addr); 2144 2145 buffer = skb->data + len; 2146 len = skb->len - len; 2147 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 2148 DMA_TO_DEVICE); 2149 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2150 goto unmap; 2151 2152 desc++; 2153 } else { 2154 desc = &priv->tx_ring[q][entry]; 2155 len = skb->len; 2156 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, 2157 DMA_TO_DEVICE); 2158 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2159 goto drop; 2160 } 2161 desc->ds_tagl = cpu_to_le16(len); 2162 desc->dptr = cpu_to_le32(dma_addr); 2163 2164 /* TX timestamp required */ 2165 if (info->gptp || info->ccc_gac) { 2166 if (q == RAVB_NC) { 2167 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 2168 if (!ts_skb) { 2169 if (num_tx_desc > 1) { 2170 desc--; 2171 dma_unmap_single(ndev->dev.parent, dma_addr, 2172 len, DMA_TO_DEVICE); 2173 } 2174 goto unmap; 2175 } 2176 ts_skb->skb = skb_get(skb); 2177 ts_skb->tag = priv->ts_skb_tag++; 2178 priv->ts_skb_tag &= 0x3ff; 2179 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 2180 2181 /* TAG and timestamp required flag */ 2182 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2183 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 2184 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12); 2185 } 2186 2187 skb_tx_timestamp(skb); 2188 } 2189 /* Descriptor type must be set after all the above writes */ 2190 dma_wmb(); 2191 if (num_tx_desc > 1) { 2192 desc->die_dt = DT_FEND; 2193 desc--; 2194 desc->die_dt = DT_FSTART; 2195 } else { 2196 desc->die_dt = DT_FSINGLE; 2197 } 2198 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 2199 2200 priv->cur_tx[q] += num_tx_desc; 2201 if (priv->cur_tx[q] - priv->dirty_tx[q] > 2202 (priv->num_tx_ring[q] - 1) * num_tx_desc && 2203 !ravb_tx_free(ndev, q, true)) 2204 netif_stop_subqueue(ndev, q); 2205 2206 exit: 2207 spin_unlock_irqrestore(&priv->lock, flags); 2208 return NETDEV_TX_OK; 2209 2210 unmap: 2211 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 2212 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 2213 drop: 2214 dev_kfree_skb_any(skb); 2215 priv->tx_skb[q][entry / num_tx_desc] = NULL; 2216 goto exit; 2217 } 2218 2219 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 2220 struct net_device *sb_dev) 2221 { 2222 /* If skb needs TX timestamp, it is handled in network control queue */ 2223 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 2224 RAVB_BE; 2225 2226 } 2227 2228 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 2229 { 2230 struct ravb_private *priv = netdev_priv(ndev); 2231 const struct ravb_hw_info *info = priv->info; 2232 struct net_device_stats *nstats, *stats0, *stats1; 2233 struct device *dev = &priv->pdev->dev; 2234 2235 nstats = &ndev->stats; 2236 2237 pm_runtime_get_noresume(dev); 2238 2239 if (!pm_runtime_active(dev)) 2240 goto out_rpm_put; 2241 2242 stats0 = &priv->stats[RAVB_BE]; 2243 2244 if (info->tx_counters) { 2245 nstats->tx_dropped += ravb_read(ndev, TROCR); 2246 ravb_write(ndev, 0, TROCR); /* (write clear) */ 2247 } 2248 2249 if (info->carrier_counters) { 2250 nstats->collisions += ravb_read(ndev, CXR41); 2251 ravb_write(ndev, 0, CXR41); /* (write clear) */ 2252 nstats->tx_carrier_errors += ravb_read(ndev, CXR42); 2253 ravb_write(ndev, 0, CXR42); /* (write clear) */ 2254 } 2255 2256 nstats->rx_packets = stats0->rx_packets; 2257 nstats->tx_packets = stats0->tx_packets; 2258 nstats->rx_bytes = stats0->rx_bytes; 2259 nstats->tx_bytes = stats0->tx_bytes; 2260 nstats->multicast = stats0->multicast; 2261 nstats->rx_errors = stats0->rx_errors; 2262 nstats->rx_crc_errors = stats0->rx_crc_errors; 2263 nstats->rx_frame_errors = stats0->rx_frame_errors; 2264 nstats->rx_length_errors = stats0->rx_length_errors; 2265 nstats->rx_missed_errors = stats0->rx_missed_errors; 2266 nstats->rx_over_errors = stats0->rx_over_errors; 2267 if (info->nc_queues) { 2268 stats1 = &priv->stats[RAVB_NC]; 2269 2270 nstats->rx_packets += stats1->rx_packets; 2271 nstats->tx_packets += stats1->tx_packets; 2272 nstats->rx_bytes += stats1->rx_bytes; 2273 nstats->tx_bytes += stats1->tx_bytes; 2274 nstats->multicast += stats1->multicast; 2275 nstats->rx_errors += stats1->rx_errors; 2276 nstats->rx_crc_errors += stats1->rx_crc_errors; 2277 nstats->rx_frame_errors += stats1->rx_frame_errors; 2278 nstats->rx_length_errors += stats1->rx_length_errors; 2279 nstats->rx_missed_errors += stats1->rx_missed_errors; 2280 nstats->rx_over_errors += stats1->rx_over_errors; 2281 } 2282 2283 out_rpm_put: 2284 pm_runtime_put_noidle(dev); 2285 return nstats; 2286 } 2287 2288 /* Update promiscuous bit */ 2289 static void ravb_set_rx_mode(struct net_device *ndev) 2290 { 2291 struct ravb_private *priv = netdev_priv(ndev); 2292 unsigned long flags; 2293 2294 spin_lock_irqsave(&priv->lock, flags); 2295 ravb_modify(ndev, ECMR, ECMR_PRM, 2296 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 2297 spin_unlock_irqrestore(&priv->lock, flags); 2298 } 2299 2300 /* Device close function for Ethernet AVB */ 2301 static int ravb_close(struct net_device *ndev) 2302 { 2303 struct device_node *np = ndev->dev.parent->of_node; 2304 struct ravb_private *priv = netdev_priv(ndev); 2305 const struct ravb_hw_info *info = priv->info; 2306 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 2307 struct device *dev = &priv->pdev->dev; 2308 int error; 2309 2310 netif_tx_stop_all_queues(ndev); 2311 2312 /* Disable interrupts by clearing the interrupt masks. */ 2313 ravb_write(ndev, 0, RIC0); 2314 ravb_write(ndev, 0, RIC2); 2315 ravb_write(ndev, 0, TIC); 2316 2317 /* PHY disconnect */ 2318 if (ndev->phydev) { 2319 phy_stop(ndev->phydev); 2320 phy_disconnect(ndev->phydev); 2321 if (of_phy_is_fixed_link(np)) 2322 of_phy_deregister_fixed_link(np); 2323 } 2324 2325 /* Stop PTP Clock driver */ 2326 if (info->gptp || info->ccc_gac) 2327 ravb_ptp_stop(ndev); 2328 2329 /* Set the config mode to stop the AVB-DMAC's processes */ 2330 if (ravb_stop_dma(ndev) < 0) 2331 netdev_err(ndev, 2332 "device will be stopped after h/w processes are done.\n"); 2333 2334 /* Clear the timestamp list */ 2335 if (info->gptp || info->ccc_gac) { 2336 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 2337 list_del(&ts_skb->list); 2338 kfree_skb(ts_skb->skb); 2339 kfree(ts_skb); 2340 } 2341 } 2342 2343 cancel_work_sync(&priv->work); 2344 2345 if (info->nc_queues) 2346 napi_disable(&priv->napi[RAVB_NC]); 2347 napi_disable(&priv->napi[RAVB_BE]); 2348 2349 /* Free all the skb's in the RX queue and the DMA buffers. */ 2350 ravb_ring_free(ndev, RAVB_BE); 2351 if (info->nc_queues) 2352 ravb_ring_free(ndev, RAVB_NC); 2353 2354 /* Update statistics. */ 2355 ravb_get_stats(ndev); 2356 2357 /* Set reset mode. */ 2358 error = ravb_set_opmode(ndev, CCC_OPC_RESET); 2359 if (error) 2360 return error; 2361 2362 pm_runtime_mark_last_busy(dev); 2363 pm_runtime_put_autosuspend(dev); 2364 2365 return 0; 2366 } 2367 2368 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 2369 { 2370 struct ravb_private *priv = netdev_priv(ndev); 2371 struct hwtstamp_config config; 2372 2373 config.flags = 0; 2374 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 2375 HWTSTAMP_TX_OFF; 2376 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) { 2377 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT: 2378 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 2379 break; 2380 case RAVB_RXTSTAMP_TYPE_ALL: 2381 config.rx_filter = HWTSTAMP_FILTER_ALL; 2382 break; 2383 default: 2384 config.rx_filter = HWTSTAMP_FILTER_NONE; 2385 } 2386 2387 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2388 -EFAULT : 0; 2389 } 2390 2391 /* Control hardware time stamping */ 2392 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 2393 { 2394 struct ravb_private *priv = netdev_priv(ndev); 2395 struct hwtstamp_config config; 2396 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 2397 u32 tstamp_tx_ctrl; 2398 2399 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 2400 return -EFAULT; 2401 2402 switch (config.tx_type) { 2403 case HWTSTAMP_TX_OFF: 2404 tstamp_tx_ctrl = 0; 2405 break; 2406 case HWTSTAMP_TX_ON: 2407 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 2408 break; 2409 default: 2410 return -ERANGE; 2411 } 2412 2413 switch (config.rx_filter) { 2414 case HWTSTAMP_FILTER_NONE: 2415 tstamp_rx_ctrl = 0; 2416 break; 2417 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2418 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 2419 break; 2420 default: 2421 config.rx_filter = HWTSTAMP_FILTER_ALL; 2422 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 2423 } 2424 2425 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 2426 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 2427 2428 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2429 -EFAULT : 0; 2430 } 2431 2432 /* ioctl to device function */ 2433 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 2434 { 2435 struct phy_device *phydev = ndev->phydev; 2436 2437 if (!netif_running(ndev)) 2438 return -EINVAL; 2439 2440 if (!phydev) 2441 return -ENODEV; 2442 2443 switch (cmd) { 2444 case SIOCGHWTSTAMP: 2445 return ravb_hwtstamp_get(ndev, req); 2446 case SIOCSHWTSTAMP: 2447 return ravb_hwtstamp_set(ndev, req); 2448 } 2449 2450 return phy_mii_ioctl(phydev, req, cmd); 2451 } 2452 2453 static int ravb_change_mtu(struct net_device *ndev, int new_mtu) 2454 { 2455 struct ravb_private *priv = netdev_priv(ndev); 2456 2457 WRITE_ONCE(ndev->mtu, new_mtu); 2458 2459 if (netif_running(ndev)) { 2460 synchronize_irq(priv->emac_irq); 2461 ravb_emac_init(ndev); 2462 } 2463 2464 netdev_update_features(ndev); 2465 2466 return 0; 2467 } 2468 2469 static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 2470 { 2471 struct ravb_private *priv = netdev_priv(ndev); 2472 unsigned long flags; 2473 2474 spin_lock_irqsave(&priv->lock, flags); 2475 2476 /* Disable TX and RX */ 2477 ravb_rcv_snd_disable(ndev); 2478 2479 /* Modify RX Checksum setting */ 2480 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 2481 2482 /* Enable TX and RX */ 2483 ravb_rcv_snd_enable(ndev); 2484 2485 spin_unlock_irqrestore(&priv->lock, flags); 2486 } 2487 2488 static int ravb_endisable_csum_gbeth(struct net_device *ndev, enum ravb_reg reg, 2489 u32 val, u32 mask) 2490 { 2491 u32 csr0 = CSR0_TPE | CSR0_RPE; 2492 int ret; 2493 2494 ravb_write(ndev, csr0 & ~mask, CSR0); 2495 ret = ravb_wait(ndev, CSR0, mask, 0); 2496 if (!ret) 2497 ravb_write(ndev, val, reg); 2498 2499 ravb_write(ndev, csr0, CSR0); 2500 2501 return ret; 2502 } 2503 2504 static int ravb_set_features_gbeth(struct net_device *ndev, 2505 netdev_features_t features) 2506 { 2507 netdev_features_t changed = ndev->features ^ features; 2508 struct ravb_private *priv = netdev_priv(ndev); 2509 unsigned long flags; 2510 int ret = 0; 2511 u32 val; 2512 2513 spin_lock_irqsave(&priv->lock, flags); 2514 if (changed & NETIF_F_RXCSUM) { 2515 if (features & NETIF_F_RXCSUM) 2516 val = CSR2_RIP4 | CSR2_RTCP4 | CSR2_RUDP4 | CSR2_RICMP4; 2517 else 2518 val = 0; 2519 2520 ret = ravb_endisable_csum_gbeth(ndev, CSR2, val, CSR0_RPE); 2521 if (ret) 2522 goto done; 2523 } 2524 2525 if (changed & NETIF_F_HW_CSUM) { 2526 if (features & NETIF_F_HW_CSUM) 2527 val = CSR1_TIP4 | CSR1_TTCP4 | CSR1_TUDP4; 2528 else 2529 val = 0; 2530 2531 ret = ravb_endisable_csum_gbeth(ndev, CSR1, val, CSR0_TPE); 2532 if (ret) 2533 goto done; 2534 } 2535 2536 done: 2537 spin_unlock_irqrestore(&priv->lock, flags); 2538 2539 return ret; 2540 } 2541 2542 static int ravb_set_features_rcar(struct net_device *ndev, 2543 netdev_features_t features) 2544 { 2545 netdev_features_t changed = ndev->features ^ features; 2546 2547 if (changed & NETIF_F_RXCSUM) 2548 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 2549 2550 return 0; 2551 } 2552 2553 static int ravb_set_features(struct net_device *ndev, 2554 netdev_features_t features) 2555 { 2556 struct ravb_private *priv = netdev_priv(ndev); 2557 const struct ravb_hw_info *info = priv->info; 2558 struct device *dev = &priv->pdev->dev; 2559 int ret; 2560 2561 pm_runtime_get_noresume(dev); 2562 2563 if (pm_runtime_active(dev)) 2564 ret = info->set_feature(ndev, features); 2565 else 2566 ret = 0; 2567 2568 pm_runtime_put_noidle(dev); 2569 2570 if (ret) 2571 return ret; 2572 2573 ndev->features = features; 2574 2575 return 0; 2576 } 2577 2578 static const struct net_device_ops ravb_netdev_ops = { 2579 .ndo_open = ravb_open, 2580 .ndo_stop = ravb_close, 2581 .ndo_start_xmit = ravb_start_xmit, 2582 .ndo_select_queue = ravb_select_queue, 2583 .ndo_get_stats = ravb_get_stats, 2584 .ndo_set_rx_mode = ravb_set_rx_mode, 2585 .ndo_tx_timeout = ravb_tx_timeout, 2586 .ndo_eth_ioctl = ravb_do_ioctl, 2587 .ndo_change_mtu = ravb_change_mtu, 2588 .ndo_validate_addr = eth_validate_addr, 2589 .ndo_set_mac_address = eth_mac_addr, 2590 .ndo_set_features = ravb_set_features, 2591 }; 2592 2593 /* MDIO bus init function */ 2594 static int ravb_mdio_init(struct ravb_private *priv) 2595 { 2596 struct platform_device *pdev = priv->pdev; 2597 struct device *dev = &pdev->dev; 2598 struct device_node *mdio_node; 2599 struct phy_device *phydev; 2600 struct device_node *pn; 2601 int error; 2602 2603 /* Bitbang init */ 2604 priv->mdiobb.ops = &bb_ops; 2605 2606 /* MII controller setting */ 2607 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 2608 if (!priv->mii_bus) 2609 return -ENOMEM; 2610 2611 /* Hook up MII support for ethtool */ 2612 priv->mii_bus->name = "ravb_mii"; 2613 priv->mii_bus->parent = dev; 2614 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2615 pdev->name, pdev->id); 2616 2617 /* Register MDIO bus */ 2618 mdio_node = of_get_child_by_name(dev->of_node, "mdio"); 2619 if (!mdio_node) { 2620 /* backwards compatibility for DT lacking mdio subnode */ 2621 mdio_node = of_node_get(dev->of_node); 2622 } 2623 error = of_mdiobus_register(priv->mii_bus, mdio_node); 2624 of_node_put(mdio_node); 2625 if (error) 2626 goto out_free_bus; 2627 2628 pn = of_parse_phandle(dev->of_node, "phy-handle", 0); 2629 phydev = of_phy_find_device(pn); 2630 if (phydev) { 2631 phydev->mac_managed_pm = true; 2632 put_device(&phydev->mdio.dev); 2633 } 2634 of_node_put(pn); 2635 2636 return 0; 2637 2638 out_free_bus: 2639 free_mdio_bitbang(priv->mii_bus); 2640 return error; 2641 } 2642 2643 /* MDIO bus release function */ 2644 static int ravb_mdio_release(struct ravb_private *priv) 2645 { 2646 /* Unregister mdio bus */ 2647 mdiobus_unregister(priv->mii_bus); 2648 2649 /* Free bitbang info */ 2650 free_mdio_bitbang(priv->mii_bus); 2651 2652 return 0; 2653 } 2654 2655 static const struct ravb_hw_info ravb_gen3_hw_info = { 2656 .receive = ravb_rx_rcar, 2657 .set_rate = ravb_set_rate_rcar, 2658 .set_feature = ravb_set_features_rcar, 2659 .dmac_init = ravb_dmac_init_rcar, 2660 .emac_init = ravb_emac_init_rcar, 2661 .gstrings_stats = ravb_gstrings_stats, 2662 .gstrings_size = sizeof(ravb_gstrings_stats), 2663 .net_hw_features = NETIF_F_RXCSUM, 2664 .net_features = NETIF_F_RXCSUM, 2665 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2666 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2667 .rx_max_frame_size = SZ_2K, 2668 .rx_buffer_size = SZ_2K + 2669 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), 2670 .rx_desc_size = sizeof(struct ravb_ex_rx_desc), 2671 .internal_delay = 1, 2672 .tx_counters = 1, 2673 .multi_irqs = 1, 2674 .irq_en_dis = 1, 2675 .ccc_gac = 1, 2676 .nc_queues = 1, 2677 .magic_pkt = 1, 2678 }; 2679 2680 static const struct ravb_hw_info ravb_gen2_hw_info = { 2681 .receive = ravb_rx_rcar, 2682 .set_rate = ravb_set_rate_rcar, 2683 .set_feature = ravb_set_features_rcar, 2684 .dmac_init = ravb_dmac_init_rcar, 2685 .emac_init = ravb_emac_init_rcar, 2686 .gstrings_stats = ravb_gstrings_stats, 2687 .gstrings_size = sizeof(ravb_gstrings_stats), 2688 .net_hw_features = NETIF_F_RXCSUM, 2689 .net_features = NETIF_F_RXCSUM, 2690 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2691 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2692 .rx_max_frame_size = SZ_2K, 2693 .rx_buffer_size = SZ_2K + 2694 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), 2695 .rx_desc_size = sizeof(struct ravb_ex_rx_desc), 2696 .aligned_tx = 1, 2697 .gptp = 1, 2698 .nc_queues = 1, 2699 .magic_pkt = 1, 2700 }; 2701 2702 static const struct ravb_hw_info ravb_rzv2m_hw_info = { 2703 .receive = ravb_rx_rcar, 2704 .set_rate = ravb_set_rate_rcar, 2705 .set_feature = ravb_set_features_rcar, 2706 .dmac_init = ravb_dmac_init_rcar, 2707 .emac_init = ravb_emac_init_rcar, 2708 .gstrings_stats = ravb_gstrings_stats, 2709 .gstrings_size = sizeof(ravb_gstrings_stats), 2710 .net_hw_features = NETIF_F_RXCSUM, 2711 .net_features = NETIF_F_RXCSUM, 2712 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2713 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2714 .rx_max_frame_size = SZ_2K, 2715 .rx_buffer_size = SZ_2K + 2716 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), 2717 .rx_desc_size = sizeof(struct ravb_ex_rx_desc), 2718 .multi_irqs = 1, 2719 .err_mgmt_irqs = 1, 2720 .gptp = 1, 2721 .gptp_ref_clk = 1, 2722 .nc_queues = 1, 2723 .magic_pkt = 1, 2724 }; 2725 2726 static const struct ravb_hw_info gbeth_hw_info = { 2727 .receive = ravb_rx_gbeth, 2728 .set_rate = ravb_set_rate_gbeth, 2729 .set_feature = ravb_set_features_gbeth, 2730 .dmac_init = ravb_dmac_init_gbeth, 2731 .emac_init = ravb_emac_init_gbeth, 2732 .gstrings_stats = ravb_gstrings_stats_gbeth, 2733 .gstrings_size = sizeof(ravb_gstrings_stats_gbeth), 2734 .net_hw_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM, 2735 .net_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM, 2736 .stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth), 2737 .tccr_mask = TCCR_TSRQ0, 2738 .rx_max_frame_size = SZ_8K, 2739 .rx_buffer_size = SZ_2K, 2740 .rx_desc_size = sizeof(struct ravb_rx_desc), 2741 .aligned_tx = 1, 2742 .coalesce_irqs = 1, 2743 .tx_counters = 1, 2744 .carrier_counters = 1, 2745 .half_duplex = 1, 2746 }; 2747 2748 static const struct of_device_id ravb_match_table[] = { 2749 { .compatible = "renesas,etheravb-r8a7790", .data = &ravb_gen2_hw_info }, 2750 { .compatible = "renesas,etheravb-r8a7794", .data = &ravb_gen2_hw_info }, 2751 { .compatible = "renesas,etheravb-rcar-gen2", .data = &ravb_gen2_hw_info }, 2752 { .compatible = "renesas,etheravb-r8a7795", .data = &ravb_gen3_hw_info }, 2753 { .compatible = "renesas,etheravb-rcar-gen3", .data = &ravb_gen3_hw_info }, 2754 { .compatible = "renesas,etheravb-rcar-gen4", .data = &ravb_gen3_hw_info }, 2755 { .compatible = "renesas,etheravb-rzv2m", .data = &ravb_rzv2m_hw_info }, 2756 { .compatible = "renesas,rzg2l-gbeth", .data = &gbeth_hw_info }, 2757 { } 2758 }; 2759 MODULE_DEVICE_TABLE(of, ravb_match_table); 2760 2761 static int ravb_setup_irq(struct ravb_private *priv, const char *irq_name, 2762 const char *ch, int *irq, irq_handler_t handler) 2763 { 2764 struct platform_device *pdev = priv->pdev; 2765 struct net_device *ndev = priv->ndev; 2766 struct device *dev = &pdev->dev; 2767 const char *devname = dev_name(dev); 2768 unsigned long flags; 2769 int error, irq_num; 2770 2771 if (irq_name) { 2772 devname = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", devname, ch); 2773 if (!devname) 2774 return -ENOMEM; 2775 2776 irq_num = platform_get_irq_byname(pdev, irq_name); 2777 flags = 0; 2778 } else { 2779 irq_num = platform_get_irq(pdev, 0); 2780 flags = IRQF_SHARED; 2781 } 2782 if (irq_num < 0) 2783 return irq_num; 2784 2785 if (irq) 2786 *irq = irq_num; 2787 2788 error = devm_request_irq(dev, irq_num, handler, flags, devname, ndev); 2789 if (error) 2790 netdev_err(ndev, "cannot request IRQ %s\n", devname); 2791 2792 return error; 2793 } 2794 2795 static int ravb_setup_irqs(struct ravb_private *priv) 2796 { 2797 const struct ravb_hw_info *info = priv->info; 2798 struct net_device *ndev = priv->ndev; 2799 const char *irq_name, *emac_irq_name; 2800 int error; 2801 2802 if (!info->multi_irqs) 2803 return ravb_setup_irq(priv, NULL, NULL, &ndev->irq, ravb_interrupt); 2804 2805 if (info->err_mgmt_irqs) { 2806 irq_name = "dia"; 2807 emac_irq_name = "line3"; 2808 } else { 2809 irq_name = "ch22"; 2810 emac_irq_name = "ch24"; 2811 } 2812 2813 error = ravb_setup_irq(priv, irq_name, "ch22:multi", &ndev->irq, ravb_multi_interrupt); 2814 if (error) 2815 return error; 2816 2817 error = ravb_setup_irq(priv, emac_irq_name, "ch24:emac", &priv->emac_irq, 2818 ravb_emac_interrupt); 2819 if (error) 2820 return error; 2821 2822 if (info->err_mgmt_irqs) { 2823 error = ravb_setup_irq(priv, "err_a", "err_a", NULL, ravb_multi_interrupt); 2824 if (error) 2825 return error; 2826 2827 error = ravb_setup_irq(priv, "mgmt_a", "mgmt_a", NULL, ravb_multi_interrupt); 2828 if (error) 2829 return error; 2830 } 2831 2832 error = ravb_setup_irq(priv, "ch0", "ch0:rx_be", NULL, ravb_be_interrupt); 2833 if (error) 2834 return error; 2835 2836 error = ravb_setup_irq(priv, "ch1", "ch1:rx_nc", NULL, ravb_nc_interrupt); 2837 if (error) 2838 return error; 2839 2840 error = ravb_setup_irq(priv, "ch18", "ch18:tx_be", NULL, ravb_be_interrupt); 2841 if (error) 2842 return error; 2843 2844 return ravb_setup_irq(priv, "ch19", "ch19:tx_nc", NULL, ravb_nc_interrupt); 2845 } 2846 2847 static int ravb_probe(struct platform_device *pdev) 2848 { 2849 struct device_node *np = pdev->dev.of_node; 2850 const struct ravb_hw_info *info; 2851 struct reset_control *rstc; 2852 struct ravb_private *priv; 2853 struct net_device *ndev; 2854 struct resource *res; 2855 int error, q; 2856 2857 if (!np) { 2858 dev_err(&pdev->dev, 2859 "this driver is required to be instantiated from device tree\n"); 2860 return -EINVAL; 2861 } 2862 2863 rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 2864 if (IS_ERR(rstc)) 2865 return dev_err_probe(&pdev->dev, PTR_ERR(rstc), 2866 "failed to get cpg reset\n"); 2867 2868 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 2869 NUM_TX_QUEUE, NUM_RX_QUEUE); 2870 if (!ndev) 2871 return -ENOMEM; 2872 2873 info = of_device_get_match_data(&pdev->dev); 2874 2875 ndev->features = info->net_features; 2876 ndev->hw_features = info->net_hw_features; 2877 2878 error = reset_control_deassert(rstc); 2879 if (error) 2880 goto out_free_netdev; 2881 2882 SET_NETDEV_DEV(ndev, &pdev->dev); 2883 2884 priv = netdev_priv(ndev); 2885 priv->info = info; 2886 priv->rstc = rstc; 2887 priv->ndev = ndev; 2888 priv->pdev = pdev; 2889 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2890 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2891 if (info->nc_queues) { 2892 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2893 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2894 } 2895 2896 error = ravb_setup_irqs(priv); 2897 if (error) 2898 goto out_reset_assert; 2899 2900 priv->clk = devm_clk_get(&pdev->dev, NULL); 2901 if (IS_ERR(priv->clk)) { 2902 error = PTR_ERR(priv->clk); 2903 goto out_reset_assert; 2904 } 2905 2906 if (info->gptp_ref_clk) { 2907 priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp"); 2908 if (IS_ERR(priv->gptp_clk)) { 2909 error = PTR_ERR(priv->gptp_clk); 2910 goto out_reset_assert; 2911 } 2912 } 2913 2914 priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk"); 2915 if (IS_ERR(priv->refclk)) { 2916 error = PTR_ERR(priv->refclk); 2917 goto out_reset_assert; 2918 } 2919 clk_prepare(priv->refclk); 2920 2921 platform_set_drvdata(pdev, ndev); 2922 pm_runtime_set_autosuspend_delay(&pdev->dev, 100); 2923 pm_runtime_use_autosuspend(&pdev->dev); 2924 pm_runtime_enable(&pdev->dev); 2925 error = pm_runtime_resume_and_get(&pdev->dev); 2926 if (error < 0) 2927 goto out_rpm_disable; 2928 2929 priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2930 if (IS_ERR(priv->addr)) { 2931 error = PTR_ERR(priv->addr); 2932 goto out_rpm_put; 2933 } 2934 2935 /* The Ether-specific entries in the device structure. */ 2936 ndev->base_addr = res->start; 2937 2938 spin_lock_init(&priv->lock); 2939 INIT_WORK(&priv->work, ravb_tx_timeout_work); 2940 2941 error = of_get_phy_mode(np, &priv->phy_interface); 2942 if (error && error != -ENODEV) 2943 goto out_rpm_put; 2944 2945 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 2946 priv->avb_link_active_low = 2947 of_property_read_bool(np, "renesas,ether-link-active-low"); 2948 2949 ndev->max_mtu = info->rx_max_frame_size - 2950 (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 2951 ndev->min_mtu = ETH_MIN_MTU; 2952 2953 /* FIXME: R-Car Gen2 has 4byte alignment restriction for tx buffer 2954 * Use two descriptor to handle such situation. First descriptor to 2955 * handle aligned data buffer and second descriptor to handle the 2956 * overflow data because of alignment. 2957 */ 2958 priv->num_tx_desc = info->aligned_tx ? 2 : 1; 2959 2960 /* Set function */ 2961 ndev->netdev_ops = &ravb_netdev_ops; 2962 ndev->ethtool_ops = &ravb_ethtool_ops; 2963 2964 error = ravb_compute_gti(ndev); 2965 if (error) 2966 goto out_rpm_put; 2967 2968 ravb_parse_delay_mode(np, ndev); 2969 2970 /* Allocate descriptor base address table */ 2971 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 2972 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 2973 &priv->desc_bat_dma, GFP_KERNEL); 2974 if (!priv->desc_bat) { 2975 dev_err(&pdev->dev, 2976 "Cannot allocate desc base address table (size %d bytes)\n", 2977 priv->desc_bat_size); 2978 error = -ENOMEM; 2979 goto out_rpm_put; 2980 } 2981 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 2982 priv->desc_bat[q].die_dt = DT_EOS; 2983 2984 /* Initialise HW timestamp list */ 2985 INIT_LIST_HEAD(&priv->ts_skb_list); 2986 2987 /* Debug message level */ 2988 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 2989 2990 /* Set config mode as this is needed for PHY initialization. */ 2991 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 2992 if (error) 2993 goto out_rpm_put; 2994 2995 /* Read and set MAC address */ 2996 ravb_read_mac_address(np, ndev); 2997 if (!is_valid_ether_addr(ndev->dev_addr)) { 2998 dev_warn(&pdev->dev, 2999 "no valid MAC address supplied, using a random one\n"); 3000 eth_hw_addr_random(ndev); 3001 } 3002 3003 /* MDIO bus init */ 3004 error = ravb_mdio_init(priv); 3005 if (error) { 3006 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 3007 goto out_reset_mode; 3008 } 3009 3010 /* Undo previous switch to config opmode. */ 3011 error = ravb_set_opmode(ndev, CCC_OPC_RESET); 3012 if (error) 3013 goto out_mdio_release; 3014 3015 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll); 3016 if (info->nc_queues) 3017 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll); 3018 3019 if (info->coalesce_irqs) { 3020 netdev_sw_irq_coalesce_default_on(ndev); 3021 if (num_present_cpus() == 1) 3022 dev_set_threaded(ndev, true); 3023 } 3024 3025 /* Network device register */ 3026 error = register_netdev(ndev); 3027 if (error) 3028 goto out_napi_del; 3029 3030 device_set_wakeup_capable(&pdev->dev, 1); 3031 3032 /* Print device information */ 3033 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 3034 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 3035 3036 pm_runtime_mark_last_busy(&pdev->dev); 3037 pm_runtime_put_autosuspend(&pdev->dev); 3038 3039 return 0; 3040 3041 out_napi_del: 3042 if (info->nc_queues) 3043 netif_napi_del(&priv->napi[RAVB_NC]); 3044 3045 netif_napi_del(&priv->napi[RAVB_BE]); 3046 out_mdio_release: 3047 ravb_mdio_release(priv); 3048 out_reset_mode: 3049 ravb_set_opmode(ndev, CCC_OPC_RESET); 3050 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 3051 priv->desc_bat_dma); 3052 out_rpm_put: 3053 pm_runtime_put(&pdev->dev); 3054 out_rpm_disable: 3055 pm_runtime_disable(&pdev->dev); 3056 pm_runtime_dont_use_autosuspend(&pdev->dev); 3057 clk_unprepare(priv->refclk); 3058 out_reset_assert: 3059 reset_control_assert(rstc); 3060 out_free_netdev: 3061 free_netdev(ndev); 3062 return error; 3063 } 3064 3065 static void ravb_remove(struct platform_device *pdev) 3066 { 3067 struct net_device *ndev = platform_get_drvdata(pdev); 3068 struct ravb_private *priv = netdev_priv(ndev); 3069 const struct ravb_hw_info *info = priv->info; 3070 struct device *dev = &priv->pdev->dev; 3071 int error; 3072 3073 error = pm_runtime_resume_and_get(dev); 3074 if (error < 0) 3075 return; 3076 3077 unregister_netdev(ndev); 3078 if (info->nc_queues) 3079 netif_napi_del(&priv->napi[RAVB_NC]); 3080 netif_napi_del(&priv->napi[RAVB_BE]); 3081 3082 ravb_mdio_release(priv); 3083 3084 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 3085 priv->desc_bat_dma); 3086 3087 pm_runtime_put_sync_suspend(&pdev->dev); 3088 pm_runtime_disable(&pdev->dev); 3089 pm_runtime_dont_use_autosuspend(dev); 3090 clk_unprepare(priv->refclk); 3091 reset_control_assert(priv->rstc); 3092 free_netdev(ndev); 3093 platform_set_drvdata(pdev, NULL); 3094 } 3095 3096 static int ravb_wol_setup(struct net_device *ndev) 3097 { 3098 struct ravb_private *priv = netdev_priv(ndev); 3099 const struct ravb_hw_info *info = priv->info; 3100 3101 /* Disable interrupts by clearing the interrupt masks. */ 3102 ravb_write(ndev, 0, RIC0); 3103 ravb_write(ndev, 0, RIC2); 3104 ravb_write(ndev, 0, TIC); 3105 3106 /* Only allow ECI interrupts */ 3107 synchronize_irq(priv->emac_irq); 3108 if (info->nc_queues) 3109 napi_disable(&priv->napi[RAVB_NC]); 3110 napi_disable(&priv->napi[RAVB_BE]); 3111 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 3112 3113 /* Enable MagicPacket */ 3114 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 3115 3116 if (priv->info->ccc_gac) 3117 ravb_ptp_stop(ndev); 3118 3119 return enable_irq_wake(priv->emac_irq); 3120 } 3121 3122 static int ravb_wol_restore(struct net_device *ndev) 3123 { 3124 struct ravb_private *priv = netdev_priv(ndev); 3125 const struct ravb_hw_info *info = priv->info; 3126 int error; 3127 3128 /* Set reset mode to rearm the WoL logic. */ 3129 error = ravb_set_opmode(ndev, CCC_OPC_RESET); 3130 if (error) 3131 return error; 3132 3133 /* Set AVB config mode. */ 3134 error = ravb_set_config_mode(ndev); 3135 if (error) 3136 return error; 3137 3138 if (priv->info->ccc_gac) 3139 ravb_ptp_init(ndev, priv->pdev); 3140 3141 if (info->nc_queues) 3142 napi_enable(&priv->napi[RAVB_NC]); 3143 napi_enable(&priv->napi[RAVB_BE]); 3144 3145 /* Disable MagicPacket */ 3146 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 3147 3148 ravb_close(ndev); 3149 3150 return disable_irq_wake(priv->emac_irq); 3151 } 3152 3153 static int ravb_suspend(struct device *dev) 3154 { 3155 struct net_device *ndev = dev_get_drvdata(dev); 3156 struct ravb_private *priv = netdev_priv(ndev); 3157 int ret; 3158 3159 if (!netif_running(ndev)) 3160 goto reset_assert; 3161 3162 netif_device_detach(ndev); 3163 3164 if (priv->wol_enabled) 3165 return ravb_wol_setup(ndev); 3166 3167 ret = ravb_close(ndev); 3168 if (ret) 3169 return ret; 3170 3171 ret = pm_runtime_force_suspend(&priv->pdev->dev); 3172 if (ret) 3173 return ret; 3174 3175 reset_assert: 3176 return reset_control_assert(priv->rstc); 3177 } 3178 3179 static int ravb_resume(struct device *dev) 3180 { 3181 struct net_device *ndev = dev_get_drvdata(dev); 3182 struct ravb_private *priv = netdev_priv(ndev); 3183 int ret; 3184 3185 ret = reset_control_deassert(priv->rstc); 3186 if (ret) 3187 return ret; 3188 3189 if (!netif_running(ndev)) 3190 return 0; 3191 3192 /* If WoL is enabled restore the interface. */ 3193 if (priv->wol_enabled) { 3194 ret = ravb_wol_restore(ndev); 3195 if (ret) 3196 return ret; 3197 } else { 3198 ret = pm_runtime_force_resume(dev); 3199 if (ret) 3200 return ret; 3201 } 3202 3203 /* Reopening the interface will restore the device to the working state. */ 3204 ret = ravb_open(ndev); 3205 if (ret < 0) 3206 goto out_rpm_put; 3207 3208 ravb_set_rx_mode(ndev); 3209 netif_device_attach(ndev); 3210 3211 return 0; 3212 3213 out_rpm_put: 3214 if (!priv->wol_enabled) { 3215 pm_runtime_mark_last_busy(dev); 3216 pm_runtime_put_autosuspend(dev); 3217 } 3218 3219 return ret; 3220 } 3221 3222 static int ravb_runtime_suspend(struct device *dev) 3223 { 3224 struct net_device *ndev = dev_get_drvdata(dev); 3225 struct ravb_private *priv = netdev_priv(ndev); 3226 3227 clk_disable(priv->refclk); 3228 3229 return 0; 3230 } 3231 3232 static int ravb_runtime_resume(struct device *dev) 3233 { 3234 struct net_device *ndev = dev_get_drvdata(dev); 3235 struct ravb_private *priv = netdev_priv(ndev); 3236 3237 return clk_enable(priv->refclk); 3238 } 3239 3240 static const struct dev_pm_ops ravb_dev_pm_ops = { 3241 SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 3242 RUNTIME_PM_OPS(ravb_runtime_suspend, ravb_runtime_resume, NULL) 3243 }; 3244 3245 static struct platform_driver ravb_driver = { 3246 .probe = ravb_probe, 3247 .remove_new = ravb_remove, 3248 .driver = { 3249 .name = "ravb", 3250 .pm = pm_ptr(&ravb_dev_pm_ops), 3251 .of_match_table = ravb_match_table, 3252 }, 3253 }; 3254 3255 module_platform_driver(ravb_driver); 3256 3257 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 3258 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 3259 MODULE_LICENSE("GPL v2"); 3260