1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet AVB device driver 3 * 4 * Copyright (C) 2014-2019 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * Based on the SuperH Ethernet driver 9 */ 10 11 #include <linux/cache.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_vlan.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/module.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/of.h> 24 #include <linux/of_mdio.h> 25 #include <linux/of_net.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/slab.h> 29 #include <linux/spinlock.h> 30 #include <linux/reset.h> 31 #include <linux/math64.h> 32 33 #include "ravb.h" 34 35 #define RAVB_DEF_MSG_ENABLE \ 36 (NETIF_MSG_LINK | \ 37 NETIF_MSG_TIMER | \ 38 NETIF_MSG_RX_ERR | \ 39 NETIF_MSG_TX_ERR) 40 41 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 42 u32 set) 43 { 44 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 45 } 46 47 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 48 { 49 int i; 50 51 for (i = 0; i < 10000; i++) { 52 if ((ravb_read(ndev, reg) & mask) == value) 53 return 0; 54 udelay(10); 55 } 56 return -ETIMEDOUT; 57 } 58 59 static int ravb_set_opmode(struct net_device *ndev, u32 opmode) 60 { 61 u32 csr_ops = 1U << (opmode & CCC_OPC); 62 u32 ccc_mask = CCC_OPC; 63 int error; 64 65 /* If gPTP active in config mode is supported it needs to be configured 66 * along with CSEL and operating mode in the same access. This is a 67 * hardware limitation. 68 */ 69 if (opmode & CCC_GAC) 70 ccc_mask |= CCC_GAC | CCC_CSEL; 71 72 /* Set operating mode */ 73 ravb_modify(ndev, CCC, ccc_mask, opmode); 74 /* Check if the operating mode is changed to the requested one */ 75 error = ravb_wait(ndev, CSR, CSR_OPS, csr_ops); 76 if (error) { 77 netdev_err(ndev, "failed to switch device to requested mode (%u)\n", 78 opmode & CCC_OPC); 79 } 80 81 return error; 82 } 83 84 static void ravb_set_rate_gbeth(struct net_device *ndev) 85 { 86 struct ravb_private *priv = netdev_priv(ndev); 87 88 switch (priv->speed) { 89 case 10: /* 10BASE */ 90 ravb_write(ndev, GBETH_GECMR_SPEED_10, GECMR); 91 break; 92 case 100: /* 100BASE */ 93 ravb_write(ndev, GBETH_GECMR_SPEED_100, GECMR); 94 break; 95 case 1000: /* 1000BASE */ 96 ravb_write(ndev, GBETH_GECMR_SPEED_1000, GECMR); 97 break; 98 } 99 } 100 101 static void ravb_set_rate_rcar(struct net_device *ndev) 102 { 103 struct ravb_private *priv = netdev_priv(ndev); 104 105 switch (priv->speed) { 106 case 100: /* 100BASE */ 107 ravb_write(ndev, GECMR_SPEED_100, GECMR); 108 break; 109 case 1000: /* 1000BASE */ 110 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 111 break; 112 } 113 } 114 115 static void ravb_set_buffer_align(struct sk_buff *skb) 116 { 117 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1); 118 119 if (reserve) 120 skb_reserve(skb, RAVB_ALIGN - reserve); 121 } 122 123 /* Get MAC address from the MAC address registers 124 * 125 * Ethernet AVB device doesn't have ROM for MAC address. 126 * This function gets the MAC address that was used by a bootloader. 127 */ 128 static void ravb_read_mac_address(struct device_node *np, 129 struct net_device *ndev) 130 { 131 int ret; 132 133 ret = of_get_ethdev_address(np, ndev); 134 if (ret) { 135 u32 mahr = ravb_read(ndev, MAHR); 136 u32 malr = ravb_read(ndev, MALR); 137 u8 addr[ETH_ALEN]; 138 139 addr[0] = (mahr >> 24) & 0xFF; 140 addr[1] = (mahr >> 16) & 0xFF; 141 addr[2] = (mahr >> 8) & 0xFF; 142 addr[3] = (mahr >> 0) & 0xFF; 143 addr[4] = (malr >> 8) & 0xFF; 144 addr[5] = (malr >> 0) & 0xFF; 145 eth_hw_addr_set(ndev, addr); 146 } 147 } 148 149 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 150 { 151 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 152 mdiobb); 153 154 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 155 } 156 157 /* MDC pin control */ 158 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 159 { 160 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 161 } 162 163 /* Data I/O pin control */ 164 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 165 { 166 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 167 } 168 169 /* Set data bit */ 170 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 171 { 172 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 173 } 174 175 /* Get data bit */ 176 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 177 { 178 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 179 mdiobb); 180 181 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 182 } 183 184 /* MDIO bus control struct */ 185 static const struct mdiobb_ops bb_ops = { 186 .owner = THIS_MODULE, 187 .set_mdc = ravb_set_mdc, 188 .set_mdio_dir = ravb_set_mdio_dir, 189 .set_mdio_data = ravb_set_mdio_data, 190 .get_mdio_data = ravb_get_mdio_data, 191 }; 192 193 /* Free TX skb function for AVB-IP */ 194 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 195 { 196 struct ravb_private *priv = netdev_priv(ndev); 197 struct net_device_stats *stats = &priv->stats[q]; 198 unsigned int num_tx_desc = priv->num_tx_desc; 199 struct ravb_tx_desc *desc; 200 unsigned int entry; 201 int free_num = 0; 202 u32 size; 203 204 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 205 bool txed; 206 207 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 208 num_tx_desc); 209 desc = &priv->tx_ring[q][entry]; 210 txed = desc->die_dt == DT_FEMPTY; 211 if (free_txed_only && !txed) 212 break; 213 /* Descriptor type must be checked before all other reads */ 214 dma_rmb(); 215 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 216 /* Free the original skb. */ 217 if (priv->tx_skb[q][entry / num_tx_desc]) { 218 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 219 size, DMA_TO_DEVICE); 220 /* Last packet descriptor? */ 221 if (entry % num_tx_desc == num_tx_desc - 1) { 222 entry /= num_tx_desc; 223 dev_kfree_skb_any(priv->tx_skb[q][entry]); 224 priv->tx_skb[q][entry] = NULL; 225 if (txed) 226 stats->tx_packets++; 227 } 228 free_num++; 229 } 230 if (txed) 231 stats->tx_bytes += size; 232 desc->die_dt = DT_EEMPTY; 233 } 234 return free_num; 235 } 236 237 static void ravb_rx_ring_free_gbeth(struct net_device *ndev, int q) 238 { 239 struct ravb_private *priv = netdev_priv(ndev); 240 unsigned int ring_size; 241 unsigned int i; 242 243 if (!priv->gbeth_rx_ring) 244 return; 245 246 for (i = 0; i < priv->num_rx_ring[q]; i++) { 247 struct ravb_rx_desc *desc = &priv->gbeth_rx_ring[i]; 248 249 if (!dma_mapping_error(ndev->dev.parent, 250 le32_to_cpu(desc->dptr))) 251 dma_unmap_single(ndev->dev.parent, 252 le32_to_cpu(desc->dptr), 253 GBETH_RX_BUFF_MAX, 254 DMA_FROM_DEVICE); 255 } 256 ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1); 257 dma_free_coherent(ndev->dev.parent, ring_size, priv->gbeth_rx_ring, 258 priv->rx_desc_dma[q]); 259 priv->gbeth_rx_ring = NULL; 260 } 261 262 static void ravb_rx_ring_free_rcar(struct net_device *ndev, int q) 263 { 264 struct ravb_private *priv = netdev_priv(ndev); 265 unsigned int ring_size; 266 unsigned int i; 267 268 if (!priv->rx_ring[q]) 269 return; 270 271 for (i = 0; i < priv->num_rx_ring[q]; i++) { 272 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i]; 273 274 if (!dma_mapping_error(ndev->dev.parent, 275 le32_to_cpu(desc->dptr))) 276 dma_unmap_single(ndev->dev.parent, 277 le32_to_cpu(desc->dptr), 278 RX_BUF_SZ, 279 DMA_FROM_DEVICE); 280 } 281 ring_size = sizeof(struct ravb_ex_rx_desc) * 282 (priv->num_rx_ring[q] + 1); 283 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q], 284 priv->rx_desc_dma[q]); 285 priv->rx_ring[q] = NULL; 286 } 287 288 /* Free skb's and DMA buffers for Ethernet AVB */ 289 static void ravb_ring_free(struct net_device *ndev, int q) 290 { 291 struct ravb_private *priv = netdev_priv(ndev); 292 const struct ravb_hw_info *info = priv->info; 293 unsigned int num_tx_desc = priv->num_tx_desc; 294 unsigned int ring_size; 295 unsigned int i; 296 297 info->rx_ring_free(ndev, q); 298 299 if (priv->tx_ring[q]) { 300 ravb_tx_free(ndev, q, false); 301 302 ring_size = sizeof(struct ravb_tx_desc) * 303 (priv->num_tx_ring[q] * num_tx_desc + 1); 304 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 305 priv->tx_desc_dma[q]); 306 priv->tx_ring[q] = NULL; 307 } 308 309 /* Free RX skb ringbuffer */ 310 if (priv->rx_skb[q]) { 311 for (i = 0; i < priv->num_rx_ring[q]; i++) 312 dev_kfree_skb(priv->rx_skb[q][i]); 313 } 314 kfree(priv->rx_skb[q]); 315 priv->rx_skb[q] = NULL; 316 317 /* Free aligned TX buffers */ 318 kfree(priv->tx_align[q]); 319 priv->tx_align[q] = NULL; 320 321 /* Free TX skb ringbuffer. 322 * SKBs are freed by ravb_tx_free() call above. 323 */ 324 kfree(priv->tx_skb[q]); 325 priv->tx_skb[q] = NULL; 326 } 327 328 static void ravb_rx_ring_format_gbeth(struct net_device *ndev, int q) 329 { 330 struct ravb_private *priv = netdev_priv(ndev); 331 struct ravb_rx_desc *rx_desc; 332 unsigned int rx_ring_size; 333 dma_addr_t dma_addr; 334 unsigned int i; 335 336 rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 337 memset(priv->gbeth_rx_ring, 0, rx_ring_size); 338 /* Build RX ring buffer */ 339 for (i = 0; i < priv->num_rx_ring[q]; i++) { 340 /* RX descriptor */ 341 rx_desc = &priv->gbeth_rx_ring[i]; 342 rx_desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE); 343 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 344 GBETH_RX_BUFF_MAX, 345 DMA_FROM_DEVICE); 346 /* We just set the data size to 0 for a failed mapping which 347 * should prevent DMA from happening... 348 */ 349 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 350 rx_desc->ds_cc = cpu_to_le16(0); 351 rx_desc->dptr = cpu_to_le32(dma_addr); 352 rx_desc->die_dt = DT_FEMPTY; 353 } 354 rx_desc = &priv->gbeth_rx_ring[i]; 355 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 356 rx_desc->die_dt = DT_LINKFIX; /* type */ 357 } 358 359 static void ravb_rx_ring_format_rcar(struct net_device *ndev, int q) 360 { 361 struct ravb_private *priv = netdev_priv(ndev); 362 struct ravb_ex_rx_desc *rx_desc; 363 unsigned int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q]; 364 dma_addr_t dma_addr; 365 unsigned int i; 366 367 memset(priv->rx_ring[q], 0, rx_ring_size); 368 /* Build RX ring buffer */ 369 for (i = 0; i < priv->num_rx_ring[q]; i++) { 370 /* RX descriptor */ 371 rx_desc = &priv->rx_ring[q][i]; 372 rx_desc->ds_cc = cpu_to_le16(RX_BUF_SZ); 373 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data, 374 RX_BUF_SZ, 375 DMA_FROM_DEVICE); 376 /* We just set the data size to 0 for a failed mapping which 377 * should prevent DMA from happening... 378 */ 379 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 380 rx_desc->ds_cc = cpu_to_le16(0); 381 rx_desc->dptr = cpu_to_le32(dma_addr); 382 rx_desc->die_dt = DT_FEMPTY; 383 } 384 rx_desc = &priv->rx_ring[q][i]; 385 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 386 rx_desc->die_dt = DT_LINKFIX; /* type */ 387 } 388 389 /* Format skb and descriptor buffer for Ethernet AVB */ 390 static void ravb_ring_format(struct net_device *ndev, int q) 391 { 392 struct ravb_private *priv = netdev_priv(ndev); 393 const struct ravb_hw_info *info = priv->info; 394 unsigned int num_tx_desc = priv->num_tx_desc; 395 struct ravb_tx_desc *tx_desc; 396 struct ravb_desc *desc; 397 unsigned int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 398 num_tx_desc; 399 unsigned int i; 400 401 priv->cur_rx[q] = 0; 402 priv->cur_tx[q] = 0; 403 priv->dirty_rx[q] = 0; 404 priv->dirty_tx[q] = 0; 405 406 info->rx_ring_format(ndev, q); 407 408 memset(priv->tx_ring[q], 0, tx_ring_size); 409 /* Build TX ring buffer */ 410 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 411 i++, tx_desc++) { 412 tx_desc->die_dt = DT_EEMPTY; 413 if (num_tx_desc > 1) { 414 tx_desc++; 415 tx_desc->die_dt = DT_EEMPTY; 416 } 417 } 418 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 419 tx_desc->die_dt = DT_LINKFIX; /* type */ 420 421 /* RX descriptor base address for best effort */ 422 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 423 desc->die_dt = DT_LINKFIX; /* type */ 424 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 425 426 /* TX descriptor base address for best effort */ 427 desc = &priv->desc_bat[q]; 428 desc->die_dt = DT_LINKFIX; /* type */ 429 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 430 } 431 432 static void *ravb_alloc_rx_desc_gbeth(struct net_device *ndev, int q) 433 { 434 struct ravb_private *priv = netdev_priv(ndev); 435 unsigned int ring_size; 436 437 ring_size = sizeof(struct ravb_rx_desc) * (priv->num_rx_ring[q] + 1); 438 439 priv->gbeth_rx_ring = dma_alloc_coherent(ndev->dev.parent, ring_size, 440 &priv->rx_desc_dma[q], 441 GFP_KERNEL); 442 return priv->gbeth_rx_ring; 443 } 444 445 static void *ravb_alloc_rx_desc_rcar(struct net_device *ndev, int q) 446 { 447 struct ravb_private *priv = netdev_priv(ndev); 448 unsigned int ring_size; 449 450 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1); 451 452 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 453 &priv->rx_desc_dma[q], 454 GFP_KERNEL); 455 return priv->rx_ring[q]; 456 } 457 458 /* Init skb and descriptor buffer for Ethernet AVB */ 459 static int ravb_ring_init(struct net_device *ndev, int q) 460 { 461 struct ravb_private *priv = netdev_priv(ndev); 462 const struct ravb_hw_info *info = priv->info; 463 unsigned int num_tx_desc = priv->num_tx_desc; 464 unsigned int ring_size; 465 struct sk_buff *skb; 466 unsigned int i; 467 468 /* Allocate RX and TX skb rings */ 469 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q], 470 sizeof(*priv->rx_skb[q]), GFP_KERNEL); 471 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 472 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 473 if (!priv->rx_skb[q] || !priv->tx_skb[q]) 474 goto error; 475 476 for (i = 0; i < priv->num_rx_ring[q]; i++) { 477 skb = __netdev_alloc_skb(ndev, info->max_rx_len, GFP_KERNEL); 478 if (!skb) 479 goto error; 480 ravb_set_buffer_align(skb); 481 priv->rx_skb[q][i] = skb; 482 } 483 484 if (num_tx_desc > 1) { 485 /* Allocate rings for the aligned buffers */ 486 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 487 DPTR_ALIGN - 1, GFP_KERNEL); 488 if (!priv->tx_align[q]) 489 goto error; 490 } 491 492 /* Allocate all RX descriptors. */ 493 if (!info->alloc_rx_desc(ndev, q)) 494 goto error; 495 496 priv->dirty_rx[q] = 0; 497 498 /* Allocate all TX descriptors. */ 499 ring_size = sizeof(struct ravb_tx_desc) * 500 (priv->num_tx_ring[q] * num_tx_desc + 1); 501 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 502 &priv->tx_desc_dma[q], 503 GFP_KERNEL); 504 if (!priv->tx_ring[q]) 505 goto error; 506 507 return 0; 508 509 error: 510 ravb_ring_free(ndev, q); 511 512 return -ENOMEM; 513 } 514 515 static void ravb_emac_init_gbeth(struct net_device *ndev) 516 { 517 struct ravb_private *priv = netdev_priv(ndev); 518 519 if (priv->phy_interface == PHY_INTERFACE_MODE_MII) { 520 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35); 521 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0); 522 } else { 523 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_RGMII, CXR35); 524 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 525 CXR31_SEL_LINK0); 526 } 527 528 /* Receive frame limit set register */ 529 ravb_write(ndev, GBETH_RX_BUFF_MAX + ETH_FCS_LEN, RFLR); 530 531 /* EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through */ 532 ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) | 533 ECMR_TE | ECMR_RE | ECMR_RCPT | 534 ECMR_TXF | ECMR_RXF, ECMR); 535 536 ravb_set_rate_gbeth(ndev); 537 538 /* Set MAC address */ 539 ravb_write(ndev, 540 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 541 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 542 ravb_write(ndev, (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 543 544 /* E-MAC status register clear */ 545 ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR); 546 ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0); 547 548 /* E-MAC interrupt enable register */ 549 ravb_write(ndev, ECSIPR_ICDIP, ECSIPR); 550 } 551 552 static void ravb_emac_init_rcar(struct net_device *ndev) 553 { 554 /* Receive frame limit set register */ 555 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR); 556 557 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 558 ravb_write(ndev, ECMR_ZPF | ECMR_DM | 559 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 560 ECMR_TE | ECMR_RE, ECMR); 561 562 ravb_set_rate_rcar(ndev); 563 564 /* Set MAC address */ 565 ravb_write(ndev, 566 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 567 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 568 ravb_write(ndev, 569 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 570 571 /* E-MAC status register clear */ 572 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 573 574 /* E-MAC interrupt enable register */ 575 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 576 } 577 578 /* E-MAC init function */ 579 static void ravb_emac_init(struct net_device *ndev) 580 { 581 struct ravb_private *priv = netdev_priv(ndev); 582 const struct ravb_hw_info *info = priv->info; 583 584 info->emac_init(ndev); 585 } 586 587 static int ravb_dmac_init_gbeth(struct net_device *ndev) 588 { 589 int error; 590 591 error = ravb_ring_init(ndev, RAVB_BE); 592 if (error) 593 return error; 594 595 /* Descriptor format */ 596 ravb_ring_format(ndev, RAVB_BE); 597 598 /* Set DMAC RX */ 599 ravb_write(ndev, 0x60000000, RCR); 600 601 /* Set Max Frame Length (RTC) */ 602 ravb_write(ndev, 0x7ffc0000 | GBETH_RX_BUFF_MAX, RTC); 603 604 /* Set FIFO size */ 605 ravb_write(ndev, 0x00222200, TGC); 606 607 ravb_write(ndev, 0, TCCR); 608 609 /* Frame receive */ 610 ravb_write(ndev, RIC0_FRE0, RIC0); 611 /* Disable FIFO full warning */ 612 ravb_write(ndev, 0x0, RIC1); 613 /* Receive FIFO full error, descriptor empty */ 614 ravb_write(ndev, RIC2_QFE0 | RIC2_RFFE, RIC2); 615 616 ravb_write(ndev, TIC_FTE0, TIC); 617 618 return 0; 619 } 620 621 static int ravb_dmac_init_rcar(struct net_device *ndev) 622 { 623 struct ravb_private *priv = netdev_priv(ndev); 624 const struct ravb_hw_info *info = priv->info; 625 int error; 626 627 error = ravb_ring_init(ndev, RAVB_BE); 628 if (error) 629 return error; 630 error = ravb_ring_init(ndev, RAVB_NC); 631 if (error) { 632 ravb_ring_free(ndev, RAVB_BE); 633 return error; 634 } 635 636 /* Descriptor format */ 637 ravb_ring_format(ndev, RAVB_BE); 638 ravb_ring_format(ndev, RAVB_NC); 639 640 /* Set AVB RX */ 641 ravb_write(ndev, 642 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 643 644 /* Set FIFO size */ 645 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC); 646 647 /* Timestamp enable */ 648 ravb_write(ndev, TCCR_TFEN, TCCR); 649 650 /* Interrupt init: */ 651 if (info->multi_irqs) { 652 /* Clear DIL.DPLx */ 653 ravb_write(ndev, 0, DIL); 654 /* Set queue specific interrupt */ 655 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 656 } 657 /* Frame receive */ 658 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 659 /* Disable FIFO full warning */ 660 ravb_write(ndev, 0, RIC1); 661 /* Receive FIFO full error, descriptor empty */ 662 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 663 /* Frame transmitted, timestamp FIFO updated */ 664 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 665 666 return 0; 667 } 668 669 /* Device init function for Ethernet AVB */ 670 static int ravb_dmac_init(struct net_device *ndev) 671 { 672 struct ravb_private *priv = netdev_priv(ndev); 673 const struct ravb_hw_info *info = priv->info; 674 int error; 675 676 /* Set CONFIG mode */ 677 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 678 if (error) 679 return error; 680 681 error = info->dmac_init(ndev); 682 if (error) 683 return error; 684 685 /* Setting the control will start the AVB-DMAC process. */ 686 return ravb_set_opmode(ndev, CCC_OPC_OPERATION); 687 } 688 689 static void ravb_get_tx_tstamp(struct net_device *ndev) 690 { 691 struct ravb_private *priv = netdev_priv(ndev); 692 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 693 struct skb_shared_hwtstamps shhwtstamps; 694 struct sk_buff *skb; 695 struct timespec64 ts; 696 u16 tag, tfa_tag; 697 int count; 698 u32 tfa2; 699 700 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 701 while (count--) { 702 tfa2 = ravb_read(ndev, TFA2); 703 tfa_tag = (tfa2 & TFA2_TST) >> 16; 704 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 705 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 706 ravb_read(ndev, TFA1); 707 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 708 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 709 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 710 list) { 711 skb = ts_skb->skb; 712 tag = ts_skb->tag; 713 list_del(&ts_skb->list); 714 kfree(ts_skb); 715 if (tag == tfa_tag) { 716 skb_tstamp_tx(skb, &shhwtstamps); 717 dev_consume_skb_any(skb); 718 break; 719 } else { 720 dev_kfree_skb_any(skb); 721 } 722 } 723 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 724 } 725 } 726 727 static void ravb_rx_csum(struct sk_buff *skb) 728 { 729 u8 *hw_csum; 730 731 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes 732 * appended to packet data 733 */ 734 if (unlikely(skb->len < sizeof(__sum16))) 735 return; 736 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); 737 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 738 skb->ip_summed = CHECKSUM_COMPLETE; 739 skb_trim(skb, skb->len - sizeof(__sum16)); 740 } 741 742 static struct sk_buff *ravb_get_skb_gbeth(struct net_device *ndev, int entry, 743 struct ravb_rx_desc *desc) 744 { 745 struct ravb_private *priv = netdev_priv(ndev); 746 struct sk_buff *skb; 747 748 skb = priv->rx_skb[RAVB_BE][entry]; 749 priv->rx_skb[RAVB_BE][entry] = NULL; 750 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 751 ALIGN(GBETH_RX_BUFF_MAX, 16), DMA_FROM_DEVICE); 752 753 return skb; 754 } 755 756 /* Packet receive function for Gigabit Ethernet */ 757 static bool ravb_rx_gbeth(struct net_device *ndev, int *quota, int q) 758 { 759 struct ravb_private *priv = netdev_priv(ndev); 760 const struct ravb_hw_info *info = priv->info; 761 struct net_device_stats *stats; 762 struct ravb_rx_desc *desc; 763 struct sk_buff *skb; 764 dma_addr_t dma_addr; 765 u8 desc_status; 766 int boguscnt; 767 u16 pkt_len; 768 u8 die_dt; 769 int entry; 770 int limit; 771 772 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 773 boguscnt = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q]; 774 stats = &priv->stats[q]; 775 776 boguscnt = min(boguscnt, *quota); 777 limit = boguscnt; 778 desc = &priv->gbeth_rx_ring[entry]; 779 while (desc->die_dt != DT_FEMPTY) { 780 /* Descriptor type must be checked before all other reads */ 781 dma_rmb(); 782 desc_status = desc->msc; 783 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 784 785 if (--boguscnt < 0) 786 break; 787 788 /* We use 0-byte descriptors to mark the DMA mapping errors */ 789 if (!pkt_len) 790 continue; 791 792 if (desc_status & MSC_MC) 793 stats->multicast++; 794 795 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | MSC_CEEF)) { 796 stats->rx_errors++; 797 if (desc_status & MSC_CRC) 798 stats->rx_crc_errors++; 799 if (desc_status & MSC_RFE) 800 stats->rx_frame_errors++; 801 if (desc_status & (MSC_RTLF | MSC_RTSF)) 802 stats->rx_length_errors++; 803 if (desc_status & MSC_CEEF) 804 stats->rx_missed_errors++; 805 } else { 806 die_dt = desc->die_dt & 0xF0; 807 switch (die_dt) { 808 case DT_FSINGLE: 809 skb = ravb_get_skb_gbeth(ndev, entry, desc); 810 skb_put(skb, pkt_len); 811 skb->protocol = eth_type_trans(skb, ndev); 812 napi_gro_receive(&priv->napi[q], skb); 813 stats->rx_packets++; 814 stats->rx_bytes += pkt_len; 815 break; 816 case DT_FSTART: 817 priv->rx_1st_skb = ravb_get_skb_gbeth(ndev, entry, desc); 818 skb_put(priv->rx_1st_skb, pkt_len); 819 break; 820 case DT_FMID: 821 skb = ravb_get_skb_gbeth(ndev, entry, desc); 822 skb_copy_to_linear_data_offset(priv->rx_1st_skb, 823 priv->rx_1st_skb->len, 824 skb->data, 825 pkt_len); 826 skb_put(priv->rx_1st_skb, pkt_len); 827 dev_kfree_skb(skb); 828 break; 829 case DT_FEND: 830 skb = ravb_get_skb_gbeth(ndev, entry, desc); 831 skb_copy_to_linear_data_offset(priv->rx_1st_skb, 832 priv->rx_1st_skb->len, 833 skb->data, 834 pkt_len); 835 skb_put(priv->rx_1st_skb, pkt_len); 836 dev_kfree_skb(skb); 837 priv->rx_1st_skb->protocol = 838 eth_type_trans(priv->rx_1st_skb, ndev); 839 napi_gro_receive(&priv->napi[q], 840 priv->rx_1st_skb); 841 stats->rx_packets++; 842 stats->rx_bytes += pkt_len; 843 break; 844 } 845 } 846 847 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 848 desc = &priv->gbeth_rx_ring[entry]; 849 } 850 851 /* Refill the RX ring buffers. */ 852 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 853 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 854 desc = &priv->gbeth_rx_ring[entry]; 855 desc->ds_cc = cpu_to_le16(GBETH_RX_DESC_DATA_SIZE); 856 857 if (!priv->rx_skb[q][entry]) { 858 skb = netdev_alloc_skb(ndev, info->max_rx_len); 859 if (!skb) 860 break; 861 ravb_set_buffer_align(skb); 862 dma_addr = dma_map_single(ndev->dev.parent, 863 skb->data, 864 GBETH_RX_BUFF_MAX, 865 DMA_FROM_DEVICE); 866 skb_checksum_none_assert(skb); 867 /* We just set the data size to 0 for a failed mapping 868 * which should prevent DMA from happening... 869 */ 870 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 871 desc->ds_cc = cpu_to_le16(0); 872 desc->dptr = cpu_to_le32(dma_addr); 873 priv->rx_skb[q][entry] = skb; 874 } 875 /* Descriptor type must be set after all the above writes */ 876 dma_wmb(); 877 desc->die_dt = DT_FEMPTY; 878 } 879 880 *quota -= limit - (++boguscnt); 881 882 return boguscnt <= 0; 883 } 884 885 /* Packet receive function for Ethernet AVB */ 886 static bool ravb_rx_rcar(struct net_device *ndev, int *quota, int q) 887 { 888 struct ravb_private *priv = netdev_priv(ndev); 889 const struct ravb_hw_info *info = priv->info; 890 int entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 891 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) - 892 priv->cur_rx[q]; 893 struct net_device_stats *stats = &priv->stats[q]; 894 struct ravb_ex_rx_desc *desc; 895 struct sk_buff *skb; 896 dma_addr_t dma_addr; 897 struct timespec64 ts; 898 u8 desc_status; 899 u16 pkt_len; 900 int limit; 901 902 boguscnt = min(boguscnt, *quota); 903 limit = boguscnt; 904 desc = &priv->rx_ring[q][entry]; 905 while (desc->die_dt != DT_FEMPTY) { 906 /* Descriptor type must be checked before all other reads */ 907 dma_rmb(); 908 desc_status = desc->msc; 909 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 910 911 if (--boguscnt < 0) 912 break; 913 914 /* We use 0-byte descriptors to mark the DMA mapping errors */ 915 if (!pkt_len) 916 continue; 917 918 if (desc_status & MSC_MC) 919 stats->multicast++; 920 921 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 922 MSC_CEEF)) { 923 stats->rx_errors++; 924 if (desc_status & MSC_CRC) 925 stats->rx_crc_errors++; 926 if (desc_status & MSC_RFE) 927 stats->rx_frame_errors++; 928 if (desc_status & (MSC_RTLF | MSC_RTSF)) 929 stats->rx_length_errors++; 930 if (desc_status & MSC_CEEF) 931 stats->rx_missed_errors++; 932 } else { 933 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 934 935 skb = priv->rx_skb[q][entry]; 936 priv->rx_skb[q][entry] = NULL; 937 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 938 RX_BUF_SZ, 939 DMA_FROM_DEVICE); 940 get_ts &= (q == RAVB_NC) ? 941 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 942 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 943 if (get_ts) { 944 struct skb_shared_hwtstamps *shhwtstamps; 945 946 shhwtstamps = skb_hwtstamps(skb); 947 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 948 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 949 32) | le32_to_cpu(desc->ts_sl); 950 ts.tv_nsec = le32_to_cpu(desc->ts_n); 951 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 952 } 953 954 skb_put(skb, pkt_len); 955 skb->protocol = eth_type_trans(skb, ndev); 956 if (ndev->features & NETIF_F_RXCSUM) 957 ravb_rx_csum(skb); 958 napi_gro_receive(&priv->napi[q], skb); 959 stats->rx_packets++; 960 stats->rx_bytes += pkt_len; 961 } 962 963 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q]; 964 desc = &priv->rx_ring[q][entry]; 965 } 966 967 /* Refill the RX ring buffers. */ 968 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) { 969 entry = priv->dirty_rx[q] % priv->num_rx_ring[q]; 970 desc = &priv->rx_ring[q][entry]; 971 desc->ds_cc = cpu_to_le16(RX_BUF_SZ); 972 973 if (!priv->rx_skb[q][entry]) { 974 skb = netdev_alloc_skb(ndev, info->max_rx_len); 975 if (!skb) 976 break; /* Better luck next round. */ 977 ravb_set_buffer_align(skb); 978 dma_addr = dma_map_single(ndev->dev.parent, skb->data, 979 le16_to_cpu(desc->ds_cc), 980 DMA_FROM_DEVICE); 981 skb_checksum_none_assert(skb); 982 /* We just set the data size to 0 for a failed mapping 983 * which should prevent DMA from happening... 984 */ 985 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 986 desc->ds_cc = cpu_to_le16(0); 987 desc->dptr = cpu_to_le32(dma_addr); 988 priv->rx_skb[q][entry] = skb; 989 } 990 /* Descriptor type must be set after all the above writes */ 991 dma_wmb(); 992 desc->die_dt = DT_FEMPTY; 993 } 994 995 *quota -= limit - (++boguscnt); 996 997 return boguscnt <= 0; 998 } 999 1000 /* Packet receive function for Ethernet AVB */ 1001 static bool ravb_rx(struct net_device *ndev, int *quota, int q) 1002 { 1003 struct ravb_private *priv = netdev_priv(ndev); 1004 const struct ravb_hw_info *info = priv->info; 1005 1006 return info->receive(ndev, quota, q); 1007 } 1008 1009 static void ravb_rcv_snd_disable(struct net_device *ndev) 1010 { 1011 /* Disable TX and RX */ 1012 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 1013 } 1014 1015 static void ravb_rcv_snd_enable(struct net_device *ndev) 1016 { 1017 /* Enable TX and RX */ 1018 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 1019 } 1020 1021 /* function for waiting dma process finished */ 1022 static int ravb_stop_dma(struct net_device *ndev) 1023 { 1024 struct ravb_private *priv = netdev_priv(ndev); 1025 const struct ravb_hw_info *info = priv->info; 1026 int error; 1027 1028 /* Wait for stopping the hardware TX process */ 1029 error = ravb_wait(ndev, TCCR, info->tccr_mask, 0); 1030 1031 if (error) 1032 return error; 1033 1034 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 1035 0); 1036 if (error) 1037 return error; 1038 1039 /* Stop the E-MAC's RX/TX processes. */ 1040 ravb_rcv_snd_disable(ndev); 1041 1042 /* Wait for stopping the RX DMA process */ 1043 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 1044 if (error) 1045 return error; 1046 1047 /* Stop AVB-DMAC process */ 1048 return ravb_set_opmode(ndev, CCC_OPC_CONFIG); 1049 } 1050 1051 /* E-MAC interrupt handler */ 1052 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 1053 { 1054 struct ravb_private *priv = netdev_priv(ndev); 1055 u32 ecsr, psr; 1056 1057 ecsr = ravb_read(ndev, ECSR); 1058 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 1059 1060 if (ecsr & ECSR_MPD) 1061 pm_wakeup_event(&priv->pdev->dev, 0); 1062 if (ecsr & ECSR_ICD) 1063 ndev->stats.tx_carrier_errors++; 1064 if (ecsr & ECSR_LCHNG) { 1065 /* Link changed */ 1066 if (priv->no_avb_link) 1067 return; 1068 psr = ravb_read(ndev, PSR); 1069 if (priv->avb_link_active_low) 1070 psr ^= PSR_LMON; 1071 if (!(psr & PSR_LMON)) { 1072 /* DIsable RX and TX */ 1073 ravb_rcv_snd_disable(ndev); 1074 } else { 1075 /* Enable RX and TX */ 1076 ravb_rcv_snd_enable(ndev); 1077 } 1078 } 1079 } 1080 1081 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 1082 { 1083 struct net_device *ndev = dev_id; 1084 struct ravb_private *priv = netdev_priv(ndev); 1085 struct device *dev = &priv->pdev->dev; 1086 irqreturn_t result = IRQ_HANDLED; 1087 1088 pm_runtime_get_noresume(dev); 1089 1090 if (unlikely(!pm_runtime_active(dev))) { 1091 result = IRQ_NONE; 1092 goto out_rpm_put; 1093 } 1094 1095 spin_lock(&priv->lock); 1096 ravb_emac_interrupt_unlocked(ndev); 1097 spin_unlock(&priv->lock); 1098 1099 out_rpm_put: 1100 pm_runtime_put_noidle(dev); 1101 return result; 1102 } 1103 1104 /* Error interrupt handler */ 1105 static void ravb_error_interrupt(struct net_device *ndev) 1106 { 1107 struct ravb_private *priv = netdev_priv(ndev); 1108 u32 eis, ris2; 1109 1110 eis = ravb_read(ndev, EIS); 1111 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS); 1112 if (eis & EIS_QFS) { 1113 ris2 = ravb_read(ndev, RIS2); 1114 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_QFF1 | RIS2_RFFF | RIS2_RESERVED), 1115 RIS2); 1116 1117 /* Receive Descriptor Empty int */ 1118 if (ris2 & RIS2_QFF0) 1119 priv->stats[RAVB_BE].rx_over_errors++; 1120 1121 /* Receive Descriptor Empty int */ 1122 if (ris2 & RIS2_QFF1) 1123 priv->stats[RAVB_NC].rx_over_errors++; 1124 1125 /* Receive FIFO Overflow int */ 1126 if (ris2 & RIS2_RFFF) 1127 priv->rx_fifo_errors++; 1128 } 1129 } 1130 1131 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 1132 { 1133 struct ravb_private *priv = netdev_priv(ndev); 1134 const struct ravb_hw_info *info = priv->info; 1135 u32 ris0 = ravb_read(ndev, RIS0); 1136 u32 ric0 = ravb_read(ndev, RIC0); 1137 u32 tis = ravb_read(ndev, TIS); 1138 u32 tic = ravb_read(ndev, TIC); 1139 1140 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 1141 if (napi_schedule_prep(&priv->napi[q])) { 1142 /* Mask RX and TX interrupts */ 1143 if (!info->irq_en_dis) { 1144 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 1145 ravb_write(ndev, tic & ~BIT(q), TIC); 1146 } else { 1147 ravb_write(ndev, BIT(q), RID0); 1148 ravb_write(ndev, BIT(q), TID); 1149 } 1150 __napi_schedule(&priv->napi[q]); 1151 } else { 1152 netdev_warn(ndev, 1153 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 1154 ris0, ric0); 1155 netdev_warn(ndev, 1156 " tx status 0x%08x, tx mask 0x%08x.\n", 1157 tis, tic); 1158 } 1159 return true; 1160 } 1161 return false; 1162 } 1163 1164 static bool ravb_timestamp_interrupt(struct net_device *ndev) 1165 { 1166 u32 tis = ravb_read(ndev, TIS); 1167 1168 if (tis & TIS_TFUF) { 1169 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS); 1170 ravb_get_tx_tstamp(ndev); 1171 return true; 1172 } 1173 return false; 1174 } 1175 1176 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 1177 { 1178 struct net_device *ndev = dev_id; 1179 struct ravb_private *priv = netdev_priv(ndev); 1180 const struct ravb_hw_info *info = priv->info; 1181 struct device *dev = &priv->pdev->dev; 1182 irqreturn_t result = IRQ_NONE; 1183 u32 iss; 1184 1185 pm_runtime_get_noresume(dev); 1186 1187 if (unlikely(!pm_runtime_active(dev))) 1188 goto out_rpm_put; 1189 1190 spin_lock(&priv->lock); 1191 /* Get interrupt status */ 1192 iss = ravb_read(ndev, ISS); 1193 1194 /* Received and transmitted interrupts */ 1195 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 1196 int q; 1197 1198 /* Timestamp updated */ 1199 if (ravb_timestamp_interrupt(ndev)) 1200 result = IRQ_HANDLED; 1201 1202 /* Network control and best effort queue RX/TX */ 1203 if (info->nc_queues) { 1204 for (q = RAVB_NC; q >= RAVB_BE; q--) { 1205 if (ravb_queue_interrupt(ndev, q)) 1206 result = IRQ_HANDLED; 1207 } 1208 } else { 1209 if (ravb_queue_interrupt(ndev, RAVB_BE)) 1210 result = IRQ_HANDLED; 1211 } 1212 } 1213 1214 /* E-MAC status summary */ 1215 if (iss & ISS_MS) { 1216 ravb_emac_interrupt_unlocked(ndev); 1217 result = IRQ_HANDLED; 1218 } 1219 1220 /* Error status summary */ 1221 if (iss & ISS_ES) { 1222 ravb_error_interrupt(ndev); 1223 result = IRQ_HANDLED; 1224 } 1225 1226 /* gPTP interrupt status summary */ 1227 if (iss & ISS_CGIS) { 1228 ravb_ptp_interrupt(ndev); 1229 result = IRQ_HANDLED; 1230 } 1231 1232 spin_unlock(&priv->lock); 1233 1234 out_rpm_put: 1235 pm_runtime_put_noidle(dev); 1236 return result; 1237 } 1238 1239 /* Timestamp/Error/gPTP interrupt handler */ 1240 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 1241 { 1242 struct net_device *ndev = dev_id; 1243 struct ravb_private *priv = netdev_priv(ndev); 1244 struct device *dev = &priv->pdev->dev; 1245 irqreturn_t result = IRQ_NONE; 1246 u32 iss; 1247 1248 pm_runtime_get_noresume(dev); 1249 1250 if (unlikely(!pm_runtime_active(dev))) 1251 goto out_rpm_put; 1252 1253 spin_lock(&priv->lock); 1254 /* Get interrupt status */ 1255 iss = ravb_read(ndev, ISS); 1256 1257 /* Timestamp updated */ 1258 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 1259 result = IRQ_HANDLED; 1260 1261 /* Error status summary */ 1262 if (iss & ISS_ES) { 1263 ravb_error_interrupt(ndev); 1264 result = IRQ_HANDLED; 1265 } 1266 1267 /* gPTP interrupt status summary */ 1268 if (iss & ISS_CGIS) { 1269 ravb_ptp_interrupt(ndev); 1270 result = IRQ_HANDLED; 1271 } 1272 1273 spin_unlock(&priv->lock); 1274 1275 out_rpm_put: 1276 pm_runtime_put_noidle(dev); 1277 return result; 1278 } 1279 1280 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 1281 { 1282 struct net_device *ndev = dev_id; 1283 struct ravb_private *priv = netdev_priv(ndev); 1284 struct device *dev = &priv->pdev->dev; 1285 irqreturn_t result = IRQ_NONE; 1286 1287 pm_runtime_get_noresume(dev); 1288 1289 if (unlikely(!pm_runtime_active(dev))) 1290 goto out_rpm_put; 1291 1292 spin_lock(&priv->lock); 1293 1294 /* Network control/Best effort queue RX/TX */ 1295 if (ravb_queue_interrupt(ndev, q)) 1296 result = IRQ_HANDLED; 1297 1298 spin_unlock(&priv->lock); 1299 1300 out_rpm_put: 1301 pm_runtime_put_noidle(dev); 1302 return result; 1303 } 1304 1305 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 1306 { 1307 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 1308 } 1309 1310 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 1311 { 1312 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 1313 } 1314 1315 static int ravb_poll(struct napi_struct *napi, int budget) 1316 { 1317 struct net_device *ndev = napi->dev; 1318 struct ravb_private *priv = netdev_priv(ndev); 1319 const struct ravb_hw_info *info = priv->info; 1320 unsigned long flags; 1321 int q = napi - priv->napi; 1322 int mask = BIT(q); 1323 int quota = budget; 1324 1325 /* Processing RX Descriptor Ring */ 1326 /* Clear RX interrupt */ 1327 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0); 1328 if (ravb_rx(ndev, "a, q)) 1329 goto out; 1330 1331 /* Processing TX Descriptor Ring */ 1332 spin_lock_irqsave(&priv->lock, flags); 1333 /* Clear TX interrupt */ 1334 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS); 1335 ravb_tx_free(ndev, q, true); 1336 netif_wake_subqueue(ndev, q); 1337 spin_unlock_irqrestore(&priv->lock, flags); 1338 1339 napi_complete(napi); 1340 1341 /* Re-enable RX/TX interrupts */ 1342 spin_lock_irqsave(&priv->lock, flags); 1343 if (!info->irq_en_dis) { 1344 ravb_modify(ndev, RIC0, mask, mask); 1345 ravb_modify(ndev, TIC, mask, mask); 1346 } else { 1347 ravb_write(ndev, mask, RIE0); 1348 ravb_write(ndev, mask, TIE); 1349 } 1350 spin_unlock_irqrestore(&priv->lock, flags); 1351 1352 /* Receive error message handling */ 1353 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 1354 if (info->nc_queues) 1355 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 1356 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 1357 ndev->stats.rx_over_errors = priv->rx_over_errors; 1358 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 1359 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 1360 out: 1361 return budget - quota; 1362 } 1363 1364 static void ravb_set_duplex_gbeth(struct net_device *ndev) 1365 { 1366 struct ravb_private *priv = netdev_priv(ndev); 1367 1368 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex > 0 ? ECMR_DM : 0); 1369 } 1370 1371 /* PHY state control function */ 1372 static void ravb_adjust_link(struct net_device *ndev) 1373 { 1374 struct ravb_private *priv = netdev_priv(ndev); 1375 const struct ravb_hw_info *info = priv->info; 1376 struct phy_device *phydev = ndev->phydev; 1377 bool new_state = false; 1378 unsigned long flags; 1379 1380 spin_lock_irqsave(&priv->lock, flags); 1381 1382 /* Disable TX and RX right over here, if E-MAC change is ignored */ 1383 if (priv->no_avb_link) 1384 ravb_rcv_snd_disable(ndev); 1385 1386 if (phydev->link) { 1387 if (info->half_duplex && phydev->duplex != priv->duplex) { 1388 new_state = true; 1389 priv->duplex = phydev->duplex; 1390 ravb_set_duplex_gbeth(ndev); 1391 } 1392 1393 if (phydev->speed != priv->speed) { 1394 new_state = true; 1395 priv->speed = phydev->speed; 1396 info->set_rate(ndev); 1397 } 1398 if (!priv->link) { 1399 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 1400 new_state = true; 1401 priv->link = phydev->link; 1402 } 1403 } else if (priv->link) { 1404 new_state = true; 1405 priv->link = 0; 1406 priv->speed = 0; 1407 if (info->half_duplex) 1408 priv->duplex = -1; 1409 } 1410 1411 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1412 if (priv->no_avb_link && phydev->link) 1413 ravb_rcv_snd_enable(ndev); 1414 1415 spin_unlock_irqrestore(&priv->lock, flags); 1416 1417 if (new_state && netif_msg_link(priv)) 1418 phy_print_status(phydev); 1419 } 1420 1421 /* PHY init function */ 1422 static int ravb_phy_init(struct net_device *ndev) 1423 { 1424 struct device_node *np = ndev->dev.parent->of_node; 1425 struct ravb_private *priv = netdev_priv(ndev); 1426 const struct ravb_hw_info *info = priv->info; 1427 struct phy_device *phydev; 1428 struct device_node *pn; 1429 phy_interface_t iface; 1430 int err; 1431 1432 priv->link = 0; 1433 priv->speed = 0; 1434 priv->duplex = -1; 1435 1436 /* Try connecting to PHY */ 1437 pn = of_parse_phandle(np, "phy-handle", 0); 1438 if (!pn) { 1439 /* In the case of a fixed PHY, the DT node associated 1440 * to the PHY is the Ethernet MAC DT node. 1441 */ 1442 if (of_phy_is_fixed_link(np)) { 1443 err = of_phy_register_fixed_link(np); 1444 if (err) 1445 return err; 1446 } 1447 pn = of_node_get(np); 1448 } 1449 1450 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII 1451 : priv->phy_interface; 1452 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface); 1453 of_node_put(pn); 1454 if (!phydev) { 1455 netdev_err(ndev, "failed to connect PHY\n"); 1456 err = -ENOENT; 1457 goto err_deregister_fixed_link; 1458 } 1459 1460 if (!info->half_duplex) { 1461 /* 10BASE, Pause and Asym Pause is not supported */ 1462 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1463 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1464 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT); 1465 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 1466 1467 /* Half Duplex is not supported */ 1468 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1469 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1470 } 1471 1472 phy_attached_info(phydev); 1473 1474 return 0; 1475 1476 err_deregister_fixed_link: 1477 if (of_phy_is_fixed_link(np)) 1478 of_phy_deregister_fixed_link(np); 1479 1480 return err; 1481 } 1482 1483 /* PHY control start function */ 1484 static int ravb_phy_start(struct net_device *ndev) 1485 { 1486 int error; 1487 1488 error = ravb_phy_init(ndev); 1489 if (error) 1490 return error; 1491 1492 phy_start(ndev->phydev); 1493 1494 return 0; 1495 } 1496 1497 static u32 ravb_get_msglevel(struct net_device *ndev) 1498 { 1499 struct ravb_private *priv = netdev_priv(ndev); 1500 1501 return priv->msg_enable; 1502 } 1503 1504 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1505 { 1506 struct ravb_private *priv = netdev_priv(ndev); 1507 1508 priv->msg_enable = value; 1509 } 1510 1511 static const char ravb_gstrings_stats_gbeth[][ETH_GSTRING_LEN] = { 1512 "rx_queue_0_current", 1513 "tx_queue_0_current", 1514 "rx_queue_0_dirty", 1515 "tx_queue_0_dirty", 1516 "rx_queue_0_packets", 1517 "tx_queue_0_packets", 1518 "rx_queue_0_bytes", 1519 "tx_queue_0_bytes", 1520 "rx_queue_0_mcast_packets", 1521 "rx_queue_0_errors", 1522 "rx_queue_0_crc_errors", 1523 "rx_queue_0_frame_errors", 1524 "rx_queue_0_length_errors", 1525 "rx_queue_0_csum_offload_errors", 1526 "rx_queue_0_over_errors", 1527 }; 1528 1529 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1530 "rx_queue_0_current", 1531 "tx_queue_0_current", 1532 "rx_queue_0_dirty", 1533 "tx_queue_0_dirty", 1534 "rx_queue_0_packets", 1535 "tx_queue_0_packets", 1536 "rx_queue_0_bytes", 1537 "tx_queue_0_bytes", 1538 "rx_queue_0_mcast_packets", 1539 "rx_queue_0_errors", 1540 "rx_queue_0_crc_errors", 1541 "rx_queue_0_frame_errors", 1542 "rx_queue_0_length_errors", 1543 "rx_queue_0_missed_errors", 1544 "rx_queue_0_over_errors", 1545 1546 "rx_queue_1_current", 1547 "tx_queue_1_current", 1548 "rx_queue_1_dirty", 1549 "tx_queue_1_dirty", 1550 "rx_queue_1_packets", 1551 "tx_queue_1_packets", 1552 "rx_queue_1_bytes", 1553 "tx_queue_1_bytes", 1554 "rx_queue_1_mcast_packets", 1555 "rx_queue_1_errors", 1556 "rx_queue_1_crc_errors", 1557 "rx_queue_1_frame_errors", 1558 "rx_queue_1_length_errors", 1559 "rx_queue_1_missed_errors", 1560 "rx_queue_1_over_errors", 1561 }; 1562 1563 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1564 { 1565 struct ravb_private *priv = netdev_priv(netdev); 1566 const struct ravb_hw_info *info = priv->info; 1567 1568 switch (sset) { 1569 case ETH_SS_STATS: 1570 return info->stats_len; 1571 default: 1572 return -EOPNOTSUPP; 1573 } 1574 } 1575 1576 static void ravb_get_ethtool_stats(struct net_device *ndev, 1577 struct ethtool_stats *estats, u64 *data) 1578 { 1579 struct ravb_private *priv = netdev_priv(ndev); 1580 const struct ravb_hw_info *info = priv->info; 1581 int num_rx_q; 1582 int i = 0; 1583 int q; 1584 1585 num_rx_q = info->nc_queues ? NUM_RX_QUEUE : 1; 1586 /* Device-specific stats */ 1587 for (q = RAVB_BE; q < num_rx_q; q++) { 1588 struct net_device_stats *stats = &priv->stats[q]; 1589 1590 data[i++] = priv->cur_rx[q]; 1591 data[i++] = priv->cur_tx[q]; 1592 data[i++] = priv->dirty_rx[q]; 1593 data[i++] = priv->dirty_tx[q]; 1594 data[i++] = stats->rx_packets; 1595 data[i++] = stats->tx_packets; 1596 data[i++] = stats->rx_bytes; 1597 data[i++] = stats->tx_bytes; 1598 data[i++] = stats->multicast; 1599 data[i++] = stats->rx_errors; 1600 data[i++] = stats->rx_crc_errors; 1601 data[i++] = stats->rx_frame_errors; 1602 data[i++] = stats->rx_length_errors; 1603 data[i++] = stats->rx_missed_errors; 1604 data[i++] = stats->rx_over_errors; 1605 } 1606 } 1607 1608 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1609 { 1610 struct ravb_private *priv = netdev_priv(ndev); 1611 const struct ravb_hw_info *info = priv->info; 1612 1613 switch (stringset) { 1614 case ETH_SS_STATS: 1615 memcpy(data, info->gstrings_stats, info->gstrings_size); 1616 break; 1617 } 1618 } 1619 1620 static void ravb_get_ringparam(struct net_device *ndev, 1621 struct ethtool_ringparam *ring, 1622 struct kernel_ethtool_ringparam *kernel_ring, 1623 struct netlink_ext_ack *extack) 1624 { 1625 struct ravb_private *priv = netdev_priv(ndev); 1626 1627 ring->rx_max_pending = BE_RX_RING_MAX; 1628 ring->tx_max_pending = BE_TX_RING_MAX; 1629 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1630 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1631 } 1632 1633 static int ravb_set_ringparam(struct net_device *ndev, 1634 struct ethtool_ringparam *ring, 1635 struct kernel_ethtool_ringparam *kernel_ring, 1636 struct netlink_ext_ack *extack) 1637 { 1638 struct ravb_private *priv = netdev_priv(ndev); 1639 const struct ravb_hw_info *info = priv->info; 1640 int error; 1641 1642 if (ring->tx_pending > BE_TX_RING_MAX || 1643 ring->rx_pending > BE_RX_RING_MAX || 1644 ring->tx_pending < BE_TX_RING_MIN || 1645 ring->rx_pending < BE_RX_RING_MIN) 1646 return -EINVAL; 1647 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1648 return -EINVAL; 1649 1650 if (netif_running(ndev)) { 1651 netif_device_detach(ndev); 1652 /* Stop PTP Clock driver */ 1653 if (info->gptp) 1654 ravb_ptp_stop(ndev); 1655 /* Wait for DMA stopping */ 1656 error = ravb_stop_dma(ndev); 1657 if (error) { 1658 netdev_err(ndev, 1659 "cannot set ringparam! Any AVB processes are still running?\n"); 1660 return error; 1661 } 1662 synchronize_irq(ndev->irq); 1663 1664 /* Free all the skb's in the RX queue and the DMA buffers. */ 1665 ravb_ring_free(ndev, RAVB_BE); 1666 if (info->nc_queues) 1667 ravb_ring_free(ndev, RAVB_NC); 1668 } 1669 1670 /* Set new parameters */ 1671 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1672 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1673 1674 if (netif_running(ndev)) { 1675 error = ravb_dmac_init(ndev); 1676 if (error) { 1677 netdev_err(ndev, 1678 "%s: ravb_dmac_init() failed, error %d\n", 1679 __func__, error); 1680 return error; 1681 } 1682 1683 ravb_emac_init(ndev); 1684 1685 /* Initialise PTP Clock driver */ 1686 if (info->gptp) 1687 ravb_ptp_init(ndev, priv->pdev); 1688 1689 netif_device_attach(ndev); 1690 } 1691 1692 return 0; 1693 } 1694 1695 static int ravb_get_ts_info(struct net_device *ndev, 1696 struct ethtool_ts_info *info) 1697 { 1698 struct ravb_private *priv = netdev_priv(ndev); 1699 const struct ravb_hw_info *hw_info = priv->info; 1700 1701 info->so_timestamping = 1702 SOF_TIMESTAMPING_TX_SOFTWARE | 1703 SOF_TIMESTAMPING_RX_SOFTWARE | 1704 SOF_TIMESTAMPING_SOFTWARE | 1705 SOF_TIMESTAMPING_TX_HARDWARE | 1706 SOF_TIMESTAMPING_RX_HARDWARE | 1707 SOF_TIMESTAMPING_RAW_HARDWARE; 1708 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1709 info->rx_filters = 1710 (1 << HWTSTAMP_FILTER_NONE) | 1711 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1712 (1 << HWTSTAMP_FILTER_ALL); 1713 if (hw_info->gptp || hw_info->ccc_gac) 1714 info->phc_index = ptp_clock_index(priv->ptp.clock); 1715 1716 return 0; 1717 } 1718 1719 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1720 { 1721 struct ravb_private *priv = netdev_priv(ndev); 1722 1723 wol->supported = WAKE_MAGIC; 1724 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1725 } 1726 1727 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1728 { 1729 struct ravb_private *priv = netdev_priv(ndev); 1730 const struct ravb_hw_info *info = priv->info; 1731 1732 if (!info->magic_pkt || (wol->wolopts & ~WAKE_MAGIC)) 1733 return -EOPNOTSUPP; 1734 1735 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1736 1737 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1738 1739 return 0; 1740 } 1741 1742 static const struct ethtool_ops ravb_ethtool_ops = { 1743 .nway_reset = phy_ethtool_nway_reset, 1744 .get_msglevel = ravb_get_msglevel, 1745 .set_msglevel = ravb_set_msglevel, 1746 .get_link = ethtool_op_get_link, 1747 .get_strings = ravb_get_strings, 1748 .get_ethtool_stats = ravb_get_ethtool_stats, 1749 .get_sset_count = ravb_get_sset_count, 1750 .get_ringparam = ravb_get_ringparam, 1751 .set_ringparam = ravb_set_ringparam, 1752 .get_ts_info = ravb_get_ts_info, 1753 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1754 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1755 .get_wol = ravb_get_wol, 1756 .set_wol = ravb_set_wol, 1757 }; 1758 1759 static int ravb_set_config_mode(struct net_device *ndev) 1760 { 1761 struct ravb_private *priv = netdev_priv(ndev); 1762 const struct ravb_hw_info *info = priv->info; 1763 int error; 1764 1765 if (info->gptp) { 1766 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 1767 if (error) 1768 return error; 1769 /* Set CSEL value */ 1770 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 1771 } else if (info->ccc_gac) { 1772 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG | CCC_GAC | CCC_CSEL_HPB); 1773 } else { 1774 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 1775 } 1776 1777 return error; 1778 } 1779 1780 static void ravb_set_gti(struct net_device *ndev) 1781 { 1782 struct ravb_private *priv = netdev_priv(ndev); 1783 const struct ravb_hw_info *info = priv->info; 1784 1785 if (!(info->gptp || info->ccc_gac)) 1786 return; 1787 1788 ravb_write(ndev, priv->gti_tiv, GTI); 1789 1790 /* Request GTI loading */ 1791 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 1792 } 1793 1794 static int ravb_compute_gti(struct net_device *ndev) 1795 { 1796 struct ravb_private *priv = netdev_priv(ndev); 1797 const struct ravb_hw_info *info = priv->info; 1798 struct device *dev = ndev->dev.parent; 1799 unsigned long rate; 1800 u64 inc; 1801 1802 if (!(info->gptp || info->ccc_gac)) 1803 return 0; 1804 1805 if (info->gptp_ref_clk) 1806 rate = clk_get_rate(priv->gptp_clk); 1807 else 1808 rate = clk_get_rate(priv->clk); 1809 if (!rate) 1810 return -EINVAL; 1811 1812 inc = div64_ul(1000000000ULL << 20, rate); 1813 1814 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 1815 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 1816 inc, GTI_TIV_MIN, GTI_TIV_MAX); 1817 return -EINVAL; 1818 } 1819 priv->gti_tiv = inc; 1820 1821 return 0; 1822 } 1823 1824 /* Set tx and rx clock internal delay modes */ 1825 static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev) 1826 { 1827 struct ravb_private *priv = netdev_priv(ndev); 1828 bool explicit_delay = false; 1829 u32 delay; 1830 1831 if (!priv->info->internal_delay) 1832 return; 1833 1834 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) { 1835 /* Valid values are 0 and 1800, according to DT bindings */ 1836 priv->rxcidm = !!delay; 1837 explicit_delay = true; 1838 } 1839 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) { 1840 /* Valid values are 0 and 2000, according to DT bindings */ 1841 priv->txcidm = !!delay; 1842 explicit_delay = true; 1843 } 1844 1845 if (explicit_delay) 1846 return; 1847 1848 /* Fall back to legacy rgmii-*id behavior */ 1849 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1850 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) { 1851 priv->rxcidm = 1; 1852 priv->rgmii_override = 1; 1853 } 1854 1855 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1856 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) { 1857 priv->txcidm = 1; 1858 priv->rgmii_override = 1; 1859 } 1860 } 1861 1862 static void ravb_set_delay_mode(struct net_device *ndev) 1863 { 1864 struct ravb_private *priv = netdev_priv(ndev); 1865 u32 set = 0; 1866 1867 if (!priv->info->internal_delay) 1868 return; 1869 1870 if (priv->rxcidm) 1871 set |= APSR_RDM; 1872 if (priv->txcidm) 1873 set |= APSR_TDM; 1874 ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set); 1875 } 1876 1877 /* Network device open function for Ethernet AVB */ 1878 static int ravb_open(struct net_device *ndev) 1879 { 1880 struct ravb_private *priv = netdev_priv(ndev); 1881 const struct ravb_hw_info *info = priv->info; 1882 int error; 1883 1884 napi_enable(&priv->napi[RAVB_BE]); 1885 if (info->nc_queues) 1886 napi_enable(&priv->napi[RAVB_NC]); 1887 1888 /* Set AVB config mode */ 1889 error = ravb_set_config_mode(ndev); 1890 if (error) 1891 goto out_napi_off; 1892 1893 ravb_set_delay_mode(ndev); 1894 ravb_write(ndev, priv->desc_bat_dma, DBAT); 1895 1896 /* Device init */ 1897 error = ravb_dmac_init(ndev); 1898 if (error) 1899 goto out_set_reset; 1900 1901 ravb_emac_init(ndev); 1902 1903 ravb_set_gti(ndev); 1904 1905 /* Initialise PTP Clock driver */ 1906 if (info->gptp || info->ccc_gac) 1907 ravb_ptp_init(ndev, priv->pdev); 1908 1909 /* PHY control start */ 1910 error = ravb_phy_start(ndev); 1911 if (error) 1912 goto out_ptp_stop; 1913 1914 netif_tx_start_all_queues(ndev); 1915 1916 return 0; 1917 1918 out_ptp_stop: 1919 /* Stop PTP Clock driver */ 1920 if (info->gptp || info->ccc_gac) 1921 ravb_ptp_stop(ndev); 1922 ravb_stop_dma(ndev); 1923 out_set_reset: 1924 ravb_set_opmode(ndev, CCC_OPC_RESET); 1925 out_napi_off: 1926 if (info->nc_queues) 1927 napi_disable(&priv->napi[RAVB_NC]); 1928 napi_disable(&priv->napi[RAVB_BE]); 1929 return error; 1930 } 1931 1932 /* Timeout function for Ethernet AVB */ 1933 static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1934 { 1935 struct ravb_private *priv = netdev_priv(ndev); 1936 1937 netif_err(priv, tx_err, ndev, 1938 "transmit timed out, status %08x, resetting...\n", 1939 ravb_read(ndev, ISS)); 1940 1941 /* tx_errors count up */ 1942 ndev->stats.tx_errors++; 1943 1944 schedule_work(&priv->work); 1945 } 1946 1947 static void ravb_tx_timeout_work(struct work_struct *work) 1948 { 1949 struct ravb_private *priv = container_of(work, struct ravb_private, 1950 work); 1951 const struct ravb_hw_info *info = priv->info; 1952 struct net_device *ndev = priv->ndev; 1953 int error; 1954 1955 if (!rtnl_trylock()) { 1956 usleep_range(1000, 2000); 1957 schedule_work(&priv->work); 1958 return; 1959 } 1960 1961 netif_tx_stop_all_queues(ndev); 1962 1963 /* Stop PTP Clock driver */ 1964 if (info->gptp) 1965 ravb_ptp_stop(ndev); 1966 1967 /* Wait for DMA stopping */ 1968 if (ravb_stop_dma(ndev)) { 1969 /* If ravb_stop_dma() fails, the hardware is still operating 1970 * for TX and/or RX. So, this should not call the following 1971 * functions because ravb_dmac_init() is possible to fail too. 1972 * Also, this should not retry ravb_stop_dma() again and again 1973 * here because it's possible to wait forever. So, this just 1974 * re-enables the TX and RX and skip the following 1975 * re-initialization procedure. 1976 */ 1977 ravb_rcv_snd_enable(ndev); 1978 goto out; 1979 } 1980 1981 ravb_ring_free(ndev, RAVB_BE); 1982 if (info->nc_queues) 1983 ravb_ring_free(ndev, RAVB_NC); 1984 1985 /* Device init */ 1986 error = ravb_dmac_init(ndev); 1987 if (error) { 1988 /* If ravb_dmac_init() fails, descriptors are freed. So, this 1989 * should return here to avoid re-enabling the TX and RX in 1990 * ravb_emac_init(). 1991 */ 1992 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n", 1993 __func__, error); 1994 goto out_unlock; 1995 } 1996 ravb_emac_init(ndev); 1997 1998 out: 1999 /* Initialise PTP Clock driver */ 2000 if (info->gptp) 2001 ravb_ptp_init(ndev, priv->pdev); 2002 2003 netif_tx_start_all_queues(ndev); 2004 2005 out_unlock: 2006 rtnl_unlock(); 2007 } 2008 2009 /* Packet transmit function for Ethernet AVB */ 2010 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 2011 { 2012 struct ravb_private *priv = netdev_priv(ndev); 2013 const struct ravb_hw_info *info = priv->info; 2014 unsigned int num_tx_desc = priv->num_tx_desc; 2015 u16 q = skb_get_queue_mapping(skb); 2016 struct ravb_tstamp_skb *ts_skb; 2017 struct ravb_tx_desc *desc; 2018 unsigned long flags; 2019 dma_addr_t dma_addr; 2020 void *buffer; 2021 u32 entry; 2022 u32 len; 2023 2024 spin_lock_irqsave(&priv->lock, flags); 2025 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 2026 num_tx_desc) { 2027 netif_err(priv, tx_queued, ndev, 2028 "still transmitting with the full ring!\n"); 2029 netif_stop_subqueue(ndev, q); 2030 spin_unlock_irqrestore(&priv->lock, flags); 2031 return NETDEV_TX_BUSY; 2032 } 2033 2034 if (skb_put_padto(skb, ETH_ZLEN)) 2035 goto exit; 2036 2037 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc); 2038 priv->tx_skb[q][entry / num_tx_desc] = skb; 2039 2040 if (num_tx_desc > 1) { 2041 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 2042 entry / num_tx_desc * DPTR_ALIGN; 2043 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 2044 2045 /* Zero length DMA descriptors are problematic as they seem 2046 * to terminate DMA transfers. Avoid them by simply using a 2047 * length of DPTR_ALIGN (4) when skb data is aligned to 2048 * DPTR_ALIGN. 2049 * 2050 * As skb is guaranteed to have at least ETH_ZLEN (60) 2051 * bytes of data by the call to skb_put_padto() above this 2052 * is safe with respect to both the length of the first DMA 2053 * descriptor (len) overflowing the available data and the 2054 * length of the second DMA descriptor (skb->len - len) 2055 * being negative. 2056 */ 2057 if (len == 0) 2058 len = DPTR_ALIGN; 2059 2060 memcpy(buffer, skb->data, len); 2061 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 2062 DMA_TO_DEVICE); 2063 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2064 goto drop; 2065 2066 desc = &priv->tx_ring[q][entry]; 2067 desc->ds_tagl = cpu_to_le16(len); 2068 desc->dptr = cpu_to_le32(dma_addr); 2069 2070 buffer = skb->data + len; 2071 len = skb->len - len; 2072 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 2073 DMA_TO_DEVICE); 2074 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2075 goto unmap; 2076 2077 desc++; 2078 } else { 2079 desc = &priv->tx_ring[q][entry]; 2080 len = skb->len; 2081 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, 2082 DMA_TO_DEVICE); 2083 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2084 goto drop; 2085 } 2086 desc->ds_tagl = cpu_to_le16(len); 2087 desc->dptr = cpu_to_le32(dma_addr); 2088 2089 /* TX timestamp required */ 2090 if (info->gptp || info->ccc_gac) { 2091 if (q == RAVB_NC) { 2092 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 2093 if (!ts_skb) { 2094 if (num_tx_desc > 1) { 2095 desc--; 2096 dma_unmap_single(ndev->dev.parent, dma_addr, 2097 len, DMA_TO_DEVICE); 2098 } 2099 goto unmap; 2100 } 2101 ts_skb->skb = skb_get(skb); 2102 ts_skb->tag = priv->ts_skb_tag++; 2103 priv->ts_skb_tag &= 0x3ff; 2104 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 2105 2106 /* TAG and timestamp required flag */ 2107 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2108 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 2109 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12); 2110 } 2111 2112 skb_tx_timestamp(skb); 2113 } 2114 /* Descriptor type must be set after all the above writes */ 2115 dma_wmb(); 2116 if (num_tx_desc > 1) { 2117 desc->die_dt = DT_FEND; 2118 desc--; 2119 desc->die_dt = DT_FSTART; 2120 } else { 2121 desc->die_dt = DT_FSINGLE; 2122 } 2123 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 2124 2125 priv->cur_tx[q] += num_tx_desc; 2126 if (priv->cur_tx[q] - priv->dirty_tx[q] > 2127 (priv->num_tx_ring[q] - 1) * num_tx_desc && 2128 !ravb_tx_free(ndev, q, true)) 2129 netif_stop_subqueue(ndev, q); 2130 2131 exit: 2132 spin_unlock_irqrestore(&priv->lock, flags); 2133 return NETDEV_TX_OK; 2134 2135 unmap: 2136 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 2137 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 2138 drop: 2139 dev_kfree_skb_any(skb); 2140 priv->tx_skb[q][entry / num_tx_desc] = NULL; 2141 goto exit; 2142 } 2143 2144 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 2145 struct net_device *sb_dev) 2146 { 2147 /* If skb needs TX timestamp, it is handled in network control queue */ 2148 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 2149 RAVB_BE; 2150 2151 } 2152 2153 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 2154 { 2155 struct ravb_private *priv = netdev_priv(ndev); 2156 const struct ravb_hw_info *info = priv->info; 2157 struct net_device_stats *nstats, *stats0, *stats1; 2158 2159 nstats = &ndev->stats; 2160 stats0 = &priv->stats[RAVB_BE]; 2161 2162 if (info->tx_counters) { 2163 nstats->tx_dropped += ravb_read(ndev, TROCR); 2164 ravb_write(ndev, 0, TROCR); /* (write clear) */ 2165 } 2166 2167 if (info->carrier_counters) { 2168 nstats->collisions += ravb_read(ndev, CXR41); 2169 ravb_write(ndev, 0, CXR41); /* (write clear) */ 2170 nstats->tx_carrier_errors += ravb_read(ndev, CXR42); 2171 ravb_write(ndev, 0, CXR42); /* (write clear) */ 2172 } 2173 2174 nstats->rx_packets = stats0->rx_packets; 2175 nstats->tx_packets = stats0->tx_packets; 2176 nstats->rx_bytes = stats0->rx_bytes; 2177 nstats->tx_bytes = stats0->tx_bytes; 2178 nstats->multicast = stats0->multicast; 2179 nstats->rx_errors = stats0->rx_errors; 2180 nstats->rx_crc_errors = stats0->rx_crc_errors; 2181 nstats->rx_frame_errors = stats0->rx_frame_errors; 2182 nstats->rx_length_errors = stats0->rx_length_errors; 2183 nstats->rx_missed_errors = stats0->rx_missed_errors; 2184 nstats->rx_over_errors = stats0->rx_over_errors; 2185 if (info->nc_queues) { 2186 stats1 = &priv->stats[RAVB_NC]; 2187 2188 nstats->rx_packets += stats1->rx_packets; 2189 nstats->tx_packets += stats1->tx_packets; 2190 nstats->rx_bytes += stats1->rx_bytes; 2191 nstats->tx_bytes += stats1->tx_bytes; 2192 nstats->multicast += stats1->multicast; 2193 nstats->rx_errors += stats1->rx_errors; 2194 nstats->rx_crc_errors += stats1->rx_crc_errors; 2195 nstats->rx_frame_errors += stats1->rx_frame_errors; 2196 nstats->rx_length_errors += stats1->rx_length_errors; 2197 nstats->rx_missed_errors += stats1->rx_missed_errors; 2198 nstats->rx_over_errors += stats1->rx_over_errors; 2199 } 2200 2201 return nstats; 2202 } 2203 2204 /* Update promiscuous bit */ 2205 static void ravb_set_rx_mode(struct net_device *ndev) 2206 { 2207 struct ravb_private *priv = netdev_priv(ndev); 2208 unsigned long flags; 2209 2210 spin_lock_irqsave(&priv->lock, flags); 2211 ravb_modify(ndev, ECMR, ECMR_PRM, 2212 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 2213 spin_unlock_irqrestore(&priv->lock, flags); 2214 } 2215 2216 /* Device close function for Ethernet AVB */ 2217 static int ravb_close(struct net_device *ndev) 2218 { 2219 struct device_node *np = ndev->dev.parent->of_node; 2220 struct ravb_private *priv = netdev_priv(ndev); 2221 const struct ravb_hw_info *info = priv->info; 2222 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 2223 2224 netif_tx_stop_all_queues(ndev); 2225 2226 /* Disable interrupts by clearing the interrupt masks. */ 2227 ravb_write(ndev, 0, RIC0); 2228 ravb_write(ndev, 0, RIC2); 2229 ravb_write(ndev, 0, TIC); 2230 2231 /* Stop PTP Clock driver */ 2232 if (info->gptp || info->ccc_gac) 2233 ravb_ptp_stop(ndev); 2234 2235 /* Set the config mode to stop the AVB-DMAC's processes */ 2236 if (ravb_stop_dma(ndev) < 0) 2237 netdev_err(ndev, 2238 "device will be stopped after h/w processes are done.\n"); 2239 2240 /* Clear the timestamp list */ 2241 if (info->gptp || info->ccc_gac) { 2242 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 2243 list_del(&ts_skb->list); 2244 kfree_skb(ts_skb->skb); 2245 kfree(ts_skb); 2246 } 2247 } 2248 2249 /* PHY disconnect */ 2250 if (ndev->phydev) { 2251 phy_stop(ndev->phydev); 2252 phy_disconnect(ndev->phydev); 2253 if (of_phy_is_fixed_link(np)) 2254 of_phy_deregister_fixed_link(np); 2255 } 2256 2257 cancel_work_sync(&priv->work); 2258 2259 if (info->nc_queues) 2260 napi_disable(&priv->napi[RAVB_NC]); 2261 napi_disable(&priv->napi[RAVB_BE]); 2262 2263 /* Free all the skb's in the RX queue and the DMA buffers. */ 2264 ravb_ring_free(ndev, RAVB_BE); 2265 if (info->nc_queues) 2266 ravb_ring_free(ndev, RAVB_NC); 2267 2268 /* Set reset mode. */ 2269 return ravb_set_opmode(ndev, CCC_OPC_RESET); 2270 } 2271 2272 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 2273 { 2274 struct ravb_private *priv = netdev_priv(ndev); 2275 struct hwtstamp_config config; 2276 2277 config.flags = 0; 2278 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 2279 HWTSTAMP_TX_OFF; 2280 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) { 2281 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT: 2282 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 2283 break; 2284 case RAVB_RXTSTAMP_TYPE_ALL: 2285 config.rx_filter = HWTSTAMP_FILTER_ALL; 2286 break; 2287 default: 2288 config.rx_filter = HWTSTAMP_FILTER_NONE; 2289 } 2290 2291 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2292 -EFAULT : 0; 2293 } 2294 2295 /* Control hardware time stamping */ 2296 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 2297 { 2298 struct ravb_private *priv = netdev_priv(ndev); 2299 struct hwtstamp_config config; 2300 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 2301 u32 tstamp_tx_ctrl; 2302 2303 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 2304 return -EFAULT; 2305 2306 switch (config.tx_type) { 2307 case HWTSTAMP_TX_OFF: 2308 tstamp_tx_ctrl = 0; 2309 break; 2310 case HWTSTAMP_TX_ON: 2311 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 2312 break; 2313 default: 2314 return -ERANGE; 2315 } 2316 2317 switch (config.rx_filter) { 2318 case HWTSTAMP_FILTER_NONE: 2319 tstamp_rx_ctrl = 0; 2320 break; 2321 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2322 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 2323 break; 2324 default: 2325 config.rx_filter = HWTSTAMP_FILTER_ALL; 2326 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 2327 } 2328 2329 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 2330 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 2331 2332 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2333 -EFAULT : 0; 2334 } 2335 2336 /* ioctl to device function */ 2337 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 2338 { 2339 struct phy_device *phydev = ndev->phydev; 2340 2341 if (!netif_running(ndev)) 2342 return -EINVAL; 2343 2344 if (!phydev) 2345 return -ENODEV; 2346 2347 switch (cmd) { 2348 case SIOCGHWTSTAMP: 2349 return ravb_hwtstamp_get(ndev, req); 2350 case SIOCSHWTSTAMP: 2351 return ravb_hwtstamp_set(ndev, req); 2352 } 2353 2354 return phy_mii_ioctl(phydev, req, cmd); 2355 } 2356 2357 static int ravb_change_mtu(struct net_device *ndev, int new_mtu) 2358 { 2359 struct ravb_private *priv = netdev_priv(ndev); 2360 2361 ndev->mtu = new_mtu; 2362 2363 if (netif_running(ndev)) { 2364 synchronize_irq(priv->emac_irq); 2365 ravb_emac_init(ndev); 2366 } 2367 2368 netdev_update_features(ndev); 2369 2370 return 0; 2371 } 2372 2373 static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 2374 { 2375 struct ravb_private *priv = netdev_priv(ndev); 2376 unsigned long flags; 2377 2378 spin_lock_irqsave(&priv->lock, flags); 2379 2380 /* Disable TX and RX */ 2381 ravb_rcv_snd_disable(ndev); 2382 2383 /* Modify RX Checksum setting */ 2384 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 2385 2386 /* Enable TX and RX */ 2387 ravb_rcv_snd_enable(ndev); 2388 2389 spin_unlock_irqrestore(&priv->lock, flags); 2390 } 2391 2392 static int ravb_set_features_gbeth(struct net_device *ndev, 2393 netdev_features_t features) 2394 { 2395 /* Place holder */ 2396 return 0; 2397 } 2398 2399 static int ravb_set_features_rcar(struct net_device *ndev, 2400 netdev_features_t features) 2401 { 2402 netdev_features_t changed = ndev->features ^ features; 2403 2404 if (changed & NETIF_F_RXCSUM) 2405 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 2406 2407 ndev->features = features; 2408 2409 return 0; 2410 } 2411 2412 static int ravb_set_features(struct net_device *ndev, 2413 netdev_features_t features) 2414 { 2415 struct ravb_private *priv = netdev_priv(ndev); 2416 const struct ravb_hw_info *info = priv->info; 2417 2418 return info->set_feature(ndev, features); 2419 } 2420 2421 static const struct net_device_ops ravb_netdev_ops = { 2422 .ndo_open = ravb_open, 2423 .ndo_stop = ravb_close, 2424 .ndo_start_xmit = ravb_start_xmit, 2425 .ndo_select_queue = ravb_select_queue, 2426 .ndo_get_stats = ravb_get_stats, 2427 .ndo_set_rx_mode = ravb_set_rx_mode, 2428 .ndo_tx_timeout = ravb_tx_timeout, 2429 .ndo_eth_ioctl = ravb_do_ioctl, 2430 .ndo_change_mtu = ravb_change_mtu, 2431 .ndo_validate_addr = eth_validate_addr, 2432 .ndo_set_mac_address = eth_mac_addr, 2433 .ndo_set_features = ravb_set_features, 2434 }; 2435 2436 /* MDIO bus init function */ 2437 static int ravb_mdio_init(struct ravb_private *priv) 2438 { 2439 struct platform_device *pdev = priv->pdev; 2440 struct device *dev = &pdev->dev; 2441 struct phy_device *phydev; 2442 struct device_node *pn; 2443 int error; 2444 2445 /* Bitbang init */ 2446 priv->mdiobb.ops = &bb_ops; 2447 2448 /* MII controller setting */ 2449 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 2450 if (!priv->mii_bus) 2451 return -ENOMEM; 2452 2453 /* Hook up MII support for ethtool */ 2454 priv->mii_bus->name = "ravb_mii"; 2455 priv->mii_bus->parent = dev; 2456 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2457 pdev->name, pdev->id); 2458 2459 /* Register MDIO bus */ 2460 error = of_mdiobus_register(priv->mii_bus, dev->of_node); 2461 if (error) 2462 goto out_free_bus; 2463 2464 pn = of_parse_phandle(dev->of_node, "phy-handle", 0); 2465 phydev = of_phy_find_device(pn); 2466 if (phydev) { 2467 phydev->mac_managed_pm = true; 2468 put_device(&phydev->mdio.dev); 2469 } 2470 of_node_put(pn); 2471 2472 return 0; 2473 2474 out_free_bus: 2475 free_mdio_bitbang(priv->mii_bus); 2476 return error; 2477 } 2478 2479 /* MDIO bus release function */ 2480 static int ravb_mdio_release(struct ravb_private *priv) 2481 { 2482 /* Unregister mdio bus */ 2483 mdiobus_unregister(priv->mii_bus); 2484 2485 /* Free bitbang info */ 2486 free_mdio_bitbang(priv->mii_bus); 2487 2488 return 0; 2489 } 2490 2491 static const struct ravb_hw_info ravb_gen3_hw_info = { 2492 .rx_ring_free = ravb_rx_ring_free_rcar, 2493 .rx_ring_format = ravb_rx_ring_format_rcar, 2494 .alloc_rx_desc = ravb_alloc_rx_desc_rcar, 2495 .receive = ravb_rx_rcar, 2496 .set_rate = ravb_set_rate_rcar, 2497 .set_feature = ravb_set_features_rcar, 2498 .dmac_init = ravb_dmac_init_rcar, 2499 .emac_init = ravb_emac_init_rcar, 2500 .gstrings_stats = ravb_gstrings_stats, 2501 .gstrings_size = sizeof(ravb_gstrings_stats), 2502 .net_hw_features = NETIF_F_RXCSUM, 2503 .net_features = NETIF_F_RXCSUM, 2504 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2505 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 2506 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2507 .rx_max_buf_size = SZ_2K, 2508 .internal_delay = 1, 2509 .tx_counters = 1, 2510 .multi_irqs = 1, 2511 .irq_en_dis = 1, 2512 .ccc_gac = 1, 2513 .nc_queues = 1, 2514 .magic_pkt = 1, 2515 }; 2516 2517 static const struct ravb_hw_info ravb_gen2_hw_info = { 2518 .rx_ring_free = ravb_rx_ring_free_rcar, 2519 .rx_ring_format = ravb_rx_ring_format_rcar, 2520 .alloc_rx_desc = ravb_alloc_rx_desc_rcar, 2521 .receive = ravb_rx_rcar, 2522 .set_rate = ravb_set_rate_rcar, 2523 .set_feature = ravb_set_features_rcar, 2524 .dmac_init = ravb_dmac_init_rcar, 2525 .emac_init = ravb_emac_init_rcar, 2526 .gstrings_stats = ravb_gstrings_stats, 2527 .gstrings_size = sizeof(ravb_gstrings_stats), 2528 .net_hw_features = NETIF_F_RXCSUM, 2529 .net_features = NETIF_F_RXCSUM, 2530 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2531 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 2532 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2533 .rx_max_buf_size = SZ_2K, 2534 .aligned_tx = 1, 2535 .gptp = 1, 2536 .nc_queues = 1, 2537 .magic_pkt = 1, 2538 }; 2539 2540 static const struct ravb_hw_info ravb_rzv2m_hw_info = { 2541 .rx_ring_free = ravb_rx_ring_free_rcar, 2542 .rx_ring_format = ravb_rx_ring_format_rcar, 2543 .alloc_rx_desc = ravb_alloc_rx_desc_rcar, 2544 .receive = ravb_rx_rcar, 2545 .set_rate = ravb_set_rate_rcar, 2546 .set_feature = ravb_set_features_rcar, 2547 .dmac_init = ravb_dmac_init_rcar, 2548 .emac_init = ravb_emac_init_rcar, 2549 .gstrings_stats = ravb_gstrings_stats, 2550 .gstrings_size = sizeof(ravb_gstrings_stats), 2551 .net_hw_features = NETIF_F_RXCSUM, 2552 .net_features = NETIF_F_RXCSUM, 2553 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2554 .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1, 2555 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2556 .rx_max_buf_size = SZ_2K, 2557 .multi_irqs = 1, 2558 .err_mgmt_irqs = 1, 2559 .gptp = 1, 2560 .gptp_ref_clk = 1, 2561 .nc_queues = 1, 2562 .magic_pkt = 1, 2563 }; 2564 2565 static const struct ravb_hw_info gbeth_hw_info = { 2566 .rx_ring_free = ravb_rx_ring_free_gbeth, 2567 .rx_ring_format = ravb_rx_ring_format_gbeth, 2568 .alloc_rx_desc = ravb_alloc_rx_desc_gbeth, 2569 .receive = ravb_rx_gbeth, 2570 .set_rate = ravb_set_rate_gbeth, 2571 .set_feature = ravb_set_features_gbeth, 2572 .dmac_init = ravb_dmac_init_gbeth, 2573 .emac_init = ravb_emac_init_gbeth, 2574 .gstrings_stats = ravb_gstrings_stats_gbeth, 2575 .gstrings_size = sizeof(ravb_gstrings_stats_gbeth), 2576 .stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth), 2577 .max_rx_len = ALIGN(GBETH_RX_BUFF_MAX, RAVB_ALIGN), 2578 .tccr_mask = TCCR_TSRQ0, 2579 .rx_max_buf_size = SZ_8K, 2580 .aligned_tx = 1, 2581 .tx_counters = 1, 2582 .carrier_counters = 1, 2583 .half_duplex = 1, 2584 }; 2585 2586 static const struct of_device_id ravb_match_table[] = { 2587 { .compatible = "renesas,etheravb-r8a7790", .data = &ravb_gen2_hw_info }, 2588 { .compatible = "renesas,etheravb-r8a7794", .data = &ravb_gen2_hw_info }, 2589 { .compatible = "renesas,etheravb-rcar-gen2", .data = &ravb_gen2_hw_info }, 2590 { .compatible = "renesas,etheravb-r8a7795", .data = &ravb_gen3_hw_info }, 2591 { .compatible = "renesas,etheravb-rcar-gen3", .data = &ravb_gen3_hw_info }, 2592 { .compatible = "renesas,etheravb-rcar-gen4", .data = &ravb_gen3_hw_info }, 2593 { .compatible = "renesas,etheravb-rzv2m", .data = &ravb_rzv2m_hw_info }, 2594 { .compatible = "renesas,rzg2l-gbeth", .data = &gbeth_hw_info }, 2595 { } 2596 }; 2597 MODULE_DEVICE_TABLE(of, ravb_match_table); 2598 2599 static int ravb_setup_irq(struct ravb_private *priv, const char *irq_name, 2600 const char *ch, int *irq, irq_handler_t handler) 2601 { 2602 struct platform_device *pdev = priv->pdev; 2603 struct net_device *ndev = priv->ndev; 2604 struct device *dev = &pdev->dev; 2605 const char *dev_name; 2606 unsigned long flags; 2607 int error; 2608 2609 if (irq_name) { 2610 dev_name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch); 2611 if (!dev_name) 2612 return -ENOMEM; 2613 2614 *irq = platform_get_irq_byname(pdev, irq_name); 2615 flags = 0; 2616 } else { 2617 dev_name = ndev->name; 2618 *irq = platform_get_irq(pdev, 0); 2619 flags = IRQF_SHARED; 2620 } 2621 if (*irq < 0) 2622 return *irq; 2623 2624 error = devm_request_irq(dev, *irq, handler, flags, dev_name, ndev); 2625 if (error) 2626 netdev_err(ndev, "cannot request IRQ %s\n", dev_name); 2627 2628 return error; 2629 } 2630 2631 static int ravb_setup_irqs(struct ravb_private *priv) 2632 { 2633 const struct ravb_hw_info *info = priv->info; 2634 struct net_device *ndev = priv->ndev; 2635 const char *irq_name, *emac_irq_name; 2636 int error, irq; 2637 2638 if (!info->multi_irqs) 2639 return ravb_setup_irq(priv, NULL, NULL, &ndev->irq, ravb_interrupt); 2640 2641 if (info->err_mgmt_irqs) { 2642 irq_name = "dia"; 2643 emac_irq_name = "line3"; 2644 } else { 2645 irq_name = "ch22"; 2646 emac_irq_name = "ch24"; 2647 } 2648 2649 error = ravb_setup_irq(priv, irq_name, "ch22:multi", &ndev->irq, ravb_multi_interrupt); 2650 if (error) 2651 return error; 2652 2653 error = ravb_setup_irq(priv, emac_irq_name, "ch24:emac", &priv->emac_irq, 2654 ravb_emac_interrupt); 2655 if (error) 2656 return error; 2657 2658 if (info->err_mgmt_irqs) { 2659 error = ravb_setup_irq(priv, "err_a", "err_a", &irq, ravb_multi_interrupt); 2660 if (error) 2661 return error; 2662 2663 error = ravb_setup_irq(priv, "mgmt_a", "mgmt_a", &irq, ravb_multi_interrupt); 2664 if (error) 2665 return error; 2666 } 2667 2668 error = ravb_setup_irq(priv, "ch0", "ch0:rx_be", &irq, ravb_be_interrupt); 2669 if (error) 2670 return error; 2671 2672 error = ravb_setup_irq(priv, "ch1", "ch1:rx_nc", &irq, ravb_nc_interrupt); 2673 if (error) 2674 return error; 2675 2676 error = ravb_setup_irq(priv, "ch18", "ch18:tx_be", &irq, ravb_be_interrupt); 2677 if (error) 2678 return error; 2679 2680 return ravb_setup_irq(priv, "ch19", "ch19:tx_nc", &irq, ravb_nc_interrupt); 2681 } 2682 2683 static int ravb_probe(struct platform_device *pdev) 2684 { 2685 struct device_node *np = pdev->dev.of_node; 2686 const struct ravb_hw_info *info; 2687 struct reset_control *rstc; 2688 struct ravb_private *priv; 2689 struct net_device *ndev; 2690 struct resource *res; 2691 int error, q; 2692 2693 if (!np) { 2694 dev_err(&pdev->dev, 2695 "this driver is required to be instantiated from device tree\n"); 2696 return -EINVAL; 2697 } 2698 2699 rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 2700 if (IS_ERR(rstc)) 2701 return dev_err_probe(&pdev->dev, PTR_ERR(rstc), 2702 "failed to get cpg reset\n"); 2703 2704 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 2705 NUM_TX_QUEUE, NUM_RX_QUEUE); 2706 if (!ndev) 2707 return -ENOMEM; 2708 2709 info = of_device_get_match_data(&pdev->dev); 2710 2711 ndev->features = info->net_features; 2712 ndev->hw_features = info->net_hw_features; 2713 2714 error = reset_control_deassert(rstc); 2715 if (error) 2716 goto out_free_netdev; 2717 2718 SET_NETDEV_DEV(ndev, &pdev->dev); 2719 2720 priv = netdev_priv(ndev); 2721 priv->info = info; 2722 priv->rstc = rstc; 2723 priv->ndev = ndev; 2724 priv->pdev = pdev; 2725 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2726 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2727 if (info->nc_queues) { 2728 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2729 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2730 } 2731 2732 error = ravb_setup_irqs(priv); 2733 if (error) 2734 goto out_reset_assert; 2735 2736 priv->clk = devm_clk_get(&pdev->dev, NULL); 2737 if (IS_ERR(priv->clk)) { 2738 error = PTR_ERR(priv->clk); 2739 goto out_reset_assert; 2740 } 2741 2742 if (info->gptp_ref_clk) { 2743 priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp"); 2744 if (IS_ERR(priv->gptp_clk)) { 2745 error = PTR_ERR(priv->gptp_clk); 2746 goto out_reset_assert; 2747 } 2748 } 2749 2750 priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk"); 2751 if (IS_ERR(priv->refclk)) { 2752 error = PTR_ERR(priv->refclk); 2753 goto out_reset_assert; 2754 } 2755 clk_prepare(priv->refclk); 2756 2757 platform_set_drvdata(pdev, ndev); 2758 pm_runtime_enable(&pdev->dev); 2759 error = pm_runtime_resume_and_get(&pdev->dev); 2760 if (error < 0) 2761 goto out_rpm_disable; 2762 2763 priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2764 if (IS_ERR(priv->addr)) { 2765 error = PTR_ERR(priv->addr); 2766 goto out_rpm_put; 2767 } 2768 2769 /* The Ether-specific entries in the device structure. */ 2770 ndev->base_addr = res->start; 2771 2772 spin_lock_init(&priv->lock); 2773 INIT_WORK(&priv->work, ravb_tx_timeout_work); 2774 2775 error = of_get_phy_mode(np, &priv->phy_interface); 2776 if (error && error != -ENODEV) 2777 goto out_rpm_put; 2778 2779 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 2780 priv->avb_link_active_low = 2781 of_property_read_bool(np, "renesas,ether-link-active-low"); 2782 2783 ndev->max_mtu = info->rx_max_buf_size - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 2784 ndev->min_mtu = ETH_MIN_MTU; 2785 2786 /* FIXME: R-Car Gen2 has 4byte alignment restriction for tx buffer 2787 * Use two descriptor to handle such situation. First descriptor to 2788 * handle aligned data buffer and second descriptor to handle the 2789 * overflow data because of alignment. 2790 */ 2791 priv->num_tx_desc = info->aligned_tx ? 2 : 1; 2792 2793 /* Set function */ 2794 ndev->netdev_ops = &ravb_netdev_ops; 2795 ndev->ethtool_ops = &ravb_ethtool_ops; 2796 2797 error = ravb_compute_gti(ndev); 2798 if (error) 2799 goto out_rpm_put; 2800 2801 ravb_parse_delay_mode(np, ndev); 2802 2803 /* Allocate descriptor base address table */ 2804 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 2805 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 2806 &priv->desc_bat_dma, GFP_KERNEL); 2807 if (!priv->desc_bat) { 2808 dev_err(&pdev->dev, 2809 "Cannot allocate desc base address table (size %d bytes)\n", 2810 priv->desc_bat_size); 2811 error = -ENOMEM; 2812 goto out_rpm_put; 2813 } 2814 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 2815 priv->desc_bat[q].die_dt = DT_EOS; 2816 2817 /* Initialise HW timestamp list */ 2818 INIT_LIST_HEAD(&priv->ts_skb_list); 2819 2820 /* Debug message level */ 2821 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 2822 2823 /* Set config mode as this is needed for PHY initialization. */ 2824 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 2825 if (error) 2826 goto out_rpm_put; 2827 2828 /* Read and set MAC address */ 2829 ravb_read_mac_address(np, ndev); 2830 if (!is_valid_ether_addr(ndev->dev_addr)) { 2831 dev_warn(&pdev->dev, 2832 "no valid MAC address supplied, using a random one\n"); 2833 eth_hw_addr_random(ndev); 2834 } 2835 2836 /* MDIO bus init */ 2837 error = ravb_mdio_init(priv); 2838 if (error) { 2839 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 2840 goto out_reset_mode; 2841 } 2842 2843 /* Undo previous switch to config opmode. */ 2844 error = ravb_set_opmode(ndev, CCC_OPC_RESET); 2845 if (error) 2846 goto out_mdio_release; 2847 2848 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll); 2849 if (info->nc_queues) 2850 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll); 2851 2852 /* Network device register */ 2853 error = register_netdev(ndev); 2854 if (error) 2855 goto out_napi_del; 2856 2857 device_set_wakeup_capable(&pdev->dev, 1); 2858 2859 /* Print device information */ 2860 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 2861 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2862 2863 return 0; 2864 2865 out_napi_del: 2866 if (info->nc_queues) 2867 netif_napi_del(&priv->napi[RAVB_NC]); 2868 2869 netif_napi_del(&priv->napi[RAVB_BE]); 2870 out_mdio_release: 2871 ravb_mdio_release(priv); 2872 out_reset_mode: 2873 ravb_set_opmode(ndev, CCC_OPC_RESET); 2874 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2875 priv->desc_bat_dma); 2876 out_rpm_put: 2877 pm_runtime_put(&pdev->dev); 2878 out_rpm_disable: 2879 pm_runtime_disable(&pdev->dev); 2880 clk_unprepare(priv->refclk); 2881 out_reset_assert: 2882 reset_control_assert(rstc); 2883 out_free_netdev: 2884 free_netdev(ndev); 2885 return error; 2886 } 2887 2888 static void ravb_remove(struct platform_device *pdev) 2889 { 2890 struct net_device *ndev = platform_get_drvdata(pdev); 2891 struct ravb_private *priv = netdev_priv(ndev); 2892 const struct ravb_hw_info *info = priv->info; 2893 2894 unregister_netdev(ndev); 2895 if (info->nc_queues) 2896 netif_napi_del(&priv->napi[RAVB_NC]); 2897 netif_napi_del(&priv->napi[RAVB_BE]); 2898 2899 ravb_mdio_release(priv); 2900 2901 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 2902 priv->desc_bat_dma); 2903 2904 pm_runtime_put_sync(&pdev->dev); 2905 pm_runtime_disable(&pdev->dev); 2906 clk_unprepare(priv->refclk); 2907 reset_control_assert(priv->rstc); 2908 free_netdev(ndev); 2909 platform_set_drvdata(pdev, NULL); 2910 } 2911 2912 static int ravb_wol_setup(struct net_device *ndev) 2913 { 2914 struct ravb_private *priv = netdev_priv(ndev); 2915 const struct ravb_hw_info *info = priv->info; 2916 2917 /* Disable interrupts by clearing the interrupt masks. */ 2918 ravb_write(ndev, 0, RIC0); 2919 ravb_write(ndev, 0, RIC2); 2920 ravb_write(ndev, 0, TIC); 2921 2922 /* Only allow ECI interrupts */ 2923 synchronize_irq(priv->emac_irq); 2924 if (info->nc_queues) 2925 napi_disable(&priv->napi[RAVB_NC]); 2926 napi_disable(&priv->napi[RAVB_BE]); 2927 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 2928 2929 /* Enable MagicPacket */ 2930 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 2931 2932 if (priv->info->ccc_gac) 2933 ravb_ptp_stop(ndev); 2934 2935 return enable_irq_wake(priv->emac_irq); 2936 } 2937 2938 static int ravb_wol_restore(struct net_device *ndev) 2939 { 2940 struct ravb_private *priv = netdev_priv(ndev); 2941 const struct ravb_hw_info *info = priv->info; 2942 int error; 2943 2944 /* Set reset mode to rearm the WoL logic. */ 2945 error = ravb_set_opmode(ndev, CCC_OPC_RESET); 2946 if (error) 2947 return error; 2948 2949 /* Set AVB config mode. */ 2950 error = ravb_set_config_mode(ndev); 2951 if (error) 2952 return error; 2953 2954 if (priv->info->ccc_gac) 2955 ravb_ptp_init(ndev, priv->pdev); 2956 2957 if (info->nc_queues) 2958 napi_enable(&priv->napi[RAVB_NC]); 2959 napi_enable(&priv->napi[RAVB_BE]); 2960 2961 /* Disable MagicPacket */ 2962 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 2963 2964 ravb_close(ndev); 2965 2966 return disable_irq_wake(priv->emac_irq); 2967 } 2968 2969 static int ravb_suspend(struct device *dev) 2970 { 2971 struct net_device *ndev = dev_get_drvdata(dev); 2972 struct ravb_private *priv = netdev_priv(ndev); 2973 int ret; 2974 2975 if (!netif_running(ndev)) 2976 goto reset_assert; 2977 2978 netif_device_detach(ndev); 2979 2980 if (priv->wol_enabled) 2981 return ravb_wol_setup(ndev); 2982 2983 ret = ravb_close(ndev); 2984 if (ret) 2985 return ret; 2986 2987 reset_assert: 2988 return reset_control_assert(priv->rstc); 2989 } 2990 2991 static int ravb_resume(struct device *dev) 2992 { 2993 struct net_device *ndev = dev_get_drvdata(dev); 2994 struct ravb_private *priv = netdev_priv(ndev); 2995 int ret; 2996 2997 ret = reset_control_deassert(priv->rstc); 2998 if (ret) 2999 return ret; 3000 3001 if (!netif_running(ndev)) 3002 return 0; 3003 3004 /* If WoL is enabled restore the interface. */ 3005 if (priv->wol_enabled) { 3006 ret = ravb_wol_restore(ndev); 3007 if (ret) 3008 return ret; 3009 } 3010 3011 /* Reopening the interface will restore the device to the working state. */ 3012 ret = ravb_open(ndev); 3013 if (ret < 0) 3014 return ret; 3015 3016 ravb_set_rx_mode(ndev); 3017 netif_device_attach(ndev); 3018 3019 return ret; 3020 } 3021 3022 static int ravb_runtime_suspend(struct device *dev) 3023 { 3024 struct net_device *ndev = dev_get_drvdata(dev); 3025 struct ravb_private *priv = netdev_priv(ndev); 3026 3027 clk_disable(priv->refclk); 3028 3029 return 0; 3030 } 3031 3032 static int ravb_runtime_resume(struct device *dev) 3033 { 3034 struct net_device *ndev = dev_get_drvdata(dev); 3035 struct ravb_private *priv = netdev_priv(ndev); 3036 3037 return clk_enable(priv->refclk); 3038 } 3039 3040 static const struct dev_pm_ops ravb_dev_pm_ops = { 3041 SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 3042 RUNTIME_PM_OPS(ravb_runtime_suspend, ravb_runtime_resume, NULL) 3043 }; 3044 3045 static struct platform_driver ravb_driver = { 3046 .probe = ravb_probe, 3047 .remove_new = ravb_remove, 3048 .driver = { 3049 .name = "ravb", 3050 .pm = pm_ptr(&ravb_dev_pm_ops), 3051 .of_match_table = ravb_match_table, 3052 }, 3053 }; 3054 3055 module_platform_driver(ravb_driver); 3056 3057 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 3058 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 3059 MODULE_LICENSE("GPL v2"); 3060