1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet AVB device driver 3 * 4 * Copyright (C) 2014-2019 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * Based on the SuperH Ethernet driver 9 */ 10 11 #include <linux/cache.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_vlan.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/module.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/of.h> 24 #include <linux/of_mdio.h> 25 #include <linux/of_net.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/slab.h> 29 #include <linux/spinlock.h> 30 #include <linux/reset.h> 31 #include <linux/math64.h> 32 #include <net/ip.h> 33 #include <net/page_pool/helpers.h> 34 35 #include "ravb.h" 36 37 #define RAVB_DEF_MSG_ENABLE \ 38 (NETIF_MSG_LINK | \ 39 NETIF_MSG_TIMER | \ 40 NETIF_MSG_RX_ERR | \ 41 NETIF_MSG_TX_ERR) 42 43 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 44 u32 set) 45 { 46 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 47 } 48 49 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 50 { 51 int i; 52 53 for (i = 0; i < 10000; i++) { 54 if ((ravb_read(ndev, reg) & mask) == value) 55 return 0; 56 udelay(10); 57 } 58 return -ETIMEDOUT; 59 } 60 61 static int ravb_set_opmode(struct net_device *ndev, u32 opmode) 62 { 63 u32 csr_ops = 1U << (opmode & CCC_OPC); 64 u32 ccc_mask = CCC_OPC; 65 int error; 66 67 /* If gPTP active in config mode is supported it needs to be configured 68 * along with CSEL and operating mode in the same access. This is a 69 * hardware limitation. 70 */ 71 if (opmode & CCC_GAC) 72 ccc_mask |= CCC_GAC | CCC_CSEL; 73 74 /* Set operating mode */ 75 ravb_modify(ndev, CCC, ccc_mask, opmode); 76 /* Check if the operating mode is changed to the requested one */ 77 error = ravb_wait(ndev, CSR, CSR_OPS, csr_ops); 78 if (error) { 79 netdev_err(ndev, "failed to switch device to requested mode (%u)\n", 80 opmode & CCC_OPC); 81 } 82 83 return error; 84 } 85 86 static void ravb_set_rate_gbeth(struct net_device *ndev) 87 { 88 struct ravb_private *priv = netdev_priv(ndev); 89 90 switch (priv->speed) { 91 case 10: /* 10BASE */ 92 ravb_write(ndev, GBETH_GECMR_SPEED_10, GECMR); 93 break; 94 case 100: /* 100BASE */ 95 ravb_write(ndev, GBETH_GECMR_SPEED_100, GECMR); 96 break; 97 case 1000: /* 1000BASE */ 98 ravb_write(ndev, GBETH_GECMR_SPEED_1000, GECMR); 99 break; 100 } 101 } 102 103 static void ravb_set_rate_rcar(struct net_device *ndev) 104 { 105 struct ravb_private *priv = netdev_priv(ndev); 106 107 switch (priv->speed) { 108 case 100: /* 100BASE */ 109 ravb_write(ndev, GECMR_SPEED_100, GECMR); 110 break; 111 case 1000: /* 1000BASE */ 112 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 113 break; 114 } 115 } 116 117 /* Get MAC address from the MAC address registers 118 * 119 * Ethernet AVB device doesn't have ROM for MAC address. 120 * This function gets the MAC address that was used by a bootloader. 121 */ 122 static void ravb_read_mac_address(struct device_node *np, 123 struct net_device *ndev) 124 { 125 int ret; 126 127 ret = of_get_ethdev_address(np, ndev); 128 if (ret) { 129 u32 mahr = ravb_read(ndev, MAHR); 130 u32 malr = ravb_read(ndev, MALR); 131 u8 addr[ETH_ALEN]; 132 133 addr[0] = (mahr >> 24) & 0xFF; 134 addr[1] = (mahr >> 16) & 0xFF; 135 addr[2] = (mahr >> 8) & 0xFF; 136 addr[3] = (mahr >> 0) & 0xFF; 137 addr[4] = (malr >> 8) & 0xFF; 138 addr[5] = (malr >> 0) & 0xFF; 139 eth_hw_addr_set(ndev, addr); 140 } 141 } 142 143 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 144 { 145 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 146 mdiobb); 147 148 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 149 } 150 151 /* MDC pin control */ 152 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 153 { 154 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 155 } 156 157 /* Data I/O pin control */ 158 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 159 { 160 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 161 } 162 163 /* Set data bit */ 164 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 165 { 166 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 167 } 168 169 /* Get data bit */ 170 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 171 { 172 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 173 mdiobb); 174 175 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 176 } 177 178 /* MDIO bus control struct */ 179 static const struct mdiobb_ops bb_ops = { 180 .owner = THIS_MODULE, 181 .set_mdc = ravb_set_mdc, 182 .set_mdio_dir = ravb_set_mdio_dir, 183 .set_mdio_data = ravb_set_mdio_data, 184 .get_mdio_data = ravb_get_mdio_data, 185 }; 186 187 static struct ravb_rx_desc * 188 ravb_rx_get_desc(struct ravb_private *priv, unsigned int q, 189 unsigned int i) 190 { 191 return priv->rx_ring[q].raw + priv->info->rx_desc_size * i; 192 } 193 194 /* Free TX skb function for AVB-IP */ 195 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 196 { 197 struct ravb_private *priv = netdev_priv(ndev); 198 struct net_device_stats *stats = &priv->stats[q]; 199 unsigned int num_tx_desc = priv->num_tx_desc; 200 struct ravb_tx_desc *desc; 201 unsigned int entry; 202 int free_num = 0; 203 u32 size; 204 205 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 206 bool txed; 207 208 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 209 num_tx_desc); 210 desc = &priv->tx_ring[q][entry]; 211 txed = desc->die_dt == DT_FEMPTY; 212 if (free_txed_only && !txed) 213 break; 214 /* Descriptor type must be checked before all other reads */ 215 dma_rmb(); 216 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 217 /* Free the original skb. */ 218 if (priv->tx_skb[q][entry / num_tx_desc]) { 219 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 220 size, DMA_TO_DEVICE); 221 /* Last packet descriptor? */ 222 if (entry % num_tx_desc == num_tx_desc - 1) { 223 entry /= num_tx_desc; 224 dev_kfree_skb_any(priv->tx_skb[q][entry]); 225 priv->tx_skb[q][entry] = NULL; 226 if (txed) 227 stats->tx_packets++; 228 } 229 free_num++; 230 } 231 if (txed) 232 stats->tx_bytes += size; 233 desc->die_dt = DT_EEMPTY; 234 } 235 return free_num; 236 } 237 238 static void ravb_rx_ring_free(struct net_device *ndev, int q) 239 { 240 struct ravb_private *priv = netdev_priv(ndev); 241 unsigned int ring_size; 242 243 if (!priv->rx_ring[q].raw) 244 return; 245 246 ring_size = priv->info->rx_desc_size * (priv->num_rx_ring[q] + 1); 247 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q].raw, 248 priv->rx_desc_dma[q]); 249 priv->rx_ring[q].raw = NULL; 250 } 251 252 /* Free skb's and DMA buffers for Ethernet AVB */ 253 static void ravb_ring_free(struct net_device *ndev, int q) 254 { 255 struct ravb_private *priv = netdev_priv(ndev); 256 unsigned int num_tx_desc = priv->num_tx_desc; 257 unsigned int ring_size; 258 unsigned int i; 259 260 ravb_rx_ring_free(ndev, q); 261 262 if (priv->tx_ring[q]) { 263 ravb_tx_free(ndev, q, false); 264 265 ring_size = sizeof(struct ravb_tx_desc) * 266 (priv->num_tx_ring[q] * num_tx_desc + 1); 267 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 268 priv->tx_desc_dma[q]); 269 priv->tx_ring[q] = NULL; 270 } 271 272 /* Free RX buffers */ 273 for (i = 0; i < priv->num_rx_ring[q]; i++) { 274 if (priv->rx_buffers[q][i].page) 275 page_pool_put_page(priv->rx_pool[q], 276 priv->rx_buffers[q][i].page, 277 0, true); 278 } 279 kfree(priv->rx_buffers[q]); 280 priv->rx_buffers[q] = NULL; 281 page_pool_destroy(priv->rx_pool[q]); 282 283 /* Free aligned TX buffers */ 284 kfree(priv->tx_align[q]); 285 priv->tx_align[q] = NULL; 286 287 /* Free TX skb ringbuffer. 288 * SKBs are freed by ravb_tx_free() call above. 289 */ 290 kfree(priv->tx_skb[q]); 291 priv->tx_skb[q] = NULL; 292 } 293 294 static int 295 ravb_alloc_rx_buffer(struct net_device *ndev, int q, u32 entry, gfp_t gfp_mask, 296 struct ravb_rx_desc *rx_desc) 297 { 298 struct ravb_private *priv = netdev_priv(ndev); 299 const struct ravb_hw_info *info = priv->info; 300 struct ravb_rx_buffer *rx_buff; 301 dma_addr_t dma_addr; 302 unsigned int size; 303 304 rx_buff = &priv->rx_buffers[q][entry]; 305 size = info->rx_buffer_size; 306 rx_buff->page = page_pool_alloc(priv->rx_pool[q], &rx_buff->offset, 307 &size, gfp_mask); 308 if (unlikely(!rx_buff->page)) { 309 /* We just set the data size to 0 for a failed mapping which 310 * should prevent DMA from happening... 311 */ 312 rx_desc->ds_cc = cpu_to_le16(0); 313 return -ENOMEM; 314 } 315 316 dma_addr = page_pool_get_dma_addr(rx_buff->page) + rx_buff->offset; 317 dma_sync_single_for_device(ndev->dev.parent, dma_addr, 318 info->rx_buffer_size, DMA_FROM_DEVICE); 319 rx_desc->dptr = cpu_to_le32(dma_addr); 320 321 /* The end of the RX buffer is used to store skb shared data, so we need 322 * to ensure that the hardware leaves enough space for this. 323 */ 324 rx_desc->ds_cc = cpu_to_le16(info->rx_buffer_size - 325 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) - 326 ETH_FCS_LEN + sizeof(__sum16)); 327 return 0; 328 } 329 330 static u32 331 ravb_rx_ring_refill(struct net_device *ndev, int q, u32 count, gfp_t gfp_mask) 332 { 333 struct ravb_private *priv = netdev_priv(ndev); 334 struct ravb_rx_desc *rx_desc; 335 u32 i, entry; 336 337 for (i = 0; i < count; i++) { 338 entry = (priv->dirty_rx[q] + i) % priv->num_rx_ring[q]; 339 rx_desc = ravb_rx_get_desc(priv, q, entry); 340 341 if (!priv->rx_buffers[q][entry].page) { 342 if (unlikely(ravb_alloc_rx_buffer(ndev, q, entry, 343 gfp_mask, rx_desc))) 344 break; 345 } 346 /* Descriptor type must be set after all the above writes */ 347 dma_wmb(); 348 rx_desc->die_dt = DT_FEMPTY; 349 } 350 351 return i; 352 } 353 354 /* Format skb and descriptor buffer for Ethernet AVB */ 355 static void ravb_ring_format(struct net_device *ndev, int q) 356 { 357 struct ravb_private *priv = netdev_priv(ndev); 358 unsigned int num_tx_desc = priv->num_tx_desc; 359 struct ravb_rx_desc *rx_desc; 360 struct ravb_tx_desc *tx_desc; 361 struct ravb_desc *desc; 362 unsigned int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 363 num_tx_desc; 364 unsigned int i; 365 366 priv->cur_rx[q] = 0; 367 priv->cur_tx[q] = 0; 368 priv->dirty_rx[q] = 0; 369 priv->dirty_tx[q] = 0; 370 371 /* Regular RX descriptors have already been initialized by 372 * ravb_rx_ring_refill(), we just need to initialize the final link 373 * descriptor. 374 */ 375 rx_desc = ravb_rx_get_desc(priv, q, priv->num_rx_ring[q]); 376 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 377 rx_desc->die_dt = DT_LINKFIX; /* type */ 378 379 memset(priv->tx_ring[q], 0, tx_ring_size); 380 /* Build TX ring buffer */ 381 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 382 i++, tx_desc++) { 383 tx_desc->die_dt = DT_EEMPTY; 384 if (num_tx_desc > 1) { 385 tx_desc++; 386 tx_desc->die_dt = DT_EEMPTY; 387 } 388 } 389 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 390 tx_desc->die_dt = DT_LINKFIX; /* type */ 391 392 /* RX descriptor base address for best effort */ 393 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 394 desc->die_dt = DT_LINKFIX; /* type */ 395 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 396 397 /* TX descriptor base address for best effort */ 398 desc = &priv->desc_bat[q]; 399 desc->die_dt = DT_LINKFIX; /* type */ 400 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 401 } 402 403 static void *ravb_alloc_rx_desc(struct net_device *ndev, int q) 404 { 405 struct ravb_private *priv = netdev_priv(ndev); 406 unsigned int ring_size; 407 408 ring_size = priv->info->rx_desc_size * (priv->num_rx_ring[q] + 1); 409 410 priv->rx_ring[q].raw = dma_alloc_coherent(ndev->dev.parent, ring_size, 411 &priv->rx_desc_dma[q], 412 GFP_KERNEL); 413 414 return priv->rx_ring[q].raw; 415 } 416 417 /* Init skb and descriptor buffer for Ethernet AVB */ 418 static int ravb_ring_init(struct net_device *ndev, int q) 419 { 420 struct ravb_private *priv = netdev_priv(ndev); 421 unsigned int num_tx_desc = priv->num_tx_desc; 422 struct page_pool_params params = { 423 .order = 0, 424 .flags = PP_FLAG_DMA_MAP, 425 .pool_size = priv->num_rx_ring[q], 426 .nid = NUMA_NO_NODE, 427 .dev = ndev->dev.parent, 428 .dma_dir = DMA_FROM_DEVICE, 429 }; 430 unsigned int ring_size; 431 u32 num_filled; 432 433 /* Allocate RX page pool and buffers */ 434 priv->rx_pool[q] = page_pool_create(¶ms); 435 if (IS_ERR(priv->rx_pool[q])) 436 goto error; 437 438 /* Allocate RX buffers */ 439 priv->rx_buffers[q] = kcalloc(priv->num_rx_ring[q], 440 sizeof(*priv->rx_buffers[q]), GFP_KERNEL); 441 if (!priv->rx_buffers[q]) 442 goto error; 443 444 /* Allocate TX skb rings */ 445 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q], 446 sizeof(*priv->tx_skb[q]), GFP_KERNEL); 447 if (!priv->tx_skb[q]) 448 goto error; 449 450 /* Allocate all RX descriptors. */ 451 if (!ravb_alloc_rx_desc(ndev, q)) 452 goto error; 453 454 /* Populate RX ring buffer. */ 455 priv->dirty_rx[q] = 0; 456 ring_size = priv->info->rx_desc_size * priv->num_rx_ring[q]; 457 memset(priv->rx_ring[q].raw, 0, ring_size); 458 num_filled = ravb_rx_ring_refill(ndev, q, priv->num_rx_ring[q], 459 GFP_KERNEL); 460 if (num_filled != priv->num_rx_ring[q]) 461 goto error; 462 463 if (num_tx_desc > 1) { 464 /* Allocate rings for the aligned buffers */ 465 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 466 DPTR_ALIGN - 1, GFP_KERNEL); 467 if (!priv->tx_align[q]) 468 goto error; 469 } 470 471 /* Allocate all TX descriptors. */ 472 ring_size = sizeof(struct ravb_tx_desc) * 473 (priv->num_tx_ring[q] * num_tx_desc + 1); 474 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 475 &priv->tx_desc_dma[q], 476 GFP_KERNEL); 477 if (!priv->tx_ring[q]) 478 goto error; 479 480 return 0; 481 482 error: 483 ravb_ring_free(ndev, q); 484 485 return -ENOMEM; 486 } 487 488 static void ravb_csum_init_gbeth(struct net_device *ndev) 489 { 490 bool tx_enable = ndev->features & NETIF_F_HW_CSUM; 491 bool rx_enable = ndev->features & NETIF_F_RXCSUM; 492 493 if (!(tx_enable || rx_enable)) 494 goto done; 495 496 ravb_write(ndev, 0, CSR0); 497 if (ravb_wait(ndev, CSR0, CSR0_TPE | CSR0_RPE, 0)) { 498 netdev_err(ndev, "Timeout enabling hardware checksum\n"); 499 500 if (tx_enable) 501 ndev->features &= ~NETIF_F_HW_CSUM; 502 503 if (rx_enable) 504 ndev->features &= ~NETIF_F_RXCSUM; 505 } else { 506 if (tx_enable) 507 ravb_write(ndev, CSR1_CSUM_ENABLE, CSR1); 508 509 if (rx_enable) 510 ravb_write(ndev, CSR2_CSUM_ENABLE, CSR2); 511 } 512 513 done: 514 ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0); 515 } 516 517 static void ravb_emac_init_gbeth(struct net_device *ndev) 518 { 519 struct ravb_private *priv = netdev_priv(ndev); 520 521 if (priv->phy_interface == PHY_INTERFACE_MODE_MII) { 522 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35); 523 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0); 524 } else { 525 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_RGMII, CXR35); 526 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 527 CXR31_SEL_LINK0); 528 } 529 530 /* Receive frame limit set register */ 531 ravb_write(ndev, priv->info->rx_max_frame_size + ETH_FCS_LEN, RFLR); 532 533 /* EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through */ 534 ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) | 535 ECMR_TE | ECMR_RE | ECMR_RCPT | 536 ECMR_TXF | ECMR_RXF, ECMR); 537 538 ravb_set_rate_gbeth(ndev); 539 540 /* Set MAC address */ 541 ravb_write(ndev, 542 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 543 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 544 ravb_write(ndev, (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 545 546 /* E-MAC status register clear */ 547 ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR); 548 549 ravb_csum_init_gbeth(ndev); 550 551 /* E-MAC interrupt enable register */ 552 ravb_write(ndev, ECSIPR_ICDIP, ECSIPR); 553 } 554 555 static void ravb_emac_init_rcar(struct net_device *ndev) 556 { 557 struct ravb_private *priv = netdev_priv(ndev); 558 559 /* Set receive frame length 560 * 561 * The length set here describes the frame from the destination address 562 * up to and including the CRC data. However only the frame data, 563 * excluding the CRC, are transferred to memory. To allow for the 564 * largest frames add the CRC length to the maximum Rx descriptor size. 565 */ 566 ravb_write(ndev, priv->info->rx_max_frame_size + ETH_FCS_LEN, RFLR); 567 568 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 569 ravb_write(ndev, ECMR_ZPF | ECMR_DM | 570 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 571 ECMR_TE | ECMR_RE, ECMR); 572 573 ravb_set_rate_rcar(ndev); 574 575 /* Set MAC address */ 576 ravb_write(ndev, 577 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 578 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 579 ravb_write(ndev, 580 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 581 582 /* E-MAC status register clear */ 583 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 584 585 /* E-MAC interrupt enable register */ 586 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 587 } 588 589 static void ravb_emac_init_rcar_gen4(struct net_device *ndev) 590 { 591 struct ravb_private *priv = netdev_priv(ndev); 592 bool mii = priv->phy_interface == PHY_INTERFACE_MODE_MII; 593 594 ravb_modify(ndev, APSR, APSR_MIISELECT, mii ? APSR_MIISELECT : 0); 595 596 ravb_emac_init_rcar(ndev); 597 } 598 599 /* E-MAC init function */ 600 static void ravb_emac_init(struct net_device *ndev) 601 { 602 struct ravb_private *priv = netdev_priv(ndev); 603 const struct ravb_hw_info *info = priv->info; 604 605 info->emac_init(ndev); 606 } 607 608 static int ravb_dmac_init_gbeth(struct net_device *ndev) 609 { 610 struct ravb_private *priv = netdev_priv(ndev); 611 int error; 612 613 error = ravb_ring_init(ndev, RAVB_BE); 614 if (error) 615 return error; 616 617 /* Descriptor format */ 618 ravb_ring_format(ndev, RAVB_BE); 619 620 /* Set DMAC RX */ 621 ravb_write(ndev, 0x60000000, RCR); 622 623 /* Set Max Frame Length (RTC) */ 624 ravb_write(ndev, 0x7ffc0000 | priv->info->rx_max_frame_size, RTC); 625 626 /* Set FIFO size */ 627 ravb_write(ndev, 0x00222200, TGC); 628 629 ravb_write(ndev, 0, TCCR); 630 631 /* Frame receive */ 632 ravb_write(ndev, RIC0_FRE0, RIC0); 633 /* Disable FIFO full warning */ 634 ravb_write(ndev, 0x0, RIC1); 635 /* Receive FIFO full error, descriptor empty */ 636 ravb_write(ndev, RIC2_QFE0 | RIC2_RFFE, RIC2); 637 638 ravb_write(ndev, TIC_FTE0, TIC); 639 640 return 0; 641 } 642 643 static int ravb_dmac_init_rcar(struct net_device *ndev) 644 { 645 struct ravb_private *priv = netdev_priv(ndev); 646 const struct ravb_hw_info *info = priv->info; 647 int error; 648 649 error = ravb_ring_init(ndev, RAVB_BE); 650 if (error) 651 return error; 652 error = ravb_ring_init(ndev, RAVB_NC); 653 if (error) { 654 ravb_ring_free(ndev, RAVB_BE); 655 return error; 656 } 657 658 /* Descriptor format */ 659 ravb_ring_format(ndev, RAVB_BE); 660 ravb_ring_format(ndev, RAVB_NC); 661 662 /* Set AVB RX */ 663 ravb_write(ndev, 664 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 665 666 /* Set FIFO size */ 667 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC); 668 669 /* Timestamp enable */ 670 ravb_write(ndev, TCCR_TFEN, TCCR); 671 672 /* Interrupt init: */ 673 if (info->multi_irqs) { 674 /* Clear DIL.DPLx */ 675 ravb_write(ndev, 0, DIL); 676 /* Set queue specific interrupt */ 677 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 678 } 679 /* Frame receive */ 680 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 681 /* Disable FIFO full warning */ 682 ravb_write(ndev, 0, RIC1); 683 /* Receive FIFO full error, descriptor empty */ 684 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 685 /* Frame transmitted, timestamp FIFO updated */ 686 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 687 688 return 0; 689 } 690 691 /* Device init function for Ethernet AVB */ 692 static int ravb_dmac_init(struct net_device *ndev) 693 { 694 struct ravb_private *priv = netdev_priv(ndev); 695 const struct ravb_hw_info *info = priv->info; 696 int error; 697 698 /* Set CONFIG mode */ 699 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 700 if (error) 701 return error; 702 703 error = info->dmac_init(ndev); 704 if (error) 705 return error; 706 707 /* Setting the control will start the AVB-DMAC process. */ 708 return ravb_set_opmode(ndev, CCC_OPC_OPERATION); 709 } 710 711 static void ravb_get_tx_tstamp(struct net_device *ndev) 712 { 713 struct ravb_private *priv = netdev_priv(ndev); 714 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 715 struct skb_shared_hwtstamps shhwtstamps; 716 struct sk_buff *skb; 717 struct timespec64 ts; 718 u16 tag, tfa_tag; 719 int count; 720 u32 tfa2; 721 722 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 723 while (count--) { 724 tfa2 = ravb_read(ndev, TFA2); 725 tfa_tag = (tfa2 & TFA2_TST) >> 16; 726 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 727 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 728 ravb_read(ndev, TFA1); 729 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 730 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 731 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 732 list) { 733 skb = ts_skb->skb; 734 tag = ts_skb->tag; 735 list_del(&ts_skb->list); 736 kfree(ts_skb); 737 if (tag == tfa_tag) { 738 skb_tstamp_tx(skb, &shhwtstamps); 739 dev_consume_skb_any(skb); 740 break; 741 } else { 742 dev_kfree_skb_any(skb); 743 } 744 } 745 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 746 } 747 } 748 749 static void ravb_rx_csum_gbeth(struct sk_buff *skb) 750 { 751 struct skb_shared_info *shinfo = skb_shinfo(skb); 752 size_t csum_len; 753 u16 *hw_csum; 754 755 /* The hardware checksum status is contained in 4 bytes appended to 756 * packet data. 757 * 758 * For ipv4, the first 2 bytes are the ip header checksum status. We can 759 * ignore this as it will always be re-checked in inet_gro_receive(). 760 * 761 * The last 2 bytes are the protocol checksum status which will be zero 762 * if the checksum has been validated. 763 */ 764 csum_len = sizeof(*hw_csum) * 2; 765 if (unlikely(skb->len < csum_len)) 766 return; 767 768 if (skb_is_nonlinear(skb)) { 769 skb_frag_t *last_frag = &shinfo->frags[shinfo->nr_frags - 1]; 770 771 hw_csum = (u16 *)(skb_frag_address(last_frag) + 772 skb_frag_size(last_frag)); 773 skb_frag_size_sub(last_frag, csum_len); 774 } else { 775 hw_csum = (u16 *)skb_tail_pointer(skb); 776 skb_trim(skb, skb->len - csum_len); 777 } 778 779 if (!get_unaligned(--hw_csum)) 780 skb->ip_summed = CHECKSUM_UNNECESSARY; 781 } 782 783 static void ravb_rx_csum(struct sk_buff *skb) 784 { 785 u8 *hw_csum; 786 787 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes 788 * appended to packet data 789 */ 790 if (unlikely(skb->len < sizeof(__sum16))) 791 return; 792 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); 793 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 794 skb->ip_summed = CHECKSUM_COMPLETE; 795 skb_trim(skb, skb->len - sizeof(__sum16)); 796 } 797 798 /* Packet receive function for Gigabit Ethernet */ 799 static int ravb_rx_gbeth(struct net_device *ndev, int budget, int q) 800 { 801 struct ravb_private *priv = netdev_priv(ndev); 802 const struct ravb_hw_info *info = priv->info; 803 struct net_device_stats *stats; 804 struct ravb_rx_desc *desc; 805 int rx_packets = 0; 806 u8 desc_status; 807 u16 desc_len; 808 u8 die_dt; 809 int entry; 810 int limit; 811 int i; 812 813 limit = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q]; 814 stats = &priv->stats[q]; 815 816 for (i = 0; i < limit; i++, priv->cur_rx[q]++) { 817 struct sk_buff *skb = NULL; 818 819 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 820 desc = &priv->rx_ring[q].desc[entry]; 821 if (rx_packets == budget || desc->die_dt == DT_FEMPTY) 822 break; 823 824 /* Descriptor type must be checked before all other reads */ 825 dma_rmb(); 826 desc_status = desc->msc; 827 desc_len = le16_to_cpu(desc->ds_cc) & RX_DS; 828 829 /* We use 0-byte descriptors to mark the DMA mapping errors */ 830 if (!desc_len) 831 continue; 832 833 if (desc_status & MSC_MC) 834 stats->multicast++; 835 836 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | MSC_CEEF)) { 837 stats->rx_errors++; 838 if (desc_status & MSC_CRC) 839 stats->rx_crc_errors++; 840 if (desc_status & MSC_RFE) 841 stats->rx_frame_errors++; 842 if (desc_status & (MSC_RTLF | MSC_RTSF)) 843 stats->rx_length_errors++; 844 if (desc_status & MSC_CEEF) 845 stats->rx_missed_errors++; 846 } else { 847 struct ravb_rx_buffer *rx_buff; 848 void *rx_addr; 849 850 rx_buff = &priv->rx_buffers[q][entry]; 851 rx_addr = page_address(rx_buff->page) + rx_buff->offset; 852 die_dt = desc->die_dt & 0xF0; 853 dma_sync_single_for_cpu(ndev->dev.parent, 854 le32_to_cpu(desc->dptr), 855 desc_len, DMA_FROM_DEVICE); 856 857 switch (die_dt) { 858 case DT_FSINGLE: 859 case DT_FSTART: 860 /* Start of packet: Set initial data length. */ 861 skb = napi_build_skb(rx_addr, 862 info->rx_buffer_size); 863 if (unlikely(!skb)) { 864 stats->rx_errors++; 865 page_pool_put_page(priv->rx_pool[q], 866 rx_buff->page, 0, 867 true); 868 goto refill; 869 } 870 skb_mark_for_recycle(skb); 871 skb_put(skb, desc_len); 872 873 /* Save this skb if the packet spans multiple 874 * descriptors. 875 */ 876 if (die_dt == DT_FSTART) 877 priv->rx_1st_skb = skb; 878 break; 879 880 case DT_FMID: 881 case DT_FEND: 882 /* Continuing a packet: Add this buffer as an RX 883 * frag. 884 */ 885 886 /* rx_1st_skb will be NULL if napi_build_skb() 887 * failed for the first descriptor of a 888 * multi-descriptor packet. 889 */ 890 if (unlikely(!priv->rx_1st_skb)) { 891 stats->rx_errors++; 892 page_pool_put_page(priv->rx_pool[q], 893 rx_buff->page, 0, 894 true); 895 896 /* We may find a DT_FSINGLE or DT_FSTART 897 * descriptor in the queue which we can 898 * process, so don't give up yet. 899 */ 900 continue; 901 } 902 skb_add_rx_frag(priv->rx_1st_skb, 903 skb_shinfo(priv->rx_1st_skb)->nr_frags, 904 rx_buff->page, rx_buff->offset, 905 desc_len, info->rx_buffer_size); 906 907 /* Set skb to point at the whole packet so that 908 * we only need one code path for finishing a 909 * packet. 910 */ 911 skb = priv->rx_1st_skb; 912 } 913 914 switch (die_dt) { 915 case DT_FSINGLE: 916 case DT_FEND: 917 /* Finishing a packet: Determine protocol & 918 * checksum, hand off to NAPI and update our 919 * stats. 920 */ 921 skb->protocol = eth_type_trans(skb, ndev); 922 if (ndev->features & NETIF_F_RXCSUM) 923 ravb_rx_csum_gbeth(skb); 924 stats->rx_bytes += skb->len; 925 napi_gro_receive(&priv->napi[q], skb); 926 rx_packets++; 927 928 /* Clear rx_1st_skb so that it will only be 929 * non-NULL when valid. 930 */ 931 priv->rx_1st_skb = NULL; 932 } 933 934 /* Mark this RX buffer as consumed. */ 935 rx_buff->page = NULL; 936 } 937 } 938 939 refill: 940 /* Refill the RX ring buffers. */ 941 priv->dirty_rx[q] += ravb_rx_ring_refill(ndev, q, 942 priv->cur_rx[q] - priv->dirty_rx[q], 943 GFP_ATOMIC); 944 945 stats->rx_packets += rx_packets; 946 return rx_packets; 947 } 948 949 /* Packet receive function for Ethernet AVB */ 950 static int ravb_rx_rcar(struct net_device *ndev, int budget, int q) 951 { 952 struct ravb_private *priv = netdev_priv(ndev); 953 const struct ravb_hw_info *info = priv->info; 954 struct net_device_stats *stats = &priv->stats[q]; 955 struct ravb_ex_rx_desc *desc; 956 unsigned int limit, i; 957 struct sk_buff *skb; 958 struct timespec64 ts; 959 int rx_packets = 0; 960 u8 desc_status; 961 u16 pkt_len; 962 int entry; 963 964 limit = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q]; 965 for (i = 0; i < limit; i++, priv->cur_rx[q]++) { 966 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 967 desc = &priv->rx_ring[q].ex_desc[entry]; 968 if (rx_packets == budget || desc->die_dt == DT_FEMPTY) 969 break; 970 971 /* Descriptor type must be checked before all other reads */ 972 dma_rmb(); 973 desc_status = desc->msc; 974 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 975 976 /* We use 0-byte descriptors to mark the DMA mapping errors */ 977 if (!pkt_len) 978 continue; 979 980 if (desc_status & MSC_MC) 981 stats->multicast++; 982 983 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 984 MSC_CEEF)) { 985 stats->rx_errors++; 986 if (desc_status & MSC_CRC) 987 stats->rx_crc_errors++; 988 if (desc_status & MSC_RFE) 989 stats->rx_frame_errors++; 990 if (desc_status & (MSC_RTLF | MSC_RTSF)) 991 stats->rx_length_errors++; 992 if (desc_status & MSC_CEEF) 993 stats->rx_missed_errors++; 994 } else { 995 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE; 996 struct ravb_rx_buffer *rx_buff; 997 void *rx_addr; 998 999 rx_buff = &priv->rx_buffers[q][entry]; 1000 rx_addr = page_address(rx_buff->page) + rx_buff->offset; 1001 dma_sync_single_for_cpu(ndev->dev.parent, 1002 le32_to_cpu(desc->dptr), 1003 pkt_len, DMA_FROM_DEVICE); 1004 1005 skb = napi_build_skb(rx_addr, info->rx_buffer_size); 1006 if (unlikely(!skb)) { 1007 stats->rx_errors++; 1008 page_pool_put_page(priv->rx_pool[q], 1009 rx_buff->page, 0, true); 1010 break; 1011 } 1012 skb_mark_for_recycle(skb); 1013 get_ts &= (q == RAVB_NC) ? 1014 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT : 1015 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 1016 if (get_ts) { 1017 struct skb_shared_hwtstamps *shhwtstamps; 1018 1019 shhwtstamps = skb_hwtstamps(skb); 1020 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 1021 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) << 1022 32) | le32_to_cpu(desc->ts_sl); 1023 ts.tv_nsec = le32_to_cpu(desc->ts_n); 1024 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 1025 } 1026 1027 skb_put(skb, pkt_len); 1028 skb->protocol = eth_type_trans(skb, ndev); 1029 if (ndev->features & NETIF_F_RXCSUM) 1030 ravb_rx_csum(skb); 1031 napi_gro_receive(&priv->napi[q], skb); 1032 rx_packets++; 1033 stats->rx_bytes += pkt_len; 1034 1035 /* Mark this RX buffer as consumed. */ 1036 rx_buff->page = NULL; 1037 } 1038 } 1039 1040 /* Refill the RX ring buffers. */ 1041 priv->dirty_rx[q] += ravb_rx_ring_refill(ndev, q, 1042 priv->cur_rx[q] - priv->dirty_rx[q], 1043 GFP_ATOMIC); 1044 1045 stats->rx_packets += rx_packets; 1046 return rx_packets; 1047 } 1048 1049 /* Packet receive function for Ethernet AVB */ 1050 static int ravb_rx(struct net_device *ndev, int budget, int q) 1051 { 1052 struct ravb_private *priv = netdev_priv(ndev); 1053 const struct ravb_hw_info *info = priv->info; 1054 1055 return info->receive(ndev, budget, q); 1056 } 1057 1058 static void ravb_rcv_snd_disable(struct net_device *ndev) 1059 { 1060 /* Disable TX and RX */ 1061 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 1062 } 1063 1064 static void ravb_rcv_snd_enable(struct net_device *ndev) 1065 { 1066 /* Enable TX and RX */ 1067 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 1068 } 1069 1070 /* function for waiting dma process finished */ 1071 static int ravb_stop_dma(struct net_device *ndev) 1072 { 1073 struct ravb_private *priv = netdev_priv(ndev); 1074 const struct ravb_hw_info *info = priv->info; 1075 int error; 1076 1077 /* Wait for stopping the hardware TX process */ 1078 error = ravb_wait(ndev, TCCR, info->tccr_mask, 0); 1079 1080 if (error) 1081 return error; 1082 1083 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 1084 0); 1085 if (error) 1086 return error; 1087 1088 /* Stop the E-MAC's RX/TX processes. */ 1089 ravb_rcv_snd_disable(ndev); 1090 1091 /* Wait for stopping the RX DMA process */ 1092 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 1093 if (error) 1094 return error; 1095 1096 /* Stop AVB-DMAC process */ 1097 return ravb_set_opmode(ndev, CCC_OPC_CONFIG); 1098 } 1099 1100 /* E-MAC interrupt handler */ 1101 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 1102 { 1103 struct ravb_private *priv = netdev_priv(ndev); 1104 u32 ecsr, psr; 1105 1106 ecsr = ravb_read(ndev, ECSR); 1107 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 1108 1109 if (ecsr & ECSR_MPD) 1110 pm_wakeup_event(&priv->pdev->dev, 0); 1111 if (ecsr & ECSR_ICD) 1112 ndev->stats.tx_carrier_errors++; 1113 if (ecsr & ECSR_LCHNG) { 1114 /* Link changed */ 1115 if (priv->no_avb_link) 1116 return; 1117 psr = ravb_read(ndev, PSR); 1118 if (priv->avb_link_active_low) 1119 psr ^= PSR_LMON; 1120 if (!(psr & PSR_LMON)) { 1121 /* DIsable RX and TX */ 1122 ravb_rcv_snd_disable(ndev); 1123 } else { 1124 /* Enable RX and TX */ 1125 ravb_rcv_snd_enable(ndev); 1126 } 1127 } 1128 } 1129 1130 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 1131 { 1132 struct net_device *ndev = dev_id; 1133 struct ravb_private *priv = netdev_priv(ndev); 1134 struct device *dev = &priv->pdev->dev; 1135 irqreturn_t result = IRQ_HANDLED; 1136 1137 pm_runtime_get_noresume(dev); 1138 1139 if (unlikely(!pm_runtime_active(dev))) { 1140 result = IRQ_NONE; 1141 goto out_rpm_put; 1142 } 1143 1144 spin_lock(&priv->lock); 1145 ravb_emac_interrupt_unlocked(ndev); 1146 spin_unlock(&priv->lock); 1147 1148 out_rpm_put: 1149 pm_runtime_put_noidle(dev); 1150 return result; 1151 } 1152 1153 /* Error interrupt handler */ 1154 static void ravb_error_interrupt(struct net_device *ndev) 1155 { 1156 struct ravb_private *priv = netdev_priv(ndev); 1157 u32 eis, ris2; 1158 1159 eis = ravb_read(ndev, EIS); 1160 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS); 1161 if (eis & EIS_QFS) { 1162 ris2 = ravb_read(ndev, RIS2); 1163 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_QFF1 | RIS2_RFFF | RIS2_RESERVED), 1164 RIS2); 1165 1166 /* Receive Descriptor Empty int */ 1167 if (ris2 & RIS2_QFF0) 1168 priv->stats[RAVB_BE].rx_over_errors++; 1169 1170 /* Receive Descriptor Empty int */ 1171 if (ris2 & RIS2_QFF1) 1172 priv->stats[RAVB_NC].rx_over_errors++; 1173 1174 /* Receive FIFO Overflow int */ 1175 if (ris2 & RIS2_RFFF) 1176 priv->rx_fifo_errors++; 1177 } 1178 } 1179 1180 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 1181 { 1182 struct ravb_private *priv = netdev_priv(ndev); 1183 const struct ravb_hw_info *info = priv->info; 1184 u32 ris0 = ravb_read(ndev, RIS0); 1185 u32 ric0 = ravb_read(ndev, RIC0); 1186 u32 tis = ravb_read(ndev, TIS); 1187 u32 tic = ravb_read(ndev, TIC); 1188 1189 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 1190 if (napi_schedule_prep(&priv->napi[q])) { 1191 /* Mask RX and TX interrupts */ 1192 if (!info->irq_en_dis) { 1193 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 1194 ravb_write(ndev, tic & ~BIT(q), TIC); 1195 } else { 1196 ravb_write(ndev, BIT(q), RID0); 1197 ravb_write(ndev, BIT(q), TID); 1198 } 1199 __napi_schedule(&priv->napi[q]); 1200 } else { 1201 netdev_warn(ndev, 1202 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 1203 ris0, ric0); 1204 netdev_warn(ndev, 1205 " tx status 0x%08x, tx mask 0x%08x.\n", 1206 tis, tic); 1207 } 1208 return true; 1209 } 1210 return false; 1211 } 1212 1213 static bool ravb_timestamp_interrupt(struct net_device *ndev) 1214 { 1215 u32 tis = ravb_read(ndev, TIS); 1216 1217 if (tis & TIS_TFUF) { 1218 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS); 1219 ravb_get_tx_tstamp(ndev); 1220 return true; 1221 } 1222 return false; 1223 } 1224 1225 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 1226 { 1227 struct net_device *ndev = dev_id; 1228 struct ravb_private *priv = netdev_priv(ndev); 1229 const struct ravb_hw_info *info = priv->info; 1230 struct device *dev = &priv->pdev->dev; 1231 irqreturn_t result = IRQ_NONE; 1232 u32 iss; 1233 1234 pm_runtime_get_noresume(dev); 1235 1236 if (unlikely(!pm_runtime_active(dev))) 1237 goto out_rpm_put; 1238 1239 spin_lock(&priv->lock); 1240 /* Get interrupt status */ 1241 iss = ravb_read(ndev, ISS); 1242 1243 /* Received and transmitted interrupts */ 1244 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 1245 int q; 1246 1247 /* Timestamp updated */ 1248 if (ravb_timestamp_interrupt(ndev)) 1249 result = IRQ_HANDLED; 1250 1251 /* Network control and best effort queue RX/TX */ 1252 if (info->nc_queues) { 1253 for (q = RAVB_NC; q >= RAVB_BE; q--) { 1254 if (ravb_queue_interrupt(ndev, q)) 1255 result = IRQ_HANDLED; 1256 } 1257 } else { 1258 if (ravb_queue_interrupt(ndev, RAVB_BE)) 1259 result = IRQ_HANDLED; 1260 } 1261 } 1262 1263 /* E-MAC status summary */ 1264 if (iss & ISS_MS) { 1265 ravb_emac_interrupt_unlocked(ndev); 1266 result = IRQ_HANDLED; 1267 } 1268 1269 /* Error status summary */ 1270 if (iss & ISS_ES) { 1271 ravb_error_interrupt(ndev); 1272 result = IRQ_HANDLED; 1273 } 1274 1275 /* gPTP interrupt status summary */ 1276 if (iss & ISS_CGIS) { 1277 ravb_ptp_interrupt(ndev); 1278 result = IRQ_HANDLED; 1279 } 1280 1281 spin_unlock(&priv->lock); 1282 1283 out_rpm_put: 1284 pm_runtime_put_noidle(dev); 1285 return result; 1286 } 1287 1288 /* Timestamp/Error/gPTP interrupt handler */ 1289 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 1290 { 1291 struct net_device *ndev = dev_id; 1292 struct ravb_private *priv = netdev_priv(ndev); 1293 struct device *dev = &priv->pdev->dev; 1294 irqreturn_t result = IRQ_NONE; 1295 u32 iss; 1296 1297 pm_runtime_get_noresume(dev); 1298 1299 if (unlikely(!pm_runtime_active(dev))) 1300 goto out_rpm_put; 1301 1302 spin_lock(&priv->lock); 1303 /* Get interrupt status */ 1304 iss = ravb_read(ndev, ISS); 1305 1306 /* Timestamp updated */ 1307 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 1308 result = IRQ_HANDLED; 1309 1310 /* Error status summary */ 1311 if (iss & ISS_ES) { 1312 ravb_error_interrupt(ndev); 1313 result = IRQ_HANDLED; 1314 } 1315 1316 /* gPTP interrupt status summary */ 1317 if (iss & ISS_CGIS) { 1318 ravb_ptp_interrupt(ndev); 1319 result = IRQ_HANDLED; 1320 } 1321 1322 spin_unlock(&priv->lock); 1323 1324 out_rpm_put: 1325 pm_runtime_put_noidle(dev); 1326 return result; 1327 } 1328 1329 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 1330 { 1331 struct net_device *ndev = dev_id; 1332 struct ravb_private *priv = netdev_priv(ndev); 1333 struct device *dev = &priv->pdev->dev; 1334 irqreturn_t result = IRQ_NONE; 1335 1336 pm_runtime_get_noresume(dev); 1337 1338 if (unlikely(!pm_runtime_active(dev))) 1339 goto out_rpm_put; 1340 1341 spin_lock(&priv->lock); 1342 1343 /* Network control/Best effort queue RX/TX */ 1344 if (ravb_queue_interrupt(ndev, q)) 1345 result = IRQ_HANDLED; 1346 1347 spin_unlock(&priv->lock); 1348 1349 out_rpm_put: 1350 pm_runtime_put_noidle(dev); 1351 return result; 1352 } 1353 1354 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 1355 { 1356 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 1357 } 1358 1359 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 1360 { 1361 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 1362 } 1363 1364 static int ravb_poll(struct napi_struct *napi, int budget) 1365 { 1366 struct net_device *ndev = napi->dev; 1367 struct ravb_private *priv = netdev_priv(ndev); 1368 const struct ravb_hw_info *info = priv->info; 1369 unsigned long flags; 1370 int q = napi - priv->napi; 1371 int mask = BIT(q); 1372 int work_done; 1373 1374 /* Processing RX Descriptor Ring */ 1375 /* Clear RX interrupt */ 1376 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0); 1377 work_done = ravb_rx(ndev, budget, q); 1378 1379 /* Processing TX Descriptor Ring */ 1380 spin_lock_irqsave(&priv->lock, flags); 1381 /* Clear TX interrupt */ 1382 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS); 1383 ravb_tx_free(ndev, q, true); 1384 netif_wake_subqueue(ndev, q); 1385 spin_unlock_irqrestore(&priv->lock, flags); 1386 1387 /* Receive error message handling */ 1388 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 1389 if (info->nc_queues) 1390 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 1391 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 1392 ndev->stats.rx_over_errors = priv->rx_over_errors; 1393 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 1394 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 1395 1396 if (work_done < budget && napi_complete_done(napi, work_done)) { 1397 /* Re-enable RX/TX interrupts */ 1398 spin_lock_irqsave(&priv->lock, flags); 1399 if (!info->irq_en_dis) { 1400 ravb_modify(ndev, RIC0, mask, mask); 1401 ravb_modify(ndev, TIC, mask, mask); 1402 } else { 1403 ravb_write(ndev, mask, RIE0); 1404 ravb_write(ndev, mask, TIE); 1405 } 1406 spin_unlock_irqrestore(&priv->lock, flags); 1407 } 1408 1409 return work_done; 1410 } 1411 1412 static void ravb_set_duplex_gbeth(struct net_device *ndev) 1413 { 1414 struct ravb_private *priv = netdev_priv(ndev); 1415 1416 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex > 0 ? ECMR_DM : 0); 1417 } 1418 1419 /* PHY state control function */ 1420 static void ravb_adjust_link(struct net_device *ndev) 1421 { 1422 struct ravb_private *priv = netdev_priv(ndev); 1423 const struct ravb_hw_info *info = priv->info; 1424 struct phy_device *phydev = ndev->phydev; 1425 bool new_state = false; 1426 unsigned long flags; 1427 1428 spin_lock_irqsave(&priv->lock, flags); 1429 1430 /* Disable TX and RX right over here, if E-MAC change is ignored */ 1431 if (priv->no_avb_link) 1432 ravb_rcv_snd_disable(ndev); 1433 1434 if (phydev->link) { 1435 if (info->half_duplex && phydev->duplex != priv->duplex) { 1436 new_state = true; 1437 priv->duplex = phydev->duplex; 1438 ravb_set_duplex_gbeth(ndev); 1439 } 1440 1441 if (phydev->speed != priv->speed) { 1442 new_state = true; 1443 priv->speed = phydev->speed; 1444 info->set_rate(ndev); 1445 } 1446 if (!priv->link) { 1447 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 1448 new_state = true; 1449 priv->link = phydev->link; 1450 } 1451 } else if (priv->link) { 1452 new_state = true; 1453 priv->link = 0; 1454 priv->speed = 0; 1455 if (info->half_duplex) 1456 priv->duplex = -1; 1457 } 1458 1459 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1460 if (priv->no_avb_link && phydev->link) 1461 ravb_rcv_snd_enable(ndev); 1462 1463 spin_unlock_irqrestore(&priv->lock, flags); 1464 1465 if (new_state && netif_msg_link(priv)) 1466 phy_print_status(phydev); 1467 } 1468 1469 /* PHY init function */ 1470 static int ravb_phy_init(struct net_device *ndev) 1471 { 1472 struct device_node *np = ndev->dev.parent->of_node; 1473 struct ravb_private *priv = netdev_priv(ndev); 1474 const struct ravb_hw_info *info = priv->info; 1475 struct phy_device *phydev; 1476 struct device_node *pn; 1477 phy_interface_t iface; 1478 int err; 1479 1480 priv->link = 0; 1481 priv->speed = 0; 1482 priv->duplex = -1; 1483 1484 /* Try connecting to PHY */ 1485 pn = of_parse_phandle(np, "phy-handle", 0); 1486 if (!pn) { 1487 /* In the case of a fixed PHY, the DT node associated 1488 * to the PHY is the Ethernet MAC DT node. 1489 */ 1490 if (of_phy_is_fixed_link(np)) { 1491 err = of_phy_register_fixed_link(np); 1492 if (err) 1493 return err; 1494 } 1495 pn = of_node_get(np); 1496 } 1497 1498 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII 1499 : priv->phy_interface; 1500 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface); 1501 of_node_put(pn); 1502 if (!phydev) { 1503 netdev_err(ndev, "failed to connect PHY\n"); 1504 err = -ENOENT; 1505 goto err_deregister_fixed_link; 1506 } 1507 1508 if (!info->half_duplex) { 1509 /* 10BASE, Pause and Asym Pause is not supported */ 1510 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1511 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1512 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT); 1513 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 1514 1515 /* Half Duplex is not supported */ 1516 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1517 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1518 } 1519 1520 phy_attached_info(phydev); 1521 1522 return 0; 1523 1524 err_deregister_fixed_link: 1525 if (of_phy_is_fixed_link(np)) 1526 of_phy_deregister_fixed_link(np); 1527 1528 return err; 1529 } 1530 1531 /* PHY control start function */ 1532 static int ravb_phy_start(struct net_device *ndev) 1533 { 1534 int error; 1535 1536 error = ravb_phy_init(ndev); 1537 if (error) 1538 return error; 1539 1540 phy_start(ndev->phydev); 1541 1542 return 0; 1543 } 1544 1545 static u32 ravb_get_msglevel(struct net_device *ndev) 1546 { 1547 struct ravb_private *priv = netdev_priv(ndev); 1548 1549 return priv->msg_enable; 1550 } 1551 1552 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1553 { 1554 struct ravb_private *priv = netdev_priv(ndev); 1555 1556 priv->msg_enable = value; 1557 } 1558 1559 static const char ravb_gstrings_stats_gbeth[][ETH_GSTRING_LEN] = { 1560 "rx_queue_0_current", 1561 "tx_queue_0_current", 1562 "rx_queue_0_dirty", 1563 "tx_queue_0_dirty", 1564 "rx_queue_0_packets", 1565 "tx_queue_0_packets", 1566 "rx_queue_0_bytes", 1567 "tx_queue_0_bytes", 1568 "rx_queue_0_mcast_packets", 1569 "rx_queue_0_errors", 1570 "rx_queue_0_crc_errors", 1571 "rx_queue_0_frame_errors", 1572 "rx_queue_0_length_errors", 1573 "rx_queue_0_csum_offload_errors", 1574 "rx_queue_0_over_errors", 1575 }; 1576 1577 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1578 "rx_queue_0_current", 1579 "tx_queue_0_current", 1580 "rx_queue_0_dirty", 1581 "tx_queue_0_dirty", 1582 "rx_queue_0_packets", 1583 "tx_queue_0_packets", 1584 "rx_queue_0_bytes", 1585 "tx_queue_0_bytes", 1586 "rx_queue_0_mcast_packets", 1587 "rx_queue_0_errors", 1588 "rx_queue_0_crc_errors", 1589 "rx_queue_0_frame_errors", 1590 "rx_queue_0_length_errors", 1591 "rx_queue_0_missed_errors", 1592 "rx_queue_0_over_errors", 1593 1594 "rx_queue_1_current", 1595 "tx_queue_1_current", 1596 "rx_queue_1_dirty", 1597 "tx_queue_1_dirty", 1598 "rx_queue_1_packets", 1599 "tx_queue_1_packets", 1600 "rx_queue_1_bytes", 1601 "tx_queue_1_bytes", 1602 "rx_queue_1_mcast_packets", 1603 "rx_queue_1_errors", 1604 "rx_queue_1_crc_errors", 1605 "rx_queue_1_frame_errors", 1606 "rx_queue_1_length_errors", 1607 "rx_queue_1_missed_errors", 1608 "rx_queue_1_over_errors", 1609 }; 1610 1611 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1612 { 1613 struct ravb_private *priv = netdev_priv(netdev); 1614 const struct ravb_hw_info *info = priv->info; 1615 1616 switch (sset) { 1617 case ETH_SS_STATS: 1618 return info->stats_len; 1619 default: 1620 return -EOPNOTSUPP; 1621 } 1622 } 1623 1624 static void ravb_get_ethtool_stats(struct net_device *ndev, 1625 struct ethtool_stats *estats, u64 *data) 1626 { 1627 struct ravb_private *priv = netdev_priv(ndev); 1628 const struct ravb_hw_info *info = priv->info; 1629 int num_rx_q; 1630 int i = 0; 1631 int q; 1632 1633 num_rx_q = info->nc_queues ? NUM_RX_QUEUE : 1; 1634 /* Device-specific stats */ 1635 for (q = RAVB_BE; q < num_rx_q; q++) { 1636 struct net_device_stats *stats = &priv->stats[q]; 1637 1638 data[i++] = priv->cur_rx[q]; 1639 data[i++] = priv->cur_tx[q]; 1640 data[i++] = priv->dirty_rx[q]; 1641 data[i++] = priv->dirty_tx[q]; 1642 data[i++] = stats->rx_packets; 1643 data[i++] = stats->tx_packets; 1644 data[i++] = stats->rx_bytes; 1645 data[i++] = stats->tx_bytes; 1646 data[i++] = stats->multicast; 1647 data[i++] = stats->rx_errors; 1648 data[i++] = stats->rx_crc_errors; 1649 data[i++] = stats->rx_frame_errors; 1650 data[i++] = stats->rx_length_errors; 1651 data[i++] = stats->rx_missed_errors; 1652 data[i++] = stats->rx_over_errors; 1653 } 1654 } 1655 1656 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1657 { 1658 struct ravb_private *priv = netdev_priv(ndev); 1659 const struct ravb_hw_info *info = priv->info; 1660 1661 switch (stringset) { 1662 case ETH_SS_STATS: 1663 memcpy(data, info->gstrings_stats, info->gstrings_size); 1664 break; 1665 } 1666 } 1667 1668 static void ravb_get_ringparam(struct net_device *ndev, 1669 struct ethtool_ringparam *ring, 1670 struct kernel_ethtool_ringparam *kernel_ring, 1671 struct netlink_ext_ack *extack) 1672 { 1673 struct ravb_private *priv = netdev_priv(ndev); 1674 1675 ring->rx_max_pending = BE_RX_RING_MAX; 1676 ring->tx_max_pending = BE_TX_RING_MAX; 1677 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1678 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1679 } 1680 1681 static int ravb_set_ringparam(struct net_device *ndev, 1682 struct ethtool_ringparam *ring, 1683 struct kernel_ethtool_ringparam *kernel_ring, 1684 struct netlink_ext_ack *extack) 1685 { 1686 struct ravb_private *priv = netdev_priv(ndev); 1687 const struct ravb_hw_info *info = priv->info; 1688 int error; 1689 1690 if (ring->tx_pending > BE_TX_RING_MAX || 1691 ring->rx_pending > BE_RX_RING_MAX || 1692 ring->tx_pending < BE_TX_RING_MIN || 1693 ring->rx_pending < BE_RX_RING_MIN) 1694 return -EINVAL; 1695 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1696 return -EINVAL; 1697 1698 if (netif_running(ndev)) { 1699 netif_device_detach(ndev); 1700 /* Stop PTP Clock driver */ 1701 if (info->gptp) 1702 ravb_ptp_stop(ndev); 1703 /* Wait for DMA stopping */ 1704 error = ravb_stop_dma(ndev); 1705 if (error) { 1706 netdev_err(ndev, 1707 "cannot set ringparam! Any AVB processes are still running?\n"); 1708 return error; 1709 } 1710 synchronize_irq(ndev->irq); 1711 1712 /* Free all the skb's in the RX queue and the DMA buffers. */ 1713 ravb_ring_free(ndev, RAVB_BE); 1714 if (info->nc_queues) 1715 ravb_ring_free(ndev, RAVB_NC); 1716 } 1717 1718 /* Set new parameters */ 1719 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1720 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1721 1722 if (netif_running(ndev)) { 1723 error = ravb_dmac_init(ndev); 1724 if (error) { 1725 netdev_err(ndev, 1726 "%s: ravb_dmac_init() failed, error %d\n", 1727 __func__, error); 1728 return error; 1729 } 1730 1731 ravb_emac_init(ndev); 1732 1733 /* Initialise PTP Clock driver */ 1734 if (info->gptp) 1735 ravb_ptp_init(ndev, priv->pdev); 1736 1737 netif_device_attach(ndev); 1738 } 1739 1740 return 0; 1741 } 1742 1743 static int ravb_get_ts_info(struct net_device *ndev, 1744 struct kernel_ethtool_ts_info *info) 1745 { 1746 struct ravb_private *priv = netdev_priv(ndev); 1747 const struct ravb_hw_info *hw_info = priv->info; 1748 1749 if (hw_info->gptp || hw_info->ccc_gac) { 1750 info->so_timestamping = 1751 SOF_TIMESTAMPING_TX_SOFTWARE | 1752 SOF_TIMESTAMPING_TX_HARDWARE | 1753 SOF_TIMESTAMPING_RX_HARDWARE | 1754 SOF_TIMESTAMPING_RAW_HARDWARE; 1755 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1756 info->rx_filters = 1757 (1 << HWTSTAMP_FILTER_NONE) | 1758 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1759 (1 << HWTSTAMP_FILTER_ALL); 1760 info->phc_index = ptp_clock_index(priv->ptp.clock); 1761 } 1762 1763 return 0; 1764 } 1765 1766 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1767 { 1768 struct ravb_private *priv = netdev_priv(ndev); 1769 1770 wol->supported = WAKE_MAGIC; 1771 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1772 } 1773 1774 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1775 { 1776 struct ravb_private *priv = netdev_priv(ndev); 1777 const struct ravb_hw_info *info = priv->info; 1778 1779 if (!info->magic_pkt || (wol->wolopts & ~WAKE_MAGIC)) 1780 return -EOPNOTSUPP; 1781 1782 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1783 1784 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1785 1786 return 0; 1787 } 1788 1789 static const struct ethtool_ops ravb_ethtool_ops = { 1790 .nway_reset = phy_ethtool_nway_reset, 1791 .get_msglevel = ravb_get_msglevel, 1792 .set_msglevel = ravb_set_msglevel, 1793 .get_link = ethtool_op_get_link, 1794 .get_strings = ravb_get_strings, 1795 .get_ethtool_stats = ravb_get_ethtool_stats, 1796 .get_sset_count = ravb_get_sset_count, 1797 .get_ringparam = ravb_get_ringparam, 1798 .set_ringparam = ravb_set_ringparam, 1799 .get_ts_info = ravb_get_ts_info, 1800 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1801 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1802 .get_wol = ravb_get_wol, 1803 .set_wol = ravb_set_wol, 1804 }; 1805 1806 static int ravb_set_config_mode(struct net_device *ndev) 1807 { 1808 struct ravb_private *priv = netdev_priv(ndev); 1809 const struct ravb_hw_info *info = priv->info; 1810 int error; 1811 1812 if (info->gptp) { 1813 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 1814 if (error) 1815 return error; 1816 /* Set CSEL value */ 1817 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 1818 } else if (info->ccc_gac) { 1819 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG | CCC_GAC | CCC_CSEL_HPB); 1820 } else { 1821 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 1822 } 1823 1824 return error; 1825 } 1826 1827 static void ravb_set_gti(struct net_device *ndev) 1828 { 1829 struct ravb_private *priv = netdev_priv(ndev); 1830 const struct ravb_hw_info *info = priv->info; 1831 1832 if (!(info->gptp || info->ccc_gac)) 1833 return; 1834 1835 ravb_write(ndev, priv->gti_tiv, GTI); 1836 1837 /* Request GTI loading */ 1838 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 1839 } 1840 1841 static int ravb_compute_gti(struct net_device *ndev) 1842 { 1843 struct ravb_private *priv = netdev_priv(ndev); 1844 const struct ravb_hw_info *info = priv->info; 1845 struct device *dev = ndev->dev.parent; 1846 unsigned long rate; 1847 u64 inc; 1848 1849 if (!(info->gptp || info->ccc_gac)) 1850 return 0; 1851 1852 if (info->gptp_ref_clk) 1853 rate = clk_get_rate(priv->gptp_clk); 1854 else 1855 rate = clk_get_rate(priv->clk); 1856 if (!rate) 1857 return -EINVAL; 1858 1859 inc = div64_ul(1000000000ULL << 20, rate); 1860 1861 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 1862 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 1863 inc, GTI_TIV_MIN, GTI_TIV_MAX); 1864 return -EINVAL; 1865 } 1866 priv->gti_tiv = inc; 1867 1868 return 0; 1869 } 1870 1871 /* Set tx and rx clock internal delay modes */ 1872 static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev) 1873 { 1874 struct ravb_private *priv = netdev_priv(ndev); 1875 bool explicit_delay = false; 1876 u32 delay; 1877 1878 if (!priv->info->internal_delay) 1879 return; 1880 1881 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) { 1882 /* Valid values are 0 and 1800, according to DT bindings */ 1883 priv->rxcidm = !!delay; 1884 explicit_delay = true; 1885 } 1886 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) { 1887 /* Valid values are 0 and 2000, according to DT bindings */ 1888 priv->txcidm = !!delay; 1889 explicit_delay = true; 1890 } 1891 1892 if (explicit_delay) 1893 return; 1894 1895 /* Fall back to legacy rgmii-*id behavior */ 1896 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1897 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) { 1898 priv->rxcidm = 1; 1899 priv->rgmii_override = 1; 1900 } 1901 1902 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1903 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) { 1904 priv->txcidm = 1; 1905 priv->rgmii_override = 1; 1906 } 1907 } 1908 1909 static void ravb_set_delay_mode(struct net_device *ndev) 1910 { 1911 struct ravb_private *priv = netdev_priv(ndev); 1912 u32 set = 0; 1913 1914 if (!priv->info->internal_delay) 1915 return; 1916 1917 if (priv->rxcidm) 1918 set |= APSR_RDM; 1919 if (priv->txcidm) 1920 set |= APSR_TDM; 1921 ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set); 1922 } 1923 1924 /* Network device open function for Ethernet AVB */ 1925 static int ravb_open(struct net_device *ndev) 1926 { 1927 struct ravb_private *priv = netdev_priv(ndev); 1928 const struct ravb_hw_info *info = priv->info; 1929 struct device *dev = &priv->pdev->dev; 1930 int error; 1931 1932 napi_enable(&priv->napi[RAVB_BE]); 1933 if (info->nc_queues) 1934 napi_enable(&priv->napi[RAVB_NC]); 1935 1936 error = pm_runtime_resume_and_get(dev); 1937 if (error < 0) 1938 goto out_napi_off; 1939 1940 /* Set AVB config mode */ 1941 error = ravb_set_config_mode(ndev); 1942 if (error) 1943 goto out_rpm_put; 1944 1945 ravb_set_delay_mode(ndev); 1946 ravb_write(ndev, priv->desc_bat_dma, DBAT); 1947 1948 /* Device init */ 1949 error = ravb_dmac_init(ndev); 1950 if (error) 1951 goto out_set_reset; 1952 1953 ravb_emac_init(ndev); 1954 1955 ravb_set_gti(ndev); 1956 1957 /* Initialise PTP Clock driver */ 1958 if (info->gptp || info->ccc_gac) 1959 ravb_ptp_init(ndev, priv->pdev); 1960 1961 /* PHY control start */ 1962 error = ravb_phy_start(ndev); 1963 if (error) 1964 goto out_ptp_stop; 1965 1966 netif_tx_start_all_queues(ndev); 1967 1968 return 0; 1969 1970 out_ptp_stop: 1971 /* Stop PTP Clock driver */ 1972 if (info->gptp || info->ccc_gac) 1973 ravb_ptp_stop(ndev); 1974 ravb_stop_dma(ndev); 1975 out_set_reset: 1976 ravb_set_opmode(ndev, CCC_OPC_RESET); 1977 out_rpm_put: 1978 pm_runtime_mark_last_busy(dev); 1979 pm_runtime_put_autosuspend(dev); 1980 out_napi_off: 1981 if (info->nc_queues) 1982 napi_disable(&priv->napi[RAVB_NC]); 1983 napi_disable(&priv->napi[RAVB_BE]); 1984 return error; 1985 } 1986 1987 /* Timeout function for Ethernet AVB */ 1988 static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1989 { 1990 struct ravb_private *priv = netdev_priv(ndev); 1991 1992 netif_err(priv, tx_err, ndev, 1993 "transmit timed out, status %08x, resetting...\n", 1994 ravb_read(ndev, ISS)); 1995 1996 /* tx_errors count up */ 1997 ndev->stats.tx_errors++; 1998 1999 schedule_work(&priv->work); 2000 } 2001 2002 static void ravb_tx_timeout_work(struct work_struct *work) 2003 { 2004 struct ravb_private *priv = container_of(work, struct ravb_private, 2005 work); 2006 const struct ravb_hw_info *info = priv->info; 2007 struct net_device *ndev = priv->ndev; 2008 int error; 2009 2010 if (!rtnl_trylock()) { 2011 usleep_range(1000, 2000); 2012 schedule_work(&priv->work); 2013 return; 2014 } 2015 2016 netif_tx_stop_all_queues(ndev); 2017 2018 /* Stop PTP Clock driver */ 2019 if (info->gptp) 2020 ravb_ptp_stop(ndev); 2021 2022 /* Wait for DMA stopping */ 2023 if (ravb_stop_dma(ndev)) { 2024 /* If ravb_stop_dma() fails, the hardware is still operating 2025 * for TX and/or RX. So, this should not call the following 2026 * functions because ravb_dmac_init() is possible to fail too. 2027 * Also, this should not retry ravb_stop_dma() again and again 2028 * here because it's possible to wait forever. So, this just 2029 * re-enables the TX and RX and skip the following 2030 * re-initialization procedure. 2031 */ 2032 ravb_rcv_snd_enable(ndev); 2033 goto out; 2034 } 2035 2036 ravb_ring_free(ndev, RAVB_BE); 2037 if (info->nc_queues) 2038 ravb_ring_free(ndev, RAVB_NC); 2039 2040 /* Device init */ 2041 error = ravb_dmac_init(ndev); 2042 if (error) { 2043 /* If ravb_dmac_init() fails, descriptors are freed. So, this 2044 * should return here to avoid re-enabling the TX and RX in 2045 * ravb_emac_init(). 2046 */ 2047 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n", 2048 __func__, error); 2049 goto out_unlock; 2050 } 2051 ravb_emac_init(ndev); 2052 2053 out: 2054 /* Initialise PTP Clock driver */ 2055 if (info->gptp) 2056 ravb_ptp_init(ndev, priv->pdev); 2057 2058 netif_tx_start_all_queues(ndev); 2059 2060 out_unlock: 2061 rtnl_unlock(); 2062 } 2063 2064 static bool ravb_can_tx_csum_gbeth(struct sk_buff *skb) 2065 { 2066 u16 net_protocol = ntohs(skb->protocol); 2067 u8 inner_protocol; 2068 2069 /* GbEth IP can calculate the checksum if: 2070 * - there are zero or one VLAN headers with TPID=0x8100 2071 * - the network protocol is IPv4 or IPv6 2072 * - the transport protocol is TCP, UDP or ICMP 2073 * - the packet is not fragmented 2074 */ 2075 2076 if (net_protocol == ETH_P_8021Q) { 2077 struct vlan_hdr vhdr, *vh; 2078 2079 vh = skb_header_pointer(skb, ETH_HLEN, sizeof(vhdr), &vhdr); 2080 if (!vh) 2081 return false; 2082 2083 net_protocol = ntohs(vh->h_vlan_encapsulated_proto); 2084 } 2085 2086 switch (net_protocol) { 2087 case ETH_P_IP: 2088 inner_protocol = ip_hdr(skb)->protocol; 2089 break; 2090 case ETH_P_IPV6: 2091 inner_protocol = ipv6_hdr(skb)->nexthdr; 2092 break; 2093 default: 2094 return false; 2095 } 2096 2097 switch (inner_protocol) { 2098 case IPPROTO_TCP: 2099 case IPPROTO_UDP: 2100 return true; 2101 default: 2102 return false; 2103 } 2104 } 2105 2106 /* Packet transmit function for Ethernet AVB */ 2107 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 2108 { 2109 struct ravb_private *priv = netdev_priv(ndev); 2110 const struct ravb_hw_info *info = priv->info; 2111 unsigned int num_tx_desc = priv->num_tx_desc; 2112 u16 q = skb_get_queue_mapping(skb); 2113 struct ravb_tstamp_skb *ts_skb; 2114 struct ravb_tx_desc *desc; 2115 unsigned long flags; 2116 dma_addr_t dma_addr; 2117 void *buffer; 2118 u32 entry; 2119 u32 len; 2120 2121 if (skb->ip_summed == CHECKSUM_PARTIAL && !ravb_can_tx_csum_gbeth(skb)) 2122 skb_checksum_help(skb); 2123 2124 spin_lock_irqsave(&priv->lock, flags); 2125 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 2126 num_tx_desc) { 2127 netif_err(priv, tx_queued, ndev, 2128 "still transmitting with the full ring!\n"); 2129 netif_stop_subqueue(ndev, q); 2130 spin_unlock_irqrestore(&priv->lock, flags); 2131 return NETDEV_TX_BUSY; 2132 } 2133 2134 if (skb_put_padto(skb, ETH_ZLEN)) 2135 goto exit; 2136 2137 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc); 2138 priv->tx_skb[q][entry / num_tx_desc] = skb; 2139 2140 if (num_tx_desc > 1) { 2141 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 2142 entry / num_tx_desc * DPTR_ALIGN; 2143 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 2144 2145 /* Zero length DMA descriptors are problematic as they seem 2146 * to terminate DMA transfers. Avoid them by simply using a 2147 * length of DPTR_ALIGN (4) when skb data is aligned to 2148 * DPTR_ALIGN. 2149 * 2150 * As skb is guaranteed to have at least ETH_ZLEN (60) 2151 * bytes of data by the call to skb_put_padto() above this 2152 * is safe with respect to both the length of the first DMA 2153 * descriptor (len) overflowing the available data and the 2154 * length of the second DMA descriptor (skb->len - len) 2155 * being negative. 2156 */ 2157 if (len == 0) 2158 len = DPTR_ALIGN; 2159 2160 memcpy(buffer, skb->data, len); 2161 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 2162 DMA_TO_DEVICE); 2163 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2164 goto drop; 2165 2166 desc = &priv->tx_ring[q][entry]; 2167 desc->ds_tagl = cpu_to_le16(len); 2168 desc->dptr = cpu_to_le32(dma_addr); 2169 2170 buffer = skb->data + len; 2171 len = skb->len - len; 2172 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 2173 DMA_TO_DEVICE); 2174 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2175 goto unmap; 2176 2177 desc++; 2178 } else { 2179 desc = &priv->tx_ring[q][entry]; 2180 len = skb->len; 2181 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, 2182 DMA_TO_DEVICE); 2183 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2184 goto drop; 2185 } 2186 desc->ds_tagl = cpu_to_le16(len); 2187 desc->dptr = cpu_to_le32(dma_addr); 2188 2189 /* TX timestamp required */ 2190 if (info->gptp || info->ccc_gac) { 2191 if (q == RAVB_NC) { 2192 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC); 2193 if (!ts_skb) { 2194 if (num_tx_desc > 1) { 2195 desc--; 2196 dma_unmap_single(ndev->dev.parent, dma_addr, 2197 len, DMA_TO_DEVICE); 2198 } 2199 goto unmap; 2200 } 2201 ts_skb->skb = skb_get(skb); 2202 ts_skb->tag = priv->ts_skb_tag++; 2203 priv->ts_skb_tag &= 0x3ff; 2204 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 2205 2206 /* TAG and timestamp required flag */ 2207 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2208 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 2209 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12); 2210 } 2211 2212 skb_tx_timestamp(skb); 2213 } 2214 2215 if (num_tx_desc > 1) { 2216 desc->die_dt = DT_FEND; 2217 desc--; 2218 /* When using multi-descriptors, DT_FEND needs to get written 2219 * before DT_FSTART, but the compiler may reorder the memory 2220 * writes in an attempt to optimize the code. 2221 * Use a dma_wmb() barrier to make sure DT_FEND and DT_FSTART 2222 * are written exactly in the order shown in the code. 2223 * This is particularly important for cases where the DMA engine 2224 * is already running when we are running this code. If the DMA 2225 * sees DT_FSTART without the corresponding DT_FEND it will enter 2226 * an error condition. 2227 */ 2228 dma_wmb(); 2229 desc->die_dt = DT_FSTART; 2230 } else { 2231 /* Descriptor type must be set after all the above writes */ 2232 dma_wmb(); 2233 desc->die_dt = DT_FSINGLE; 2234 } 2235 2236 /* Before ringing the doorbell we need to make sure that the latest 2237 * writes have been committed to memory, otherwise it could delay 2238 * things until the doorbell is rang again. 2239 * This is in replacement of the read operation mentioned in the HW 2240 * manuals. 2241 */ 2242 dma_wmb(); 2243 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 2244 2245 priv->cur_tx[q] += num_tx_desc; 2246 if (priv->cur_tx[q] - priv->dirty_tx[q] > 2247 (priv->num_tx_ring[q] - 1) * num_tx_desc && 2248 !ravb_tx_free(ndev, q, true)) 2249 netif_stop_subqueue(ndev, q); 2250 2251 exit: 2252 spin_unlock_irqrestore(&priv->lock, flags); 2253 return NETDEV_TX_OK; 2254 2255 unmap: 2256 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 2257 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 2258 drop: 2259 dev_kfree_skb_any(skb); 2260 priv->tx_skb[q][entry / num_tx_desc] = NULL; 2261 goto exit; 2262 } 2263 2264 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 2265 struct net_device *sb_dev) 2266 { 2267 /* If skb needs TX timestamp, it is handled in network control queue */ 2268 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 2269 RAVB_BE; 2270 2271 } 2272 2273 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 2274 { 2275 struct ravb_private *priv = netdev_priv(ndev); 2276 const struct ravb_hw_info *info = priv->info; 2277 struct net_device_stats *nstats, *stats0, *stats1; 2278 struct device *dev = &priv->pdev->dev; 2279 2280 nstats = &ndev->stats; 2281 2282 pm_runtime_get_noresume(dev); 2283 2284 if (!pm_runtime_active(dev)) 2285 goto out_rpm_put; 2286 2287 stats0 = &priv->stats[RAVB_BE]; 2288 2289 if (info->tx_counters) { 2290 nstats->tx_dropped += ravb_read(ndev, TROCR); 2291 ravb_write(ndev, 0, TROCR); /* (write clear) */ 2292 } 2293 2294 if (info->carrier_counters) { 2295 nstats->collisions += ravb_read(ndev, CXR41); 2296 ravb_write(ndev, 0, CXR41); /* (write clear) */ 2297 nstats->tx_carrier_errors += ravb_read(ndev, CXR42); 2298 ravb_write(ndev, 0, CXR42); /* (write clear) */ 2299 } 2300 2301 nstats->rx_packets = stats0->rx_packets; 2302 nstats->tx_packets = stats0->tx_packets; 2303 nstats->rx_bytes = stats0->rx_bytes; 2304 nstats->tx_bytes = stats0->tx_bytes; 2305 nstats->multicast = stats0->multicast; 2306 nstats->rx_errors = stats0->rx_errors; 2307 nstats->rx_crc_errors = stats0->rx_crc_errors; 2308 nstats->rx_frame_errors = stats0->rx_frame_errors; 2309 nstats->rx_length_errors = stats0->rx_length_errors; 2310 nstats->rx_missed_errors = stats0->rx_missed_errors; 2311 nstats->rx_over_errors = stats0->rx_over_errors; 2312 if (info->nc_queues) { 2313 stats1 = &priv->stats[RAVB_NC]; 2314 2315 nstats->rx_packets += stats1->rx_packets; 2316 nstats->tx_packets += stats1->tx_packets; 2317 nstats->rx_bytes += stats1->rx_bytes; 2318 nstats->tx_bytes += stats1->tx_bytes; 2319 nstats->multicast += stats1->multicast; 2320 nstats->rx_errors += stats1->rx_errors; 2321 nstats->rx_crc_errors += stats1->rx_crc_errors; 2322 nstats->rx_frame_errors += stats1->rx_frame_errors; 2323 nstats->rx_length_errors += stats1->rx_length_errors; 2324 nstats->rx_missed_errors += stats1->rx_missed_errors; 2325 nstats->rx_over_errors += stats1->rx_over_errors; 2326 } 2327 2328 out_rpm_put: 2329 pm_runtime_put_noidle(dev); 2330 return nstats; 2331 } 2332 2333 /* Update promiscuous bit */ 2334 static void ravb_set_rx_mode(struct net_device *ndev) 2335 { 2336 struct ravb_private *priv = netdev_priv(ndev); 2337 unsigned long flags; 2338 2339 spin_lock_irqsave(&priv->lock, flags); 2340 ravb_modify(ndev, ECMR, ECMR_PRM, 2341 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 2342 spin_unlock_irqrestore(&priv->lock, flags); 2343 } 2344 2345 /* Device close function for Ethernet AVB */ 2346 static int ravb_close(struct net_device *ndev) 2347 { 2348 struct device_node *np = ndev->dev.parent->of_node; 2349 struct ravb_private *priv = netdev_priv(ndev); 2350 const struct ravb_hw_info *info = priv->info; 2351 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 2352 struct device *dev = &priv->pdev->dev; 2353 int error; 2354 2355 netif_tx_stop_all_queues(ndev); 2356 2357 /* Disable interrupts by clearing the interrupt masks. */ 2358 ravb_write(ndev, 0, RIC0); 2359 ravb_write(ndev, 0, RIC2); 2360 ravb_write(ndev, 0, TIC); 2361 2362 /* PHY disconnect */ 2363 if (ndev->phydev) { 2364 phy_stop(ndev->phydev); 2365 phy_disconnect(ndev->phydev); 2366 if (of_phy_is_fixed_link(np)) 2367 of_phy_deregister_fixed_link(np); 2368 } 2369 2370 /* Stop PTP Clock driver */ 2371 if (info->gptp || info->ccc_gac) 2372 ravb_ptp_stop(ndev); 2373 2374 /* Set the config mode to stop the AVB-DMAC's processes */ 2375 if (ravb_stop_dma(ndev) < 0) 2376 netdev_err(ndev, 2377 "device will be stopped after h/w processes are done.\n"); 2378 2379 /* Clear the timestamp list */ 2380 if (info->gptp || info->ccc_gac) { 2381 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 2382 list_del(&ts_skb->list); 2383 kfree_skb(ts_skb->skb); 2384 kfree(ts_skb); 2385 } 2386 } 2387 2388 cancel_work_sync(&priv->work); 2389 2390 if (info->nc_queues) 2391 napi_disable(&priv->napi[RAVB_NC]); 2392 napi_disable(&priv->napi[RAVB_BE]); 2393 2394 /* Free all the skb's in the RX queue and the DMA buffers. */ 2395 ravb_ring_free(ndev, RAVB_BE); 2396 if (info->nc_queues) 2397 ravb_ring_free(ndev, RAVB_NC); 2398 2399 /* Update statistics. */ 2400 ravb_get_stats(ndev); 2401 2402 /* Set reset mode. */ 2403 error = ravb_set_opmode(ndev, CCC_OPC_RESET); 2404 if (error) 2405 return error; 2406 2407 pm_runtime_mark_last_busy(dev); 2408 pm_runtime_put_autosuspend(dev); 2409 2410 return 0; 2411 } 2412 2413 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req) 2414 { 2415 struct ravb_private *priv = netdev_priv(ndev); 2416 struct hwtstamp_config config; 2417 2418 config.flags = 0; 2419 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON : 2420 HWTSTAMP_TX_OFF; 2421 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) { 2422 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT: 2423 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 2424 break; 2425 case RAVB_RXTSTAMP_TYPE_ALL: 2426 config.rx_filter = HWTSTAMP_FILTER_ALL; 2427 break; 2428 default: 2429 config.rx_filter = HWTSTAMP_FILTER_NONE; 2430 } 2431 2432 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2433 -EFAULT : 0; 2434 } 2435 2436 /* Control hardware time stamping */ 2437 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req) 2438 { 2439 struct ravb_private *priv = netdev_priv(ndev); 2440 struct hwtstamp_config config; 2441 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED; 2442 u32 tstamp_tx_ctrl; 2443 2444 if (copy_from_user(&config, req->ifr_data, sizeof(config))) 2445 return -EFAULT; 2446 2447 switch (config.tx_type) { 2448 case HWTSTAMP_TX_OFF: 2449 tstamp_tx_ctrl = 0; 2450 break; 2451 case HWTSTAMP_TX_ON: 2452 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED; 2453 break; 2454 default: 2455 return -ERANGE; 2456 } 2457 2458 switch (config.rx_filter) { 2459 case HWTSTAMP_FILTER_NONE: 2460 tstamp_rx_ctrl = 0; 2461 break; 2462 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2463 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT; 2464 break; 2465 default: 2466 config.rx_filter = HWTSTAMP_FILTER_ALL; 2467 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL; 2468 } 2469 2470 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 2471 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 2472 2473 return copy_to_user(req->ifr_data, &config, sizeof(config)) ? 2474 -EFAULT : 0; 2475 } 2476 2477 /* ioctl to device function */ 2478 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) 2479 { 2480 struct phy_device *phydev = ndev->phydev; 2481 2482 if (!netif_running(ndev)) 2483 return -EINVAL; 2484 2485 if (!phydev) 2486 return -ENODEV; 2487 2488 switch (cmd) { 2489 case SIOCGHWTSTAMP: 2490 return ravb_hwtstamp_get(ndev, req); 2491 case SIOCSHWTSTAMP: 2492 return ravb_hwtstamp_set(ndev, req); 2493 } 2494 2495 return phy_mii_ioctl(phydev, req, cmd); 2496 } 2497 2498 static int ravb_change_mtu(struct net_device *ndev, int new_mtu) 2499 { 2500 struct ravb_private *priv = netdev_priv(ndev); 2501 2502 WRITE_ONCE(ndev->mtu, new_mtu); 2503 2504 if (netif_running(ndev)) { 2505 synchronize_irq(priv->emac_irq); 2506 ravb_emac_init(ndev); 2507 } 2508 2509 netdev_update_features(ndev); 2510 2511 return 0; 2512 } 2513 2514 static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 2515 { 2516 struct ravb_private *priv = netdev_priv(ndev); 2517 unsigned long flags; 2518 2519 spin_lock_irqsave(&priv->lock, flags); 2520 2521 /* Disable TX and RX */ 2522 ravb_rcv_snd_disable(ndev); 2523 2524 /* Modify RX Checksum setting */ 2525 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 2526 2527 /* Enable TX and RX */ 2528 ravb_rcv_snd_enable(ndev); 2529 2530 spin_unlock_irqrestore(&priv->lock, flags); 2531 } 2532 2533 static int ravb_endisable_csum_gbeth(struct net_device *ndev, enum ravb_reg reg, 2534 u32 val, u32 mask) 2535 { 2536 u32 csr0 = CSR0_TPE | CSR0_RPE; 2537 int ret; 2538 2539 ravb_write(ndev, csr0 & ~mask, CSR0); 2540 ret = ravb_wait(ndev, CSR0, mask, 0); 2541 if (!ret) 2542 ravb_write(ndev, val, reg); 2543 2544 ravb_write(ndev, csr0, CSR0); 2545 2546 return ret; 2547 } 2548 2549 static int ravb_set_features_gbeth(struct net_device *ndev, 2550 netdev_features_t features) 2551 { 2552 netdev_features_t changed = ndev->features ^ features; 2553 struct ravb_private *priv = netdev_priv(ndev); 2554 unsigned long flags; 2555 int ret = 0; 2556 u32 val; 2557 2558 spin_lock_irqsave(&priv->lock, flags); 2559 if (changed & NETIF_F_RXCSUM) { 2560 if (features & NETIF_F_RXCSUM) 2561 val = CSR2_CSUM_ENABLE; 2562 else 2563 val = 0; 2564 2565 ret = ravb_endisable_csum_gbeth(ndev, CSR2, val, CSR0_RPE); 2566 if (ret) 2567 goto done; 2568 } 2569 2570 if (changed & NETIF_F_HW_CSUM) { 2571 if (features & NETIF_F_HW_CSUM) 2572 val = CSR1_CSUM_ENABLE; 2573 else 2574 val = 0; 2575 2576 ret = ravb_endisable_csum_gbeth(ndev, CSR1, val, CSR0_TPE); 2577 if (ret) 2578 goto done; 2579 } 2580 2581 done: 2582 spin_unlock_irqrestore(&priv->lock, flags); 2583 2584 return ret; 2585 } 2586 2587 static int ravb_set_features_rcar(struct net_device *ndev, 2588 netdev_features_t features) 2589 { 2590 netdev_features_t changed = ndev->features ^ features; 2591 2592 if (changed & NETIF_F_RXCSUM) 2593 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 2594 2595 return 0; 2596 } 2597 2598 static int ravb_set_features(struct net_device *ndev, 2599 netdev_features_t features) 2600 { 2601 struct ravb_private *priv = netdev_priv(ndev); 2602 const struct ravb_hw_info *info = priv->info; 2603 struct device *dev = &priv->pdev->dev; 2604 int ret; 2605 2606 pm_runtime_get_noresume(dev); 2607 2608 if (pm_runtime_active(dev)) 2609 ret = info->set_feature(ndev, features); 2610 else 2611 ret = 0; 2612 2613 pm_runtime_put_noidle(dev); 2614 2615 if (ret) 2616 return ret; 2617 2618 ndev->features = features; 2619 2620 return 0; 2621 } 2622 2623 static const struct net_device_ops ravb_netdev_ops = { 2624 .ndo_open = ravb_open, 2625 .ndo_stop = ravb_close, 2626 .ndo_start_xmit = ravb_start_xmit, 2627 .ndo_select_queue = ravb_select_queue, 2628 .ndo_get_stats = ravb_get_stats, 2629 .ndo_set_rx_mode = ravb_set_rx_mode, 2630 .ndo_tx_timeout = ravb_tx_timeout, 2631 .ndo_eth_ioctl = ravb_do_ioctl, 2632 .ndo_change_mtu = ravb_change_mtu, 2633 .ndo_validate_addr = eth_validate_addr, 2634 .ndo_set_mac_address = eth_mac_addr, 2635 .ndo_set_features = ravb_set_features, 2636 }; 2637 2638 /* MDIO bus init function */ 2639 static int ravb_mdio_init(struct ravb_private *priv) 2640 { 2641 struct platform_device *pdev = priv->pdev; 2642 struct device *dev = &pdev->dev; 2643 struct device_node *mdio_node; 2644 struct phy_device *phydev; 2645 struct device_node *pn; 2646 int error; 2647 2648 /* Bitbang init */ 2649 priv->mdiobb.ops = &bb_ops; 2650 2651 /* MII controller setting */ 2652 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 2653 if (!priv->mii_bus) 2654 return -ENOMEM; 2655 2656 /* Hook up MII support for ethtool */ 2657 priv->mii_bus->name = "ravb_mii"; 2658 priv->mii_bus->parent = dev; 2659 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2660 pdev->name, pdev->id); 2661 2662 /* Register MDIO bus */ 2663 mdio_node = of_get_child_by_name(dev->of_node, "mdio"); 2664 if (!mdio_node) { 2665 /* backwards compatibility for DT lacking mdio subnode */ 2666 mdio_node = of_node_get(dev->of_node); 2667 } 2668 error = of_mdiobus_register(priv->mii_bus, mdio_node); 2669 of_node_put(mdio_node); 2670 if (error) 2671 goto out_free_bus; 2672 2673 pn = of_parse_phandle(dev->of_node, "phy-handle", 0); 2674 phydev = of_phy_find_device(pn); 2675 if (phydev) { 2676 phydev->mac_managed_pm = true; 2677 put_device(&phydev->mdio.dev); 2678 } 2679 of_node_put(pn); 2680 2681 return 0; 2682 2683 out_free_bus: 2684 free_mdio_bitbang(priv->mii_bus); 2685 return error; 2686 } 2687 2688 /* MDIO bus release function */ 2689 static int ravb_mdio_release(struct ravb_private *priv) 2690 { 2691 /* Unregister mdio bus */ 2692 mdiobus_unregister(priv->mii_bus); 2693 2694 /* Free bitbang info */ 2695 free_mdio_bitbang(priv->mii_bus); 2696 2697 return 0; 2698 } 2699 2700 static const struct ravb_hw_info ravb_gen2_hw_info = { 2701 .receive = ravb_rx_rcar, 2702 .set_rate = ravb_set_rate_rcar, 2703 .set_feature = ravb_set_features_rcar, 2704 .dmac_init = ravb_dmac_init_rcar, 2705 .emac_init = ravb_emac_init_rcar, 2706 .gstrings_stats = ravb_gstrings_stats, 2707 .gstrings_size = sizeof(ravb_gstrings_stats), 2708 .net_hw_features = NETIF_F_RXCSUM, 2709 .net_features = NETIF_F_RXCSUM, 2710 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2711 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2712 .tx_max_frame_size = SZ_2K, 2713 .rx_max_frame_size = SZ_2K, 2714 .rx_buffer_size = SZ_2K + 2715 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), 2716 .rx_desc_size = sizeof(struct ravb_ex_rx_desc), 2717 .aligned_tx = 1, 2718 .gptp = 1, 2719 .nc_queues = 1, 2720 .magic_pkt = 1, 2721 }; 2722 2723 static const struct ravb_hw_info ravb_gen3_hw_info = { 2724 .receive = ravb_rx_rcar, 2725 .set_rate = ravb_set_rate_rcar, 2726 .set_feature = ravb_set_features_rcar, 2727 .dmac_init = ravb_dmac_init_rcar, 2728 .emac_init = ravb_emac_init_rcar, 2729 .gstrings_stats = ravb_gstrings_stats, 2730 .gstrings_size = sizeof(ravb_gstrings_stats), 2731 .net_hw_features = NETIF_F_RXCSUM, 2732 .net_features = NETIF_F_RXCSUM, 2733 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2734 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2735 .tx_max_frame_size = SZ_2K, 2736 .rx_max_frame_size = SZ_2K, 2737 .rx_buffer_size = SZ_2K + 2738 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), 2739 .rx_desc_size = sizeof(struct ravb_ex_rx_desc), 2740 .internal_delay = 1, 2741 .tx_counters = 1, 2742 .multi_irqs = 1, 2743 .irq_en_dis = 1, 2744 .ccc_gac = 1, 2745 .nc_queues = 1, 2746 .magic_pkt = 1, 2747 }; 2748 2749 static const struct ravb_hw_info ravb_gen4_hw_info = { 2750 .receive = ravb_rx_rcar, 2751 .set_rate = ravb_set_rate_rcar, 2752 .set_feature = ravb_set_features_rcar, 2753 .dmac_init = ravb_dmac_init_rcar, 2754 .emac_init = ravb_emac_init_rcar_gen4, 2755 .gstrings_stats = ravb_gstrings_stats, 2756 .gstrings_size = sizeof(ravb_gstrings_stats), 2757 .net_hw_features = NETIF_F_RXCSUM, 2758 .net_features = NETIF_F_RXCSUM, 2759 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2760 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2761 .tx_max_frame_size = SZ_2K, 2762 .rx_max_frame_size = SZ_2K, 2763 .rx_buffer_size = SZ_2K + 2764 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), 2765 .rx_desc_size = sizeof(struct ravb_ex_rx_desc), 2766 .internal_delay = 1, 2767 .tx_counters = 1, 2768 .multi_irqs = 1, 2769 .irq_en_dis = 1, 2770 .ccc_gac = 1, 2771 .nc_queues = 1, 2772 .magic_pkt = 1, 2773 }; 2774 2775 static const struct ravb_hw_info ravb_rzv2m_hw_info = { 2776 .receive = ravb_rx_rcar, 2777 .set_rate = ravb_set_rate_rcar, 2778 .set_feature = ravb_set_features_rcar, 2779 .dmac_init = ravb_dmac_init_rcar, 2780 .emac_init = ravb_emac_init_rcar, 2781 .gstrings_stats = ravb_gstrings_stats, 2782 .gstrings_size = sizeof(ravb_gstrings_stats), 2783 .net_hw_features = NETIF_F_RXCSUM, 2784 .net_features = NETIF_F_RXCSUM, 2785 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2786 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2787 .tx_max_frame_size = SZ_2K, 2788 .rx_max_frame_size = SZ_2K, 2789 .rx_buffer_size = SZ_2K + 2790 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), 2791 .rx_desc_size = sizeof(struct ravb_ex_rx_desc), 2792 .multi_irqs = 1, 2793 .err_mgmt_irqs = 1, 2794 .gptp = 1, 2795 .gptp_ref_clk = 1, 2796 .nc_queues = 1, 2797 .magic_pkt = 1, 2798 }; 2799 2800 static const struct ravb_hw_info gbeth_hw_info = { 2801 .receive = ravb_rx_gbeth, 2802 .set_rate = ravb_set_rate_gbeth, 2803 .set_feature = ravb_set_features_gbeth, 2804 .dmac_init = ravb_dmac_init_gbeth, 2805 .emac_init = ravb_emac_init_gbeth, 2806 .gstrings_stats = ravb_gstrings_stats_gbeth, 2807 .gstrings_size = sizeof(ravb_gstrings_stats_gbeth), 2808 .net_hw_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM, 2809 .net_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM, 2810 .vlan_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM, 2811 .stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth), 2812 .tccr_mask = TCCR_TSRQ0, 2813 .tx_max_frame_size = 1522, 2814 .rx_max_frame_size = SZ_8K, 2815 .rx_buffer_size = SZ_2K, 2816 .rx_desc_size = sizeof(struct ravb_rx_desc), 2817 .aligned_tx = 1, 2818 .coalesce_irqs = 1, 2819 .tx_counters = 1, 2820 .carrier_counters = 1, 2821 .half_duplex = 1, 2822 }; 2823 2824 static const struct of_device_id ravb_match_table[] = { 2825 { .compatible = "renesas,etheravb-r8a7790", .data = &ravb_gen2_hw_info }, 2826 { .compatible = "renesas,etheravb-r8a7794", .data = &ravb_gen2_hw_info }, 2827 { .compatible = "renesas,etheravb-rcar-gen2", .data = &ravb_gen2_hw_info }, 2828 { .compatible = "renesas,etheravb-r8a7795", .data = &ravb_gen3_hw_info }, 2829 { .compatible = "renesas,etheravb-rcar-gen3", .data = &ravb_gen3_hw_info }, 2830 { .compatible = "renesas,etheravb-rcar-gen4", .data = &ravb_gen4_hw_info }, 2831 { .compatible = "renesas,etheravb-rzv2m", .data = &ravb_rzv2m_hw_info }, 2832 { .compatible = "renesas,rzg2l-gbeth", .data = &gbeth_hw_info }, 2833 { } 2834 }; 2835 MODULE_DEVICE_TABLE(of, ravb_match_table); 2836 2837 static int ravb_setup_irq(struct ravb_private *priv, const char *irq_name, 2838 const char *ch, int *irq, irq_handler_t handler) 2839 { 2840 struct platform_device *pdev = priv->pdev; 2841 struct net_device *ndev = priv->ndev; 2842 struct device *dev = &pdev->dev; 2843 const char *devname = dev_name(dev); 2844 unsigned long flags; 2845 int error, irq_num; 2846 2847 if (irq_name) { 2848 devname = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", devname, ch); 2849 if (!devname) 2850 return -ENOMEM; 2851 2852 irq_num = platform_get_irq_byname(pdev, irq_name); 2853 flags = 0; 2854 } else { 2855 irq_num = platform_get_irq(pdev, 0); 2856 flags = IRQF_SHARED; 2857 } 2858 if (irq_num < 0) 2859 return irq_num; 2860 2861 if (irq) 2862 *irq = irq_num; 2863 2864 error = devm_request_irq(dev, irq_num, handler, flags, devname, ndev); 2865 if (error) 2866 netdev_err(ndev, "cannot request IRQ %s\n", devname); 2867 2868 return error; 2869 } 2870 2871 static int ravb_setup_irqs(struct ravb_private *priv) 2872 { 2873 const struct ravb_hw_info *info = priv->info; 2874 struct net_device *ndev = priv->ndev; 2875 const char *irq_name, *emac_irq_name; 2876 int error; 2877 2878 if (!info->multi_irqs) 2879 return ravb_setup_irq(priv, NULL, NULL, &ndev->irq, ravb_interrupt); 2880 2881 if (info->err_mgmt_irqs) { 2882 irq_name = "dia"; 2883 emac_irq_name = "line3"; 2884 } else { 2885 irq_name = "ch22"; 2886 emac_irq_name = "ch24"; 2887 } 2888 2889 error = ravb_setup_irq(priv, irq_name, "ch22:multi", &ndev->irq, ravb_multi_interrupt); 2890 if (error) 2891 return error; 2892 2893 error = ravb_setup_irq(priv, emac_irq_name, "ch24:emac", &priv->emac_irq, 2894 ravb_emac_interrupt); 2895 if (error) 2896 return error; 2897 2898 if (info->err_mgmt_irqs) { 2899 error = ravb_setup_irq(priv, "err_a", "err_a", NULL, ravb_multi_interrupt); 2900 if (error) 2901 return error; 2902 2903 error = ravb_setup_irq(priv, "mgmt_a", "mgmt_a", NULL, ravb_multi_interrupt); 2904 if (error) 2905 return error; 2906 } 2907 2908 error = ravb_setup_irq(priv, "ch0", "ch0:rx_be", NULL, ravb_be_interrupt); 2909 if (error) 2910 return error; 2911 2912 error = ravb_setup_irq(priv, "ch1", "ch1:rx_nc", NULL, ravb_nc_interrupt); 2913 if (error) 2914 return error; 2915 2916 error = ravb_setup_irq(priv, "ch18", "ch18:tx_be", NULL, ravb_be_interrupt); 2917 if (error) 2918 return error; 2919 2920 return ravb_setup_irq(priv, "ch19", "ch19:tx_nc", NULL, ravb_nc_interrupt); 2921 } 2922 2923 static int ravb_probe(struct platform_device *pdev) 2924 { 2925 struct device_node *np = pdev->dev.of_node; 2926 const struct ravb_hw_info *info; 2927 struct reset_control *rstc; 2928 struct ravb_private *priv; 2929 struct net_device *ndev; 2930 struct resource *res; 2931 int error, q; 2932 2933 if (!np) { 2934 dev_err(&pdev->dev, 2935 "this driver is required to be instantiated from device tree\n"); 2936 return -EINVAL; 2937 } 2938 2939 rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 2940 if (IS_ERR(rstc)) 2941 return dev_err_probe(&pdev->dev, PTR_ERR(rstc), 2942 "failed to get cpg reset\n"); 2943 2944 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 2945 NUM_TX_QUEUE, NUM_RX_QUEUE); 2946 if (!ndev) 2947 return -ENOMEM; 2948 2949 info = of_device_get_match_data(&pdev->dev); 2950 2951 ndev->features = info->net_features; 2952 ndev->hw_features = info->net_hw_features; 2953 ndev->vlan_features = info->vlan_features; 2954 2955 error = reset_control_deassert(rstc); 2956 if (error) 2957 goto out_free_netdev; 2958 2959 SET_NETDEV_DEV(ndev, &pdev->dev); 2960 2961 priv = netdev_priv(ndev); 2962 priv->info = info; 2963 priv->rstc = rstc; 2964 priv->ndev = ndev; 2965 priv->pdev = pdev; 2966 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2967 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2968 if (info->nc_queues) { 2969 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2970 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2971 } 2972 2973 error = ravb_setup_irqs(priv); 2974 if (error) 2975 goto out_reset_assert; 2976 2977 priv->clk = devm_clk_get(&pdev->dev, NULL); 2978 if (IS_ERR(priv->clk)) { 2979 error = PTR_ERR(priv->clk); 2980 goto out_reset_assert; 2981 } 2982 2983 if (info->gptp_ref_clk) { 2984 priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp"); 2985 if (IS_ERR(priv->gptp_clk)) { 2986 error = PTR_ERR(priv->gptp_clk); 2987 goto out_reset_assert; 2988 } 2989 } 2990 2991 priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk"); 2992 if (IS_ERR(priv->refclk)) { 2993 error = PTR_ERR(priv->refclk); 2994 goto out_reset_assert; 2995 } 2996 clk_prepare(priv->refclk); 2997 2998 platform_set_drvdata(pdev, ndev); 2999 pm_runtime_set_autosuspend_delay(&pdev->dev, 100); 3000 pm_runtime_use_autosuspend(&pdev->dev); 3001 pm_runtime_enable(&pdev->dev); 3002 error = pm_runtime_resume_and_get(&pdev->dev); 3003 if (error < 0) 3004 goto out_rpm_disable; 3005 3006 priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 3007 if (IS_ERR(priv->addr)) { 3008 error = PTR_ERR(priv->addr); 3009 goto out_rpm_put; 3010 } 3011 3012 /* The Ether-specific entries in the device structure. */ 3013 ndev->base_addr = res->start; 3014 3015 spin_lock_init(&priv->lock); 3016 INIT_WORK(&priv->work, ravb_tx_timeout_work); 3017 3018 error = of_get_phy_mode(np, &priv->phy_interface); 3019 if (error && error != -ENODEV) 3020 goto out_rpm_put; 3021 3022 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 3023 priv->avb_link_active_low = 3024 of_property_read_bool(np, "renesas,ether-link-active-low"); 3025 3026 ndev->max_mtu = info->tx_max_frame_size - 3027 (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 3028 ndev->min_mtu = ETH_MIN_MTU; 3029 3030 /* FIXME: R-Car Gen2 has 4byte alignment restriction for tx buffer 3031 * Use two descriptor to handle such situation. First descriptor to 3032 * handle aligned data buffer and second descriptor to handle the 3033 * overflow data because of alignment. 3034 */ 3035 priv->num_tx_desc = info->aligned_tx ? 2 : 1; 3036 3037 /* Set function */ 3038 ndev->netdev_ops = &ravb_netdev_ops; 3039 ndev->ethtool_ops = &ravb_ethtool_ops; 3040 3041 error = ravb_compute_gti(ndev); 3042 if (error) 3043 goto out_rpm_put; 3044 3045 ravb_parse_delay_mode(np, ndev); 3046 3047 /* Allocate descriptor base address table */ 3048 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM; 3049 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 3050 &priv->desc_bat_dma, GFP_KERNEL); 3051 if (!priv->desc_bat) { 3052 dev_err(&pdev->dev, 3053 "Cannot allocate desc base address table (size %d bytes)\n", 3054 priv->desc_bat_size); 3055 error = -ENOMEM; 3056 goto out_rpm_put; 3057 } 3058 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++) 3059 priv->desc_bat[q].die_dt = DT_EOS; 3060 3061 /* Initialise HW timestamp list */ 3062 INIT_LIST_HEAD(&priv->ts_skb_list); 3063 3064 /* Debug message level */ 3065 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 3066 3067 /* Set config mode as this is needed for PHY initialization. */ 3068 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 3069 if (error) 3070 goto out_rpm_put; 3071 3072 /* Read and set MAC address */ 3073 ravb_read_mac_address(np, ndev); 3074 if (!is_valid_ether_addr(ndev->dev_addr)) { 3075 dev_warn(&pdev->dev, 3076 "no valid MAC address supplied, using a random one\n"); 3077 eth_hw_addr_random(ndev); 3078 } 3079 3080 /* MDIO bus init */ 3081 error = ravb_mdio_init(priv); 3082 if (error) { 3083 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 3084 goto out_reset_mode; 3085 } 3086 3087 /* Undo previous switch to config opmode. */ 3088 error = ravb_set_opmode(ndev, CCC_OPC_RESET); 3089 if (error) 3090 goto out_mdio_release; 3091 3092 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll); 3093 if (info->nc_queues) 3094 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll); 3095 3096 if (info->coalesce_irqs) { 3097 netdev_sw_irq_coalesce_default_on(ndev); 3098 if (num_present_cpus() == 1) 3099 netif_threaded_enable(ndev); 3100 } 3101 3102 /* Network device register */ 3103 error = register_netdev(ndev); 3104 if (error) 3105 goto out_napi_del; 3106 3107 device_set_wakeup_capable(&pdev->dev, 1); 3108 3109 /* Print device information */ 3110 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 3111 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 3112 3113 pm_runtime_mark_last_busy(&pdev->dev); 3114 pm_runtime_put_autosuspend(&pdev->dev); 3115 3116 return 0; 3117 3118 out_napi_del: 3119 if (info->nc_queues) 3120 netif_napi_del(&priv->napi[RAVB_NC]); 3121 3122 netif_napi_del(&priv->napi[RAVB_BE]); 3123 out_mdio_release: 3124 ravb_mdio_release(priv); 3125 out_reset_mode: 3126 ravb_set_opmode(ndev, CCC_OPC_RESET); 3127 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 3128 priv->desc_bat_dma); 3129 out_rpm_put: 3130 pm_runtime_put(&pdev->dev); 3131 out_rpm_disable: 3132 pm_runtime_disable(&pdev->dev); 3133 pm_runtime_dont_use_autosuspend(&pdev->dev); 3134 clk_unprepare(priv->refclk); 3135 out_reset_assert: 3136 reset_control_assert(rstc); 3137 out_free_netdev: 3138 free_netdev(ndev); 3139 return error; 3140 } 3141 3142 static void ravb_remove(struct platform_device *pdev) 3143 { 3144 struct net_device *ndev = platform_get_drvdata(pdev); 3145 struct ravb_private *priv = netdev_priv(ndev); 3146 const struct ravb_hw_info *info = priv->info; 3147 struct device *dev = &priv->pdev->dev; 3148 int error; 3149 3150 error = pm_runtime_resume_and_get(dev); 3151 if (error < 0) 3152 return; 3153 3154 unregister_netdev(ndev); 3155 if (info->nc_queues) 3156 netif_napi_del(&priv->napi[RAVB_NC]); 3157 netif_napi_del(&priv->napi[RAVB_BE]); 3158 3159 ravb_mdio_release(priv); 3160 3161 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 3162 priv->desc_bat_dma); 3163 3164 pm_runtime_put_sync_suspend(&pdev->dev); 3165 pm_runtime_disable(&pdev->dev); 3166 pm_runtime_dont_use_autosuspend(dev); 3167 clk_unprepare(priv->refclk); 3168 reset_control_assert(priv->rstc); 3169 free_netdev(ndev); 3170 platform_set_drvdata(pdev, NULL); 3171 } 3172 3173 static int ravb_wol_setup(struct net_device *ndev) 3174 { 3175 struct ravb_private *priv = netdev_priv(ndev); 3176 const struct ravb_hw_info *info = priv->info; 3177 3178 /* Disable interrupts by clearing the interrupt masks. */ 3179 ravb_write(ndev, 0, RIC0); 3180 ravb_write(ndev, 0, RIC2); 3181 ravb_write(ndev, 0, TIC); 3182 3183 /* Only allow ECI interrupts */ 3184 synchronize_irq(priv->emac_irq); 3185 if (info->nc_queues) 3186 napi_disable(&priv->napi[RAVB_NC]); 3187 napi_disable(&priv->napi[RAVB_BE]); 3188 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 3189 3190 /* Enable MagicPacket */ 3191 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 3192 3193 if (priv->info->ccc_gac) 3194 ravb_ptp_stop(ndev); 3195 3196 return enable_irq_wake(priv->emac_irq); 3197 } 3198 3199 static int ravb_wol_restore(struct net_device *ndev) 3200 { 3201 struct ravb_private *priv = netdev_priv(ndev); 3202 const struct ravb_hw_info *info = priv->info; 3203 int error; 3204 3205 /* Set reset mode to rearm the WoL logic. */ 3206 error = ravb_set_opmode(ndev, CCC_OPC_RESET); 3207 if (error) 3208 return error; 3209 3210 /* Set AVB config mode. */ 3211 error = ravb_set_config_mode(ndev); 3212 if (error) 3213 return error; 3214 3215 if (priv->info->ccc_gac) 3216 ravb_ptp_init(ndev, priv->pdev); 3217 3218 if (info->nc_queues) 3219 napi_enable(&priv->napi[RAVB_NC]); 3220 napi_enable(&priv->napi[RAVB_BE]); 3221 3222 /* Disable MagicPacket */ 3223 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 3224 3225 ravb_close(ndev); 3226 3227 return disable_irq_wake(priv->emac_irq); 3228 } 3229 3230 static int ravb_suspend(struct device *dev) 3231 { 3232 struct net_device *ndev = dev_get_drvdata(dev); 3233 struct ravb_private *priv = netdev_priv(ndev); 3234 int ret; 3235 3236 if (!netif_running(ndev)) 3237 goto reset_assert; 3238 3239 netif_device_detach(ndev); 3240 3241 rtnl_lock(); 3242 if (priv->wol_enabled) { 3243 ret = ravb_wol_setup(ndev); 3244 rtnl_unlock(); 3245 return ret; 3246 } 3247 3248 ret = ravb_close(ndev); 3249 rtnl_unlock(); 3250 if (ret) 3251 return ret; 3252 3253 ret = pm_runtime_force_suspend(&priv->pdev->dev); 3254 if (ret) 3255 return ret; 3256 3257 reset_assert: 3258 return reset_control_assert(priv->rstc); 3259 } 3260 3261 static int ravb_resume(struct device *dev) 3262 { 3263 struct net_device *ndev = dev_get_drvdata(dev); 3264 struct ravb_private *priv = netdev_priv(ndev); 3265 int ret; 3266 3267 ret = reset_control_deassert(priv->rstc); 3268 if (ret) 3269 return ret; 3270 3271 if (!netif_running(ndev)) 3272 return 0; 3273 3274 rtnl_lock(); 3275 /* If WoL is enabled restore the interface. */ 3276 if (priv->wol_enabled) 3277 ret = ravb_wol_restore(ndev); 3278 else 3279 ret = pm_runtime_force_resume(dev); 3280 if (ret) { 3281 rtnl_unlock(); 3282 return ret; 3283 } 3284 3285 /* Reopening the interface will restore the device to the working state. */ 3286 ret = ravb_open(ndev); 3287 rtnl_unlock(); 3288 if (ret < 0) 3289 goto out_rpm_put; 3290 3291 ravb_set_rx_mode(ndev); 3292 netif_device_attach(ndev); 3293 3294 return 0; 3295 3296 out_rpm_put: 3297 if (!priv->wol_enabled) { 3298 pm_runtime_mark_last_busy(dev); 3299 pm_runtime_put_autosuspend(dev); 3300 } 3301 3302 return ret; 3303 } 3304 3305 static int ravb_runtime_suspend(struct device *dev) 3306 { 3307 struct net_device *ndev = dev_get_drvdata(dev); 3308 struct ravb_private *priv = netdev_priv(ndev); 3309 3310 clk_disable(priv->refclk); 3311 3312 return 0; 3313 } 3314 3315 static int ravb_runtime_resume(struct device *dev) 3316 { 3317 struct net_device *ndev = dev_get_drvdata(dev); 3318 struct ravb_private *priv = netdev_priv(ndev); 3319 3320 return clk_enable(priv->refclk); 3321 } 3322 3323 static const struct dev_pm_ops ravb_dev_pm_ops = { 3324 SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 3325 RUNTIME_PM_OPS(ravb_runtime_suspend, ravb_runtime_resume, NULL) 3326 }; 3327 3328 static struct platform_driver ravb_driver = { 3329 .probe = ravb_probe, 3330 .remove = ravb_remove, 3331 .driver = { 3332 .name = "ravb", 3333 .pm = pm_ptr(&ravb_dev_pm_ops), 3334 .of_match_table = ravb_match_table, 3335 }, 3336 }; 3337 3338 module_platform_driver(ravb_driver); 3339 3340 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 3341 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 3342 MODULE_LICENSE("GPL v2"); 3343