xref: /linux/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c (revision 9410645520e9b820069761f3450ef6661418e279)
1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell RVU Ethernet driver
3  *
4  * Copyright (C) 2020 Marvell.
5  *
6  */
7 
8 #include <linux/etherdevice.h>
9 #include <net/ip.h>
10 #include <net/tso.h>
11 #include <linux/bpf.h>
12 #include <linux/bpf_trace.h>
13 #include <net/ip6_checksum.h>
14 
15 #include "otx2_reg.h"
16 #include "otx2_common.h"
17 #include "otx2_struct.h"
18 #include "otx2_txrx.h"
19 #include "otx2_ptp.h"
20 #include "cn10k.h"
21 
22 #define CQE_ADDR(CQ, idx) ((CQ)->cqe_base + ((CQ)->cqe_size * (idx)))
23 #define PTP_PORT	        0x13F
24 /* PTPv2 header Original Timestamp starts at byte offset 34 and
25  * contains 6 byte seconds field and 4 byte nano seconds field.
26  */
27 #define PTP_SYNC_SEC_OFFSET	34
28 
29 static bool otx2_xdp_rcv_pkt_handler(struct otx2_nic *pfvf,
30 				     struct bpf_prog *prog,
31 				     struct nix_cqe_rx_s *cqe,
32 				     struct otx2_cq_queue *cq,
33 				     bool *need_xdp_flush);
34 
otx2_nix_cq_op_status(struct otx2_nic * pfvf,struct otx2_cq_queue * cq)35 static int otx2_nix_cq_op_status(struct otx2_nic *pfvf,
36 				 struct otx2_cq_queue *cq)
37 {
38 	u64 incr = (u64)(cq->cq_idx) << 32;
39 	u64 status;
40 
41 	status = otx2_atomic64_fetch_add(incr, pfvf->cq_op_addr);
42 
43 	if (unlikely(status & BIT_ULL(CQ_OP_STAT_OP_ERR) ||
44 		     status & BIT_ULL(CQ_OP_STAT_CQ_ERR))) {
45 		dev_err(pfvf->dev, "CQ stopped due to error");
46 		return -EINVAL;
47 	}
48 
49 	cq->cq_tail = status & 0xFFFFF;
50 	cq->cq_head = (status >> 20) & 0xFFFFF;
51 	if (cq->cq_tail < cq->cq_head)
52 		cq->pend_cqe = (cq->cqe_cnt - cq->cq_head) +
53 				cq->cq_tail;
54 	else
55 		cq->pend_cqe = cq->cq_tail - cq->cq_head;
56 
57 	return 0;
58 }
59 
otx2_get_next_cqe(struct otx2_cq_queue * cq)60 static struct nix_cqe_hdr_s *otx2_get_next_cqe(struct otx2_cq_queue *cq)
61 {
62 	struct nix_cqe_hdr_s *cqe_hdr;
63 
64 	cqe_hdr = (struct nix_cqe_hdr_s *)CQE_ADDR(cq, cq->cq_head);
65 	if (cqe_hdr->cqe_type == NIX_XQE_TYPE_INVALID)
66 		return NULL;
67 
68 	cq->cq_head++;
69 	cq->cq_head &= (cq->cqe_cnt - 1);
70 
71 	return cqe_hdr;
72 }
73 
frag_num(unsigned int i)74 static unsigned int frag_num(unsigned int i)
75 {
76 #ifdef __BIG_ENDIAN
77 	return (i & ~3) + 3 - (i & 3);
78 #else
79 	return i;
80 #endif
81 }
82 
otx2_dma_map_skb_frag(struct otx2_nic * pfvf,struct sk_buff * skb,int seg,int * len)83 static dma_addr_t otx2_dma_map_skb_frag(struct otx2_nic *pfvf,
84 					struct sk_buff *skb, int seg, int *len)
85 {
86 	const skb_frag_t *frag;
87 	struct page *page;
88 	int offset;
89 
90 	/* First segment is always skb->data */
91 	if (!seg) {
92 		page = virt_to_page(skb->data);
93 		offset = offset_in_page(skb->data);
94 		*len = skb_headlen(skb);
95 	} else {
96 		frag = &skb_shinfo(skb)->frags[seg - 1];
97 		page = skb_frag_page(frag);
98 		offset = skb_frag_off(frag);
99 		*len = skb_frag_size(frag);
100 	}
101 	return otx2_dma_map_page(pfvf, page, offset, *len, DMA_TO_DEVICE);
102 }
103 
otx2_dma_unmap_skb_frags(struct otx2_nic * pfvf,struct sg_list * sg)104 static void otx2_dma_unmap_skb_frags(struct otx2_nic *pfvf, struct sg_list *sg)
105 {
106 	int seg;
107 
108 	for (seg = 0; seg < sg->num_segs; seg++) {
109 		otx2_dma_unmap_page(pfvf, sg->dma_addr[seg],
110 				    sg->size[seg], DMA_TO_DEVICE);
111 	}
112 	sg->num_segs = 0;
113 }
114 
otx2_xdp_snd_pkt_handler(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct nix_cqe_tx_s * cqe)115 static void otx2_xdp_snd_pkt_handler(struct otx2_nic *pfvf,
116 				     struct otx2_snd_queue *sq,
117 				 struct nix_cqe_tx_s *cqe)
118 {
119 	struct nix_send_comp_s *snd_comp = &cqe->comp;
120 	struct sg_list *sg;
121 	struct page *page;
122 	u64 pa;
123 
124 	sg = &sq->sg[snd_comp->sqe_id];
125 
126 	pa = otx2_iova_to_phys(pfvf->iommu_domain, sg->dma_addr[0]);
127 	otx2_dma_unmap_page(pfvf, sg->dma_addr[0],
128 			    sg->size[0], DMA_TO_DEVICE);
129 	page = virt_to_page(phys_to_virt(pa));
130 	put_page(page);
131 }
132 
otx2_snd_pkt_handler(struct otx2_nic * pfvf,struct otx2_cq_queue * cq,struct otx2_snd_queue * sq,struct nix_cqe_tx_s * cqe,int budget,int * tx_pkts,int * tx_bytes)133 static void otx2_snd_pkt_handler(struct otx2_nic *pfvf,
134 				 struct otx2_cq_queue *cq,
135 				 struct otx2_snd_queue *sq,
136 				 struct nix_cqe_tx_s *cqe,
137 				 int budget, int *tx_pkts, int *tx_bytes)
138 {
139 	struct nix_send_comp_s *snd_comp = &cqe->comp;
140 	struct skb_shared_hwtstamps ts;
141 	struct sk_buff *skb = NULL;
142 	u64 timestamp, tsns;
143 	struct sg_list *sg;
144 	int err;
145 
146 	if (unlikely(snd_comp->status) && netif_msg_tx_err(pfvf))
147 		net_err_ratelimited("%s: TX%d: Error in send CQ status:%x\n",
148 				    pfvf->netdev->name, cq->cint_idx,
149 				    snd_comp->status);
150 
151 	sg = &sq->sg[snd_comp->sqe_id];
152 	skb = (struct sk_buff *)sg->skb;
153 	if (unlikely(!skb))
154 		return;
155 
156 	if (skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) {
157 		timestamp = ((u64 *)sq->timestamps->base)[snd_comp->sqe_id];
158 		if (timestamp != 1) {
159 			timestamp = pfvf->ptp->convert_tx_ptp_tstmp(timestamp);
160 			err = otx2_ptp_tstamp2time(pfvf, timestamp, &tsns);
161 			if (!err) {
162 				memset(&ts, 0, sizeof(ts));
163 				ts.hwtstamp = ns_to_ktime(tsns);
164 				skb_tstamp_tx(skb, &ts);
165 			}
166 		}
167 	}
168 
169 	*tx_bytes += skb->len;
170 	(*tx_pkts)++;
171 	otx2_dma_unmap_skb_frags(pfvf, sg);
172 	napi_consume_skb(skb, budget);
173 	sg->skb = (u64)NULL;
174 }
175 
otx2_set_rxtstamp(struct otx2_nic * pfvf,struct sk_buff * skb,void * data)176 static void otx2_set_rxtstamp(struct otx2_nic *pfvf,
177 			      struct sk_buff *skb, void *data)
178 {
179 	u64 timestamp, tsns;
180 	int err;
181 
182 	if (!(pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED))
183 		return;
184 
185 	timestamp = pfvf->ptp->convert_rx_ptp_tstmp(*(u64 *)data);
186 	/* The first 8 bytes is the timestamp */
187 	err = otx2_ptp_tstamp2time(pfvf, timestamp, &tsns);
188 	if (err)
189 		return;
190 
191 	skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(tsns);
192 }
193 
otx2_skb_add_frag(struct otx2_nic * pfvf,struct sk_buff * skb,u64 iova,int len,struct nix_rx_parse_s * parse,int qidx)194 static bool otx2_skb_add_frag(struct otx2_nic *pfvf, struct sk_buff *skb,
195 			      u64 iova, int len, struct nix_rx_parse_s *parse,
196 			      int qidx)
197 {
198 	struct page *page;
199 	int off = 0;
200 	void *va;
201 
202 	va = phys_to_virt(otx2_iova_to_phys(pfvf->iommu_domain, iova));
203 
204 	if (likely(!skb_shinfo(skb)->nr_frags)) {
205 		/* Check if data starts at some nonzero offset
206 		 * from the start of the buffer.  For now the
207 		 * only possible offset is 8 bytes in the case
208 		 * where packet is prepended by a timestamp.
209 		 */
210 		if (parse->laptr) {
211 			otx2_set_rxtstamp(pfvf, skb, va);
212 			off = OTX2_HW_TIMESTAMP_LEN;
213 		}
214 	}
215 
216 	page = virt_to_page(va);
217 	if (likely(skb_shinfo(skb)->nr_frags < MAX_SKB_FRAGS)) {
218 		skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
219 				va - page_address(page) + off,
220 				len - off, pfvf->rbsize);
221 		return true;
222 	}
223 
224 	/* If more than MAX_SKB_FRAGS fragments are received then
225 	 * give back those buffer pointers to hardware for reuse.
226 	 */
227 	pfvf->hw_ops->aura_freeptr(pfvf, qidx, iova & ~0x07ULL);
228 
229 	return false;
230 }
231 
otx2_set_rxhash(struct otx2_nic * pfvf,struct nix_cqe_rx_s * cqe,struct sk_buff * skb)232 static void otx2_set_rxhash(struct otx2_nic *pfvf,
233 			    struct nix_cqe_rx_s *cqe, struct sk_buff *skb)
234 {
235 	enum pkt_hash_types hash_type = PKT_HASH_TYPE_NONE;
236 	struct otx2_rss_info *rss;
237 	u32 hash = 0;
238 
239 	if (!(pfvf->netdev->features & NETIF_F_RXHASH))
240 		return;
241 
242 	rss = &pfvf->hw.rss_info;
243 	if (rss->flowkey_cfg) {
244 		if (rss->flowkey_cfg &
245 		    ~(NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6))
246 			hash_type = PKT_HASH_TYPE_L4;
247 		else
248 			hash_type = PKT_HASH_TYPE_L3;
249 		hash = cqe->hdr.flow_tag;
250 	}
251 	skb_set_hash(skb, hash, hash_type);
252 }
253 
otx2_free_rcv_seg(struct otx2_nic * pfvf,struct nix_cqe_rx_s * cqe,int qidx)254 static void otx2_free_rcv_seg(struct otx2_nic *pfvf, struct nix_cqe_rx_s *cqe,
255 			      int qidx)
256 {
257 	struct nix_rx_sg_s *sg = &cqe->sg;
258 	void *end, *start;
259 	u64 *seg_addr;
260 	int seg;
261 
262 	start = (void *)sg;
263 	end = start + ((cqe->parse.desc_sizem1 + 1) * 16);
264 	while (start < end) {
265 		sg = (struct nix_rx_sg_s *)start;
266 		seg_addr = &sg->seg_addr;
267 		for (seg = 0; seg < sg->segs; seg++, seg_addr++)
268 			pfvf->hw_ops->aura_freeptr(pfvf, qidx,
269 						   *seg_addr & ~0x07ULL);
270 		start += sizeof(*sg);
271 	}
272 }
273 
otx2_check_rcv_errors(struct otx2_nic * pfvf,struct nix_cqe_rx_s * cqe,int qidx)274 static bool otx2_check_rcv_errors(struct otx2_nic *pfvf,
275 				  struct nix_cqe_rx_s *cqe, int qidx)
276 {
277 	struct otx2_drv_stats *stats = &pfvf->hw.drv_stats;
278 	struct nix_rx_parse_s *parse = &cqe->parse;
279 
280 	if (netif_msg_rx_err(pfvf))
281 		netdev_err(pfvf->netdev,
282 			   "RQ%d: Error pkt with errlev:0x%x errcode:0x%x\n",
283 			   qidx, parse->errlev, parse->errcode);
284 
285 	if (parse->errlev == NPC_ERRLVL_RE) {
286 		switch (parse->errcode) {
287 		case ERRCODE_FCS:
288 		case ERRCODE_FCS_RCV:
289 			atomic_inc(&stats->rx_fcs_errs);
290 			break;
291 		case ERRCODE_UNDERSIZE:
292 			atomic_inc(&stats->rx_undersize_errs);
293 			break;
294 		case ERRCODE_OVERSIZE:
295 			atomic_inc(&stats->rx_oversize_errs);
296 			break;
297 		case ERRCODE_OL2_LEN_MISMATCH:
298 			atomic_inc(&stats->rx_len_errs);
299 			break;
300 		default:
301 			atomic_inc(&stats->rx_other_errs);
302 			break;
303 		}
304 	} else if (parse->errlev == NPC_ERRLVL_NIX) {
305 		switch (parse->errcode) {
306 		case ERRCODE_OL3_LEN:
307 		case ERRCODE_OL4_LEN:
308 		case ERRCODE_IL3_LEN:
309 		case ERRCODE_IL4_LEN:
310 			atomic_inc(&stats->rx_len_errs);
311 			break;
312 		case ERRCODE_OL4_CSUM:
313 		case ERRCODE_IL4_CSUM:
314 			atomic_inc(&stats->rx_csum_errs);
315 			break;
316 		default:
317 			atomic_inc(&stats->rx_other_errs);
318 			break;
319 		}
320 	} else {
321 		atomic_inc(&stats->rx_other_errs);
322 		/* For now ignore all the NPC parser errors and
323 		 * pass the packets to stack.
324 		 */
325 		return false;
326 	}
327 
328 	/* If RXALL is enabled pass on packets to stack. */
329 	if (pfvf->netdev->features & NETIF_F_RXALL)
330 		return false;
331 
332 	/* Free buffer back to pool */
333 	if (cqe->sg.segs)
334 		otx2_free_rcv_seg(pfvf, cqe, qidx);
335 	return true;
336 }
337 
otx2_rcv_pkt_handler(struct otx2_nic * pfvf,struct napi_struct * napi,struct otx2_cq_queue * cq,struct nix_cqe_rx_s * cqe,bool * need_xdp_flush)338 static void otx2_rcv_pkt_handler(struct otx2_nic *pfvf,
339 				 struct napi_struct *napi,
340 				 struct otx2_cq_queue *cq,
341 				 struct nix_cqe_rx_s *cqe, bool *need_xdp_flush)
342 {
343 	struct nix_rx_parse_s *parse = &cqe->parse;
344 	struct nix_rx_sg_s *sg = &cqe->sg;
345 	struct sk_buff *skb = NULL;
346 	void *end, *start;
347 	u64 *seg_addr;
348 	u16 *seg_size;
349 	int seg;
350 
351 	if (unlikely(parse->errlev || parse->errcode)) {
352 		if (otx2_check_rcv_errors(pfvf, cqe, cq->cq_idx))
353 			return;
354 	}
355 
356 	if (pfvf->xdp_prog)
357 		if (otx2_xdp_rcv_pkt_handler(pfvf, pfvf->xdp_prog, cqe, cq, need_xdp_flush))
358 			return;
359 
360 	skb = napi_get_frags(napi);
361 	if (unlikely(!skb))
362 		return;
363 
364 	start = (void *)sg;
365 	end = start + ((cqe->parse.desc_sizem1 + 1) * 16);
366 	while (start < end) {
367 		sg = (struct nix_rx_sg_s *)start;
368 		seg_addr = &sg->seg_addr;
369 		seg_size = (void *)sg;
370 		for (seg = 0; seg < sg->segs; seg++, seg_addr++) {
371 			if (otx2_skb_add_frag(pfvf, skb, *seg_addr,
372 					      seg_size[seg], parse, cq->cq_idx))
373 				cq->pool_ptrs++;
374 		}
375 		start += sizeof(*sg);
376 	}
377 	otx2_set_rxhash(pfvf, cqe, skb);
378 
379 	skb_record_rx_queue(skb, cq->cq_idx);
380 	if (pfvf->netdev->features & NETIF_F_RXCSUM)
381 		skb->ip_summed = CHECKSUM_UNNECESSARY;
382 
383 	if (pfvf->flags & OTX2_FLAG_TC_MARK_ENABLED)
384 		skb->mark = parse->match_id;
385 
386 	skb_mark_for_recycle(skb);
387 
388 	napi_gro_frags(napi);
389 }
390 
otx2_rx_napi_handler(struct otx2_nic * pfvf,struct napi_struct * napi,struct otx2_cq_queue * cq,int budget)391 static int otx2_rx_napi_handler(struct otx2_nic *pfvf,
392 				struct napi_struct *napi,
393 				struct otx2_cq_queue *cq, int budget)
394 {
395 	bool need_xdp_flush = false;
396 	struct nix_cqe_rx_s *cqe;
397 	int processed_cqe = 0;
398 
399 	if (cq->pend_cqe >= budget)
400 		goto process_cqe;
401 
402 	if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe)
403 		return 0;
404 
405 process_cqe:
406 	while (likely(processed_cqe < budget) && cq->pend_cqe) {
407 		cqe = (struct nix_cqe_rx_s *)CQE_ADDR(cq, cq->cq_head);
408 		if (cqe->hdr.cqe_type == NIX_XQE_TYPE_INVALID ||
409 		    !cqe->sg.seg_addr) {
410 			if (!processed_cqe)
411 				return 0;
412 			break;
413 		}
414 		cq->cq_head++;
415 		cq->cq_head &= (cq->cqe_cnt - 1);
416 
417 		otx2_rcv_pkt_handler(pfvf, napi, cq, cqe, &need_xdp_flush);
418 
419 		cqe->hdr.cqe_type = NIX_XQE_TYPE_INVALID;
420 		cqe->sg.seg_addr = 0x00;
421 		processed_cqe++;
422 		cq->pend_cqe--;
423 	}
424 	if (need_xdp_flush)
425 		xdp_do_flush();
426 
427 	/* Free CQEs to HW */
428 	otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR,
429 		     ((u64)cq->cq_idx << 32) | processed_cqe);
430 
431 	return processed_cqe;
432 }
433 
otx2_refill_pool_ptrs(void * dev,struct otx2_cq_queue * cq)434 int otx2_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq)
435 {
436 	struct otx2_nic *pfvf = dev;
437 	int cnt = cq->pool_ptrs;
438 	dma_addr_t bufptr;
439 
440 	while (cq->pool_ptrs) {
441 		if (otx2_alloc_buffer(pfvf, cq, &bufptr))
442 			break;
443 		otx2_aura_freeptr(pfvf, cq->cq_idx, bufptr + OTX2_HEAD_ROOM);
444 		cq->pool_ptrs--;
445 	}
446 
447 	return cnt - cq->pool_ptrs;
448 }
449 
otx2_tx_napi_handler(struct otx2_nic * pfvf,struct otx2_cq_queue * cq,int budget)450 static int otx2_tx_napi_handler(struct otx2_nic *pfvf,
451 				struct otx2_cq_queue *cq, int budget)
452 {
453 	int tx_pkts = 0, tx_bytes = 0, qidx;
454 	struct otx2_snd_queue *sq;
455 	struct nix_cqe_tx_s *cqe;
456 	int processed_cqe = 0;
457 
458 	if (cq->pend_cqe >= budget)
459 		goto process_cqe;
460 
461 	if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe)
462 		return 0;
463 
464 process_cqe:
465 	qidx = cq->cq_idx - pfvf->hw.rx_queues;
466 	sq = &pfvf->qset.sq[qidx];
467 
468 	while (likely(processed_cqe < budget) && cq->pend_cqe) {
469 		cqe = (struct nix_cqe_tx_s *)otx2_get_next_cqe(cq);
470 		if (unlikely(!cqe)) {
471 			if (!processed_cqe)
472 				return 0;
473 			break;
474 		}
475 
476 		qidx = cq->cq_idx - pfvf->hw.rx_queues;
477 
478 		if (cq->cq_type == CQ_XDP)
479 			otx2_xdp_snd_pkt_handler(pfvf, sq, cqe);
480 		else
481 			otx2_snd_pkt_handler(pfvf, cq, &pfvf->qset.sq[qidx],
482 					     cqe, budget, &tx_pkts, &tx_bytes);
483 
484 		cqe->hdr.cqe_type = NIX_XQE_TYPE_INVALID;
485 		processed_cqe++;
486 		cq->pend_cqe--;
487 
488 		sq->cons_head++;
489 		sq->cons_head &= (sq->sqe_cnt - 1);
490 	}
491 
492 	/* Free CQEs to HW */
493 	otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR,
494 		     ((u64)cq->cq_idx << 32) | processed_cqe);
495 
496 	if (likely(tx_pkts)) {
497 		struct netdev_queue *txq;
498 
499 		qidx = cq->cq_idx - pfvf->hw.rx_queues;
500 
501 		if (qidx >= pfvf->hw.tx_queues)
502 			qidx -= pfvf->hw.xdp_queues;
503 		txq = netdev_get_tx_queue(pfvf->netdev, qidx);
504 		netdev_tx_completed_queue(txq, tx_pkts, tx_bytes);
505 		/* Check if queue was stopped earlier due to ring full */
506 		smp_mb();
507 		if (netif_tx_queue_stopped(txq) &&
508 		    netif_carrier_ok(pfvf->netdev))
509 			netif_tx_wake_queue(txq);
510 	}
511 	return 0;
512 }
513 
otx2_adjust_adaptive_coalese(struct otx2_nic * pfvf,struct otx2_cq_poll * cq_poll)514 static void otx2_adjust_adaptive_coalese(struct otx2_nic *pfvf, struct otx2_cq_poll *cq_poll)
515 {
516 	struct dim_sample dim_sample = { 0 };
517 	u64 rx_frames, rx_bytes;
518 	u64 tx_frames, tx_bytes;
519 
520 	rx_frames = OTX2_GET_RX_STATS(RX_BCAST) + OTX2_GET_RX_STATS(RX_MCAST) +
521 		OTX2_GET_RX_STATS(RX_UCAST);
522 	rx_bytes = OTX2_GET_RX_STATS(RX_OCTS);
523 	tx_bytes = OTX2_GET_TX_STATS(TX_OCTS);
524 	tx_frames = OTX2_GET_TX_STATS(TX_UCAST);
525 
526 	dim_update_sample(pfvf->napi_events,
527 			  rx_frames + tx_frames,
528 			  rx_bytes + tx_bytes,
529 			  &dim_sample);
530 	net_dim(&cq_poll->dim, dim_sample);
531 }
532 
otx2_napi_handler(struct napi_struct * napi,int budget)533 int otx2_napi_handler(struct napi_struct *napi, int budget)
534 {
535 	struct otx2_cq_queue *rx_cq = NULL;
536 	struct otx2_cq_poll *cq_poll;
537 	int workdone = 0, cq_idx, i;
538 	struct otx2_cq_queue *cq;
539 	struct otx2_qset *qset;
540 	struct otx2_nic *pfvf;
541 	int filled_cnt = -1;
542 
543 	cq_poll = container_of(napi, struct otx2_cq_poll, napi);
544 	pfvf = (struct otx2_nic *)cq_poll->dev;
545 	qset = &pfvf->qset;
546 
547 	for (i = 0; i < CQS_PER_CINT; i++) {
548 		cq_idx = cq_poll->cq_ids[i];
549 		if (unlikely(cq_idx == CINT_INVALID_CQ))
550 			continue;
551 		cq = &qset->cq[cq_idx];
552 		if (cq->cq_type == CQ_RX) {
553 			rx_cq = cq;
554 			workdone += otx2_rx_napi_handler(pfvf, napi,
555 							 cq, budget);
556 		} else {
557 			workdone += otx2_tx_napi_handler(pfvf, cq, budget);
558 		}
559 	}
560 
561 	if (rx_cq && rx_cq->pool_ptrs)
562 		filled_cnt = pfvf->hw_ops->refill_pool_ptrs(pfvf, rx_cq);
563 	/* Clear the IRQ */
564 	otx2_write64(pfvf, NIX_LF_CINTX_INT(cq_poll->cint_idx), BIT_ULL(0));
565 
566 	if (workdone < budget && napi_complete_done(napi, workdone)) {
567 		/* If interface is going down, don't re-enable IRQ */
568 		if (pfvf->flags & OTX2_FLAG_INTF_DOWN)
569 			return workdone;
570 
571 		/* Adjust irq coalese using net_dim */
572 		if (pfvf->flags & OTX2_FLAG_ADPTV_INT_COAL_ENABLED)
573 			otx2_adjust_adaptive_coalese(pfvf, cq_poll);
574 
575 		if (unlikely(!filled_cnt)) {
576 			struct refill_work *work;
577 			struct delayed_work *dwork;
578 
579 			work = &pfvf->refill_wrk[cq->cq_idx];
580 			dwork = &work->pool_refill_work;
581 			/* Schedule a task if no other task is running */
582 			if (!cq->refill_task_sched) {
583 				work->napi = napi;
584 				cq->refill_task_sched = true;
585 				schedule_delayed_work(dwork,
586 						      msecs_to_jiffies(100));
587 			}
588 		} else {
589 			/* Re-enable interrupts */
590 			otx2_write64(pfvf,
591 				     NIX_LF_CINTX_ENA_W1S(cq_poll->cint_idx),
592 				     BIT_ULL(0));
593 		}
594 	}
595 	return workdone;
596 }
597 
otx2_sqe_flush(void * dev,struct otx2_snd_queue * sq,int size,int qidx)598 void otx2_sqe_flush(void *dev, struct otx2_snd_queue *sq,
599 		    int size, int qidx)
600 {
601 	u64 status;
602 
603 	/* Packet data stores should finish before SQE is flushed to HW */
604 	dma_wmb();
605 
606 	do {
607 		memcpy(sq->lmt_addr, sq->sqe_base, size);
608 		status = otx2_lmt_flush(sq->io_addr);
609 	} while (status == 0);
610 
611 	sq->head++;
612 	sq->head &= (sq->sqe_cnt - 1);
613 }
614 
615 #define MAX_SEGS_PER_SG	3
616 /* Add SQE scatter/gather subdescriptor structure */
otx2_sqe_add_sg(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct sk_buff * skb,int num_segs,int * offset)617 static bool otx2_sqe_add_sg(struct otx2_nic *pfvf, struct otx2_snd_queue *sq,
618 			    struct sk_buff *skb, int num_segs, int *offset)
619 {
620 	struct nix_sqe_sg_s *sg = NULL;
621 	u64 dma_addr, *iova = NULL;
622 	u16 *sg_lens = NULL;
623 	int seg, len;
624 
625 	sq->sg[sq->head].num_segs = 0;
626 
627 	for (seg = 0; seg < num_segs; seg++) {
628 		if ((seg % MAX_SEGS_PER_SG) == 0) {
629 			sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset);
630 			sg->ld_type = NIX_SEND_LDTYPE_LDD;
631 			sg->subdc = NIX_SUBDC_SG;
632 			sg->segs = 0;
633 			sg_lens = (void *)sg;
634 			iova = (void *)sg + sizeof(*sg);
635 			/* Next subdc always starts at a 16byte boundary.
636 			 * So if sg->segs is whether 2 or 3, offset += 16bytes.
637 			 */
638 			if ((num_segs - seg) >= (MAX_SEGS_PER_SG - 1))
639 				*offset += sizeof(*sg) + (3 * sizeof(u64));
640 			else
641 				*offset += sizeof(*sg) + sizeof(u64);
642 		}
643 		dma_addr = otx2_dma_map_skb_frag(pfvf, skb, seg, &len);
644 		if (dma_mapping_error(pfvf->dev, dma_addr))
645 			return false;
646 
647 		sg_lens[frag_num(seg % MAX_SEGS_PER_SG)] = len;
648 		sg->segs++;
649 		*iova++ = dma_addr;
650 
651 		/* Save DMA mapping info for later unmapping */
652 		sq->sg[sq->head].dma_addr[seg] = dma_addr;
653 		sq->sg[sq->head].size[seg] = len;
654 		sq->sg[sq->head].num_segs++;
655 	}
656 
657 	sq->sg[sq->head].skb = (u64)skb;
658 	return true;
659 }
660 
661 /* Add SQE extended header subdescriptor */
otx2_sqe_add_ext(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct sk_buff * skb,int * offset)662 static void otx2_sqe_add_ext(struct otx2_nic *pfvf, struct otx2_snd_queue *sq,
663 			     struct sk_buff *skb, int *offset)
664 {
665 	struct nix_sqe_ext_s *ext;
666 
667 	ext = (struct nix_sqe_ext_s *)(sq->sqe_base + *offset);
668 	ext->subdc = NIX_SUBDC_EXT;
669 	if (skb_shinfo(skb)->gso_size) {
670 		ext->lso = 1;
671 		ext->lso_sb = skb_tcp_all_headers(skb);
672 		ext->lso_mps = skb_shinfo(skb)->gso_size;
673 
674 		/* Only TSOv4 and TSOv6 GSO offloads are supported */
675 		if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4) {
676 			ext->lso_format = pfvf->hw.lso_tsov4_idx;
677 
678 			/* HW adds payload size to 'ip_hdr->tot_len' while
679 			 * sending TSO segment, hence set payload length
680 			 * in IP header of the packet to just header length.
681 			 */
682 			ip_hdr(skb)->tot_len =
683 				htons(ext->lso_sb - skb_network_offset(skb));
684 		} else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
685 			ext->lso_format = pfvf->hw.lso_tsov6_idx;
686 			ipv6_hdr(skb)->payload_len = htons(tcp_hdrlen(skb));
687 		} else if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) {
688 			__be16 l3_proto = vlan_get_protocol(skb);
689 			struct udphdr *udph = udp_hdr(skb);
690 			__be16 iplen;
691 
692 			ext->lso_sb = skb_transport_offset(skb) +
693 					sizeof(struct udphdr);
694 
695 			/* HW adds payload size to length fields in IP and
696 			 * UDP headers while segmentation, hence adjust the
697 			 * lengths to just header sizes.
698 			 */
699 			iplen = htons(ext->lso_sb - skb_network_offset(skb));
700 			if (l3_proto == htons(ETH_P_IP)) {
701 				ip_hdr(skb)->tot_len = iplen;
702 				ext->lso_format = pfvf->hw.lso_udpv4_idx;
703 			} else {
704 				ipv6_hdr(skb)->payload_len = iplen;
705 				ext->lso_format = pfvf->hw.lso_udpv6_idx;
706 			}
707 
708 			udph->len = htons(sizeof(struct udphdr));
709 		}
710 	} else if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
711 		ext->tstmp = 1;
712 	}
713 
714 #define OTX2_VLAN_PTR_OFFSET     (ETH_HLEN - ETH_TLEN)
715 	if (skb_vlan_tag_present(skb)) {
716 		if (skb->vlan_proto == htons(ETH_P_8021Q)) {
717 			ext->vlan1_ins_ena = 1;
718 			ext->vlan1_ins_ptr = OTX2_VLAN_PTR_OFFSET;
719 			ext->vlan1_ins_tci = skb_vlan_tag_get(skb);
720 		} else if (skb->vlan_proto == htons(ETH_P_8021AD)) {
721 			ext->vlan0_ins_ena = 1;
722 			ext->vlan0_ins_ptr = OTX2_VLAN_PTR_OFFSET;
723 			ext->vlan0_ins_tci = skb_vlan_tag_get(skb);
724 		}
725 	}
726 
727 	*offset += sizeof(*ext);
728 }
729 
otx2_sqe_add_mem(struct otx2_snd_queue * sq,int * offset,int alg,u64 iova,int ptp_offset,u64 base_ns,bool udp_csum_crt)730 static void otx2_sqe_add_mem(struct otx2_snd_queue *sq, int *offset,
731 			     int alg, u64 iova, int ptp_offset,
732 			     u64 base_ns, bool udp_csum_crt)
733 {
734 	struct nix_sqe_mem_s *mem;
735 
736 	mem = (struct nix_sqe_mem_s *)(sq->sqe_base + *offset);
737 	mem->subdc = NIX_SUBDC_MEM;
738 	mem->alg = alg;
739 	mem->wmem = 1; /* wait for the memory operation */
740 	mem->addr = iova;
741 
742 	if (ptp_offset) {
743 		mem->start_offset = ptp_offset;
744 		mem->udp_csum_crt = !!udp_csum_crt;
745 		mem->base_ns = base_ns;
746 		mem->step_type = 1;
747 	}
748 
749 	*offset += sizeof(*mem);
750 }
751 
752 /* Add SQE header subdescriptor structure */
otx2_sqe_add_hdr(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct nix_sqe_hdr_s * sqe_hdr,struct sk_buff * skb,u16 qidx)753 static void otx2_sqe_add_hdr(struct otx2_nic *pfvf, struct otx2_snd_queue *sq,
754 			     struct nix_sqe_hdr_s *sqe_hdr,
755 			     struct sk_buff *skb, u16 qidx)
756 {
757 	int proto = 0;
758 
759 	/* Check if SQE was framed before, if yes then no need to
760 	 * set these constants again and again.
761 	 */
762 	if (!sqe_hdr->total) {
763 		/* Don't free Tx buffers to Aura */
764 		sqe_hdr->df = 1;
765 		sqe_hdr->aura = sq->aura_id;
766 		/* Post a CQE Tx after pkt transmission */
767 		sqe_hdr->pnc = 1;
768 		sqe_hdr->sq = (qidx >=  pfvf->hw.tx_queues) ?
769 			       qidx + pfvf->hw.xdp_queues : qidx;
770 	}
771 	sqe_hdr->total = skb->len;
772 	/* Set SQE identifier which will be used later for freeing SKB */
773 	sqe_hdr->sqe_id = sq->head;
774 
775 	/* Offload TCP/UDP checksum to HW */
776 	if (skb->ip_summed == CHECKSUM_PARTIAL) {
777 		sqe_hdr->ol3ptr = skb_network_offset(skb);
778 		sqe_hdr->ol4ptr = skb_transport_offset(skb);
779 		/* get vlan protocol Ethertype */
780 		if (eth_type_vlan(skb->protocol))
781 			skb->protocol = vlan_get_protocol(skb);
782 
783 		if (skb->protocol == htons(ETH_P_IP)) {
784 			proto = ip_hdr(skb)->protocol;
785 			/* In case of TSO, HW needs this to be explicitly set.
786 			 * So set this always, instead of adding a check.
787 			 */
788 			sqe_hdr->ol3type = NIX_SENDL3TYPE_IP4_CKSUM;
789 		} else if (skb->protocol == htons(ETH_P_IPV6)) {
790 			proto = ipv6_hdr(skb)->nexthdr;
791 			sqe_hdr->ol3type = NIX_SENDL3TYPE_IP6;
792 		}
793 
794 		if (proto == IPPROTO_TCP)
795 			sqe_hdr->ol4type = NIX_SENDL4TYPE_TCP_CKSUM;
796 		else if (proto == IPPROTO_UDP)
797 			sqe_hdr->ol4type = NIX_SENDL4TYPE_UDP_CKSUM;
798 	}
799 }
800 
otx2_dma_map_tso_skb(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct sk_buff * skb,int sqe,int hdr_len)801 static int otx2_dma_map_tso_skb(struct otx2_nic *pfvf,
802 				struct otx2_snd_queue *sq,
803 				struct sk_buff *skb, int sqe, int hdr_len)
804 {
805 	int num_segs = skb_shinfo(skb)->nr_frags + 1;
806 	struct sg_list *sg = &sq->sg[sqe];
807 	u64 dma_addr;
808 	int seg, len;
809 
810 	sg->num_segs = 0;
811 
812 	/* Get payload length at skb->data */
813 	len = skb_headlen(skb) - hdr_len;
814 
815 	for (seg = 0; seg < num_segs; seg++) {
816 		/* Skip skb->data, if there is no payload */
817 		if (!seg && !len)
818 			continue;
819 		dma_addr = otx2_dma_map_skb_frag(pfvf, skb, seg, &len);
820 		if (dma_mapping_error(pfvf->dev, dma_addr))
821 			goto unmap;
822 
823 		/* Save DMA mapping info for later unmapping */
824 		sg->dma_addr[sg->num_segs] = dma_addr;
825 		sg->size[sg->num_segs] = len;
826 		sg->num_segs++;
827 	}
828 	return 0;
829 unmap:
830 	otx2_dma_unmap_skb_frags(pfvf, sg);
831 	return -EINVAL;
832 }
833 
otx2_tso_frag_dma_addr(struct otx2_snd_queue * sq,struct sk_buff * skb,int seg,u64 seg_addr,int hdr_len,int sqe)834 static u64 otx2_tso_frag_dma_addr(struct otx2_snd_queue *sq,
835 				  struct sk_buff *skb, int seg,
836 				  u64 seg_addr, int hdr_len, int sqe)
837 {
838 	struct sg_list *sg = &sq->sg[sqe];
839 	const skb_frag_t *frag;
840 	int offset;
841 
842 	if (seg < 0)
843 		return sg->dma_addr[0] + (seg_addr - (u64)skb->data);
844 
845 	frag = &skb_shinfo(skb)->frags[seg];
846 	offset = seg_addr - (u64)skb_frag_address(frag);
847 	if (skb_headlen(skb) - hdr_len)
848 		seg++;
849 	return sg->dma_addr[seg] + offset;
850 }
851 
otx2_sqe_tso_add_sg(struct otx2_snd_queue * sq,struct sg_list * list,int * offset)852 static void otx2_sqe_tso_add_sg(struct otx2_snd_queue *sq,
853 				struct sg_list *list, int *offset)
854 {
855 	struct nix_sqe_sg_s *sg = NULL;
856 	u16 *sg_lens = NULL;
857 	u64 *iova = NULL;
858 	int seg;
859 
860 	/* Add SG descriptors with buffer addresses */
861 	for (seg = 0; seg < list->num_segs; seg++) {
862 		if ((seg % MAX_SEGS_PER_SG) == 0) {
863 			sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset);
864 			sg->ld_type = NIX_SEND_LDTYPE_LDD;
865 			sg->subdc = NIX_SUBDC_SG;
866 			sg->segs = 0;
867 			sg_lens = (void *)sg;
868 			iova = (void *)sg + sizeof(*sg);
869 			/* Next subdc always starts at a 16byte boundary.
870 			 * So if sg->segs is whether 2 or 3, offset += 16bytes.
871 			 */
872 			if ((list->num_segs - seg) >= (MAX_SEGS_PER_SG - 1))
873 				*offset += sizeof(*sg) + (3 * sizeof(u64));
874 			else
875 				*offset += sizeof(*sg) + sizeof(u64);
876 		}
877 		sg_lens[frag_num(seg % MAX_SEGS_PER_SG)] = list->size[seg];
878 		*iova++ = list->dma_addr[seg];
879 		sg->segs++;
880 	}
881 }
882 
otx2_sq_append_tso(struct otx2_nic * pfvf,struct otx2_snd_queue * sq,struct sk_buff * skb,u16 qidx)883 static void otx2_sq_append_tso(struct otx2_nic *pfvf, struct otx2_snd_queue *sq,
884 			       struct sk_buff *skb, u16 qidx)
885 {
886 	struct netdev_queue *txq = netdev_get_tx_queue(pfvf->netdev, qidx);
887 	int hdr_len, tcp_data, seg_len, pkt_len, offset;
888 	struct nix_sqe_hdr_s *sqe_hdr;
889 	int first_sqe = sq->head;
890 	struct sg_list list;
891 	struct tso_t tso;
892 
893 	hdr_len = tso_start(skb, &tso);
894 
895 	/* Map SKB's fragments to DMA.
896 	 * It's done here to avoid mapping for every TSO segment's packet.
897 	 */
898 	if (otx2_dma_map_tso_skb(pfvf, sq, skb, first_sqe, hdr_len)) {
899 		dev_kfree_skb_any(skb);
900 		return;
901 	}
902 
903 	netdev_tx_sent_queue(txq, skb->len);
904 
905 	tcp_data = skb->len - hdr_len;
906 	while (tcp_data > 0) {
907 		char *hdr;
908 
909 		seg_len = min_t(int, skb_shinfo(skb)->gso_size, tcp_data);
910 		tcp_data -= seg_len;
911 
912 		/* Set SQE's SEND_HDR */
913 		memset(sq->sqe_base, 0, sq->sqe_size);
914 		sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base);
915 		otx2_sqe_add_hdr(pfvf, sq, sqe_hdr, skb, qidx);
916 		offset = sizeof(*sqe_hdr);
917 
918 		/* Add TSO segment's pkt header */
919 		hdr = sq->tso_hdrs->base + (sq->head * TSO_HEADER_SIZE);
920 		tso_build_hdr(skb, hdr, &tso, seg_len, tcp_data == 0);
921 		list.dma_addr[0] =
922 			sq->tso_hdrs->iova + (sq->head * TSO_HEADER_SIZE);
923 		list.size[0] = hdr_len;
924 		list.num_segs = 1;
925 
926 		/* Add TSO segment's payload data fragments */
927 		pkt_len = hdr_len;
928 		while (seg_len > 0) {
929 			int size;
930 
931 			size = min_t(int, tso.size, seg_len);
932 
933 			list.size[list.num_segs] = size;
934 			list.dma_addr[list.num_segs] =
935 				otx2_tso_frag_dma_addr(sq, skb,
936 						       tso.next_frag_idx - 1,
937 						       (u64)tso.data, hdr_len,
938 						       first_sqe);
939 			list.num_segs++;
940 			pkt_len += size;
941 			seg_len -= size;
942 			tso_build_data(skb, &tso, size);
943 		}
944 		sqe_hdr->total = pkt_len;
945 		otx2_sqe_tso_add_sg(sq, &list, &offset);
946 
947 		/* DMA mappings and skb needs to be freed only after last
948 		 * TSO segment is transmitted out. So set 'PNC' only for
949 		 * last segment. Also point last segment's sqe_id to first
950 		 * segment's SQE index where skb address and DMA mappings
951 		 * are saved.
952 		 */
953 		if (!tcp_data) {
954 			sqe_hdr->pnc = 1;
955 			sqe_hdr->sqe_id = first_sqe;
956 			sq->sg[first_sqe].skb = (u64)skb;
957 		} else {
958 			sqe_hdr->pnc = 0;
959 		}
960 
961 		sqe_hdr->sizem1 = (offset / 16) - 1;
962 
963 		/* Flush SQE to HW */
964 		pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx);
965 	}
966 }
967 
is_hw_tso_supported(struct otx2_nic * pfvf,struct sk_buff * skb)968 static bool is_hw_tso_supported(struct otx2_nic *pfvf,
969 				struct sk_buff *skb)
970 {
971 	int payload_len, last_seg_size;
972 
973 	if (test_bit(HW_TSO, &pfvf->hw.cap_flag))
974 		return true;
975 
976 	/* On 96xx A0, HW TSO not supported */
977 	if (!is_96xx_B0(pfvf->pdev))
978 		return false;
979 
980 	/* HW has an issue due to which when the payload of the last LSO
981 	 * segment is shorter than 16 bytes, some header fields may not
982 	 * be correctly modified, hence don't offload such TSO segments.
983 	 */
984 
985 	payload_len = skb->len - skb_tcp_all_headers(skb);
986 	last_seg_size = payload_len % skb_shinfo(skb)->gso_size;
987 	if (last_seg_size && last_seg_size < 16)
988 		return false;
989 
990 	return true;
991 }
992 
otx2_get_sqe_count(struct otx2_nic * pfvf,struct sk_buff * skb)993 static int otx2_get_sqe_count(struct otx2_nic *pfvf, struct sk_buff *skb)
994 {
995 	if (!skb_shinfo(skb)->gso_size)
996 		return 1;
997 
998 	/* HW TSO */
999 	if (is_hw_tso_supported(pfvf, skb))
1000 		return 1;
1001 
1002 	/* SW TSO */
1003 	return skb_shinfo(skb)->gso_segs;
1004 }
1005 
otx2_validate_network_transport(struct sk_buff * skb)1006 static bool otx2_validate_network_transport(struct sk_buff *skb)
1007 {
1008 	if ((ip_hdr(skb)->protocol == IPPROTO_UDP) ||
1009 	    (ipv6_hdr(skb)->nexthdr == IPPROTO_UDP)) {
1010 		struct udphdr *udph = udp_hdr(skb);
1011 
1012 		if (udph->source == htons(PTP_PORT) &&
1013 		    udph->dest == htons(PTP_PORT))
1014 			return true;
1015 	}
1016 
1017 	return false;
1018 }
1019 
otx2_ptp_is_sync(struct sk_buff * skb,int * offset,bool * udp_csum_crt)1020 static bool otx2_ptp_is_sync(struct sk_buff *skb, int *offset, bool *udp_csum_crt)
1021 {
1022 	struct ethhdr *eth = (struct ethhdr *)(skb->data);
1023 	u16 nix_offload_hlen = 0, inner_vhlen = 0;
1024 	bool udp_hdr_present = false, is_sync;
1025 	u8 *data = skb->data, *msgtype;
1026 	__be16 proto = eth->h_proto;
1027 	int network_depth = 0;
1028 
1029 	/* NIX is programmed to offload outer  VLAN header
1030 	 * in case of single vlan protocol field holds Network header ETH_IP/V6
1031 	 * in case of stacked vlan protocol field holds Inner vlan (8100)
1032 	 */
1033 	if (skb->dev->features & NETIF_F_HW_VLAN_CTAG_TX &&
1034 	    skb->dev->features & NETIF_F_HW_VLAN_STAG_TX) {
1035 		if (skb->vlan_proto == htons(ETH_P_8021AD)) {
1036 			/* Get vlan protocol */
1037 			proto = __vlan_get_protocol(skb, eth->h_proto, NULL);
1038 			/* SKB APIs like skb_transport_offset does not include
1039 			 * offloaded vlan header length. Need to explicitly add
1040 			 * the length
1041 			 */
1042 			nix_offload_hlen = VLAN_HLEN;
1043 			inner_vhlen = VLAN_HLEN;
1044 		} else if (skb->vlan_proto == htons(ETH_P_8021Q)) {
1045 			nix_offload_hlen = VLAN_HLEN;
1046 		}
1047 	} else if (eth_type_vlan(eth->h_proto)) {
1048 		proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
1049 	}
1050 
1051 	switch (ntohs(proto)) {
1052 	case ETH_P_1588:
1053 		if (network_depth)
1054 			*offset = network_depth;
1055 		else
1056 			*offset = ETH_HLEN + nix_offload_hlen +
1057 				  inner_vhlen;
1058 		break;
1059 	case ETH_P_IP:
1060 	case ETH_P_IPV6:
1061 		if (!otx2_validate_network_transport(skb))
1062 			return false;
1063 
1064 		*offset = nix_offload_hlen + skb_transport_offset(skb) +
1065 			  sizeof(struct udphdr);
1066 		udp_hdr_present = true;
1067 
1068 	}
1069 
1070 	msgtype = data + *offset;
1071 	/* Check PTP messageId is SYNC or not */
1072 	is_sync = !(*msgtype & 0xf);
1073 	if (is_sync)
1074 		*udp_csum_crt = udp_hdr_present;
1075 	else
1076 		*offset = 0;
1077 
1078 	return is_sync;
1079 }
1080 
otx2_set_txtstamp(struct otx2_nic * pfvf,struct sk_buff * skb,struct otx2_snd_queue * sq,int * offset)1081 static void otx2_set_txtstamp(struct otx2_nic *pfvf, struct sk_buff *skb,
1082 			      struct otx2_snd_queue *sq, int *offset)
1083 {
1084 	struct ethhdr	*eth = (struct ethhdr *)(skb->data);
1085 	struct ptpv2_tstamp *origin_tstamp;
1086 	bool udp_csum_crt = false;
1087 	unsigned int udphoff;
1088 	struct timespec64 ts;
1089 	int ptp_offset = 0;
1090 	__wsum skb_csum;
1091 	u64 iova;
1092 
1093 	if (unlikely(!skb_shinfo(skb)->gso_size &&
1094 		     (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) {
1095 		if (unlikely(pfvf->flags & OTX2_FLAG_PTP_ONESTEP_SYNC &&
1096 			     otx2_ptp_is_sync(skb, &ptp_offset, &udp_csum_crt))) {
1097 			origin_tstamp = (struct ptpv2_tstamp *)
1098 					((u8 *)skb->data + ptp_offset +
1099 					 PTP_SYNC_SEC_OFFSET);
1100 			ts = ns_to_timespec64(pfvf->ptp->tstamp);
1101 			origin_tstamp->seconds_msb = htons((ts.tv_sec >> 32) & 0xffff);
1102 			origin_tstamp->seconds_lsb = htonl(ts.tv_sec & 0xffffffff);
1103 			origin_tstamp->nanoseconds = htonl(ts.tv_nsec);
1104 			/* Point to correction field in PTP packet */
1105 			ptp_offset += 8;
1106 
1107 			/* When user disables hw checksum, stack calculates the csum,
1108 			 * but it does not cover ptp timestamp which is added later.
1109 			 * Recalculate the checksum manually considering the timestamp.
1110 			 */
1111 			if (udp_csum_crt) {
1112 				struct udphdr *uh = udp_hdr(skb);
1113 
1114 				if (skb->ip_summed != CHECKSUM_PARTIAL && uh->check != 0) {
1115 					udphoff = skb_transport_offset(skb);
1116 					uh->check = 0;
1117 					skb_csum = skb_checksum(skb, udphoff, skb->len - udphoff,
1118 								0);
1119 					if (ntohs(eth->h_proto) == ETH_P_IPV6)
1120 						uh->check = csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
1121 									    &ipv6_hdr(skb)->daddr,
1122 									    skb->len - udphoff,
1123 									    ipv6_hdr(skb)->nexthdr,
1124 									    skb_csum);
1125 					else
1126 						uh->check = csum_tcpudp_magic(ip_hdr(skb)->saddr,
1127 									      ip_hdr(skb)->daddr,
1128 									      skb->len - udphoff,
1129 									      IPPROTO_UDP,
1130 									      skb_csum);
1131 				}
1132 			}
1133 		} else {
1134 			skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1135 		}
1136 		iova = sq->timestamps->iova + (sq->head * sizeof(u64));
1137 		otx2_sqe_add_mem(sq, offset, NIX_SENDMEMALG_E_SETTSTMP, iova,
1138 				 ptp_offset, pfvf->ptp->base_ns, udp_csum_crt);
1139 	} else {
1140 		skb_tx_timestamp(skb);
1141 	}
1142 }
1143 
otx2_sq_append_skb(struct net_device * netdev,struct otx2_snd_queue * sq,struct sk_buff * skb,u16 qidx)1144 bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq,
1145 			struct sk_buff *skb, u16 qidx)
1146 {
1147 	struct netdev_queue *txq = netdev_get_tx_queue(netdev, qidx);
1148 	struct otx2_nic *pfvf = netdev_priv(netdev);
1149 	int offset, num_segs, free_desc;
1150 	struct nix_sqe_hdr_s *sqe_hdr;
1151 
1152 	/* Check if there is enough room between producer
1153 	 * and consumer index.
1154 	 */
1155 	free_desc = (sq->cons_head - sq->head - 1 + sq->sqe_cnt) & (sq->sqe_cnt - 1);
1156 	if (free_desc < sq->sqe_thresh)
1157 		return false;
1158 
1159 	if (free_desc < otx2_get_sqe_count(pfvf, skb))
1160 		return false;
1161 
1162 	num_segs = skb_shinfo(skb)->nr_frags + 1;
1163 
1164 	/* If SKB doesn't fit in a single SQE, linearize it.
1165 	 * TODO: Consider adding JUMP descriptor instead.
1166 	 */
1167 	if (unlikely(num_segs > OTX2_MAX_FRAGS_IN_SQE)) {
1168 		if (__skb_linearize(skb)) {
1169 			dev_kfree_skb_any(skb);
1170 			return true;
1171 		}
1172 		num_segs = skb_shinfo(skb)->nr_frags + 1;
1173 	}
1174 
1175 	if (skb_shinfo(skb)->gso_size && !is_hw_tso_supported(pfvf, skb)) {
1176 		/* Insert vlan tag before giving pkt to tso */
1177 		if (skb_vlan_tag_present(skb)) {
1178 			skb = __vlan_hwaccel_push_inside(skb);
1179 			if (!skb)
1180 				return true;
1181 		}
1182 		otx2_sq_append_tso(pfvf, sq, skb, qidx);
1183 		return true;
1184 	}
1185 
1186 	/* Set SQE's SEND_HDR.
1187 	 * Do not clear the first 64bit as it contains constant info.
1188 	 */
1189 	memset(sq->sqe_base + 8, 0, sq->sqe_size - 8);
1190 	sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base);
1191 	otx2_sqe_add_hdr(pfvf, sq, sqe_hdr, skb, qidx);
1192 	offset = sizeof(*sqe_hdr);
1193 
1194 	/* Add extended header if needed */
1195 	otx2_sqe_add_ext(pfvf, sq, skb, &offset);
1196 
1197 	/* Add SG subdesc with data frags */
1198 	if (!otx2_sqe_add_sg(pfvf, sq, skb, num_segs, &offset)) {
1199 		otx2_dma_unmap_skb_frags(pfvf, &sq->sg[sq->head]);
1200 		return false;
1201 	}
1202 
1203 	otx2_set_txtstamp(pfvf, skb, sq, &offset);
1204 
1205 	sqe_hdr->sizem1 = (offset / 16) - 1;
1206 
1207 	netdev_tx_sent_queue(txq, skb->len);
1208 
1209 	/* Flush SQE to HW */
1210 	pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx);
1211 
1212 	return true;
1213 }
1214 EXPORT_SYMBOL(otx2_sq_append_skb);
1215 
otx2_cleanup_rx_cqes(struct otx2_nic * pfvf,struct otx2_cq_queue * cq,int qidx)1216 void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, int qidx)
1217 {
1218 	struct nix_cqe_rx_s *cqe;
1219 	struct otx2_pool *pool;
1220 	int processed_cqe = 0;
1221 	u16 pool_id;
1222 	u64 iova;
1223 
1224 	if (pfvf->xdp_prog)
1225 		xdp_rxq_info_unreg(&cq->xdp_rxq);
1226 
1227 	if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe)
1228 		return;
1229 
1230 	pool_id = otx2_get_pool_idx(pfvf, AURA_NIX_RQ, qidx);
1231 	pool = &pfvf->qset.pool[pool_id];
1232 
1233 	while (cq->pend_cqe) {
1234 		cqe = (struct nix_cqe_rx_s *)otx2_get_next_cqe(cq);
1235 		processed_cqe++;
1236 		cq->pend_cqe--;
1237 
1238 		if (!cqe)
1239 			continue;
1240 		if (cqe->sg.segs > 1) {
1241 			otx2_free_rcv_seg(pfvf, cqe, cq->cq_idx);
1242 			continue;
1243 		}
1244 		iova = cqe->sg.seg_addr - OTX2_HEAD_ROOM;
1245 
1246 		otx2_free_bufs(pfvf, pool, iova, pfvf->rbsize);
1247 	}
1248 
1249 	/* Free CQEs to HW */
1250 	otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR,
1251 		     ((u64)cq->cq_idx << 32) | processed_cqe);
1252 }
1253 
otx2_cleanup_tx_cqes(struct otx2_nic * pfvf,struct otx2_cq_queue * cq)1254 void otx2_cleanup_tx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq)
1255 {
1256 	int tx_pkts = 0, tx_bytes = 0;
1257 	struct sk_buff *skb = NULL;
1258 	struct otx2_snd_queue *sq;
1259 	struct nix_cqe_tx_s *cqe;
1260 	struct netdev_queue *txq;
1261 	int processed_cqe = 0;
1262 	struct sg_list *sg;
1263 	int qidx;
1264 
1265 	qidx = cq->cq_idx - pfvf->hw.rx_queues;
1266 	sq = &pfvf->qset.sq[qidx];
1267 
1268 	if (otx2_nix_cq_op_status(pfvf, cq) || !cq->pend_cqe)
1269 		return;
1270 
1271 	while (cq->pend_cqe) {
1272 		cqe = (struct nix_cqe_tx_s *)otx2_get_next_cqe(cq);
1273 		processed_cqe++;
1274 		cq->pend_cqe--;
1275 
1276 		if (!cqe)
1277 			continue;
1278 		sg = &sq->sg[cqe->comp.sqe_id];
1279 		skb = (struct sk_buff *)sg->skb;
1280 		if (skb) {
1281 			tx_bytes += skb->len;
1282 			tx_pkts++;
1283 			otx2_dma_unmap_skb_frags(pfvf, sg);
1284 			dev_kfree_skb_any(skb);
1285 			sg->skb = (u64)NULL;
1286 		}
1287 	}
1288 
1289 	if (likely(tx_pkts)) {
1290 		if (qidx >= pfvf->hw.tx_queues)
1291 			qidx -= pfvf->hw.xdp_queues;
1292 		txq = netdev_get_tx_queue(pfvf->netdev, qidx);
1293 		netdev_tx_completed_queue(txq, tx_pkts, tx_bytes);
1294 	}
1295 	/* Free CQEs to HW */
1296 	otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR,
1297 		     ((u64)cq->cq_idx << 32) | processed_cqe);
1298 }
1299 
otx2_rxtx_enable(struct otx2_nic * pfvf,bool enable)1300 int otx2_rxtx_enable(struct otx2_nic *pfvf, bool enable)
1301 {
1302 	struct msg_req *msg;
1303 	int err;
1304 
1305 	mutex_lock(&pfvf->mbox.lock);
1306 	if (enable)
1307 		msg = otx2_mbox_alloc_msg_nix_lf_start_rx(&pfvf->mbox);
1308 	else
1309 		msg = otx2_mbox_alloc_msg_nix_lf_stop_rx(&pfvf->mbox);
1310 
1311 	if (!msg) {
1312 		mutex_unlock(&pfvf->mbox.lock);
1313 		return -ENOMEM;
1314 	}
1315 
1316 	err = otx2_sync_mbox_msg(&pfvf->mbox);
1317 	mutex_unlock(&pfvf->mbox.lock);
1318 	return err;
1319 }
1320 
otx2_free_pending_sqe(struct otx2_nic * pfvf)1321 void otx2_free_pending_sqe(struct otx2_nic *pfvf)
1322 {
1323 	int tx_pkts = 0, tx_bytes = 0;
1324 	struct sk_buff *skb = NULL;
1325 	struct otx2_snd_queue *sq;
1326 	struct netdev_queue *txq;
1327 	struct sg_list *sg;
1328 	int sq_idx, sqe;
1329 
1330 	for (sq_idx = 0; sq_idx < pfvf->hw.tx_queues; sq_idx++) {
1331 		sq = &pfvf->qset.sq[sq_idx];
1332 		for (sqe = 0; sqe < sq->sqe_cnt; sqe++) {
1333 			sg = &sq->sg[sqe];
1334 			skb = (struct sk_buff *)sg->skb;
1335 			if (skb) {
1336 				tx_bytes += skb->len;
1337 				tx_pkts++;
1338 				otx2_dma_unmap_skb_frags(pfvf, sg);
1339 				dev_kfree_skb_any(skb);
1340 				sg->skb = (u64)NULL;
1341 			}
1342 		}
1343 
1344 		if (!tx_pkts)
1345 			continue;
1346 		txq = netdev_get_tx_queue(pfvf->netdev, sq_idx);
1347 		netdev_tx_completed_queue(txq, tx_pkts, tx_bytes);
1348 		tx_pkts = 0;
1349 		tx_bytes = 0;
1350 	}
1351 }
1352 
otx2_xdp_sqe_add_sg(struct otx2_snd_queue * sq,u64 dma_addr,int len,int * offset)1353 static void otx2_xdp_sqe_add_sg(struct otx2_snd_queue *sq, u64 dma_addr,
1354 				int len, int *offset)
1355 {
1356 	struct nix_sqe_sg_s *sg = NULL;
1357 	u64 *iova = NULL;
1358 
1359 	sg = (struct nix_sqe_sg_s *)(sq->sqe_base + *offset);
1360 	sg->ld_type = NIX_SEND_LDTYPE_LDD;
1361 	sg->subdc = NIX_SUBDC_SG;
1362 	sg->segs = 1;
1363 	sg->seg1_size = len;
1364 	iova = (void *)sg + sizeof(*sg);
1365 	*iova = dma_addr;
1366 	*offset += sizeof(*sg) + sizeof(u64);
1367 
1368 	sq->sg[sq->head].dma_addr[0] = dma_addr;
1369 	sq->sg[sq->head].size[0] = len;
1370 	sq->sg[sq->head].num_segs = 1;
1371 }
1372 
otx2_xdp_sq_append_pkt(struct otx2_nic * pfvf,u64 iova,int len,u16 qidx)1373 bool otx2_xdp_sq_append_pkt(struct otx2_nic *pfvf, u64 iova, int len, u16 qidx)
1374 {
1375 	struct nix_sqe_hdr_s *sqe_hdr;
1376 	struct otx2_snd_queue *sq;
1377 	int offset, free_sqe;
1378 
1379 	sq = &pfvf->qset.sq[qidx];
1380 	free_sqe = (sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb;
1381 	if (free_sqe < sq->sqe_thresh)
1382 		return false;
1383 
1384 	memset(sq->sqe_base + 8, 0, sq->sqe_size - 8);
1385 
1386 	sqe_hdr = (struct nix_sqe_hdr_s *)(sq->sqe_base);
1387 
1388 	if (!sqe_hdr->total) {
1389 		sqe_hdr->aura = sq->aura_id;
1390 		sqe_hdr->df = 1;
1391 		sqe_hdr->sq = qidx;
1392 		sqe_hdr->pnc = 1;
1393 	}
1394 	sqe_hdr->total = len;
1395 	sqe_hdr->sqe_id = sq->head;
1396 
1397 	offset = sizeof(*sqe_hdr);
1398 
1399 	otx2_xdp_sqe_add_sg(sq, iova, len, &offset);
1400 	sqe_hdr->sizem1 = (offset / 16) - 1;
1401 	pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx);
1402 
1403 	return true;
1404 }
1405 
otx2_xdp_rcv_pkt_handler(struct otx2_nic * pfvf,struct bpf_prog * prog,struct nix_cqe_rx_s * cqe,struct otx2_cq_queue * cq,bool * need_xdp_flush)1406 static bool otx2_xdp_rcv_pkt_handler(struct otx2_nic *pfvf,
1407 				     struct bpf_prog *prog,
1408 				     struct nix_cqe_rx_s *cqe,
1409 				     struct otx2_cq_queue *cq,
1410 				     bool *need_xdp_flush)
1411 {
1412 	unsigned char *hard_start;
1413 	int qidx = cq->cq_idx;
1414 	struct xdp_buff xdp;
1415 	struct page *page;
1416 	u64 iova, pa;
1417 	u32 act;
1418 	int err;
1419 
1420 	iova = cqe->sg.seg_addr - OTX2_HEAD_ROOM;
1421 	pa = otx2_iova_to_phys(pfvf->iommu_domain, iova);
1422 	page = virt_to_page(phys_to_virt(pa));
1423 
1424 	xdp_init_buff(&xdp, pfvf->rbsize, &cq->xdp_rxq);
1425 
1426 	hard_start = (unsigned char *)phys_to_virt(pa);
1427 	xdp_prepare_buff(&xdp, hard_start, OTX2_HEAD_ROOM,
1428 			 cqe->sg.seg_size, false);
1429 
1430 	act = bpf_prog_run_xdp(prog, &xdp);
1431 
1432 	switch (act) {
1433 	case XDP_PASS:
1434 		break;
1435 	case XDP_TX:
1436 		qidx += pfvf->hw.tx_queues;
1437 		cq->pool_ptrs++;
1438 		return otx2_xdp_sq_append_pkt(pfvf, iova,
1439 					      cqe->sg.seg_size, qidx);
1440 	case XDP_REDIRECT:
1441 		cq->pool_ptrs++;
1442 		err = xdp_do_redirect(pfvf->netdev, &xdp, prog);
1443 
1444 		otx2_dma_unmap_page(pfvf, iova, pfvf->rbsize,
1445 				    DMA_FROM_DEVICE);
1446 		if (!err) {
1447 			*need_xdp_flush = true;
1448 			return true;
1449 		}
1450 		put_page(page);
1451 		break;
1452 	default:
1453 		bpf_warn_invalid_xdp_action(pfvf->netdev, prog, act);
1454 		break;
1455 	case XDP_ABORTED:
1456 		trace_xdp_exception(pfvf->netdev, prog, act);
1457 		break;
1458 	case XDP_DROP:
1459 		otx2_dma_unmap_page(pfvf, iova, pfvf->rbsize,
1460 				    DMA_FROM_DEVICE);
1461 		put_page(page);
1462 		cq->pool_ptrs++;
1463 		return true;
1464 	}
1465 	return false;
1466 }
1467