1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License version 2 as published 4 * by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, write to the Free Software 13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 14 * 15 * Copyright (C) 2011 John Crispin <blogic@openwrt.org> 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/slab.h> 20 #include <linux/errno.h> 21 #include <linux/types.h> 22 #include <linux/interrupt.h> 23 #include <linux/uaccess.h> 24 #include <linux/in.h> 25 #include <linux/netdevice.h> 26 #include <linux/etherdevice.h> 27 #include <linux/phy.h> 28 #include <linux/ip.h> 29 #include <linux/tcp.h> 30 #include <linux/skbuff.h> 31 #include <linux/mm.h> 32 #include <linux/platform_device.h> 33 #include <linux/ethtool.h> 34 #include <linux/init.h> 35 #include <linux/delay.h> 36 #include <linux/io.h> 37 #include <linux/dma-mapping.h> 38 #include <linux/module.h> 39 40 #include <asm/checksum.h> 41 42 #include <lantiq_soc.h> 43 #include <xway_dma.h> 44 #include <lantiq_platform.h> 45 46 #define LTQ_ETOP_MDIO 0x11804 47 #define MDIO_REQUEST 0x80000000 48 #define MDIO_READ 0x40000000 49 #define MDIO_ADDR_MASK 0x1f 50 #define MDIO_ADDR_OFFSET 0x15 51 #define MDIO_REG_MASK 0x1f 52 #define MDIO_REG_OFFSET 0x10 53 #define MDIO_VAL_MASK 0xffff 54 55 #define PPE32_CGEN 0x800 56 #define LQ_PPE32_ENET_MAC_CFG 0x1840 57 58 #define LTQ_ETOP_ENETS0 0x11850 59 #define LTQ_ETOP_MAC_DA0 0x1186C 60 #define LTQ_ETOP_MAC_DA1 0x11870 61 #define LTQ_ETOP_CFG 0x16020 62 #define LTQ_ETOP_IGPLEN 0x16080 63 64 #define MAX_DMA_CHAN 0x8 65 #define MAX_DMA_CRC_LEN 0x4 66 #define MAX_DMA_DATA_LEN 0x600 67 68 #define ETOP_FTCU BIT(28) 69 #define ETOP_MII_MASK 0xf 70 #define ETOP_MII_NORMAL 0xd 71 #define ETOP_MII_REVERSE 0xe 72 #define ETOP_PLEN_UNDER 0x40 73 #define ETOP_CGEN 0x800 74 75 /* use 2 static channels for TX/RX */ 76 #define LTQ_ETOP_TX_CHANNEL 1 77 #define LTQ_ETOP_RX_CHANNEL 6 78 #define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) 79 #define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) 80 81 #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x)) 82 #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y)) 83 #define ltq_etop_w32_mask(x, y, z) \ 84 ltq_w32_mask(x, y, ltq_etop_membase + (z)) 85 86 #define DRV_VERSION "1.0" 87 88 static void __iomem *ltq_etop_membase; 89 90 struct ltq_etop_chan { 91 int idx; 92 int tx_free; 93 struct net_device *netdev; 94 struct napi_struct napi; 95 struct ltq_dma_channel dma; 96 struct sk_buff *skb[LTQ_DESC_NUM]; 97 }; 98 99 struct ltq_etop_priv { 100 struct net_device *netdev; 101 struct platform_device *pdev; 102 struct ltq_eth_data *pldata; 103 struct resource *res; 104 105 struct mii_bus *mii_bus; 106 struct phy_device *phydev; 107 108 struct ltq_etop_chan ch[MAX_DMA_CHAN]; 109 int tx_free[MAX_DMA_CHAN >> 1]; 110 111 spinlock_t lock; 112 }; 113 114 static int 115 ltq_etop_alloc_skb(struct ltq_etop_chan *ch) 116 { 117 ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN); 118 if (!ch->skb[ch->dma.desc]) 119 return -ENOMEM; 120 ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL, 121 ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN, 122 DMA_FROM_DEVICE); 123 ch->dma.desc_base[ch->dma.desc].addr = 124 CPHYSADDR(ch->skb[ch->dma.desc]->data); 125 ch->dma.desc_base[ch->dma.desc].ctl = 126 LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | 127 MAX_DMA_DATA_LEN; 128 skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN); 129 return 0; 130 } 131 132 static void 133 ltq_etop_hw_receive(struct ltq_etop_chan *ch) 134 { 135 struct ltq_etop_priv *priv = netdev_priv(ch->netdev); 136 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 137 struct sk_buff *skb = ch->skb[ch->dma.desc]; 138 int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN; 139 unsigned long flags; 140 141 spin_lock_irqsave(&priv->lock, flags); 142 if (ltq_etop_alloc_skb(ch)) { 143 netdev_err(ch->netdev, 144 "failed to allocate new rx buffer, stopping DMA\n"); 145 ltq_dma_close(&ch->dma); 146 } 147 ch->dma.desc++; 148 ch->dma.desc %= LTQ_DESC_NUM; 149 spin_unlock_irqrestore(&priv->lock, flags); 150 151 skb_put(skb, len); 152 skb->dev = ch->netdev; 153 skb->protocol = eth_type_trans(skb, ch->netdev); 154 netif_receive_skb(skb); 155 } 156 157 static int 158 ltq_etop_poll_rx(struct napi_struct *napi, int budget) 159 { 160 struct ltq_etop_chan *ch = container_of(napi, 161 struct ltq_etop_chan, napi); 162 int rx = 0; 163 int complete = 0; 164 165 while ((rx < budget) && !complete) { 166 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 167 168 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { 169 ltq_etop_hw_receive(ch); 170 rx++; 171 } else { 172 complete = 1; 173 } 174 } 175 if (complete || !rx) { 176 napi_complete(&ch->napi); 177 ltq_dma_ack_irq(&ch->dma); 178 } 179 return rx; 180 } 181 182 static int 183 ltq_etop_poll_tx(struct napi_struct *napi, int budget) 184 { 185 struct ltq_etop_chan *ch = 186 container_of(napi, struct ltq_etop_chan, napi); 187 struct ltq_etop_priv *priv = netdev_priv(ch->netdev); 188 struct netdev_queue *txq = 189 netdev_get_tx_queue(ch->netdev, ch->idx >> 1); 190 unsigned long flags; 191 192 spin_lock_irqsave(&priv->lock, flags); 193 while ((ch->dma.desc_base[ch->tx_free].ctl & 194 (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { 195 dev_kfree_skb_any(ch->skb[ch->tx_free]); 196 ch->skb[ch->tx_free] = NULL; 197 memset(&ch->dma.desc_base[ch->tx_free], 0, 198 sizeof(struct ltq_dma_desc)); 199 ch->tx_free++; 200 ch->tx_free %= LTQ_DESC_NUM; 201 } 202 spin_unlock_irqrestore(&priv->lock, flags); 203 204 if (netif_tx_queue_stopped(txq)) 205 netif_tx_start_queue(txq); 206 napi_complete(&ch->napi); 207 ltq_dma_ack_irq(&ch->dma); 208 return 1; 209 } 210 211 static irqreturn_t 212 ltq_etop_dma_irq(int irq, void *_priv) 213 { 214 struct ltq_etop_priv *priv = _priv; 215 int ch = irq - LTQ_DMA_CH0_INT; 216 217 napi_schedule(&priv->ch[ch].napi); 218 return IRQ_HANDLED; 219 } 220 221 static void 222 ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch) 223 { 224 struct ltq_etop_priv *priv = netdev_priv(dev); 225 226 ltq_dma_free(&ch->dma); 227 if (ch->dma.irq) 228 free_irq(ch->dma.irq, priv); 229 if (IS_RX(ch->idx)) { 230 int desc; 231 for (desc = 0; desc < LTQ_DESC_NUM; desc++) 232 dev_kfree_skb_any(ch->skb[ch->dma.desc]); 233 } 234 } 235 236 static void 237 ltq_etop_hw_exit(struct net_device *dev) 238 { 239 struct ltq_etop_priv *priv = netdev_priv(dev); 240 int i; 241 242 ltq_pmu_disable(PMU_PPE); 243 for (i = 0; i < MAX_DMA_CHAN; i++) 244 if (IS_TX(i) || IS_RX(i)) 245 ltq_etop_free_channel(dev, &priv->ch[i]); 246 } 247 248 static int 249 ltq_etop_hw_init(struct net_device *dev) 250 { 251 struct ltq_etop_priv *priv = netdev_priv(dev); 252 int i; 253 254 ltq_pmu_enable(PMU_PPE); 255 256 switch (priv->pldata->mii_mode) { 257 case PHY_INTERFACE_MODE_RMII: 258 ltq_etop_w32_mask(ETOP_MII_MASK, 259 ETOP_MII_REVERSE, LTQ_ETOP_CFG); 260 break; 261 262 case PHY_INTERFACE_MODE_MII: 263 ltq_etop_w32_mask(ETOP_MII_MASK, 264 ETOP_MII_NORMAL, LTQ_ETOP_CFG); 265 break; 266 267 default: 268 netdev_err(dev, "unknown mii mode %d\n", 269 priv->pldata->mii_mode); 270 return -ENOTSUPP; 271 } 272 273 /* enable crc generation */ 274 ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG); 275 276 ltq_dma_init_port(DMA_PORT_ETOP); 277 278 for (i = 0; i < MAX_DMA_CHAN; i++) { 279 int irq = LTQ_DMA_CH0_INT + i; 280 struct ltq_etop_chan *ch = &priv->ch[i]; 281 282 ch->idx = ch->dma.nr = i; 283 284 if (IS_TX(i)) { 285 ltq_dma_alloc_tx(&ch->dma); 286 request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED, 287 "etop_tx", priv); 288 } else if (IS_RX(i)) { 289 ltq_dma_alloc_rx(&ch->dma); 290 for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; 291 ch->dma.desc++) 292 if (ltq_etop_alloc_skb(ch)) 293 return -ENOMEM; 294 ch->dma.desc = 0; 295 request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED, 296 "etop_rx", priv); 297 } 298 ch->dma.irq = irq; 299 } 300 return 0; 301 } 302 303 static void 304 ltq_etop_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 305 { 306 strcpy(info->driver, "Lantiq ETOP"); 307 strcpy(info->bus_info, "internal"); 308 strcpy(info->version, DRV_VERSION); 309 } 310 311 static int 312 ltq_etop_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 313 { 314 struct ltq_etop_priv *priv = netdev_priv(dev); 315 316 return phy_ethtool_gset(priv->phydev, cmd); 317 } 318 319 static int 320 ltq_etop_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 321 { 322 struct ltq_etop_priv *priv = netdev_priv(dev); 323 324 return phy_ethtool_sset(priv->phydev, cmd); 325 } 326 327 static int 328 ltq_etop_nway_reset(struct net_device *dev) 329 { 330 struct ltq_etop_priv *priv = netdev_priv(dev); 331 332 return phy_start_aneg(priv->phydev); 333 } 334 335 static const struct ethtool_ops ltq_etop_ethtool_ops = { 336 .get_drvinfo = ltq_etop_get_drvinfo, 337 .get_settings = ltq_etop_get_settings, 338 .set_settings = ltq_etop_set_settings, 339 .nway_reset = ltq_etop_nway_reset, 340 }; 341 342 static int 343 ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) 344 { 345 u32 val = MDIO_REQUEST | 346 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | 347 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) | 348 phy_data; 349 350 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) 351 ; 352 ltq_etop_w32(val, LTQ_ETOP_MDIO); 353 return 0; 354 } 355 356 static int 357 ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg) 358 { 359 u32 val = MDIO_REQUEST | MDIO_READ | 360 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | 361 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET); 362 363 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) 364 ; 365 ltq_etop_w32(val, LTQ_ETOP_MDIO); 366 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) 367 ; 368 val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK; 369 return val; 370 } 371 372 static void 373 ltq_etop_mdio_link(struct net_device *dev) 374 { 375 /* nothing to do */ 376 } 377 378 static int 379 ltq_etop_mdio_probe(struct net_device *dev) 380 { 381 struct ltq_etop_priv *priv = netdev_priv(dev); 382 struct phy_device *phydev = NULL; 383 int phy_addr; 384 385 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { 386 if (priv->mii_bus->phy_map[phy_addr]) { 387 phydev = priv->mii_bus->phy_map[phy_addr]; 388 break; 389 } 390 } 391 392 if (!phydev) { 393 netdev_err(dev, "no PHY found\n"); 394 return -ENODEV; 395 } 396 397 phydev = phy_connect(dev, dev_name(&phydev->dev), <q_etop_mdio_link, 398 0, priv->pldata->mii_mode); 399 400 if (IS_ERR(phydev)) { 401 netdev_err(dev, "Could not attach to PHY\n"); 402 return PTR_ERR(phydev); 403 } 404 405 phydev->supported &= (SUPPORTED_10baseT_Half 406 | SUPPORTED_10baseT_Full 407 | SUPPORTED_100baseT_Half 408 | SUPPORTED_100baseT_Full 409 | SUPPORTED_Autoneg 410 | SUPPORTED_MII 411 | SUPPORTED_TP); 412 413 phydev->advertising = phydev->supported; 414 priv->phydev = phydev; 415 pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n", 416 dev->name, phydev->drv->name, 417 dev_name(&phydev->dev), phydev->irq); 418 419 return 0; 420 } 421 422 static int 423 ltq_etop_mdio_init(struct net_device *dev) 424 { 425 struct ltq_etop_priv *priv = netdev_priv(dev); 426 int i; 427 int err; 428 429 priv->mii_bus = mdiobus_alloc(); 430 if (!priv->mii_bus) { 431 netdev_err(dev, "failed to allocate mii bus\n"); 432 err = -ENOMEM; 433 goto err_out; 434 } 435 436 priv->mii_bus->priv = dev; 437 priv->mii_bus->read = ltq_etop_mdio_rd; 438 priv->mii_bus->write = ltq_etop_mdio_wr; 439 priv->mii_bus->name = "ltq_mii"; 440 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 441 priv->pdev->name, priv->pdev->id); 442 priv->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); 443 if (!priv->mii_bus->irq) { 444 err = -ENOMEM; 445 goto err_out_free_mdiobus; 446 } 447 448 for (i = 0; i < PHY_MAX_ADDR; ++i) 449 priv->mii_bus->irq[i] = PHY_POLL; 450 451 if (mdiobus_register(priv->mii_bus)) { 452 err = -ENXIO; 453 goto err_out_free_mdio_irq; 454 } 455 456 if (ltq_etop_mdio_probe(dev)) { 457 err = -ENXIO; 458 goto err_out_unregister_bus; 459 } 460 return 0; 461 462 err_out_unregister_bus: 463 mdiobus_unregister(priv->mii_bus); 464 err_out_free_mdio_irq: 465 kfree(priv->mii_bus->irq); 466 err_out_free_mdiobus: 467 mdiobus_free(priv->mii_bus); 468 err_out: 469 return err; 470 } 471 472 static void 473 ltq_etop_mdio_cleanup(struct net_device *dev) 474 { 475 struct ltq_etop_priv *priv = netdev_priv(dev); 476 477 phy_disconnect(priv->phydev); 478 mdiobus_unregister(priv->mii_bus); 479 kfree(priv->mii_bus->irq); 480 mdiobus_free(priv->mii_bus); 481 } 482 483 static int 484 ltq_etop_open(struct net_device *dev) 485 { 486 struct ltq_etop_priv *priv = netdev_priv(dev); 487 int i; 488 489 for (i = 0; i < MAX_DMA_CHAN; i++) { 490 struct ltq_etop_chan *ch = &priv->ch[i]; 491 492 if (!IS_TX(i) && (!IS_RX(i))) 493 continue; 494 ltq_dma_open(&ch->dma); 495 napi_enable(&ch->napi); 496 } 497 phy_start(priv->phydev); 498 netif_tx_start_all_queues(dev); 499 return 0; 500 } 501 502 static int 503 ltq_etop_stop(struct net_device *dev) 504 { 505 struct ltq_etop_priv *priv = netdev_priv(dev); 506 int i; 507 508 netif_tx_stop_all_queues(dev); 509 phy_stop(priv->phydev); 510 for (i = 0; i < MAX_DMA_CHAN; i++) { 511 struct ltq_etop_chan *ch = &priv->ch[i]; 512 513 if (!IS_RX(i) && !IS_TX(i)) 514 continue; 515 napi_disable(&ch->napi); 516 ltq_dma_close(&ch->dma); 517 } 518 return 0; 519 } 520 521 static int 522 ltq_etop_tx(struct sk_buff *skb, struct net_device *dev) 523 { 524 int queue = skb_get_queue_mapping(skb); 525 struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); 526 struct ltq_etop_priv *priv = netdev_priv(dev); 527 struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1]; 528 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 529 int len; 530 unsigned long flags; 531 u32 byte_offset; 532 533 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; 534 535 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { 536 dev_kfree_skb_any(skb); 537 netdev_err(dev, "tx ring full\n"); 538 netif_tx_stop_queue(txq); 539 return NETDEV_TX_BUSY; 540 } 541 542 /* dma needs to start on a 16 byte aligned address */ 543 byte_offset = CPHYSADDR(skb->data) % 16; 544 ch->skb[ch->dma.desc] = skb; 545 546 dev->trans_start = jiffies; 547 548 spin_lock_irqsave(&priv->lock, flags); 549 desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len, 550 DMA_TO_DEVICE)) - byte_offset; 551 wmb(); 552 desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | 553 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); 554 ch->dma.desc++; 555 ch->dma.desc %= LTQ_DESC_NUM; 556 spin_unlock_irqrestore(&priv->lock, flags); 557 558 if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN) 559 netif_tx_stop_queue(txq); 560 561 return NETDEV_TX_OK; 562 } 563 564 static int 565 ltq_etop_change_mtu(struct net_device *dev, int new_mtu) 566 { 567 int ret = eth_change_mtu(dev, new_mtu); 568 569 if (!ret) { 570 struct ltq_etop_priv *priv = netdev_priv(dev); 571 unsigned long flags; 572 573 spin_lock_irqsave(&priv->lock, flags); 574 ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, 575 LTQ_ETOP_IGPLEN); 576 spin_unlock_irqrestore(&priv->lock, flags); 577 } 578 return ret; 579 } 580 581 static int 582 ltq_etop_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 583 { 584 struct ltq_etop_priv *priv = netdev_priv(dev); 585 586 /* TODO: mii-toll reports "No MII transceiver present!." ?!*/ 587 return phy_mii_ioctl(priv->phydev, rq, cmd); 588 } 589 590 static int 591 ltq_etop_set_mac_address(struct net_device *dev, void *p) 592 { 593 int ret = eth_mac_addr(dev, p); 594 595 if (!ret) { 596 struct ltq_etop_priv *priv = netdev_priv(dev); 597 unsigned long flags; 598 599 /* store the mac for the unicast filter */ 600 spin_lock_irqsave(&priv->lock, flags); 601 ltq_etop_w32(*((u32 *)dev->dev_addr), LTQ_ETOP_MAC_DA0); 602 ltq_etop_w32(*((u16 *)&dev->dev_addr[4]) << 16, 603 LTQ_ETOP_MAC_DA1); 604 spin_unlock_irqrestore(&priv->lock, flags); 605 } 606 return ret; 607 } 608 609 static void 610 ltq_etop_set_multicast_list(struct net_device *dev) 611 { 612 struct ltq_etop_priv *priv = netdev_priv(dev); 613 unsigned long flags; 614 615 /* ensure that the unicast filter is not enabled in promiscious mode */ 616 spin_lock_irqsave(&priv->lock, flags); 617 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) 618 ltq_etop_w32_mask(ETOP_FTCU, 0, LTQ_ETOP_ENETS0); 619 else 620 ltq_etop_w32_mask(0, ETOP_FTCU, LTQ_ETOP_ENETS0); 621 spin_unlock_irqrestore(&priv->lock, flags); 622 } 623 624 static u16 625 ltq_etop_select_queue(struct net_device *dev, struct sk_buff *skb) 626 { 627 /* we are currently only using the first queue */ 628 return 0; 629 } 630 631 static int 632 ltq_etop_init(struct net_device *dev) 633 { 634 struct ltq_etop_priv *priv = netdev_priv(dev); 635 struct sockaddr mac; 636 int err; 637 638 ether_setup(dev); 639 dev->watchdog_timeo = 10 * HZ; 640 err = ltq_etop_hw_init(dev); 641 if (err) 642 goto err_hw; 643 ltq_etop_change_mtu(dev, 1500); 644 645 memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); 646 if (!is_valid_ether_addr(mac.sa_data)) { 647 pr_warn("etop: invalid MAC, using random\n"); 648 random_ether_addr(mac.sa_data); 649 } 650 651 err = ltq_etop_set_mac_address(dev, &mac); 652 if (err) 653 goto err_netdev; 654 ltq_etop_set_multicast_list(dev); 655 err = ltq_etop_mdio_init(dev); 656 if (err) 657 goto err_netdev; 658 return 0; 659 660 err_netdev: 661 unregister_netdev(dev); 662 free_netdev(dev); 663 err_hw: 664 ltq_etop_hw_exit(dev); 665 return err; 666 } 667 668 static void 669 ltq_etop_tx_timeout(struct net_device *dev) 670 { 671 int err; 672 673 ltq_etop_hw_exit(dev); 674 err = ltq_etop_hw_init(dev); 675 if (err) 676 goto err_hw; 677 dev->trans_start = jiffies; 678 netif_wake_queue(dev); 679 return; 680 681 err_hw: 682 ltq_etop_hw_exit(dev); 683 netdev_err(dev, "failed to restart etop after TX timeout\n"); 684 } 685 686 static const struct net_device_ops ltq_eth_netdev_ops = { 687 .ndo_open = ltq_etop_open, 688 .ndo_stop = ltq_etop_stop, 689 .ndo_start_xmit = ltq_etop_tx, 690 .ndo_change_mtu = ltq_etop_change_mtu, 691 .ndo_do_ioctl = ltq_etop_ioctl, 692 .ndo_set_mac_address = ltq_etop_set_mac_address, 693 .ndo_validate_addr = eth_validate_addr, 694 .ndo_set_rx_mode = ltq_etop_set_multicast_list, 695 .ndo_select_queue = ltq_etop_select_queue, 696 .ndo_init = ltq_etop_init, 697 .ndo_tx_timeout = ltq_etop_tx_timeout, 698 }; 699 700 static int __init 701 ltq_etop_probe(struct platform_device *pdev) 702 { 703 struct net_device *dev; 704 struct ltq_etop_priv *priv; 705 struct resource *res; 706 int err; 707 int i; 708 709 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 710 if (!res) { 711 dev_err(&pdev->dev, "failed to get etop resource\n"); 712 err = -ENOENT; 713 goto err_out; 714 } 715 716 res = devm_request_mem_region(&pdev->dev, res->start, 717 resource_size(res), dev_name(&pdev->dev)); 718 if (!res) { 719 dev_err(&pdev->dev, "failed to request etop resource\n"); 720 err = -EBUSY; 721 goto err_out; 722 } 723 724 ltq_etop_membase = devm_ioremap_nocache(&pdev->dev, 725 res->start, resource_size(res)); 726 if (!ltq_etop_membase) { 727 dev_err(&pdev->dev, "failed to remap etop engine %d\n", 728 pdev->id); 729 err = -ENOMEM; 730 goto err_out; 731 } 732 733 dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); 734 strcpy(dev->name, "eth%d"); 735 dev->netdev_ops = <q_eth_netdev_ops; 736 dev->ethtool_ops = <q_etop_ethtool_ops; 737 priv = netdev_priv(dev); 738 priv->res = res; 739 priv->pdev = pdev; 740 priv->pldata = dev_get_platdata(&pdev->dev); 741 priv->netdev = dev; 742 spin_lock_init(&priv->lock); 743 744 for (i = 0; i < MAX_DMA_CHAN; i++) { 745 if (IS_TX(i)) 746 netif_napi_add(dev, &priv->ch[i].napi, 747 ltq_etop_poll_tx, 8); 748 else if (IS_RX(i)) 749 netif_napi_add(dev, &priv->ch[i].napi, 750 ltq_etop_poll_rx, 32); 751 priv->ch[i].netdev = dev; 752 } 753 754 err = register_netdev(dev); 755 if (err) 756 goto err_free; 757 758 platform_set_drvdata(pdev, dev); 759 return 0; 760 761 err_free: 762 kfree(dev); 763 err_out: 764 return err; 765 } 766 767 static int __devexit 768 ltq_etop_remove(struct platform_device *pdev) 769 { 770 struct net_device *dev = platform_get_drvdata(pdev); 771 772 if (dev) { 773 netif_tx_stop_all_queues(dev); 774 ltq_etop_hw_exit(dev); 775 ltq_etop_mdio_cleanup(dev); 776 unregister_netdev(dev); 777 } 778 return 0; 779 } 780 781 static struct platform_driver ltq_mii_driver = { 782 .remove = __devexit_p(ltq_etop_remove), 783 .driver = { 784 .name = "ltq_etop", 785 .owner = THIS_MODULE, 786 }, 787 }; 788 789 int __init 790 init_ltq_etop(void) 791 { 792 int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe); 793 794 if (ret) 795 pr_err("ltq_etop: Error registering platfom driver!"); 796 return ret; 797 } 798 799 static void __exit 800 exit_ltq_etop(void) 801 { 802 platform_driver_unregister(<q_mii_driver); 803 } 804 805 module_init(init_ltq_etop); 806 module_exit(exit_ltq_etop); 807 808 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 809 MODULE_DESCRIPTION("Lantiq SoC ETOP"); 810 MODULE_LICENSE("GPL"); 811