1 /* 2 * This program is free software; you can redistribute it and/or modify it 3 * under the terms of the GNU General Public License version 2 as published 4 * by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, write to the Free Software 13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 14 * 15 * Copyright (C) 2011 John Crispin <blogic@openwrt.org> 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/slab.h> 20 #include <linux/errno.h> 21 #include <linux/types.h> 22 #include <linux/interrupt.h> 23 #include <linux/uaccess.h> 24 #include <linux/in.h> 25 #include <linux/netdevice.h> 26 #include <linux/etherdevice.h> 27 #include <linux/phy.h> 28 #include <linux/ip.h> 29 #include <linux/tcp.h> 30 #include <linux/skbuff.h> 31 #include <linux/mm.h> 32 #include <linux/platform_device.h> 33 #include <linux/ethtool.h> 34 #include <linux/init.h> 35 #include <linux/delay.h> 36 #include <linux/io.h> 37 #include <linux/dma-mapping.h> 38 #include <linux/module.h> 39 40 #include <asm/checksum.h> 41 42 #include <lantiq_soc.h> 43 #include <xway_dma.h> 44 #include <lantiq_platform.h> 45 46 #define LTQ_ETOP_MDIO 0x11804 47 #define MDIO_REQUEST 0x80000000 48 #define MDIO_READ 0x40000000 49 #define MDIO_ADDR_MASK 0x1f 50 #define MDIO_ADDR_OFFSET 0x15 51 #define MDIO_REG_MASK 0x1f 52 #define MDIO_REG_OFFSET 0x10 53 #define MDIO_VAL_MASK 0xffff 54 55 #define PPE32_CGEN 0x800 56 #define LQ_PPE32_ENET_MAC_CFG 0x1840 57 58 #define LTQ_ETOP_ENETS0 0x11850 59 #define LTQ_ETOP_MAC_DA0 0x1186C 60 #define LTQ_ETOP_MAC_DA1 0x11870 61 #define LTQ_ETOP_CFG 0x16020 62 #define LTQ_ETOP_IGPLEN 0x16080 63 64 #define MAX_DMA_CHAN 0x8 65 #define MAX_DMA_CRC_LEN 0x4 66 #define MAX_DMA_DATA_LEN 0x600 67 68 #define ETOP_FTCU BIT(28) 69 #define ETOP_MII_MASK 0xf 70 #define ETOP_MII_NORMAL 0xd 71 #define ETOP_MII_REVERSE 0xe 72 #define ETOP_PLEN_UNDER 0x40 73 #define ETOP_CGEN 0x800 74 75 /* use 2 static channels for TX/RX */ 76 #define LTQ_ETOP_TX_CHANNEL 1 77 #define LTQ_ETOP_RX_CHANNEL 6 78 #define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) 79 #define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) 80 81 #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x)) 82 #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y)) 83 #define ltq_etop_w32_mask(x, y, z) \ 84 ltq_w32_mask(x, y, ltq_etop_membase + (z)) 85 86 #define DRV_VERSION "1.0" 87 88 static void __iomem *ltq_etop_membase; 89 90 struct ltq_etop_chan { 91 int idx; 92 int tx_free; 93 struct net_device *netdev; 94 struct napi_struct napi; 95 struct ltq_dma_channel dma; 96 struct sk_buff *skb[LTQ_DESC_NUM]; 97 }; 98 99 struct ltq_etop_priv { 100 struct net_device *netdev; 101 struct platform_device *pdev; 102 struct ltq_eth_data *pldata; 103 struct resource *res; 104 105 struct mii_bus *mii_bus; 106 struct phy_device *phydev; 107 108 struct ltq_etop_chan ch[MAX_DMA_CHAN]; 109 int tx_free[MAX_DMA_CHAN >> 1]; 110 111 spinlock_t lock; 112 }; 113 114 static int 115 ltq_etop_alloc_skb(struct ltq_etop_chan *ch) 116 { 117 ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN); 118 if (!ch->skb[ch->dma.desc]) 119 return -ENOMEM; 120 ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL, 121 ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN, 122 DMA_FROM_DEVICE); 123 ch->dma.desc_base[ch->dma.desc].addr = 124 CPHYSADDR(ch->skb[ch->dma.desc]->data); 125 ch->dma.desc_base[ch->dma.desc].ctl = 126 LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | 127 MAX_DMA_DATA_LEN; 128 skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN); 129 return 0; 130 } 131 132 static void 133 ltq_etop_hw_receive(struct ltq_etop_chan *ch) 134 { 135 struct ltq_etop_priv *priv = netdev_priv(ch->netdev); 136 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 137 struct sk_buff *skb = ch->skb[ch->dma.desc]; 138 int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN; 139 unsigned long flags; 140 141 spin_lock_irqsave(&priv->lock, flags); 142 if (ltq_etop_alloc_skb(ch)) { 143 netdev_err(ch->netdev, 144 "failed to allocate new rx buffer, stopping DMA\n"); 145 ltq_dma_close(&ch->dma); 146 } 147 ch->dma.desc++; 148 ch->dma.desc %= LTQ_DESC_NUM; 149 spin_unlock_irqrestore(&priv->lock, flags); 150 151 skb_put(skb, len); 152 skb->protocol = eth_type_trans(skb, ch->netdev); 153 netif_receive_skb(skb); 154 } 155 156 static int 157 ltq_etop_poll_rx(struct napi_struct *napi, int budget) 158 { 159 struct ltq_etop_chan *ch = container_of(napi, 160 struct ltq_etop_chan, napi); 161 int rx = 0; 162 int complete = 0; 163 164 while ((rx < budget) && !complete) { 165 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 166 167 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { 168 ltq_etop_hw_receive(ch); 169 rx++; 170 } else { 171 complete = 1; 172 } 173 } 174 if (complete || !rx) { 175 napi_complete(&ch->napi); 176 ltq_dma_ack_irq(&ch->dma); 177 } 178 return rx; 179 } 180 181 static int 182 ltq_etop_poll_tx(struct napi_struct *napi, int budget) 183 { 184 struct ltq_etop_chan *ch = 185 container_of(napi, struct ltq_etop_chan, napi); 186 struct ltq_etop_priv *priv = netdev_priv(ch->netdev); 187 struct netdev_queue *txq = 188 netdev_get_tx_queue(ch->netdev, ch->idx >> 1); 189 unsigned long flags; 190 191 spin_lock_irqsave(&priv->lock, flags); 192 while ((ch->dma.desc_base[ch->tx_free].ctl & 193 (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { 194 dev_kfree_skb_any(ch->skb[ch->tx_free]); 195 ch->skb[ch->tx_free] = NULL; 196 memset(&ch->dma.desc_base[ch->tx_free], 0, 197 sizeof(struct ltq_dma_desc)); 198 ch->tx_free++; 199 ch->tx_free %= LTQ_DESC_NUM; 200 } 201 spin_unlock_irqrestore(&priv->lock, flags); 202 203 if (netif_tx_queue_stopped(txq)) 204 netif_tx_start_queue(txq); 205 napi_complete(&ch->napi); 206 ltq_dma_ack_irq(&ch->dma); 207 return 1; 208 } 209 210 static irqreturn_t 211 ltq_etop_dma_irq(int irq, void *_priv) 212 { 213 struct ltq_etop_priv *priv = _priv; 214 int ch = irq - LTQ_DMA_CH0_INT; 215 216 napi_schedule(&priv->ch[ch].napi); 217 return IRQ_HANDLED; 218 } 219 220 static void 221 ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch) 222 { 223 struct ltq_etop_priv *priv = netdev_priv(dev); 224 225 ltq_dma_free(&ch->dma); 226 if (ch->dma.irq) 227 free_irq(ch->dma.irq, priv); 228 if (IS_RX(ch->idx)) { 229 int desc; 230 for (desc = 0; desc < LTQ_DESC_NUM; desc++) 231 dev_kfree_skb_any(ch->skb[ch->dma.desc]); 232 } 233 } 234 235 static void 236 ltq_etop_hw_exit(struct net_device *dev) 237 { 238 struct ltq_etop_priv *priv = netdev_priv(dev); 239 int i; 240 241 ltq_pmu_disable(PMU_PPE); 242 for (i = 0; i < MAX_DMA_CHAN; i++) 243 if (IS_TX(i) || IS_RX(i)) 244 ltq_etop_free_channel(dev, &priv->ch[i]); 245 } 246 247 static int 248 ltq_etop_hw_init(struct net_device *dev) 249 { 250 struct ltq_etop_priv *priv = netdev_priv(dev); 251 int i; 252 253 ltq_pmu_enable(PMU_PPE); 254 255 switch (priv->pldata->mii_mode) { 256 case PHY_INTERFACE_MODE_RMII: 257 ltq_etop_w32_mask(ETOP_MII_MASK, 258 ETOP_MII_REVERSE, LTQ_ETOP_CFG); 259 break; 260 261 case PHY_INTERFACE_MODE_MII: 262 ltq_etop_w32_mask(ETOP_MII_MASK, 263 ETOP_MII_NORMAL, LTQ_ETOP_CFG); 264 break; 265 266 default: 267 netdev_err(dev, "unknown mii mode %d\n", 268 priv->pldata->mii_mode); 269 return -ENOTSUPP; 270 } 271 272 /* enable crc generation */ 273 ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG); 274 275 ltq_dma_init_port(DMA_PORT_ETOP); 276 277 for (i = 0; i < MAX_DMA_CHAN; i++) { 278 int irq = LTQ_DMA_CH0_INT + i; 279 struct ltq_etop_chan *ch = &priv->ch[i]; 280 281 ch->idx = ch->dma.nr = i; 282 283 if (IS_TX(i)) { 284 ltq_dma_alloc_tx(&ch->dma); 285 request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED, 286 "etop_tx", priv); 287 } else if (IS_RX(i)) { 288 ltq_dma_alloc_rx(&ch->dma); 289 for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; 290 ch->dma.desc++) 291 if (ltq_etop_alloc_skb(ch)) 292 return -ENOMEM; 293 ch->dma.desc = 0; 294 request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED, 295 "etop_rx", priv); 296 } 297 ch->dma.irq = irq; 298 } 299 return 0; 300 } 301 302 static void 303 ltq_etop_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 304 { 305 strcpy(info->driver, "Lantiq ETOP"); 306 strcpy(info->bus_info, "internal"); 307 strcpy(info->version, DRV_VERSION); 308 } 309 310 static int 311 ltq_etop_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 312 { 313 struct ltq_etop_priv *priv = netdev_priv(dev); 314 315 return phy_ethtool_gset(priv->phydev, cmd); 316 } 317 318 static int 319 ltq_etop_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 320 { 321 struct ltq_etop_priv *priv = netdev_priv(dev); 322 323 return phy_ethtool_sset(priv->phydev, cmd); 324 } 325 326 static int 327 ltq_etop_nway_reset(struct net_device *dev) 328 { 329 struct ltq_etop_priv *priv = netdev_priv(dev); 330 331 return phy_start_aneg(priv->phydev); 332 } 333 334 static const struct ethtool_ops ltq_etop_ethtool_ops = { 335 .get_drvinfo = ltq_etop_get_drvinfo, 336 .get_settings = ltq_etop_get_settings, 337 .set_settings = ltq_etop_set_settings, 338 .nway_reset = ltq_etop_nway_reset, 339 }; 340 341 static int 342 ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) 343 { 344 u32 val = MDIO_REQUEST | 345 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | 346 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) | 347 phy_data; 348 349 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) 350 ; 351 ltq_etop_w32(val, LTQ_ETOP_MDIO); 352 return 0; 353 } 354 355 static int 356 ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg) 357 { 358 u32 val = MDIO_REQUEST | MDIO_READ | 359 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) | 360 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET); 361 362 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) 363 ; 364 ltq_etop_w32(val, LTQ_ETOP_MDIO); 365 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST) 366 ; 367 val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK; 368 return val; 369 } 370 371 static void 372 ltq_etop_mdio_link(struct net_device *dev) 373 { 374 /* nothing to do */ 375 } 376 377 static int 378 ltq_etop_mdio_probe(struct net_device *dev) 379 { 380 struct ltq_etop_priv *priv = netdev_priv(dev); 381 struct phy_device *phydev = NULL; 382 int phy_addr; 383 384 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { 385 if (priv->mii_bus->phy_map[phy_addr]) { 386 phydev = priv->mii_bus->phy_map[phy_addr]; 387 break; 388 } 389 } 390 391 if (!phydev) { 392 netdev_err(dev, "no PHY found\n"); 393 return -ENODEV; 394 } 395 396 phydev = phy_connect(dev, dev_name(&phydev->dev), <q_etop_mdio_link, 397 0, priv->pldata->mii_mode); 398 399 if (IS_ERR(phydev)) { 400 netdev_err(dev, "Could not attach to PHY\n"); 401 return PTR_ERR(phydev); 402 } 403 404 phydev->supported &= (SUPPORTED_10baseT_Half 405 | SUPPORTED_10baseT_Full 406 | SUPPORTED_100baseT_Half 407 | SUPPORTED_100baseT_Full 408 | SUPPORTED_Autoneg 409 | SUPPORTED_MII 410 | SUPPORTED_TP); 411 412 phydev->advertising = phydev->supported; 413 priv->phydev = phydev; 414 pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n", 415 dev->name, phydev->drv->name, 416 dev_name(&phydev->dev), phydev->irq); 417 418 return 0; 419 } 420 421 static int 422 ltq_etop_mdio_init(struct net_device *dev) 423 { 424 struct ltq_etop_priv *priv = netdev_priv(dev); 425 int i; 426 int err; 427 428 priv->mii_bus = mdiobus_alloc(); 429 if (!priv->mii_bus) { 430 netdev_err(dev, "failed to allocate mii bus\n"); 431 err = -ENOMEM; 432 goto err_out; 433 } 434 435 priv->mii_bus->priv = dev; 436 priv->mii_bus->read = ltq_etop_mdio_rd; 437 priv->mii_bus->write = ltq_etop_mdio_wr; 438 priv->mii_bus->name = "ltq_mii"; 439 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 440 priv->pdev->name, priv->pdev->id); 441 priv->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); 442 if (!priv->mii_bus->irq) { 443 err = -ENOMEM; 444 goto err_out_free_mdiobus; 445 } 446 447 for (i = 0; i < PHY_MAX_ADDR; ++i) 448 priv->mii_bus->irq[i] = PHY_POLL; 449 450 if (mdiobus_register(priv->mii_bus)) { 451 err = -ENXIO; 452 goto err_out_free_mdio_irq; 453 } 454 455 if (ltq_etop_mdio_probe(dev)) { 456 err = -ENXIO; 457 goto err_out_unregister_bus; 458 } 459 return 0; 460 461 err_out_unregister_bus: 462 mdiobus_unregister(priv->mii_bus); 463 err_out_free_mdio_irq: 464 kfree(priv->mii_bus->irq); 465 err_out_free_mdiobus: 466 mdiobus_free(priv->mii_bus); 467 err_out: 468 return err; 469 } 470 471 static void 472 ltq_etop_mdio_cleanup(struct net_device *dev) 473 { 474 struct ltq_etop_priv *priv = netdev_priv(dev); 475 476 phy_disconnect(priv->phydev); 477 mdiobus_unregister(priv->mii_bus); 478 kfree(priv->mii_bus->irq); 479 mdiobus_free(priv->mii_bus); 480 } 481 482 static int 483 ltq_etop_open(struct net_device *dev) 484 { 485 struct ltq_etop_priv *priv = netdev_priv(dev); 486 int i; 487 488 for (i = 0; i < MAX_DMA_CHAN; i++) { 489 struct ltq_etop_chan *ch = &priv->ch[i]; 490 491 if (!IS_TX(i) && (!IS_RX(i))) 492 continue; 493 ltq_dma_open(&ch->dma); 494 napi_enable(&ch->napi); 495 } 496 phy_start(priv->phydev); 497 netif_tx_start_all_queues(dev); 498 return 0; 499 } 500 501 static int 502 ltq_etop_stop(struct net_device *dev) 503 { 504 struct ltq_etop_priv *priv = netdev_priv(dev); 505 int i; 506 507 netif_tx_stop_all_queues(dev); 508 phy_stop(priv->phydev); 509 for (i = 0; i < MAX_DMA_CHAN; i++) { 510 struct ltq_etop_chan *ch = &priv->ch[i]; 511 512 if (!IS_RX(i) && !IS_TX(i)) 513 continue; 514 napi_disable(&ch->napi); 515 ltq_dma_close(&ch->dma); 516 } 517 return 0; 518 } 519 520 static int 521 ltq_etop_tx(struct sk_buff *skb, struct net_device *dev) 522 { 523 int queue = skb_get_queue_mapping(skb); 524 struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); 525 struct ltq_etop_priv *priv = netdev_priv(dev); 526 struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1]; 527 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; 528 int len; 529 unsigned long flags; 530 u32 byte_offset; 531 532 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; 533 534 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { 535 dev_kfree_skb_any(skb); 536 netdev_err(dev, "tx ring full\n"); 537 netif_tx_stop_queue(txq); 538 return NETDEV_TX_BUSY; 539 } 540 541 /* dma needs to start on a 16 byte aligned address */ 542 byte_offset = CPHYSADDR(skb->data) % 16; 543 ch->skb[ch->dma.desc] = skb; 544 545 dev->trans_start = jiffies; 546 547 spin_lock_irqsave(&priv->lock, flags); 548 desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len, 549 DMA_TO_DEVICE)) - byte_offset; 550 wmb(); 551 desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | 552 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); 553 ch->dma.desc++; 554 ch->dma.desc %= LTQ_DESC_NUM; 555 spin_unlock_irqrestore(&priv->lock, flags); 556 557 if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN) 558 netif_tx_stop_queue(txq); 559 560 return NETDEV_TX_OK; 561 } 562 563 static int 564 ltq_etop_change_mtu(struct net_device *dev, int new_mtu) 565 { 566 int ret = eth_change_mtu(dev, new_mtu); 567 568 if (!ret) { 569 struct ltq_etop_priv *priv = netdev_priv(dev); 570 unsigned long flags; 571 572 spin_lock_irqsave(&priv->lock, flags); 573 ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, 574 LTQ_ETOP_IGPLEN); 575 spin_unlock_irqrestore(&priv->lock, flags); 576 } 577 return ret; 578 } 579 580 static int 581 ltq_etop_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 582 { 583 struct ltq_etop_priv *priv = netdev_priv(dev); 584 585 /* TODO: mii-toll reports "No MII transceiver present!." ?!*/ 586 return phy_mii_ioctl(priv->phydev, rq, cmd); 587 } 588 589 static int 590 ltq_etop_set_mac_address(struct net_device *dev, void *p) 591 { 592 int ret = eth_mac_addr(dev, p); 593 594 if (!ret) { 595 struct ltq_etop_priv *priv = netdev_priv(dev); 596 unsigned long flags; 597 598 /* store the mac for the unicast filter */ 599 spin_lock_irqsave(&priv->lock, flags); 600 ltq_etop_w32(*((u32 *)dev->dev_addr), LTQ_ETOP_MAC_DA0); 601 ltq_etop_w32(*((u16 *)&dev->dev_addr[4]) << 16, 602 LTQ_ETOP_MAC_DA1); 603 spin_unlock_irqrestore(&priv->lock, flags); 604 } 605 return ret; 606 } 607 608 static void 609 ltq_etop_set_multicast_list(struct net_device *dev) 610 { 611 struct ltq_etop_priv *priv = netdev_priv(dev); 612 unsigned long flags; 613 614 /* ensure that the unicast filter is not enabled in promiscious mode */ 615 spin_lock_irqsave(&priv->lock, flags); 616 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) 617 ltq_etop_w32_mask(ETOP_FTCU, 0, LTQ_ETOP_ENETS0); 618 else 619 ltq_etop_w32_mask(0, ETOP_FTCU, LTQ_ETOP_ENETS0); 620 spin_unlock_irqrestore(&priv->lock, flags); 621 } 622 623 static u16 624 ltq_etop_select_queue(struct net_device *dev, struct sk_buff *skb) 625 { 626 /* we are currently only using the first queue */ 627 return 0; 628 } 629 630 static int 631 ltq_etop_init(struct net_device *dev) 632 { 633 struct ltq_etop_priv *priv = netdev_priv(dev); 634 struct sockaddr mac; 635 int err; 636 bool random_mac = false; 637 638 ether_setup(dev); 639 dev->watchdog_timeo = 10 * HZ; 640 err = ltq_etop_hw_init(dev); 641 if (err) 642 goto err_hw; 643 ltq_etop_change_mtu(dev, 1500); 644 645 memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); 646 if (!is_valid_ether_addr(mac.sa_data)) { 647 pr_warn("etop: invalid MAC, using random\n"); 648 eth_random_addr(mac.sa_data); 649 random_mac = true; 650 } 651 652 err = ltq_etop_set_mac_address(dev, &mac); 653 if (err) 654 goto err_netdev; 655 656 /* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */ 657 if (random_mac) 658 dev->addr_assign_type |= NET_ADDR_RANDOM; 659 660 ltq_etop_set_multicast_list(dev); 661 err = ltq_etop_mdio_init(dev); 662 if (err) 663 goto err_netdev; 664 return 0; 665 666 err_netdev: 667 unregister_netdev(dev); 668 free_netdev(dev); 669 err_hw: 670 ltq_etop_hw_exit(dev); 671 return err; 672 } 673 674 static void 675 ltq_etop_tx_timeout(struct net_device *dev) 676 { 677 int err; 678 679 ltq_etop_hw_exit(dev); 680 err = ltq_etop_hw_init(dev); 681 if (err) 682 goto err_hw; 683 dev->trans_start = jiffies; 684 netif_wake_queue(dev); 685 return; 686 687 err_hw: 688 ltq_etop_hw_exit(dev); 689 netdev_err(dev, "failed to restart etop after TX timeout\n"); 690 } 691 692 static const struct net_device_ops ltq_eth_netdev_ops = { 693 .ndo_open = ltq_etop_open, 694 .ndo_stop = ltq_etop_stop, 695 .ndo_start_xmit = ltq_etop_tx, 696 .ndo_change_mtu = ltq_etop_change_mtu, 697 .ndo_do_ioctl = ltq_etop_ioctl, 698 .ndo_set_mac_address = ltq_etop_set_mac_address, 699 .ndo_validate_addr = eth_validate_addr, 700 .ndo_set_rx_mode = ltq_etop_set_multicast_list, 701 .ndo_select_queue = ltq_etop_select_queue, 702 .ndo_init = ltq_etop_init, 703 .ndo_tx_timeout = ltq_etop_tx_timeout, 704 }; 705 706 static int __init 707 ltq_etop_probe(struct platform_device *pdev) 708 { 709 struct net_device *dev; 710 struct ltq_etop_priv *priv; 711 struct resource *res; 712 int err; 713 int i; 714 715 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 716 if (!res) { 717 dev_err(&pdev->dev, "failed to get etop resource\n"); 718 err = -ENOENT; 719 goto err_out; 720 } 721 722 res = devm_request_mem_region(&pdev->dev, res->start, 723 resource_size(res), dev_name(&pdev->dev)); 724 if (!res) { 725 dev_err(&pdev->dev, "failed to request etop resource\n"); 726 err = -EBUSY; 727 goto err_out; 728 } 729 730 ltq_etop_membase = devm_ioremap_nocache(&pdev->dev, 731 res->start, resource_size(res)); 732 if (!ltq_etop_membase) { 733 dev_err(&pdev->dev, "failed to remap etop engine %d\n", 734 pdev->id); 735 err = -ENOMEM; 736 goto err_out; 737 } 738 739 dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); 740 if (!dev) { 741 err = -ENOMEM; 742 goto err_out; 743 } 744 strcpy(dev->name, "eth%d"); 745 dev->netdev_ops = <q_eth_netdev_ops; 746 dev->ethtool_ops = <q_etop_ethtool_ops; 747 priv = netdev_priv(dev); 748 priv->res = res; 749 priv->pdev = pdev; 750 priv->pldata = dev_get_platdata(&pdev->dev); 751 priv->netdev = dev; 752 spin_lock_init(&priv->lock); 753 754 for (i = 0; i < MAX_DMA_CHAN; i++) { 755 if (IS_TX(i)) 756 netif_napi_add(dev, &priv->ch[i].napi, 757 ltq_etop_poll_tx, 8); 758 else if (IS_RX(i)) 759 netif_napi_add(dev, &priv->ch[i].napi, 760 ltq_etop_poll_rx, 32); 761 priv->ch[i].netdev = dev; 762 } 763 764 err = register_netdev(dev); 765 if (err) 766 goto err_free; 767 768 platform_set_drvdata(pdev, dev); 769 return 0; 770 771 err_free: 772 kfree(dev); 773 err_out: 774 return err; 775 } 776 777 static int 778 ltq_etop_remove(struct platform_device *pdev) 779 { 780 struct net_device *dev = platform_get_drvdata(pdev); 781 782 if (dev) { 783 netif_tx_stop_all_queues(dev); 784 ltq_etop_hw_exit(dev); 785 ltq_etop_mdio_cleanup(dev); 786 unregister_netdev(dev); 787 } 788 return 0; 789 } 790 791 static struct platform_driver ltq_mii_driver = { 792 .remove = ltq_etop_remove, 793 .driver = { 794 .name = "ltq_etop", 795 .owner = THIS_MODULE, 796 }, 797 }; 798 799 int __init 800 init_ltq_etop(void) 801 { 802 int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe); 803 804 if (ret) 805 pr_err("ltq_etop: Error registering platform driver!"); 806 return ret; 807 } 808 809 static void __exit 810 exit_ltq_etop(void) 811 { 812 platform_driver_unregister(<q_mii_driver); 813 } 814 815 module_init(init_ltq_etop); 816 module_exit(exit_ltq_etop); 817 818 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); 819 MODULE_DESCRIPTION("Lantiq SoC ETOP"); 820 MODULE_LICENSE("GPL"); 821