1 /******************************************************************************* 2 3 Intel 10 Gigabit PCI Express Linux driver 4 Copyright(c) 1999 - 2016 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27 *******************************************************************************/ 28 #include "ixgbe.h" 29 #include <linux/ptp_classify.h> 30 #include <linux/clocksource.h> 31 32 /* 33 * The 82599 and the X540 do not have true 64bit nanosecond scale 34 * counter registers. Instead, SYSTIME is defined by a fixed point 35 * system which allows the user to define the scale counter increment 36 * value at every level change of the oscillator driving the SYSTIME 37 * value. For both devices the TIMINCA:IV field defines this 38 * increment. On the X540 device, 31 bits are provided. However on the 39 * 82599 only provides 24 bits. The time unit is determined by the 40 * clock frequency of the oscillator in combination with the TIMINCA 41 * register. When these devices link at 10Gb the oscillator has a 42 * period of 6.4ns. In order to convert the scale counter into 43 * nanoseconds the cyclecounter and timecounter structures are 44 * used. The SYSTIME registers need to be converted to ns values by use 45 * of only a right shift (division by power of 2). The following math 46 * determines the largest incvalue that will fit into the available 47 * bits in the TIMINCA register. 48 * 49 * PeriodWidth: Number of bits to store the clock period 50 * MaxWidth: The maximum width value of the TIMINCA register 51 * Period: The clock period for the oscillator 52 * round(): discard the fractional portion of the calculation 53 * 54 * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ] 55 * 56 * For the X540, MaxWidth is 31 bits, and the base period is 6.4 ns 57 * For the 82599, MaxWidth is 24 bits, and the base period is 6.4 ns 58 * 59 * The period also changes based on the link speed: 60 * At 10Gb link or no link, the period remains the same. 61 * At 1Gb link, the period is multiplied by 10. (64ns) 62 * At 100Mb link, the period is multiplied by 100. (640ns) 63 * 64 * The calculated value allows us to right shift the SYSTIME register 65 * value in order to quickly convert it into a nanosecond clock, 66 * while allowing for the maximum possible adjustment value. 67 * 68 * These diagrams are only for the 10Gb link period 69 * 70 * SYSTIMEH SYSTIMEL 71 * +--------------+ +--------------+ 72 * X540 | 32 | | 1 | 3 | 28 | 73 * *--------------+ +--------------+ 74 * \________ 36 bits ______/ fract 75 * 76 * +--------------+ +--------------+ 77 * 82599 | 32 | | 8 | 3 | 21 | 78 * *--------------+ +--------------+ 79 * \________ 43 bits ______/ fract 80 * 81 * The 36 bit X540 SYSTIME overflows every 82 * 2^36 * 10^-9 / 60 = 1.14 minutes or 69 seconds 83 * 84 * The 43 bit 82599 SYSTIME overflows every 85 * 2^43 * 10^-9 / 3600 = 2.4 hours 86 */ 87 #define IXGBE_INCVAL_10GB 0x66666666 88 #define IXGBE_INCVAL_1GB 0x40000000 89 #define IXGBE_INCVAL_100 0x50000000 90 91 #define IXGBE_INCVAL_SHIFT_10GB 28 92 #define IXGBE_INCVAL_SHIFT_1GB 24 93 #define IXGBE_INCVAL_SHIFT_100 21 94 95 #define IXGBE_INCVAL_SHIFT_82599 7 96 #define IXGBE_INCPER_SHIFT_82599 24 97 98 #define IXGBE_OVERFLOW_PERIOD (HZ * 30) 99 #define IXGBE_PTP_TX_TIMEOUT (HZ * 15) 100 101 /* half of a one second clock period, for use with PPS signal. We have to use 102 * this instead of something pre-defined like IXGBE_PTP_PPS_HALF_SECOND, in 103 * order to force at least 64bits of precision for shifting 104 */ 105 #define IXGBE_PTP_PPS_HALF_SECOND 500000000ULL 106 107 /* In contrast, the X550 controller has two registers, SYSTIMEH and SYSTIMEL 108 * which contain measurements of seconds and nanoseconds respectively. This 109 * matches the standard linux representation of time in the kernel. In addition, 110 * the X550 also has a SYSTIMER register which represents residue, or 111 * subnanosecond overflow adjustments. To control clock adjustment, the TIMINCA 112 * register is used, but it is unlike the X540 and 82599 devices. TIMINCA 113 * represents units of 2^-32 nanoseconds, and uses 31 bits for this, with the 114 * high bit representing whether the adjustent is positive or negative. Every 115 * clock cycle, the X550 will add 12.5 ns + TIMINCA which can result in a range 116 * of 12 to 13 nanoseconds adjustment. Unlike the 82599 and X540 devices, the 117 * X550's clock for purposes of SYSTIME generation is constant and not dependent 118 * on the link speed. 119 * 120 * SYSTIMEH SYSTIMEL SYSTIMER 121 * +--------------+ +--------------+ +-------------+ 122 * X550 | 32 | | 32 | | 32 | 123 * *--------------+ +--------------+ +-------------+ 124 * \____seconds___/ \_nanoseconds_/ \__2^-32 ns__/ 125 * 126 * This results in a full 96 bits to represent the clock, with 32 bits for 127 * seconds, 32 bits for nanoseconds (largest value is 0d999999999 or just under 128 * 1 second) and an additional 32 bits to measure sub nanosecond adjustments for 129 * underflow of adjustments. 130 * 131 * The 32 bits of seconds for the X550 overflows every 132 * 2^32 / ( 365.25 * 24 * 60 * 60 ) = ~136 years. 133 * 134 * In order to adjust the clock frequency for the X550, the TIMINCA register is 135 * provided. This register represents a + or minus nearly 0.5 ns adjustment to 136 * the base frequency. It is measured in 2^-32 ns units, with the high bit being 137 * the sign bit. This register enables software to calculate frequency 138 * adjustments and apply them directly to the clock rate. 139 * 140 * The math for converting ppb into TIMINCA values is fairly straightforward. 141 * TIMINCA value = ( Base_Frequency * ppb ) / 1000000000ULL 142 * 143 * This assumes that ppb is never high enough to create a value bigger than 144 * TIMINCA's 31 bits can store. This is ensured by the stack. Calculating this 145 * value is also simple. 146 * Max ppb = ( Max Adjustment / Base Frequency ) / 1000000000ULL 147 * 148 * For the X550, the Max adjustment is +/- 0.5 ns, and the base frequency is 149 * 12.5 nanoseconds. This means that the Max ppb is 39999999 150 * Note: We subtract one in order to ensure no overflow, because the TIMINCA 151 * register can only hold slightly under 0.5 nanoseconds. 152 * 153 * Because TIMINCA is measured in 2^-32 ns units, we have to convert 12.5 ns 154 * into 2^-32 units, which is 155 * 156 * 12.5 * 2^32 = C80000000 157 * 158 * Some revisions of hardware have a faster base frequency than the registers 159 * were defined for. To fix this, we use a timecounter structure with the 160 * proper mult and shift to convert the cycles into nanoseconds of time. 161 */ 162 #define IXGBE_X550_BASE_PERIOD 0xC80000000ULL 163 #define INCVALUE_MASK 0x7FFFFFFF 164 #define ISGN 0x80000000 165 #define MAX_TIMADJ 0x7FFFFFFF 166 167 /** 168 * ixgbe_ptp_setup_sdp_x540 169 * @hw: the hardware private structure 170 * 171 * this function enables or disables the clock out feature on SDP0 for 172 * the X540 device. It will create a 1second periodic output that can 173 * be used as the PPS (via an interrupt). 174 * 175 * It calculates when the systime will be on an exact second, and then 176 * aligns the start of the PPS signal to that value. The shift is 177 * necessary because it can change based on the link speed. 178 */ 179 static void ixgbe_ptp_setup_sdp_x540(struct ixgbe_adapter *adapter) 180 { 181 struct ixgbe_hw *hw = &adapter->hw; 182 int shift = adapter->hw_cc.shift; 183 u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh, rem; 184 u64 ns = 0, clock_edge = 0; 185 186 /* disable the pin first */ 187 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0); 188 IXGBE_WRITE_FLUSH(hw); 189 190 if (!(adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED)) 191 return; 192 193 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 194 195 /* enable the SDP0 pin as output, and connected to the 196 * native function for Timesync (ClockOut) 197 */ 198 esdp |= IXGBE_ESDP_SDP0_DIR | 199 IXGBE_ESDP_SDP0_NATIVE; 200 201 /* enable the Clock Out feature on SDP0, and allow 202 * interrupts to occur when the pin changes 203 */ 204 tsauxc = IXGBE_TSAUXC_EN_CLK | 205 IXGBE_TSAUXC_SYNCLK | 206 IXGBE_TSAUXC_SDP0_INT; 207 208 /* clock period (or pulse length) */ 209 clktiml = (u32)(IXGBE_PTP_PPS_HALF_SECOND << shift); 210 clktimh = (u32)((IXGBE_PTP_PPS_HALF_SECOND << shift) >> 32); 211 212 /* Account for the cyclecounter wrap-around value by 213 * using the converted ns value of the current time to 214 * check for when the next aligned second would occur. 215 */ 216 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 217 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32; 218 ns = timecounter_cyc2time(&adapter->hw_tc, clock_edge); 219 220 div_u64_rem(ns, IXGBE_PTP_PPS_HALF_SECOND, &rem); 221 clock_edge += ((IXGBE_PTP_PPS_HALF_SECOND - (u64)rem) << shift); 222 223 /* specify the initial clock start time */ 224 trgttiml = (u32)clock_edge; 225 trgttimh = (u32)(clock_edge >> 32); 226 227 IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml); 228 IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh); 229 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml); 230 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh); 231 232 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 233 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc); 234 235 IXGBE_WRITE_FLUSH(hw); 236 } 237 238 /** 239 * ixgbe_ptp_read_X550 - read cycle counter value 240 * @hw_cc: cyclecounter structure 241 * 242 * This function reads SYSTIME registers. It is called by the cyclecounter 243 * structure to convert from internal representation into nanoseconds. We need 244 * this for X550 since some skews do not have expected clock frequency and 245 * result of SYSTIME is 32bits of "billions of cycles" and 32 bits of 246 * "cycles", rather than seconds and nanoseconds. 247 */ 248 static u64 ixgbe_ptp_read_X550(const struct cyclecounter *hw_cc) 249 { 250 struct ixgbe_adapter *adapter = 251 container_of(hw_cc, struct ixgbe_adapter, hw_cc); 252 struct ixgbe_hw *hw = &adapter->hw; 253 struct timespec64 ts; 254 255 /* storage is 32 bits of 'billions of cycles' and 32 bits of 'cycles'. 256 * Some revisions of hardware run at a higher frequency and so the 257 * cycles are not guaranteed to be nanoseconds. The timespec64 created 258 * here is used for its math/conversions but does not necessarily 259 * represent nominal time. 260 * 261 * It should be noted that this cyclecounter will overflow at a 262 * non-bitmask field since we have to convert our billions of cycles 263 * into an actual cycles count. This results in some possible weird 264 * situations at high cycle counter stamps. However given that 32 bits 265 * of "seconds" is ~138 years this isn't a problem. Even at the 266 * increased frequency of some revisions, this is still ~103 years. 267 * Since the SYSTIME values start at 0 and we never write them, it is 268 * highly unlikely for the cyclecounter to overflow in practice. 269 */ 270 IXGBE_READ_REG(hw, IXGBE_SYSTIMR); 271 ts.tv_nsec = IXGBE_READ_REG(hw, IXGBE_SYSTIML); 272 ts.tv_sec = IXGBE_READ_REG(hw, IXGBE_SYSTIMH); 273 274 return (u64)timespec64_to_ns(&ts); 275 } 276 277 /** 278 * ixgbe_ptp_read_82599 - read raw cycle counter (to be used by time counter) 279 * @cc: the cyclecounter structure 280 * 281 * this function reads the cyclecounter registers and is called by the 282 * cyclecounter structure used to construct a ns counter from the 283 * arbitrary fixed point registers 284 */ 285 static u64 ixgbe_ptp_read_82599(const struct cyclecounter *cc) 286 { 287 struct ixgbe_adapter *adapter = 288 container_of(cc, struct ixgbe_adapter, hw_cc); 289 struct ixgbe_hw *hw = &adapter->hw; 290 u64 stamp = 0; 291 292 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML); 293 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32; 294 295 return stamp; 296 } 297 298 /** 299 * ixgbe_ptp_convert_to_hwtstamp - convert register value to hw timestamp 300 * @adapter: private adapter structure 301 * @hwtstamp: stack timestamp structure 302 * @systim: unsigned 64bit system time value 303 * 304 * We need to convert the adapter's RX/TXSTMP registers into a hwtstamp value 305 * which can be used by the stack's ptp functions. 306 * 307 * The lock is used to protect consistency of the cyclecounter and the SYSTIME 308 * registers. However, it does not need to protect against the Rx or Tx 309 * timestamp registers, as there can't be a new timestamp until the old one is 310 * unlatched by reading. 311 * 312 * In addition to the timestamp in hardware, some controllers need a software 313 * overflow cyclecounter, and this function takes this into account as well. 314 **/ 315 static void ixgbe_ptp_convert_to_hwtstamp(struct ixgbe_adapter *adapter, 316 struct skb_shared_hwtstamps *hwtstamp, 317 u64 timestamp) 318 { 319 unsigned long flags; 320 struct timespec64 systime; 321 u64 ns; 322 323 memset(hwtstamp, 0, sizeof(*hwtstamp)); 324 325 switch (adapter->hw.mac.type) { 326 /* X550 and later hardware supposedly represent time using a seconds 327 * and nanoseconds counter, instead of raw 64bits nanoseconds. We need 328 * to convert the timestamp into cycles before it can be fed to the 329 * cyclecounter. We need an actual cyclecounter because some revisions 330 * of hardware run at a higher frequency and thus the counter does 331 * not represent seconds/nanoseconds. Instead it can be thought of as 332 * cycles and billions of cycles. 333 */ 334 case ixgbe_mac_X550: 335 case ixgbe_mac_X550EM_x: 336 case ixgbe_mac_x550em_a: 337 /* Upper 32 bits represent billions of cycles, lower 32 bits 338 * represent cycles. However, we use timespec64_to_ns for the 339 * correct math even though the units haven't been corrected 340 * yet. 341 */ 342 systime.tv_sec = timestamp >> 32; 343 systime.tv_nsec = timestamp & 0xFFFFFFFF; 344 345 timestamp = timespec64_to_ns(&systime); 346 break; 347 default: 348 break; 349 } 350 351 spin_lock_irqsave(&adapter->tmreg_lock, flags); 352 ns = timecounter_cyc2time(&adapter->hw_tc, timestamp); 353 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 354 355 hwtstamp->hwtstamp = ns_to_ktime(ns); 356 } 357 358 /** 359 * ixgbe_ptp_adjfreq_82599 360 * @ptp: the ptp clock structure 361 * @ppb: parts per billion adjustment from base 362 * 363 * adjust the frequency of the ptp cycle counter by the 364 * indicated ppb from the base frequency. 365 */ 366 static int ixgbe_ptp_adjfreq_82599(struct ptp_clock_info *ptp, s32 ppb) 367 { 368 struct ixgbe_adapter *adapter = 369 container_of(ptp, struct ixgbe_adapter, ptp_caps); 370 struct ixgbe_hw *hw = &adapter->hw; 371 u64 freq, incval; 372 u32 diff; 373 int neg_adj = 0; 374 375 if (ppb < 0) { 376 neg_adj = 1; 377 ppb = -ppb; 378 } 379 380 smp_mb(); 381 incval = ACCESS_ONCE(adapter->base_incval); 382 383 freq = incval; 384 freq *= ppb; 385 diff = div_u64(freq, 1000000000ULL); 386 387 incval = neg_adj ? (incval - diff) : (incval + diff); 388 389 switch (hw->mac.type) { 390 case ixgbe_mac_X540: 391 if (incval > 0xFFFFFFFFULL) 392 e_dev_warn("PTP ppb adjusted SYSTIME rate overflowed!\n"); 393 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, (u32)incval); 394 break; 395 case ixgbe_mac_82599EB: 396 if (incval > 0x00FFFFFFULL) 397 e_dev_warn("PTP ppb adjusted SYSTIME rate overflowed!\n"); 398 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 399 BIT(IXGBE_INCPER_SHIFT_82599) | 400 ((u32)incval & 0x00FFFFFFUL)); 401 break; 402 default: 403 break; 404 } 405 406 return 0; 407 } 408 409 /** 410 * ixgbe_ptp_adjfreq_X550 411 * @ptp: the ptp clock structure 412 * @ppb: parts per billion adjustment from base 413 * 414 * adjust the frequency of the SYSTIME registers by the indicated ppb from base 415 * frequency 416 */ 417 static int ixgbe_ptp_adjfreq_X550(struct ptp_clock_info *ptp, s32 ppb) 418 { 419 struct ixgbe_adapter *adapter = 420 container_of(ptp, struct ixgbe_adapter, ptp_caps); 421 struct ixgbe_hw *hw = &adapter->hw; 422 int neg_adj = 0; 423 u64 rate = IXGBE_X550_BASE_PERIOD; 424 u32 inca; 425 426 if (ppb < 0) { 427 neg_adj = 1; 428 ppb = -ppb; 429 } 430 rate *= ppb; 431 rate = div_u64(rate, 1000000000ULL); 432 433 /* warn if rate is too large */ 434 if (rate >= INCVALUE_MASK) 435 e_dev_warn("PTP ppb adjusted SYSTIME rate overflowed!\n"); 436 437 inca = rate & INCVALUE_MASK; 438 if (neg_adj) 439 inca |= ISGN; 440 441 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, inca); 442 443 return 0; 444 } 445 446 /** 447 * ixgbe_ptp_adjtime 448 * @ptp: the ptp clock structure 449 * @delta: offset to adjust the cycle counter by 450 * 451 * adjust the timer by resetting the timecounter structure. 452 */ 453 static int ixgbe_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 454 { 455 struct ixgbe_adapter *adapter = 456 container_of(ptp, struct ixgbe_adapter, ptp_caps); 457 unsigned long flags; 458 459 spin_lock_irqsave(&adapter->tmreg_lock, flags); 460 timecounter_adjtime(&adapter->hw_tc, delta); 461 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 462 463 if (adapter->ptp_setup_sdp) 464 adapter->ptp_setup_sdp(adapter); 465 466 return 0; 467 } 468 469 /** 470 * ixgbe_ptp_gettime 471 * @ptp: the ptp clock structure 472 * @ts: timespec structure to hold the current time value 473 * 474 * read the timecounter and return the correct value on ns, 475 * after converting it into a struct timespec. 476 */ 477 static int ixgbe_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) 478 { 479 struct ixgbe_adapter *adapter = 480 container_of(ptp, struct ixgbe_adapter, ptp_caps); 481 unsigned long flags; 482 u64 ns; 483 484 spin_lock_irqsave(&adapter->tmreg_lock, flags); 485 ns = timecounter_read(&adapter->hw_tc); 486 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 487 488 *ts = ns_to_timespec64(ns); 489 490 return 0; 491 } 492 493 /** 494 * ixgbe_ptp_settime 495 * @ptp: the ptp clock structure 496 * @ts: the timespec containing the new time for the cycle counter 497 * 498 * reset the timecounter to use a new base value instead of the kernel 499 * wall timer value. 500 */ 501 static int ixgbe_ptp_settime(struct ptp_clock_info *ptp, 502 const struct timespec64 *ts) 503 { 504 struct ixgbe_adapter *adapter = 505 container_of(ptp, struct ixgbe_adapter, ptp_caps); 506 unsigned long flags; 507 u64 ns = timespec64_to_ns(ts); 508 509 /* reset the timecounter */ 510 spin_lock_irqsave(&adapter->tmreg_lock, flags); 511 timecounter_init(&adapter->hw_tc, &adapter->hw_cc, ns); 512 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 513 514 if (adapter->ptp_setup_sdp) 515 adapter->ptp_setup_sdp(adapter); 516 return 0; 517 } 518 519 /** 520 * ixgbe_ptp_feature_enable 521 * @ptp: the ptp clock structure 522 * @rq: the requested feature to change 523 * @on: whether to enable or disable the feature 524 * 525 * enable (or disable) ancillary features of the phc subsystem. 526 * our driver only supports the PPS feature on the X540 527 */ 528 static int ixgbe_ptp_feature_enable(struct ptp_clock_info *ptp, 529 struct ptp_clock_request *rq, int on) 530 { 531 struct ixgbe_adapter *adapter = 532 container_of(ptp, struct ixgbe_adapter, ptp_caps); 533 534 /** 535 * When PPS is enabled, unmask the interrupt for the ClockOut 536 * feature, so that the interrupt handler can send the PPS 537 * event when the clock SDP triggers. Clear mask when PPS is 538 * disabled 539 */ 540 if (rq->type != PTP_CLK_REQ_PPS || !adapter->ptp_setup_sdp) 541 return -ENOTSUPP; 542 543 if (on) 544 adapter->flags2 |= IXGBE_FLAG2_PTP_PPS_ENABLED; 545 else 546 adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED; 547 548 adapter->ptp_setup_sdp(adapter); 549 return 0; 550 } 551 552 /** 553 * ixgbe_ptp_check_pps_event 554 * @adapter: the private adapter structure 555 * 556 * This function is called by the interrupt routine when checking for 557 * interrupts. It will check and handle a pps event. 558 */ 559 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter) 560 { 561 struct ixgbe_hw *hw = &adapter->hw; 562 struct ptp_clock_event event; 563 564 event.type = PTP_CLOCK_PPS; 565 566 /* this check is necessary in case the interrupt was enabled via some 567 * alternative means (ex. debug_fs). Better to check here than 568 * everywhere that calls this function. 569 */ 570 if (!adapter->ptp_clock) 571 return; 572 573 switch (hw->mac.type) { 574 case ixgbe_mac_X540: 575 ptp_clock_event(adapter->ptp_clock, &event); 576 break; 577 default: 578 break; 579 } 580 } 581 582 /** 583 * ixgbe_ptp_overflow_check - watchdog task to detect SYSTIME overflow 584 * @adapter: private adapter struct 585 * 586 * this watchdog task periodically reads the timecounter 587 * in order to prevent missing when the system time registers wrap 588 * around. This needs to be run approximately twice a minute. 589 */ 590 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter) 591 { 592 bool timeout = time_is_before_jiffies(adapter->last_overflow_check + 593 IXGBE_OVERFLOW_PERIOD); 594 struct timespec64 ts; 595 596 if (timeout) { 597 ixgbe_ptp_gettime(&adapter->ptp_caps, &ts); 598 adapter->last_overflow_check = jiffies; 599 } 600 } 601 602 /** 603 * ixgbe_ptp_rx_hang - detect error case when Rx timestamp registers latched 604 * @adapter: private network adapter structure 605 * 606 * this watchdog task is scheduled to detect error case where hardware has 607 * dropped an Rx packet that was timestamped when the ring is full. The 608 * particular error is rare but leaves the device in a state unable to timestamp 609 * any future packets. 610 */ 611 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter) 612 { 613 struct ixgbe_hw *hw = &adapter->hw; 614 u32 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 615 struct ixgbe_ring *rx_ring; 616 unsigned long rx_event; 617 int n; 618 619 /* if we don't have a valid timestamp in the registers, just update the 620 * timeout counter and exit 621 */ 622 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID)) { 623 adapter->last_rx_ptp_check = jiffies; 624 return; 625 } 626 627 /* determine the most recent watchdog or rx_timestamp event */ 628 rx_event = adapter->last_rx_ptp_check; 629 for (n = 0; n < adapter->num_rx_queues; n++) { 630 rx_ring = adapter->rx_ring[n]; 631 if (time_after(rx_ring->last_rx_timestamp, rx_event)) 632 rx_event = rx_ring->last_rx_timestamp; 633 } 634 635 /* only need to read the high RXSTMP register to clear the lock */ 636 if (time_is_before_jiffies(rx_event + 5 * HZ)) { 637 IXGBE_READ_REG(hw, IXGBE_RXSTMPH); 638 adapter->last_rx_ptp_check = jiffies; 639 640 adapter->rx_hwtstamp_cleared++; 641 e_warn(drv, "clearing RX Timestamp hang\n"); 642 } 643 } 644 645 /** 646 * ixgbe_ptp_clear_tx_timestamp - utility function to clear Tx timestamp state 647 * @adapter: the private adapter structure 648 * 649 * This function should be called whenever the state related to a Tx timestamp 650 * needs to be cleared. This helps ensure that all related bits are reset for 651 * the next Tx timestamp event. 652 */ 653 static void ixgbe_ptp_clear_tx_timestamp(struct ixgbe_adapter *adapter) 654 { 655 struct ixgbe_hw *hw = &adapter->hw; 656 657 IXGBE_READ_REG(hw, IXGBE_TXSTMPH); 658 if (adapter->ptp_tx_skb) { 659 dev_kfree_skb_any(adapter->ptp_tx_skb); 660 adapter->ptp_tx_skb = NULL; 661 } 662 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state); 663 } 664 665 /** 666 * ixgbe_ptp_tx_hwtstamp - utility function which checks for TX time stamp 667 * @adapter: the private adapter struct 668 * 669 * if the timestamp is valid, we convert it into the timecounter ns 670 * value, then store that result into the shhwtstamps structure which 671 * is passed up the network stack 672 */ 673 static void ixgbe_ptp_tx_hwtstamp(struct ixgbe_adapter *adapter) 674 { 675 struct ixgbe_hw *hw = &adapter->hw; 676 struct skb_shared_hwtstamps shhwtstamps; 677 u64 regval = 0; 678 679 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL); 680 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32; 681 682 ixgbe_ptp_convert_to_hwtstamp(adapter, &shhwtstamps, regval); 683 skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps); 684 685 ixgbe_ptp_clear_tx_timestamp(adapter); 686 } 687 688 /** 689 * ixgbe_ptp_tx_hwtstamp_work 690 * @work: pointer to the work struct 691 * 692 * This work item polls TSYNCTXCTL valid bit to determine when a Tx hardware 693 * timestamp has been taken for the current skb. It is necessary, because the 694 * descriptor's "done" bit does not correlate with the timestamp event. 695 */ 696 static void ixgbe_ptp_tx_hwtstamp_work(struct work_struct *work) 697 { 698 struct ixgbe_adapter *adapter = container_of(work, struct ixgbe_adapter, 699 ptp_tx_work); 700 struct ixgbe_hw *hw = &adapter->hw; 701 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start + 702 IXGBE_PTP_TX_TIMEOUT); 703 u32 tsynctxctl; 704 705 /* we have to have a valid skb to poll for a timestamp */ 706 if (!adapter->ptp_tx_skb) { 707 ixgbe_ptp_clear_tx_timestamp(adapter); 708 return; 709 } 710 711 /* stop polling once we have a valid timestamp */ 712 tsynctxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 713 if (tsynctxctl & IXGBE_TSYNCTXCTL_VALID) { 714 ixgbe_ptp_tx_hwtstamp(adapter); 715 return; 716 } 717 718 if (timeout) { 719 ixgbe_ptp_clear_tx_timestamp(adapter); 720 adapter->tx_hwtstamp_timeouts++; 721 e_warn(drv, "clearing Tx Timestamp hang\n"); 722 } else { 723 /* reschedule to keep checking if it's not available yet */ 724 schedule_work(&adapter->ptp_tx_work); 725 } 726 } 727 728 /** 729 * ixgbe_ptp_rx_pktstamp - utility function to get RX time stamp from buffer 730 * @q_vector: structure containing interrupt and ring information 731 * @skb: the packet 732 * 733 * This function will be called by the Rx routine of the timestamp for this 734 * packet is stored in the buffer. The value is stored in little endian format 735 * starting at the end of the packet data. 736 */ 737 void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *q_vector, 738 struct sk_buff *skb) 739 { 740 __le64 regval; 741 742 /* copy the bits out of the skb, and then trim the skb length */ 743 skb_copy_bits(skb, skb->len - IXGBE_TS_HDR_LEN, ®val, 744 IXGBE_TS_HDR_LEN); 745 __pskb_trim(skb, skb->len - IXGBE_TS_HDR_LEN); 746 747 /* The timestamp is recorded in little endian format, and is stored at 748 * the end of the packet. 749 * 750 * DWORD: N N + 1 N + 2 751 * Field: End of Packet SYSTIMH SYSTIML 752 */ 753 ixgbe_ptp_convert_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb), 754 le64_to_cpu(regval)); 755 } 756 757 /** 758 * ixgbe_ptp_rx_rgtstamp - utility function which checks for RX time stamp 759 * @q_vector: structure containing interrupt and ring information 760 * @skb: particular skb to send timestamp with 761 * 762 * if the timestamp is valid, we convert it into the timecounter ns 763 * value, then store that result into the shhwtstamps structure which 764 * is passed up the network stack 765 */ 766 void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *q_vector, 767 struct sk_buff *skb) 768 { 769 struct ixgbe_adapter *adapter; 770 struct ixgbe_hw *hw; 771 u64 regval = 0; 772 u32 tsyncrxctl; 773 774 /* we cannot process timestamps on a ring without a q_vector */ 775 if (!q_vector || !q_vector->adapter) 776 return; 777 778 adapter = q_vector->adapter; 779 hw = &adapter->hw; 780 781 /* Read the tsyncrxctl register afterwards in order to prevent taking an 782 * I/O hit on every packet. 783 */ 784 785 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 786 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID)) 787 return; 788 789 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL); 790 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32; 791 792 ixgbe_ptp_convert_to_hwtstamp(adapter, skb_hwtstamps(skb), regval); 793 } 794 795 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr) 796 { 797 struct hwtstamp_config *config = &adapter->tstamp_config; 798 799 return copy_to_user(ifr->ifr_data, config, 800 sizeof(*config)) ? -EFAULT : 0; 801 } 802 803 /** 804 * ixgbe_ptp_set_timestamp_mode - setup the hardware for the requested mode 805 * @adapter: the private ixgbe adapter structure 806 * @config: the hwtstamp configuration requested 807 * 808 * Outgoing time stamping can be enabled and disabled. Play nice and 809 * disable it when requested, although it shouldn't cause any overhead 810 * when no packet needs it. At most one packet in the queue may be 811 * marked for time stamping, otherwise it would be impossible to tell 812 * for sure to which packet the hardware time stamp belongs. 813 * 814 * Incoming time stamping has to be configured via the hardware 815 * filters. Not all combinations are supported, in particular event 816 * type has to be specified. Matching the kind of event packet is 817 * not supported, with the exception of "all V2 events regardless of 818 * level 2 or 4". 819 * 820 * Since hardware always timestamps Path delay packets when timestamping V2 821 * packets, regardless of the type specified in the register, only use V2 822 * Event mode. This more accurately tells the user what the hardware is going 823 * to do anyways. 824 * 825 * Note: this may modify the hwtstamp configuration towards a more general 826 * mode, if required to support the specifically requested mode. 827 */ 828 static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter, 829 struct hwtstamp_config *config) 830 { 831 struct ixgbe_hw *hw = &adapter->hw; 832 u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED; 833 u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED; 834 u32 tsync_rx_mtrl = PTP_EV_PORT << 16; 835 bool is_l2 = false; 836 u32 regval; 837 838 /* reserved for future extensions */ 839 if (config->flags) 840 return -EINVAL; 841 842 switch (config->tx_type) { 843 case HWTSTAMP_TX_OFF: 844 tsync_tx_ctl = 0; 845 case HWTSTAMP_TX_ON: 846 break; 847 default: 848 return -ERANGE; 849 } 850 851 switch (config->rx_filter) { 852 case HWTSTAMP_FILTER_NONE: 853 tsync_rx_ctl = 0; 854 tsync_rx_mtrl = 0; 855 adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED | 856 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); 857 break; 858 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 859 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1; 860 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_SYNC_MSG; 861 adapter->flags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED | 862 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); 863 break; 864 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 865 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1; 866 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_DELAY_REQ_MSG; 867 adapter->flags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED | 868 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); 869 break; 870 case HWTSTAMP_FILTER_PTP_V2_EVENT: 871 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 872 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 873 case HWTSTAMP_FILTER_PTP_V2_SYNC: 874 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 875 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 876 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 877 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 878 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 879 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2; 880 is_l2 = true; 881 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 882 adapter->flags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED | 883 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); 884 break; 885 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 886 case HWTSTAMP_FILTER_ALL: 887 /* The X550 controller is capable of timestamping all packets, 888 * which allows it to accept any filter. 889 */ 890 if (hw->mac.type >= ixgbe_mac_X550) { 891 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_ALL; 892 config->rx_filter = HWTSTAMP_FILTER_ALL; 893 adapter->flags |= IXGBE_FLAG_RX_HWTSTAMP_ENABLED; 894 break; 895 } 896 /* fall through */ 897 default: 898 /* 899 * register RXMTRL must be set in order to do V1 packets, 900 * therefore it is not possible to time stamp both V1 Sync and 901 * Delay_Req messages and hardware does not support 902 * timestamping all packets => return error 903 */ 904 adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED | 905 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); 906 config->rx_filter = HWTSTAMP_FILTER_NONE; 907 return -ERANGE; 908 } 909 910 if (hw->mac.type == ixgbe_mac_82598EB) { 911 adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED | 912 IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); 913 if (tsync_rx_ctl | tsync_tx_ctl) 914 return -ERANGE; 915 return 0; 916 } 917 918 /* Per-packet timestamping only works if the filter is set to all 919 * packets. Since this is desired, always timestamp all packets as long 920 * as any Rx filter was configured. 921 */ 922 switch (hw->mac.type) { 923 case ixgbe_mac_X550: 924 case ixgbe_mac_X550EM_x: 925 case ixgbe_mac_x550em_a: 926 /* enable timestamping all packets only if at least some 927 * packets were requested. Otherwise, play nice and disable 928 * timestamping 929 */ 930 if (config->rx_filter == HWTSTAMP_FILTER_NONE) 931 break; 932 933 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED | 934 IXGBE_TSYNCRXCTL_TYPE_ALL | 935 IXGBE_TSYNCRXCTL_TSIP_UT_EN; 936 config->rx_filter = HWTSTAMP_FILTER_ALL; 937 adapter->flags |= IXGBE_FLAG_RX_HWTSTAMP_ENABLED; 938 adapter->flags &= ~IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER; 939 is_l2 = true; 940 break; 941 default: 942 break; 943 } 944 945 /* define ethertype filter for timestamping L2 packets */ 946 if (is_l2) 947 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 948 (IXGBE_ETQF_FILTER_EN | /* enable filter */ 949 IXGBE_ETQF_1588 | /* enable timestamping */ 950 ETH_P_1588)); /* 1588 eth protocol type */ 951 else 952 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0); 953 954 /* enable/disable TX */ 955 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL); 956 regval &= ~IXGBE_TSYNCTXCTL_ENABLED; 957 regval |= tsync_tx_ctl; 958 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, regval); 959 960 /* enable/disable RX */ 961 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL); 962 regval &= ~(IXGBE_TSYNCRXCTL_ENABLED | IXGBE_TSYNCRXCTL_TYPE_MASK); 963 regval |= tsync_rx_ctl; 964 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, regval); 965 966 /* define which PTP packets are time stamped */ 967 IXGBE_WRITE_REG(hw, IXGBE_RXMTRL, tsync_rx_mtrl); 968 969 IXGBE_WRITE_FLUSH(hw); 970 971 /* clear TX/RX time stamp registers, just to be sure */ 972 ixgbe_ptp_clear_tx_timestamp(adapter); 973 IXGBE_READ_REG(hw, IXGBE_RXSTMPH); 974 975 return 0; 976 } 977 978 /** 979 * ixgbe_ptp_set_ts_config - user entry point for timestamp mode 980 * @adapter: pointer to adapter struct 981 * @ifreq: ioctl data 982 * 983 * Set hardware to requested mode. If unsupported, return an error with no 984 * changes. Otherwise, store the mode for future reference. 985 */ 986 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr) 987 { 988 struct hwtstamp_config config; 989 int err; 990 991 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 992 return -EFAULT; 993 994 err = ixgbe_ptp_set_timestamp_mode(adapter, &config); 995 if (err) 996 return err; 997 998 /* save these settings for future reference */ 999 memcpy(&adapter->tstamp_config, &config, 1000 sizeof(adapter->tstamp_config)); 1001 1002 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 1003 -EFAULT : 0; 1004 } 1005 1006 static void ixgbe_ptp_link_speed_adjust(struct ixgbe_adapter *adapter, 1007 u32 *shift, u32 *incval) 1008 { 1009 /** 1010 * Scale the NIC cycle counter by a large factor so that 1011 * relatively small corrections to the frequency can be added 1012 * or subtracted. The drawbacks of a large factor include 1013 * (a) the clock register overflows more quickly, (b) the cycle 1014 * counter structure must be able to convert the systime value 1015 * to nanoseconds using only a multiplier and a right-shift, 1016 * and (c) the value must fit within the timinca register space 1017 * => math based on internal DMA clock rate and available bits 1018 * 1019 * Note that when there is no link, internal DMA clock is same as when 1020 * link speed is 10Gb. Set the registers correctly even when link is 1021 * down to preserve the clock setting 1022 */ 1023 switch (adapter->link_speed) { 1024 case IXGBE_LINK_SPEED_100_FULL: 1025 *shift = IXGBE_INCVAL_SHIFT_100; 1026 *incval = IXGBE_INCVAL_100; 1027 break; 1028 case IXGBE_LINK_SPEED_1GB_FULL: 1029 *shift = IXGBE_INCVAL_SHIFT_1GB; 1030 *incval = IXGBE_INCVAL_1GB; 1031 break; 1032 case IXGBE_LINK_SPEED_10GB_FULL: 1033 default: 1034 *shift = IXGBE_INCVAL_SHIFT_10GB; 1035 *incval = IXGBE_INCVAL_10GB; 1036 break; 1037 } 1038 } 1039 1040 /** 1041 * ixgbe_ptp_start_cyclecounter - create the cycle counter from hw 1042 * @adapter: pointer to the adapter structure 1043 * 1044 * This function should be called to set the proper values for the TIMINCA 1045 * register and tell the cyclecounter structure what the tick rate of SYSTIME 1046 * is. It does not directly modify SYSTIME registers or the timecounter 1047 * structure. It should be called whenever a new TIMINCA value is necessary, 1048 * such as during initialization or when the link speed changes. 1049 */ 1050 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter) 1051 { 1052 struct ixgbe_hw *hw = &adapter->hw; 1053 struct cyclecounter cc; 1054 unsigned long flags; 1055 u32 incval = 0; 1056 u32 tsauxc = 0; 1057 u32 fuse0 = 0; 1058 1059 /* For some of the boards below this mask is technically incorrect. 1060 * The timestamp mask overflows at approximately 61bits. However the 1061 * particular hardware does not overflow on an even bitmask value. 1062 * Instead, it overflows due to conversion of upper 32bits billions of 1063 * cycles. Timecounters are not really intended for this purpose so 1064 * they do not properly function if the overflow point isn't 2^N-1. 1065 * However, the actual SYSTIME values in question take ~138 years to 1066 * overflow. In practice this means they won't actually overflow. A 1067 * proper fix to this problem would require modification of the 1068 * timecounter delta calculations. 1069 */ 1070 cc.mask = CLOCKSOURCE_MASK(64); 1071 cc.mult = 1; 1072 cc.shift = 0; 1073 1074 switch (hw->mac.type) { 1075 case ixgbe_mac_X550EM_x: 1076 /* SYSTIME assumes X550EM_x board frequency is 300Mhz, and is 1077 * designed to represent seconds and nanoseconds when this is 1078 * the case. However, some revisions of hardware have a 400Mhz 1079 * clock and we have to compensate for this frequency 1080 * variation using corrected mult and shift values. 1081 */ 1082 fuse0 = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)); 1083 if (!(fuse0 & IXGBE_FUSES0_300MHZ)) { 1084 cc.mult = 3; 1085 cc.shift = 2; 1086 } 1087 /* fallthrough */ 1088 case ixgbe_mac_x550em_a: 1089 case ixgbe_mac_X550: 1090 cc.read = ixgbe_ptp_read_X550; 1091 1092 /* enable SYSTIME counter */ 1093 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMR, 0); 1094 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0); 1095 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0); 1096 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC); 1097 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 1098 tsauxc & ~IXGBE_TSAUXC_DISABLE_SYSTIME); 1099 IXGBE_WRITE_REG(hw, IXGBE_TSIM, IXGBE_TSIM_TXTS); 1100 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_TIMESYNC); 1101 1102 IXGBE_WRITE_FLUSH(hw); 1103 break; 1104 case ixgbe_mac_X540: 1105 cc.read = ixgbe_ptp_read_82599; 1106 1107 ixgbe_ptp_link_speed_adjust(adapter, &cc.shift, &incval); 1108 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval); 1109 break; 1110 case ixgbe_mac_82599EB: 1111 cc.read = ixgbe_ptp_read_82599; 1112 1113 ixgbe_ptp_link_speed_adjust(adapter, &cc.shift, &incval); 1114 incval >>= IXGBE_INCVAL_SHIFT_82599; 1115 cc.shift -= IXGBE_INCVAL_SHIFT_82599; 1116 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 1117 BIT(IXGBE_INCPER_SHIFT_82599) | incval); 1118 break; 1119 default: 1120 /* other devices aren't supported */ 1121 return; 1122 } 1123 1124 /* update the base incval used to calculate frequency adjustment */ 1125 ACCESS_ONCE(adapter->base_incval) = incval; 1126 smp_mb(); 1127 1128 /* need lock to prevent incorrect read while modifying cyclecounter */ 1129 spin_lock_irqsave(&adapter->tmreg_lock, flags); 1130 memcpy(&adapter->hw_cc, &cc, sizeof(adapter->hw_cc)); 1131 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 1132 } 1133 1134 /** 1135 * ixgbe_ptp_reset 1136 * @adapter: the ixgbe private board structure 1137 * 1138 * When the MAC resets, all the hardware bits for timesync are reset. This 1139 * function is used to re-enable the device for PTP based on current settings. 1140 * We do lose the current clock time, so just reset the cyclecounter to the 1141 * system real clock time. 1142 * 1143 * This function will maintain hwtstamp_config settings, and resets the SDP 1144 * output if it was enabled. 1145 */ 1146 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter) 1147 { 1148 struct ixgbe_hw *hw = &adapter->hw; 1149 unsigned long flags; 1150 1151 /* reset the hardware timestamping mode */ 1152 ixgbe_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config); 1153 1154 /* 82598 does not support PTP */ 1155 if (hw->mac.type == ixgbe_mac_82598EB) 1156 return; 1157 1158 ixgbe_ptp_start_cyclecounter(adapter); 1159 1160 spin_lock_irqsave(&adapter->tmreg_lock, flags); 1161 timecounter_init(&adapter->hw_tc, &adapter->hw_cc, 1162 ktime_to_ns(ktime_get_real())); 1163 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 1164 1165 adapter->last_overflow_check = jiffies; 1166 1167 /* Now that the shift has been calculated and the systime 1168 * registers reset, (re-)enable the Clock out feature 1169 */ 1170 if (adapter->ptp_setup_sdp) 1171 adapter->ptp_setup_sdp(adapter); 1172 } 1173 1174 /** 1175 * ixgbe_ptp_create_clock 1176 * @adapter: the ixgbe private adapter structure 1177 * 1178 * This function performs setup of the user entry point function table and 1179 * initializes the PTP clock device, which is used to access the clock-like 1180 * features of the PTP core. It will be called by ixgbe_ptp_init, and may 1181 * reuse a previously initialized clock (such as during a suspend/resume 1182 * cycle). 1183 */ 1184 static long ixgbe_ptp_create_clock(struct ixgbe_adapter *adapter) 1185 { 1186 struct net_device *netdev = adapter->netdev; 1187 long err; 1188 1189 /* do nothing if we already have a clock device */ 1190 if (!IS_ERR_OR_NULL(adapter->ptp_clock)) 1191 return 0; 1192 1193 switch (adapter->hw.mac.type) { 1194 case ixgbe_mac_X540: 1195 snprintf(adapter->ptp_caps.name, 1196 sizeof(adapter->ptp_caps.name), 1197 "%s", netdev->name); 1198 adapter->ptp_caps.owner = THIS_MODULE; 1199 adapter->ptp_caps.max_adj = 250000000; 1200 adapter->ptp_caps.n_alarm = 0; 1201 adapter->ptp_caps.n_ext_ts = 0; 1202 adapter->ptp_caps.n_per_out = 0; 1203 adapter->ptp_caps.pps = 1; 1204 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq_82599; 1205 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime; 1206 adapter->ptp_caps.gettime64 = ixgbe_ptp_gettime; 1207 adapter->ptp_caps.settime64 = ixgbe_ptp_settime; 1208 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable; 1209 adapter->ptp_setup_sdp = ixgbe_ptp_setup_sdp_x540; 1210 break; 1211 case ixgbe_mac_82599EB: 1212 snprintf(adapter->ptp_caps.name, 1213 sizeof(adapter->ptp_caps.name), 1214 "%s", netdev->name); 1215 adapter->ptp_caps.owner = THIS_MODULE; 1216 adapter->ptp_caps.max_adj = 250000000; 1217 adapter->ptp_caps.n_alarm = 0; 1218 adapter->ptp_caps.n_ext_ts = 0; 1219 adapter->ptp_caps.n_per_out = 0; 1220 adapter->ptp_caps.pps = 0; 1221 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq_82599; 1222 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime; 1223 adapter->ptp_caps.gettime64 = ixgbe_ptp_gettime; 1224 adapter->ptp_caps.settime64 = ixgbe_ptp_settime; 1225 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable; 1226 break; 1227 case ixgbe_mac_X550: 1228 case ixgbe_mac_X550EM_x: 1229 case ixgbe_mac_x550em_a: 1230 snprintf(adapter->ptp_caps.name, 16, "%s", netdev->name); 1231 adapter->ptp_caps.owner = THIS_MODULE; 1232 adapter->ptp_caps.max_adj = 30000000; 1233 adapter->ptp_caps.n_alarm = 0; 1234 adapter->ptp_caps.n_ext_ts = 0; 1235 adapter->ptp_caps.n_per_out = 0; 1236 adapter->ptp_caps.pps = 0; 1237 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq_X550; 1238 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime; 1239 adapter->ptp_caps.gettime64 = ixgbe_ptp_gettime; 1240 adapter->ptp_caps.settime64 = ixgbe_ptp_settime; 1241 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable; 1242 adapter->ptp_setup_sdp = NULL; 1243 break; 1244 default: 1245 adapter->ptp_clock = NULL; 1246 adapter->ptp_setup_sdp = NULL; 1247 return -EOPNOTSUPP; 1248 } 1249 1250 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps, 1251 &adapter->pdev->dev); 1252 if (IS_ERR(adapter->ptp_clock)) { 1253 err = PTR_ERR(adapter->ptp_clock); 1254 adapter->ptp_clock = NULL; 1255 e_dev_err("ptp_clock_register failed\n"); 1256 return err; 1257 } else if (adapter->ptp_clock) 1258 e_dev_info("registered PHC device on %s\n", netdev->name); 1259 1260 /* set default timestamp mode to disabled here. We do this in 1261 * create_clock instead of init, because we don't want to override the 1262 * previous settings during a resume cycle. 1263 */ 1264 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; 1265 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF; 1266 1267 return 0; 1268 } 1269 1270 /** 1271 * ixgbe_ptp_init 1272 * @adapter: the ixgbe private adapter structure 1273 * 1274 * This function performs the required steps for enabling PTP 1275 * support. If PTP support has already been loaded it simply calls the 1276 * cyclecounter init routine and exits. 1277 */ 1278 void ixgbe_ptp_init(struct ixgbe_adapter *adapter) 1279 { 1280 /* initialize the spin lock first since we can't control when a user 1281 * will call the entry functions once we have initialized the clock 1282 * device 1283 */ 1284 spin_lock_init(&adapter->tmreg_lock); 1285 1286 /* obtain a PTP device, or re-use an existing device */ 1287 if (ixgbe_ptp_create_clock(adapter)) 1288 return; 1289 1290 /* we have a clock so we can initialize work now */ 1291 INIT_WORK(&adapter->ptp_tx_work, ixgbe_ptp_tx_hwtstamp_work); 1292 1293 /* reset the PTP related hardware bits */ 1294 ixgbe_ptp_reset(adapter); 1295 1296 /* enter the IXGBE_PTP_RUNNING state */ 1297 set_bit(__IXGBE_PTP_RUNNING, &adapter->state); 1298 1299 return; 1300 } 1301 1302 /** 1303 * ixgbe_ptp_suspend - stop PTP work items 1304 * @ adapter: pointer to adapter struct 1305 * 1306 * this function suspends PTP activity, and prevents more PTP work from being 1307 * generated, but does not destroy the PTP clock device. 1308 */ 1309 void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter) 1310 { 1311 /* Leave the IXGBE_PTP_RUNNING state. */ 1312 if (!test_and_clear_bit(__IXGBE_PTP_RUNNING, &adapter->state)) 1313 return; 1314 1315 adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED; 1316 if (adapter->ptp_setup_sdp) 1317 adapter->ptp_setup_sdp(adapter); 1318 1319 /* ensure that we cancel any pending PTP Tx work item in progress */ 1320 cancel_work_sync(&adapter->ptp_tx_work); 1321 ixgbe_ptp_clear_tx_timestamp(adapter); 1322 } 1323 1324 /** 1325 * ixgbe_ptp_stop - close the PTP device 1326 * @adapter: pointer to adapter struct 1327 * 1328 * completely destroy the PTP device, should only be called when the device is 1329 * being fully closed. 1330 */ 1331 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter) 1332 { 1333 /* first, suspend PTP activity */ 1334 ixgbe_ptp_suspend(adapter); 1335 1336 /* disable the PTP clock device */ 1337 if (adapter->ptp_clock) { 1338 ptp_clock_unregister(adapter->ptp_clock); 1339 adapter->ptp_clock = NULL; 1340 e_dev_info("removed PHC on %s\n", 1341 adapter->netdev->name); 1342 } 1343 } 1344