1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (C) 2021, Intel Corporation. */ 3 4 #include <linux/delay.h> 5 #include <linux/iopoll.h> 6 #include "ice_common.h" 7 #include "ice_ptp_hw.h" 8 #include "ice_ptp_consts.h" 9 #include "ice_cgu_regs.h" 10 11 static struct dpll_pin_frequency ice_cgu_pin_freq_common[] = { 12 DPLL_PIN_FREQUENCY_1PPS, 13 DPLL_PIN_FREQUENCY_10MHZ, 14 }; 15 16 static struct dpll_pin_frequency ice_cgu_pin_freq_1_hz[] = { 17 DPLL_PIN_FREQUENCY_1PPS, 18 }; 19 20 static struct dpll_pin_frequency ice_cgu_pin_freq_10_mhz[] = { 21 DPLL_PIN_FREQUENCY_10MHZ, 22 }; 23 24 static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_inputs[] = { 25 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR, 26 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 27 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR, 28 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 29 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, }, 30 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, }, 31 { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT, 32 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 33 { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT, 34 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 35 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS, 36 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 37 }; 38 39 static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_inputs[] = { 40 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR, 41 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 42 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR, 43 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 44 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, }, 45 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, }, 46 { "C827_1-RCLKA", ZL_REF2P, DPLL_PIN_TYPE_MUX, }, 47 { "C827_1-RCLKB", ZL_REF2N, DPLL_PIN_TYPE_MUX, }, 48 { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT, 49 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 50 { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT, 51 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 52 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS, 53 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 54 }; 55 56 static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_outputs[] = { 57 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT, 58 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 59 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT, 60 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 61 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, }, 62 { "MAC-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, }, 63 { "CVL-SDP21", ZL_OUT4, DPLL_PIN_TYPE_EXT, 64 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 65 { "CVL-SDP23", ZL_OUT5, DPLL_PIN_TYPE_EXT, 66 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 67 }; 68 69 static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_outputs[] = { 70 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT, 71 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 72 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT, 73 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 74 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 75 { "PHY2-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 76 { "MAC-CLK", ZL_OUT4, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 77 { "CVL-SDP21", ZL_OUT5, DPLL_PIN_TYPE_EXT, 78 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 79 { "CVL-SDP23", ZL_OUT6, DPLL_PIN_TYPE_EXT, 80 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 81 }; 82 83 static const struct ice_cgu_pin_desc ice_e823_si_cgu_inputs[] = { 84 { "NONE", SI_REF0P, 0, 0 }, 85 { "NONE", SI_REF0N, 0, 0 }, 86 { "SYNCE0_DP", SI_REF1P, DPLL_PIN_TYPE_MUX, 0 }, 87 { "SYNCE0_DN", SI_REF1N, DPLL_PIN_TYPE_MUX, 0 }, 88 { "EXT_CLK_SYNC", SI_REF2P, DPLL_PIN_TYPE_EXT, 89 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 90 { "NONE", SI_REF2N, 0, 0 }, 91 { "EXT_PPS_OUT", SI_REF3, DPLL_PIN_TYPE_EXT, 92 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 93 { "INT_PPS_OUT", SI_REF4, DPLL_PIN_TYPE_EXT, 94 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 95 }; 96 97 static const struct ice_cgu_pin_desc ice_e823_si_cgu_outputs[] = { 98 { "1588-TIME_SYNC", SI_OUT0, DPLL_PIN_TYPE_EXT, 99 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 100 { "PHY-CLK", SI_OUT1, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 101 { "10MHZ-SMA2", SI_OUT2, DPLL_PIN_TYPE_EXT, 102 ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz }, 103 { "PPS-SMA1", SI_OUT3, DPLL_PIN_TYPE_EXT, 104 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 105 }; 106 107 static const struct ice_cgu_pin_desc ice_e823_zl_cgu_inputs[] = { 108 { "NONE", ZL_REF0P, 0, 0 }, 109 { "INT_PPS_OUT", ZL_REF0N, DPLL_PIN_TYPE_EXT, 110 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 111 { "SYNCE0_DP", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0 }, 112 { "SYNCE0_DN", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0 }, 113 { "NONE", ZL_REF2P, 0, 0 }, 114 { "NONE", ZL_REF2N, 0, 0 }, 115 { "EXT_CLK_SYNC", ZL_REF3P, DPLL_PIN_TYPE_EXT, 116 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 117 { "NONE", ZL_REF3N, 0, 0 }, 118 { "EXT_PPS_OUT", ZL_REF4P, DPLL_PIN_TYPE_EXT, 119 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 120 { "OCXO", ZL_REF4N, DPLL_PIN_TYPE_INT_OSCILLATOR, 0 }, 121 }; 122 123 static const struct ice_cgu_pin_desc ice_e823_zl_cgu_outputs[] = { 124 { "PPS-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT, 125 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 126 { "10MHZ-SMA2", ZL_OUT1, DPLL_PIN_TYPE_EXT, 127 ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz }, 128 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 129 { "1588-TIME_REF", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 130 { "CPK-TIME_SYNC", ZL_OUT4, DPLL_PIN_TYPE_EXT, 131 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 132 { "NONE", ZL_OUT5, 0, 0 }, 133 }; 134 135 /* Low level functions for interacting with and managing the device clock used 136 * for the Precision Time Protocol. 137 * 138 * The ice hardware represents the current time using three registers: 139 * 140 * GLTSYN_TIME_H GLTSYN_TIME_L GLTSYN_TIME_R 141 * +---------------+ +---------------+ +---------------+ 142 * | 32 bits | | 32 bits | | 32 bits | 143 * +---------------+ +---------------+ +---------------+ 144 * 145 * The registers are incremented every clock tick using a 40bit increment 146 * value defined over two registers: 147 * 148 * GLTSYN_INCVAL_H GLTSYN_INCVAL_L 149 * +---------------+ +---------------+ 150 * | 8 bit s | | 32 bits | 151 * +---------------+ +---------------+ 152 * 153 * The increment value is added to the GLSTYN_TIME_R and GLSTYN_TIME_L 154 * registers every clock source tick. Depending on the specific device 155 * configuration, the clock source frequency could be one of a number of 156 * values. 157 * 158 * For E810 devices, the increment frequency is 812.5 MHz 159 * 160 * For E822 devices the clock can be derived from different sources, and the 161 * increment has an effective frequency of one of the following: 162 * - 823.4375 MHz 163 * - 783.36 MHz 164 * - 796.875 MHz 165 * - 816 MHz 166 * - 830.078125 MHz 167 * - 783.36 MHz 168 * 169 * The hardware captures timestamps in the PHY for incoming packets, and for 170 * outgoing packets on request. To support this, the PHY maintains a timer 171 * that matches the lower 64 bits of the global source timer. 172 * 173 * In order to ensure that the PHY timers and the source timer are equivalent, 174 * shadow registers are used to prepare the desired initial values. A special 175 * sync command is issued to trigger copying from the shadow registers into 176 * the appropriate source and PHY registers simultaneously. 177 * 178 * The driver supports devices which have different PHYs with subtly different 179 * mechanisms to program and control the timers. We divide the devices into 180 * families named after the first major device, E810 and similar devices, and 181 * E822 and similar devices. 182 * 183 * - E822 based devices have additional support for fine grained Vernier 184 * calibration which requires significant setup 185 * - The layout of timestamp data in the PHY register blocks is different 186 * - The way timer synchronization commands are issued is different. 187 * 188 * To support this, very low level functions have an e810 or e822 suffix 189 * indicating what type of device they work on. Higher level abstractions for 190 * tasks that can be done on both devices do not have the suffix and will 191 * correctly look up the appropriate low level function when running. 192 * 193 * Functions which only make sense on a single device family may not have 194 * a suitable generic implementation 195 */ 196 197 /** 198 * ice_get_ptp_src_clock_index - determine source clock index 199 * @hw: pointer to HW struct 200 * 201 * Determine the source clock index currently in use, based on device 202 * capabilities reported during initialization. 203 */ 204 u8 ice_get_ptp_src_clock_index(struct ice_hw *hw) 205 { 206 return hw->func_caps.ts_func_info.tmr_index_assoc; 207 } 208 209 /** 210 * ice_ptp_read_src_incval - Read source timer increment value 211 * @hw: pointer to HW struct 212 * 213 * Read the increment value of the source timer and return it. 214 */ 215 static u64 ice_ptp_read_src_incval(struct ice_hw *hw) 216 { 217 u32 lo, hi; 218 u8 tmr_idx; 219 220 tmr_idx = ice_get_ptp_src_clock_index(hw); 221 222 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 223 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 224 225 return ((u64)(hi & INCVAL_HIGH_M) << 32) | lo; 226 } 227 228 /** 229 * ice_read_cgu_reg_e82x - Read a CGU register 230 * @hw: pointer to the HW struct 231 * @addr: Register address to read 232 * @val: storage for register value read 233 * 234 * Read the contents of a register of the Clock Generation Unit. Only 235 * applicable to E822 devices. 236 * 237 * Return: 0 on success, other error codes when failed to read from CGU 238 */ 239 static int ice_read_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 *val) 240 { 241 struct ice_sbq_msg_input cgu_msg = { 242 .opcode = ice_sbq_msg_rd, 243 .dest_dev = cgu, 244 .msg_addr_low = addr 245 }; 246 int err; 247 248 err = ice_sbq_rw_reg(hw, &cgu_msg, ICE_AQ_FLAG_RD); 249 if (err) { 250 ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n", 251 addr, err); 252 return err; 253 } 254 255 *val = cgu_msg.data; 256 257 return 0; 258 } 259 260 /** 261 * ice_write_cgu_reg_e82x - Write a CGU register 262 * @hw: pointer to the HW struct 263 * @addr: Register address to write 264 * @val: value to write into the register 265 * 266 * Write the specified value to a register of the Clock Generation Unit. Only 267 * applicable to E822 devices. 268 * 269 * Return: 0 on success, other error codes when failed to write to CGU 270 */ 271 static int ice_write_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 val) 272 { 273 struct ice_sbq_msg_input cgu_msg = { 274 .opcode = ice_sbq_msg_wr, 275 .dest_dev = cgu, 276 .msg_addr_low = addr, 277 .data = val 278 }; 279 int err; 280 281 err = ice_sbq_rw_reg(hw, &cgu_msg, ICE_AQ_FLAG_RD); 282 if (err) { 283 ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n", 284 addr, err); 285 return err; 286 } 287 288 return err; 289 } 290 291 /** 292 * ice_clk_freq_str - Convert time_ref_freq to string 293 * @clk_freq: Clock frequency 294 * 295 * Return: specified TIME_REF clock frequency converted to a string 296 */ 297 static const char *ice_clk_freq_str(enum ice_time_ref_freq clk_freq) 298 { 299 switch (clk_freq) { 300 case ICE_TIME_REF_FREQ_25_000: 301 return "25 MHz"; 302 case ICE_TIME_REF_FREQ_122_880: 303 return "122.88 MHz"; 304 case ICE_TIME_REF_FREQ_125_000: 305 return "125 MHz"; 306 case ICE_TIME_REF_FREQ_153_600: 307 return "153.6 MHz"; 308 case ICE_TIME_REF_FREQ_156_250: 309 return "156.25 MHz"; 310 case ICE_TIME_REF_FREQ_245_760: 311 return "245.76 MHz"; 312 default: 313 return "Unknown"; 314 } 315 } 316 317 /** 318 * ice_clk_src_str - Convert time_ref_src to string 319 * @clk_src: Clock source 320 * 321 * Return: specified clock source converted to its string name 322 */ 323 static const char *ice_clk_src_str(enum ice_clk_src clk_src) 324 { 325 switch (clk_src) { 326 case ICE_CLK_SRC_TCXO: 327 return "TCXO"; 328 case ICE_CLK_SRC_TIME_REF: 329 return "TIME_REF"; 330 default: 331 return "Unknown"; 332 } 333 } 334 335 /** 336 * ice_cfg_cgu_pll_e82x - Configure the Clock Generation Unit 337 * @hw: pointer to the HW struct 338 * @clk_freq: Clock frequency to program 339 * @clk_src: Clock source to select (TIME_REF, or TCXO) 340 * 341 * Configure the Clock Generation Unit with the desired clock frequency and 342 * time reference, enabling the PLL which drives the PTP hardware clock. 343 * 344 * Return: 345 * * %0 - success 346 * * %-EINVAL - input parameters are incorrect 347 * * %-EBUSY - failed to lock TS PLL 348 * * %other - CGU read/write failure 349 */ 350 static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw, 351 enum ice_time_ref_freq clk_freq, 352 enum ice_clk_src clk_src) 353 { 354 union tspll_ro_bwm_lf bwm_lf; 355 union nac_cgu_dword19 dw19; 356 union nac_cgu_dword22 dw22; 357 union nac_cgu_dword24 dw24; 358 union nac_cgu_dword9 dw9; 359 int err; 360 361 if (clk_freq >= NUM_ICE_TIME_REF_FREQ) { 362 dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n", 363 clk_freq); 364 return -EINVAL; 365 } 366 367 if (clk_src >= NUM_ICE_CLK_SRC) { 368 dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n", 369 clk_src); 370 return -EINVAL; 371 } 372 373 if (clk_src == ICE_CLK_SRC_TCXO && 374 clk_freq != ICE_TIME_REF_FREQ_25_000) { 375 dev_warn(ice_hw_to_dev(hw), 376 "TCXO only supports 25 MHz frequency\n"); 377 return -EINVAL; 378 } 379 380 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val); 381 if (err) 382 return err; 383 384 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val); 385 if (err) 386 return err; 387 388 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val); 389 if (err) 390 return err; 391 392 /* Log the current clock configuration */ 393 ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", 394 str_enabled_disabled(dw24.ts_pll_enable), 395 ice_clk_src_str(dw24.time_ref_sel), 396 ice_clk_freq_str(dw9.time_ref_freq_sel), 397 bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked"); 398 399 /* Disable the PLL before changing the clock source or frequency */ 400 if (dw24.ts_pll_enable) { 401 dw24.ts_pll_enable = 0; 402 403 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val); 404 if (err) 405 return err; 406 } 407 408 /* Set the frequency */ 409 dw9.time_ref_freq_sel = clk_freq; 410 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val); 411 if (err) 412 return err; 413 414 /* Configure the TS PLL feedback divisor */ 415 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val); 416 if (err) 417 return err; 418 419 dw19.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div; 420 dw19.tspll_ndivratio = 1; 421 422 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val); 423 if (err) 424 return err; 425 426 /* Configure the TS PLL post divisor */ 427 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val); 428 if (err) 429 return err; 430 431 dw22.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div; 432 dw22.time1588clk_sel_div2 = 0; 433 434 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val); 435 if (err) 436 return err; 437 438 /* Configure the TS PLL pre divisor and clock source */ 439 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val); 440 if (err) 441 return err; 442 443 dw24.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div; 444 dw24.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div; 445 dw24.time_ref_sel = clk_src; 446 447 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val); 448 if (err) 449 return err; 450 451 /* Finally, enable the PLL */ 452 dw24.ts_pll_enable = 1; 453 454 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val); 455 if (err) 456 return err; 457 458 /* Wait to verify if the PLL locks */ 459 usleep_range(1000, 5000); 460 461 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val); 462 if (err) 463 return err; 464 465 if (!bwm_lf.plllock_true_lock_cri) { 466 dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n"); 467 return -EBUSY; 468 } 469 470 /* Log the current clock configuration */ 471 ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", 472 str_enabled_disabled(dw24.ts_pll_enable), 473 ice_clk_src_str(dw24.time_ref_sel), 474 ice_clk_freq_str(dw9.time_ref_freq_sel), 475 bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked"); 476 477 return 0; 478 } 479 480 /** 481 * ice_cfg_cgu_pll_e825c - Configure the Clock Generation Unit for E825-C 482 * @hw: pointer to the HW struct 483 * @clk_freq: Clock frequency to program 484 * @clk_src: Clock source to select (TIME_REF, or TCXO) 485 * 486 * Configure the Clock Generation Unit with the desired clock frequency and 487 * time reference, enabling the PLL which drives the PTP hardware clock. 488 * 489 * Return: 490 * * %0 - success 491 * * %-EINVAL - input parameters are incorrect 492 * * %-EBUSY - failed to lock TS PLL 493 * * %other - CGU read/write failure 494 */ 495 static int ice_cfg_cgu_pll_e825c(struct ice_hw *hw, 496 enum ice_time_ref_freq clk_freq, 497 enum ice_clk_src clk_src) 498 { 499 union tspll_ro_lock_e825c ro_lock; 500 union nac_cgu_dword16_e825c dw16; 501 union nac_cgu_dword23_e825c dw23; 502 union nac_cgu_dword19 dw19; 503 union nac_cgu_dword22 dw22; 504 union nac_cgu_dword24 dw24; 505 union nac_cgu_dword9 dw9; 506 int err; 507 508 if (clk_freq >= NUM_ICE_TIME_REF_FREQ) { 509 dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n", 510 clk_freq); 511 return -EINVAL; 512 } 513 514 if (clk_src >= NUM_ICE_CLK_SRC) { 515 dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n", 516 clk_src); 517 return -EINVAL; 518 } 519 520 if (clk_src == ICE_CLK_SRC_TCXO && 521 clk_freq != ICE_TIME_REF_FREQ_156_250) { 522 dev_warn(ice_hw_to_dev(hw), 523 "TCXO only supports 156.25 MHz frequency\n"); 524 return -EINVAL; 525 } 526 527 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val); 528 if (err) 529 return err; 530 531 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val); 532 if (err) 533 return err; 534 535 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD16_E825C, &dw16.val); 536 if (err) 537 return err; 538 539 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val); 540 if (err) 541 return err; 542 543 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val); 544 if (err) 545 return err; 546 547 /* Log the current clock configuration */ 548 ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", 549 str_enabled_disabled(dw24.ts_pll_enable), 550 ice_clk_src_str(dw23.time_ref_sel), 551 ice_clk_freq_str(dw9.time_ref_freq_sel), 552 ro_lock.plllock_true_lock_cri ? "locked" : "unlocked"); 553 554 /* Disable the PLL before changing the clock source or frequency */ 555 if (dw23.ts_pll_enable) { 556 dw23.ts_pll_enable = 0; 557 558 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, 559 dw23.val); 560 if (err) 561 return err; 562 } 563 564 /* Set the frequency */ 565 dw9.time_ref_freq_sel = clk_freq; 566 567 /* Enable the correct receiver */ 568 if (clk_src == ICE_CLK_SRC_TCXO) { 569 dw9.time_ref_en = 0; 570 dw9.clk_eref0_en = 1; 571 } else { 572 dw9.time_ref_en = 1; 573 dw9.clk_eref0_en = 0; 574 } 575 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val); 576 if (err) 577 return err; 578 579 /* Choose the referenced frequency */ 580 dw16.tspll_ck_refclkfreq = 581 e825c_cgu_params[clk_freq].tspll_ck_refclkfreq; 582 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD16_E825C, dw16.val); 583 if (err) 584 return err; 585 586 /* Configure the TS PLL feedback divisor */ 587 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val); 588 if (err) 589 return err; 590 591 dw19.tspll_fbdiv_intgr = 592 e825c_cgu_params[clk_freq].tspll_fbdiv_intgr; 593 dw19.tspll_ndivratio = 594 e825c_cgu_params[clk_freq].tspll_ndivratio; 595 596 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val); 597 if (err) 598 return err; 599 600 /* Configure the TS PLL post divisor */ 601 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val); 602 if (err) 603 return err; 604 605 /* These two are constant for E825C */ 606 dw22.time1588clk_div = 5; 607 dw22.time1588clk_sel_div2 = 0; 608 609 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val); 610 if (err) 611 return err; 612 613 /* Configure the TS PLL pre divisor and clock source */ 614 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val); 615 if (err) 616 return err; 617 618 dw23.ref1588_ck_div = 619 e825c_cgu_params[clk_freq].ref1588_ck_div; 620 dw23.time_ref_sel = clk_src; 621 622 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val); 623 if (err) 624 return err; 625 626 dw24.tspll_fbdiv_frac = 627 e825c_cgu_params[clk_freq].tspll_fbdiv_frac; 628 629 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val); 630 if (err) 631 return err; 632 633 /* Finally, enable the PLL */ 634 dw23.ts_pll_enable = 1; 635 636 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val); 637 if (err) 638 return err; 639 640 /* Wait to verify if the PLL locks */ 641 usleep_range(1000, 5000); 642 643 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val); 644 if (err) 645 return err; 646 647 if (!ro_lock.plllock_true_lock_cri) { 648 dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n"); 649 return -EBUSY; 650 } 651 652 /* Log the current clock configuration */ 653 ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", 654 str_enabled_disabled(dw24.ts_pll_enable), 655 ice_clk_src_str(dw23.time_ref_sel), 656 ice_clk_freq_str(dw9.time_ref_freq_sel), 657 ro_lock.plllock_true_lock_cri ? "locked" : "unlocked"); 658 659 return 0; 660 } 661 662 #define ICE_ONE_PPS_OUT_AMP_MAX 3 663 664 /** 665 * ice_cgu_cfg_pps_out - Configure 1PPS output from CGU 666 * @hw: pointer to the HW struct 667 * @enable: true to enable 1PPS output, false to disable it 668 * 669 * Return: 0 on success, other negative error code when CGU read/write failed 670 */ 671 int ice_cgu_cfg_pps_out(struct ice_hw *hw, bool enable) 672 { 673 union nac_cgu_dword9 dw9; 674 int err; 675 676 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val); 677 if (err) 678 return err; 679 680 dw9.one_pps_out_en = enable; 681 dw9.one_pps_out_amp = enable * ICE_ONE_PPS_OUT_AMP_MAX; 682 return ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val); 683 } 684 685 /** 686 * ice_cfg_cgu_pll_dis_sticky_bits_e82x - disable TS PLL sticky bits 687 * @hw: pointer to the HW struct 688 * 689 * Configure the Clock Generation Unit TS PLL sticky bits so they don't latch on 690 * losing TS PLL lock, but always show current state. 691 * 692 * Return: 0 on success, other error codes when failed to read/write CGU 693 */ 694 static int ice_cfg_cgu_pll_dis_sticky_bits_e82x(struct ice_hw *hw) 695 { 696 union tspll_cntr_bist_settings cntr_bist; 697 int err; 698 699 err = ice_read_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS, 700 &cntr_bist.val); 701 if (err) 702 return err; 703 704 /* Disable sticky lock detection so lock err reported is accurate */ 705 cntr_bist.i_plllock_sel_0 = 0; 706 cntr_bist.i_plllock_sel_1 = 0; 707 708 return ice_write_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS, 709 cntr_bist.val); 710 } 711 712 /** 713 * ice_cfg_cgu_pll_dis_sticky_bits_e825c - disable TS PLL sticky bits for E825-C 714 * @hw: pointer to the HW struct 715 * 716 * Configure the Clock Generation Unit TS PLL sticky bits so they don't latch on 717 * losing TS PLL lock, but always show current state. 718 * 719 * Return: 0 on success, other error codes when failed to read/write CGU 720 */ 721 static int ice_cfg_cgu_pll_dis_sticky_bits_e825c(struct ice_hw *hw) 722 { 723 union tspll_bw_tdc_e825c bw_tdc; 724 int err; 725 726 err = ice_read_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C, &bw_tdc.val); 727 if (err) 728 return err; 729 730 bw_tdc.i_plllock_sel_1_0 = 0; 731 732 return ice_write_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C, bw_tdc.val); 733 } 734 735 /** 736 * ice_init_cgu_e82x - Initialize CGU with settings from firmware 737 * @hw: pointer to the HW structure 738 * 739 * Initialize the Clock Generation Unit of the E822 device. 740 * 741 * Return: 0 on success, other error codes when failed to read/write/cfg CGU 742 */ 743 static int ice_init_cgu_e82x(struct ice_hw *hw) 744 { 745 struct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info; 746 int err; 747 748 /* Disable sticky lock detection so lock err reported is accurate */ 749 if (hw->mac_type == ICE_MAC_GENERIC_3K_E825) 750 err = ice_cfg_cgu_pll_dis_sticky_bits_e825c(hw); 751 else 752 err = ice_cfg_cgu_pll_dis_sticky_bits_e82x(hw); 753 if (err) 754 return err; 755 756 /* Configure the CGU PLL using the parameters from the function 757 * capabilities. 758 */ 759 if (hw->mac_type == ICE_MAC_GENERIC_3K_E825) 760 err = ice_cfg_cgu_pll_e825c(hw, ts_info->time_ref, 761 (enum ice_clk_src)ts_info->clk_src); 762 else 763 err = ice_cfg_cgu_pll_e82x(hw, ts_info->time_ref, 764 (enum ice_clk_src)ts_info->clk_src); 765 766 return err; 767 } 768 769 /** 770 * ice_ptp_tmr_cmd_to_src_reg - Convert to source timer command value 771 * @hw: pointer to HW struct 772 * @cmd: Timer command 773 * 774 * Return: the source timer command register value for the given PTP timer 775 * command. 776 */ 777 static u32 ice_ptp_tmr_cmd_to_src_reg(struct ice_hw *hw, 778 enum ice_ptp_tmr_cmd cmd) 779 { 780 u32 cmd_val, tmr_idx; 781 782 switch (cmd) { 783 case ICE_PTP_INIT_TIME: 784 cmd_val = GLTSYN_CMD_INIT_TIME; 785 break; 786 case ICE_PTP_INIT_INCVAL: 787 cmd_val = GLTSYN_CMD_INIT_INCVAL; 788 break; 789 case ICE_PTP_ADJ_TIME: 790 cmd_val = GLTSYN_CMD_ADJ_TIME; 791 break; 792 case ICE_PTP_ADJ_TIME_AT_TIME: 793 cmd_val = GLTSYN_CMD_ADJ_INIT_TIME; 794 break; 795 case ICE_PTP_NOP: 796 case ICE_PTP_READ_TIME: 797 cmd_val = GLTSYN_CMD_READ_TIME; 798 break; 799 default: 800 dev_warn(ice_hw_to_dev(hw), 801 "Ignoring unrecognized timer command %u\n", cmd); 802 cmd_val = 0; 803 } 804 805 tmr_idx = ice_get_ptp_src_clock_index(hw); 806 807 return tmr_idx << SEL_CPK_SRC | cmd_val; 808 } 809 810 /** 811 * ice_ptp_tmr_cmd_to_port_reg- Convert to port timer command value 812 * @hw: pointer to HW struct 813 * @cmd: Timer command 814 * 815 * Note that some hardware families use a different command register value for 816 * the PHY ports, while other hardware families use the same register values 817 * as the source timer. 818 * 819 * Return: the PHY port timer command register value for the given PTP timer 820 * command. 821 */ 822 static u32 ice_ptp_tmr_cmd_to_port_reg(struct ice_hw *hw, 823 enum ice_ptp_tmr_cmd cmd) 824 { 825 u32 cmd_val, tmr_idx; 826 827 /* Certain hardware families share the same register values for the 828 * port register and source timer register. 829 */ 830 switch (hw->mac_type) { 831 case ICE_MAC_E810: 832 case ICE_MAC_E830: 833 return ice_ptp_tmr_cmd_to_src_reg(hw, cmd) & TS_CMD_MASK_E810; 834 default: 835 break; 836 } 837 838 switch (cmd) { 839 case ICE_PTP_INIT_TIME: 840 cmd_val = PHY_CMD_INIT_TIME; 841 break; 842 case ICE_PTP_INIT_INCVAL: 843 cmd_val = PHY_CMD_INIT_INCVAL; 844 break; 845 case ICE_PTP_ADJ_TIME: 846 cmd_val = PHY_CMD_ADJ_TIME; 847 break; 848 case ICE_PTP_ADJ_TIME_AT_TIME: 849 cmd_val = PHY_CMD_ADJ_TIME_AT_TIME; 850 break; 851 case ICE_PTP_READ_TIME: 852 cmd_val = PHY_CMD_READ_TIME; 853 break; 854 case ICE_PTP_NOP: 855 cmd_val = 0; 856 break; 857 default: 858 dev_warn(ice_hw_to_dev(hw), 859 "Ignoring unrecognized timer command %u\n", cmd); 860 cmd_val = 0; 861 } 862 863 tmr_idx = ice_get_ptp_src_clock_index(hw); 864 865 return tmr_idx << SEL_PHY_SRC | cmd_val; 866 } 867 868 /** 869 * ice_ptp_src_cmd - Prepare source timer for a timer command 870 * @hw: pointer to HW structure 871 * @cmd: Timer command 872 * 873 * Prepare the source timer for an upcoming timer sync command. 874 */ 875 void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 876 { 877 u32 cmd_val = ice_ptp_tmr_cmd_to_src_reg(hw, cmd); 878 879 wr32(hw, GLTSYN_CMD, cmd_val); 880 } 881 882 /** 883 * ice_ptp_exec_tmr_cmd - Execute all prepared timer commands 884 * @hw: pointer to HW struct 885 * 886 * Write the SYNC_EXEC_CMD bit to the GLTSYN_CMD_SYNC register, and flush the 887 * write immediately. This triggers the hardware to begin executing all of the 888 * source and PHY timer commands synchronously. 889 */ 890 static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw) 891 { 892 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 893 894 guard(spinlock)(&pf->adapter->ptp_gltsyn_time_lock); 895 wr32(hw, GLTSYN_CMD_SYNC, SYNC_EXEC_CMD); 896 ice_flush(hw); 897 } 898 899 /** 900 * ice_ptp_cfg_sync_delay - Configure PHC to PHY synchronization delay 901 * @hw: pointer to HW struct 902 * @delay: delay between PHC and PHY SYNC command execution in nanoseconds 903 */ 904 static void ice_ptp_cfg_sync_delay(const struct ice_hw *hw, u32 delay) 905 { 906 wr32(hw, GLTSYN_SYNC_DLAY, delay); 907 ice_flush(hw); 908 } 909 910 /* 56G PHY device functions 911 * 912 * The following functions operate on devices with the ETH 56G PHY. 913 */ 914 915 /** 916 * ice_ptp_get_dest_dev_e825 - get destination PHY for given port number 917 * @hw: pointer to the HW struct 918 * @port: destination port 919 * 920 * Return: destination sideband queue PHY device. 921 */ 922 static enum ice_sbq_msg_dev ice_ptp_get_dest_dev_e825(struct ice_hw *hw, 923 u8 port) 924 { 925 /* On a single complex E825, PHY 0 is always destination device phy_0 926 * and PHY 1 is phy_0_peer. 927 */ 928 if (port >= hw->ptp.ports_per_phy) 929 return eth56g_phy_1; 930 else 931 return eth56g_phy_0; 932 } 933 934 /** 935 * ice_write_phy_eth56g - Write a PHY port register 936 * @hw: pointer to the HW struct 937 * @port: destination port 938 * @addr: PHY register address 939 * @val: Value to write 940 * 941 * Return: 0 on success, other error codes when failed to write to PHY 942 */ 943 static int ice_write_phy_eth56g(struct ice_hw *hw, u8 port, u32 addr, u32 val) 944 { 945 struct ice_sbq_msg_input msg = { 946 .dest_dev = ice_ptp_get_dest_dev_e825(hw, port), 947 .opcode = ice_sbq_msg_wr, 948 .msg_addr_low = lower_16_bits(addr), 949 .msg_addr_high = upper_16_bits(addr), 950 .data = val 951 }; 952 int err; 953 954 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 955 if (err) 956 ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n", 957 err); 958 959 return err; 960 } 961 962 /** 963 * ice_read_phy_eth56g - Read a PHY port register 964 * @hw: pointer to the HW struct 965 * @port: destination port 966 * @addr: PHY register address 967 * @val: Value to write 968 * 969 * Return: 0 on success, other error codes when failed to read from PHY 970 */ 971 static int ice_read_phy_eth56g(struct ice_hw *hw, u8 port, u32 addr, u32 *val) 972 { 973 struct ice_sbq_msg_input msg = { 974 .dest_dev = ice_ptp_get_dest_dev_e825(hw, port), 975 .opcode = ice_sbq_msg_rd, 976 .msg_addr_low = lower_16_bits(addr), 977 .msg_addr_high = upper_16_bits(addr) 978 }; 979 int err; 980 981 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 982 if (err) 983 ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n", 984 err); 985 else 986 *val = msg.data; 987 988 return err; 989 } 990 991 /** 992 * ice_phy_res_address_eth56g - Calculate a PHY port register address 993 * @hw: pointer to the HW struct 994 * @lane: Lane number to be written 995 * @res_type: resource type (register/memory) 996 * @offset: Offset from PHY port register base 997 * @addr: The result address 998 * 999 * Return: 1000 * * %0 - success 1001 * * %EINVAL - invalid port number or resource type 1002 */ 1003 static int ice_phy_res_address_eth56g(struct ice_hw *hw, u8 lane, 1004 enum eth56g_res_type res_type, 1005 u32 offset, 1006 u32 *addr) 1007 { 1008 if (res_type >= NUM_ETH56G_PHY_RES) 1009 return -EINVAL; 1010 1011 /* Lanes 4..7 are in fact 0..3 on a second PHY */ 1012 lane %= hw->ptp.ports_per_phy; 1013 *addr = eth56g_phy_res[res_type].base[0] + 1014 lane * eth56g_phy_res[res_type].step + offset; 1015 1016 return 0; 1017 } 1018 1019 /** 1020 * ice_write_port_eth56g - Write a PHY port register 1021 * @hw: pointer to the HW struct 1022 * @offset: PHY register offset 1023 * @port: Port number 1024 * @val: Value to write 1025 * @res_type: resource type (register/memory) 1026 * 1027 * Return: 1028 * * %0 - success 1029 * * %EINVAL - invalid port number or resource type 1030 * * %other - failed to write to PHY 1031 */ 1032 static int ice_write_port_eth56g(struct ice_hw *hw, u8 port, u32 offset, 1033 u32 val, enum eth56g_res_type res_type) 1034 { 1035 u32 addr; 1036 int err; 1037 1038 if (port >= hw->ptp.num_lports) 1039 return -EINVAL; 1040 1041 err = ice_phy_res_address_eth56g(hw, port, res_type, offset, &addr); 1042 if (err) 1043 return err; 1044 1045 return ice_write_phy_eth56g(hw, port, addr, val); 1046 } 1047 1048 /** 1049 * ice_read_port_eth56g - Read a PHY port register 1050 * @hw: pointer to the HW struct 1051 * @offset: PHY register offset 1052 * @port: Port number 1053 * @val: Value to write 1054 * @res_type: resource type (register/memory) 1055 * 1056 * Return: 1057 * * %0 - success 1058 * * %EINVAL - invalid port number or resource type 1059 * * %other - failed to read from PHY 1060 */ 1061 static int ice_read_port_eth56g(struct ice_hw *hw, u8 port, u32 offset, 1062 u32 *val, enum eth56g_res_type res_type) 1063 { 1064 u32 addr; 1065 int err; 1066 1067 if (port >= hw->ptp.num_lports) 1068 return -EINVAL; 1069 1070 err = ice_phy_res_address_eth56g(hw, port, res_type, offset, &addr); 1071 if (err) 1072 return err; 1073 1074 return ice_read_phy_eth56g(hw, port, addr, val); 1075 } 1076 1077 /** 1078 * ice_write_ptp_reg_eth56g - Write a PHY port register 1079 * @hw: pointer to the HW struct 1080 * @port: Port number to be written 1081 * @offset: Offset from PHY port register base 1082 * @val: Value to write 1083 * 1084 * Return: 1085 * * %0 - success 1086 * * %EINVAL - invalid port number or resource type 1087 * * %other - failed to write to PHY 1088 */ 1089 static int ice_write_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1090 u32 val) 1091 { 1092 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_PTP); 1093 } 1094 1095 /** 1096 * ice_write_mac_reg_eth56g - Write a MAC PHY port register 1097 * parameter 1098 * @hw: pointer to the HW struct 1099 * @port: Port number to be written 1100 * @offset: Offset from PHY port register base 1101 * @val: Value to write 1102 * 1103 * Return: 1104 * * %0 - success 1105 * * %EINVAL - invalid port number or resource type 1106 * * %other - failed to write to PHY 1107 */ 1108 static int ice_write_mac_reg_eth56g(struct ice_hw *hw, u8 port, u32 offset, 1109 u32 val) 1110 { 1111 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_MAC); 1112 } 1113 1114 /** 1115 * ice_write_xpcs_reg_eth56g - Write a PHY port register 1116 * @hw: pointer to the HW struct 1117 * @port: Port number to be written 1118 * @offset: Offset from PHY port register base 1119 * @val: Value to write 1120 * 1121 * Return: 1122 * * %0 - success 1123 * * %EINVAL - invalid port number or resource type 1124 * * %other - failed to write to PHY 1125 */ 1126 static int ice_write_xpcs_reg_eth56g(struct ice_hw *hw, u8 port, u32 offset, 1127 u32 val) 1128 { 1129 return ice_write_port_eth56g(hw, port, offset, val, 1130 ETH56G_PHY_REG_XPCS); 1131 } 1132 1133 /** 1134 * ice_read_ptp_reg_eth56g - Read a PHY port register 1135 * @hw: pointer to the HW struct 1136 * @port: Port number to be read 1137 * @offset: Offset from PHY port register base 1138 * @val: Pointer to the value to read (out param) 1139 * 1140 * Return: 1141 * * %0 - success 1142 * * %EINVAL - invalid port number or resource type 1143 * * %other - failed to read from PHY 1144 */ 1145 static int ice_read_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1146 u32 *val) 1147 { 1148 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_PTP); 1149 } 1150 1151 /** 1152 * ice_read_mac_reg_eth56g - Read a PHY port register 1153 * @hw: pointer to the HW struct 1154 * @port: Port number to be read 1155 * @offset: Offset from PHY port register base 1156 * @val: Pointer to the value to read (out param) 1157 * 1158 * Return: 1159 * * %0 - success 1160 * * %EINVAL - invalid port number or resource type 1161 * * %other - failed to read from PHY 1162 */ 1163 static int ice_read_mac_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1164 u32 *val) 1165 { 1166 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_MAC); 1167 } 1168 1169 /** 1170 * ice_read_gpcs_reg_eth56g - Read a PHY port register 1171 * @hw: pointer to the HW struct 1172 * @port: Port number to be read 1173 * @offset: Offset from PHY port register base 1174 * @val: Pointer to the value to read (out param) 1175 * 1176 * Return: 1177 * * %0 - success 1178 * * %EINVAL - invalid port number or resource type 1179 * * %other - failed to read from PHY 1180 */ 1181 static int ice_read_gpcs_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1182 u32 *val) 1183 { 1184 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_GPCS); 1185 } 1186 1187 /** 1188 * ice_read_port_mem_eth56g - Read a PHY port memory location 1189 * @hw: pointer to the HW struct 1190 * @port: Port number to be read 1191 * @offset: Offset from PHY port register base 1192 * @val: Pointer to the value to read (out param) 1193 * 1194 * Return: 1195 * * %0 - success 1196 * * %EINVAL - invalid port number or resource type 1197 * * %other - failed to read from PHY 1198 */ 1199 static int ice_read_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1200 u32 *val) 1201 { 1202 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_MEM_PTP); 1203 } 1204 1205 /** 1206 * ice_write_port_mem_eth56g - Write a PHY port memory location 1207 * @hw: pointer to the HW struct 1208 * @port: Port number to be read 1209 * @offset: Offset from PHY port register base 1210 * @val: Pointer to the value to read (out param) 1211 * 1212 * Return: 1213 * * %0 - success 1214 * * %EINVAL - invalid port number or resource type 1215 * * %other - failed to write to PHY 1216 */ 1217 static int ice_write_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1218 u32 val) 1219 { 1220 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_MEM_PTP); 1221 } 1222 1223 /** 1224 * ice_write_quad_ptp_reg_eth56g - Write a PHY quad register 1225 * @hw: pointer to the HW struct 1226 * @offset: PHY register offset 1227 * @port: Port number 1228 * @val: Value to write 1229 * 1230 * Return: 1231 * * %0 - success 1232 * * %EIO - invalid port number or resource type 1233 * * %other - failed to write to PHY 1234 */ 1235 static int ice_write_quad_ptp_reg_eth56g(struct ice_hw *hw, u8 port, 1236 u32 offset, u32 val) 1237 { 1238 u32 addr; 1239 1240 if (port >= hw->ptp.num_lports) 1241 return -EIO; 1242 1243 addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base[0] + offset; 1244 1245 return ice_write_phy_eth56g(hw, port, addr, val); 1246 } 1247 1248 /** 1249 * ice_read_quad_ptp_reg_eth56g - Read a PHY quad register 1250 * @hw: pointer to the HW struct 1251 * @offset: PHY register offset 1252 * @port: Port number 1253 * @val: Value to read 1254 * 1255 * Return: 1256 * * %0 - success 1257 * * %EIO - invalid port number or resource type 1258 * * %other - failed to read from PHY 1259 */ 1260 static int ice_read_quad_ptp_reg_eth56g(struct ice_hw *hw, u8 port, 1261 u32 offset, u32 *val) 1262 { 1263 u32 addr; 1264 1265 if (port >= hw->ptp.num_lports) 1266 return -EIO; 1267 1268 addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base[0] + offset; 1269 1270 return ice_read_phy_eth56g(hw, port, addr, val); 1271 } 1272 1273 /** 1274 * ice_is_64b_phy_reg_eth56g - Check if this is a 64bit PHY register 1275 * @low_addr: the low address to check 1276 * @high_addr: on return, contains the high address of the 64bit register 1277 * 1278 * Write the appropriate high register offset to use. 1279 * 1280 * Return: true if the provided low address is one of the known 64bit PHY values 1281 * represented as two 32bit registers, false otherwise. 1282 */ 1283 static bool ice_is_64b_phy_reg_eth56g(u16 low_addr, u16 *high_addr) 1284 { 1285 switch (low_addr) { 1286 case PHY_REG_TX_TIMER_INC_PRE_L: 1287 *high_addr = PHY_REG_TX_TIMER_INC_PRE_U; 1288 return true; 1289 case PHY_REG_RX_TIMER_INC_PRE_L: 1290 *high_addr = PHY_REG_RX_TIMER_INC_PRE_U; 1291 return true; 1292 case PHY_REG_TX_CAPTURE_L: 1293 *high_addr = PHY_REG_TX_CAPTURE_U; 1294 return true; 1295 case PHY_REG_RX_CAPTURE_L: 1296 *high_addr = PHY_REG_RX_CAPTURE_U; 1297 return true; 1298 case PHY_REG_TOTAL_TX_OFFSET_L: 1299 *high_addr = PHY_REG_TOTAL_TX_OFFSET_U; 1300 return true; 1301 case PHY_REG_TOTAL_RX_OFFSET_L: 1302 *high_addr = PHY_REG_TOTAL_RX_OFFSET_U; 1303 return true; 1304 case PHY_REG_TX_MEMORY_STATUS_L: 1305 *high_addr = PHY_REG_TX_MEMORY_STATUS_U; 1306 return true; 1307 default: 1308 return false; 1309 } 1310 } 1311 1312 /** 1313 * ice_is_40b_phy_reg_eth56g - Check if this is a 40bit PHY register 1314 * @low_addr: the low address to check 1315 * @high_addr: on return, contains the high address of the 40bit value 1316 * 1317 * Write the appropriate high register offset to use. 1318 * 1319 * Return: true if the provided low address is one of the known 40bit PHY 1320 * values split into two registers with the lower 8 bits in the low register and 1321 * the upper 32 bits in the high register, false otherwise. 1322 */ 1323 static bool ice_is_40b_phy_reg_eth56g(u16 low_addr, u16 *high_addr) 1324 { 1325 switch (low_addr) { 1326 case PHY_REG_TIMETUS_L: 1327 *high_addr = PHY_REG_TIMETUS_U; 1328 return true; 1329 case PHY_PCS_REF_TUS_L: 1330 *high_addr = PHY_PCS_REF_TUS_U; 1331 return true; 1332 case PHY_PCS_REF_INC_L: 1333 *high_addr = PHY_PCS_REF_INC_U; 1334 return true; 1335 default: 1336 return false; 1337 } 1338 } 1339 1340 /** 1341 * ice_read_64b_phy_reg_eth56g - Read a 64bit value from PHY registers 1342 * @hw: pointer to the HW struct 1343 * @port: PHY port to read from 1344 * @low_addr: offset of the lower register to read from 1345 * @val: on return, the contents of the 64bit value from the PHY registers 1346 * @res_type: resource type 1347 * 1348 * Check if the caller has specified a known 40 bit register offset and read 1349 * the two registers associated with a 40bit value and return it in the val 1350 * pointer. 1351 * 1352 * Return: 1353 * * %0 - success 1354 * * %EINVAL - not a 64 bit register 1355 * * %other - failed to read from PHY 1356 */ 1357 static int ice_read_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, 1358 u64 *val, enum eth56g_res_type res_type) 1359 { 1360 u16 high_addr; 1361 u32 lo, hi; 1362 int err; 1363 1364 if (!ice_is_64b_phy_reg_eth56g(low_addr, &high_addr)) 1365 return -EINVAL; 1366 1367 err = ice_read_port_eth56g(hw, port, low_addr, &lo, res_type); 1368 if (err) { 1369 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register %#08x\n, err %d", 1370 low_addr, err); 1371 return err; 1372 } 1373 1374 err = ice_read_port_eth56g(hw, port, high_addr, &hi, res_type); 1375 if (err) { 1376 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register %#08x\n, err %d", 1377 high_addr, err); 1378 return err; 1379 } 1380 1381 *val = ((u64)hi << 32) | lo; 1382 1383 return 0; 1384 } 1385 1386 /** 1387 * ice_read_64b_ptp_reg_eth56g - Read a 64bit value from PHY registers 1388 * @hw: pointer to the HW struct 1389 * @port: PHY port to read from 1390 * @low_addr: offset of the lower register to read from 1391 * @val: on return, the contents of the 64bit value from the PHY registers 1392 * 1393 * Check if the caller has specified a known 40 bit register offset and read 1394 * the two registers associated with a 40bit value and return it in the val 1395 * pointer. 1396 * 1397 * Return: 1398 * * %0 - success 1399 * * %EINVAL - not a 64 bit register 1400 * * %other - failed to read from PHY 1401 */ 1402 static int ice_read_64b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, 1403 u64 *val) 1404 { 1405 return ice_read_64b_phy_reg_eth56g(hw, port, low_addr, val, 1406 ETH56G_PHY_REG_PTP); 1407 } 1408 1409 /** 1410 * ice_write_40b_phy_reg_eth56g - Write a 40b value to the PHY 1411 * @hw: pointer to the HW struct 1412 * @port: port to write to 1413 * @low_addr: offset of the low register 1414 * @val: 40b value to write 1415 * @res_type: resource type 1416 * 1417 * Check if the caller has specified a known 40 bit register offset and write 1418 * provided 40b value to the two associated registers by splitting it up into 1419 * two chunks, the lower 8 bits and the upper 32 bits. 1420 * 1421 * Return: 1422 * * %0 - success 1423 * * %EINVAL - not a 40 bit register 1424 * * %other - failed to write to PHY 1425 */ 1426 static int ice_write_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port, 1427 u16 low_addr, u64 val, 1428 enum eth56g_res_type res_type) 1429 { 1430 u16 high_addr; 1431 u32 lo, hi; 1432 int err; 1433 1434 if (!ice_is_40b_phy_reg_eth56g(low_addr, &high_addr)) 1435 return -EINVAL; 1436 1437 lo = FIELD_GET(P_REG_40B_LOW_M, val); 1438 hi = (u32)(val >> P_REG_40B_HIGH_S); 1439 1440 err = ice_write_port_eth56g(hw, port, low_addr, lo, res_type); 1441 if (err) { 1442 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 1443 low_addr, err); 1444 return err; 1445 } 1446 1447 err = ice_write_port_eth56g(hw, port, high_addr, hi, res_type); 1448 if (err) { 1449 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 1450 high_addr, err); 1451 return err; 1452 } 1453 1454 return 0; 1455 } 1456 1457 /** 1458 * ice_write_40b_ptp_reg_eth56g - Write a 40b value to the PHY 1459 * @hw: pointer to the HW struct 1460 * @port: port to write to 1461 * @low_addr: offset of the low register 1462 * @val: 40b value to write 1463 * 1464 * Check if the caller has specified a known 40 bit register offset and write 1465 * provided 40b value to the two associated registers by splitting it up into 1466 * two chunks, the lower 8 bits and the upper 32 bits. 1467 * 1468 * Return: 1469 * * %0 - success 1470 * * %EINVAL - not a 40 bit register 1471 * * %other - failed to write to PHY 1472 */ 1473 static int ice_write_40b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, 1474 u16 low_addr, u64 val) 1475 { 1476 return ice_write_40b_phy_reg_eth56g(hw, port, low_addr, val, 1477 ETH56G_PHY_REG_PTP); 1478 } 1479 1480 /** 1481 * ice_write_64b_phy_reg_eth56g - Write a 64bit value to PHY registers 1482 * @hw: pointer to the HW struct 1483 * @port: PHY port to read from 1484 * @low_addr: offset of the lower register to read from 1485 * @val: the contents of the 64bit value to write to PHY 1486 * @res_type: resource type 1487 * 1488 * Check if the caller has specified a known 64 bit register offset and write 1489 * the 64bit value to the two associated 32bit PHY registers. 1490 * 1491 * Return: 1492 * * %0 - success 1493 * * %EINVAL - not a 64 bit register 1494 * * %other - failed to write to PHY 1495 */ 1496 static int ice_write_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, 1497 u16 low_addr, u64 val, 1498 enum eth56g_res_type res_type) 1499 { 1500 u16 high_addr; 1501 u32 lo, hi; 1502 int err; 1503 1504 if (!ice_is_64b_phy_reg_eth56g(low_addr, &high_addr)) 1505 return -EINVAL; 1506 1507 lo = lower_32_bits(val); 1508 hi = upper_32_bits(val); 1509 1510 err = ice_write_port_eth56g(hw, port, low_addr, lo, res_type); 1511 if (err) { 1512 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 1513 low_addr, err); 1514 return err; 1515 } 1516 1517 err = ice_write_port_eth56g(hw, port, high_addr, hi, res_type); 1518 if (err) { 1519 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 1520 high_addr, err); 1521 return err; 1522 } 1523 1524 return 0; 1525 } 1526 1527 /** 1528 * ice_write_64b_ptp_reg_eth56g - Write a 64bit value to PHY registers 1529 * @hw: pointer to the HW struct 1530 * @port: PHY port to read from 1531 * @low_addr: offset of the lower register to read from 1532 * @val: the contents of the 64bit value to write to PHY 1533 * 1534 * Check if the caller has specified a known 64 bit register offset and write 1535 * the 64bit value to the two associated 32bit PHY registers. 1536 * 1537 * Return: 1538 * * %0 - success 1539 * * %EINVAL - not a 64 bit register 1540 * * %other - failed to write to PHY 1541 */ 1542 static int ice_write_64b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, 1543 u16 low_addr, u64 val) 1544 { 1545 return ice_write_64b_phy_reg_eth56g(hw, port, low_addr, val, 1546 ETH56G_PHY_REG_PTP); 1547 } 1548 1549 /** 1550 * ice_read_ptp_tstamp_eth56g - Read a PHY timestamp out of the port memory 1551 * @hw: pointer to the HW struct 1552 * @port: the port to read from 1553 * @idx: the timestamp index to read 1554 * @tstamp: on return, the 40bit timestamp value 1555 * 1556 * Read a 40bit timestamp value out of the two associated entries in the 1557 * port memory block of the internal PHYs of the 56G devices. 1558 * 1559 * Return: 1560 * * %0 - success 1561 * * %other - failed to read from PHY 1562 */ 1563 static int ice_read_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx, 1564 u64 *tstamp) 1565 { 1566 u16 lo_addr, hi_addr; 1567 u32 lo, hi; 1568 int err; 1569 1570 lo_addr = (u16)PHY_TSTAMP_L(idx); 1571 hi_addr = (u16)PHY_TSTAMP_U(idx); 1572 1573 err = ice_read_port_mem_eth56g(hw, port, lo_addr, &lo); 1574 if (err) { 1575 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 1576 err); 1577 return err; 1578 } 1579 1580 err = ice_read_port_mem_eth56g(hw, port, hi_addr, &hi); 1581 if (err) { 1582 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 1583 err); 1584 return err; 1585 } 1586 1587 /* For 56G based internal PHYs, the timestamp is reported with the 1588 * lower 8 bits in the low register, and the upper 32 bits in the high 1589 * register. 1590 */ 1591 *tstamp = FIELD_PREP(PHY_40B_HIGH_M, hi) | 1592 FIELD_PREP(PHY_40B_LOW_M, lo); 1593 return 0; 1594 } 1595 1596 /** 1597 * ice_clear_ptp_tstamp_eth56g - Clear a timestamp from the quad block 1598 * @hw: pointer to the HW struct 1599 * @port: the quad to read from 1600 * @idx: the timestamp index to reset 1601 * 1602 * Read and then forcibly clear the timestamp index to ensure the valid bit is 1603 * cleared and the timestamp status bit is reset in the PHY port memory of 1604 * internal PHYs of the 56G devices. 1605 * 1606 * To directly clear the contents of the timestamp block entirely, discarding 1607 * all timestamp data at once, software should instead use 1608 * ice_ptp_reset_ts_memory_quad_eth56g(). 1609 * 1610 * This function should only be called on an idx whose bit is set according to 1611 * ice_get_phy_tx_tstamp_ready(). 1612 * 1613 * Return: 1614 * * %0 - success 1615 * * %other - failed to write to PHY 1616 */ 1617 static int ice_clear_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx) 1618 { 1619 u64 unused_tstamp; 1620 u16 lo_addr; 1621 int err; 1622 1623 /* Read the timestamp register to ensure the timestamp status bit is 1624 * cleared. 1625 */ 1626 err = ice_read_ptp_tstamp_eth56g(hw, port, idx, &unused_tstamp); 1627 if (err) { 1628 ice_debug(hw, ICE_DBG_PTP, "Failed to read the PHY timestamp register for port %u, idx %u, err %d\n", 1629 port, idx, err); 1630 } 1631 1632 lo_addr = (u16)PHY_TSTAMP_L(idx); 1633 1634 err = ice_write_port_mem_eth56g(hw, port, lo_addr, 0); 1635 if (err) { 1636 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for port %u, idx %u, err %d\n", 1637 port, idx, err); 1638 return err; 1639 } 1640 1641 return 0; 1642 } 1643 1644 /** 1645 * ice_ptp_reset_ts_memory_eth56g - Clear all timestamps from the port block 1646 * @hw: pointer to the HW struct 1647 */ 1648 static void ice_ptp_reset_ts_memory_eth56g(struct ice_hw *hw) 1649 { 1650 unsigned int port; 1651 1652 for (port = 0; port < hw->ptp.num_lports; port++) { 1653 ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L, 1654 0); 1655 ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_U, 1656 0); 1657 } 1658 } 1659 1660 /** 1661 * ice_ptp_prep_port_time_eth56g - Prepare one PHY port with initial time 1662 * @hw: pointer to the HW struct 1663 * @port: port number 1664 * @time: time to initialize the PHY port clocks to 1665 * 1666 * Write a new initial time value into registers of a specific PHY port. 1667 * 1668 * Return: 1669 * * %0 - success 1670 * * %other - failed to write to PHY 1671 */ 1672 static int ice_ptp_prep_port_time_eth56g(struct ice_hw *hw, u8 port, 1673 u64 time) 1674 { 1675 int err; 1676 1677 /* Tx case */ 1678 err = ice_write_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_L, 1679 time); 1680 if (err) 1681 return err; 1682 1683 /* Rx case */ 1684 return ice_write_64b_ptp_reg_eth56g(hw, port, 1685 PHY_REG_RX_TIMER_INC_PRE_L, time); 1686 } 1687 1688 /** 1689 * ice_ptp_prep_phy_time_eth56g - Prepare PHY port with initial time 1690 * @hw: pointer to the HW struct 1691 * @time: Time to initialize the PHY port clocks to 1692 * 1693 * Program the PHY port registers with a new initial time value. The port 1694 * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync 1695 * command. The time value is the upper 32 bits of the PHY timer, usually in 1696 * units of nominal nanoseconds. 1697 * 1698 * Return: 1699 * * %0 - success 1700 * * %other - failed to write to PHY 1701 */ 1702 static int ice_ptp_prep_phy_time_eth56g(struct ice_hw *hw, u32 time) 1703 { 1704 u64 phy_time; 1705 u8 port; 1706 1707 /* The time represents the upper 32 bits of the PHY timer, so we need 1708 * to shift to account for this when programming. 1709 */ 1710 phy_time = (u64)time << 32; 1711 1712 for (port = 0; port < hw->ptp.num_lports; port++) { 1713 int err; 1714 1715 err = ice_ptp_prep_port_time_eth56g(hw, port, phy_time); 1716 if (err) { 1717 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n", 1718 port, err); 1719 return err; 1720 } 1721 } 1722 1723 return 0; 1724 } 1725 1726 /** 1727 * ice_ptp_prep_port_adj_eth56g - Prepare a single port for time adjust 1728 * @hw: pointer to HW struct 1729 * @port: Port number to be programmed 1730 * @time: time in cycles to adjust the port clocks 1731 * 1732 * Program the port for an atomic adjustment by writing the Tx and Rx timer 1733 * registers. The atomic adjustment won't be completed until the driver issues 1734 * an ICE_PTP_ADJ_TIME command. 1735 * 1736 * Note that time is not in units of nanoseconds. It is in clock time 1737 * including the lower sub-nanosecond portion of the port timer. 1738 * 1739 * Negative adjustments are supported using 2s complement arithmetic. 1740 * 1741 * Return: 1742 * * %0 - success 1743 * * %other - failed to write to PHY 1744 */ 1745 static int ice_ptp_prep_port_adj_eth56g(struct ice_hw *hw, u8 port, s64 time) 1746 { 1747 u32 l_time, u_time; 1748 int err; 1749 1750 l_time = lower_32_bits(time); 1751 u_time = upper_32_bits(time); 1752 1753 /* Tx case */ 1754 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_L, 1755 l_time); 1756 if (err) 1757 goto exit_err; 1758 1759 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_U, 1760 u_time); 1761 if (err) 1762 goto exit_err; 1763 1764 /* Rx case */ 1765 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TIMER_INC_PRE_L, 1766 l_time); 1767 if (err) 1768 goto exit_err; 1769 1770 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TIMER_INC_PRE_U, 1771 u_time); 1772 if (err) 1773 goto exit_err; 1774 1775 return 0; 1776 1777 exit_err: 1778 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n", 1779 port, err); 1780 return err; 1781 } 1782 1783 /** 1784 * ice_ptp_prep_phy_adj_eth56g - Prep PHY ports for a time adjustment 1785 * @hw: pointer to HW struct 1786 * @adj: adjustment in nanoseconds 1787 * 1788 * Prepare the PHY ports for an atomic time adjustment by programming the PHY 1789 * Tx and Rx port registers. The actual adjustment is completed by issuing an 1790 * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command. 1791 * 1792 * Return: 1793 * * %0 - success 1794 * * %other - failed to write to PHY 1795 */ 1796 static int ice_ptp_prep_phy_adj_eth56g(struct ice_hw *hw, s32 adj) 1797 { 1798 s64 cycles; 1799 u8 port; 1800 1801 /* The port clock supports adjustment of the sub-nanosecond portion of 1802 * the clock (lowest 32 bits). We shift the provided adjustment in 1803 * nanoseconds by 32 to calculate the appropriate adjustment to program 1804 * into the PHY ports. 1805 */ 1806 cycles = (s64)adj << 32; 1807 1808 for (port = 0; port < hw->ptp.num_lports; port++) { 1809 int err; 1810 1811 err = ice_ptp_prep_port_adj_eth56g(hw, port, cycles); 1812 if (err) 1813 return err; 1814 } 1815 1816 return 0; 1817 } 1818 1819 /** 1820 * ice_ptp_prep_phy_incval_eth56g - Prepare PHY ports for time adjustment 1821 * @hw: pointer to HW struct 1822 * @incval: new increment value to prepare 1823 * 1824 * Prepare each of the PHY ports for a new increment value by programming the 1825 * port's TIMETUS registers. The new increment value will be updated after 1826 * issuing an ICE_PTP_INIT_INCVAL command. 1827 * 1828 * Return: 1829 * * %0 - success 1830 * * %other - failed to write to PHY 1831 */ 1832 static int ice_ptp_prep_phy_incval_eth56g(struct ice_hw *hw, u64 incval) 1833 { 1834 u8 port; 1835 1836 for (port = 0; port < hw->ptp.num_lports; port++) { 1837 int err; 1838 1839 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_REG_TIMETUS_L, 1840 incval); 1841 if (err) { 1842 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n", 1843 port, err); 1844 return err; 1845 } 1846 } 1847 1848 return 0; 1849 } 1850 1851 /** 1852 * ice_ptp_read_port_capture_eth56g - Read a port's local time capture 1853 * @hw: pointer to HW struct 1854 * @port: Port number to read 1855 * @tx_ts: on return, the Tx port time capture 1856 * @rx_ts: on return, the Rx port time capture 1857 * 1858 * Read the port's Tx and Rx local time capture values. 1859 * 1860 * Return: 1861 * * %0 - success 1862 * * %other - failed to read from PHY 1863 */ 1864 static int ice_ptp_read_port_capture_eth56g(struct ice_hw *hw, u8 port, 1865 u64 *tx_ts, u64 *rx_ts) 1866 { 1867 int err; 1868 1869 /* Tx case */ 1870 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_CAPTURE_L, 1871 tx_ts); 1872 if (err) { 1873 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n", 1874 err); 1875 return err; 1876 } 1877 1878 ice_debug(hw, ICE_DBG_PTP, "tx_init = %#016llx\n", *tx_ts); 1879 1880 /* Rx case */ 1881 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_RX_CAPTURE_L, 1882 rx_ts); 1883 if (err) { 1884 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n", 1885 err); 1886 return err; 1887 } 1888 1889 ice_debug(hw, ICE_DBG_PTP, "rx_init = %#016llx\n", *rx_ts); 1890 1891 return 0; 1892 } 1893 1894 /** 1895 * ice_ptp_write_port_cmd_eth56g - Prepare a single PHY port for a timer command 1896 * @hw: pointer to HW struct 1897 * @port: Port to which cmd has to be sent 1898 * @cmd: Command to be sent to the port 1899 * 1900 * Prepare the requested port for an upcoming timer sync command. 1901 * 1902 * Return: 1903 * * %0 - success 1904 * * %other - failed to write to PHY 1905 */ 1906 static int ice_ptp_write_port_cmd_eth56g(struct ice_hw *hw, u8 port, 1907 enum ice_ptp_tmr_cmd cmd) 1908 { 1909 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 1910 int err; 1911 1912 /* Tx case */ 1913 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TMR_CMD, val); 1914 if (err) { 1915 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n", 1916 err); 1917 return err; 1918 } 1919 1920 /* Rx case */ 1921 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TMR_CMD, val); 1922 if (err) { 1923 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n", 1924 err); 1925 return err; 1926 } 1927 1928 return 0; 1929 } 1930 1931 /** 1932 * ice_phy_get_speed_eth56g - Get link speed based on PHY link type 1933 * @li: pointer to link information struct 1934 * 1935 * Return: simplified ETH56G PHY speed 1936 */ 1937 static enum ice_eth56g_link_spd 1938 ice_phy_get_speed_eth56g(struct ice_link_status *li) 1939 { 1940 u16 speed = ice_get_link_speed_based_on_phy_type(li->phy_type_low, 1941 li->phy_type_high); 1942 1943 switch (speed) { 1944 case ICE_AQ_LINK_SPEED_1000MB: 1945 return ICE_ETH56G_LNK_SPD_1G; 1946 case ICE_AQ_LINK_SPEED_2500MB: 1947 return ICE_ETH56G_LNK_SPD_2_5G; 1948 case ICE_AQ_LINK_SPEED_10GB: 1949 return ICE_ETH56G_LNK_SPD_10G; 1950 case ICE_AQ_LINK_SPEED_25GB: 1951 return ICE_ETH56G_LNK_SPD_25G; 1952 case ICE_AQ_LINK_SPEED_40GB: 1953 return ICE_ETH56G_LNK_SPD_40G; 1954 case ICE_AQ_LINK_SPEED_50GB: 1955 switch (li->phy_type_low) { 1956 case ICE_PHY_TYPE_LOW_50GBASE_SR: 1957 case ICE_PHY_TYPE_LOW_50GBASE_FR: 1958 case ICE_PHY_TYPE_LOW_50GBASE_LR: 1959 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 1960 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 1961 case ICE_PHY_TYPE_LOW_50G_AUI1: 1962 return ICE_ETH56G_LNK_SPD_50G; 1963 default: 1964 return ICE_ETH56G_LNK_SPD_50G2; 1965 } 1966 case ICE_AQ_LINK_SPEED_100GB: 1967 if (li->phy_type_high || 1968 li->phy_type_low == ICE_PHY_TYPE_LOW_100GBASE_SR2) 1969 return ICE_ETH56G_LNK_SPD_100G2; 1970 else 1971 return ICE_ETH56G_LNK_SPD_100G; 1972 default: 1973 return ICE_ETH56G_LNK_SPD_1G; 1974 } 1975 } 1976 1977 /** 1978 * ice_phy_cfg_parpcs_eth56g - Configure TUs per PAR/PCS clock cycle 1979 * @hw: pointer to the HW struct 1980 * @port: port to configure 1981 * 1982 * Configure the number of TUs for the PAR and PCS clocks used as part of the 1983 * timestamp calibration process. 1984 * 1985 * Return: 1986 * * %0 - success 1987 * * %other - PHY read/write failed 1988 */ 1989 static int ice_phy_cfg_parpcs_eth56g(struct ice_hw *hw, u8 port) 1990 { 1991 u32 val; 1992 int err; 1993 1994 err = ice_write_xpcs_reg_eth56g(hw, port, PHY_VENDOR_TXLANE_THRESH, 1995 ICE_ETH56G_NOMINAL_THRESH4); 1996 if (err) { 1997 ice_debug(hw, ICE_DBG_PTP, "Failed to read VENDOR_TXLANE_THRESH, status: %d", 1998 err); 1999 return err; 2000 } 2001 2002 switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) { 2003 case ICE_ETH56G_LNK_SPD_1G: 2004 case ICE_ETH56G_LNK_SPD_2_5G: 2005 err = ice_read_quad_ptp_reg_eth56g(hw, port, 2006 PHY_GPCS_CONFIG_REG0, &val); 2007 if (err) { 2008 ice_debug(hw, ICE_DBG_PTP, "Failed to read PHY_GPCS_CONFIG_REG0, status: %d", 2009 err); 2010 return err; 2011 } 2012 2013 val &= ~PHY_GPCS_CONFIG_REG0_TX_THR_M; 2014 val |= FIELD_PREP(PHY_GPCS_CONFIG_REG0_TX_THR_M, 2015 ICE_ETH56G_NOMINAL_TX_THRESH); 2016 2017 err = ice_write_quad_ptp_reg_eth56g(hw, port, 2018 PHY_GPCS_CONFIG_REG0, val); 2019 if (err) { 2020 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_GPCS_CONFIG_REG0, status: %d", 2021 err); 2022 return err; 2023 } 2024 break; 2025 default: 2026 break; 2027 } 2028 2029 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_PCS_REF_TUS_L, 2030 ICE_ETH56G_NOMINAL_PCS_REF_TUS); 2031 if (err) { 2032 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_PCS_REF_TUS, status: %d", 2033 err); 2034 return err; 2035 } 2036 2037 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_PCS_REF_INC_L, 2038 ICE_ETH56G_NOMINAL_PCS_REF_INC); 2039 if (err) { 2040 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_PCS_REF_INC, status: %d", 2041 err); 2042 return err; 2043 } 2044 2045 return 0; 2046 } 2047 2048 /** 2049 * ice_phy_cfg_ptp_1step_eth56g - Configure 1-step PTP settings 2050 * @hw: Pointer to the HW struct 2051 * @port: Port to configure 2052 * 2053 * Return: 2054 * * %0 - success 2055 * * %other - PHY read/write failed 2056 */ 2057 int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port) 2058 { 2059 u8 quad_lane = port % ICE_PORTS_PER_QUAD; 2060 u32 addr, val, peer_delay; 2061 bool enable, sfd_ena; 2062 int err; 2063 2064 enable = hw->ptp.phy.eth56g.onestep_ena; 2065 peer_delay = hw->ptp.phy.eth56g.peer_delay; 2066 sfd_ena = hw->ptp.phy.eth56g.sfd_ena; 2067 2068 addr = PHY_PTP_1STEP_CONFIG; 2069 err = ice_read_quad_ptp_reg_eth56g(hw, port, addr, &val); 2070 if (err) 2071 return err; 2072 2073 if (enable) 2074 val |= BIT(quad_lane); 2075 else 2076 val &= ~BIT(quad_lane); 2077 2078 val &= ~(PHY_PTP_1STEP_T1S_UP64_M | PHY_PTP_1STEP_T1S_DELTA_M); 2079 2080 err = ice_write_quad_ptp_reg_eth56g(hw, port, addr, val); 2081 if (err) 2082 return err; 2083 2084 addr = PHY_PTP_1STEP_PEER_DELAY(quad_lane); 2085 val = FIELD_PREP(PHY_PTP_1STEP_PD_DELAY_M, peer_delay); 2086 if (peer_delay) 2087 val |= PHY_PTP_1STEP_PD_ADD_PD_M; 2088 val |= PHY_PTP_1STEP_PD_DLY_V_M; 2089 err = ice_write_quad_ptp_reg_eth56g(hw, port, addr, val); 2090 if (err) 2091 return err; 2092 2093 val &= ~PHY_PTP_1STEP_PD_DLY_V_M; 2094 err = ice_write_quad_ptp_reg_eth56g(hw, port, addr, val); 2095 if (err) 2096 return err; 2097 2098 addr = PHY_MAC_XIF_MODE; 2099 err = ice_read_mac_reg_eth56g(hw, port, addr, &val); 2100 if (err) 2101 return err; 2102 2103 val &= ~(PHY_MAC_XIF_1STEP_ENA_M | PHY_MAC_XIF_TS_BIN_MODE_M | 2104 PHY_MAC_XIF_TS_SFD_ENA_M | PHY_MAC_XIF_GMII_TS_SEL_M); 2105 2106 switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) { 2107 case ICE_ETH56G_LNK_SPD_1G: 2108 case ICE_ETH56G_LNK_SPD_2_5G: 2109 val |= PHY_MAC_XIF_GMII_TS_SEL_M; 2110 break; 2111 default: 2112 break; 2113 } 2114 2115 val |= FIELD_PREP(PHY_MAC_XIF_1STEP_ENA_M, enable) | 2116 FIELD_PREP(PHY_MAC_XIF_TS_BIN_MODE_M, enable) | 2117 FIELD_PREP(PHY_MAC_XIF_TS_SFD_ENA_M, sfd_ena); 2118 2119 return ice_write_mac_reg_eth56g(hw, port, addr, val); 2120 } 2121 2122 /** 2123 * mul_u32_u32_fx_q9 - Multiply two u32 fixed point Q9 values 2124 * @a: multiplier value 2125 * @b: multiplicand value 2126 * 2127 * Return: result of multiplication 2128 */ 2129 static u32 mul_u32_u32_fx_q9(u32 a, u32 b) 2130 { 2131 return (u32)(((u64)a * b) >> ICE_ETH56G_MAC_CFG_FRAC_W); 2132 } 2133 2134 /** 2135 * add_u32_u32_fx - Add two u32 fixed point values and discard overflow 2136 * @a: first value 2137 * @b: second value 2138 * 2139 * Return: result of addition 2140 */ 2141 static u32 add_u32_u32_fx(u32 a, u32 b) 2142 { 2143 return lower_32_bits(((u64)a + b)); 2144 } 2145 2146 /** 2147 * ice_ptp_calc_bitslip_eth56g - Calculate bitslip value 2148 * @hw: pointer to the HW struct 2149 * @port: port to configure 2150 * @bs: bitslip multiplier 2151 * @fc: FC-FEC enabled 2152 * @rs: RS-FEC enabled 2153 * @spd: link speed 2154 * 2155 * Return: calculated bitslip value 2156 */ 2157 static u32 ice_ptp_calc_bitslip_eth56g(struct ice_hw *hw, u8 port, u32 bs, 2158 bool fc, bool rs, 2159 enum ice_eth56g_link_spd spd) 2160 { 2161 u32 bitslip; 2162 int err; 2163 2164 if (!bs || rs) 2165 return 0; 2166 2167 if (spd == ICE_ETH56G_LNK_SPD_1G || spd == ICE_ETH56G_LNK_SPD_2_5G) { 2168 err = ice_read_gpcs_reg_eth56g(hw, port, PHY_GPCS_BITSLIP, 2169 &bitslip); 2170 } else { 2171 u8 quad_lane = port % ICE_PORTS_PER_QUAD; 2172 u32 addr; 2173 2174 addr = PHY_REG_SD_BIT_SLIP(quad_lane); 2175 err = ice_read_quad_ptp_reg_eth56g(hw, port, addr, &bitslip); 2176 } 2177 if (err) 2178 return 0; 2179 2180 if (spd == ICE_ETH56G_LNK_SPD_1G && !bitslip) { 2181 /* Bitslip register value of 0 corresponds to 10 so substitute 2182 * it for calculations 2183 */ 2184 bitslip = 10; 2185 } else if (spd == ICE_ETH56G_LNK_SPD_10G || 2186 spd == ICE_ETH56G_LNK_SPD_25G) { 2187 if (fc) 2188 bitslip = bitslip * 2 + 32; 2189 else 2190 bitslip = (u32)((s32)bitslip * -1 + 20); 2191 } 2192 2193 bitslip <<= ICE_ETH56G_MAC_CFG_FRAC_W; 2194 return mul_u32_u32_fx_q9(bitslip, bs); 2195 } 2196 2197 /** 2198 * ice_ptp_calc_deskew_eth56g - Calculate deskew value 2199 * @hw: pointer to the HW struct 2200 * @port: port to configure 2201 * @ds: deskew multiplier 2202 * @rs: RS-FEC enabled 2203 * @spd: link speed 2204 * 2205 * Return: calculated deskew value 2206 */ 2207 static u32 ice_ptp_calc_deskew_eth56g(struct ice_hw *hw, u8 port, u32 ds, 2208 bool rs, enum ice_eth56g_link_spd spd) 2209 { 2210 u32 deskew_i, deskew_f; 2211 int err; 2212 2213 if (!ds) 2214 return 0; 2215 2216 read_poll_timeout(ice_read_ptp_reg_eth56g, err, 2217 FIELD_GET(PHY_REG_DESKEW_0_VALID, deskew_i), 500, 2218 50 * USEC_PER_MSEC, false, hw, port, PHY_REG_DESKEW_0, 2219 &deskew_i); 2220 if (err) 2221 return err; 2222 2223 deskew_f = FIELD_GET(PHY_REG_DESKEW_0_RLEVEL_FRAC, deskew_i); 2224 deskew_i = FIELD_GET(PHY_REG_DESKEW_0_RLEVEL, deskew_i); 2225 2226 if (rs && spd == ICE_ETH56G_LNK_SPD_50G2) 2227 ds = 0x633; /* 3.1 */ 2228 else if (rs && spd == ICE_ETH56G_LNK_SPD_100G) 2229 ds = 0x31b; /* 1.552 */ 2230 2231 deskew_i = FIELD_PREP(ICE_ETH56G_MAC_CFG_RX_OFFSET_INT, deskew_i); 2232 /* Shift 3 fractional bits to the end of the integer part */ 2233 deskew_f <<= ICE_ETH56G_MAC_CFG_FRAC_W - PHY_REG_DESKEW_0_RLEVEL_FRAC_W; 2234 return mul_u32_u32_fx_q9(deskew_i | deskew_f, ds); 2235 } 2236 2237 /** 2238 * ice_phy_set_offsets_eth56g - Set Tx/Rx offset values 2239 * @hw: pointer to the HW struct 2240 * @port: port to configure 2241 * @spd: link speed 2242 * @cfg: structure to store output values 2243 * @fc: FC-FEC enabled 2244 * @rs: RS-FEC enabled 2245 * 2246 * Return: 2247 * * %0 - success 2248 * * %other - failed to write to PHY 2249 */ 2250 static int ice_phy_set_offsets_eth56g(struct ice_hw *hw, u8 port, 2251 enum ice_eth56g_link_spd spd, 2252 const struct ice_eth56g_mac_reg_cfg *cfg, 2253 bool fc, bool rs) 2254 { 2255 u32 rx_offset, tx_offset, bs_ds; 2256 bool onestep, sfd; 2257 2258 onestep = hw->ptp.phy.eth56g.onestep_ena; 2259 sfd = hw->ptp.phy.eth56g.sfd_ena; 2260 bs_ds = cfg->rx_offset.bs_ds; 2261 2262 if (fc) 2263 rx_offset = cfg->rx_offset.fc; 2264 else if (rs) 2265 rx_offset = cfg->rx_offset.rs; 2266 else 2267 rx_offset = cfg->rx_offset.no_fec; 2268 2269 rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.serdes); 2270 if (sfd) 2271 rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.sfd); 2272 2273 if (spd < ICE_ETH56G_LNK_SPD_40G) 2274 bs_ds = ice_ptp_calc_bitslip_eth56g(hw, port, bs_ds, fc, rs, 2275 spd); 2276 else 2277 bs_ds = ice_ptp_calc_deskew_eth56g(hw, port, bs_ds, rs, spd); 2278 rx_offset = add_u32_u32_fx(rx_offset, bs_ds); 2279 rx_offset &= ICE_ETH56G_MAC_CFG_RX_OFFSET_INT | 2280 ICE_ETH56G_MAC_CFG_RX_OFFSET_FRAC; 2281 2282 if (fc) 2283 tx_offset = cfg->tx_offset.fc; 2284 else if (rs) 2285 tx_offset = cfg->tx_offset.rs; 2286 else 2287 tx_offset = cfg->tx_offset.no_fec; 2288 tx_offset += cfg->tx_offset.serdes + cfg->tx_offset.sfd * sfd + 2289 cfg->tx_offset.onestep * onestep; 2290 2291 ice_write_mac_reg_eth56g(hw, port, PHY_MAC_RX_OFFSET, rx_offset); 2292 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TX_OFFSET, tx_offset); 2293 } 2294 2295 /** 2296 * ice_phy_cfg_mac_eth56g - Configure MAC for PTP 2297 * @hw: Pointer to the HW struct 2298 * @port: Port to configure 2299 * 2300 * Return: 2301 * * %0 - success 2302 * * %other - failed to write to PHY 2303 */ 2304 static int ice_phy_cfg_mac_eth56g(struct ice_hw *hw, u8 port) 2305 { 2306 const struct ice_eth56g_mac_reg_cfg *cfg; 2307 enum ice_eth56g_link_spd spd; 2308 struct ice_link_status *li; 2309 bool fc = false; 2310 bool rs = false; 2311 bool onestep; 2312 u32 val; 2313 int err; 2314 2315 onestep = hw->ptp.phy.eth56g.onestep_ena; 2316 li = &hw->port_info->phy.link_info; 2317 spd = ice_phy_get_speed_eth56g(li); 2318 if (!!(li->an_info & ICE_AQ_FEC_EN)) { 2319 if (spd == ICE_ETH56G_LNK_SPD_10G) { 2320 fc = true; 2321 } else { 2322 fc = !!(li->fec_info & ICE_AQ_LINK_25G_KR_FEC_EN); 2323 rs = !!(li->fec_info & ~ICE_AQ_LINK_25G_KR_FEC_EN); 2324 } 2325 } 2326 cfg = ð56g_mac_cfg[spd]; 2327 2328 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_RX_MODULO, 0); 2329 if (err) 2330 return err; 2331 2332 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TX_MODULO, 0); 2333 if (err) 2334 return err; 2335 2336 val = FIELD_PREP(PHY_MAC_TSU_CFG_TX_MODE_M, 2337 cfg->tx_mode.def + rs * cfg->tx_mode.rs) | 2338 FIELD_PREP(PHY_MAC_TSU_CFG_TX_MII_MK_DLY_M, cfg->tx_mk_dly) | 2339 FIELD_PREP(PHY_MAC_TSU_CFG_TX_MII_CW_DLY_M, 2340 cfg->tx_cw_dly.def + 2341 onestep * cfg->tx_cw_dly.onestep) | 2342 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MODE_M, 2343 cfg->rx_mode.def + rs * cfg->rx_mode.rs) | 2344 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MII_MK_DLY_M, 2345 cfg->rx_mk_dly.def + rs * cfg->rx_mk_dly.rs) | 2346 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MII_CW_DLY_M, 2347 cfg->rx_cw_dly.def + rs * cfg->rx_cw_dly.rs) | 2348 FIELD_PREP(PHY_MAC_TSU_CFG_BLKS_PER_CLK_M, cfg->blks_per_clk); 2349 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TSU_CONFIG, val); 2350 if (err) 2351 return err; 2352 2353 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_BLOCKTIME, 2354 cfg->blktime); 2355 if (err) 2356 return err; 2357 2358 err = ice_phy_set_offsets_eth56g(hw, port, spd, cfg, fc, rs); 2359 if (err) 2360 return err; 2361 2362 if (spd == ICE_ETH56G_LNK_SPD_25G && !rs) 2363 val = 0; 2364 else 2365 val = cfg->mktime; 2366 2367 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_MARKERTIME, val); 2368 } 2369 2370 /** 2371 * ice_phy_cfg_intr_eth56g - Configure TX timestamp interrupt 2372 * @hw: pointer to the HW struct 2373 * @port: the timestamp port 2374 * @ena: enable or disable interrupt 2375 * @threshold: interrupt threshold 2376 * 2377 * Configure TX timestamp interrupt for the specified port 2378 * 2379 * Return: 2380 * * %0 - success 2381 * * %other - PHY read/write failed 2382 */ 2383 int ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold) 2384 { 2385 int err; 2386 u32 val; 2387 2388 err = ice_read_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, &val); 2389 if (err) 2390 return err; 2391 2392 if (ena) { 2393 val |= PHY_TS_INT_CONFIG_ENA_M; 2394 val &= ~PHY_TS_INT_CONFIG_THRESHOLD_M; 2395 val |= FIELD_PREP(PHY_TS_INT_CONFIG_THRESHOLD_M, threshold); 2396 } else { 2397 val &= ~PHY_TS_INT_CONFIG_ENA_M; 2398 } 2399 2400 return ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, val); 2401 } 2402 2403 /** 2404 * ice_read_phy_and_phc_time_eth56g - Simultaneously capture PHC and PHY time 2405 * @hw: pointer to the HW struct 2406 * @port: the PHY port to read 2407 * @phy_time: on return, the 64bit PHY timer value 2408 * @phc_time: on return, the lower 64bits of PHC time 2409 * 2410 * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY 2411 * and PHC timer values. 2412 * 2413 * Return: 2414 * * %0 - success 2415 * * %other - PHY read/write failed 2416 */ 2417 static int ice_read_phy_and_phc_time_eth56g(struct ice_hw *hw, u8 port, 2418 u64 *phy_time, u64 *phc_time) 2419 { 2420 u64 tx_time, rx_time; 2421 u32 zo, lo; 2422 u8 tmr_idx; 2423 int err; 2424 2425 tmr_idx = ice_get_ptp_src_clock_index(hw); 2426 2427 /* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */ 2428 ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME); 2429 2430 /* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */ 2431 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME); 2432 if (err) 2433 return err; 2434 2435 /* Issue the sync to start the ICE_PTP_READ_TIME capture */ 2436 ice_ptp_exec_tmr_cmd(hw); 2437 2438 /* Read the captured PHC time from the shadow time registers */ 2439 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx)); 2440 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx)); 2441 *phc_time = (u64)lo << 32 | zo; 2442 2443 /* Read the captured PHY time from the PHY shadow registers */ 2444 err = ice_ptp_read_port_capture_eth56g(hw, port, &tx_time, &rx_time); 2445 if (err) 2446 return err; 2447 2448 /* If the PHY Tx and Rx timers don't match, log a warning message. 2449 * Note that this should not happen in normal circumstances since the 2450 * driver always programs them together. 2451 */ 2452 if (tx_time != rx_time) 2453 dev_warn(ice_hw_to_dev(hw), "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n", 2454 port, tx_time, rx_time); 2455 2456 *phy_time = tx_time; 2457 2458 return 0; 2459 } 2460 2461 /** 2462 * ice_sync_phy_timer_eth56g - Synchronize the PHY timer with PHC timer 2463 * @hw: pointer to the HW struct 2464 * @port: the PHY port to synchronize 2465 * 2466 * Perform an adjustment to ensure that the PHY and PHC timers are in sync. 2467 * This is done by issuing a ICE_PTP_READ_TIME command which triggers a 2468 * simultaneous read of the PHY timer and PHC timer. Then we use the 2469 * difference to calculate an appropriate 2s complement addition to add 2470 * to the PHY timer in order to ensure it reads the same value as the 2471 * primary PHC timer. 2472 * 2473 * Return: 2474 * * %0 - success 2475 * * %-EBUSY- failed to acquire PTP semaphore 2476 * * %other - PHY read/write failed 2477 */ 2478 static int ice_sync_phy_timer_eth56g(struct ice_hw *hw, u8 port) 2479 { 2480 u64 phc_time, phy_time, difference; 2481 int err; 2482 2483 if (!ice_ptp_lock(hw)) { 2484 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n"); 2485 return -EBUSY; 2486 } 2487 2488 err = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time, &phc_time); 2489 if (err) 2490 goto err_unlock; 2491 2492 /* Calculate the amount required to add to the port time in order for 2493 * it to match the PHC time. 2494 * 2495 * Note that the port adjustment is done using 2s complement 2496 * arithmetic. This is convenient since it means that we can simply 2497 * calculate the difference between the PHC time and the port time, 2498 * and it will be interpreted correctly. 2499 */ 2500 2501 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 2502 difference = phc_time - phy_time; 2503 2504 err = ice_ptp_prep_port_adj_eth56g(hw, port, (s64)difference); 2505 if (err) 2506 goto err_unlock; 2507 2508 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME); 2509 if (err) 2510 goto err_unlock; 2511 2512 /* Issue the sync to activate the time adjustment */ 2513 ice_ptp_exec_tmr_cmd(hw); 2514 2515 /* Re-capture the timer values to flush the command registers and 2516 * verify that the time was properly adjusted. 2517 */ 2518 err = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time, &phc_time); 2519 if (err) 2520 goto err_unlock; 2521 2522 dev_info(ice_hw_to_dev(hw), 2523 "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n", 2524 port, phy_time, phc_time); 2525 2526 err_unlock: 2527 ice_ptp_unlock(hw); 2528 return err; 2529 } 2530 2531 /** 2532 * ice_stop_phy_timer_eth56g - Stop the PHY clock timer 2533 * @hw: pointer to the HW struct 2534 * @port: the PHY port to stop 2535 * @soft_reset: if true, hold the SOFT_RESET bit of PHY_REG_PS 2536 * 2537 * Stop the clock of a PHY port. This must be done as part of the flow to 2538 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 2539 * initialized or when link speed changes. 2540 * 2541 * Return: 2542 * * %0 - success 2543 * * %other - failed to write to PHY 2544 */ 2545 int ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset) 2546 { 2547 int err; 2548 2549 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 0); 2550 if (err) 2551 return err; 2552 2553 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 0); 2554 if (err) 2555 return err; 2556 2557 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port); 2558 2559 return 0; 2560 } 2561 2562 /** 2563 * ice_start_phy_timer_eth56g - Start the PHY clock timer 2564 * @hw: pointer to the HW struct 2565 * @port: the PHY port to start 2566 * 2567 * Start the clock of a PHY port. This must be done as part of the flow to 2568 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 2569 * initialized or when link speed changes. 2570 * 2571 * Return: 2572 * * %0 - success 2573 * * %other - PHY read/write failed 2574 */ 2575 int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port) 2576 { 2577 u32 lo, hi; 2578 u64 incval; 2579 u8 tmr_idx; 2580 int err; 2581 2582 tmr_idx = ice_get_ptp_src_clock_index(hw); 2583 2584 err = ice_stop_phy_timer_eth56g(hw, port, false); 2585 if (err) 2586 return err; 2587 2588 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 2589 2590 err = ice_phy_cfg_parpcs_eth56g(hw, port); 2591 if (err) 2592 return err; 2593 2594 err = ice_phy_cfg_ptp_1step_eth56g(hw, port); 2595 if (err) 2596 return err; 2597 2598 err = ice_phy_cfg_mac_eth56g(hw, port); 2599 if (err) 2600 return err; 2601 2602 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 2603 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 2604 incval = (u64)hi << 32 | lo; 2605 2606 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_REG_TIMETUS_L, incval); 2607 if (err) 2608 return err; 2609 2610 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL); 2611 if (err) 2612 return err; 2613 2614 ice_ptp_exec_tmr_cmd(hw); 2615 2616 err = ice_sync_phy_timer_eth56g(hw, port); 2617 if (err) 2618 return err; 2619 2620 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 1); 2621 if (err) 2622 return err; 2623 2624 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 1); 2625 if (err) 2626 return err; 2627 2628 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port); 2629 2630 return 0; 2631 } 2632 2633 /** 2634 * ice_sb_access_ena_eth56g - Enable SB devices (PHY and others) access 2635 * @hw: pointer to HW struct 2636 * @enable: Enable or disable access 2637 * 2638 * Enable sideband devices (PHY and others) access. 2639 */ 2640 static void ice_sb_access_ena_eth56g(struct ice_hw *hw, bool enable) 2641 { 2642 u32 val = rd32(hw, PF_SB_REM_DEV_CTL); 2643 2644 if (enable) 2645 val |= BIT(eth56g_phy_0) | BIT(cgu) | BIT(eth56g_phy_1); 2646 else 2647 val &= ~(BIT(eth56g_phy_0) | BIT(cgu) | BIT(eth56g_phy_1)); 2648 2649 wr32(hw, PF_SB_REM_DEV_CTL, val); 2650 } 2651 2652 /** 2653 * ice_ptp_init_phc_eth56g - Perform E82X specific PHC initialization 2654 * @hw: pointer to HW struct 2655 * 2656 * Perform PHC initialization steps specific to E82X devices. 2657 * 2658 * Return: 2659 * * %0 - success 2660 * * %other - failed to initialize CGU 2661 */ 2662 static int ice_ptp_init_phc_eth56g(struct ice_hw *hw) 2663 { 2664 ice_sb_access_ena_eth56g(hw, true); 2665 /* Initialize the Clock Generation Unit */ 2666 return ice_init_cgu_e82x(hw); 2667 } 2668 2669 /** 2670 * ice_ptp_read_tx_hwtstamp_status_eth56g - Get TX timestamp status 2671 * @hw: pointer to the HW struct 2672 * @ts_status: the timestamp mask pointer 2673 * 2674 * Read the PHY Tx timestamp status mask indicating which ports have Tx 2675 * timestamps available. 2676 * 2677 * Return: 2678 * * %0 - success 2679 * * %other - failed to read from PHY 2680 */ 2681 int ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status) 2682 { 2683 const struct ice_eth56g_params *params = &hw->ptp.phy.eth56g; 2684 u8 phy, mask; 2685 u32 status; 2686 2687 mask = (1 << hw->ptp.ports_per_phy) - 1; 2688 *ts_status = 0; 2689 2690 for (phy = 0; phy < params->num_phys; phy++) { 2691 int err; 2692 2693 err = ice_read_phy_eth56g(hw, phy, PHY_PTP_INT_STATUS, &status); 2694 if (err) 2695 return err; 2696 2697 *ts_status |= (status & mask) << (phy * hw->ptp.ports_per_phy); 2698 } 2699 2700 ice_debug(hw, ICE_DBG_PTP, "PHY interrupt err: %x\n", *ts_status); 2701 2702 return 0; 2703 } 2704 2705 /** 2706 * ice_get_phy_tx_tstamp_ready_eth56g - Read the Tx memory status register 2707 * @hw: pointer to the HW struct 2708 * @port: the PHY port to read from 2709 * @tstamp_ready: contents of the Tx memory status register 2710 * 2711 * Read the PHY_REG_TX_MEMORY_STATUS register indicating which timestamps in 2712 * the PHY are ready. A set bit means the corresponding timestamp is valid and 2713 * ready to be captured from the PHY timestamp block. 2714 * 2715 * Return: 2716 * * %0 - success 2717 * * %other - failed to read from PHY 2718 */ 2719 static int ice_get_phy_tx_tstamp_ready_eth56g(struct ice_hw *hw, u8 port, 2720 u64 *tstamp_ready) 2721 { 2722 int err; 2723 2724 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L, 2725 tstamp_ready); 2726 if (err) { 2727 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS for port %u, err %d\n", 2728 port, err); 2729 return err; 2730 } 2731 2732 return 0; 2733 } 2734 2735 /** 2736 * ice_ptp_init_phy_e825 - initialize PHY parameters 2737 * @hw: pointer to the HW struct 2738 */ 2739 static void ice_ptp_init_phy_e825(struct ice_hw *hw) 2740 { 2741 struct ice_ptp_hw *ptp = &hw->ptp; 2742 struct ice_eth56g_params *params; 2743 2744 params = &ptp->phy.eth56g; 2745 params->onestep_ena = false; 2746 params->peer_delay = 0; 2747 params->sfd_ena = false; 2748 params->num_phys = 2; 2749 ptp->ports_per_phy = 4; 2750 ptp->num_lports = params->num_phys * ptp->ports_per_phy; 2751 2752 ice_sb_access_ena_eth56g(hw, true); 2753 } 2754 2755 /* E822 family functions 2756 * 2757 * The following functions operate on the E822 family of devices. 2758 */ 2759 2760 /** 2761 * ice_fill_phy_msg_e82x - Fill message data for a PHY register access 2762 * @hw: pointer to the HW struct 2763 * @msg: the PHY message buffer to fill in 2764 * @port: the port to access 2765 * @offset: the register offset 2766 */ 2767 static void ice_fill_phy_msg_e82x(struct ice_hw *hw, 2768 struct ice_sbq_msg_input *msg, u8 port, 2769 u16 offset) 2770 { 2771 int phy_port, quadtype; 2772 2773 phy_port = port % hw->ptp.ports_per_phy; 2774 quadtype = ICE_GET_QUAD_NUM(port) % 2775 ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy); 2776 2777 if (quadtype == 0) { 2778 msg->msg_addr_low = P_Q0_L(P_0_BASE + offset, phy_port); 2779 msg->msg_addr_high = P_Q0_H(P_0_BASE + offset, phy_port); 2780 } else { 2781 msg->msg_addr_low = P_Q1_L(P_4_BASE + offset, phy_port); 2782 msg->msg_addr_high = P_Q1_H(P_4_BASE + offset, phy_port); 2783 } 2784 2785 msg->dest_dev = rmn_0; 2786 } 2787 2788 /** 2789 * ice_is_64b_phy_reg_e82x - Check if this is a 64bit PHY register 2790 * @low_addr: the low address to check 2791 * @high_addr: on return, contains the high address of the 64bit register 2792 * 2793 * Checks if the provided low address is one of the known 64bit PHY values 2794 * represented as two 32bit registers. If it is, return the appropriate high 2795 * register offset to use. 2796 */ 2797 static bool ice_is_64b_phy_reg_e82x(u16 low_addr, u16 *high_addr) 2798 { 2799 switch (low_addr) { 2800 case P_REG_PAR_PCS_TX_OFFSET_L: 2801 *high_addr = P_REG_PAR_PCS_TX_OFFSET_U; 2802 return true; 2803 case P_REG_PAR_PCS_RX_OFFSET_L: 2804 *high_addr = P_REG_PAR_PCS_RX_OFFSET_U; 2805 return true; 2806 case P_REG_PAR_TX_TIME_L: 2807 *high_addr = P_REG_PAR_TX_TIME_U; 2808 return true; 2809 case P_REG_PAR_RX_TIME_L: 2810 *high_addr = P_REG_PAR_RX_TIME_U; 2811 return true; 2812 case P_REG_TOTAL_TX_OFFSET_L: 2813 *high_addr = P_REG_TOTAL_TX_OFFSET_U; 2814 return true; 2815 case P_REG_TOTAL_RX_OFFSET_L: 2816 *high_addr = P_REG_TOTAL_RX_OFFSET_U; 2817 return true; 2818 case P_REG_UIX66_10G_40G_L: 2819 *high_addr = P_REG_UIX66_10G_40G_U; 2820 return true; 2821 case P_REG_UIX66_25G_100G_L: 2822 *high_addr = P_REG_UIX66_25G_100G_U; 2823 return true; 2824 case P_REG_TX_CAPTURE_L: 2825 *high_addr = P_REG_TX_CAPTURE_U; 2826 return true; 2827 case P_REG_RX_CAPTURE_L: 2828 *high_addr = P_REG_RX_CAPTURE_U; 2829 return true; 2830 case P_REG_TX_TIMER_INC_PRE_L: 2831 *high_addr = P_REG_TX_TIMER_INC_PRE_U; 2832 return true; 2833 case P_REG_RX_TIMER_INC_PRE_L: 2834 *high_addr = P_REG_RX_TIMER_INC_PRE_U; 2835 return true; 2836 default: 2837 return false; 2838 } 2839 } 2840 2841 /** 2842 * ice_is_40b_phy_reg_e82x - Check if this is a 40bit PHY register 2843 * @low_addr: the low address to check 2844 * @high_addr: on return, contains the high address of the 40bit value 2845 * 2846 * Checks if the provided low address is one of the known 40bit PHY values 2847 * split into two registers with the lower 8 bits in the low register and the 2848 * upper 32 bits in the high register. If it is, return the appropriate high 2849 * register offset to use. 2850 */ 2851 static bool ice_is_40b_phy_reg_e82x(u16 low_addr, u16 *high_addr) 2852 { 2853 switch (low_addr) { 2854 case P_REG_TIMETUS_L: 2855 *high_addr = P_REG_TIMETUS_U; 2856 return true; 2857 case P_REG_PAR_RX_TUS_L: 2858 *high_addr = P_REG_PAR_RX_TUS_U; 2859 return true; 2860 case P_REG_PAR_TX_TUS_L: 2861 *high_addr = P_REG_PAR_TX_TUS_U; 2862 return true; 2863 case P_REG_PCS_RX_TUS_L: 2864 *high_addr = P_REG_PCS_RX_TUS_U; 2865 return true; 2866 case P_REG_PCS_TX_TUS_L: 2867 *high_addr = P_REG_PCS_TX_TUS_U; 2868 return true; 2869 case P_REG_DESK_PAR_RX_TUS_L: 2870 *high_addr = P_REG_DESK_PAR_RX_TUS_U; 2871 return true; 2872 case P_REG_DESK_PAR_TX_TUS_L: 2873 *high_addr = P_REG_DESK_PAR_TX_TUS_U; 2874 return true; 2875 case P_REG_DESK_PCS_RX_TUS_L: 2876 *high_addr = P_REG_DESK_PCS_RX_TUS_U; 2877 return true; 2878 case P_REG_DESK_PCS_TX_TUS_L: 2879 *high_addr = P_REG_DESK_PCS_TX_TUS_U; 2880 return true; 2881 default: 2882 return false; 2883 } 2884 } 2885 2886 /** 2887 * ice_read_phy_reg_e82x - Read a PHY register 2888 * @hw: pointer to the HW struct 2889 * @port: PHY port to read from 2890 * @offset: PHY register offset to read 2891 * @val: on return, the contents read from the PHY 2892 * 2893 * Read a PHY register for the given port over the device sideband queue. 2894 */ 2895 static int 2896 ice_read_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 *val) 2897 { 2898 struct ice_sbq_msg_input msg = {0}; 2899 int err; 2900 2901 ice_fill_phy_msg_e82x(hw, &msg, port, offset); 2902 msg.opcode = ice_sbq_msg_rd; 2903 2904 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 2905 if (err) { 2906 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2907 err); 2908 return err; 2909 } 2910 2911 *val = msg.data; 2912 2913 return 0; 2914 } 2915 2916 /** 2917 * ice_read_64b_phy_reg_e82x - Read a 64bit value from PHY registers 2918 * @hw: pointer to the HW struct 2919 * @port: PHY port to read from 2920 * @low_addr: offset of the lower register to read from 2921 * @val: on return, the contents of the 64bit value from the PHY registers 2922 * 2923 * Reads the two registers associated with a 64bit value and returns it in the 2924 * val pointer. The offset always specifies the lower register offset to use. 2925 * The high offset is looked up. This function only operates on registers 2926 * known to be two parts of a 64bit value. 2927 */ 2928 static int 2929 ice_read_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val) 2930 { 2931 u32 low, high; 2932 u16 high_addr; 2933 int err; 2934 2935 /* Only operate on registers known to be split into two 32bit 2936 * registers. 2937 */ 2938 if (!ice_is_64b_phy_reg_e82x(low_addr, &high_addr)) { 2939 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n", 2940 low_addr); 2941 return -EINVAL; 2942 } 2943 2944 err = ice_read_phy_reg_e82x(hw, port, low_addr, &low); 2945 if (err) { 2946 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, err %d", 2947 low_addr, err); 2948 return err; 2949 } 2950 2951 err = ice_read_phy_reg_e82x(hw, port, high_addr, &high); 2952 if (err) { 2953 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, err %d", 2954 high_addr, err); 2955 return err; 2956 } 2957 2958 *val = (u64)high << 32 | low; 2959 2960 return 0; 2961 } 2962 2963 /** 2964 * ice_write_phy_reg_e82x - Write a PHY register 2965 * @hw: pointer to the HW struct 2966 * @port: PHY port to write to 2967 * @offset: PHY register offset to write 2968 * @val: The value to write to the register 2969 * 2970 * Write a PHY register for the given port over the device sideband queue. 2971 */ 2972 static int 2973 ice_write_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 val) 2974 { 2975 struct ice_sbq_msg_input msg = {0}; 2976 int err; 2977 2978 ice_fill_phy_msg_e82x(hw, &msg, port, offset); 2979 msg.opcode = ice_sbq_msg_wr; 2980 msg.data = val; 2981 2982 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 2983 if (err) { 2984 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2985 err); 2986 return err; 2987 } 2988 2989 return 0; 2990 } 2991 2992 /** 2993 * ice_write_40b_phy_reg_e82x - Write a 40b value to the PHY 2994 * @hw: pointer to the HW struct 2995 * @port: port to write to 2996 * @low_addr: offset of the low register 2997 * @val: 40b value to write 2998 * 2999 * Write the provided 40b value to the two associated registers by splitting 3000 * it up into two chunks, the lower 8 bits and the upper 32 bits. 3001 */ 3002 static int 3003 ice_write_40b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) 3004 { 3005 u32 low, high; 3006 u16 high_addr; 3007 int err; 3008 3009 /* Only operate on registers known to be split into a lower 8 bit 3010 * register and an upper 32 bit register. 3011 */ 3012 if (!ice_is_40b_phy_reg_e82x(low_addr, &high_addr)) { 3013 ice_debug(hw, ICE_DBG_PTP, "Invalid 40b register addr 0x%08x\n", 3014 low_addr); 3015 return -EINVAL; 3016 } 3017 low = FIELD_GET(P_REG_40B_LOW_M, val); 3018 high = (u32)(val >> P_REG_40B_HIGH_S); 3019 3020 err = ice_write_phy_reg_e82x(hw, port, low_addr, low); 3021 if (err) { 3022 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 3023 low_addr, err); 3024 return err; 3025 } 3026 3027 err = ice_write_phy_reg_e82x(hw, port, high_addr, high); 3028 if (err) { 3029 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 3030 high_addr, err); 3031 return err; 3032 } 3033 3034 return 0; 3035 } 3036 3037 /** 3038 * ice_write_64b_phy_reg_e82x - Write a 64bit value to PHY registers 3039 * @hw: pointer to the HW struct 3040 * @port: PHY port to read from 3041 * @low_addr: offset of the lower register to read from 3042 * @val: the contents of the 64bit value to write to PHY 3043 * 3044 * Write the 64bit value to the two associated 32bit PHY registers. The offset 3045 * is always specified as the lower register, and the high address is looked 3046 * up. This function only operates on registers known to be two parts of 3047 * a 64bit value. 3048 */ 3049 static int 3050 ice_write_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) 3051 { 3052 u32 low, high; 3053 u16 high_addr; 3054 int err; 3055 3056 /* Only operate on registers known to be split into two 32bit 3057 * registers. 3058 */ 3059 if (!ice_is_64b_phy_reg_e82x(low_addr, &high_addr)) { 3060 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n", 3061 low_addr); 3062 return -EINVAL; 3063 } 3064 3065 low = lower_32_bits(val); 3066 high = upper_32_bits(val); 3067 3068 err = ice_write_phy_reg_e82x(hw, port, low_addr, low); 3069 if (err) { 3070 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 3071 low_addr, err); 3072 return err; 3073 } 3074 3075 err = ice_write_phy_reg_e82x(hw, port, high_addr, high); 3076 if (err) { 3077 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 3078 high_addr, err); 3079 return err; 3080 } 3081 3082 return 0; 3083 } 3084 3085 /** 3086 * ice_fill_quad_msg_e82x - Fill message data for quad register access 3087 * @hw: pointer to the HW struct 3088 * @msg: the PHY message buffer to fill in 3089 * @quad: the quad to access 3090 * @offset: the register offset 3091 * 3092 * Fill a message buffer for accessing a register in a quad shared between 3093 * multiple PHYs. 3094 * 3095 * Return: 3096 * * %0 - OK 3097 * * %-EINVAL - invalid quad number 3098 */ 3099 static int ice_fill_quad_msg_e82x(struct ice_hw *hw, 3100 struct ice_sbq_msg_input *msg, u8 quad, 3101 u16 offset) 3102 { 3103 u32 addr; 3104 3105 if (quad >= ICE_GET_QUAD_NUM(hw->ptp.num_lports)) 3106 return -EINVAL; 3107 3108 msg->dest_dev = rmn_0; 3109 3110 if (!(quad % ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy))) 3111 addr = Q_0_BASE + offset; 3112 else 3113 addr = Q_1_BASE + offset; 3114 3115 msg->msg_addr_low = lower_16_bits(addr); 3116 msg->msg_addr_high = upper_16_bits(addr); 3117 3118 return 0; 3119 } 3120 3121 /** 3122 * ice_read_quad_reg_e82x - Read a PHY quad register 3123 * @hw: pointer to the HW struct 3124 * @quad: quad to read from 3125 * @offset: quad register offset to read 3126 * @val: on return, the contents read from the quad 3127 * 3128 * Read a quad register over the device sideband queue. Quad registers are 3129 * shared between multiple PHYs. 3130 */ 3131 int 3132 ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val) 3133 { 3134 struct ice_sbq_msg_input msg = {0}; 3135 int err; 3136 3137 err = ice_fill_quad_msg_e82x(hw, &msg, quad, offset); 3138 if (err) 3139 return err; 3140 3141 msg.opcode = ice_sbq_msg_rd; 3142 3143 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 3144 if (err) { 3145 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 3146 err); 3147 return err; 3148 } 3149 3150 *val = msg.data; 3151 3152 return 0; 3153 } 3154 3155 /** 3156 * ice_write_quad_reg_e82x - Write a PHY quad register 3157 * @hw: pointer to the HW struct 3158 * @quad: quad to write to 3159 * @offset: quad register offset to write 3160 * @val: The value to write to the register 3161 * 3162 * Write a quad register over the device sideband queue. Quad registers are 3163 * shared between multiple PHYs. 3164 */ 3165 int 3166 ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val) 3167 { 3168 struct ice_sbq_msg_input msg = {0}; 3169 int err; 3170 3171 err = ice_fill_quad_msg_e82x(hw, &msg, quad, offset); 3172 if (err) 3173 return err; 3174 3175 msg.opcode = ice_sbq_msg_wr; 3176 msg.data = val; 3177 3178 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 3179 if (err) { 3180 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 3181 err); 3182 return err; 3183 } 3184 3185 return 0; 3186 } 3187 3188 /** 3189 * ice_read_phy_tstamp_e82x - Read a PHY timestamp out of the quad block 3190 * @hw: pointer to the HW struct 3191 * @quad: the quad to read from 3192 * @idx: the timestamp index to read 3193 * @tstamp: on return, the 40bit timestamp value 3194 * 3195 * Read a 40bit timestamp value out of the two associated registers in the 3196 * quad memory block that is shared between the internal PHYs of the E822 3197 * family of devices. 3198 */ 3199 static int 3200 ice_read_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp) 3201 { 3202 u16 lo_addr, hi_addr; 3203 u32 lo, hi; 3204 int err; 3205 3206 lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx); 3207 hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx); 3208 3209 err = ice_read_quad_reg_e82x(hw, quad, lo_addr, &lo); 3210 if (err) { 3211 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 3212 err); 3213 return err; 3214 } 3215 3216 err = ice_read_quad_reg_e82x(hw, quad, hi_addr, &hi); 3217 if (err) { 3218 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 3219 err); 3220 return err; 3221 } 3222 3223 /* For E822 based internal PHYs, the timestamp is reported with the 3224 * lower 8 bits in the low register, and the upper 32 bits in the high 3225 * register. 3226 */ 3227 *tstamp = FIELD_PREP(PHY_40B_HIGH_M, hi) | 3228 FIELD_PREP(PHY_40B_LOW_M, lo); 3229 3230 return 0; 3231 } 3232 3233 /** 3234 * ice_clear_phy_tstamp_e82x - Clear a timestamp from the quad block 3235 * @hw: pointer to the HW struct 3236 * @quad: the quad to read from 3237 * @idx: the timestamp index to reset 3238 * 3239 * Read the timestamp out of the quad to clear its timestamp status bit from 3240 * the PHY quad block that is shared between the internal PHYs of the E822 3241 * devices. 3242 * 3243 * Note that unlike E810, software cannot directly write to the quad memory 3244 * bank registers. E822 relies on the ice_get_phy_tx_tstamp_ready() function 3245 * to determine which timestamps are valid. Reading a timestamp auto-clears 3246 * the valid bit. 3247 * 3248 * To directly clear the contents of the timestamp block entirely, discarding 3249 * all timestamp data at once, software should instead use 3250 * ice_ptp_reset_ts_memory_quad_e82x(). 3251 * 3252 * This function should only be called on an idx whose bit is set according to 3253 * ice_get_phy_tx_tstamp_ready(). 3254 */ 3255 static int 3256 ice_clear_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx) 3257 { 3258 u64 unused_tstamp; 3259 int err; 3260 3261 err = ice_read_phy_tstamp_e82x(hw, quad, idx, &unused_tstamp); 3262 if (err) { 3263 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for quad %u, idx %u, err %d\n", 3264 quad, idx, err); 3265 return err; 3266 } 3267 3268 return 0; 3269 } 3270 3271 /** 3272 * ice_ptp_reset_ts_memory_quad_e82x - Clear all timestamps from the quad block 3273 * @hw: pointer to the HW struct 3274 * @quad: the quad to read from 3275 * 3276 * Clear all timestamps from the PHY quad block that is shared between the 3277 * internal PHYs on the E822 devices. 3278 */ 3279 void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad) 3280 { 3281 ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M); 3282 ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M); 3283 } 3284 3285 /** 3286 * ice_ptp_reset_ts_memory_e82x - Clear all timestamps from all quad blocks 3287 * @hw: pointer to the HW struct 3288 */ 3289 static void ice_ptp_reset_ts_memory_e82x(struct ice_hw *hw) 3290 { 3291 unsigned int quad; 3292 3293 for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports); quad++) 3294 ice_ptp_reset_ts_memory_quad_e82x(hw, quad); 3295 } 3296 3297 /** 3298 * ice_ptp_set_vernier_wl - Set the window length for vernier calibration 3299 * @hw: pointer to the HW struct 3300 * 3301 * Set the window length used for the vernier port calibration process. 3302 */ 3303 static int ice_ptp_set_vernier_wl(struct ice_hw *hw) 3304 { 3305 u8 port; 3306 3307 for (port = 0; port < hw->ptp.num_lports; port++) { 3308 int err; 3309 3310 err = ice_write_phy_reg_e82x(hw, port, P_REG_WL, 3311 PTP_VERNIER_WL); 3312 if (err) { 3313 ice_debug(hw, ICE_DBG_PTP, "Failed to set vernier window length for port %u, err %d\n", 3314 port, err); 3315 return err; 3316 } 3317 } 3318 3319 return 0; 3320 } 3321 3322 /** 3323 * ice_ptp_init_phc_e82x - Perform E822 specific PHC initialization 3324 * @hw: pointer to HW struct 3325 * 3326 * Perform PHC initialization steps specific to E822 devices. 3327 */ 3328 static int ice_ptp_init_phc_e82x(struct ice_hw *hw) 3329 { 3330 int err; 3331 u32 val; 3332 3333 /* Enable reading switch and PHY registers over the sideband queue */ 3334 #define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1) 3335 #define PF_SB_REM_DEV_CTL_PHY0 BIT(2) 3336 val = rd32(hw, PF_SB_REM_DEV_CTL); 3337 val |= (PF_SB_REM_DEV_CTL_SWITCH_READ | PF_SB_REM_DEV_CTL_PHY0); 3338 wr32(hw, PF_SB_REM_DEV_CTL, val); 3339 3340 /* Initialize the Clock Generation Unit */ 3341 err = ice_init_cgu_e82x(hw); 3342 if (err) 3343 return err; 3344 3345 /* Set window length for all the ports */ 3346 return ice_ptp_set_vernier_wl(hw); 3347 } 3348 3349 /** 3350 * ice_ptp_prep_phy_time_e82x - Prepare PHY port with initial time 3351 * @hw: pointer to the HW struct 3352 * @time: Time to initialize the PHY port clocks to 3353 * 3354 * Program the PHY port registers with a new initial time value. The port 3355 * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync 3356 * command. The time value is the upper 32 bits of the PHY timer, usually in 3357 * units of nominal nanoseconds. 3358 */ 3359 static int 3360 ice_ptp_prep_phy_time_e82x(struct ice_hw *hw, u32 time) 3361 { 3362 u64 phy_time; 3363 u8 port; 3364 int err; 3365 3366 /* The time represents the upper 32 bits of the PHY timer, so we need 3367 * to shift to account for this when programming. 3368 */ 3369 phy_time = (u64)time << 32; 3370 3371 for (port = 0; port < hw->ptp.num_lports; port++) { 3372 /* Tx case */ 3373 err = ice_write_64b_phy_reg_e82x(hw, port, 3374 P_REG_TX_TIMER_INC_PRE_L, 3375 phy_time); 3376 if (err) 3377 goto exit_err; 3378 3379 /* Rx case */ 3380 err = ice_write_64b_phy_reg_e82x(hw, port, 3381 P_REG_RX_TIMER_INC_PRE_L, 3382 phy_time); 3383 if (err) 3384 goto exit_err; 3385 } 3386 3387 return 0; 3388 3389 exit_err: 3390 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n", 3391 port, err); 3392 3393 return err; 3394 } 3395 3396 /** 3397 * ice_ptp_prep_port_adj_e82x - Prepare a single port for time adjust 3398 * @hw: pointer to HW struct 3399 * @port: Port number to be programmed 3400 * @time: time in cycles to adjust the port Tx and Rx clocks 3401 * 3402 * Program the port for an atomic adjustment by writing the Tx and Rx timer 3403 * registers. The atomic adjustment won't be completed until the driver issues 3404 * an ICE_PTP_ADJ_TIME command. 3405 * 3406 * Note that time is not in units of nanoseconds. It is in clock time 3407 * including the lower sub-nanosecond portion of the port timer. 3408 * 3409 * Negative adjustments are supported using 2s complement arithmetic. 3410 */ 3411 static int 3412 ice_ptp_prep_port_adj_e82x(struct ice_hw *hw, u8 port, s64 time) 3413 { 3414 u32 l_time, u_time; 3415 int err; 3416 3417 l_time = lower_32_bits(time); 3418 u_time = upper_32_bits(time); 3419 3420 /* Tx case */ 3421 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TIMER_INC_PRE_L, 3422 l_time); 3423 if (err) 3424 goto exit_err; 3425 3426 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TIMER_INC_PRE_U, 3427 u_time); 3428 if (err) 3429 goto exit_err; 3430 3431 /* Rx case */ 3432 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TIMER_INC_PRE_L, 3433 l_time); 3434 if (err) 3435 goto exit_err; 3436 3437 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TIMER_INC_PRE_U, 3438 u_time); 3439 if (err) 3440 goto exit_err; 3441 3442 return 0; 3443 3444 exit_err: 3445 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n", 3446 port, err); 3447 return err; 3448 } 3449 3450 /** 3451 * ice_ptp_prep_phy_adj_e82x - Prep PHY ports for a time adjustment 3452 * @hw: pointer to HW struct 3453 * @adj: adjustment in nanoseconds 3454 * 3455 * Prepare the PHY ports for an atomic time adjustment by programming the PHY 3456 * Tx and Rx port registers. The actual adjustment is completed by issuing an 3457 * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command. 3458 */ 3459 static int 3460 ice_ptp_prep_phy_adj_e82x(struct ice_hw *hw, s32 adj) 3461 { 3462 s64 cycles; 3463 u8 port; 3464 3465 /* The port clock supports adjustment of the sub-nanosecond portion of 3466 * the clock. We shift the provided adjustment in nanoseconds to 3467 * calculate the appropriate adjustment to program into the PHY ports. 3468 */ 3469 if (adj > 0) 3470 cycles = (s64)adj << 32; 3471 else 3472 cycles = -(((s64)-adj) << 32); 3473 3474 for (port = 0; port < hw->ptp.num_lports; port++) { 3475 int err; 3476 3477 err = ice_ptp_prep_port_adj_e82x(hw, port, cycles); 3478 if (err) 3479 return err; 3480 } 3481 3482 return 0; 3483 } 3484 3485 /** 3486 * ice_ptp_prep_phy_incval_e82x - Prepare PHY ports for time adjustment 3487 * @hw: pointer to HW struct 3488 * @incval: new increment value to prepare 3489 * 3490 * Prepare each of the PHY ports for a new increment value by programming the 3491 * port's TIMETUS registers. The new increment value will be updated after 3492 * issuing an ICE_PTP_INIT_INCVAL command. 3493 */ 3494 static int 3495 ice_ptp_prep_phy_incval_e82x(struct ice_hw *hw, u64 incval) 3496 { 3497 int err; 3498 u8 port; 3499 3500 for (port = 0; port < hw->ptp.num_lports; port++) { 3501 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L, 3502 incval); 3503 if (err) 3504 goto exit_err; 3505 } 3506 3507 return 0; 3508 3509 exit_err: 3510 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n", 3511 port, err); 3512 3513 return err; 3514 } 3515 3516 /** 3517 * ice_ptp_read_port_capture - Read a port's local time capture 3518 * @hw: pointer to HW struct 3519 * @port: Port number to read 3520 * @tx_ts: on return, the Tx port time capture 3521 * @rx_ts: on return, the Rx port time capture 3522 * 3523 * Read the port's Tx and Rx local time capture values. 3524 * 3525 * Note this has no equivalent for the E810 devices. 3526 */ 3527 static int 3528 ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts) 3529 { 3530 int err; 3531 3532 /* Tx case */ 3533 err = ice_read_64b_phy_reg_e82x(hw, port, P_REG_TX_CAPTURE_L, tx_ts); 3534 if (err) { 3535 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n", 3536 err); 3537 return err; 3538 } 3539 3540 ice_debug(hw, ICE_DBG_PTP, "tx_init = 0x%016llx\n", 3541 (unsigned long long)*tx_ts); 3542 3543 /* Rx case */ 3544 err = ice_read_64b_phy_reg_e82x(hw, port, P_REG_RX_CAPTURE_L, rx_ts); 3545 if (err) { 3546 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n", 3547 err); 3548 return err; 3549 } 3550 3551 ice_debug(hw, ICE_DBG_PTP, "rx_init = 0x%016llx\n", 3552 (unsigned long long)*rx_ts); 3553 3554 return 0; 3555 } 3556 3557 /** 3558 * ice_ptp_write_port_cmd_e82x - Prepare a single PHY port for a timer command 3559 * @hw: pointer to HW struct 3560 * @port: Port to which cmd has to be sent 3561 * @cmd: Command to be sent to the port 3562 * 3563 * Prepare the requested port for an upcoming timer sync command. 3564 * 3565 * Note there is no equivalent of this operation on E810, as that device 3566 * always handles all external PHYs internally. 3567 * 3568 * Return: 3569 * * %0 - success 3570 * * %other - failed to write to PHY 3571 */ 3572 static int ice_ptp_write_port_cmd_e82x(struct ice_hw *hw, u8 port, 3573 enum ice_ptp_tmr_cmd cmd) 3574 { 3575 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 3576 int err; 3577 3578 /* Tx case */ 3579 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TMR_CMD, val); 3580 if (err) { 3581 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n", 3582 err); 3583 return err; 3584 } 3585 3586 /* Rx case */ 3587 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TMR_CMD, 3588 val | TS_CMD_RX_TYPE); 3589 if (err) { 3590 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n", 3591 err); 3592 return err; 3593 } 3594 3595 return 0; 3596 } 3597 3598 /* E822 Vernier calibration functions 3599 * 3600 * The following functions are used as part of the vernier calibration of 3601 * a port. This calibration increases the precision of the timestamps on the 3602 * port. 3603 */ 3604 3605 /** 3606 * ice_phy_get_speed_and_fec_e82x - Get link speed and FEC based on serdes mode 3607 * @hw: pointer to HW struct 3608 * @port: the port to read from 3609 * @link_out: if non-NULL, holds link speed on success 3610 * @fec_out: if non-NULL, holds FEC algorithm on success 3611 * 3612 * Read the serdes data for the PHY port and extract the link speed and FEC 3613 * algorithm. 3614 */ 3615 static int 3616 ice_phy_get_speed_and_fec_e82x(struct ice_hw *hw, u8 port, 3617 enum ice_ptp_link_spd *link_out, 3618 enum ice_ptp_fec_mode *fec_out) 3619 { 3620 enum ice_ptp_link_spd link; 3621 enum ice_ptp_fec_mode fec; 3622 u32 serdes; 3623 int err; 3624 3625 err = ice_read_phy_reg_e82x(hw, port, P_REG_LINK_SPEED, &serdes); 3626 if (err) { 3627 ice_debug(hw, ICE_DBG_PTP, "Failed to read serdes info\n"); 3628 return err; 3629 } 3630 3631 /* Determine the FEC algorithm */ 3632 fec = (enum ice_ptp_fec_mode)P_REG_LINK_SPEED_FEC_MODE(serdes); 3633 3634 serdes &= P_REG_LINK_SPEED_SERDES_M; 3635 3636 /* Determine the link speed */ 3637 if (fec == ICE_PTP_FEC_MODE_RS_FEC) { 3638 switch (serdes) { 3639 case ICE_PTP_SERDES_25G: 3640 link = ICE_PTP_LNK_SPD_25G_RS; 3641 break; 3642 case ICE_PTP_SERDES_50G: 3643 link = ICE_PTP_LNK_SPD_50G_RS; 3644 break; 3645 case ICE_PTP_SERDES_100G: 3646 link = ICE_PTP_LNK_SPD_100G_RS; 3647 break; 3648 default: 3649 return -EIO; 3650 } 3651 } else { 3652 switch (serdes) { 3653 case ICE_PTP_SERDES_1G: 3654 link = ICE_PTP_LNK_SPD_1G; 3655 break; 3656 case ICE_PTP_SERDES_10G: 3657 link = ICE_PTP_LNK_SPD_10G; 3658 break; 3659 case ICE_PTP_SERDES_25G: 3660 link = ICE_PTP_LNK_SPD_25G; 3661 break; 3662 case ICE_PTP_SERDES_40G: 3663 link = ICE_PTP_LNK_SPD_40G; 3664 break; 3665 case ICE_PTP_SERDES_50G: 3666 link = ICE_PTP_LNK_SPD_50G; 3667 break; 3668 default: 3669 return -EIO; 3670 } 3671 } 3672 3673 if (link_out) 3674 *link_out = link; 3675 if (fec_out) 3676 *fec_out = fec; 3677 3678 return 0; 3679 } 3680 3681 /** 3682 * ice_phy_cfg_lane_e82x - Configure PHY quad for single/multi-lane timestamp 3683 * @hw: pointer to HW struct 3684 * @port: to configure the quad for 3685 */ 3686 static void ice_phy_cfg_lane_e82x(struct ice_hw *hw, u8 port) 3687 { 3688 enum ice_ptp_link_spd link_spd; 3689 int err; 3690 u32 val; 3691 u8 quad; 3692 3693 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, NULL); 3694 if (err) { 3695 ice_debug(hw, ICE_DBG_PTP, "Failed to get PHY link speed, err %d\n", 3696 err); 3697 return; 3698 } 3699 3700 quad = ICE_GET_QUAD_NUM(port); 3701 3702 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val); 3703 if (err) { 3704 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEM_GLB_CFG, err %d\n", 3705 err); 3706 return; 3707 } 3708 3709 if (link_spd >= ICE_PTP_LNK_SPD_40G) 3710 val &= ~Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M; 3711 else 3712 val |= Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M; 3713 3714 err = ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val); 3715 if (err) { 3716 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_MEM_GBL_CFG, err %d\n", 3717 err); 3718 return; 3719 } 3720 } 3721 3722 /** 3723 * ice_phy_cfg_uix_e82x - Configure Serdes UI to TU conversion for E822 3724 * @hw: pointer to the HW structure 3725 * @port: the port to configure 3726 * 3727 * Program the conversion ration of Serdes clock "unit intervals" (UIs) to PHC 3728 * hardware clock time units (TUs). That is, determine the number of TUs per 3729 * serdes unit interval, and program the UIX registers with this conversion. 3730 * 3731 * This conversion is used as part of the calibration process when determining 3732 * the additional error of a timestamp vs the real time of transmission or 3733 * receipt of the packet. 3734 * 3735 * Hardware uses the number of TUs per 66 UIs, written to the UIX registers 3736 * for the two main serdes clock rates, 10G/40G and 25G/100G serdes clocks. 3737 * 3738 * To calculate the conversion ratio, we use the following facts: 3739 * 3740 * a) the clock frequency in Hz (cycles per second) 3741 * b) the number of TUs per cycle (the increment value of the clock) 3742 * c) 1 second per 1 billion nanoseconds 3743 * d) the duration of 66 UIs in nanoseconds 3744 * 3745 * Given these facts, we can use the following table to work out what ratios 3746 * to multiply in order to get the number of TUs per 66 UIs: 3747 * 3748 * cycles | 1 second | incval (TUs) | nanoseconds 3749 * -------+--------------+--------------+------------- 3750 * second | 1 billion ns | cycle | 66 UIs 3751 * 3752 * To perform the multiplication using integers without too much loss of 3753 * precision, we can take use the following equation: 3754 * 3755 * (freq * incval * 6600 LINE_UI ) / ( 100 * 1 billion) 3756 * 3757 * We scale up to using 6600 UI instead of 66 in order to avoid fractional 3758 * nanosecond UIs (66 UI at 10G/40G is 6.4 ns) 3759 * 3760 * The increment value has a maximum expected range of about 34 bits, while 3761 * the frequency value is about 29 bits. Multiplying these values shouldn't 3762 * overflow the 64 bits. However, we must then further multiply them again by 3763 * the Serdes unit interval duration. To avoid overflow here, we split the 3764 * overall divide by 1e11 into a divide by 256 (shift down by 8 bits) and 3765 * a divide by 390,625,000. This does lose some precision, but avoids 3766 * miscalculation due to arithmetic overflow. 3767 */ 3768 static int ice_phy_cfg_uix_e82x(struct ice_hw *hw, u8 port) 3769 { 3770 u64 cur_freq, clk_incval, tu_per_sec, uix; 3771 int err; 3772 3773 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3774 clk_incval = ice_ptp_read_src_incval(hw); 3775 3776 /* Calculate TUs per second divided by 256 */ 3777 tu_per_sec = (cur_freq * clk_incval) >> 8; 3778 3779 #define LINE_UI_10G_40G 640 /* 6600 UIs is 640 nanoseconds at 10Gb/40Gb */ 3780 #define LINE_UI_25G_100G 256 /* 6600 UIs is 256 nanoseconds at 25Gb/100Gb */ 3781 3782 /* Program the 10Gb/40Gb conversion ratio */ 3783 uix = div_u64(tu_per_sec * LINE_UI_10G_40G, 390625000); 3784 3785 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_UIX66_10G_40G_L, 3786 uix); 3787 if (err) { 3788 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_10G_40G, err %d\n", 3789 err); 3790 return err; 3791 } 3792 3793 /* Program the 25Gb/100Gb conversion ratio */ 3794 uix = div_u64(tu_per_sec * LINE_UI_25G_100G, 390625000); 3795 3796 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_UIX66_25G_100G_L, 3797 uix); 3798 if (err) { 3799 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_25G_100G, err %d\n", 3800 err); 3801 return err; 3802 } 3803 3804 return 0; 3805 } 3806 3807 /** 3808 * ice_phy_cfg_parpcs_e82x - Configure TUs per PAR/PCS clock cycle 3809 * @hw: pointer to the HW struct 3810 * @port: port to configure 3811 * 3812 * Configure the number of TUs for the PAR and PCS clocks used as part of the 3813 * timestamp calibration process. This depends on the link speed, as the PHY 3814 * uses different markers depending on the speed. 3815 * 3816 * 1Gb/10Gb/25Gb: 3817 * - Tx/Rx PAR/PCS markers 3818 * 3819 * 25Gb RS: 3820 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers 3821 * 3822 * 40Gb/50Gb: 3823 * - Tx/Rx PAR/PCS markers 3824 * - Rx Deskew PAR/PCS markers 3825 * 3826 * 50G RS and 100GB RS: 3827 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers 3828 * - Rx Deskew PAR/PCS markers 3829 * - Tx PAR/PCS markers 3830 * 3831 * To calculate the conversion, we use the PHC clock frequency (cycles per 3832 * second), the increment value (TUs per cycle), and the related PHY clock 3833 * frequency to calculate the TUs per unit of the PHY link clock. The 3834 * following table shows how the units convert: 3835 * 3836 * cycles | TUs | second 3837 * -------+-------+-------- 3838 * second | cycle | cycles 3839 * 3840 * For each conversion register, look up the appropriate frequency from the 3841 * e822 PAR/PCS table and calculate the TUs per unit of that clock. Program 3842 * this to the appropriate register, preparing hardware to perform timestamp 3843 * calibration to calculate the total Tx or Rx offset to adjust the timestamp 3844 * in order to calibrate for the internal PHY delays. 3845 * 3846 * Note that the increment value ranges up to ~34 bits, and the clock 3847 * frequency is ~29 bits, so multiplying them together should fit within the 3848 * 64 bit arithmetic. 3849 */ 3850 static int ice_phy_cfg_parpcs_e82x(struct ice_hw *hw, u8 port) 3851 { 3852 u64 cur_freq, clk_incval, tu_per_sec, phy_tus; 3853 enum ice_ptp_link_spd link_spd; 3854 enum ice_ptp_fec_mode fec_mode; 3855 int err; 3856 3857 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode); 3858 if (err) 3859 return err; 3860 3861 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3862 clk_incval = ice_ptp_read_src_incval(hw); 3863 3864 /* Calculate TUs per cycle of the PHC clock */ 3865 tu_per_sec = cur_freq * clk_incval; 3866 3867 /* For each PHY conversion register, look up the appropriate link 3868 * speed frequency and determine the TUs per that clock's cycle time. 3869 * Split this into a high and low value and then program the 3870 * appropriate register. If that link speed does not use the 3871 * associated register, write zeros to clear it instead. 3872 */ 3873 3874 /* P_REG_PAR_TX_TUS */ 3875 if (e822_vernier[link_spd].tx_par_clk) 3876 phy_tus = div_u64(tu_per_sec, 3877 e822_vernier[link_spd].tx_par_clk); 3878 else 3879 phy_tus = 0; 3880 3881 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PAR_TX_TUS_L, 3882 phy_tus); 3883 if (err) 3884 return err; 3885 3886 /* P_REG_PAR_RX_TUS */ 3887 if (e822_vernier[link_spd].rx_par_clk) 3888 phy_tus = div_u64(tu_per_sec, 3889 e822_vernier[link_spd].rx_par_clk); 3890 else 3891 phy_tus = 0; 3892 3893 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PAR_RX_TUS_L, 3894 phy_tus); 3895 if (err) 3896 return err; 3897 3898 /* P_REG_PCS_TX_TUS */ 3899 if (e822_vernier[link_spd].tx_pcs_clk) 3900 phy_tus = div_u64(tu_per_sec, 3901 e822_vernier[link_spd].tx_pcs_clk); 3902 else 3903 phy_tus = 0; 3904 3905 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PCS_TX_TUS_L, 3906 phy_tus); 3907 if (err) 3908 return err; 3909 3910 /* P_REG_PCS_RX_TUS */ 3911 if (e822_vernier[link_spd].rx_pcs_clk) 3912 phy_tus = div_u64(tu_per_sec, 3913 e822_vernier[link_spd].rx_pcs_clk); 3914 else 3915 phy_tus = 0; 3916 3917 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PCS_RX_TUS_L, 3918 phy_tus); 3919 if (err) 3920 return err; 3921 3922 /* P_REG_DESK_PAR_TX_TUS */ 3923 if (e822_vernier[link_spd].tx_desk_rsgb_par) 3924 phy_tus = div_u64(tu_per_sec, 3925 e822_vernier[link_spd].tx_desk_rsgb_par); 3926 else 3927 phy_tus = 0; 3928 3929 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PAR_TX_TUS_L, 3930 phy_tus); 3931 if (err) 3932 return err; 3933 3934 /* P_REG_DESK_PAR_RX_TUS */ 3935 if (e822_vernier[link_spd].rx_desk_rsgb_par) 3936 phy_tus = div_u64(tu_per_sec, 3937 e822_vernier[link_spd].rx_desk_rsgb_par); 3938 else 3939 phy_tus = 0; 3940 3941 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PAR_RX_TUS_L, 3942 phy_tus); 3943 if (err) 3944 return err; 3945 3946 /* P_REG_DESK_PCS_TX_TUS */ 3947 if (e822_vernier[link_spd].tx_desk_rsgb_pcs) 3948 phy_tus = div_u64(tu_per_sec, 3949 e822_vernier[link_spd].tx_desk_rsgb_pcs); 3950 else 3951 phy_tus = 0; 3952 3953 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PCS_TX_TUS_L, 3954 phy_tus); 3955 if (err) 3956 return err; 3957 3958 /* P_REG_DESK_PCS_RX_TUS */ 3959 if (e822_vernier[link_spd].rx_desk_rsgb_pcs) 3960 phy_tus = div_u64(tu_per_sec, 3961 e822_vernier[link_spd].rx_desk_rsgb_pcs); 3962 else 3963 phy_tus = 0; 3964 3965 return ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PCS_RX_TUS_L, 3966 phy_tus); 3967 } 3968 3969 /** 3970 * ice_calc_fixed_tx_offset_e82x - Calculated Fixed Tx offset for a port 3971 * @hw: pointer to the HW struct 3972 * @link_spd: the Link speed to calculate for 3973 * 3974 * Calculate the fixed offset due to known static latency data. 3975 */ 3976 static u64 3977 ice_calc_fixed_tx_offset_e82x(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) 3978 { 3979 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset; 3980 3981 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3982 clk_incval = ice_ptp_read_src_incval(hw); 3983 3984 /* Calculate TUs per second */ 3985 tu_per_sec = cur_freq * clk_incval; 3986 3987 /* Calculate number of TUs to add for the fixed Tx latency. Since the 3988 * latency measurement is in 1/100th of a nanosecond, we need to 3989 * multiply by tu_per_sec and then divide by 1e11. This calculation 3990 * overflows 64 bit integer arithmetic, so break it up into two 3991 * divisions by 1e4 first then by 1e7. 3992 */ 3993 fixed_offset = div_u64(tu_per_sec, 10000); 3994 fixed_offset *= e822_vernier[link_spd].tx_fixed_delay; 3995 fixed_offset = div_u64(fixed_offset, 10000000); 3996 3997 return fixed_offset; 3998 } 3999 4000 /** 4001 * ice_phy_cfg_tx_offset_e82x - Configure total Tx timestamp offset 4002 * @hw: pointer to the HW struct 4003 * @port: the PHY port to configure 4004 * 4005 * Program the P_REG_TOTAL_TX_OFFSET register with the total number of TUs to 4006 * adjust Tx timestamps by. This is calculated by combining some known static 4007 * latency along with the Vernier offset computations done by hardware. 4008 * 4009 * This function will not return successfully until the Tx offset calculations 4010 * have been completed, which requires waiting until at least one packet has 4011 * been transmitted by the device. It is safe to call this function 4012 * periodically until calibration succeeds, as it will only program the offset 4013 * once. 4014 * 4015 * To avoid overflow, when calculating the offset based on the known static 4016 * latency values, we use measurements in 1/100th of a nanosecond, and divide 4017 * the TUs per second up front. This avoids overflow while allowing 4018 * calculation of the adjustment using integer arithmetic. 4019 * 4020 * Returns zero on success, -EBUSY if the hardware vernier offset 4021 * calibration has not completed, or another error code on failure. 4022 */ 4023 int ice_phy_cfg_tx_offset_e82x(struct ice_hw *hw, u8 port) 4024 { 4025 enum ice_ptp_link_spd link_spd; 4026 enum ice_ptp_fec_mode fec_mode; 4027 u64 total_offset, val; 4028 int err; 4029 u32 reg; 4030 4031 /* Nothing to do if we've already programmed the offset */ 4032 err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_OR, ®); 4033 if (err) { 4034 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OR for port %u, err %d\n", 4035 port, err); 4036 return err; 4037 } 4038 4039 if (reg) 4040 return 0; 4041 4042 err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_OV_STATUS, ®); 4043 if (err) { 4044 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OV_STATUS for port %u, err %d\n", 4045 port, err); 4046 return err; 4047 } 4048 4049 if (!(reg & P_REG_TX_OV_STATUS_OV_M)) 4050 return -EBUSY; 4051 4052 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode); 4053 if (err) 4054 return err; 4055 4056 total_offset = ice_calc_fixed_tx_offset_e82x(hw, link_spd); 4057 4058 /* Read the first Vernier offset from the PHY register and add it to 4059 * the total offset. 4060 */ 4061 if (link_spd == ICE_PTP_LNK_SPD_1G || 4062 link_spd == ICE_PTP_LNK_SPD_10G || 4063 link_spd == ICE_PTP_LNK_SPD_25G || 4064 link_spd == ICE_PTP_LNK_SPD_25G_RS || 4065 link_spd == ICE_PTP_LNK_SPD_40G || 4066 link_spd == ICE_PTP_LNK_SPD_50G) { 4067 err = ice_read_64b_phy_reg_e82x(hw, port, 4068 P_REG_PAR_PCS_TX_OFFSET_L, 4069 &val); 4070 if (err) 4071 return err; 4072 4073 total_offset += val; 4074 } 4075 4076 /* For Tx, we only need to use the second Vernier offset for 4077 * multi-lane link speeds with RS-FEC. The lanes will always be 4078 * aligned. 4079 */ 4080 if (link_spd == ICE_PTP_LNK_SPD_50G_RS || 4081 link_spd == ICE_PTP_LNK_SPD_100G_RS) { 4082 err = ice_read_64b_phy_reg_e82x(hw, port, 4083 P_REG_PAR_TX_TIME_L, 4084 &val); 4085 if (err) 4086 return err; 4087 4088 total_offset += val; 4089 } 4090 4091 /* Now that the total offset has been calculated, program it to the 4092 * PHY and indicate that the Tx offset is ready. After this, 4093 * timestamps will be enabled. 4094 */ 4095 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_TOTAL_TX_OFFSET_L, 4096 total_offset); 4097 if (err) 4098 return err; 4099 4100 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 1); 4101 if (err) 4102 return err; 4103 4104 dev_info(ice_hw_to_dev(hw), "Port=%d Tx vernier offset calibration complete\n", 4105 port); 4106 4107 return 0; 4108 } 4109 4110 /** 4111 * ice_phy_calc_pmd_adj_e82x - Calculate PMD adjustment for Rx 4112 * @hw: pointer to the HW struct 4113 * @port: the PHY port to adjust for 4114 * @link_spd: the current link speed of the PHY 4115 * @fec_mode: the current FEC mode of the PHY 4116 * @pmd_adj: on return, the amount to adjust the Rx total offset by 4117 * 4118 * Calculates the adjustment to Rx timestamps due to PMD alignment in the PHY. 4119 * This varies by link speed and FEC mode. The value calculated accounts for 4120 * various delays caused when receiving a packet. 4121 */ 4122 static int 4123 ice_phy_calc_pmd_adj_e82x(struct ice_hw *hw, u8 port, 4124 enum ice_ptp_link_spd link_spd, 4125 enum ice_ptp_fec_mode fec_mode, u64 *pmd_adj) 4126 { 4127 u64 cur_freq, clk_incval, tu_per_sec, mult, adj; 4128 u8 pmd_align; 4129 u32 val; 4130 int err; 4131 4132 err = ice_read_phy_reg_e82x(hw, port, P_REG_PMD_ALIGNMENT, &val); 4133 if (err) { 4134 ice_debug(hw, ICE_DBG_PTP, "Failed to read PMD alignment, err %d\n", 4135 err); 4136 return err; 4137 } 4138 4139 pmd_align = (u8)val; 4140 4141 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 4142 clk_incval = ice_ptp_read_src_incval(hw); 4143 4144 /* Calculate TUs per second */ 4145 tu_per_sec = cur_freq * clk_incval; 4146 4147 /* The PMD alignment adjustment measurement depends on the link speed, 4148 * and whether FEC is enabled. For each link speed, the alignment 4149 * adjustment is calculated by dividing a value by the length of 4150 * a Time Unit in nanoseconds. 4151 * 4152 * 1G: align == 4 ? 10 * 0.8 : (align + 6 % 10) * 0.8 4153 * 10G: align == 65 ? 0 : (align * 0.1 * 32/33) 4154 * 10G w/FEC: align * 0.1 * 32/33 4155 * 25G: align == 65 ? 0 : (align * 0.4 * 32/33) 4156 * 25G w/FEC: align * 0.4 * 32/33 4157 * 40G: align == 65 ? 0 : (align * 0.1 * 32/33) 4158 * 40G w/FEC: align * 0.1 * 32/33 4159 * 50G: align == 65 ? 0 : (align * 0.4 * 32/33) 4160 * 50G w/FEC: align * 0.8 * 32/33 4161 * 4162 * For RS-FEC, if align is < 17 then we must also add 1.6 * 32/33. 4163 * 4164 * To allow for calculating this value using integer arithmetic, we 4165 * instead start with the number of TUs per second, (inverse of the 4166 * length of a Time Unit in nanoseconds), multiply by a value based 4167 * on the PMD alignment register, and then divide by the right value 4168 * calculated based on the table above. To avoid integer overflow this 4169 * division is broken up into a step of dividing by 125 first. 4170 */ 4171 if (link_spd == ICE_PTP_LNK_SPD_1G) { 4172 if (pmd_align == 4) 4173 mult = 10; 4174 else 4175 mult = (pmd_align + 6) % 10; 4176 } else if (link_spd == ICE_PTP_LNK_SPD_10G || 4177 link_spd == ICE_PTP_LNK_SPD_25G || 4178 link_spd == ICE_PTP_LNK_SPD_40G || 4179 link_spd == ICE_PTP_LNK_SPD_50G) { 4180 /* If Clause 74 FEC, always calculate PMD adjust */ 4181 if (pmd_align != 65 || fec_mode == ICE_PTP_FEC_MODE_CLAUSE74) 4182 mult = pmd_align; 4183 else 4184 mult = 0; 4185 } else if (link_spd == ICE_PTP_LNK_SPD_25G_RS || 4186 link_spd == ICE_PTP_LNK_SPD_50G_RS || 4187 link_spd == ICE_PTP_LNK_SPD_100G_RS) { 4188 if (pmd_align < 17) 4189 mult = pmd_align + 40; 4190 else 4191 mult = pmd_align; 4192 } else { 4193 ice_debug(hw, ICE_DBG_PTP, "Unknown link speed %d, skipping PMD adjustment\n", 4194 link_spd); 4195 mult = 0; 4196 } 4197 4198 /* In some cases, there's no need to adjust for the PMD alignment */ 4199 if (!mult) { 4200 *pmd_adj = 0; 4201 return 0; 4202 } 4203 4204 /* Calculate the adjustment by multiplying TUs per second by the 4205 * appropriate multiplier and divisor. To avoid overflow, we first 4206 * divide by 125, and then handle remaining divisor based on the link 4207 * speed pmd_adj_divisor value. 4208 */ 4209 adj = div_u64(tu_per_sec, 125); 4210 adj *= mult; 4211 adj = div_u64(adj, e822_vernier[link_spd].pmd_adj_divisor); 4212 4213 /* Finally, for 25G-RS and 50G-RS, a further adjustment for the Rx 4214 * cycle count is necessary. 4215 */ 4216 if (link_spd == ICE_PTP_LNK_SPD_25G_RS) { 4217 u64 cycle_adj; 4218 u8 rx_cycle; 4219 4220 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_40_TO_160_CNT, 4221 &val); 4222 if (err) { 4223 ice_debug(hw, ICE_DBG_PTP, "Failed to read 25G-RS Rx cycle count, err %d\n", 4224 err); 4225 return err; 4226 } 4227 4228 rx_cycle = val & P_REG_RX_40_TO_160_CNT_RXCYC_M; 4229 if (rx_cycle) { 4230 mult = (4 - rx_cycle) * 40; 4231 4232 cycle_adj = div_u64(tu_per_sec, 125); 4233 cycle_adj *= mult; 4234 cycle_adj = div_u64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor); 4235 4236 adj += cycle_adj; 4237 } 4238 } else if (link_spd == ICE_PTP_LNK_SPD_50G_RS) { 4239 u64 cycle_adj; 4240 u8 rx_cycle; 4241 4242 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_80_TO_160_CNT, 4243 &val); 4244 if (err) { 4245 ice_debug(hw, ICE_DBG_PTP, "Failed to read 50G-RS Rx cycle count, err %d\n", 4246 err); 4247 return err; 4248 } 4249 4250 rx_cycle = val & P_REG_RX_80_TO_160_CNT_RXCYC_M; 4251 if (rx_cycle) { 4252 mult = rx_cycle * 40; 4253 4254 cycle_adj = div_u64(tu_per_sec, 125); 4255 cycle_adj *= mult; 4256 cycle_adj = div_u64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor); 4257 4258 adj += cycle_adj; 4259 } 4260 } 4261 4262 /* Return the calculated adjustment */ 4263 *pmd_adj = adj; 4264 4265 return 0; 4266 } 4267 4268 /** 4269 * ice_calc_fixed_rx_offset_e82x - Calculated the fixed Rx offset for a port 4270 * @hw: pointer to HW struct 4271 * @link_spd: The Link speed to calculate for 4272 * 4273 * Determine the fixed Rx latency for a given link speed. 4274 */ 4275 static u64 4276 ice_calc_fixed_rx_offset_e82x(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) 4277 { 4278 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset; 4279 4280 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 4281 clk_incval = ice_ptp_read_src_incval(hw); 4282 4283 /* Calculate TUs per second */ 4284 tu_per_sec = cur_freq * clk_incval; 4285 4286 /* Calculate number of TUs to add for the fixed Rx latency. Since the 4287 * latency measurement is in 1/100th of a nanosecond, we need to 4288 * multiply by tu_per_sec and then divide by 1e11. This calculation 4289 * overflows 64 bit integer arithmetic, so break it up into two 4290 * divisions by 1e4 first then by 1e7. 4291 */ 4292 fixed_offset = div_u64(tu_per_sec, 10000); 4293 fixed_offset *= e822_vernier[link_spd].rx_fixed_delay; 4294 fixed_offset = div_u64(fixed_offset, 10000000); 4295 4296 return fixed_offset; 4297 } 4298 4299 /** 4300 * ice_phy_cfg_rx_offset_e82x - Configure total Rx timestamp offset 4301 * @hw: pointer to the HW struct 4302 * @port: the PHY port to configure 4303 * 4304 * Program the P_REG_TOTAL_RX_OFFSET register with the number of Time Units to 4305 * adjust Rx timestamps by. This combines calculations from the Vernier offset 4306 * measurements taken in hardware with some data about known fixed delay as 4307 * well as adjusting for multi-lane alignment delay. 4308 * 4309 * This function will not return successfully until the Rx offset calculations 4310 * have been completed, which requires waiting until at least one packet has 4311 * been received by the device. It is safe to call this function periodically 4312 * until calibration succeeds, as it will only program the offset once. 4313 * 4314 * This function must be called only after the offset registers are valid, 4315 * i.e. after the Vernier calibration wait has passed, to ensure that the PHY 4316 * has measured the offset. 4317 * 4318 * To avoid overflow, when calculating the offset based on the known static 4319 * latency values, we use measurements in 1/100th of a nanosecond, and divide 4320 * the TUs per second up front. This avoids overflow while allowing 4321 * calculation of the adjustment using integer arithmetic. 4322 * 4323 * Returns zero on success, -EBUSY if the hardware vernier offset 4324 * calibration has not completed, or another error code on failure. 4325 */ 4326 int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port) 4327 { 4328 enum ice_ptp_link_spd link_spd; 4329 enum ice_ptp_fec_mode fec_mode; 4330 u64 total_offset, pmd, val; 4331 int err; 4332 u32 reg; 4333 4334 /* Nothing to do if we've already programmed the offset */ 4335 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_OR, ®); 4336 if (err) { 4337 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OR for port %u, err %d\n", 4338 port, err); 4339 return err; 4340 } 4341 4342 if (reg) 4343 return 0; 4344 4345 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_OV_STATUS, ®); 4346 if (err) { 4347 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OV_STATUS for port %u, err %d\n", 4348 port, err); 4349 return err; 4350 } 4351 4352 if (!(reg & P_REG_RX_OV_STATUS_OV_M)) 4353 return -EBUSY; 4354 4355 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode); 4356 if (err) 4357 return err; 4358 4359 total_offset = ice_calc_fixed_rx_offset_e82x(hw, link_spd); 4360 4361 /* Read the first Vernier offset from the PHY register and add it to 4362 * the total offset. 4363 */ 4364 err = ice_read_64b_phy_reg_e82x(hw, port, 4365 P_REG_PAR_PCS_RX_OFFSET_L, 4366 &val); 4367 if (err) 4368 return err; 4369 4370 total_offset += val; 4371 4372 /* For Rx, all multi-lane link speeds include a second Vernier 4373 * calibration, because the lanes might not be aligned. 4374 */ 4375 if (link_spd == ICE_PTP_LNK_SPD_40G || 4376 link_spd == ICE_PTP_LNK_SPD_50G || 4377 link_spd == ICE_PTP_LNK_SPD_50G_RS || 4378 link_spd == ICE_PTP_LNK_SPD_100G_RS) { 4379 err = ice_read_64b_phy_reg_e82x(hw, port, 4380 P_REG_PAR_RX_TIME_L, 4381 &val); 4382 if (err) 4383 return err; 4384 4385 total_offset += val; 4386 } 4387 4388 /* In addition, Rx must account for the PMD alignment */ 4389 err = ice_phy_calc_pmd_adj_e82x(hw, port, link_spd, fec_mode, &pmd); 4390 if (err) 4391 return err; 4392 4393 /* For RS-FEC, this adjustment adds delay, but for other modes, it 4394 * subtracts delay. 4395 */ 4396 if (fec_mode == ICE_PTP_FEC_MODE_RS_FEC) 4397 total_offset += pmd; 4398 else 4399 total_offset -= pmd; 4400 4401 /* Now that the total offset has been calculated, program it to the 4402 * PHY and indicate that the Rx offset is ready. After this, 4403 * timestamps will be enabled. 4404 */ 4405 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_TOTAL_RX_OFFSET_L, 4406 total_offset); 4407 if (err) 4408 return err; 4409 4410 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 1); 4411 if (err) 4412 return err; 4413 4414 dev_info(ice_hw_to_dev(hw), "Port=%d Rx vernier offset calibration complete\n", 4415 port); 4416 4417 return 0; 4418 } 4419 4420 /** 4421 * ice_ptp_clear_phy_offset_ready_e82x - Clear PHY TX_/RX_OFFSET_READY registers 4422 * @hw: pointer to the HW struct 4423 * 4424 * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted 4425 * and received timestamps as invalid. 4426 * 4427 * Return: 0 on success, other error codes when failed to write to PHY 4428 */ 4429 int ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw *hw) 4430 { 4431 u8 port; 4432 4433 for (port = 0; port < hw->ptp.num_lports; port++) { 4434 int err; 4435 4436 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0); 4437 if (err) { 4438 dev_warn(ice_hw_to_dev(hw), 4439 "Failed to clear PHY TX_OFFSET_READY register\n"); 4440 return err; 4441 } 4442 4443 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0); 4444 if (err) { 4445 dev_warn(ice_hw_to_dev(hw), 4446 "Failed to clear PHY RX_OFFSET_READY register\n"); 4447 return err; 4448 } 4449 } 4450 4451 return 0; 4452 } 4453 4454 /** 4455 * ice_read_phy_and_phc_time_e82x - Simultaneously capture PHC and PHY time 4456 * @hw: pointer to the HW struct 4457 * @port: the PHY port to read 4458 * @phy_time: on return, the 64bit PHY timer value 4459 * @phc_time: on return, the lower 64bits of PHC time 4460 * 4461 * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY 4462 * and PHC timer values. 4463 */ 4464 static int 4465 ice_read_phy_and_phc_time_e82x(struct ice_hw *hw, u8 port, u64 *phy_time, 4466 u64 *phc_time) 4467 { 4468 u64 tx_time, rx_time; 4469 u32 zo, lo; 4470 u8 tmr_idx; 4471 int err; 4472 4473 tmr_idx = ice_get_ptp_src_clock_index(hw); 4474 4475 /* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */ 4476 ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME); 4477 4478 /* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */ 4479 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME); 4480 if (err) 4481 return err; 4482 4483 /* Issue the sync to start the ICE_PTP_READ_TIME capture */ 4484 ice_ptp_exec_tmr_cmd(hw); 4485 4486 /* Read the captured PHC time from the shadow time registers */ 4487 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx)); 4488 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx)); 4489 *phc_time = (u64)lo << 32 | zo; 4490 4491 /* Read the captured PHY time from the PHY shadow registers */ 4492 err = ice_ptp_read_port_capture(hw, port, &tx_time, &rx_time); 4493 if (err) 4494 return err; 4495 4496 /* If the PHY Tx and Rx timers don't match, log a warning message. 4497 * Note that this should not happen in normal circumstances since the 4498 * driver always programs them together. 4499 */ 4500 if (tx_time != rx_time) 4501 dev_warn(ice_hw_to_dev(hw), 4502 "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n", 4503 port, (unsigned long long)tx_time, 4504 (unsigned long long)rx_time); 4505 4506 *phy_time = tx_time; 4507 4508 return 0; 4509 } 4510 4511 /** 4512 * ice_sync_phy_timer_e82x - Synchronize the PHY timer with PHC timer 4513 * @hw: pointer to the HW struct 4514 * @port: the PHY port to synchronize 4515 * 4516 * Perform an adjustment to ensure that the PHY and PHC timers are in sync. 4517 * This is done by issuing a ICE_PTP_READ_TIME command which triggers a 4518 * simultaneous read of the PHY timer and PHC timer. Then we use the 4519 * difference to calculate an appropriate 2s complement addition to add 4520 * to the PHY timer in order to ensure it reads the same value as the 4521 * primary PHC timer. 4522 */ 4523 static int ice_sync_phy_timer_e82x(struct ice_hw *hw, u8 port) 4524 { 4525 u64 phc_time, phy_time, difference; 4526 int err; 4527 4528 if (!ice_ptp_lock(hw)) { 4529 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n"); 4530 return -EBUSY; 4531 } 4532 4533 err = ice_read_phy_and_phc_time_e82x(hw, port, &phy_time, &phc_time); 4534 if (err) 4535 goto err_unlock; 4536 4537 /* Calculate the amount required to add to the port time in order for 4538 * it to match the PHC time. 4539 * 4540 * Note that the port adjustment is done using 2s complement 4541 * arithmetic. This is convenient since it means that we can simply 4542 * calculate the difference between the PHC time and the port time, 4543 * and it will be interpreted correctly. 4544 */ 4545 difference = phc_time - phy_time; 4546 4547 err = ice_ptp_prep_port_adj_e82x(hw, port, (s64)difference); 4548 if (err) 4549 goto err_unlock; 4550 4551 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME); 4552 if (err) 4553 goto err_unlock; 4554 4555 /* Do not perform any action on the main timer */ 4556 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 4557 4558 /* Issue the sync to activate the time adjustment */ 4559 ice_ptp_exec_tmr_cmd(hw); 4560 4561 /* Re-capture the timer values to flush the command registers and 4562 * verify that the time was properly adjusted. 4563 */ 4564 err = ice_read_phy_and_phc_time_e82x(hw, port, &phy_time, &phc_time); 4565 if (err) 4566 goto err_unlock; 4567 4568 dev_info(ice_hw_to_dev(hw), 4569 "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n", 4570 port, (unsigned long long)phy_time, 4571 (unsigned long long)phc_time); 4572 4573 ice_ptp_unlock(hw); 4574 4575 return 0; 4576 4577 err_unlock: 4578 ice_ptp_unlock(hw); 4579 return err; 4580 } 4581 4582 /** 4583 * ice_stop_phy_timer_e82x - Stop the PHY clock timer 4584 * @hw: pointer to the HW struct 4585 * @port: the PHY port to stop 4586 * @soft_reset: if true, hold the SOFT_RESET bit of P_REG_PS 4587 * 4588 * Stop the clock of a PHY port. This must be done as part of the flow to 4589 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 4590 * initialized or when link speed changes. 4591 */ 4592 int 4593 ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset) 4594 { 4595 int err; 4596 u32 val; 4597 4598 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0); 4599 if (err) 4600 return err; 4601 4602 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0); 4603 if (err) 4604 return err; 4605 4606 err = ice_read_phy_reg_e82x(hw, port, P_REG_PS, &val); 4607 if (err) 4608 return err; 4609 4610 val &= ~P_REG_PS_START_M; 4611 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4612 if (err) 4613 return err; 4614 4615 val &= ~P_REG_PS_ENA_CLK_M; 4616 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4617 if (err) 4618 return err; 4619 4620 if (soft_reset) { 4621 val |= P_REG_PS_SFT_RESET_M; 4622 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4623 if (err) 4624 return err; 4625 } 4626 4627 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port); 4628 4629 return 0; 4630 } 4631 4632 /** 4633 * ice_start_phy_timer_e82x - Start the PHY clock timer 4634 * @hw: pointer to the HW struct 4635 * @port: the PHY port to start 4636 * 4637 * Start the clock of a PHY port. This must be done as part of the flow to 4638 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 4639 * initialized or when link speed changes. 4640 * 4641 * Hardware will take Vernier measurements on Tx or Rx of packets. 4642 */ 4643 int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port) 4644 { 4645 u32 lo, hi, val; 4646 u64 incval; 4647 u8 tmr_idx; 4648 int err; 4649 4650 tmr_idx = ice_get_ptp_src_clock_index(hw); 4651 4652 err = ice_stop_phy_timer_e82x(hw, port, false); 4653 if (err) 4654 return err; 4655 4656 ice_phy_cfg_lane_e82x(hw, port); 4657 4658 err = ice_phy_cfg_uix_e82x(hw, port); 4659 if (err) 4660 return err; 4661 4662 err = ice_phy_cfg_parpcs_e82x(hw, port); 4663 if (err) 4664 return err; 4665 4666 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 4667 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 4668 incval = (u64)hi << 32 | lo; 4669 4670 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L, incval); 4671 if (err) 4672 return err; 4673 4674 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL); 4675 if (err) 4676 return err; 4677 4678 /* Do not perform any action on the main timer */ 4679 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 4680 4681 ice_ptp_exec_tmr_cmd(hw); 4682 4683 err = ice_read_phy_reg_e82x(hw, port, P_REG_PS, &val); 4684 if (err) 4685 return err; 4686 4687 val |= P_REG_PS_SFT_RESET_M; 4688 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4689 if (err) 4690 return err; 4691 4692 val |= P_REG_PS_START_M; 4693 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4694 if (err) 4695 return err; 4696 4697 val &= ~P_REG_PS_SFT_RESET_M; 4698 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4699 if (err) 4700 return err; 4701 4702 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL); 4703 if (err) 4704 return err; 4705 4706 ice_ptp_exec_tmr_cmd(hw); 4707 4708 val |= P_REG_PS_ENA_CLK_M; 4709 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4710 if (err) 4711 return err; 4712 4713 val |= P_REG_PS_LOAD_OFFSET_M; 4714 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4715 if (err) 4716 return err; 4717 4718 ice_ptp_exec_tmr_cmd(hw); 4719 4720 err = ice_sync_phy_timer_e82x(hw, port); 4721 if (err) 4722 return err; 4723 4724 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port); 4725 4726 return 0; 4727 } 4728 4729 /** 4730 * ice_get_phy_tx_tstamp_ready_e82x - Read Tx memory status register 4731 * @hw: pointer to the HW struct 4732 * @quad: the timestamp quad to read from 4733 * @tstamp_ready: contents of the Tx memory status register 4734 * 4735 * Read the Q_REG_TX_MEMORY_STATUS register indicating which timestamps in 4736 * the PHY are ready. A set bit means the corresponding timestamp is valid and 4737 * ready to be captured from the PHY timestamp block. 4738 */ 4739 static int 4740 ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw *hw, u8 quad, u64 *tstamp_ready) 4741 { 4742 u32 hi, lo; 4743 int err; 4744 4745 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_U, &hi); 4746 if (err) { 4747 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_U for quad %u, err %d\n", 4748 quad, err); 4749 return err; 4750 } 4751 4752 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_L, &lo); 4753 if (err) { 4754 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_L for quad %u, err %d\n", 4755 quad, err); 4756 return err; 4757 } 4758 4759 *tstamp_ready = (u64)hi << 32 | (u64)lo; 4760 4761 return 0; 4762 } 4763 4764 /** 4765 * ice_phy_cfg_intr_e82x - Configure TX timestamp interrupt 4766 * @hw: pointer to the HW struct 4767 * @quad: the timestamp quad 4768 * @ena: enable or disable interrupt 4769 * @threshold: interrupt threshold 4770 * 4771 * Configure TX timestamp interrupt for the specified quad 4772 * 4773 * Return: 0 on success, other error codes when failed to read/write quad 4774 */ 4775 4776 int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold) 4777 { 4778 int err; 4779 u32 val; 4780 4781 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val); 4782 if (err) 4783 return err; 4784 4785 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M; 4786 if (ena) { 4787 val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M; 4788 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M; 4789 val |= FIELD_PREP(Q_REG_TX_MEM_GBL_CFG_INTR_THR_M, threshold); 4790 } 4791 4792 return ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val); 4793 } 4794 4795 /** 4796 * ice_ptp_init_phy_e82x - initialize PHY parameters 4797 * @ptp: pointer to the PTP HW struct 4798 */ 4799 static void ice_ptp_init_phy_e82x(struct ice_ptp_hw *ptp) 4800 { 4801 ptp->num_lports = 8; 4802 ptp->ports_per_phy = 8; 4803 } 4804 4805 /* E810 functions 4806 * 4807 * The following functions operate on the E810 series devices which use 4808 * a separate external PHY. 4809 */ 4810 4811 /** 4812 * ice_read_phy_reg_e810 - Read register from external PHY on E810 4813 * @hw: pointer to the HW struct 4814 * @addr: the address to read from 4815 * @val: On return, the value read from the PHY 4816 * 4817 * Read a register from the external PHY on the E810 device. 4818 */ 4819 static int ice_read_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 *val) 4820 { 4821 struct ice_sbq_msg_input msg = {0}; 4822 int err; 4823 4824 msg.msg_addr_low = lower_16_bits(addr); 4825 msg.msg_addr_high = upper_16_bits(addr); 4826 msg.opcode = ice_sbq_msg_rd; 4827 msg.dest_dev = rmn_0; 4828 4829 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 4830 if (err) { 4831 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 4832 err); 4833 return err; 4834 } 4835 4836 *val = msg.data; 4837 4838 return 0; 4839 } 4840 4841 /** 4842 * ice_write_phy_reg_e810 - Write register on external PHY on E810 4843 * @hw: pointer to the HW struct 4844 * @addr: the address to writem to 4845 * @val: the value to write to the PHY 4846 * 4847 * Write a value to a register of the external PHY on the E810 device. 4848 */ 4849 static int ice_write_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 val) 4850 { 4851 struct ice_sbq_msg_input msg = {0}; 4852 int err; 4853 4854 msg.msg_addr_low = lower_16_bits(addr); 4855 msg.msg_addr_high = upper_16_bits(addr); 4856 msg.opcode = ice_sbq_msg_wr; 4857 msg.dest_dev = rmn_0; 4858 msg.data = val; 4859 4860 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 4861 if (err) { 4862 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 4863 err); 4864 return err; 4865 } 4866 4867 return 0; 4868 } 4869 4870 /** 4871 * ice_read_phy_tstamp_ll_e810 - Read a PHY timestamp registers through the FW 4872 * @hw: pointer to the HW struct 4873 * @idx: the timestamp index to read 4874 * @hi: 8 bit timestamp high value 4875 * @lo: 32 bit timestamp low value 4876 * 4877 * Read a 8bit timestamp high value and 32 bit timestamp low value out of the 4878 * timestamp block of the external PHY on the E810 device using the low latency 4879 * timestamp read. 4880 */ 4881 static int 4882 ice_read_phy_tstamp_ll_e810(struct ice_hw *hw, u8 idx, u8 *hi, u32 *lo) 4883 { 4884 struct ice_e810_params *params = &hw->ptp.phy.e810; 4885 unsigned long flags; 4886 u32 val; 4887 int err; 4888 4889 spin_lock_irqsave(¶ms->atqbal_wq.lock, flags); 4890 4891 /* Wait for any pending in-progress low latency interrupt */ 4892 err = wait_event_interruptible_locked_irq(params->atqbal_wq, 4893 !(params->atqbal_flags & 4894 ATQBAL_FLAGS_INTR_IN_PROGRESS)); 4895 if (err) { 4896 spin_unlock_irqrestore(¶ms->atqbal_wq.lock, flags); 4897 return err; 4898 } 4899 4900 /* Write TS index to read to the PF register so the FW can read it */ 4901 val = FIELD_PREP(REG_LL_PROXY_H_TS_IDX, idx) | REG_LL_PROXY_H_EXEC; 4902 wr32(hw, REG_LL_PROXY_H, val); 4903 4904 /* Read the register repeatedly until the FW provides us the TS */ 4905 err = read_poll_timeout_atomic(rd32, val, 4906 !FIELD_GET(REG_LL_PROXY_H_EXEC, val), 10, 4907 REG_LL_PROXY_H_TIMEOUT_US, false, hw, 4908 REG_LL_PROXY_H); 4909 if (err) { 4910 ice_debug(hw, ICE_DBG_PTP, "Failed to read PTP timestamp using low latency read\n"); 4911 spin_unlock_irqrestore(¶ms->atqbal_wq.lock, flags); 4912 return err; 4913 } 4914 4915 /* High 8 bit value of the TS is on the bits 16:23 */ 4916 *hi = FIELD_GET(REG_LL_PROXY_H_TS_HIGH, val); 4917 4918 /* Read the low 32 bit value and set the TS valid bit */ 4919 *lo = rd32(hw, REG_LL_PROXY_L) | TS_VALID; 4920 4921 spin_unlock_irqrestore(¶ms->atqbal_wq.lock, flags); 4922 4923 return 0; 4924 } 4925 4926 /** 4927 * ice_read_phy_tstamp_sbq_e810 - Read a PHY timestamp registers through the sbq 4928 * @hw: pointer to the HW struct 4929 * @lport: the lport to read from 4930 * @idx: the timestamp index to read 4931 * @hi: 8 bit timestamp high value 4932 * @lo: 32 bit timestamp low value 4933 * 4934 * Read a 8bit timestamp high value and 32 bit timestamp low value out of the 4935 * timestamp block of the external PHY on the E810 device using sideband queue. 4936 */ 4937 static int 4938 ice_read_phy_tstamp_sbq_e810(struct ice_hw *hw, u8 lport, u8 idx, u8 *hi, 4939 u32 *lo) 4940 { 4941 u32 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); 4942 u32 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); 4943 u32 lo_val, hi_val; 4944 int err; 4945 4946 err = ice_read_phy_reg_e810(hw, lo_addr, &lo_val); 4947 if (err) { 4948 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 4949 err); 4950 return err; 4951 } 4952 4953 err = ice_read_phy_reg_e810(hw, hi_addr, &hi_val); 4954 if (err) { 4955 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 4956 err); 4957 return err; 4958 } 4959 4960 *lo = lo_val; 4961 *hi = (u8)hi_val; 4962 4963 return 0; 4964 } 4965 4966 /** 4967 * ice_read_phy_tstamp_e810 - Read a PHY timestamp out of the external PHY 4968 * @hw: pointer to the HW struct 4969 * @lport: the lport to read from 4970 * @idx: the timestamp index to read 4971 * @tstamp: on return, the 40bit timestamp value 4972 * 4973 * Read a 40bit timestamp value out of the timestamp block of the external PHY 4974 * on the E810 device. 4975 */ 4976 static int 4977 ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) 4978 { 4979 u32 lo = 0; 4980 u8 hi = 0; 4981 int err; 4982 4983 if (hw->dev_caps.ts_dev_info.ts_ll_read) 4984 err = ice_read_phy_tstamp_ll_e810(hw, idx, &hi, &lo); 4985 else 4986 err = ice_read_phy_tstamp_sbq_e810(hw, lport, idx, &hi, &lo); 4987 4988 if (err) 4989 return err; 4990 4991 /* For E810 devices, the timestamp is reported with the lower 32 bits 4992 * in the low register, and the upper 8 bits in the high register. 4993 */ 4994 *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) | 4995 FIELD_PREP(PHY_EXT_40B_LOW_M, lo); 4996 4997 return 0; 4998 } 4999 5000 /** 5001 * ice_clear_phy_tstamp_e810 - Clear a timestamp from the external PHY 5002 * @hw: pointer to the HW struct 5003 * @lport: the lport to read from 5004 * @idx: the timestamp index to reset 5005 * 5006 * Read the timestamp and then forcibly overwrite its value to clear the valid 5007 * bit from the timestamp block of the external PHY on the E810 device. 5008 * 5009 * This function should only be called on an idx whose bit is set according to 5010 * ice_get_phy_tx_tstamp_ready(). 5011 */ 5012 static int ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx) 5013 { 5014 u32 lo_addr, hi_addr; 5015 u64 unused_tstamp; 5016 int err; 5017 5018 err = ice_read_phy_tstamp_e810(hw, lport, idx, &unused_tstamp); 5019 if (err) { 5020 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for lport %u, idx %u, err %d\n", 5021 lport, idx, err); 5022 return err; 5023 } 5024 5025 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); 5026 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); 5027 5028 err = ice_write_phy_reg_e810(hw, lo_addr, 0); 5029 if (err) { 5030 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for lport %u, idx %u, err %d\n", 5031 lport, idx, err); 5032 return err; 5033 } 5034 5035 err = ice_write_phy_reg_e810(hw, hi_addr, 0); 5036 if (err) { 5037 ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register for lport %u, idx %u, err %d\n", 5038 lport, idx, err); 5039 return err; 5040 } 5041 5042 return 0; 5043 } 5044 5045 /** 5046 * ice_ptp_init_phc_e810 - Perform E810 specific PHC initialization 5047 * @hw: pointer to HW struct 5048 * 5049 * Perform E810-specific PTP hardware clock initialization steps. 5050 * 5051 * Return: 0 on success, other error codes when failed to initialize TimeSync 5052 */ 5053 static int ice_ptp_init_phc_e810(struct ice_hw *hw) 5054 { 5055 u8 tmr_idx; 5056 int err; 5057 5058 ice_ptp_cfg_sync_delay(hw, ICE_E810_E830_SYNC_DELAY); 5059 5060 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5061 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_ENA(tmr_idx), 5062 GLTSYN_ENA_TSYN_ENA_M); 5063 if (err) 5064 ice_debug(hw, ICE_DBG_PTP, "PTP failed in ena_phy_time_syn %d\n", 5065 err); 5066 5067 return err; 5068 } 5069 5070 /** 5071 * ice_ptp_prep_phy_time_e810 - Prepare PHY port with initial time 5072 * @hw: Board private structure 5073 * @time: Time to initialize the PHY port clock to 5074 * 5075 * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the 5076 * initial clock time. The time will not actually be programmed until the 5077 * driver issues an ICE_PTP_INIT_TIME command. 5078 * 5079 * The time value is the upper 32 bits of the PHY timer, usually in units of 5080 * nominal nanoseconds. 5081 */ 5082 static int ice_ptp_prep_phy_time_e810(struct ice_hw *hw, u32 time) 5083 { 5084 u8 tmr_idx; 5085 int err; 5086 5087 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5088 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_0(tmr_idx), 0); 5089 if (err) { 5090 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_0, err %d\n", 5091 err); 5092 return err; 5093 } 5094 5095 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_L(tmr_idx), time); 5096 if (err) { 5097 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_L, err %d\n", 5098 err); 5099 return err; 5100 } 5101 5102 return 0; 5103 } 5104 5105 /** 5106 * ice_ptp_prep_phy_adj_ll_e810 - Prep PHY ports for a time adjustment 5107 * @hw: pointer to HW struct 5108 * @adj: adjustment value to program 5109 * 5110 * Use the low latency firmware interface to program PHY time adjustment to 5111 * all PHY ports. 5112 * 5113 * Return: 0 on success, -EBUSY on timeout 5114 */ 5115 static int ice_ptp_prep_phy_adj_ll_e810(struct ice_hw *hw, s32 adj) 5116 { 5117 const u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5118 struct ice_e810_params *params = &hw->ptp.phy.e810; 5119 u32 val; 5120 int err; 5121 5122 spin_lock_irq(¶ms->atqbal_wq.lock); 5123 5124 /* Wait for any pending in-progress low latency interrupt */ 5125 err = wait_event_interruptible_locked_irq(params->atqbal_wq, 5126 !(params->atqbal_flags & 5127 ATQBAL_FLAGS_INTR_IN_PROGRESS)); 5128 if (err) { 5129 spin_unlock_irq(¶ms->atqbal_wq.lock); 5130 return err; 5131 } 5132 5133 wr32(hw, REG_LL_PROXY_L, adj); 5134 val = FIELD_PREP(REG_LL_PROXY_H_PHY_TMR_CMD_M, REG_LL_PROXY_H_PHY_TMR_CMD_ADJ) | 5135 FIELD_PREP(REG_LL_PROXY_H_PHY_TMR_IDX_M, tmr_idx) | REG_LL_PROXY_H_EXEC; 5136 wr32(hw, REG_LL_PROXY_H, val); 5137 5138 /* Read the register repeatedly until the FW indicates completion */ 5139 err = read_poll_timeout_atomic(rd32, val, 5140 !FIELD_GET(REG_LL_PROXY_H_EXEC, val), 5141 10, REG_LL_PROXY_H_TIMEOUT_US, false, hw, 5142 REG_LL_PROXY_H); 5143 if (err) { 5144 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY timer adjustment using low latency interface\n"); 5145 spin_unlock_irq(¶ms->atqbal_wq.lock); 5146 return err; 5147 } 5148 5149 spin_unlock_irq(¶ms->atqbal_wq.lock); 5150 5151 return 0; 5152 } 5153 5154 /** 5155 * ice_ptp_prep_phy_adj_e810 - Prep PHY port for a time adjustment 5156 * @hw: pointer to HW struct 5157 * @adj: adjustment value to program 5158 * 5159 * Prepare the PHY port for an atomic adjustment by programming the PHY 5160 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual adjustment 5161 * is completed by issuing an ICE_PTP_ADJ_TIME sync command. 5162 * 5163 * The adjustment value only contains the portion used for the upper 32bits of 5164 * the PHY timer, usually in units of nominal nanoseconds. Negative 5165 * adjustments are supported using 2s complement arithmetic. 5166 */ 5167 static int ice_ptp_prep_phy_adj_e810(struct ice_hw *hw, s32 adj) 5168 { 5169 u8 tmr_idx; 5170 int err; 5171 5172 if (hw->dev_caps.ts_dev_info.ll_phy_tmr_update) 5173 return ice_ptp_prep_phy_adj_ll_e810(hw, adj); 5174 5175 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5176 5177 /* Adjustments are represented as signed 2's complement values in 5178 * nanoseconds. Sub-nanosecond adjustment is not supported. 5179 */ 5180 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), 0); 5181 if (err) { 5182 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_L, err %d\n", 5183 err); 5184 return err; 5185 } 5186 5187 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), adj); 5188 if (err) { 5189 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_H, err %d\n", 5190 err); 5191 return err; 5192 } 5193 5194 return 0; 5195 } 5196 5197 /** 5198 * ice_ptp_prep_phy_incval_ll_e810 - Prep PHY ports increment value change 5199 * @hw: pointer to HW struct 5200 * @incval: The new 40bit increment value to prepare 5201 * 5202 * Use the low latency firmware interface to program PHY time increment value 5203 * for all PHY ports. 5204 * 5205 * Return: 0 on success, -EBUSY on timeout 5206 */ 5207 static int ice_ptp_prep_phy_incval_ll_e810(struct ice_hw *hw, u64 incval) 5208 { 5209 const u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5210 struct ice_e810_params *params = &hw->ptp.phy.e810; 5211 u32 val; 5212 int err; 5213 5214 spin_lock_irq(¶ms->atqbal_wq.lock); 5215 5216 /* Wait for any pending in-progress low latency interrupt */ 5217 err = wait_event_interruptible_locked_irq(params->atqbal_wq, 5218 !(params->atqbal_flags & 5219 ATQBAL_FLAGS_INTR_IN_PROGRESS)); 5220 if (err) { 5221 spin_unlock_irq(¶ms->atqbal_wq.lock); 5222 return err; 5223 } 5224 5225 wr32(hw, REG_LL_PROXY_L, lower_32_bits(incval)); 5226 val = FIELD_PREP(REG_LL_PROXY_H_PHY_TMR_CMD_M, REG_LL_PROXY_H_PHY_TMR_CMD_FREQ) | 5227 FIELD_PREP(REG_LL_PROXY_H_TS_HIGH, (u8)upper_32_bits(incval)) | 5228 FIELD_PREP(REG_LL_PROXY_H_PHY_TMR_IDX_M, tmr_idx) | REG_LL_PROXY_H_EXEC; 5229 wr32(hw, REG_LL_PROXY_H, val); 5230 5231 /* Read the register repeatedly until the FW indicates completion */ 5232 err = read_poll_timeout_atomic(rd32, val, 5233 !FIELD_GET(REG_LL_PROXY_H_EXEC, val), 5234 10, REG_LL_PROXY_H_TIMEOUT_US, false, hw, 5235 REG_LL_PROXY_H); 5236 if (err) { 5237 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY timer increment using low latency interface\n"); 5238 spin_unlock_irq(¶ms->atqbal_wq.lock); 5239 return err; 5240 } 5241 5242 spin_unlock_irq(¶ms->atqbal_wq.lock); 5243 5244 return 0; 5245 } 5246 5247 /** 5248 * ice_ptp_prep_phy_incval_e810 - Prep PHY port increment value change 5249 * @hw: pointer to HW struct 5250 * @incval: The new 40bit increment value to prepare 5251 * 5252 * Prepare the PHY port for a new increment value by programming the PHY 5253 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual change is 5254 * completed by issuing an ICE_PTP_INIT_INCVAL command. 5255 */ 5256 static int ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval) 5257 { 5258 u32 high, low; 5259 u8 tmr_idx; 5260 int err; 5261 5262 if (hw->dev_caps.ts_dev_info.ll_phy_tmr_update) 5263 return ice_ptp_prep_phy_incval_ll_e810(hw, incval); 5264 5265 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5266 low = lower_32_bits(incval); 5267 high = upper_32_bits(incval); 5268 5269 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), low); 5270 if (err) { 5271 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval to PHY SHADJ_L, err %d\n", 5272 err); 5273 return err; 5274 } 5275 5276 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), high); 5277 if (err) { 5278 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval PHY SHADJ_H, err %d\n", 5279 err); 5280 return err; 5281 } 5282 5283 return 0; 5284 } 5285 5286 /** 5287 * ice_ptp_port_cmd_e810 - Prepare all external PHYs for a timer command 5288 * @hw: pointer to HW struct 5289 * @cmd: Command to be sent to the port 5290 * 5291 * Prepare the external PHYs connected to this device for a timer sync 5292 * command. 5293 */ 5294 static int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 5295 { 5296 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 5297 5298 return ice_write_phy_reg_e810(hw, E810_ETH_GLTSYN_CMD, val); 5299 } 5300 5301 /** 5302 * ice_get_phy_tx_tstamp_ready_e810 - Read Tx memory status register 5303 * @hw: pointer to the HW struct 5304 * @port: the PHY port to read 5305 * @tstamp_ready: contents of the Tx memory status register 5306 * 5307 * E810 devices do not use a Tx memory status register. Instead simply 5308 * indicate that all timestamps are currently ready. 5309 */ 5310 static int 5311 ice_get_phy_tx_tstamp_ready_e810(struct ice_hw *hw, u8 port, u64 *tstamp_ready) 5312 { 5313 *tstamp_ready = 0xFFFFFFFFFFFFFFFF; 5314 return 0; 5315 } 5316 5317 /* E810 SMA functions 5318 * 5319 * The following functions operate specifically on E810 hardware and are used 5320 * to access the extended GPIOs available. 5321 */ 5322 5323 /** 5324 * ice_read_sma_ctrl 5325 * @hw: pointer to the hw struct 5326 * @data: pointer to data to be read from the GPIO controller 5327 * 5328 * Read the SMA controller state. It is connected to pins 3-7 of Port 1 of the 5329 * PCA9575 expander, so only bits 3-7 in data are valid. 5330 */ 5331 int ice_read_sma_ctrl(struct ice_hw *hw, u8 *data) 5332 { 5333 int status; 5334 u16 handle; 5335 u8 i; 5336 5337 status = ice_get_pca9575_handle(hw, &handle); 5338 if (status) 5339 return status; 5340 5341 *data = 0; 5342 5343 for (i = ICE_SMA_MIN_BIT; i <= ICE_SMA_MAX_BIT; i++) { 5344 bool pin; 5345 5346 status = ice_aq_get_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET, 5347 &pin, NULL); 5348 if (status) 5349 break; 5350 *data |= (u8)(!pin) << i; 5351 } 5352 5353 return status; 5354 } 5355 5356 /** 5357 * ice_write_sma_ctrl 5358 * @hw: pointer to the hw struct 5359 * @data: data to be written to the GPIO controller 5360 * 5361 * Write the data to the SMA controller. It is connected to pins 3-7 of Port 1 5362 * of the PCA9575 expander, so only bits 3-7 in data are valid. 5363 */ 5364 int ice_write_sma_ctrl(struct ice_hw *hw, u8 data) 5365 { 5366 int status; 5367 u16 handle; 5368 u8 i; 5369 5370 status = ice_get_pca9575_handle(hw, &handle); 5371 if (status) 5372 return status; 5373 5374 for (i = ICE_SMA_MIN_BIT; i <= ICE_SMA_MAX_BIT; i++) { 5375 bool pin; 5376 5377 pin = !(data & (1 << i)); 5378 status = ice_aq_set_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET, 5379 pin, NULL); 5380 if (status) 5381 break; 5382 } 5383 5384 return status; 5385 } 5386 5387 /** 5388 * ice_ptp_read_sdp_ac - read SDP available connections section from NVM 5389 * @hw: pointer to the HW struct 5390 * @entries: returns the SDP available connections section from NVM 5391 * @num_entries: returns the number of valid entries 5392 * 5393 * Return: 0 on success, negative error code if NVM read failed or section does 5394 * not exist or is corrupted 5395 */ 5396 int ice_ptp_read_sdp_ac(struct ice_hw *hw, __le16 *entries, uint *num_entries) 5397 { 5398 __le16 data; 5399 u32 offset; 5400 int err; 5401 5402 err = ice_acquire_nvm(hw, ICE_RES_READ); 5403 if (err) 5404 goto exit; 5405 5406 /* Read the offset of SDP_AC */ 5407 offset = ICE_AQC_NVM_SDP_AC_PTR_OFFSET; 5408 err = ice_aq_read_nvm(hw, 0, offset, sizeof(data), &data, false, true, 5409 NULL); 5410 if (err) 5411 goto exit; 5412 5413 /* Check if section exist */ 5414 offset = FIELD_GET(ICE_AQC_NVM_SDP_AC_PTR_M, le16_to_cpu(data)); 5415 if (offset == ICE_AQC_NVM_SDP_AC_PTR_INVAL) { 5416 err = -EINVAL; 5417 goto exit; 5418 } 5419 5420 if (offset & ICE_AQC_NVM_SDP_AC_PTR_TYPE_M) { 5421 offset &= ICE_AQC_NVM_SDP_AC_PTR_M; 5422 offset *= ICE_AQC_NVM_SECTOR_UNIT; 5423 } else { 5424 offset *= sizeof(data); 5425 } 5426 5427 /* Skip reading section length and read the number of valid entries */ 5428 offset += sizeof(data); 5429 err = ice_aq_read_nvm(hw, 0, offset, sizeof(data), &data, false, true, 5430 NULL); 5431 if (err) 5432 goto exit; 5433 *num_entries = le16_to_cpu(data); 5434 5435 /* Read SDP configuration section */ 5436 offset += sizeof(data); 5437 err = ice_aq_read_nvm(hw, 0, offset, *num_entries * sizeof(data), 5438 entries, false, true, NULL); 5439 5440 exit: 5441 if (err) 5442 dev_dbg(ice_hw_to_dev(hw), "Failed to configure SDP connection section\n"); 5443 ice_release_nvm(hw); 5444 return err; 5445 } 5446 5447 /** 5448 * ice_ptp_init_phy_e810 - initialize PHY parameters 5449 * @ptp: pointer to the PTP HW struct 5450 */ 5451 static void ice_ptp_init_phy_e810(struct ice_ptp_hw *ptp) 5452 { 5453 ptp->num_lports = 8; 5454 ptp->ports_per_phy = 4; 5455 5456 init_waitqueue_head(&ptp->phy.e810.atqbal_wq); 5457 } 5458 5459 /* E830 functions 5460 * 5461 * The following functions operate on the E830 series devices. 5462 * 5463 */ 5464 5465 /** 5466 * ice_ptp_init_phc_e830 - Perform E830 specific PHC initialization 5467 * @hw: pointer to HW struct 5468 * 5469 * Perform E830-specific PTP hardware clock initialization steps. 5470 */ 5471 static void ice_ptp_init_phc_e830(const struct ice_hw *hw) 5472 { 5473 ice_ptp_cfg_sync_delay(hw, ICE_E810_E830_SYNC_DELAY); 5474 } 5475 5476 /** 5477 * ice_ptp_write_direct_incval_e830 - Prep PHY port increment value change 5478 * @hw: pointer to HW struct 5479 * @incval: The new 40bit increment value to prepare 5480 * 5481 * Prepare the PHY port for a new increment value by programming the PHC 5482 * GLTSYN_INCVAL_L and GLTSYN_INCVAL_H registers. The actual change is 5483 * completed by FW automatically. 5484 */ 5485 static void ice_ptp_write_direct_incval_e830(const struct ice_hw *hw, 5486 u64 incval) 5487 { 5488 u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5489 5490 wr32(hw, GLTSYN_INCVAL_L(tmr_idx), lower_32_bits(incval)); 5491 wr32(hw, GLTSYN_INCVAL_H(tmr_idx), upper_32_bits(incval)); 5492 } 5493 5494 /** 5495 * ice_ptp_write_direct_phc_time_e830 - Prepare PHY port with initial time 5496 * @hw: Board private structure 5497 * @time: Time to initialize the PHY port clock to 5498 * 5499 * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the 5500 * initial clock time. The time will not actually be programmed until the 5501 * driver issues an ICE_PTP_INIT_TIME command. 5502 * 5503 * The time value is the upper 32 bits of the PHY timer, usually in units of 5504 * nominal nanoseconds. 5505 */ 5506 static void ice_ptp_write_direct_phc_time_e830(const struct ice_hw *hw, 5507 u64 time) 5508 { 5509 u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5510 5511 wr32(hw, GLTSYN_TIME_0(tmr_idx), 0); 5512 wr32(hw, GLTSYN_TIME_L(tmr_idx), lower_32_bits(time)); 5513 wr32(hw, GLTSYN_TIME_H(tmr_idx), upper_32_bits(time)); 5514 } 5515 5516 /** 5517 * ice_ptp_port_cmd_e830 - Prepare all external PHYs for a timer command 5518 * @hw: pointer to HW struct 5519 * @cmd: Command to be sent to the port 5520 * 5521 * Prepare the external PHYs connected to this device for a timer sync 5522 * command. 5523 * 5524 * Return: 0 on success, negative error code when PHY write failed 5525 */ 5526 static int ice_ptp_port_cmd_e830(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 5527 { 5528 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 5529 5530 return ice_write_phy_reg_e810(hw, E830_ETH_GLTSYN_CMD, val); 5531 } 5532 5533 /** 5534 * ice_read_phy_tstamp_e830 - Read a PHY timestamp out of the external PHY 5535 * @hw: pointer to the HW struct 5536 * @idx: the timestamp index to read 5537 * @tstamp: on return, the 40bit timestamp value 5538 * 5539 * Read a 40bit timestamp value out of the timestamp block of the external PHY 5540 * on the E830 device. 5541 */ 5542 static void ice_read_phy_tstamp_e830(const struct ice_hw *hw, u8 idx, 5543 u64 *tstamp) 5544 { 5545 u32 hi, lo; 5546 5547 hi = rd32(hw, E830_PRTTSYN_TXTIME_H(idx)); 5548 lo = rd32(hw, E830_PRTTSYN_TXTIME_L(idx)); 5549 5550 /* For E830 devices, the timestamp is reported with the lower 32 bits 5551 * in the low register, and the upper 8 bits in the high register. 5552 */ 5553 *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) | 5554 FIELD_PREP(PHY_EXT_40B_LOW_M, lo); 5555 } 5556 5557 /** 5558 * ice_get_phy_tx_tstamp_ready_e830 - Read Tx memory status register 5559 * @hw: pointer to the HW struct 5560 * @port: the PHY port to read 5561 * @tstamp_ready: contents of the Tx memory status register 5562 */ 5563 static void ice_get_phy_tx_tstamp_ready_e830(const struct ice_hw *hw, u8 port, 5564 u64 *tstamp_ready) 5565 { 5566 *tstamp_ready = rd32(hw, E830_PRTMAC_TS_TX_MEM_VALID_H); 5567 *tstamp_ready <<= 32; 5568 *tstamp_ready |= rd32(hw, E830_PRTMAC_TS_TX_MEM_VALID_L); 5569 } 5570 5571 /** 5572 * ice_ptp_init_phy_e830 - initialize PHY parameters 5573 * @ptp: pointer to the PTP HW struct 5574 */ 5575 static void ice_ptp_init_phy_e830(struct ice_ptp_hw *ptp) 5576 { 5577 ptp->num_lports = 8; 5578 ptp->ports_per_phy = 4; 5579 } 5580 5581 /* Device agnostic functions 5582 * 5583 * The following functions implement shared behavior common to all devices, 5584 * possibly calling a device specific implementation where necessary. 5585 */ 5586 5587 /** 5588 * ice_ptp_lock - Acquire PTP global semaphore register lock 5589 * @hw: pointer to the HW struct 5590 * 5591 * Acquire the global PTP hardware semaphore lock. Returns true if the lock 5592 * was acquired, false otherwise. 5593 * 5594 * The PFTSYN_SEM register sets the busy bit on read, returning the previous 5595 * value. If software sees the busy bit cleared, this means that this function 5596 * acquired the lock (and the busy bit is now set). If software sees the busy 5597 * bit set, it means that another function acquired the lock. 5598 * 5599 * Software must clear the busy bit with a write to release the lock for other 5600 * functions when done. 5601 */ 5602 bool ice_ptp_lock(struct ice_hw *hw) 5603 { 5604 u32 hw_lock; 5605 int i; 5606 5607 #define MAX_TRIES 15 5608 5609 for (i = 0; i < MAX_TRIES; i++) { 5610 hw_lock = rd32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id)); 5611 hw_lock = hw_lock & PFTSYN_SEM_BUSY_M; 5612 if (hw_lock) { 5613 /* Somebody is holding the lock */ 5614 usleep_range(5000, 6000); 5615 continue; 5616 } 5617 5618 break; 5619 } 5620 5621 return !hw_lock; 5622 } 5623 5624 /** 5625 * ice_ptp_unlock - Release PTP global semaphore register lock 5626 * @hw: pointer to the HW struct 5627 * 5628 * Release the global PTP hardware semaphore lock. This is done by writing to 5629 * the PFTSYN_SEM register. 5630 */ 5631 void ice_ptp_unlock(struct ice_hw *hw) 5632 { 5633 wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0); 5634 } 5635 5636 /** 5637 * ice_ptp_init_hw - Initialize hw based on device type 5638 * @hw: pointer to the HW structure 5639 * 5640 * Determine the PHY model for the device, and initialize hw 5641 * for use by other functions. 5642 */ 5643 void ice_ptp_init_hw(struct ice_hw *hw) 5644 { 5645 struct ice_ptp_hw *ptp = &hw->ptp; 5646 5647 switch (hw->mac_type) { 5648 case ICE_MAC_E810: 5649 ice_ptp_init_phy_e810(ptp); 5650 break; 5651 case ICE_MAC_E830: 5652 ice_ptp_init_phy_e830(ptp); 5653 break; 5654 case ICE_MAC_GENERIC: 5655 ice_ptp_init_phy_e82x(ptp); 5656 break; 5657 case ICE_MAC_GENERIC_3K_E825: 5658 ice_ptp_init_phy_e825(hw); 5659 break; 5660 default: 5661 return; 5662 } 5663 } 5664 5665 /** 5666 * ice_ptp_write_port_cmd - Prepare a single PHY port for a timer command 5667 * @hw: pointer to HW struct 5668 * @port: Port to which cmd has to be sent 5669 * @cmd: Command to be sent to the port 5670 * 5671 * Prepare one port for the upcoming timer sync command. Do not use this for 5672 * programming only a single port, instead use ice_ptp_one_port_cmd() to 5673 * ensure non-modified ports get properly initialized to ICE_PTP_NOP. 5674 * 5675 * Return: 5676 * * %0 - success 5677 * %-EBUSY - PHY type not supported 5678 * * %other - failed to write port command 5679 */ 5680 static int ice_ptp_write_port_cmd(struct ice_hw *hw, u8 port, 5681 enum ice_ptp_tmr_cmd cmd) 5682 { 5683 switch (hw->mac_type) { 5684 case ICE_MAC_GENERIC: 5685 return ice_ptp_write_port_cmd_e82x(hw, port, cmd); 5686 case ICE_MAC_GENERIC_3K_E825: 5687 return ice_ptp_write_port_cmd_eth56g(hw, port, cmd); 5688 default: 5689 return -EOPNOTSUPP; 5690 } 5691 } 5692 5693 /** 5694 * ice_ptp_one_port_cmd - Program one PHY port for a timer command 5695 * @hw: pointer to HW struct 5696 * @configured_port: the port that should execute the command 5697 * @configured_cmd: the command to be executed on the configured port 5698 * 5699 * Prepare one port for executing a timer command, while preparing all other 5700 * ports to ICE_PTP_NOP. This allows executing a command on a single port 5701 * while ensuring all other ports do not execute stale commands. 5702 * 5703 * Return: 5704 * * %0 - success 5705 * * %other - failed to write port command 5706 */ 5707 int ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port, 5708 enum ice_ptp_tmr_cmd configured_cmd) 5709 { 5710 u32 port; 5711 5712 for (port = 0; port < hw->ptp.num_lports; port++) { 5713 int err; 5714 5715 /* Program the configured port with the configured command, 5716 * program all other ports with ICE_PTP_NOP. 5717 */ 5718 if (port == configured_port) 5719 err = ice_ptp_write_port_cmd(hw, port, configured_cmd); 5720 else 5721 err = ice_ptp_write_port_cmd(hw, port, ICE_PTP_NOP); 5722 5723 if (err) 5724 return err; 5725 } 5726 5727 return 0; 5728 } 5729 5730 /** 5731 * ice_ptp_port_cmd - Prepare PHY ports for a timer sync command 5732 * @hw: pointer to HW struct 5733 * @cmd: the timer command to setup 5734 * 5735 * Prepare all PHY ports on this device for the requested timer command. For 5736 * some families this can be done in one shot, but for other families each 5737 * port must be configured individually. 5738 * 5739 * Return: 5740 * * %0 - success 5741 * * %other - failed to write port command 5742 */ 5743 static int ice_ptp_port_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 5744 { 5745 u32 port; 5746 5747 /* PHY models which can program all ports simultaneously */ 5748 switch (hw->mac_type) { 5749 case ICE_MAC_E810: 5750 return ice_ptp_port_cmd_e810(hw, cmd); 5751 case ICE_MAC_E830: 5752 return ice_ptp_port_cmd_e830(hw, cmd); 5753 default: 5754 break; 5755 } 5756 5757 /* PHY models which require programming each port separately */ 5758 for (port = 0; port < hw->ptp.num_lports; port++) { 5759 int err; 5760 5761 err = ice_ptp_write_port_cmd(hw, port, cmd); 5762 if (err) 5763 return err; 5764 } 5765 5766 return 0; 5767 } 5768 5769 /** 5770 * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command 5771 * @hw: pointer to HW struct 5772 * @cmd: the command to issue 5773 * 5774 * Prepare the source timer and PHY timers and then trigger the requested 5775 * command. This causes the shadow registers previously written in preparation 5776 * for the command to be synchronously applied to both the source and PHY 5777 * timers. 5778 */ 5779 static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 5780 { 5781 int err; 5782 5783 /* First, prepare the source timer */ 5784 ice_ptp_src_cmd(hw, cmd); 5785 5786 /* Next, prepare the ports */ 5787 err = ice_ptp_port_cmd(hw, cmd); 5788 if (err) { 5789 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for timer command %u, err %d\n", 5790 cmd, err); 5791 return err; 5792 } 5793 5794 /* Write the sync command register to drive both source and PHY timer 5795 * commands synchronously 5796 */ 5797 ice_ptp_exec_tmr_cmd(hw); 5798 5799 return 0; 5800 } 5801 5802 /** 5803 * ice_ptp_init_time - Initialize device time to provided value 5804 * @hw: pointer to HW struct 5805 * @time: 64bits of time (GLTSYN_TIME_L and GLTSYN_TIME_H) 5806 * 5807 * Initialize the device to the specified time provided. This requires a three 5808 * step process: 5809 * 5810 * 1) write the new init time to the source timer shadow registers 5811 * 2) write the new init time to the PHY timer shadow registers 5812 * 3) issue an init_time timer command to synchronously switch both the source 5813 * and port timers to the new init time value at the next clock cycle. 5814 */ 5815 int ice_ptp_init_time(struct ice_hw *hw, u64 time) 5816 { 5817 u8 tmr_idx; 5818 int err; 5819 5820 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5821 5822 /* Source timers */ 5823 /* For E830 we don't need to use shadow registers, its automatic */ 5824 if (hw->mac_type == ICE_MAC_E830) { 5825 ice_ptp_write_direct_phc_time_e830(hw, time); 5826 return 0; 5827 } 5828 5829 wr32(hw, GLTSYN_SHTIME_L(tmr_idx), lower_32_bits(time)); 5830 wr32(hw, GLTSYN_SHTIME_H(tmr_idx), upper_32_bits(time)); 5831 wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0); 5832 5833 /* PHY timers */ 5834 /* Fill Rx and Tx ports and send msg to PHY */ 5835 switch (hw->mac_type) { 5836 case ICE_MAC_E810: 5837 err = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF); 5838 break; 5839 case ICE_MAC_GENERIC: 5840 err = ice_ptp_prep_phy_time_e82x(hw, time & 0xFFFFFFFF); 5841 break; 5842 case ICE_MAC_GENERIC_3K_E825: 5843 err = ice_ptp_prep_phy_time_eth56g(hw, 5844 (u32)(time & 0xFFFFFFFF)); 5845 break; 5846 default: 5847 err = -EOPNOTSUPP; 5848 } 5849 5850 if (err) 5851 return err; 5852 5853 return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_TIME); 5854 } 5855 5856 /** 5857 * ice_ptp_write_incval - Program PHC with new increment value 5858 * @hw: pointer to HW struct 5859 * @incval: Source timer increment value per clock cycle 5860 * 5861 * Program the PHC with a new increment value. This requires a three-step 5862 * process: 5863 * 5864 * 1) Write the increment value to the source timer shadow registers 5865 * 2) Write the increment value to the PHY timer shadow registers 5866 * 3) Issue an ICE_PTP_INIT_INCVAL timer command to synchronously switch both 5867 * the source and port timers to the new increment value at the next clock 5868 * cycle. 5869 */ 5870 int ice_ptp_write_incval(struct ice_hw *hw, u64 incval) 5871 { 5872 u8 tmr_idx; 5873 int err; 5874 5875 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5876 5877 /* For E830 we don't need to use shadow registers, its automatic */ 5878 if (hw->mac_type == ICE_MAC_E830) { 5879 ice_ptp_write_direct_incval_e830(hw, incval); 5880 return 0; 5881 } 5882 5883 /* Shadow Adjust */ 5884 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), lower_32_bits(incval)); 5885 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), upper_32_bits(incval)); 5886 5887 switch (hw->mac_type) { 5888 case ICE_MAC_E810: 5889 err = ice_ptp_prep_phy_incval_e810(hw, incval); 5890 break; 5891 case ICE_MAC_GENERIC: 5892 err = ice_ptp_prep_phy_incval_e82x(hw, incval); 5893 break; 5894 case ICE_MAC_GENERIC_3K_E825: 5895 err = ice_ptp_prep_phy_incval_eth56g(hw, incval); 5896 break; 5897 default: 5898 err = -EOPNOTSUPP; 5899 } 5900 5901 if (err) 5902 return err; 5903 5904 return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_INCVAL); 5905 } 5906 5907 /** 5908 * ice_ptp_write_incval_locked - Program new incval while holding semaphore 5909 * @hw: pointer to HW struct 5910 * @incval: Source timer increment value per clock cycle 5911 * 5912 * Program a new PHC incval while holding the PTP semaphore. 5913 */ 5914 int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval) 5915 { 5916 int err; 5917 5918 if (!ice_ptp_lock(hw)) 5919 return -EBUSY; 5920 5921 err = ice_ptp_write_incval(hw, incval); 5922 5923 ice_ptp_unlock(hw); 5924 5925 return err; 5926 } 5927 5928 /** 5929 * ice_ptp_adj_clock - Adjust PHC clock time atomically 5930 * @hw: pointer to HW struct 5931 * @adj: Adjustment in nanoseconds 5932 * 5933 * Perform an atomic adjustment of the PHC time by the specified number of 5934 * nanoseconds. This requires a three-step process: 5935 * 5936 * 1) Write the adjustment to the source timer shadow registers 5937 * 2) Write the adjustment to the PHY timer shadow registers 5938 * 3) Issue an ICE_PTP_ADJ_TIME timer command to synchronously apply the 5939 * adjustment to both the source and port timers at the next clock cycle. 5940 */ 5941 int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj) 5942 { 5943 u8 tmr_idx; 5944 int err; 5945 5946 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5947 5948 /* Write the desired clock adjustment into the GLTSYN_SHADJ register. 5949 * For an ICE_PTP_ADJ_TIME command, this set of registers represents 5950 * the value to add to the clock time. It supports subtraction by 5951 * interpreting the value as a 2's complement integer. 5952 */ 5953 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0); 5954 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj); 5955 5956 switch (hw->mac_type) { 5957 case ICE_MAC_E810: 5958 err = ice_ptp_prep_phy_adj_e810(hw, adj); 5959 break; 5960 case ICE_MAC_E830: 5961 /* E830 sync PHYs automatically after setting GLTSYN_SHADJ */ 5962 return 0; 5963 case ICE_MAC_GENERIC: 5964 err = ice_ptp_prep_phy_adj_e82x(hw, adj); 5965 break; 5966 case ICE_MAC_GENERIC_3K_E825: 5967 err = ice_ptp_prep_phy_adj_eth56g(hw, adj); 5968 break; 5969 default: 5970 err = -EOPNOTSUPP; 5971 } 5972 5973 if (err) 5974 return err; 5975 5976 return ice_ptp_tmr_cmd(hw, ICE_PTP_ADJ_TIME); 5977 } 5978 5979 /** 5980 * ice_read_phy_tstamp - Read a PHY timestamp from the timestamo block 5981 * @hw: pointer to the HW struct 5982 * @block: the block to read from 5983 * @idx: the timestamp index to read 5984 * @tstamp: on return, the 40bit timestamp value 5985 * 5986 * Read a 40bit timestamp value out of the timestamp block. For E822 devices, 5987 * the block is the quad to read from. For E810 devices, the block is the 5988 * logical port to read from. 5989 */ 5990 int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp) 5991 { 5992 switch (hw->mac_type) { 5993 case ICE_MAC_E810: 5994 return ice_read_phy_tstamp_e810(hw, block, idx, tstamp); 5995 case ICE_MAC_E830: 5996 ice_read_phy_tstamp_e830(hw, idx, tstamp); 5997 return 0; 5998 case ICE_MAC_GENERIC: 5999 return ice_read_phy_tstamp_e82x(hw, block, idx, tstamp); 6000 case ICE_MAC_GENERIC_3K_E825: 6001 return ice_read_ptp_tstamp_eth56g(hw, block, idx, tstamp); 6002 default: 6003 return -EOPNOTSUPP; 6004 } 6005 } 6006 6007 /** 6008 * ice_clear_phy_tstamp - Clear a timestamp from the timestamp block 6009 * @hw: pointer to the HW struct 6010 * @block: the block to read from 6011 * @idx: the timestamp index to reset 6012 * 6013 * Clear a timestamp from the timestamp block, discarding its value without 6014 * returning it. This resets the memory status bit for the timestamp index 6015 * allowing it to be reused for another timestamp in the future. 6016 * 6017 * For E822 devices, the block number is the PHY quad to clear from. For E810 6018 * devices, the block number is the logical port to clear from. 6019 * 6020 * This function must only be called on a timestamp index whose valid bit is 6021 * set according to ice_get_phy_tx_tstamp_ready(). 6022 */ 6023 int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx) 6024 { 6025 switch (hw->mac_type) { 6026 case ICE_MAC_E810: 6027 return ice_clear_phy_tstamp_e810(hw, block, idx); 6028 case ICE_MAC_GENERIC: 6029 return ice_clear_phy_tstamp_e82x(hw, block, idx); 6030 case ICE_MAC_GENERIC_3K_E825: 6031 return ice_clear_ptp_tstamp_eth56g(hw, block, idx); 6032 default: 6033 return -EOPNOTSUPP; 6034 } 6035 } 6036 6037 /** 6038 * ice_get_pf_c827_idx - find and return the C827 index for the current pf 6039 * @hw: pointer to the hw struct 6040 * @idx: index of the found C827 PHY 6041 * Return: 6042 * * 0 - success 6043 * * negative - failure 6044 */ 6045 static int ice_get_pf_c827_idx(struct ice_hw *hw, u8 *idx) 6046 { 6047 struct ice_aqc_get_link_topo cmd; 6048 u8 node_part_number; 6049 u16 node_handle; 6050 int status; 6051 u8 ctx; 6052 6053 if (hw->mac_type != ICE_MAC_E810) 6054 return -ENODEV; 6055 6056 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) { 6057 *idx = C827_0; 6058 return 0; 6059 } 6060 6061 memset(&cmd, 0, sizeof(cmd)); 6062 6063 ctx = ICE_AQC_LINK_TOPO_NODE_TYPE_PHY << ICE_AQC_LINK_TOPO_NODE_TYPE_S; 6064 ctx |= ICE_AQC_LINK_TOPO_NODE_CTX_PORT << ICE_AQC_LINK_TOPO_NODE_CTX_S; 6065 cmd.addr.topo_params.node_type_ctx = ctx; 6066 6067 status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number, 6068 &node_handle); 6069 if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827) 6070 return -ENOENT; 6071 6072 if (node_handle == E810C_QSFP_C827_0_HANDLE) 6073 *idx = C827_0; 6074 else if (node_handle == E810C_QSFP_C827_1_HANDLE) 6075 *idx = C827_1; 6076 else 6077 return -EIO; 6078 6079 return 0; 6080 } 6081 6082 /** 6083 * ice_ptp_reset_ts_memory - Reset timestamp memory for all blocks 6084 * @hw: pointer to the HW struct 6085 */ 6086 void ice_ptp_reset_ts_memory(struct ice_hw *hw) 6087 { 6088 switch (hw->mac_type) { 6089 case ICE_MAC_GENERIC: 6090 ice_ptp_reset_ts_memory_e82x(hw); 6091 break; 6092 case ICE_MAC_GENERIC_3K_E825: 6093 ice_ptp_reset_ts_memory_eth56g(hw); 6094 break; 6095 case ICE_MAC_E810: 6096 default: 6097 return; 6098 } 6099 } 6100 6101 /** 6102 * ice_ptp_init_phc - Initialize PTP hardware clock 6103 * @hw: pointer to the HW struct 6104 * 6105 * Perform the steps required to initialize the PTP hardware clock. 6106 */ 6107 int ice_ptp_init_phc(struct ice_hw *hw) 6108 { 6109 u8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned; 6110 6111 /* Enable source clocks */ 6112 wr32(hw, GLTSYN_ENA(src_idx), GLTSYN_ENA_TSYN_ENA_M); 6113 6114 /* Clear event err indications for auxiliary pins */ 6115 (void)rd32(hw, GLTSYN_STAT(src_idx)); 6116 6117 switch (hw->mac_type) { 6118 case ICE_MAC_E810: 6119 return ice_ptp_init_phc_e810(hw); 6120 case ICE_MAC_E830: 6121 ice_ptp_init_phc_e830(hw); 6122 return 0; 6123 case ICE_MAC_GENERIC: 6124 return ice_ptp_init_phc_e82x(hw); 6125 case ICE_MAC_GENERIC_3K_E825: 6126 return ice_ptp_init_phc_eth56g(hw); 6127 default: 6128 return -EOPNOTSUPP; 6129 } 6130 } 6131 6132 /** 6133 * ice_get_phy_tx_tstamp_ready - Read PHY Tx memory status indication 6134 * @hw: pointer to the HW struct 6135 * @block: the timestamp block to check 6136 * @tstamp_ready: storage for the PHY Tx memory status information 6137 * 6138 * Check the PHY for Tx timestamp memory status. This reports a 64 bit value 6139 * which indicates which timestamps in the block may be captured. A set bit 6140 * means the timestamp can be read. An unset bit means the timestamp is not 6141 * ready and software should avoid reading the register. 6142 */ 6143 int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready) 6144 { 6145 switch (hw->mac_type) { 6146 case ICE_MAC_E810: 6147 return ice_get_phy_tx_tstamp_ready_e810(hw, block, 6148 tstamp_ready); 6149 case ICE_MAC_E830: 6150 ice_get_phy_tx_tstamp_ready_e830(hw, block, tstamp_ready); 6151 return 0; 6152 case ICE_MAC_GENERIC: 6153 return ice_get_phy_tx_tstamp_ready_e82x(hw, block, 6154 tstamp_ready); 6155 case ICE_MAC_GENERIC_3K_E825: 6156 return ice_get_phy_tx_tstamp_ready_eth56g(hw, block, 6157 tstamp_ready); 6158 default: 6159 return -EOPNOTSUPP; 6160 } 6161 } 6162 6163 /** 6164 * ice_cgu_get_pin_desc_e823 - get pin description array 6165 * @hw: pointer to the hw struct 6166 * @input: if request is done against input or output pin 6167 * @size: number of inputs/outputs 6168 * 6169 * Return: pointer to pin description array associated to given hw. 6170 */ 6171 static const struct ice_cgu_pin_desc * 6172 ice_cgu_get_pin_desc_e823(struct ice_hw *hw, bool input, int *size) 6173 { 6174 static const struct ice_cgu_pin_desc *t; 6175 6176 if (hw->cgu_part_number == 6177 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032) { 6178 if (input) { 6179 t = ice_e823_zl_cgu_inputs; 6180 *size = ARRAY_SIZE(ice_e823_zl_cgu_inputs); 6181 } else { 6182 t = ice_e823_zl_cgu_outputs; 6183 *size = ARRAY_SIZE(ice_e823_zl_cgu_outputs); 6184 } 6185 } else if (hw->cgu_part_number == 6186 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384) { 6187 if (input) { 6188 t = ice_e823_si_cgu_inputs; 6189 *size = ARRAY_SIZE(ice_e823_si_cgu_inputs); 6190 } else { 6191 t = ice_e823_si_cgu_outputs; 6192 *size = ARRAY_SIZE(ice_e823_si_cgu_outputs); 6193 } 6194 } else { 6195 t = NULL; 6196 *size = 0; 6197 } 6198 6199 return t; 6200 } 6201 6202 /** 6203 * ice_cgu_get_pin_desc - get pin description array 6204 * @hw: pointer to the hw struct 6205 * @input: if request is done against input or output pins 6206 * @size: size of array returned by function 6207 * 6208 * Return: pointer to pin description array associated to given hw. 6209 */ 6210 static const struct ice_cgu_pin_desc * 6211 ice_cgu_get_pin_desc(struct ice_hw *hw, bool input, int *size) 6212 { 6213 const struct ice_cgu_pin_desc *t = NULL; 6214 6215 switch (hw->device_id) { 6216 case ICE_DEV_ID_E810C_SFP: 6217 if (input) { 6218 t = ice_e810t_sfp_cgu_inputs; 6219 *size = ARRAY_SIZE(ice_e810t_sfp_cgu_inputs); 6220 } else { 6221 t = ice_e810t_sfp_cgu_outputs; 6222 *size = ARRAY_SIZE(ice_e810t_sfp_cgu_outputs); 6223 } 6224 break; 6225 case ICE_DEV_ID_E810C_QSFP: 6226 if (input) { 6227 t = ice_e810t_qsfp_cgu_inputs; 6228 *size = ARRAY_SIZE(ice_e810t_qsfp_cgu_inputs); 6229 } else { 6230 t = ice_e810t_qsfp_cgu_outputs; 6231 *size = ARRAY_SIZE(ice_e810t_qsfp_cgu_outputs); 6232 } 6233 break; 6234 case ICE_DEV_ID_E823L_10G_BASE_T: 6235 case ICE_DEV_ID_E823L_1GBE: 6236 case ICE_DEV_ID_E823L_BACKPLANE: 6237 case ICE_DEV_ID_E823L_QSFP: 6238 case ICE_DEV_ID_E823L_SFP: 6239 case ICE_DEV_ID_E823C_10G_BASE_T: 6240 case ICE_DEV_ID_E823C_BACKPLANE: 6241 case ICE_DEV_ID_E823C_QSFP: 6242 case ICE_DEV_ID_E823C_SFP: 6243 case ICE_DEV_ID_E823C_SGMII: 6244 t = ice_cgu_get_pin_desc_e823(hw, input, size); 6245 break; 6246 default: 6247 break; 6248 } 6249 6250 return t; 6251 } 6252 6253 /** 6254 * ice_cgu_get_num_pins - get pin description array size 6255 * @hw: pointer to the hw struct 6256 * @input: if request is done against input or output pins 6257 * 6258 * Return: size of pin description array for given hw. 6259 */ 6260 int ice_cgu_get_num_pins(struct ice_hw *hw, bool input) 6261 { 6262 const struct ice_cgu_pin_desc *t; 6263 int size; 6264 6265 t = ice_cgu_get_pin_desc(hw, input, &size); 6266 if (t) 6267 return size; 6268 6269 return 0; 6270 } 6271 6272 /** 6273 * ice_cgu_get_pin_type - get pin's type 6274 * @hw: pointer to the hw struct 6275 * @pin: pin index 6276 * @input: if request is done against input or output pin 6277 * 6278 * Return: type of a pin. 6279 */ 6280 enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool input) 6281 { 6282 const struct ice_cgu_pin_desc *t; 6283 int t_size; 6284 6285 t = ice_cgu_get_pin_desc(hw, input, &t_size); 6286 6287 if (!t) 6288 return 0; 6289 6290 if (pin >= t_size) 6291 return 0; 6292 6293 return t[pin].type; 6294 } 6295 6296 /** 6297 * ice_cgu_get_pin_freq_supp - get pin's supported frequency 6298 * @hw: pointer to the hw struct 6299 * @pin: pin index 6300 * @input: if request is done against input or output pin 6301 * @num: output number of supported frequencies 6302 * 6303 * Get frequency supported number and array of supported frequencies. 6304 * 6305 * Return: array of supported frequencies for given pin. 6306 */ 6307 struct dpll_pin_frequency * 6308 ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num) 6309 { 6310 const struct ice_cgu_pin_desc *t; 6311 int t_size; 6312 6313 *num = 0; 6314 t = ice_cgu_get_pin_desc(hw, input, &t_size); 6315 if (!t) 6316 return NULL; 6317 if (pin >= t_size) 6318 return NULL; 6319 *num = t[pin].freq_supp_num; 6320 6321 return t[pin].freq_supp; 6322 } 6323 6324 /** 6325 * ice_cgu_get_pin_name - get pin's name 6326 * @hw: pointer to the hw struct 6327 * @pin: pin index 6328 * @input: if request is done against input or output pin 6329 * 6330 * Return: 6331 * * null terminated char array with name 6332 * * NULL in case of failure 6333 */ 6334 const char *ice_cgu_get_pin_name(struct ice_hw *hw, u8 pin, bool input) 6335 { 6336 const struct ice_cgu_pin_desc *t; 6337 int t_size; 6338 6339 t = ice_cgu_get_pin_desc(hw, input, &t_size); 6340 6341 if (!t) 6342 return NULL; 6343 6344 if (pin >= t_size) 6345 return NULL; 6346 6347 return t[pin].name; 6348 } 6349 6350 /** 6351 * ice_get_cgu_state - get the state of the DPLL 6352 * @hw: pointer to the hw struct 6353 * @dpll_idx: Index of internal DPLL unit 6354 * @last_dpll_state: last known state of DPLL 6355 * @pin: pointer to a buffer for returning currently active pin 6356 * @ref_state: reference clock state 6357 * @eec_mode: eec mode of the DPLL 6358 * @phase_offset: pointer to a buffer for returning phase offset 6359 * @dpll_state: state of the DPLL (output) 6360 * 6361 * This function will read the state of the DPLL(dpll_idx). Non-null 6362 * 'pin', 'ref_state', 'eec_mode' and 'phase_offset' parameters are used to 6363 * retrieve currently active pin, state, mode and phase_offset respectively. 6364 * 6365 * Return: state of the DPLL 6366 */ 6367 int ice_get_cgu_state(struct ice_hw *hw, u8 dpll_idx, 6368 enum dpll_lock_status last_dpll_state, u8 *pin, 6369 u8 *ref_state, u8 *eec_mode, s64 *phase_offset, 6370 enum dpll_lock_status *dpll_state) 6371 { 6372 u8 hw_ref_state, hw_dpll_state, hw_eec_mode, hw_config; 6373 s64 hw_phase_offset; 6374 int status; 6375 6376 status = ice_aq_get_cgu_dpll_status(hw, dpll_idx, &hw_ref_state, 6377 &hw_dpll_state, &hw_config, 6378 &hw_phase_offset, &hw_eec_mode); 6379 if (status) 6380 return status; 6381 6382 if (pin) 6383 /* current ref pin in dpll_state_refsel_status_X register */ 6384 *pin = hw_config & ICE_AQC_GET_CGU_DPLL_CONFIG_CLK_REF_SEL; 6385 if (phase_offset) 6386 *phase_offset = hw_phase_offset; 6387 if (ref_state) 6388 *ref_state = hw_ref_state; 6389 if (eec_mode) 6390 *eec_mode = hw_eec_mode; 6391 if (!dpll_state) 6392 return 0; 6393 6394 /* According to ZL DPLL documentation, once state reach LOCKED_HO_ACQ 6395 * it would never return to FREERUN. This aligns to ITU-T G.781 6396 * Recommendation. We cannot report HOLDOVER as HO memory is cleared 6397 * while switching to another reference. 6398 * Only for situations where previous state was either: "LOCKED without 6399 * HO_ACQ" or "HOLDOVER" we actually back to FREERUN. 6400 */ 6401 if (hw_dpll_state & ICE_AQC_GET_CGU_DPLL_STATUS_STATE_LOCK) { 6402 if (hw_dpll_state & ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO_READY) 6403 *dpll_state = DPLL_LOCK_STATUS_LOCKED_HO_ACQ; 6404 else 6405 *dpll_state = DPLL_LOCK_STATUS_LOCKED; 6406 } else if (last_dpll_state == DPLL_LOCK_STATUS_LOCKED_HO_ACQ || 6407 last_dpll_state == DPLL_LOCK_STATUS_HOLDOVER) { 6408 *dpll_state = DPLL_LOCK_STATUS_HOLDOVER; 6409 } else { 6410 *dpll_state = DPLL_LOCK_STATUS_UNLOCKED; 6411 } 6412 6413 return 0; 6414 } 6415 6416 /** 6417 * ice_get_cgu_rclk_pin_info - get info on available recovered clock pins 6418 * @hw: pointer to the hw struct 6419 * @base_idx: returns index of first recovered clock pin on device 6420 * @pin_num: returns number of recovered clock pins available on device 6421 * 6422 * Based on hw provide caller info about recovery clock pins available on the 6423 * board. 6424 * 6425 * Return: 6426 * * 0 - success, information is valid 6427 * * negative - failure, information is not valid 6428 */ 6429 int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num) 6430 { 6431 u8 phy_idx; 6432 int ret; 6433 6434 switch (hw->device_id) { 6435 case ICE_DEV_ID_E810C_SFP: 6436 case ICE_DEV_ID_E810C_QSFP: 6437 6438 ret = ice_get_pf_c827_idx(hw, &phy_idx); 6439 if (ret) 6440 return ret; 6441 *base_idx = E810T_CGU_INPUT_C827(phy_idx, ICE_RCLKA_PIN); 6442 *pin_num = ICE_E810_RCLK_PINS_NUM; 6443 ret = 0; 6444 break; 6445 case ICE_DEV_ID_E823L_10G_BASE_T: 6446 case ICE_DEV_ID_E823L_1GBE: 6447 case ICE_DEV_ID_E823L_BACKPLANE: 6448 case ICE_DEV_ID_E823L_QSFP: 6449 case ICE_DEV_ID_E823L_SFP: 6450 case ICE_DEV_ID_E823C_10G_BASE_T: 6451 case ICE_DEV_ID_E823C_BACKPLANE: 6452 case ICE_DEV_ID_E823C_QSFP: 6453 case ICE_DEV_ID_E823C_SFP: 6454 case ICE_DEV_ID_E823C_SGMII: 6455 *pin_num = ICE_E82X_RCLK_PINS_NUM; 6456 ret = 0; 6457 if (hw->cgu_part_number == 6458 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032) 6459 *base_idx = ZL_REF1P; 6460 else if (hw->cgu_part_number == 6461 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384) 6462 *base_idx = SI_REF1P; 6463 else 6464 ret = -ENODEV; 6465 6466 break; 6467 default: 6468 ret = -ENODEV; 6469 break; 6470 } 6471 6472 return ret; 6473 } 6474 6475 /** 6476 * ice_cgu_get_output_pin_state_caps - get output pin state capabilities 6477 * @hw: pointer to the hw struct 6478 * @pin_id: id of a pin 6479 * @caps: capabilities to modify 6480 * 6481 * Return: 6482 * * 0 - success, state capabilities were modified 6483 * * negative - failure, capabilities were not modified 6484 */ 6485 int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id, 6486 unsigned long *caps) 6487 { 6488 bool can_change = true; 6489 6490 switch (hw->device_id) { 6491 case ICE_DEV_ID_E810C_SFP: 6492 if (pin_id == ZL_OUT2 || pin_id == ZL_OUT3) 6493 can_change = false; 6494 break; 6495 case ICE_DEV_ID_E810C_QSFP: 6496 if (pin_id == ZL_OUT2 || pin_id == ZL_OUT3 || pin_id == ZL_OUT4) 6497 can_change = false; 6498 break; 6499 case ICE_DEV_ID_E823L_10G_BASE_T: 6500 case ICE_DEV_ID_E823L_1GBE: 6501 case ICE_DEV_ID_E823L_BACKPLANE: 6502 case ICE_DEV_ID_E823L_QSFP: 6503 case ICE_DEV_ID_E823L_SFP: 6504 case ICE_DEV_ID_E823C_10G_BASE_T: 6505 case ICE_DEV_ID_E823C_BACKPLANE: 6506 case ICE_DEV_ID_E823C_QSFP: 6507 case ICE_DEV_ID_E823C_SFP: 6508 case ICE_DEV_ID_E823C_SGMII: 6509 if (hw->cgu_part_number == 6510 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032 && 6511 pin_id == ZL_OUT2) 6512 can_change = false; 6513 else if (hw->cgu_part_number == 6514 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384 && 6515 pin_id == SI_OUT1) 6516 can_change = false; 6517 break; 6518 default: 6519 return -EINVAL; 6520 } 6521 if (can_change) 6522 *caps |= DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE; 6523 else 6524 *caps &= ~DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE; 6525 6526 return 0; 6527 } 6528