1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (C) 2021, Intel Corporation. */ 3 4 #include <linux/delay.h> 5 #include <linux/iopoll.h> 6 #include "ice_common.h" 7 #include "ice_ptp_hw.h" 8 #include "ice_ptp_consts.h" 9 10 static struct dpll_pin_frequency ice_cgu_pin_freq_common[] = { 11 DPLL_PIN_FREQUENCY_1PPS, 12 DPLL_PIN_FREQUENCY_10MHZ, 13 }; 14 15 static struct dpll_pin_frequency ice_cgu_pin_freq_1_hz[] = { 16 DPLL_PIN_FREQUENCY_1PPS, 17 }; 18 19 static struct dpll_pin_frequency ice_cgu_pin_freq_10_mhz[] = { 20 DPLL_PIN_FREQUENCY_10MHZ, 21 }; 22 23 static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_inputs[] = { 24 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR, 25 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 26 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR, 27 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 28 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, }, 29 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, }, 30 { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT, 31 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 32 { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT, 33 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 34 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS, 35 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 36 }; 37 38 static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_inputs[] = { 39 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR, 40 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 41 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR, 42 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 43 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, }, 44 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, }, 45 { "C827_1-RCLKA", ZL_REF2P, DPLL_PIN_TYPE_MUX, }, 46 { "C827_1-RCLKB", ZL_REF2N, DPLL_PIN_TYPE_MUX, }, 47 { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT, 48 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 49 { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT, 50 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 51 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS, 52 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 53 }; 54 55 static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_outputs[] = { 56 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT, 57 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 58 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT, 59 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 60 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, }, 61 { "MAC-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, }, 62 { "CVL-SDP21", ZL_OUT4, DPLL_PIN_TYPE_EXT, 63 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 64 { "CVL-SDP23", ZL_OUT5, DPLL_PIN_TYPE_EXT, 65 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 66 }; 67 68 static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_outputs[] = { 69 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT, 70 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 71 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT, 72 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 73 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 74 { "PHY2-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 75 { "MAC-CLK", ZL_OUT4, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 76 { "CVL-SDP21", ZL_OUT5, DPLL_PIN_TYPE_EXT, 77 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 78 { "CVL-SDP23", ZL_OUT6, DPLL_PIN_TYPE_EXT, 79 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 80 }; 81 82 static const struct ice_cgu_pin_desc ice_e823_si_cgu_inputs[] = { 83 { "NONE", SI_REF0P, 0, 0 }, 84 { "NONE", SI_REF0N, 0, 0 }, 85 { "SYNCE0_DP", SI_REF1P, DPLL_PIN_TYPE_MUX, 0 }, 86 { "SYNCE0_DN", SI_REF1N, DPLL_PIN_TYPE_MUX, 0 }, 87 { "EXT_CLK_SYNC", SI_REF2P, DPLL_PIN_TYPE_EXT, 88 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 89 { "NONE", SI_REF2N, 0, 0 }, 90 { "EXT_PPS_OUT", SI_REF3, DPLL_PIN_TYPE_EXT, 91 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 92 { "INT_PPS_OUT", SI_REF4, DPLL_PIN_TYPE_EXT, 93 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 94 }; 95 96 static const struct ice_cgu_pin_desc ice_e823_si_cgu_outputs[] = { 97 { "1588-TIME_SYNC", SI_OUT0, DPLL_PIN_TYPE_EXT, 98 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 99 { "PHY-CLK", SI_OUT1, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 100 { "10MHZ-SMA2", SI_OUT2, DPLL_PIN_TYPE_EXT, 101 ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz }, 102 { "PPS-SMA1", SI_OUT3, DPLL_PIN_TYPE_EXT, 103 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 104 }; 105 106 static const struct ice_cgu_pin_desc ice_e823_zl_cgu_inputs[] = { 107 { "NONE", ZL_REF0P, 0, 0 }, 108 { "INT_PPS_OUT", ZL_REF0N, DPLL_PIN_TYPE_EXT, 109 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 110 { "SYNCE0_DP", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0 }, 111 { "SYNCE0_DN", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0 }, 112 { "NONE", ZL_REF2P, 0, 0 }, 113 { "NONE", ZL_REF2N, 0, 0 }, 114 { "EXT_CLK_SYNC", ZL_REF3P, DPLL_PIN_TYPE_EXT, 115 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 116 { "NONE", ZL_REF3N, 0, 0 }, 117 { "EXT_PPS_OUT", ZL_REF4P, DPLL_PIN_TYPE_EXT, 118 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 119 { "OCXO", ZL_REF4N, DPLL_PIN_TYPE_INT_OSCILLATOR, 0 }, 120 }; 121 122 static const struct ice_cgu_pin_desc ice_e823_zl_cgu_outputs[] = { 123 { "PPS-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT, 124 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 125 { "10MHZ-SMA2", ZL_OUT1, DPLL_PIN_TYPE_EXT, 126 ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz }, 127 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 128 { "1588-TIME_REF", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 129 { "CPK-TIME_SYNC", ZL_OUT4, DPLL_PIN_TYPE_EXT, 130 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 131 { "NONE", ZL_OUT5, 0, 0 }, 132 }; 133 134 /* Low level functions for interacting with and managing the device clock used 135 * for the Precision Time Protocol. 136 * 137 * The ice hardware represents the current time using three registers: 138 * 139 * GLTSYN_TIME_H GLTSYN_TIME_L GLTSYN_TIME_R 140 * +---------------+ +---------------+ +---------------+ 141 * | 32 bits | | 32 bits | | 32 bits | 142 * +---------------+ +---------------+ +---------------+ 143 * 144 * The registers are incremented every clock tick using a 40bit increment 145 * value defined over two registers: 146 * 147 * GLTSYN_INCVAL_H GLTSYN_INCVAL_L 148 * +---------------+ +---------------+ 149 * | 8 bit s | | 32 bits | 150 * +---------------+ +---------------+ 151 * 152 * The increment value is added to the GLSTYN_TIME_R and GLSTYN_TIME_L 153 * registers every clock source tick. Depending on the specific device 154 * configuration, the clock source frequency could be one of a number of 155 * values. 156 * 157 * For E810 devices, the increment frequency is 812.5 MHz 158 * 159 * For E822 devices the clock can be derived from different sources, and the 160 * increment has an effective frequency of one of the following: 161 * - 823.4375 MHz 162 * - 783.36 MHz 163 * - 796.875 MHz 164 * - 816 MHz 165 * - 830.078125 MHz 166 * - 783.36 MHz 167 * 168 * The hardware captures timestamps in the PHY for incoming packets, and for 169 * outgoing packets on request. To support this, the PHY maintains a timer 170 * that matches the lower 64 bits of the global source timer. 171 * 172 * In order to ensure that the PHY timers and the source timer are equivalent, 173 * shadow registers are used to prepare the desired initial values. A special 174 * sync command is issued to trigger copying from the shadow registers into 175 * the appropriate source and PHY registers simultaneously. 176 * 177 * The driver supports devices which have different PHYs with subtly different 178 * mechanisms to program and control the timers. We divide the devices into 179 * families named after the first major device, E810 and similar devices, and 180 * E822 and similar devices. 181 * 182 * - E822 based devices have additional support for fine grained Vernier 183 * calibration which requires significant setup 184 * - The layout of timestamp data in the PHY register blocks is different 185 * - The way timer synchronization commands are issued is different. 186 * 187 * To support this, very low level functions have an e810 or e822 suffix 188 * indicating what type of device they work on. Higher level abstractions for 189 * tasks that can be done on both devices do not have the suffix and will 190 * correctly look up the appropriate low level function when running. 191 * 192 * Functions which only make sense on a single device family may not have 193 * a suitable generic implementation 194 */ 195 196 /** 197 * ice_get_ptp_src_clock_index - determine source clock index 198 * @hw: pointer to HW struct 199 * 200 * Determine the source clock index currently in use, based on device 201 * capabilities reported during initialization. 202 */ 203 u8 ice_get_ptp_src_clock_index(struct ice_hw *hw) 204 { 205 return hw->func_caps.ts_func_info.tmr_index_assoc; 206 } 207 208 /** 209 * ice_ptp_read_src_incval - Read source timer increment value 210 * @hw: pointer to HW struct 211 * 212 * Read the increment value of the source timer and return it. 213 */ 214 static u64 ice_ptp_read_src_incval(struct ice_hw *hw) 215 { 216 u32 lo, hi; 217 u8 tmr_idx; 218 219 tmr_idx = ice_get_ptp_src_clock_index(hw); 220 221 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 222 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 223 224 return ((u64)(hi & INCVAL_HIGH_M) << 32) | lo; 225 } 226 227 /** 228 * ice_ptp_tmr_cmd_to_src_reg - Convert to source timer command value 229 * @hw: pointer to HW struct 230 * @cmd: Timer command 231 * 232 * Return: the source timer command register value for the given PTP timer 233 * command. 234 */ 235 static u32 ice_ptp_tmr_cmd_to_src_reg(struct ice_hw *hw, 236 enum ice_ptp_tmr_cmd cmd) 237 { 238 u32 cmd_val, tmr_idx; 239 240 switch (cmd) { 241 case ICE_PTP_INIT_TIME: 242 cmd_val = GLTSYN_CMD_INIT_TIME; 243 break; 244 case ICE_PTP_INIT_INCVAL: 245 cmd_val = GLTSYN_CMD_INIT_INCVAL; 246 break; 247 case ICE_PTP_ADJ_TIME: 248 cmd_val = GLTSYN_CMD_ADJ_TIME; 249 break; 250 case ICE_PTP_ADJ_TIME_AT_TIME: 251 cmd_val = GLTSYN_CMD_ADJ_INIT_TIME; 252 break; 253 case ICE_PTP_NOP: 254 case ICE_PTP_READ_TIME: 255 cmd_val = GLTSYN_CMD_READ_TIME; 256 break; 257 default: 258 dev_warn(ice_hw_to_dev(hw), 259 "Ignoring unrecognized timer command %u\n", cmd); 260 cmd_val = 0; 261 } 262 263 tmr_idx = ice_get_ptp_src_clock_index(hw); 264 265 return tmr_idx << SEL_CPK_SRC | cmd_val; 266 } 267 268 /** 269 * ice_ptp_tmr_cmd_to_port_reg- Convert to port timer command value 270 * @hw: pointer to HW struct 271 * @cmd: Timer command 272 * 273 * Note that some hardware families use a different command register value for 274 * the PHY ports, while other hardware families use the same register values 275 * as the source timer. 276 * 277 * Return: the PHY port timer command register value for the given PTP timer 278 * command. 279 */ 280 static u32 ice_ptp_tmr_cmd_to_port_reg(struct ice_hw *hw, 281 enum ice_ptp_tmr_cmd cmd) 282 { 283 u32 cmd_val, tmr_idx; 284 285 /* Certain hardware families share the same register values for the 286 * port register and source timer register. 287 */ 288 switch (hw->mac_type) { 289 case ICE_MAC_E810: 290 case ICE_MAC_E830: 291 return ice_ptp_tmr_cmd_to_src_reg(hw, cmd) & TS_CMD_MASK_E810; 292 default: 293 break; 294 } 295 296 switch (cmd) { 297 case ICE_PTP_INIT_TIME: 298 cmd_val = PHY_CMD_INIT_TIME; 299 break; 300 case ICE_PTP_INIT_INCVAL: 301 cmd_val = PHY_CMD_INIT_INCVAL; 302 break; 303 case ICE_PTP_ADJ_TIME: 304 cmd_val = PHY_CMD_ADJ_TIME; 305 break; 306 case ICE_PTP_ADJ_TIME_AT_TIME: 307 cmd_val = PHY_CMD_ADJ_TIME_AT_TIME; 308 break; 309 case ICE_PTP_READ_TIME: 310 cmd_val = PHY_CMD_READ_TIME; 311 break; 312 case ICE_PTP_NOP: 313 cmd_val = 0; 314 break; 315 default: 316 dev_warn(ice_hw_to_dev(hw), 317 "Ignoring unrecognized timer command %u\n", cmd); 318 cmd_val = 0; 319 } 320 321 tmr_idx = ice_get_ptp_src_clock_index(hw); 322 323 return tmr_idx << SEL_PHY_SRC | cmd_val; 324 } 325 326 /** 327 * ice_ptp_src_cmd - Prepare source timer for a timer command 328 * @hw: pointer to HW structure 329 * @cmd: Timer command 330 * 331 * Prepare the source timer for an upcoming timer sync command. 332 */ 333 void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 334 { 335 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 336 u32 cmd_val = ice_ptp_tmr_cmd_to_src_reg(hw, cmd); 337 338 if (!ice_is_primary(hw)) 339 hw = ice_get_primary_hw(pf); 340 341 wr32(hw, GLTSYN_CMD, cmd_val); 342 } 343 344 /** 345 * ice_ptp_exec_tmr_cmd - Execute all prepared timer commands 346 * @hw: pointer to HW struct 347 * 348 * Write the SYNC_EXEC_CMD bit to the GLTSYN_CMD_SYNC register, and flush the 349 * write immediately. This triggers the hardware to begin executing all of the 350 * source and PHY timer commands synchronously. 351 */ 352 static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw) 353 { 354 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 355 356 if (!ice_is_primary(hw)) 357 hw = ice_get_primary_hw(pf); 358 359 guard(spinlock)(&pf->adapter->ptp_gltsyn_time_lock); 360 wr32(hw, GLTSYN_CMD_SYNC, SYNC_EXEC_CMD); 361 ice_flush(hw); 362 } 363 364 /** 365 * ice_ptp_cfg_sync_delay - Configure PHC to PHY synchronization delay 366 * @hw: pointer to HW struct 367 * @delay: delay between PHC and PHY SYNC command execution in nanoseconds 368 */ 369 static void ice_ptp_cfg_sync_delay(const struct ice_hw *hw, u32 delay) 370 { 371 wr32(hw, GLTSYN_SYNC_DLAY, delay); 372 ice_flush(hw); 373 } 374 375 /* 56G PHY device functions 376 * 377 * The following functions operate on devices with the ETH 56G PHY. 378 */ 379 380 /** 381 * ice_ptp_get_dest_dev_e825 - get destination PHY for given port number 382 * @hw: pointer to the HW struct 383 * @port: destination port 384 * 385 * Return: destination sideband queue PHY device. 386 */ 387 static enum ice_sbq_dev_id ice_ptp_get_dest_dev_e825(struct ice_hw *hw, 388 u8 port) 389 { 390 u8 curr_phy, tgt_phy; 391 392 tgt_phy = port >= hw->ptp.ports_per_phy; 393 curr_phy = hw->lane_num >= hw->ptp.ports_per_phy; 394 /* In the driver, lanes 4..7 are in fact 0..3 on a second PHY. 395 * On a single complex E825C, PHY 0 is always destination device phy_0 396 * and PHY 1 is phy_0_peer. 397 * On dual complex E825C, device phy_0 points to PHY on a current 398 * complex and phy_0_peer to PHY on a different complex. 399 */ 400 if ((!ice_is_dual(hw) && tgt_phy == 1) || 401 (ice_is_dual(hw) && tgt_phy != curr_phy)) 402 return ice_sbq_dev_phy_0_peer; 403 else 404 return ice_sbq_dev_phy_0; 405 } 406 407 /** 408 * ice_write_phy_eth56g - Write a PHY port register 409 * @hw: pointer to the HW struct 410 * @port: destination port 411 * @addr: PHY register address 412 * @val: Value to write 413 * 414 * Return: 0 on success, other error codes when failed to write to PHY 415 */ 416 static int ice_write_phy_eth56g(struct ice_hw *hw, u8 port, u32 addr, u32 val) 417 { 418 struct ice_sbq_msg_input msg = { 419 .dest_dev = ice_ptp_get_dest_dev_e825(hw, port), 420 .opcode = ice_sbq_msg_wr, 421 .msg_addr_low = lower_16_bits(addr), 422 .msg_addr_high = upper_16_bits(addr), 423 .data = val 424 }; 425 int err; 426 427 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 428 if (err) 429 ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n", 430 err); 431 432 return err; 433 } 434 435 /** 436 * ice_read_phy_eth56g - Read a PHY port register 437 * @hw: pointer to the HW struct 438 * @port: destination port 439 * @addr: PHY register address 440 * @val: Value to write 441 * 442 * Return: 0 on success, other error codes when failed to read from PHY 443 */ 444 static int ice_read_phy_eth56g(struct ice_hw *hw, u8 port, u32 addr, u32 *val) 445 { 446 struct ice_sbq_msg_input msg = { 447 .dest_dev = ice_ptp_get_dest_dev_e825(hw, port), 448 .opcode = ice_sbq_msg_rd, 449 .msg_addr_low = lower_16_bits(addr), 450 .msg_addr_high = upper_16_bits(addr) 451 }; 452 int err; 453 454 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 455 if (err) 456 ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n", 457 err); 458 else 459 *val = msg.data; 460 461 return err; 462 } 463 464 /** 465 * ice_phy_res_address_eth56g - Calculate a PHY port register address 466 * @hw: pointer to the HW struct 467 * @lane: Lane number to be written 468 * @res_type: resource type (register/memory) 469 * @offset: Offset from PHY port register base 470 * @addr: The result address 471 * 472 * Return: 473 * * %0 - success 474 * * %EINVAL - invalid port number or resource type 475 */ 476 static int ice_phy_res_address_eth56g(struct ice_hw *hw, u8 lane, 477 enum eth56g_res_type res_type, 478 u32 offset, 479 u32 *addr) 480 { 481 if (res_type >= NUM_ETH56G_PHY_RES) 482 return -EINVAL; 483 484 /* Lanes 4..7 are in fact 0..3 on a second PHY */ 485 lane %= hw->ptp.ports_per_phy; 486 *addr = eth56g_phy_res[res_type].base_addr + 487 lane * eth56g_phy_res[res_type].step + offset; 488 489 return 0; 490 } 491 492 /** 493 * ice_write_port_eth56g - Write a PHY port register 494 * @hw: pointer to the HW struct 495 * @offset: PHY register offset 496 * @port: Port number 497 * @val: Value to write 498 * @res_type: resource type (register/memory) 499 * 500 * Return: 501 * * %0 - success 502 * * %EINVAL - invalid port number or resource type 503 * * %other - failed to write to PHY 504 */ 505 static int ice_write_port_eth56g(struct ice_hw *hw, u8 port, u32 offset, 506 u32 val, enum eth56g_res_type res_type) 507 { 508 u32 addr; 509 int err; 510 511 if (port >= hw->ptp.num_lports) 512 return -EINVAL; 513 514 err = ice_phy_res_address_eth56g(hw, port, res_type, offset, &addr); 515 if (err) 516 return err; 517 518 return ice_write_phy_eth56g(hw, port, addr, val); 519 } 520 521 /** 522 * ice_read_port_eth56g - Read a PHY port register 523 * @hw: pointer to the HW struct 524 * @offset: PHY register offset 525 * @port: Port number 526 * @val: Value to write 527 * @res_type: resource type (register/memory) 528 * 529 * Return: 530 * * %0 - success 531 * * %EINVAL - invalid port number or resource type 532 * * %other - failed to read from PHY 533 */ 534 static int ice_read_port_eth56g(struct ice_hw *hw, u8 port, u32 offset, 535 u32 *val, enum eth56g_res_type res_type) 536 { 537 u32 addr; 538 int err; 539 540 if (port >= hw->ptp.num_lports) 541 return -EINVAL; 542 543 err = ice_phy_res_address_eth56g(hw, port, res_type, offset, &addr); 544 if (err) 545 return err; 546 547 return ice_read_phy_eth56g(hw, port, addr, val); 548 } 549 550 /** 551 * ice_write_ptp_reg_eth56g - Write a PHY port register 552 * @hw: pointer to the HW struct 553 * @port: Port number to be written 554 * @offset: Offset from PHY port register base 555 * @val: Value to write 556 * 557 * Return: 558 * * %0 - success 559 * * %EINVAL - invalid port number or resource type 560 * * %other - failed to write to PHY 561 */ 562 static int ice_write_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 563 u32 val) 564 { 565 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_PTP); 566 } 567 568 /** 569 * ice_write_mac_reg_eth56g - Write a MAC PHY port register 570 * parameter 571 * @hw: pointer to the HW struct 572 * @port: Port number to be written 573 * @offset: Offset from PHY port register base 574 * @val: Value to write 575 * 576 * Return: 577 * * %0 - success 578 * * %EINVAL - invalid port number or resource type 579 * * %other - failed to write to PHY 580 */ 581 static int ice_write_mac_reg_eth56g(struct ice_hw *hw, u8 port, u32 offset, 582 u32 val) 583 { 584 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_MAC); 585 } 586 587 /** 588 * ice_write_xpcs_reg_eth56g - Write a PHY port register 589 * @hw: pointer to the HW struct 590 * @port: Port number to be written 591 * @offset: Offset from PHY port register base 592 * @val: Value to write 593 * 594 * Return: 595 * * %0 - success 596 * * %EINVAL - invalid port number or resource type 597 * * %other - failed to write to PHY 598 */ 599 static int ice_write_xpcs_reg_eth56g(struct ice_hw *hw, u8 port, u32 offset, 600 u32 val) 601 { 602 return ice_write_port_eth56g(hw, port, offset, val, 603 ETH56G_PHY_REG_XPCS); 604 } 605 606 /** 607 * ice_read_ptp_reg_eth56g - Read a PHY port register 608 * @hw: pointer to the HW struct 609 * @port: Port number to be read 610 * @offset: Offset from PHY port register base 611 * @val: Pointer to the value to read (out param) 612 * 613 * Return: 614 * * %0 - success 615 * * %EINVAL - invalid port number or resource type 616 * * %other - failed to read from PHY 617 */ 618 static int ice_read_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 619 u32 *val) 620 { 621 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_PTP); 622 } 623 624 /** 625 * ice_read_mac_reg_eth56g - Read a PHY port register 626 * @hw: pointer to the HW struct 627 * @port: Port number to be read 628 * @offset: Offset from PHY port register base 629 * @val: Pointer to the value to read (out param) 630 * 631 * Return: 632 * * %0 - success 633 * * %EINVAL - invalid port number or resource type 634 * * %other - failed to read from PHY 635 */ 636 static int ice_read_mac_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 637 u32 *val) 638 { 639 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_MAC); 640 } 641 642 /** 643 * ice_read_gpcs_reg_eth56g - Read a PHY port register 644 * @hw: pointer to the HW struct 645 * @port: Port number to be read 646 * @offset: Offset from PHY port register base 647 * @val: Pointer to the value to read (out param) 648 * 649 * Return: 650 * * %0 - success 651 * * %EINVAL - invalid port number or resource type 652 * * %other - failed to read from PHY 653 */ 654 static int ice_read_gpcs_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 655 u32 *val) 656 { 657 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_GPCS); 658 } 659 660 /** 661 * ice_read_port_mem_eth56g - Read a PHY port memory location 662 * @hw: pointer to the HW struct 663 * @port: Port number to be read 664 * @offset: Offset from PHY port register base 665 * @val: Pointer to the value to read (out param) 666 * 667 * Return: 668 * * %0 - success 669 * * %EINVAL - invalid port number or resource type 670 * * %other - failed to read from PHY 671 */ 672 static int ice_read_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset, 673 u32 *val) 674 { 675 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_MEM_PTP); 676 } 677 678 /** 679 * ice_write_port_mem_eth56g - Write a PHY port memory location 680 * @hw: pointer to the HW struct 681 * @port: Port number to be read 682 * @offset: Offset from PHY port register base 683 * @val: Pointer to the value to read (out param) 684 * 685 * Return: 686 * * %0 - success 687 * * %EINVAL - invalid port number or resource type 688 * * %other - failed to write to PHY 689 */ 690 static int ice_write_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset, 691 u32 val) 692 { 693 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_MEM_PTP); 694 } 695 696 /** 697 * ice_write_quad_ptp_reg_eth56g - Write a PHY quad register 698 * @hw: pointer to the HW struct 699 * @offset: PHY register offset 700 * @port: Port number 701 * @val: Value to write 702 * 703 * Return: 704 * * %0 - success 705 * * %EIO - invalid port number or resource type 706 * * %other - failed to write to PHY 707 */ 708 static int ice_write_quad_ptp_reg_eth56g(struct ice_hw *hw, u8 port, 709 u32 offset, u32 val) 710 { 711 u32 addr; 712 713 if (port >= hw->ptp.num_lports) 714 return -EIO; 715 716 addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base_addr + offset; 717 718 return ice_write_phy_eth56g(hw, port, addr, val); 719 } 720 721 /** 722 * ice_read_quad_ptp_reg_eth56g - Read a PHY quad register 723 * @hw: pointer to the HW struct 724 * @offset: PHY register offset 725 * @port: Port number 726 * @val: Value to read 727 * 728 * Return: 729 * * %0 - success 730 * * %EIO - invalid port number or resource type 731 * * %other - failed to read from PHY 732 */ 733 static int ice_read_quad_ptp_reg_eth56g(struct ice_hw *hw, u8 port, 734 u32 offset, u32 *val) 735 { 736 u32 addr; 737 738 if (port >= hw->ptp.num_lports) 739 return -EIO; 740 741 addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base_addr + offset; 742 743 return ice_read_phy_eth56g(hw, port, addr, val); 744 } 745 746 /** 747 * ice_is_64b_phy_reg_eth56g - Check if this is a 64bit PHY register 748 * @low_addr: the low address to check 749 * @high_addr: on return, contains the high address of the 64bit register 750 * 751 * Write the appropriate high register offset to use. 752 * 753 * Return: true if the provided low address is one of the known 64bit PHY values 754 * represented as two 32bit registers, false otherwise. 755 */ 756 static bool ice_is_64b_phy_reg_eth56g(u16 low_addr, u16 *high_addr) 757 { 758 switch (low_addr) { 759 case PHY_REG_TX_TIMER_INC_PRE_L: 760 *high_addr = PHY_REG_TX_TIMER_INC_PRE_U; 761 return true; 762 case PHY_REG_RX_TIMER_INC_PRE_L: 763 *high_addr = PHY_REG_RX_TIMER_INC_PRE_U; 764 return true; 765 case PHY_REG_TX_CAPTURE_L: 766 *high_addr = PHY_REG_TX_CAPTURE_U; 767 return true; 768 case PHY_REG_RX_CAPTURE_L: 769 *high_addr = PHY_REG_RX_CAPTURE_U; 770 return true; 771 case PHY_REG_TOTAL_TX_OFFSET_L: 772 *high_addr = PHY_REG_TOTAL_TX_OFFSET_U; 773 return true; 774 case PHY_REG_TOTAL_RX_OFFSET_L: 775 *high_addr = PHY_REG_TOTAL_RX_OFFSET_U; 776 return true; 777 case PHY_REG_TX_MEMORY_STATUS_L: 778 *high_addr = PHY_REG_TX_MEMORY_STATUS_U; 779 return true; 780 default: 781 return false; 782 } 783 } 784 785 /** 786 * ice_is_40b_phy_reg_eth56g - Check if this is a 40bit PHY register 787 * @low_addr: the low address to check 788 * @high_addr: on return, contains the high address of the 40bit value 789 * 790 * Write the appropriate high register offset to use. 791 * 792 * Return: true if the provided low address is one of the known 40bit PHY 793 * values split into two registers with the lower 8 bits in the low register and 794 * the upper 32 bits in the high register, false otherwise. 795 */ 796 static bool ice_is_40b_phy_reg_eth56g(u16 low_addr, u16 *high_addr) 797 { 798 switch (low_addr) { 799 case PHY_REG_TIMETUS_L: 800 *high_addr = PHY_REG_TIMETUS_U; 801 return true; 802 case PHY_PCS_REF_TUS_L: 803 *high_addr = PHY_PCS_REF_TUS_U; 804 return true; 805 case PHY_PCS_REF_INC_L: 806 *high_addr = PHY_PCS_REF_INC_U; 807 return true; 808 default: 809 return false; 810 } 811 } 812 813 /** 814 * ice_read_64b_phy_reg_eth56g - Read a 64bit value from PHY registers 815 * @hw: pointer to the HW struct 816 * @port: PHY port to read from 817 * @low_addr: offset of the lower register to read from 818 * @val: on return, the contents of the 64bit value from the PHY registers 819 * @res_type: resource type 820 * 821 * Check if the caller has specified a known 40 bit register offset and read 822 * the two registers associated with a 40bit value and return it in the val 823 * pointer. 824 * 825 * Return: 826 * * %0 - success 827 * * %EINVAL - not a 64 bit register 828 * * %other - failed to read from PHY 829 */ 830 static int ice_read_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, 831 u64 *val, enum eth56g_res_type res_type) 832 { 833 u16 high_addr; 834 u32 lo, hi; 835 int err; 836 837 if (!ice_is_64b_phy_reg_eth56g(low_addr, &high_addr)) 838 return -EINVAL; 839 840 err = ice_read_port_eth56g(hw, port, low_addr, &lo, res_type); 841 if (err) { 842 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register %#08x\n, err %d", 843 low_addr, err); 844 return err; 845 } 846 847 err = ice_read_port_eth56g(hw, port, high_addr, &hi, res_type); 848 if (err) { 849 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register %#08x\n, err %d", 850 high_addr, err); 851 return err; 852 } 853 854 *val = ((u64)hi << 32) | lo; 855 856 return 0; 857 } 858 859 /** 860 * ice_read_64b_ptp_reg_eth56g - Read a 64bit value from PHY registers 861 * @hw: pointer to the HW struct 862 * @port: PHY port to read from 863 * @low_addr: offset of the lower register to read from 864 * @val: on return, the contents of the 64bit value from the PHY registers 865 * 866 * Check if the caller has specified a known 40 bit register offset and read 867 * the two registers associated with a 40bit value and return it in the val 868 * pointer. 869 * 870 * Return: 871 * * %0 - success 872 * * %EINVAL - not a 64 bit register 873 * * %other - failed to read from PHY 874 */ 875 static int ice_read_64b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, 876 u64 *val) 877 { 878 return ice_read_64b_phy_reg_eth56g(hw, port, low_addr, val, 879 ETH56G_PHY_REG_PTP); 880 } 881 882 /** 883 * ice_write_40b_phy_reg_eth56g - Write a 40b value to the PHY 884 * @hw: pointer to the HW struct 885 * @port: port to write to 886 * @low_addr: offset of the low register 887 * @val: 40b value to write 888 * @res_type: resource type 889 * 890 * Check if the caller has specified a known 40 bit register offset and write 891 * provided 40b value to the two associated registers by splitting it up into 892 * two chunks, the lower 8 bits and the upper 32 bits. 893 * 894 * Return: 895 * * %0 - success 896 * * %EINVAL - not a 40 bit register 897 * * %other - failed to write to PHY 898 */ 899 static int ice_write_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port, 900 u16 low_addr, u64 val, 901 enum eth56g_res_type res_type) 902 { 903 u16 high_addr; 904 u32 lo, hi; 905 int err; 906 907 if (!ice_is_40b_phy_reg_eth56g(low_addr, &high_addr)) 908 return -EINVAL; 909 910 lo = FIELD_GET(P_REG_40B_LOW_M, val); 911 hi = (u32)(val >> P_REG_40B_HIGH_S); 912 913 err = ice_write_port_eth56g(hw, port, low_addr, lo, res_type); 914 if (err) { 915 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 916 low_addr, err); 917 return err; 918 } 919 920 err = ice_write_port_eth56g(hw, port, high_addr, hi, res_type); 921 if (err) { 922 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 923 high_addr, err); 924 return err; 925 } 926 927 return 0; 928 } 929 930 /** 931 * ice_write_40b_ptp_reg_eth56g - Write a 40b value to the PHY 932 * @hw: pointer to the HW struct 933 * @port: port to write to 934 * @low_addr: offset of the low register 935 * @val: 40b value to write 936 * 937 * Check if the caller has specified a known 40 bit register offset and write 938 * provided 40b value to the two associated registers by splitting it up into 939 * two chunks, the lower 8 bits and the upper 32 bits. 940 * 941 * Return: 942 * * %0 - success 943 * * %EINVAL - not a 40 bit register 944 * * %other - failed to write to PHY 945 */ 946 static int ice_write_40b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, 947 u16 low_addr, u64 val) 948 { 949 return ice_write_40b_phy_reg_eth56g(hw, port, low_addr, val, 950 ETH56G_PHY_REG_PTP); 951 } 952 953 /** 954 * ice_write_64b_phy_reg_eth56g - Write a 64bit value to PHY registers 955 * @hw: pointer to the HW struct 956 * @port: PHY port to read from 957 * @low_addr: offset of the lower register to read from 958 * @val: the contents of the 64bit value to write to PHY 959 * @res_type: resource type 960 * 961 * Check if the caller has specified a known 64 bit register offset and write 962 * the 64bit value to the two associated 32bit PHY registers. 963 * 964 * Return: 965 * * %0 - success 966 * * %EINVAL - not a 64 bit register 967 * * %other - failed to write to PHY 968 */ 969 static int ice_write_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, 970 u16 low_addr, u64 val, 971 enum eth56g_res_type res_type) 972 { 973 u16 high_addr; 974 u32 lo, hi; 975 int err; 976 977 if (!ice_is_64b_phy_reg_eth56g(low_addr, &high_addr)) 978 return -EINVAL; 979 980 lo = lower_32_bits(val); 981 hi = upper_32_bits(val); 982 983 err = ice_write_port_eth56g(hw, port, low_addr, lo, res_type); 984 if (err) { 985 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 986 low_addr, err); 987 return err; 988 } 989 990 err = ice_write_port_eth56g(hw, port, high_addr, hi, res_type); 991 if (err) { 992 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 993 high_addr, err); 994 return err; 995 } 996 997 return 0; 998 } 999 1000 /** 1001 * ice_write_64b_ptp_reg_eth56g - Write a 64bit value to PHY registers 1002 * @hw: pointer to the HW struct 1003 * @port: PHY port to read from 1004 * @low_addr: offset of the lower register to read from 1005 * @val: the contents of the 64bit value to write to PHY 1006 * 1007 * Check if the caller has specified a known 64 bit register offset and write 1008 * the 64bit value to the two associated 32bit PHY registers. 1009 * 1010 * Return: 1011 * * %0 - success 1012 * * %EINVAL - not a 64 bit register 1013 * * %other - failed to write to PHY 1014 */ 1015 static int ice_write_64b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, 1016 u16 low_addr, u64 val) 1017 { 1018 return ice_write_64b_phy_reg_eth56g(hw, port, low_addr, val, 1019 ETH56G_PHY_REG_PTP); 1020 } 1021 1022 /** 1023 * ice_read_ptp_tstamp_eth56g - Read a PHY timestamp out of the port memory 1024 * @hw: pointer to the HW struct 1025 * @port: the port to read from 1026 * @idx: the timestamp index to read 1027 * @tstamp: on return, the 40bit timestamp value 1028 * 1029 * Read a 40bit timestamp value out of the two associated entries in the 1030 * port memory block of the internal PHYs of the 56G devices. 1031 * 1032 * Return: 1033 * * %0 - success 1034 * * %other - failed to read from PHY 1035 */ 1036 static int ice_read_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx, 1037 u64 *tstamp) 1038 { 1039 u16 lo_addr, hi_addr; 1040 u32 lo, hi; 1041 int err; 1042 1043 lo_addr = (u16)PHY_TSTAMP_L(idx); 1044 hi_addr = (u16)PHY_TSTAMP_U(idx); 1045 1046 err = ice_read_port_mem_eth56g(hw, port, lo_addr, &lo); 1047 if (err) { 1048 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 1049 err); 1050 return err; 1051 } 1052 1053 err = ice_read_port_mem_eth56g(hw, port, hi_addr, &hi); 1054 if (err) { 1055 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 1056 err); 1057 return err; 1058 } 1059 1060 /* For 56G based internal PHYs, the timestamp is reported with the 1061 * lower 8 bits in the low register, and the upper 32 bits in the high 1062 * register. 1063 */ 1064 *tstamp = FIELD_PREP(PHY_40B_HIGH_M, hi) | 1065 FIELD_PREP(PHY_40B_LOW_M, lo); 1066 return 0; 1067 } 1068 1069 /** 1070 * ice_clear_ptp_tstamp_eth56g - Clear a timestamp from the quad block 1071 * @hw: pointer to the HW struct 1072 * @port: the quad to read from 1073 * @idx: the timestamp index to reset 1074 * 1075 * Read and then forcibly clear the timestamp index to ensure the valid bit is 1076 * cleared and the timestamp status bit is reset in the PHY port memory of 1077 * internal PHYs of the 56G devices. 1078 * 1079 * To directly clear the contents of the timestamp block entirely, discarding 1080 * all timestamp data at once, software should instead use 1081 * ice_ptp_reset_ts_memory_quad_eth56g(). 1082 * 1083 * This function should only be called on an idx whose bit is set according to 1084 * ice_get_phy_tx_tstamp_ready(). 1085 * 1086 * Return: 1087 * * %0 - success 1088 * * %other - failed to write to PHY 1089 */ 1090 static int ice_clear_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx) 1091 { 1092 u64 unused_tstamp; 1093 u16 lo_addr; 1094 int err; 1095 1096 /* Read the timestamp register to ensure the timestamp status bit is 1097 * cleared. 1098 */ 1099 err = ice_read_ptp_tstamp_eth56g(hw, port, idx, &unused_tstamp); 1100 if (err) { 1101 ice_debug(hw, ICE_DBG_PTP, "Failed to read the PHY timestamp register for port %u, idx %u, err %d\n", 1102 port, idx, err); 1103 } 1104 1105 lo_addr = (u16)PHY_TSTAMP_L(idx); 1106 1107 err = ice_write_port_mem_eth56g(hw, port, lo_addr, 0); 1108 if (err) { 1109 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for port %u, idx %u, err %d\n", 1110 port, idx, err); 1111 return err; 1112 } 1113 1114 return 0; 1115 } 1116 1117 /** 1118 * ice_ptp_reset_ts_memory_eth56g - Clear all timestamps from the port block 1119 * @hw: pointer to the HW struct 1120 */ 1121 static void ice_ptp_reset_ts_memory_eth56g(struct ice_hw *hw) 1122 { 1123 unsigned int port; 1124 1125 for (port = 0; port < hw->ptp.num_lports; port++) { 1126 ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L, 1127 0); 1128 ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_U, 1129 0); 1130 } 1131 } 1132 1133 /** 1134 * ice_ptp_prep_port_time_eth56g - Prepare one PHY port with initial time 1135 * @hw: pointer to the HW struct 1136 * @port: port number 1137 * @time: time to initialize the PHY port clocks to 1138 * 1139 * Write a new initial time value into registers of a specific PHY port. 1140 * 1141 * Return: 1142 * * %0 - success 1143 * * %other - failed to write to PHY 1144 */ 1145 static int ice_ptp_prep_port_time_eth56g(struct ice_hw *hw, u8 port, 1146 u64 time) 1147 { 1148 int err; 1149 1150 /* Tx case */ 1151 err = ice_write_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_L, 1152 time); 1153 if (err) 1154 return err; 1155 1156 /* Rx case */ 1157 return ice_write_64b_ptp_reg_eth56g(hw, port, 1158 PHY_REG_RX_TIMER_INC_PRE_L, time); 1159 } 1160 1161 /** 1162 * ice_ptp_prep_phy_time_eth56g - Prepare PHY port with initial time 1163 * @hw: pointer to the HW struct 1164 * @time: Time to initialize the PHY port clocks to 1165 * 1166 * Program the PHY port registers with a new initial time value. The port 1167 * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync 1168 * command. The time value is the upper 32 bits of the PHY timer, usually in 1169 * units of nominal nanoseconds. 1170 * 1171 * Return: 1172 * * %0 - success 1173 * * %other - failed to write to PHY 1174 */ 1175 static int ice_ptp_prep_phy_time_eth56g(struct ice_hw *hw, u32 time) 1176 { 1177 u64 phy_time; 1178 u8 port; 1179 1180 /* The time represents the upper 32 bits of the PHY timer, so we need 1181 * to shift to account for this when programming. 1182 */ 1183 phy_time = (u64)time << 32; 1184 1185 for (port = 0; port < hw->ptp.num_lports; port++) { 1186 int err; 1187 1188 err = ice_ptp_prep_port_time_eth56g(hw, port, phy_time); 1189 if (err) { 1190 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n", 1191 port, err); 1192 return err; 1193 } 1194 } 1195 1196 return 0; 1197 } 1198 1199 /** 1200 * ice_ptp_prep_port_adj_eth56g - Prepare a single port for time adjust 1201 * @hw: pointer to HW struct 1202 * @port: Port number to be programmed 1203 * @time: time in cycles to adjust the port clocks 1204 * 1205 * Program the port for an atomic adjustment by writing the Tx and Rx timer 1206 * registers. The atomic adjustment won't be completed until the driver issues 1207 * an ICE_PTP_ADJ_TIME command. 1208 * 1209 * Note that time is not in units of nanoseconds. It is in clock time 1210 * including the lower sub-nanosecond portion of the port timer. 1211 * 1212 * Negative adjustments are supported using 2s complement arithmetic. 1213 * 1214 * Return: 1215 * * %0 - success 1216 * * %other - failed to write to PHY 1217 */ 1218 static int ice_ptp_prep_port_adj_eth56g(struct ice_hw *hw, u8 port, s64 time) 1219 { 1220 u32 l_time, u_time; 1221 int err; 1222 1223 l_time = lower_32_bits(time); 1224 u_time = upper_32_bits(time); 1225 1226 /* Tx case */ 1227 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_L, 1228 l_time); 1229 if (err) 1230 goto exit_err; 1231 1232 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_U, 1233 u_time); 1234 if (err) 1235 goto exit_err; 1236 1237 /* Rx case */ 1238 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TIMER_INC_PRE_L, 1239 l_time); 1240 if (err) 1241 goto exit_err; 1242 1243 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TIMER_INC_PRE_U, 1244 u_time); 1245 if (err) 1246 goto exit_err; 1247 1248 return 0; 1249 1250 exit_err: 1251 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n", 1252 port, err); 1253 return err; 1254 } 1255 1256 /** 1257 * ice_ptp_prep_phy_adj_eth56g - Prep PHY ports for a time adjustment 1258 * @hw: pointer to HW struct 1259 * @adj: adjustment in nanoseconds 1260 * 1261 * Prepare the PHY ports for an atomic time adjustment by programming the PHY 1262 * Tx and Rx port registers. The actual adjustment is completed by issuing an 1263 * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command. 1264 * 1265 * Return: 1266 * * %0 - success 1267 * * %other - failed to write to PHY 1268 */ 1269 static int ice_ptp_prep_phy_adj_eth56g(struct ice_hw *hw, s32 adj) 1270 { 1271 s64 cycles; 1272 u8 port; 1273 1274 /* The port clock supports adjustment of the sub-nanosecond portion of 1275 * the clock (lowest 32 bits). We shift the provided adjustment in 1276 * nanoseconds by 32 to calculate the appropriate adjustment to program 1277 * into the PHY ports. 1278 */ 1279 cycles = (s64)adj << 32; 1280 1281 for (port = 0; port < hw->ptp.num_lports; port++) { 1282 int err; 1283 1284 err = ice_ptp_prep_port_adj_eth56g(hw, port, cycles); 1285 if (err) 1286 return err; 1287 } 1288 1289 return 0; 1290 } 1291 1292 /** 1293 * ice_ptp_prep_phy_incval_eth56g - Prepare PHY ports for time adjustment 1294 * @hw: pointer to HW struct 1295 * @incval: new increment value to prepare 1296 * 1297 * Prepare each of the PHY ports for a new increment value by programming the 1298 * port's TIMETUS registers. The new increment value will be updated after 1299 * issuing an ICE_PTP_INIT_INCVAL command. 1300 * 1301 * Return: 1302 * * %0 - success 1303 * * %other - failed to write to PHY 1304 */ 1305 static int ice_ptp_prep_phy_incval_eth56g(struct ice_hw *hw, u64 incval) 1306 { 1307 u8 port; 1308 1309 for (port = 0; port < hw->ptp.num_lports; port++) { 1310 int err; 1311 1312 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_REG_TIMETUS_L, 1313 incval); 1314 if (err) { 1315 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n", 1316 port, err); 1317 return err; 1318 } 1319 } 1320 1321 return 0; 1322 } 1323 1324 /** 1325 * ice_ptp_read_port_capture_eth56g - Read a port's local time capture 1326 * @hw: pointer to HW struct 1327 * @port: Port number to read 1328 * @tx_ts: on return, the Tx port time capture 1329 * @rx_ts: on return, the Rx port time capture 1330 * 1331 * Read the port's Tx and Rx local time capture values. 1332 * 1333 * Return: 1334 * * %0 - success 1335 * * %other - failed to read from PHY 1336 */ 1337 static int ice_ptp_read_port_capture_eth56g(struct ice_hw *hw, u8 port, 1338 u64 *tx_ts, u64 *rx_ts) 1339 { 1340 int err; 1341 1342 /* Tx case */ 1343 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_CAPTURE_L, 1344 tx_ts); 1345 if (err) { 1346 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n", 1347 err); 1348 return err; 1349 } 1350 1351 ice_debug(hw, ICE_DBG_PTP, "tx_init = %#016llx\n", *tx_ts); 1352 1353 /* Rx case */ 1354 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_RX_CAPTURE_L, 1355 rx_ts); 1356 if (err) { 1357 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n", 1358 err); 1359 return err; 1360 } 1361 1362 ice_debug(hw, ICE_DBG_PTP, "rx_init = %#016llx\n", *rx_ts); 1363 1364 return 0; 1365 } 1366 1367 /** 1368 * ice_ptp_write_port_cmd_eth56g - Prepare a single PHY port for a timer command 1369 * @hw: pointer to HW struct 1370 * @port: Port to which cmd has to be sent 1371 * @cmd: Command to be sent to the port 1372 * 1373 * Prepare the requested port for an upcoming timer sync command. 1374 * 1375 * Return: 1376 * * %0 - success 1377 * * %other - failed to write to PHY 1378 */ 1379 static int ice_ptp_write_port_cmd_eth56g(struct ice_hw *hw, u8 port, 1380 enum ice_ptp_tmr_cmd cmd) 1381 { 1382 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 1383 int err; 1384 1385 /* Tx case */ 1386 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TMR_CMD, val); 1387 if (err) { 1388 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n", 1389 err); 1390 return err; 1391 } 1392 1393 /* Rx case */ 1394 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TMR_CMD, val); 1395 if (err) { 1396 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n", 1397 err); 1398 return err; 1399 } 1400 1401 return 0; 1402 } 1403 1404 /** 1405 * ice_phy_get_speed_eth56g - Get link speed based on PHY link type 1406 * @li: pointer to link information struct 1407 * 1408 * Return: simplified ETH56G PHY speed 1409 */ 1410 static enum ice_eth56g_link_spd 1411 ice_phy_get_speed_eth56g(struct ice_link_status *li) 1412 { 1413 u16 speed = ice_get_link_speed_based_on_phy_type(li->phy_type_low, 1414 li->phy_type_high); 1415 1416 switch (speed) { 1417 case ICE_AQ_LINK_SPEED_1000MB: 1418 return ICE_ETH56G_LNK_SPD_1G; 1419 case ICE_AQ_LINK_SPEED_2500MB: 1420 return ICE_ETH56G_LNK_SPD_2_5G; 1421 case ICE_AQ_LINK_SPEED_10GB: 1422 return ICE_ETH56G_LNK_SPD_10G; 1423 case ICE_AQ_LINK_SPEED_25GB: 1424 return ICE_ETH56G_LNK_SPD_25G; 1425 case ICE_AQ_LINK_SPEED_40GB: 1426 return ICE_ETH56G_LNK_SPD_40G; 1427 case ICE_AQ_LINK_SPEED_50GB: 1428 switch (li->phy_type_low) { 1429 case ICE_PHY_TYPE_LOW_50GBASE_SR: 1430 case ICE_PHY_TYPE_LOW_50GBASE_FR: 1431 case ICE_PHY_TYPE_LOW_50GBASE_LR: 1432 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 1433 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 1434 case ICE_PHY_TYPE_LOW_50G_AUI1: 1435 return ICE_ETH56G_LNK_SPD_50G; 1436 default: 1437 return ICE_ETH56G_LNK_SPD_50G2; 1438 } 1439 case ICE_AQ_LINK_SPEED_100GB: 1440 if (li->phy_type_high || 1441 li->phy_type_low == ICE_PHY_TYPE_LOW_100GBASE_SR2) 1442 return ICE_ETH56G_LNK_SPD_100G2; 1443 else 1444 return ICE_ETH56G_LNK_SPD_100G; 1445 default: 1446 return ICE_ETH56G_LNK_SPD_1G; 1447 } 1448 } 1449 1450 /** 1451 * ice_phy_cfg_parpcs_eth56g - Configure TUs per PAR/PCS clock cycle 1452 * @hw: pointer to the HW struct 1453 * @port: port to configure 1454 * 1455 * Configure the number of TUs for the PAR and PCS clocks used as part of the 1456 * timestamp calibration process. 1457 * 1458 * Return: 1459 * * %0 - success 1460 * * %other - PHY read/write failed 1461 */ 1462 static int ice_phy_cfg_parpcs_eth56g(struct ice_hw *hw, u8 port) 1463 { 1464 u32 val; 1465 int err; 1466 1467 err = ice_write_xpcs_reg_eth56g(hw, port, PHY_VENDOR_TXLANE_THRESH, 1468 ICE_ETH56G_NOMINAL_THRESH4); 1469 if (err) { 1470 ice_debug(hw, ICE_DBG_PTP, "Failed to read VENDOR_TXLANE_THRESH, status: %d", 1471 err); 1472 return err; 1473 } 1474 1475 switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) { 1476 case ICE_ETH56G_LNK_SPD_1G: 1477 case ICE_ETH56G_LNK_SPD_2_5G: 1478 err = ice_read_quad_ptp_reg_eth56g(hw, port, 1479 PHY_GPCS_CONFIG_REG0, &val); 1480 if (err) { 1481 ice_debug(hw, ICE_DBG_PTP, "Failed to read PHY_GPCS_CONFIG_REG0, status: %d", 1482 err); 1483 return err; 1484 } 1485 1486 val &= ~PHY_GPCS_CONFIG_REG0_TX_THR_M; 1487 val |= FIELD_PREP(PHY_GPCS_CONFIG_REG0_TX_THR_M, 1488 ICE_ETH56G_NOMINAL_TX_THRESH); 1489 1490 err = ice_write_quad_ptp_reg_eth56g(hw, port, 1491 PHY_GPCS_CONFIG_REG0, val); 1492 if (err) { 1493 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_GPCS_CONFIG_REG0, status: %d", 1494 err); 1495 return err; 1496 } 1497 break; 1498 default: 1499 break; 1500 } 1501 1502 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_PCS_REF_TUS_L, 1503 ICE_ETH56G_NOMINAL_PCS_REF_TUS); 1504 if (err) { 1505 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_PCS_REF_TUS, status: %d", 1506 err); 1507 return err; 1508 } 1509 1510 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_PCS_REF_INC_L, 1511 ICE_ETH56G_NOMINAL_PCS_REF_INC); 1512 if (err) { 1513 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_PCS_REF_INC, status: %d", 1514 err); 1515 return err; 1516 } 1517 1518 return 0; 1519 } 1520 1521 /** 1522 * ice_phy_cfg_ptp_1step_eth56g - Configure 1-step PTP settings 1523 * @hw: Pointer to the HW struct 1524 * @port: Port to configure 1525 * 1526 * Return: 1527 * * %0 - success 1528 * * %other - PHY read/write failed 1529 */ 1530 int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port) 1531 { 1532 u8 quad_lane = port % ICE_PORTS_PER_QUAD; 1533 u32 addr, val, peer_delay; 1534 bool enable, sfd_ena; 1535 int err; 1536 1537 enable = hw->ptp.phy.eth56g.onestep_ena; 1538 peer_delay = hw->ptp.phy.eth56g.peer_delay; 1539 sfd_ena = hw->ptp.phy.eth56g.sfd_ena; 1540 1541 addr = PHY_PTP_1STEP_CONFIG; 1542 err = ice_read_quad_ptp_reg_eth56g(hw, port, addr, &val); 1543 if (err) 1544 return err; 1545 1546 if (enable) 1547 val |= BIT(quad_lane); 1548 else 1549 val &= ~BIT(quad_lane); 1550 1551 val &= ~(PHY_PTP_1STEP_T1S_UP64_M | PHY_PTP_1STEP_T1S_DELTA_M); 1552 1553 err = ice_write_quad_ptp_reg_eth56g(hw, port, addr, val); 1554 if (err) 1555 return err; 1556 1557 addr = PHY_PTP_1STEP_PEER_DELAY(quad_lane); 1558 val = FIELD_PREP(PHY_PTP_1STEP_PD_DELAY_M, peer_delay); 1559 if (peer_delay) 1560 val |= PHY_PTP_1STEP_PD_ADD_PD_M; 1561 val |= PHY_PTP_1STEP_PD_DLY_V_M; 1562 err = ice_write_quad_ptp_reg_eth56g(hw, port, addr, val); 1563 if (err) 1564 return err; 1565 1566 val &= ~PHY_PTP_1STEP_PD_DLY_V_M; 1567 err = ice_write_quad_ptp_reg_eth56g(hw, port, addr, val); 1568 if (err) 1569 return err; 1570 1571 addr = PHY_MAC_XIF_MODE; 1572 err = ice_read_mac_reg_eth56g(hw, port, addr, &val); 1573 if (err) 1574 return err; 1575 1576 val &= ~(PHY_MAC_XIF_1STEP_ENA_M | PHY_MAC_XIF_TS_BIN_MODE_M | 1577 PHY_MAC_XIF_TS_SFD_ENA_M | PHY_MAC_XIF_GMII_TS_SEL_M); 1578 1579 switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) { 1580 case ICE_ETH56G_LNK_SPD_1G: 1581 case ICE_ETH56G_LNK_SPD_2_5G: 1582 val |= PHY_MAC_XIF_GMII_TS_SEL_M; 1583 break; 1584 default: 1585 break; 1586 } 1587 1588 val |= FIELD_PREP(PHY_MAC_XIF_1STEP_ENA_M, enable) | 1589 FIELD_PREP(PHY_MAC_XIF_TS_BIN_MODE_M, enable) | 1590 FIELD_PREP(PHY_MAC_XIF_TS_SFD_ENA_M, sfd_ena); 1591 1592 return ice_write_mac_reg_eth56g(hw, port, addr, val); 1593 } 1594 1595 /** 1596 * mul_u32_u32_fx_q9 - Multiply two u32 fixed point Q9 values 1597 * @a: multiplier value 1598 * @b: multiplicand value 1599 * 1600 * Return: result of multiplication 1601 */ 1602 static u32 mul_u32_u32_fx_q9(u32 a, u32 b) 1603 { 1604 return (u32)(((u64)a * b) >> ICE_ETH56G_MAC_CFG_FRAC_W); 1605 } 1606 1607 /** 1608 * add_u32_u32_fx - Add two u32 fixed point values and discard overflow 1609 * @a: first value 1610 * @b: second value 1611 * 1612 * Return: result of addition 1613 */ 1614 static u32 add_u32_u32_fx(u32 a, u32 b) 1615 { 1616 return lower_32_bits(((u64)a + b)); 1617 } 1618 1619 /** 1620 * ice_ptp_calc_bitslip_eth56g - Calculate bitslip value 1621 * @hw: pointer to the HW struct 1622 * @port: port to configure 1623 * @bs: bitslip multiplier 1624 * @fc: FC-FEC enabled 1625 * @rs: RS-FEC enabled 1626 * @spd: link speed 1627 * 1628 * Return: calculated bitslip value 1629 */ 1630 static u32 ice_ptp_calc_bitslip_eth56g(struct ice_hw *hw, u8 port, u32 bs, 1631 bool fc, bool rs, 1632 enum ice_eth56g_link_spd spd) 1633 { 1634 u32 bitslip; 1635 int err; 1636 1637 if (!bs || rs) 1638 return 0; 1639 1640 if (spd == ICE_ETH56G_LNK_SPD_1G || spd == ICE_ETH56G_LNK_SPD_2_5G) { 1641 err = ice_read_gpcs_reg_eth56g(hw, port, PHY_GPCS_BITSLIP, 1642 &bitslip); 1643 } else { 1644 u8 quad_lane = port % ICE_PORTS_PER_QUAD; 1645 u32 addr; 1646 1647 addr = PHY_REG_SD_BIT_SLIP(quad_lane); 1648 err = ice_read_quad_ptp_reg_eth56g(hw, port, addr, &bitslip); 1649 } 1650 if (err) 1651 return 0; 1652 1653 if (spd == ICE_ETH56G_LNK_SPD_1G && !bitslip) { 1654 /* Bitslip register value of 0 corresponds to 10 so substitute 1655 * it for calculations 1656 */ 1657 bitslip = 10; 1658 } else if (spd == ICE_ETH56G_LNK_SPD_10G || 1659 spd == ICE_ETH56G_LNK_SPD_25G) { 1660 if (fc) 1661 bitslip = bitslip * 2 + 32; 1662 else 1663 bitslip = (u32)((s32)bitslip * -1 + 20); 1664 } 1665 1666 bitslip <<= ICE_ETH56G_MAC_CFG_FRAC_W; 1667 return mul_u32_u32_fx_q9(bitslip, bs); 1668 } 1669 1670 /** 1671 * ice_ptp_calc_deskew_eth56g - Calculate deskew value 1672 * @hw: pointer to the HW struct 1673 * @port: port to configure 1674 * @ds: deskew multiplier 1675 * @rs: RS-FEC enabled 1676 * @spd: link speed 1677 * 1678 * Return: calculated deskew value 1679 */ 1680 static u32 ice_ptp_calc_deskew_eth56g(struct ice_hw *hw, u8 port, u32 ds, 1681 bool rs, enum ice_eth56g_link_spd spd) 1682 { 1683 u32 deskew_i, deskew_f; 1684 int err; 1685 1686 if (!ds) 1687 return 0; 1688 1689 read_poll_timeout(ice_read_ptp_reg_eth56g, err, 1690 FIELD_GET(PHY_REG_DESKEW_0_VALID, deskew_i), 500, 1691 50 * USEC_PER_MSEC, false, hw, port, PHY_REG_DESKEW_0, 1692 &deskew_i); 1693 if (err) 1694 return err; 1695 1696 deskew_f = FIELD_GET(PHY_REG_DESKEW_0_RLEVEL_FRAC, deskew_i); 1697 deskew_i = FIELD_GET(PHY_REG_DESKEW_0_RLEVEL, deskew_i); 1698 1699 if (rs && spd == ICE_ETH56G_LNK_SPD_50G2) 1700 ds = 0x633; /* 3.1 */ 1701 else if (rs && spd == ICE_ETH56G_LNK_SPD_100G) 1702 ds = 0x31b; /* 1.552 */ 1703 1704 deskew_i = FIELD_PREP(ICE_ETH56G_MAC_CFG_RX_OFFSET_INT, deskew_i); 1705 /* Shift 3 fractional bits to the end of the integer part */ 1706 deskew_f <<= ICE_ETH56G_MAC_CFG_FRAC_W - PHY_REG_DESKEW_0_RLEVEL_FRAC_W; 1707 return mul_u32_u32_fx_q9(deskew_i | deskew_f, ds); 1708 } 1709 1710 /** 1711 * ice_phy_set_offsets_eth56g - Set Tx/Rx offset values 1712 * @hw: pointer to the HW struct 1713 * @port: port to configure 1714 * @spd: link speed 1715 * @cfg: structure to store output values 1716 * @fc: FC-FEC enabled 1717 * @rs: RS-FEC enabled 1718 * 1719 * Return: 1720 * * %0 - success 1721 * * %other - failed to write to PHY 1722 */ 1723 static int ice_phy_set_offsets_eth56g(struct ice_hw *hw, u8 port, 1724 enum ice_eth56g_link_spd spd, 1725 const struct ice_eth56g_mac_reg_cfg *cfg, 1726 bool fc, bool rs) 1727 { 1728 u32 rx_offset, tx_offset, bs_ds; 1729 bool onestep, sfd; 1730 1731 onestep = hw->ptp.phy.eth56g.onestep_ena; 1732 sfd = hw->ptp.phy.eth56g.sfd_ena; 1733 bs_ds = cfg->rx_offset.bs_ds; 1734 1735 if (fc) 1736 rx_offset = cfg->rx_offset.fc; 1737 else if (rs) 1738 rx_offset = cfg->rx_offset.rs; 1739 else 1740 rx_offset = cfg->rx_offset.no_fec; 1741 1742 rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.serdes); 1743 if (sfd) 1744 rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.sfd); 1745 1746 if (spd < ICE_ETH56G_LNK_SPD_40G) 1747 bs_ds = ice_ptp_calc_bitslip_eth56g(hw, port, bs_ds, fc, rs, 1748 spd); 1749 else 1750 bs_ds = ice_ptp_calc_deskew_eth56g(hw, port, bs_ds, rs, spd); 1751 rx_offset = add_u32_u32_fx(rx_offset, bs_ds); 1752 rx_offset &= ICE_ETH56G_MAC_CFG_RX_OFFSET_INT | 1753 ICE_ETH56G_MAC_CFG_RX_OFFSET_FRAC; 1754 1755 if (fc) 1756 tx_offset = cfg->tx_offset.fc; 1757 else if (rs) 1758 tx_offset = cfg->tx_offset.rs; 1759 else 1760 tx_offset = cfg->tx_offset.no_fec; 1761 tx_offset += cfg->tx_offset.serdes + cfg->tx_offset.sfd * sfd + 1762 cfg->tx_offset.onestep * onestep; 1763 1764 ice_write_mac_reg_eth56g(hw, port, PHY_MAC_RX_OFFSET, rx_offset); 1765 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TX_OFFSET, tx_offset); 1766 } 1767 1768 /** 1769 * ice_phy_cfg_mac_eth56g - Configure MAC for PTP 1770 * @hw: Pointer to the HW struct 1771 * @port: Port to configure 1772 * 1773 * Return: 1774 * * %0 - success 1775 * * %other - failed to write to PHY 1776 */ 1777 static int ice_phy_cfg_mac_eth56g(struct ice_hw *hw, u8 port) 1778 { 1779 const struct ice_eth56g_mac_reg_cfg *cfg; 1780 enum ice_eth56g_link_spd spd; 1781 struct ice_link_status *li; 1782 bool fc = false; 1783 bool rs = false; 1784 bool onestep; 1785 u32 val; 1786 int err; 1787 1788 onestep = hw->ptp.phy.eth56g.onestep_ena; 1789 li = &hw->port_info->phy.link_info; 1790 spd = ice_phy_get_speed_eth56g(li); 1791 if (!!(li->an_info & ICE_AQ_FEC_EN)) { 1792 if (spd == ICE_ETH56G_LNK_SPD_10G) { 1793 fc = true; 1794 } else { 1795 fc = !!(li->fec_info & ICE_AQ_LINK_25G_KR_FEC_EN); 1796 rs = !!(li->fec_info & ~ICE_AQ_LINK_25G_KR_FEC_EN); 1797 } 1798 } 1799 cfg = ð56g_mac_cfg[spd]; 1800 1801 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_RX_MODULO, 0); 1802 if (err) 1803 return err; 1804 1805 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TX_MODULO, 0); 1806 if (err) 1807 return err; 1808 1809 val = FIELD_PREP(PHY_MAC_TSU_CFG_TX_MODE_M, 1810 cfg->tx_mode.def + rs * cfg->tx_mode.rs) | 1811 FIELD_PREP(PHY_MAC_TSU_CFG_TX_MII_MK_DLY_M, cfg->tx_mk_dly) | 1812 FIELD_PREP(PHY_MAC_TSU_CFG_TX_MII_CW_DLY_M, 1813 cfg->tx_cw_dly.def + 1814 onestep * cfg->tx_cw_dly.onestep) | 1815 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MODE_M, 1816 cfg->rx_mode.def + rs * cfg->rx_mode.rs) | 1817 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MII_MK_DLY_M, 1818 cfg->rx_mk_dly.def + rs * cfg->rx_mk_dly.rs) | 1819 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MII_CW_DLY_M, 1820 cfg->rx_cw_dly.def + rs * cfg->rx_cw_dly.rs) | 1821 FIELD_PREP(PHY_MAC_TSU_CFG_BLKS_PER_CLK_M, cfg->blks_per_clk); 1822 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TSU_CONFIG, val); 1823 if (err) 1824 return err; 1825 1826 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_BLOCKTIME, 1827 cfg->blktime); 1828 if (err) 1829 return err; 1830 1831 err = ice_phy_set_offsets_eth56g(hw, port, spd, cfg, fc, rs); 1832 if (err) 1833 return err; 1834 1835 if (spd == ICE_ETH56G_LNK_SPD_25G && !rs) 1836 val = 0; 1837 else 1838 val = cfg->mktime; 1839 1840 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_MARKERTIME, val); 1841 } 1842 1843 /** 1844 * ice_phy_cfg_intr_eth56g - Configure TX timestamp interrupt 1845 * @hw: pointer to the HW struct 1846 * @port: the timestamp port 1847 * @ena: enable or disable interrupt 1848 * @threshold: interrupt threshold 1849 * 1850 * Configure TX timestamp interrupt for the specified port 1851 * 1852 * Return: 1853 * * %0 - success 1854 * * %other - PHY read/write failed 1855 */ 1856 int ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold) 1857 { 1858 int err; 1859 u32 val; 1860 1861 err = ice_read_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, &val); 1862 if (err) 1863 return err; 1864 1865 if (ena) { 1866 val |= PHY_TS_INT_CONFIG_ENA_M; 1867 val &= ~PHY_TS_INT_CONFIG_THRESHOLD_M; 1868 val |= FIELD_PREP(PHY_TS_INT_CONFIG_THRESHOLD_M, threshold); 1869 } else { 1870 val &= ~PHY_TS_INT_CONFIG_ENA_M; 1871 } 1872 1873 return ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, val); 1874 } 1875 1876 /** 1877 * ice_read_phy_and_phc_time_eth56g - Simultaneously capture PHC and PHY time 1878 * @hw: pointer to the HW struct 1879 * @port: the PHY port to read 1880 * @phy_time: on return, the 64bit PHY timer value 1881 * @phc_time: on return, the lower 64bits of PHC time 1882 * 1883 * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY 1884 * and PHC timer values. 1885 * 1886 * Return: 1887 * * %0 - success 1888 * * %other - PHY read/write failed 1889 */ 1890 static int ice_read_phy_and_phc_time_eth56g(struct ice_hw *hw, u8 port, 1891 u64 *phy_time, u64 *phc_time) 1892 { 1893 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 1894 u64 tx_time, rx_time; 1895 u32 zo, lo; 1896 u8 tmr_idx; 1897 int err; 1898 1899 tmr_idx = ice_get_ptp_src_clock_index(hw); 1900 1901 /* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */ 1902 ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME); 1903 1904 /* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */ 1905 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME); 1906 if (err) 1907 return err; 1908 1909 /* Issue the sync to start the ICE_PTP_READ_TIME capture */ 1910 ice_ptp_exec_tmr_cmd(hw); 1911 1912 /* Read the captured PHC time from the shadow time registers */ 1913 if (ice_is_primary(hw)) { 1914 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx)); 1915 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx)); 1916 } else { 1917 zo = rd32(ice_get_primary_hw(pf), GLTSYN_SHTIME_0(tmr_idx)); 1918 lo = rd32(ice_get_primary_hw(pf), GLTSYN_SHTIME_L(tmr_idx)); 1919 } 1920 *phc_time = (u64)lo << 32 | zo; 1921 1922 /* Read the captured PHY time from the PHY shadow registers */ 1923 err = ice_ptp_read_port_capture_eth56g(hw, port, &tx_time, &rx_time); 1924 if (err) 1925 return err; 1926 1927 /* If the PHY Tx and Rx timers don't match, log a warning message. 1928 * Note that this should not happen in normal circumstances since the 1929 * driver always programs them together. 1930 */ 1931 if (tx_time != rx_time) 1932 dev_warn(ice_hw_to_dev(hw), "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n", 1933 port, tx_time, rx_time); 1934 1935 *phy_time = tx_time; 1936 1937 return 0; 1938 } 1939 1940 /** 1941 * ice_sync_phy_timer_eth56g - Synchronize the PHY timer with PHC timer 1942 * @hw: pointer to the HW struct 1943 * @port: the PHY port to synchronize 1944 * 1945 * Perform an adjustment to ensure that the PHY and PHC timers are in sync. 1946 * This is done by issuing a ICE_PTP_READ_TIME command which triggers a 1947 * simultaneous read of the PHY timer and PHC timer. Then we use the 1948 * difference to calculate an appropriate 2s complement addition to add 1949 * to the PHY timer in order to ensure it reads the same value as the 1950 * primary PHC timer. 1951 * 1952 * Return: 1953 * * %0 - success 1954 * * %-EBUSY- failed to acquire PTP semaphore 1955 * * %other - PHY read/write failed 1956 */ 1957 static int ice_sync_phy_timer_eth56g(struct ice_hw *hw, u8 port) 1958 { 1959 u64 phc_time, phy_time, difference; 1960 int err; 1961 1962 if (!ice_ptp_lock(hw)) { 1963 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n"); 1964 return -EBUSY; 1965 } 1966 1967 err = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time, &phc_time); 1968 if (err) 1969 goto err_unlock; 1970 1971 /* Calculate the amount required to add to the port time in order for 1972 * it to match the PHC time. 1973 * 1974 * Note that the port adjustment is done using 2s complement 1975 * arithmetic. This is convenient since it means that we can simply 1976 * calculate the difference between the PHC time and the port time, 1977 * and it will be interpreted correctly. 1978 */ 1979 1980 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 1981 difference = phc_time - phy_time; 1982 1983 err = ice_ptp_prep_port_adj_eth56g(hw, port, (s64)difference); 1984 if (err) 1985 goto err_unlock; 1986 1987 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME); 1988 if (err) 1989 goto err_unlock; 1990 1991 /* Issue the sync to activate the time adjustment */ 1992 ice_ptp_exec_tmr_cmd(hw); 1993 1994 /* Re-capture the timer values to flush the command registers and 1995 * verify that the time was properly adjusted. 1996 */ 1997 err = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time, &phc_time); 1998 if (err) 1999 goto err_unlock; 2000 2001 dev_info(ice_hw_to_dev(hw), 2002 "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n", 2003 port, phy_time, phc_time); 2004 2005 err_unlock: 2006 ice_ptp_unlock(hw); 2007 return err; 2008 } 2009 2010 /** 2011 * ice_stop_phy_timer_eth56g - Stop the PHY clock timer 2012 * @hw: pointer to the HW struct 2013 * @port: the PHY port to stop 2014 * @soft_reset: if true, hold the SOFT_RESET bit of PHY_REG_PS 2015 * 2016 * Stop the clock of a PHY port. This must be done as part of the flow to 2017 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 2018 * initialized or when link speed changes. 2019 * 2020 * Return: 2021 * * %0 - success 2022 * * %other - failed to write to PHY 2023 */ 2024 int ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset) 2025 { 2026 int err; 2027 2028 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 0); 2029 if (err) 2030 return err; 2031 2032 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 0); 2033 if (err) 2034 return err; 2035 2036 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port); 2037 2038 return 0; 2039 } 2040 2041 /** 2042 * ice_start_phy_timer_eth56g - Start the PHY clock timer 2043 * @hw: pointer to the HW struct 2044 * @port: the PHY port to start 2045 * 2046 * Start the clock of a PHY port. This must be done as part of the flow to 2047 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 2048 * initialized or when link speed changes. 2049 * 2050 * Return: 2051 * * %0 - success 2052 * * %other - PHY read/write failed 2053 */ 2054 int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port) 2055 { 2056 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 2057 u32 lo, hi; 2058 u64 incval; 2059 u8 tmr_idx; 2060 int err; 2061 2062 tmr_idx = ice_get_ptp_src_clock_index(hw); 2063 2064 err = ice_stop_phy_timer_eth56g(hw, port, false); 2065 if (err) 2066 return err; 2067 2068 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 2069 2070 err = ice_phy_cfg_parpcs_eth56g(hw, port); 2071 if (err) 2072 return err; 2073 2074 err = ice_phy_cfg_ptp_1step_eth56g(hw, port); 2075 if (err) 2076 return err; 2077 2078 err = ice_phy_cfg_mac_eth56g(hw, port); 2079 if (err) 2080 return err; 2081 2082 if (ice_is_primary(hw)) { 2083 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 2084 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 2085 } else { 2086 lo = rd32(ice_get_primary_hw(pf), GLTSYN_INCVAL_L(tmr_idx)); 2087 hi = rd32(ice_get_primary_hw(pf), GLTSYN_INCVAL_H(tmr_idx)); 2088 } 2089 incval = (u64)hi << 32 | lo; 2090 2091 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_REG_TIMETUS_L, incval); 2092 if (err) 2093 return err; 2094 2095 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL); 2096 if (err) 2097 return err; 2098 2099 ice_ptp_exec_tmr_cmd(hw); 2100 2101 err = ice_sync_phy_timer_eth56g(hw, port); 2102 if (err) 2103 return err; 2104 2105 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 1); 2106 if (err) 2107 return err; 2108 2109 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 1); 2110 if (err) 2111 return err; 2112 2113 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port); 2114 2115 return 0; 2116 } 2117 2118 /** 2119 * ice_ptp_init_phc_e825 - Perform E825 specific PHC initialization 2120 * @hw: pointer to HW struct 2121 * 2122 * Perform E825-specific PTP hardware clock initialization steps. 2123 * 2124 * Return: 0 on success, negative error code otherwise. 2125 */ 2126 static int ice_ptp_init_phc_e825(struct ice_hw *hw) 2127 { 2128 /* Initialize the Clock Generation Unit */ 2129 return ice_tspll_init(hw); 2130 } 2131 2132 /** 2133 * ice_ptp_read_tx_hwtstamp_status_eth56g - Get TX timestamp status 2134 * @hw: pointer to the HW struct 2135 * @ts_status: the timestamp mask pointer 2136 * 2137 * Read the PHY Tx timestamp status mask indicating which ports have Tx 2138 * timestamps available. 2139 * 2140 * Return: 2141 * * %0 - success 2142 * * %other - failed to read from PHY 2143 */ 2144 int ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status) 2145 { 2146 const struct ice_eth56g_params *params = &hw->ptp.phy.eth56g; 2147 u8 phy, mask; 2148 u32 status; 2149 2150 mask = (1 << hw->ptp.ports_per_phy) - 1; 2151 *ts_status = 0; 2152 2153 for (phy = 0; phy < params->num_phys; phy++) { 2154 int err; 2155 2156 err = ice_read_phy_eth56g(hw, phy, PHY_PTP_INT_STATUS, &status); 2157 if (err) 2158 return err; 2159 2160 *ts_status |= (status & mask) << (phy * hw->ptp.ports_per_phy); 2161 } 2162 2163 ice_debug(hw, ICE_DBG_PTP, "PHY interrupt err: %x\n", *ts_status); 2164 2165 return 0; 2166 } 2167 2168 /** 2169 * ice_get_phy_tx_tstamp_ready_eth56g - Read the Tx memory status register 2170 * @hw: pointer to the HW struct 2171 * @port: the PHY port to read from 2172 * @tstamp_ready: contents of the Tx memory status register 2173 * 2174 * Read the PHY_REG_TX_MEMORY_STATUS register indicating which timestamps in 2175 * the PHY are ready. A set bit means the corresponding timestamp is valid and 2176 * ready to be captured from the PHY timestamp block. 2177 * 2178 * Return: 2179 * * %0 - success 2180 * * %other - failed to read from PHY 2181 */ 2182 static int ice_get_phy_tx_tstamp_ready_eth56g(struct ice_hw *hw, u8 port, 2183 u64 *tstamp_ready) 2184 { 2185 int err; 2186 2187 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L, 2188 tstamp_ready); 2189 if (err) { 2190 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS for port %u, err %d\n", 2191 port, err); 2192 return err; 2193 } 2194 2195 return 0; 2196 } 2197 2198 /** 2199 * ice_ptp_init_phy_e825 - initialize PHY parameters 2200 * @hw: pointer to the HW struct 2201 */ 2202 static void ice_ptp_init_phy_e825(struct ice_hw *hw) 2203 { 2204 struct ice_ptp_hw *ptp = &hw->ptp; 2205 struct ice_eth56g_params *params; 2206 2207 params = &ptp->phy.eth56g; 2208 params->onestep_ena = false; 2209 params->peer_delay = 0; 2210 params->sfd_ena = false; 2211 params->num_phys = 2; 2212 ptp->ports_per_phy = 4; 2213 ptp->num_lports = params->num_phys * ptp->ports_per_phy; 2214 } 2215 2216 /* E822 family functions 2217 * 2218 * The following functions operate on the E822 family of devices. 2219 */ 2220 2221 /** 2222 * ice_fill_phy_msg_e82x - Fill message data for a PHY register access 2223 * @hw: pointer to the HW struct 2224 * @msg: the PHY message buffer to fill in 2225 * @port: the port to access 2226 * @offset: the register offset 2227 */ 2228 static void ice_fill_phy_msg_e82x(struct ice_hw *hw, 2229 struct ice_sbq_msg_input *msg, u8 port, 2230 u16 offset) 2231 { 2232 int phy_port, quadtype; 2233 2234 phy_port = port % hw->ptp.ports_per_phy; 2235 quadtype = ICE_GET_QUAD_NUM(port) % 2236 ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy); 2237 2238 if (quadtype == 0) { 2239 msg->msg_addr_low = P_Q0_L(P_0_BASE + offset, phy_port); 2240 msg->msg_addr_high = P_Q0_H(P_0_BASE + offset, phy_port); 2241 } else { 2242 msg->msg_addr_low = P_Q1_L(P_4_BASE + offset, phy_port); 2243 msg->msg_addr_high = P_Q1_H(P_4_BASE + offset, phy_port); 2244 } 2245 2246 msg->dest_dev = ice_sbq_dev_phy_0; 2247 } 2248 2249 /** 2250 * ice_is_64b_phy_reg_e82x - Check if this is a 64bit PHY register 2251 * @low_addr: the low address to check 2252 * @high_addr: on return, contains the high address of the 64bit register 2253 * 2254 * Checks if the provided low address is one of the known 64bit PHY values 2255 * represented as two 32bit registers. If it is, return the appropriate high 2256 * register offset to use. 2257 */ 2258 static bool ice_is_64b_phy_reg_e82x(u16 low_addr, u16 *high_addr) 2259 { 2260 switch (low_addr) { 2261 case P_REG_PAR_PCS_TX_OFFSET_L: 2262 *high_addr = P_REG_PAR_PCS_TX_OFFSET_U; 2263 return true; 2264 case P_REG_PAR_PCS_RX_OFFSET_L: 2265 *high_addr = P_REG_PAR_PCS_RX_OFFSET_U; 2266 return true; 2267 case P_REG_PAR_TX_TIME_L: 2268 *high_addr = P_REG_PAR_TX_TIME_U; 2269 return true; 2270 case P_REG_PAR_RX_TIME_L: 2271 *high_addr = P_REG_PAR_RX_TIME_U; 2272 return true; 2273 case P_REG_TOTAL_TX_OFFSET_L: 2274 *high_addr = P_REG_TOTAL_TX_OFFSET_U; 2275 return true; 2276 case P_REG_TOTAL_RX_OFFSET_L: 2277 *high_addr = P_REG_TOTAL_RX_OFFSET_U; 2278 return true; 2279 case P_REG_UIX66_10G_40G_L: 2280 *high_addr = P_REG_UIX66_10G_40G_U; 2281 return true; 2282 case P_REG_UIX66_25G_100G_L: 2283 *high_addr = P_REG_UIX66_25G_100G_U; 2284 return true; 2285 case P_REG_TX_CAPTURE_L: 2286 *high_addr = P_REG_TX_CAPTURE_U; 2287 return true; 2288 case P_REG_RX_CAPTURE_L: 2289 *high_addr = P_REG_RX_CAPTURE_U; 2290 return true; 2291 case P_REG_TX_TIMER_INC_PRE_L: 2292 *high_addr = P_REG_TX_TIMER_INC_PRE_U; 2293 return true; 2294 case P_REG_RX_TIMER_INC_PRE_L: 2295 *high_addr = P_REG_RX_TIMER_INC_PRE_U; 2296 return true; 2297 default: 2298 return false; 2299 } 2300 } 2301 2302 /** 2303 * ice_is_40b_phy_reg_e82x - Check if this is a 40bit PHY register 2304 * @low_addr: the low address to check 2305 * @high_addr: on return, contains the high address of the 40bit value 2306 * 2307 * Checks if the provided low address is one of the known 40bit PHY values 2308 * split into two registers with the lower 8 bits in the low register and the 2309 * upper 32 bits in the high register. If it is, return the appropriate high 2310 * register offset to use. 2311 */ 2312 static bool ice_is_40b_phy_reg_e82x(u16 low_addr, u16 *high_addr) 2313 { 2314 switch (low_addr) { 2315 case P_REG_TIMETUS_L: 2316 *high_addr = P_REG_TIMETUS_U; 2317 return true; 2318 case P_REG_PAR_RX_TUS_L: 2319 *high_addr = P_REG_PAR_RX_TUS_U; 2320 return true; 2321 case P_REG_PAR_TX_TUS_L: 2322 *high_addr = P_REG_PAR_TX_TUS_U; 2323 return true; 2324 case P_REG_PCS_RX_TUS_L: 2325 *high_addr = P_REG_PCS_RX_TUS_U; 2326 return true; 2327 case P_REG_PCS_TX_TUS_L: 2328 *high_addr = P_REG_PCS_TX_TUS_U; 2329 return true; 2330 case P_REG_DESK_PAR_RX_TUS_L: 2331 *high_addr = P_REG_DESK_PAR_RX_TUS_U; 2332 return true; 2333 case P_REG_DESK_PAR_TX_TUS_L: 2334 *high_addr = P_REG_DESK_PAR_TX_TUS_U; 2335 return true; 2336 case P_REG_DESK_PCS_RX_TUS_L: 2337 *high_addr = P_REG_DESK_PCS_RX_TUS_U; 2338 return true; 2339 case P_REG_DESK_PCS_TX_TUS_L: 2340 *high_addr = P_REG_DESK_PCS_TX_TUS_U; 2341 return true; 2342 default: 2343 return false; 2344 } 2345 } 2346 2347 /** 2348 * ice_read_phy_reg_e82x - Read a PHY register 2349 * @hw: pointer to the HW struct 2350 * @port: PHY port to read from 2351 * @offset: PHY register offset to read 2352 * @val: on return, the contents read from the PHY 2353 * 2354 * Read a PHY register for the given port over the device sideband queue. 2355 */ 2356 static int 2357 ice_read_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 *val) 2358 { 2359 struct ice_sbq_msg_input msg = {0}; 2360 int err; 2361 2362 ice_fill_phy_msg_e82x(hw, &msg, port, offset); 2363 msg.opcode = ice_sbq_msg_rd; 2364 2365 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 2366 if (err) { 2367 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2368 err); 2369 return err; 2370 } 2371 2372 *val = msg.data; 2373 2374 return 0; 2375 } 2376 2377 /** 2378 * ice_read_64b_phy_reg_e82x - Read a 64bit value from PHY registers 2379 * @hw: pointer to the HW struct 2380 * @port: PHY port to read from 2381 * @low_addr: offset of the lower register to read from 2382 * @val: on return, the contents of the 64bit value from the PHY registers 2383 * 2384 * Reads the two registers associated with a 64bit value and returns it in the 2385 * val pointer. The offset always specifies the lower register offset to use. 2386 * The high offset is looked up. This function only operates on registers 2387 * known to be two parts of a 64bit value. 2388 */ 2389 static int 2390 ice_read_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val) 2391 { 2392 u32 low, high; 2393 u16 high_addr; 2394 int err; 2395 2396 /* Only operate on registers known to be split into two 32bit 2397 * registers. 2398 */ 2399 if (!ice_is_64b_phy_reg_e82x(low_addr, &high_addr)) { 2400 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n", 2401 low_addr); 2402 return -EINVAL; 2403 } 2404 2405 err = ice_read_phy_reg_e82x(hw, port, low_addr, &low); 2406 if (err) { 2407 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, err %d", 2408 low_addr, err); 2409 return err; 2410 } 2411 2412 err = ice_read_phy_reg_e82x(hw, port, high_addr, &high); 2413 if (err) { 2414 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, err %d", 2415 high_addr, err); 2416 return err; 2417 } 2418 2419 *val = (u64)high << 32 | low; 2420 2421 return 0; 2422 } 2423 2424 /** 2425 * ice_write_phy_reg_e82x - Write a PHY register 2426 * @hw: pointer to the HW struct 2427 * @port: PHY port to write to 2428 * @offset: PHY register offset to write 2429 * @val: The value to write to the register 2430 * 2431 * Write a PHY register for the given port over the device sideband queue. 2432 */ 2433 static int 2434 ice_write_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 val) 2435 { 2436 struct ice_sbq_msg_input msg = {0}; 2437 int err; 2438 2439 ice_fill_phy_msg_e82x(hw, &msg, port, offset); 2440 msg.opcode = ice_sbq_msg_wr; 2441 msg.data = val; 2442 2443 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 2444 if (err) { 2445 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2446 err); 2447 return err; 2448 } 2449 2450 return 0; 2451 } 2452 2453 /** 2454 * ice_write_40b_phy_reg_e82x - Write a 40b value to the PHY 2455 * @hw: pointer to the HW struct 2456 * @port: port to write to 2457 * @low_addr: offset of the low register 2458 * @val: 40b value to write 2459 * 2460 * Write the provided 40b value to the two associated registers by splitting 2461 * it up into two chunks, the lower 8 bits and the upper 32 bits. 2462 */ 2463 static int 2464 ice_write_40b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) 2465 { 2466 u32 low, high; 2467 u16 high_addr; 2468 int err; 2469 2470 /* Only operate on registers known to be split into a lower 8 bit 2471 * register and an upper 32 bit register. 2472 */ 2473 if (!ice_is_40b_phy_reg_e82x(low_addr, &high_addr)) { 2474 ice_debug(hw, ICE_DBG_PTP, "Invalid 40b register addr 0x%08x\n", 2475 low_addr); 2476 return -EINVAL; 2477 } 2478 low = FIELD_GET(P_REG_40B_LOW_M, val); 2479 high = (u32)(val >> P_REG_40B_HIGH_S); 2480 2481 err = ice_write_phy_reg_e82x(hw, port, low_addr, low); 2482 if (err) { 2483 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 2484 low_addr, err); 2485 return err; 2486 } 2487 2488 err = ice_write_phy_reg_e82x(hw, port, high_addr, high); 2489 if (err) { 2490 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 2491 high_addr, err); 2492 return err; 2493 } 2494 2495 return 0; 2496 } 2497 2498 /** 2499 * ice_write_64b_phy_reg_e82x - Write a 64bit value to PHY registers 2500 * @hw: pointer to the HW struct 2501 * @port: PHY port to read from 2502 * @low_addr: offset of the lower register to read from 2503 * @val: the contents of the 64bit value to write to PHY 2504 * 2505 * Write the 64bit value to the two associated 32bit PHY registers. The offset 2506 * is always specified as the lower register, and the high address is looked 2507 * up. This function only operates on registers known to be two parts of 2508 * a 64bit value. 2509 */ 2510 static int 2511 ice_write_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) 2512 { 2513 u32 low, high; 2514 u16 high_addr; 2515 int err; 2516 2517 /* Only operate on registers known to be split into two 32bit 2518 * registers. 2519 */ 2520 if (!ice_is_64b_phy_reg_e82x(low_addr, &high_addr)) { 2521 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n", 2522 low_addr); 2523 return -EINVAL; 2524 } 2525 2526 low = lower_32_bits(val); 2527 high = upper_32_bits(val); 2528 2529 err = ice_write_phy_reg_e82x(hw, port, low_addr, low); 2530 if (err) { 2531 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 2532 low_addr, err); 2533 return err; 2534 } 2535 2536 err = ice_write_phy_reg_e82x(hw, port, high_addr, high); 2537 if (err) { 2538 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 2539 high_addr, err); 2540 return err; 2541 } 2542 2543 return 0; 2544 } 2545 2546 /** 2547 * ice_fill_quad_msg_e82x - Fill message data for quad register access 2548 * @hw: pointer to the HW struct 2549 * @msg: the PHY message buffer to fill in 2550 * @quad: the quad to access 2551 * @offset: the register offset 2552 * 2553 * Fill a message buffer for accessing a register in a quad shared between 2554 * multiple PHYs. 2555 * 2556 * Return: 2557 * * %0 - OK 2558 * * %-EINVAL - invalid quad number 2559 */ 2560 static int ice_fill_quad_msg_e82x(struct ice_hw *hw, 2561 struct ice_sbq_msg_input *msg, u8 quad, 2562 u16 offset) 2563 { 2564 u32 addr; 2565 2566 if (quad >= ICE_GET_QUAD_NUM(hw->ptp.num_lports)) 2567 return -EINVAL; 2568 2569 msg->dest_dev = ice_sbq_dev_phy_0; 2570 2571 if (!(quad % ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy))) 2572 addr = Q_0_BASE + offset; 2573 else 2574 addr = Q_1_BASE + offset; 2575 2576 msg->msg_addr_low = lower_16_bits(addr); 2577 msg->msg_addr_high = upper_16_bits(addr); 2578 2579 return 0; 2580 } 2581 2582 /** 2583 * ice_read_quad_reg_e82x - Read a PHY quad register 2584 * @hw: pointer to the HW struct 2585 * @quad: quad to read from 2586 * @offset: quad register offset to read 2587 * @val: on return, the contents read from the quad 2588 * 2589 * Read a quad register over the device sideband queue. Quad registers are 2590 * shared between multiple PHYs. 2591 */ 2592 int 2593 ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val) 2594 { 2595 struct ice_sbq_msg_input msg = {0}; 2596 int err; 2597 2598 err = ice_fill_quad_msg_e82x(hw, &msg, quad, offset); 2599 if (err) 2600 return err; 2601 2602 msg.opcode = ice_sbq_msg_rd; 2603 2604 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 2605 if (err) { 2606 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2607 err); 2608 return err; 2609 } 2610 2611 *val = msg.data; 2612 2613 return 0; 2614 } 2615 2616 /** 2617 * ice_write_quad_reg_e82x - Write a PHY quad register 2618 * @hw: pointer to the HW struct 2619 * @quad: quad to write to 2620 * @offset: quad register offset to write 2621 * @val: The value to write to the register 2622 * 2623 * Write a quad register over the device sideband queue. Quad registers are 2624 * shared between multiple PHYs. 2625 */ 2626 int 2627 ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val) 2628 { 2629 struct ice_sbq_msg_input msg = {0}; 2630 int err; 2631 2632 err = ice_fill_quad_msg_e82x(hw, &msg, quad, offset); 2633 if (err) 2634 return err; 2635 2636 msg.opcode = ice_sbq_msg_wr; 2637 msg.data = val; 2638 2639 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 2640 if (err) { 2641 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2642 err); 2643 return err; 2644 } 2645 2646 return 0; 2647 } 2648 2649 /** 2650 * ice_read_phy_tstamp_e82x - Read a PHY timestamp out of the quad block 2651 * @hw: pointer to the HW struct 2652 * @quad: the quad to read from 2653 * @idx: the timestamp index to read 2654 * @tstamp: on return, the 40bit timestamp value 2655 * 2656 * Read a 40bit timestamp value out of the two associated registers in the 2657 * quad memory block that is shared between the internal PHYs of the E822 2658 * family of devices. 2659 */ 2660 static int 2661 ice_read_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp) 2662 { 2663 u16 lo_addr, hi_addr; 2664 u32 lo, hi; 2665 int err; 2666 2667 lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx); 2668 hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx); 2669 2670 err = ice_read_quad_reg_e82x(hw, quad, lo_addr, &lo); 2671 if (err) { 2672 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 2673 err); 2674 return err; 2675 } 2676 2677 err = ice_read_quad_reg_e82x(hw, quad, hi_addr, &hi); 2678 if (err) { 2679 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 2680 err); 2681 return err; 2682 } 2683 2684 /* For E822 based internal PHYs, the timestamp is reported with the 2685 * lower 8 bits in the low register, and the upper 32 bits in the high 2686 * register. 2687 */ 2688 *tstamp = FIELD_PREP(PHY_40B_HIGH_M, hi) | 2689 FIELD_PREP(PHY_40B_LOW_M, lo); 2690 2691 return 0; 2692 } 2693 2694 /** 2695 * ice_clear_phy_tstamp_e82x - Clear a timestamp from the quad block 2696 * @hw: pointer to the HW struct 2697 * @quad: the quad to read from 2698 * @idx: the timestamp index to reset 2699 * 2700 * Read the timestamp out of the quad to clear its timestamp status bit from 2701 * the PHY quad block that is shared between the internal PHYs of the E822 2702 * devices. 2703 * 2704 * Note that unlike E810, software cannot directly write to the quad memory 2705 * bank registers. E822 relies on the ice_get_phy_tx_tstamp_ready() function 2706 * to determine which timestamps are valid. Reading a timestamp auto-clears 2707 * the valid bit. 2708 * 2709 * To directly clear the contents of the timestamp block entirely, discarding 2710 * all timestamp data at once, software should instead use 2711 * ice_ptp_reset_ts_memory_quad_e82x(). 2712 * 2713 * This function should only be called on an idx whose bit is set according to 2714 * ice_get_phy_tx_tstamp_ready(). 2715 */ 2716 static int 2717 ice_clear_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx) 2718 { 2719 u64 unused_tstamp; 2720 int err; 2721 2722 err = ice_read_phy_tstamp_e82x(hw, quad, idx, &unused_tstamp); 2723 if (err) { 2724 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for quad %u, idx %u, err %d\n", 2725 quad, idx, err); 2726 return err; 2727 } 2728 2729 return 0; 2730 } 2731 2732 /** 2733 * ice_ptp_reset_ts_memory_quad_e82x - Clear all timestamps from the quad block 2734 * @hw: pointer to the HW struct 2735 * @quad: the quad to read from 2736 * 2737 * Clear all timestamps from the PHY quad block that is shared between the 2738 * internal PHYs on the E822 devices. 2739 */ 2740 void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad) 2741 { 2742 ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M); 2743 ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M); 2744 } 2745 2746 /** 2747 * ice_ptp_reset_ts_memory_e82x - Clear all timestamps from all quad blocks 2748 * @hw: pointer to the HW struct 2749 */ 2750 static void ice_ptp_reset_ts_memory_e82x(struct ice_hw *hw) 2751 { 2752 unsigned int quad; 2753 2754 for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports); quad++) 2755 ice_ptp_reset_ts_memory_quad_e82x(hw, quad); 2756 } 2757 2758 /** 2759 * ice_ptp_set_vernier_wl - Set the window length for vernier calibration 2760 * @hw: pointer to the HW struct 2761 * 2762 * Set the window length used for the vernier port calibration process. 2763 */ 2764 static int ice_ptp_set_vernier_wl(struct ice_hw *hw) 2765 { 2766 u8 port; 2767 2768 for (port = 0; port < hw->ptp.num_lports; port++) { 2769 int err; 2770 2771 err = ice_write_phy_reg_e82x(hw, port, P_REG_WL, 2772 PTP_VERNIER_WL); 2773 if (err) { 2774 ice_debug(hw, ICE_DBG_PTP, "Failed to set vernier window length for port %u, err %d\n", 2775 port, err); 2776 return err; 2777 } 2778 } 2779 2780 return 0; 2781 } 2782 2783 /** 2784 * ice_ptp_init_phc_e82x - Perform E822 specific PHC initialization 2785 * @hw: pointer to HW struct 2786 * 2787 * Perform PHC initialization steps specific to E822 devices. 2788 */ 2789 static int ice_ptp_init_phc_e82x(struct ice_hw *hw) 2790 { 2791 int err; 2792 u32 val; 2793 2794 /* Enable reading switch and PHY registers over the sideband queue */ 2795 #define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1) 2796 #define PF_SB_REM_DEV_CTL_PHY0 BIT(2) 2797 val = rd32(hw, PF_SB_REM_DEV_CTL); 2798 val |= (PF_SB_REM_DEV_CTL_SWITCH_READ | PF_SB_REM_DEV_CTL_PHY0); 2799 wr32(hw, PF_SB_REM_DEV_CTL, val); 2800 2801 /* Initialize the Clock Generation Unit */ 2802 err = ice_tspll_init(hw); 2803 if (err) 2804 return err; 2805 2806 /* Set window length for all the ports */ 2807 return ice_ptp_set_vernier_wl(hw); 2808 } 2809 2810 /** 2811 * ice_ptp_prep_phy_time_e82x - Prepare PHY port with initial time 2812 * @hw: pointer to the HW struct 2813 * @time: Time to initialize the PHY port clocks to 2814 * 2815 * Program the PHY port registers with a new initial time value. The port 2816 * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync 2817 * command. The time value is the upper 32 bits of the PHY timer, usually in 2818 * units of nominal nanoseconds. 2819 */ 2820 static int 2821 ice_ptp_prep_phy_time_e82x(struct ice_hw *hw, u32 time) 2822 { 2823 u64 phy_time; 2824 u8 port; 2825 int err; 2826 2827 /* The time represents the upper 32 bits of the PHY timer, so we need 2828 * to shift to account for this when programming. 2829 */ 2830 phy_time = (u64)time << 32; 2831 2832 for (port = 0; port < hw->ptp.num_lports; port++) { 2833 /* Tx case */ 2834 err = ice_write_64b_phy_reg_e82x(hw, port, 2835 P_REG_TX_TIMER_INC_PRE_L, 2836 phy_time); 2837 if (err) 2838 goto exit_err; 2839 2840 /* Rx case */ 2841 err = ice_write_64b_phy_reg_e82x(hw, port, 2842 P_REG_RX_TIMER_INC_PRE_L, 2843 phy_time); 2844 if (err) 2845 goto exit_err; 2846 } 2847 2848 return 0; 2849 2850 exit_err: 2851 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n", 2852 port, err); 2853 2854 return err; 2855 } 2856 2857 /** 2858 * ice_ptp_prep_port_adj_e82x - Prepare a single port for time adjust 2859 * @hw: pointer to HW struct 2860 * @port: Port number to be programmed 2861 * @time: time in cycles to adjust the port Tx and Rx clocks 2862 * 2863 * Program the port for an atomic adjustment by writing the Tx and Rx timer 2864 * registers. The atomic adjustment won't be completed until the driver issues 2865 * an ICE_PTP_ADJ_TIME command. 2866 * 2867 * Note that time is not in units of nanoseconds. It is in clock time 2868 * including the lower sub-nanosecond portion of the port timer. 2869 * 2870 * Negative adjustments are supported using 2s complement arithmetic. 2871 */ 2872 static int 2873 ice_ptp_prep_port_adj_e82x(struct ice_hw *hw, u8 port, s64 time) 2874 { 2875 u32 l_time, u_time; 2876 int err; 2877 2878 l_time = lower_32_bits(time); 2879 u_time = upper_32_bits(time); 2880 2881 /* Tx case */ 2882 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TIMER_INC_PRE_L, 2883 l_time); 2884 if (err) 2885 goto exit_err; 2886 2887 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TIMER_INC_PRE_U, 2888 u_time); 2889 if (err) 2890 goto exit_err; 2891 2892 /* Rx case */ 2893 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TIMER_INC_PRE_L, 2894 l_time); 2895 if (err) 2896 goto exit_err; 2897 2898 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TIMER_INC_PRE_U, 2899 u_time); 2900 if (err) 2901 goto exit_err; 2902 2903 return 0; 2904 2905 exit_err: 2906 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n", 2907 port, err); 2908 return err; 2909 } 2910 2911 /** 2912 * ice_ptp_prep_phy_adj_e82x - Prep PHY ports for a time adjustment 2913 * @hw: pointer to HW struct 2914 * @adj: adjustment in nanoseconds 2915 * 2916 * Prepare the PHY ports for an atomic time adjustment by programming the PHY 2917 * Tx and Rx port registers. The actual adjustment is completed by issuing an 2918 * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command. 2919 */ 2920 static int 2921 ice_ptp_prep_phy_adj_e82x(struct ice_hw *hw, s32 adj) 2922 { 2923 s64 cycles; 2924 u8 port; 2925 2926 /* The port clock supports adjustment of the sub-nanosecond portion of 2927 * the clock. We shift the provided adjustment in nanoseconds to 2928 * calculate the appropriate adjustment to program into the PHY ports. 2929 */ 2930 if (adj > 0) 2931 cycles = (s64)adj << 32; 2932 else 2933 cycles = -(((s64)-adj) << 32); 2934 2935 for (port = 0; port < hw->ptp.num_lports; port++) { 2936 int err; 2937 2938 err = ice_ptp_prep_port_adj_e82x(hw, port, cycles); 2939 if (err) 2940 return err; 2941 } 2942 2943 return 0; 2944 } 2945 2946 /** 2947 * ice_ptp_prep_phy_incval_e82x - Prepare PHY ports for time adjustment 2948 * @hw: pointer to HW struct 2949 * @incval: new increment value to prepare 2950 * 2951 * Prepare each of the PHY ports for a new increment value by programming the 2952 * port's TIMETUS registers. The new increment value will be updated after 2953 * issuing an ICE_PTP_INIT_INCVAL command. 2954 */ 2955 static int 2956 ice_ptp_prep_phy_incval_e82x(struct ice_hw *hw, u64 incval) 2957 { 2958 int err; 2959 u8 port; 2960 2961 for (port = 0; port < hw->ptp.num_lports; port++) { 2962 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L, 2963 incval); 2964 if (err) 2965 goto exit_err; 2966 } 2967 2968 return 0; 2969 2970 exit_err: 2971 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n", 2972 port, err); 2973 2974 return err; 2975 } 2976 2977 /** 2978 * ice_ptp_read_port_capture - Read a port's local time capture 2979 * @hw: pointer to HW struct 2980 * @port: Port number to read 2981 * @tx_ts: on return, the Tx port time capture 2982 * @rx_ts: on return, the Rx port time capture 2983 * 2984 * Read the port's Tx and Rx local time capture values. 2985 * 2986 * Note this has no equivalent for the E810 devices. 2987 */ 2988 static int 2989 ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts) 2990 { 2991 int err; 2992 2993 /* Tx case */ 2994 err = ice_read_64b_phy_reg_e82x(hw, port, P_REG_TX_CAPTURE_L, tx_ts); 2995 if (err) { 2996 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n", 2997 err); 2998 return err; 2999 } 3000 3001 ice_debug(hw, ICE_DBG_PTP, "tx_init = 0x%016llx\n", 3002 (unsigned long long)*tx_ts); 3003 3004 /* Rx case */ 3005 err = ice_read_64b_phy_reg_e82x(hw, port, P_REG_RX_CAPTURE_L, rx_ts); 3006 if (err) { 3007 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n", 3008 err); 3009 return err; 3010 } 3011 3012 ice_debug(hw, ICE_DBG_PTP, "rx_init = 0x%016llx\n", 3013 (unsigned long long)*rx_ts); 3014 3015 return 0; 3016 } 3017 3018 /** 3019 * ice_ptp_write_port_cmd_e82x - Prepare a single PHY port for a timer command 3020 * @hw: pointer to HW struct 3021 * @port: Port to which cmd has to be sent 3022 * @cmd: Command to be sent to the port 3023 * 3024 * Prepare the requested port for an upcoming timer sync command. 3025 * 3026 * Note there is no equivalent of this operation on E810, as that device 3027 * always handles all external PHYs internally. 3028 * 3029 * Return: 3030 * * %0 - success 3031 * * %other - failed to write to PHY 3032 */ 3033 static int ice_ptp_write_port_cmd_e82x(struct ice_hw *hw, u8 port, 3034 enum ice_ptp_tmr_cmd cmd) 3035 { 3036 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 3037 int err; 3038 3039 /* Tx case */ 3040 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TMR_CMD, val); 3041 if (err) { 3042 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n", 3043 err); 3044 return err; 3045 } 3046 3047 /* Rx case */ 3048 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TMR_CMD, 3049 val | TS_CMD_RX_TYPE); 3050 if (err) { 3051 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n", 3052 err); 3053 return err; 3054 } 3055 3056 return 0; 3057 } 3058 3059 /* E822 Vernier calibration functions 3060 * 3061 * The following functions are used as part of the vernier calibration of 3062 * a port. This calibration increases the precision of the timestamps on the 3063 * port. 3064 */ 3065 3066 /** 3067 * ice_phy_get_speed_and_fec_e82x - Get link speed and FEC based on serdes mode 3068 * @hw: pointer to HW struct 3069 * @port: the port to read from 3070 * @link_out: if non-NULL, holds link speed on success 3071 * @fec_out: if non-NULL, holds FEC algorithm on success 3072 * 3073 * Read the serdes data for the PHY port and extract the link speed and FEC 3074 * algorithm. 3075 */ 3076 static int 3077 ice_phy_get_speed_and_fec_e82x(struct ice_hw *hw, u8 port, 3078 enum ice_ptp_link_spd *link_out, 3079 enum ice_ptp_fec_mode *fec_out) 3080 { 3081 enum ice_ptp_link_spd link; 3082 enum ice_ptp_fec_mode fec; 3083 u32 serdes; 3084 int err; 3085 3086 err = ice_read_phy_reg_e82x(hw, port, P_REG_LINK_SPEED, &serdes); 3087 if (err) { 3088 ice_debug(hw, ICE_DBG_PTP, "Failed to read serdes info\n"); 3089 return err; 3090 } 3091 3092 /* Determine the FEC algorithm */ 3093 fec = (enum ice_ptp_fec_mode)P_REG_LINK_SPEED_FEC_MODE(serdes); 3094 3095 serdes &= P_REG_LINK_SPEED_SERDES_M; 3096 3097 /* Determine the link speed */ 3098 if (fec == ICE_PTP_FEC_MODE_RS_FEC) { 3099 switch (serdes) { 3100 case ICE_PTP_SERDES_25G: 3101 link = ICE_PTP_LNK_SPD_25G_RS; 3102 break; 3103 case ICE_PTP_SERDES_50G: 3104 link = ICE_PTP_LNK_SPD_50G_RS; 3105 break; 3106 case ICE_PTP_SERDES_100G: 3107 link = ICE_PTP_LNK_SPD_100G_RS; 3108 break; 3109 default: 3110 return -EIO; 3111 } 3112 } else { 3113 switch (serdes) { 3114 case ICE_PTP_SERDES_1G: 3115 link = ICE_PTP_LNK_SPD_1G; 3116 break; 3117 case ICE_PTP_SERDES_10G: 3118 link = ICE_PTP_LNK_SPD_10G; 3119 break; 3120 case ICE_PTP_SERDES_25G: 3121 link = ICE_PTP_LNK_SPD_25G; 3122 break; 3123 case ICE_PTP_SERDES_40G: 3124 link = ICE_PTP_LNK_SPD_40G; 3125 break; 3126 case ICE_PTP_SERDES_50G: 3127 link = ICE_PTP_LNK_SPD_50G; 3128 break; 3129 default: 3130 return -EIO; 3131 } 3132 } 3133 3134 if (link_out) 3135 *link_out = link; 3136 if (fec_out) 3137 *fec_out = fec; 3138 3139 return 0; 3140 } 3141 3142 /** 3143 * ice_phy_cfg_lane_e82x - Configure PHY quad for single/multi-lane timestamp 3144 * @hw: pointer to HW struct 3145 * @port: to configure the quad for 3146 */ 3147 static void ice_phy_cfg_lane_e82x(struct ice_hw *hw, u8 port) 3148 { 3149 enum ice_ptp_link_spd link_spd; 3150 int err; 3151 u32 val; 3152 u8 quad; 3153 3154 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, NULL); 3155 if (err) { 3156 ice_debug(hw, ICE_DBG_PTP, "Failed to get PHY link speed, err %d\n", 3157 err); 3158 return; 3159 } 3160 3161 quad = ICE_GET_QUAD_NUM(port); 3162 3163 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val); 3164 if (err) { 3165 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEM_GLB_CFG, err %d\n", 3166 err); 3167 return; 3168 } 3169 3170 if (link_spd >= ICE_PTP_LNK_SPD_40G) 3171 val &= ~Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M; 3172 else 3173 val |= Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M; 3174 3175 err = ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val); 3176 if (err) { 3177 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_MEM_GBL_CFG, err %d\n", 3178 err); 3179 return; 3180 } 3181 } 3182 3183 /** 3184 * ice_phy_cfg_uix_e82x - Configure Serdes UI to TU conversion for E822 3185 * @hw: pointer to the HW structure 3186 * @port: the port to configure 3187 * 3188 * Program the conversion ration of Serdes clock "unit intervals" (UIs) to PHC 3189 * hardware clock time units (TUs). That is, determine the number of TUs per 3190 * serdes unit interval, and program the UIX registers with this conversion. 3191 * 3192 * This conversion is used as part of the calibration process when determining 3193 * the additional error of a timestamp vs the real time of transmission or 3194 * receipt of the packet. 3195 * 3196 * Hardware uses the number of TUs per 66 UIs, written to the UIX registers 3197 * for the two main serdes clock rates, 10G/40G and 25G/100G serdes clocks. 3198 * 3199 * To calculate the conversion ratio, we use the following facts: 3200 * 3201 * a) the clock frequency in Hz (cycles per second) 3202 * b) the number of TUs per cycle (the increment value of the clock) 3203 * c) 1 second per 1 billion nanoseconds 3204 * d) the duration of 66 UIs in nanoseconds 3205 * 3206 * Given these facts, we can use the following table to work out what ratios 3207 * to multiply in order to get the number of TUs per 66 UIs: 3208 * 3209 * cycles | 1 second | incval (TUs) | nanoseconds 3210 * -------+--------------+--------------+------------- 3211 * second | 1 billion ns | cycle | 66 UIs 3212 * 3213 * To perform the multiplication using integers without too much loss of 3214 * precision, we can take use the following equation: 3215 * 3216 * (freq * incval * 6600 LINE_UI ) / ( 100 * 1 billion) 3217 * 3218 * We scale up to using 6600 UI instead of 66 in order to avoid fractional 3219 * nanosecond UIs (66 UI at 10G/40G is 6.4 ns) 3220 * 3221 * The increment value has a maximum expected range of about 34 bits, while 3222 * the frequency value is about 29 bits. Multiplying these values shouldn't 3223 * overflow the 64 bits. However, we must then further multiply them again by 3224 * the Serdes unit interval duration. To avoid overflow here, we split the 3225 * overall divide by 1e11 into a divide by 256 (shift down by 8 bits) and 3226 * a divide by 390,625,000. This does lose some precision, but avoids 3227 * miscalculation due to arithmetic overflow. 3228 */ 3229 static int ice_phy_cfg_uix_e82x(struct ice_hw *hw, u8 port) 3230 { 3231 u64 cur_freq, clk_incval, tu_per_sec, uix; 3232 int err; 3233 3234 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3235 clk_incval = ice_ptp_read_src_incval(hw); 3236 3237 /* Calculate TUs per second divided by 256 */ 3238 tu_per_sec = (cur_freq * clk_incval) >> 8; 3239 3240 #define LINE_UI_10G_40G 640 /* 6600 UIs is 640 nanoseconds at 10Gb/40Gb */ 3241 #define LINE_UI_25G_100G 256 /* 6600 UIs is 256 nanoseconds at 25Gb/100Gb */ 3242 3243 /* Program the 10Gb/40Gb conversion ratio */ 3244 uix = div_u64(tu_per_sec * LINE_UI_10G_40G, 390625000); 3245 3246 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_UIX66_10G_40G_L, 3247 uix); 3248 if (err) { 3249 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_10G_40G, err %d\n", 3250 err); 3251 return err; 3252 } 3253 3254 /* Program the 25Gb/100Gb conversion ratio */ 3255 uix = div_u64(tu_per_sec * LINE_UI_25G_100G, 390625000); 3256 3257 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_UIX66_25G_100G_L, 3258 uix); 3259 if (err) { 3260 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_25G_100G, err %d\n", 3261 err); 3262 return err; 3263 } 3264 3265 return 0; 3266 } 3267 3268 /** 3269 * ice_phy_cfg_parpcs_e82x - Configure TUs per PAR/PCS clock cycle 3270 * @hw: pointer to the HW struct 3271 * @port: port to configure 3272 * 3273 * Configure the number of TUs for the PAR and PCS clocks used as part of the 3274 * timestamp calibration process. This depends on the link speed, as the PHY 3275 * uses different markers depending on the speed. 3276 * 3277 * 1Gb/10Gb/25Gb: 3278 * - Tx/Rx PAR/PCS markers 3279 * 3280 * 25Gb RS: 3281 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers 3282 * 3283 * 40Gb/50Gb: 3284 * - Tx/Rx PAR/PCS markers 3285 * - Rx Deskew PAR/PCS markers 3286 * 3287 * 50G RS and 100GB RS: 3288 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers 3289 * - Rx Deskew PAR/PCS markers 3290 * - Tx PAR/PCS markers 3291 * 3292 * To calculate the conversion, we use the PHC clock frequency (cycles per 3293 * second), the increment value (TUs per cycle), and the related PHY clock 3294 * frequency to calculate the TUs per unit of the PHY link clock. The 3295 * following table shows how the units convert: 3296 * 3297 * cycles | TUs | second 3298 * -------+-------+-------- 3299 * second | cycle | cycles 3300 * 3301 * For each conversion register, look up the appropriate frequency from the 3302 * e822 PAR/PCS table and calculate the TUs per unit of that clock. Program 3303 * this to the appropriate register, preparing hardware to perform timestamp 3304 * calibration to calculate the total Tx or Rx offset to adjust the timestamp 3305 * in order to calibrate for the internal PHY delays. 3306 * 3307 * Note that the increment value ranges up to ~34 bits, and the clock 3308 * frequency is ~29 bits, so multiplying them together should fit within the 3309 * 64 bit arithmetic. 3310 */ 3311 static int ice_phy_cfg_parpcs_e82x(struct ice_hw *hw, u8 port) 3312 { 3313 u64 cur_freq, clk_incval, tu_per_sec, phy_tus; 3314 enum ice_ptp_link_spd link_spd; 3315 enum ice_ptp_fec_mode fec_mode; 3316 int err; 3317 3318 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode); 3319 if (err) 3320 return err; 3321 3322 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3323 clk_incval = ice_ptp_read_src_incval(hw); 3324 3325 /* Calculate TUs per cycle of the PHC clock */ 3326 tu_per_sec = cur_freq * clk_incval; 3327 3328 /* For each PHY conversion register, look up the appropriate link 3329 * speed frequency and determine the TUs per that clock's cycle time. 3330 * Split this into a high and low value and then program the 3331 * appropriate register. If that link speed does not use the 3332 * associated register, write zeros to clear it instead. 3333 */ 3334 3335 /* P_REG_PAR_TX_TUS */ 3336 if (e822_vernier[link_spd].tx_par_clk) 3337 phy_tus = div_u64(tu_per_sec, 3338 e822_vernier[link_spd].tx_par_clk); 3339 else 3340 phy_tus = 0; 3341 3342 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PAR_TX_TUS_L, 3343 phy_tus); 3344 if (err) 3345 return err; 3346 3347 /* P_REG_PAR_RX_TUS */ 3348 if (e822_vernier[link_spd].rx_par_clk) 3349 phy_tus = div_u64(tu_per_sec, 3350 e822_vernier[link_spd].rx_par_clk); 3351 else 3352 phy_tus = 0; 3353 3354 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PAR_RX_TUS_L, 3355 phy_tus); 3356 if (err) 3357 return err; 3358 3359 /* P_REG_PCS_TX_TUS */ 3360 if (e822_vernier[link_spd].tx_pcs_clk) 3361 phy_tus = div_u64(tu_per_sec, 3362 e822_vernier[link_spd].tx_pcs_clk); 3363 else 3364 phy_tus = 0; 3365 3366 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PCS_TX_TUS_L, 3367 phy_tus); 3368 if (err) 3369 return err; 3370 3371 /* P_REG_PCS_RX_TUS */ 3372 if (e822_vernier[link_spd].rx_pcs_clk) 3373 phy_tus = div_u64(tu_per_sec, 3374 e822_vernier[link_spd].rx_pcs_clk); 3375 else 3376 phy_tus = 0; 3377 3378 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PCS_RX_TUS_L, 3379 phy_tus); 3380 if (err) 3381 return err; 3382 3383 /* P_REG_DESK_PAR_TX_TUS */ 3384 if (e822_vernier[link_spd].tx_desk_rsgb_par) 3385 phy_tus = div_u64(tu_per_sec, 3386 e822_vernier[link_spd].tx_desk_rsgb_par); 3387 else 3388 phy_tus = 0; 3389 3390 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PAR_TX_TUS_L, 3391 phy_tus); 3392 if (err) 3393 return err; 3394 3395 /* P_REG_DESK_PAR_RX_TUS */ 3396 if (e822_vernier[link_spd].rx_desk_rsgb_par) 3397 phy_tus = div_u64(tu_per_sec, 3398 e822_vernier[link_spd].rx_desk_rsgb_par); 3399 else 3400 phy_tus = 0; 3401 3402 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PAR_RX_TUS_L, 3403 phy_tus); 3404 if (err) 3405 return err; 3406 3407 /* P_REG_DESK_PCS_TX_TUS */ 3408 if (e822_vernier[link_spd].tx_desk_rsgb_pcs) 3409 phy_tus = div_u64(tu_per_sec, 3410 e822_vernier[link_spd].tx_desk_rsgb_pcs); 3411 else 3412 phy_tus = 0; 3413 3414 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PCS_TX_TUS_L, 3415 phy_tus); 3416 if (err) 3417 return err; 3418 3419 /* P_REG_DESK_PCS_RX_TUS */ 3420 if (e822_vernier[link_spd].rx_desk_rsgb_pcs) 3421 phy_tus = div_u64(tu_per_sec, 3422 e822_vernier[link_spd].rx_desk_rsgb_pcs); 3423 else 3424 phy_tus = 0; 3425 3426 return ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PCS_RX_TUS_L, 3427 phy_tus); 3428 } 3429 3430 /** 3431 * ice_calc_fixed_tx_offset_e82x - Calculated Fixed Tx offset for a port 3432 * @hw: pointer to the HW struct 3433 * @link_spd: the Link speed to calculate for 3434 * 3435 * Calculate the fixed offset due to known static latency data. 3436 */ 3437 static u64 3438 ice_calc_fixed_tx_offset_e82x(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) 3439 { 3440 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset; 3441 3442 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3443 clk_incval = ice_ptp_read_src_incval(hw); 3444 3445 /* Calculate TUs per second */ 3446 tu_per_sec = cur_freq * clk_incval; 3447 3448 /* Calculate number of TUs to add for the fixed Tx latency. Since the 3449 * latency measurement is in 1/100th of a nanosecond, we need to 3450 * multiply by tu_per_sec and then divide by 1e11. This calculation 3451 * overflows 64 bit integer arithmetic, so break it up into two 3452 * divisions by 1e4 first then by 1e7. 3453 */ 3454 fixed_offset = div_u64(tu_per_sec, 10000); 3455 fixed_offset *= e822_vernier[link_spd].tx_fixed_delay; 3456 fixed_offset = div_u64(fixed_offset, 10000000); 3457 3458 return fixed_offset; 3459 } 3460 3461 /** 3462 * ice_phy_cfg_tx_offset_e82x - Configure total Tx timestamp offset 3463 * @hw: pointer to the HW struct 3464 * @port: the PHY port to configure 3465 * 3466 * Program the P_REG_TOTAL_TX_OFFSET register with the total number of TUs to 3467 * adjust Tx timestamps by. This is calculated by combining some known static 3468 * latency along with the Vernier offset computations done by hardware. 3469 * 3470 * This function will not return successfully until the Tx offset calculations 3471 * have been completed, which requires waiting until at least one packet has 3472 * been transmitted by the device. It is safe to call this function 3473 * periodically until calibration succeeds, as it will only program the offset 3474 * once. 3475 * 3476 * To avoid overflow, when calculating the offset based on the known static 3477 * latency values, we use measurements in 1/100th of a nanosecond, and divide 3478 * the TUs per second up front. This avoids overflow while allowing 3479 * calculation of the adjustment using integer arithmetic. 3480 * 3481 * Returns zero on success, -EBUSY if the hardware vernier offset 3482 * calibration has not completed, or another error code on failure. 3483 */ 3484 int ice_phy_cfg_tx_offset_e82x(struct ice_hw *hw, u8 port) 3485 { 3486 enum ice_ptp_link_spd link_spd; 3487 enum ice_ptp_fec_mode fec_mode; 3488 u64 total_offset, val; 3489 int err; 3490 u32 reg; 3491 3492 /* Nothing to do if we've already programmed the offset */ 3493 err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_OR, ®); 3494 if (err) { 3495 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OR for port %u, err %d\n", 3496 port, err); 3497 return err; 3498 } 3499 3500 if (reg) 3501 return 0; 3502 3503 err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_OV_STATUS, ®); 3504 if (err) { 3505 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OV_STATUS for port %u, err %d\n", 3506 port, err); 3507 return err; 3508 } 3509 3510 if (!(reg & P_REG_TX_OV_STATUS_OV_M)) 3511 return -EBUSY; 3512 3513 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode); 3514 if (err) 3515 return err; 3516 3517 total_offset = ice_calc_fixed_tx_offset_e82x(hw, link_spd); 3518 3519 /* Read the first Vernier offset from the PHY register and add it to 3520 * the total offset. 3521 */ 3522 if (link_spd == ICE_PTP_LNK_SPD_1G || 3523 link_spd == ICE_PTP_LNK_SPD_10G || 3524 link_spd == ICE_PTP_LNK_SPD_25G || 3525 link_spd == ICE_PTP_LNK_SPD_25G_RS || 3526 link_spd == ICE_PTP_LNK_SPD_40G || 3527 link_spd == ICE_PTP_LNK_SPD_50G) { 3528 err = ice_read_64b_phy_reg_e82x(hw, port, 3529 P_REG_PAR_PCS_TX_OFFSET_L, 3530 &val); 3531 if (err) 3532 return err; 3533 3534 total_offset += val; 3535 } 3536 3537 /* For Tx, we only need to use the second Vernier offset for 3538 * multi-lane link speeds with RS-FEC. The lanes will always be 3539 * aligned. 3540 */ 3541 if (link_spd == ICE_PTP_LNK_SPD_50G_RS || 3542 link_spd == ICE_PTP_LNK_SPD_100G_RS) { 3543 err = ice_read_64b_phy_reg_e82x(hw, port, 3544 P_REG_PAR_TX_TIME_L, 3545 &val); 3546 if (err) 3547 return err; 3548 3549 total_offset += val; 3550 } 3551 3552 /* Now that the total offset has been calculated, program it to the 3553 * PHY and indicate that the Tx offset is ready. After this, 3554 * timestamps will be enabled. 3555 */ 3556 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_TOTAL_TX_OFFSET_L, 3557 total_offset); 3558 if (err) 3559 return err; 3560 3561 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 1); 3562 if (err) 3563 return err; 3564 3565 dev_info(ice_hw_to_dev(hw), "Port=%d Tx vernier offset calibration complete\n", 3566 port); 3567 3568 return 0; 3569 } 3570 3571 /** 3572 * ice_phy_calc_pmd_adj_e82x - Calculate PMD adjustment for Rx 3573 * @hw: pointer to the HW struct 3574 * @port: the PHY port to adjust for 3575 * @link_spd: the current link speed of the PHY 3576 * @fec_mode: the current FEC mode of the PHY 3577 * @pmd_adj: on return, the amount to adjust the Rx total offset by 3578 * 3579 * Calculates the adjustment to Rx timestamps due to PMD alignment in the PHY. 3580 * This varies by link speed and FEC mode. The value calculated accounts for 3581 * various delays caused when receiving a packet. 3582 */ 3583 static int 3584 ice_phy_calc_pmd_adj_e82x(struct ice_hw *hw, u8 port, 3585 enum ice_ptp_link_spd link_spd, 3586 enum ice_ptp_fec_mode fec_mode, u64 *pmd_adj) 3587 { 3588 u64 cur_freq, clk_incval, tu_per_sec, mult, adj; 3589 u8 pmd_align; 3590 u32 val; 3591 int err; 3592 3593 err = ice_read_phy_reg_e82x(hw, port, P_REG_PMD_ALIGNMENT, &val); 3594 if (err) { 3595 ice_debug(hw, ICE_DBG_PTP, "Failed to read PMD alignment, err %d\n", 3596 err); 3597 return err; 3598 } 3599 3600 pmd_align = (u8)val; 3601 3602 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3603 clk_incval = ice_ptp_read_src_incval(hw); 3604 3605 /* Calculate TUs per second */ 3606 tu_per_sec = cur_freq * clk_incval; 3607 3608 /* The PMD alignment adjustment measurement depends on the link speed, 3609 * and whether FEC is enabled. For each link speed, the alignment 3610 * adjustment is calculated by dividing a value by the length of 3611 * a Time Unit in nanoseconds. 3612 * 3613 * 1G: align == 4 ? 10 * 0.8 : (align + 6 % 10) * 0.8 3614 * 10G: align == 65 ? 0 : (align * 0.1 * 32/33) 3615 * 10G w/FEC: align * 0.1 * 32/33 3616 * 25G: align == 65 ? 0 : (align * 0.4 * 32/33) 3617 * 25G w/FEC: align * 0.4 * 32/33 3618 * 40G: align == 65 ? 0 : (align * 0.1 * 32/33) 3619 * 40G w/FEC: align * 0.1 * 32/33 3620 * 50G: align == 65 ? 0 : (align * 0.4 * 32/33) 3621 * 50G w/FEC: align * 0.8 * 32/33 3622 * 3623 * For RS-FEC, if align is < 17 then we must also add 1.6 * 32/33. 3624 * 3625 * To allow for calculating this value using integer arithmetic, we 3626 * instead start with the number of TUs per second, (inverse of the 3627 * length of a Time Unit in nanoseconds), multiply by a value based 3628 * on the PMD alignment register, and then divide by the right value 3629 * calculated based on the table above. To avoid integer overflow this 3630 * division is broken up into a step of dividing by 125 first. 3631 */ 3632 if (link_spd == ICE_PTP_LNK_SPD_1G) { 3633 if (pmd_align == 4) 3634 mult = 10; 3635 else 3636 mult = (pmd_align + 6) % 10; 3637 } else if (link_spd == ICE_PTP_LNK_SPD_10G || 3638 link_spd == ICE_PTP_LNK_SPD_25G || 3639 link_spd == ICE_PTP_LNK_SPD_40G || 3640 link_spd == ICE_PTP_LNK_SPD_50G) { 3641 /* If Clause 74 FEC, always calculate PMD adjust */ 3642 if (pmd_align != 65 || fec_mode == ICE_PTP_FEC_MODE_CLAUSE74) 3643 mult = pmd_align; 3644 else 3645 mult = 0; 3646 } else if (link_spd == ICE_PTP_LNK_SPD_25G_RS || 3647 link_spd == ICE_PTP_LNK_SPD_50G_RS || 3648 link_spd == ICE_PTP_LNK_SPD_100G_RS) { 3649 if (pmd_align < 17) 3650 mult = pmd_align + 40; 3651 else 3652 mult = pmd_align; 3653 } else { 3654 ice_debug(hw, ICE_DBG_PTP, "Unknown link speed %d, skipping PMD adjustment\n", 3655 link_spd); 3656 mult = 0; 3657 } 3658 3659 /* In some cases, there's no need to adjust for the PMD alignment */ 3660 if (!mult) { 3661 *pmd_adj = 0; 3662 return 0; 3663 } 3664 3665 /* Calculate the adjustment by multiplying TUs per second by the 3666 * appropriate multiplier and divisor. To avoid overflow, we first 3667 * divide by 125, and then handle remaining divisor based on the link 3668 * speed pmd_adj_divisor value. 3669 */ 3670 adj = div_u64(tu_per_sec, 125); 3671 adj *= mult; 3672 adj = div_u64(adj, e822_vernier[link_spd].pmd_adj_divisor); 3673 3674 /* Finally, for 25G-RS and 50G-RS, a further adjustment for the Rx 3675 * cycle count is necessary. 3676 */ 3677 if (link_spd == ICE_PTP_LNK_SPD_25G_RS) { 3678 u64 cycle_adj; 3679 u8 rx_cycle; 3680 3681 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_40_TO_160_CNT, 3682 &val); 3683 if (err) { 3684 ice_debug(hw, ICE_DBG_PTP, "Failed to read 25G-RS Rx cycle count, err %d\n", 3685 err); 3686 return err; 3687 } 3688 3689 rx_cycle = val & P_REG_RX_40_TO_160_CNT_RXCYC_M; 3690 if (rx_cycle) { 3691 mult = (4 - rx_cycle) * 40; 3692 3693 cycle_adj = div_u64(tu_per_sec, 125); 3694 cycle_adj *= mult; 3695 cycle_adj = div_u64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor); 3696 3697 adj += cycle_adj; 3698 } 3699 } else if (link_spd == ICE_PTP_LNK_SPD_50G_RS) { 3700 u64 cycle_adj; 3701 u8 rx_cycle; 3702 3703 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_80_TO_160_CNT, 3704 &val); 3705 if (err) { 3706 ice_debug(hw, ICE_DBG_PTP, "Failed to read 50G-RS Rx cycle count, err %d\n", 3707 err); 3708 return err; 3709 } 3710 3711 rx_cycle = val & P_REG_RX_80_TO_160_CNT_RXCYC_M; 3712 if (rx_cycle) { 3713 mult = rx_cycle * 40; 3714 3715 cycle_adj = div_u64(tu_per_sec, 125); 3716 cycle_adj *= mult; 3717 cycle_adj = div_u64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor); 3718 3719 adj += cycle_adj; 3720 } 3721 } 3722 3723 /* Return the calculated adjustment */ 3724 *pmd_adj = adj; 3725 3726 return 0; 3727 } 3728 3729 /** 3730 * ice_calc_fixed_rx_offset_e82x - Calculated the fixed Rx offset for a port 3731 * @hw: pointer to HW struct 3732 * @link_spd: The Link speed to calculate for 3733 * 3734 * Determine the fixed Rx latency for a given link speed. 3735 */ 3736 static u64 3737 ice_calc_fixed_rx_offset_e82x(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) 3738 { 3739 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset; 3740 3741 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3742 clk_incval = ice_ptp_read_src_incval(hw); 3743 3744 /* Calculate TUs per second */ 3745 tu_per_sec = cur_freq * clk_incval; 3746 3747 /* Calculate number of TUs to add for the fixed Rx latency. Since the 3748 * latency measurement is in 1/100th of a nanosecond, we need to 3749 * multiply by tu_per_sec and then divide by 1e11. This calculation 3750 * overflows 64 bit integer arithmetic, so break it up into two 3751 * divisions by 1e4 first then by 1e7. 3752 */ 3753 fixed_offset = div_u64(tu_per_sec, 10000); 3754 fixed_offset *= e822_vernier[link_spd].rx_fixed_delay; 3755 fixed_offset = div_u64(fixed_offset, 10000000); 3756 3757 return fixed_offset; 3758 } 3759 3760 /** 3761 * ice_phy_cfg_rx_offset_e82x - Configure total Rx timestamp offset 3762 * @hw: pointer to the HW struct 3763 * @port: the PHY port to configure 3764 * 3765 * Program the P_REG_TOTAL_RX_OFFSET register with the number of Time Units to 3766 * adjust Rx timestamps by. This combines calculations from the Vernier offset 3767 * measurements taken in hardware with some data about known fixed delay as 3768 * well as adjusting for multi-lane alignment delay. 3769 * 3770 * This function will not return successfully until the Rx offset calculations 3771 * have been completed, which requires waiting until at least one packet has 3772 * been received by the device. It is safe to call this function periodically 3773 * until calibration succeeds, as it will only program the offset once. 3774 * 3775 * This function must be called only after the offset registers are valid, 3776 * i.e. after the Vernier calibration wait has passed, to ensure that the PHY 3777 * has measured the offset. 3778 * 3779 * To avoid overflow, when calculating the offset based on the known static 3780 * latency values, we use measurements in 1/100th of a nanosecond, and divide 3781 * the TUs per second up front. This avoids overflow while allowing 3782 * calculation of the adjustment using integer arithmetic. 3783 * 3784 * Returns zero on success, -EBUSY if the hardware vernier offset 3785 * calibration has not completed, or another error code on failure. 3786 */ 3787 int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port) 3788 { 3789 enum ice_ptp_link_spd link_spd; 3790 enum ice_ptp_fec_mode fec_mode; 3791 u64 total_offset, pmd, val; 3792 int err; 3793 u32 reg; 3794 3795 /* Nothing to do if we've already programmed the offset */ 3796 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_OR, ®); 3797 if (err) { 3798 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OR for port %u, err %d\n", 3799 port, err); 3800 return err; 3801 } 3802 3803 if (reg) 3804 return 0; 3805 3806 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_OV_STATUS, ®); 3807 if (err) { 3808 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OV_STATUS for port %u, err %d\n", 3809 port, err); 3810 return err; 3811 } 3812 3813 if (!(reg & P_REG_RX_OV_STATUS_OV_M)) 3814 return -EBUSY; 3815 3816 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode); 3817 if (err) 3818 return err; 3819 3820 total_offset = ice_calc_fixed_rx_offset_e82x(hw, link_spd); 3821 3822 /* Read the first Vernier offset from the PHY register and add it to 3823 * the total offset. 3824 */ 3825 err = ice_read_64b_phy_reg_e82x(hw, port, 3826 P_REG_PAR_PCS_RX_OFFSET_L, 3827 &val); 3828 if (err) 3829 return err; 3830 3831 total_offset += val; 3832 3833 /* For Rx, all multi-lane link speeds include a second Vernier 3834 * calibration, because the lanes might not be aligned. 3835 */ 3836 if (link_spd == ICE_PTP_LNK_SPD_40G || 3837 link_spd == ICE_PTP_LNK_SPD_50G || 3838 link_spd == ICE_PTP_LNK_SPD_50G_RS || 3839 link_spd == ICE_PTP_LNK_SPD_100G_RS) { 3840 err = ice_read_64b_phy_reg_e82x(hw, port, 3841 P_REG_PAR_RX_TIME_L, 3842 &val); 3843 if (err) 3844 return err; 3845 3846 total_offset += val; 3847 } 3848 3849 /* In addition, Rx must account for the PMD alignment */ 3850 err = ice_phy_calc_pmd_adj_e82x(hw, port, link_spd, fec_mode, &pmd); 3851 if (err) 3852 return err; 3853 3854 /* For RS-FEC, this adjustment adds delay, but for other modes, it 3855 * subtracts delay. 3856 */ 3857 if (fec_mode == ICE_PTP_FEC_MODE_RS_FEC) 3858 total_offset += pmd; 3859 else 3860 total_offset -= pmd; 3861 3862 /* Now that the total offset has been calculated, program it to the 3863 * PHY and indicate that the Rx offset is ready. After this, 3864 * timestamps will be enabled. 3865 */ 3866 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_TOTAL_RX_OFFSET_L, 3867 total_offset); 3868 if (err) 3869 return err; 3870 3871 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 1); 3872 if (err) 3873 return err; 3874 3875 dev_info(ice_hw_to_dev(hw), "Port=%d Rx vernier offset calibration complete\n", 3876 port); 3877 3878 return 0; 3879 } 3880 3881 /** 3882 * ice_ptp_clear_phy_offset_ready_e82x - Clear PHY TX_/RX_OFFSET_READY registers 3883 * @hw: pointer to the HW struct 3884 * 3885 * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted 3886 * and received timestamps as invalid. 3887 * 3888 * Return: 0 on success, other error codes when failed to write to PHY 3889 */ 3890 int ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw *hw) 3891 { 3892 u8 port; 3893 3894 for (port = 0; port < hw->ptp.num_lports; port++) { 3895 int err; 3896 3897 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0); 3898 if (err) { 3899 dev_warn(ice_hw_to_dev(hw), 3900 "Failed to clear PHY TX_OFFSET_READY register\n"); 3901 return err; 3902 } 3903 3904 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0); 3905 if (err) { 3906 dev_warn(ice_hw_to_dev(hw), 3907 "Failed to clear PHY RX_OFFSET_READY register\n"); 3908 return err; 3909 } 3910 } 3911 3912 return 0; 3913 } 3914 3915 /** 3916 * ice_read_phy_and_phc_time_e82x - Simultaneously capture PHC and PHY time 3917 * @hw: pointer to the HW struct 3918 * @port: the PHY port to read 3919 * @phy_time: on return, the 64bit PHY timer value 3920 * @phc_time: on return, the lower 64bits of PHC time 3921 * 3922 * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY 3923 * and PHC timer values. 3924 */ 3925 static int 3926 ice_read_phy_and_phc_time_e82x(struct ice_hw *hw, u8 port, u64 *phy_time, 3927 u64 *phc_time) 3928 { 3929 u64 tx_time, rx_time; 3930 u32 zo, lo; 3931 u8 tmr_idx; 3932 int err; 3933 3934 tmr_idx = ice_get_ptp_src_clock_index(hw); 3935 3936 /* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */ 3937 ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME); 3938 3939 /* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */ 3940 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME); 3941 if (err) 3942 return err; 3943 3944 /* Issue the sync to start the ICE_PTP_READ_TIME capture */ 3945 ice_ptp_exec_tmr_cmd(hw); 3946 3947 /* Read the captured PHC time from the shadow time registers */ 3948 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx)); 3949 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx)); 3950 *phc_time = (u64)lo << 32 | zo; 3951 3952 /* Read the captured PHY time from the PHY shadow registers */ 3953 err = ice_ptp_read_port_capture(hw, port, &tx_time, &rx_time); 3954 if (err) 3955 return err; 3956 3957 /* If the PHY Tx and Rx timers don't match, log a warning message. 3958 * Note that this should not happen in normal circumstances since the 3959 * driver always programs them together. 3960 */ 3961 if (tx_time != rx_time) 3962 dev_warn(ice_hw_to_dev(hw), 3963 "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n", 3964 port, (unsigned long long)tx_time, 3965 (unsigned long long)rx_time); 3966 3967 *phy_time = tx_time; 3968 3969 return 0; 3970 } 3971 3972 /** 3973 * ice_sync_phy_timer_e82x - Synchronize the PHY timer with PHC timer 3974 * @hw: pointer to the HW struct 3975 * @port: the PHY port to synchronize 3976 * 3977 * Perform an adjustment to ensure that the PHY and PHC timers are in sync. 3978 * This is done by issuing a ICE_PTP_READ_TIME command which triggers a 3979 * simultaneous read of the PHY timer and PHC timer. Then we use the 3980 * difference to calculate an appropriate 2s complement addition to add 3981 * to the PHY timer in order to ensure it reads the same value as the 3982 * primary PHC timer. 3983 */ 3984 static int ice_sync_phy_timer_e82x(struct ice_hw *hw, u8 port) 3985 { 3986 u64 phc_time, phy_time, difference; 3987 int err; 3988 3989 if (!ice_ptp_lock(hw)) { 3990 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n"); 3991 return -EBUSY; 3992 } 3993 3994 err = ice_read_phy_and_phc_time_e82x(hw, port, &phy_time, &phc_time); 3995 if (err) 3996 goto err_unlock; 3997 3998 /* Calculate the amount required to add to the port time in order for 3999 * it to match the PHC time. 4000 * 4001 * Note that the port adjustment is done using 2s complement 4002 * arithmetic. This is convenient since it means that we can simply 4003 * calculate the difference between the PHC time and the port time, 4004 * and it will be interpreted correctly. 4005 */ 4006 difference = phc_time - phy_time; 4007 4008 err = ice_ptp_prep_port_adj_e82x(hw, port, (s64)difference); 4009 if (err) 4010 goto err_unlock; 4011 4012 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME); 4013 if (err) 4014 goto err_unlock; 4015 4016 /* Do not perform any action on the main timer */ 4017 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 4018 4019 /* Issue the sync to activate the time adjustment */ 4020 ice_ptp_exec_tmr_cmd(hw); 4021 4022 /* Re-capture the timer values to flush the command registers and 4023 * verify that the time was properly adjusted. 4024 */ 4025 err = ice_read_phy_and_phc_time_e82x(hw, port, &phy_time, &phc_time); 4026 if (err) 4027 goto err_unlock; 4028 4029 dev_info(ice_hw_to_dev(hw), 4030 "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n", 4031 port, (unsigned long long)phy_time, 4032 (unsigned long long)phc_time); 4033 4034 ice_ptp_unlock(hw); 4035 4036 return 0; 4037 4038 err_unlock: 4039 ice_ptp_unlock(hw); 4040 return err; 4041 } 4042 4043 /** 4044 * ice_stop_phy_timer_e82x - Stop the PHY clock timer 4045 * @hw: pointer to the HW struct 4046 * @port: the PHY port to stop 4047 * @soft_reset: if true, hold the SOFT_RESET bit of P_REG_PS 4048 * 4049 * Stop the clock of a PHY port. This must be done as part of the flow to 4050 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 4051 * initialized or when link speed changes. 4052 */ 4053 int 4054 ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset) 4055 { 4056 int err; 4057 u32 val; 4058 4059 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0); 4060 if (err) 4061 return err; 4062 4063 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0); 4064 if (err) 4065 return err; 4066 4067 err = ice_read_phy_reg_e82x(hw, port, P_REG_PS, &val); 4068 if (err) 4069 return err; 4070 4071 val &= ~P_REG_PS_START_M; 4072 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4073 if (err) 4074 return err; 4075 4076 val &= ~P_REG_PS_ENA_CLK_M; 4077 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4078 if (err) 4079 return err; 4080 4081 if (soft_reset) { 4082 val |= P_REG_PS_SFT_RESET_M; 4083 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4084 if (err) 4085 return err; 4086 } 4087 4088 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port); 4089 4090 return 0; 4091 } 4092 4093 /** 4094 * ice_start_phy_timer_e82x - Start the PHY clock timer 4095 * @hw: pointer to the HW struct 4096 * @port: the PHY port to start 4097 * 4098 * Start the clock of a PHY port. This must be done as part of the flow to 4099 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 4100 * initialized or when link speed changes. 4101 * 4102 * Hardware will take Vernier measurements on Tx or Rx of packets. 4103 */ 4104 int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port) 4105 { 4106 u32 lo, hi, val; 4107 u64 incval; 4108 u8 tmr_idx; 4109 int err; 4110 4111 tmr_idx = ice_get_ptp_src_clock_index(hw); 4112 4113 err = ice_stop_phy_timer_e82x(hw, port, false); 4114 if (err) 4115 return err; 4116 4117 ice_phy_cfg_lane_e82x(hw, port); 4118 4119 err = ice_phy_cfg_uix_e82x(hw, port); 4120 if (err) 4121 return err; 4122 4123 err = ice_phy_cfg_parpcs_e82x(hw, port); 4124 if (err) 4125 return err; 4126 4127 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 4128 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 4129 incval = (u64)hi << 32 | lo; 4130 4131 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L, incval); 4132 if (err) 4133 return err; 4134 4135 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL); 4136 if (err) 4137 return err; 4138 4139 /* Do not perform any action on the main timer */ 4140 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 4141 4142 ice_ptp_exec_tmr_cmd(hw); 4143 4144 err = ice_read_phy_reg_e82x(hw, port, P_REG_PS, &val); 4145 if (err) 4146 return err; 4147 4148 val |= P_REG_PS_SFT_RESET_M; 4149 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4150 if (err) 4151 return err; 4152 4153 val |= P_REG_PS_START_M; 4154 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4155 if (err) 4156 return err; 4157 4158 val &= ~P_REG_PS_SFT_RESET_M; 4159 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4160 if (err) 4161 return err; 4162 4163 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL); 4164 if (err) 4165 return err; 4166 4167 ice_ptp_exec_tmr_cmd(hw); 4168 4169 val |= P_REG_PS_ENA_CLK_M; 4170 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4171 if (err) 4172 return err; 4173 4174 val |= P_REG_PS_LOAD_OFFSET_M; 4175 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4176 if (err) 4177 return err; 4178 4179 ice_ptp_exec_tmr_cmd(hw); 4180 4181 err = ice_sync_phy_timer_e82x(hw, port); 4182 if (err) 4183 return err; 4184 4185 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port); 4186 4187 return 0; 4188 } 4189 4190 /** 4191 * ice_get_phy_tx_tstamp_ready_e82x - Read Tx memory status register 4192 * @hw: pointer to the HW struct 4193 * @quad: the timestamp quad to read from 4194 * @tstamp_ready: contents of the Tx memory status register 4195 * 4196 * Read the Q_REG_TX_MEMORY_STATUS register indicating which timestamps in 4197 * the PHY are ready. A set bit means the corresponding timestamp is valid and 4198 * ready to be captured from the PHY timestamp block. 4199 */ 4200 static int 4201 ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw *hw, u8 quad, u64 *tstamp_ready) 4202 { 4203 u32 hi, lo; 4204 int err; 4205 4206 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_U, &hi); 4207 if (err) { 4208 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_U for quad %u, err %d\n", 4209 quad, err); 4210 return err; 4211 } 4212 4213 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_L, &lo); 4214 if (err) { 4215 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_L for quad %u, err %d\n", 4216 quad, err); 4217 return err; 4218 } 4219 4220 *tstamp_ready = (u64)hi << 32 | (u64)lo; 4221 4222 return 0; 4223 } 4224 4225 /** 4226 * ice_phy_cfg_intr_e82x - Configure TX timestamp interrupt 4227 * @hw: pointer to the HW struct 4228 * @quad: the timestamp quad 4229 * @ena: enable or disable interrupt 4230 * @threshold: interrupt threshold 4231 * 4232 * Configure TX timestamp interrupt for the specified quad 4233 * 4234 * Return: 0 on success, other error codes when failed to read/write quad 4235 */ 4236 4237 int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold) 4238 { 4239 int err; 4240 u32 val; 4241 4242 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val); 4243 if (err) 4244 return err; 4245 4246 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M; 4247 if (ena) { 4248 val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M; 4249 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M; 4250 val |= FIELD_PREP(Q_REG_TX_MEM_GBL_CFG_INTR_THR_M, threshold); 4251 } 4252 4253 return ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val); 4254 } 4255 4256 /** 4257 * ice_ptp_init_phy_e82x - initialize PHY parameters 4258 * @ptp: pointer to the PTP HW struct 4259 */ 4260 static void ice_ptp_init_phy_e82x(struct ice_ptp_hw *ptp) 4261 { 4262 ptp->num_lports = 8; 4263 ptp->ports_per_phy = 8; 4264 } 4265 4266 /* E810 functions 4267 * 4268 * The following functions operate on the E810 series devices which use 4269 * a separate external PHY. 4270 */ 4271 4272 /** 4273 * ice_read_phy_reg_e810 - Read register from external PHY on E810 4274 * @hw: pointer to the HW struct 4275 * @addr: the address to read from 4276 * @val: On return, the value read from the PHY 4277 * 4278 * Read a register from the external PHY on the E810 device. 4279 */ 4280 static int ice_read_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 *val) 4281 { 4282 struct ice_sbq_msg_input msg = {0}; 4283 int err; 4284 4285 msg.msg_addr_low = lower_16_bits(addr); 4286 msg.msg_addr_high = upper_16_bits(addr); 4287 msg.opcode = ice_sbq_msg_rd; 4288 msg.dest_dev = ice_sbq_dev_phy_0; 4289 4290 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 4291 if (err) { 4292 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 4293 err); 4294 return err; 4295 } 4296 4297 *val = msg.data; 4298 4299 return 0; 4300 } 4301 4302 /** 4303 * ice_write_phy_reg_e810 - Write register on external PHY on E810 4304 * @hw: pointer to the HW struct 4305 * @addr: the address to writem to 4306 * @val: the value to write to the PHY 4307 * 4308 * Write a value to a register of the external PHY on the E810 device. 4309 */ 4310 static int ice_write_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 val) 4311 { 4312 struct ice_sbq_msg_input msg = {0}; 4313 int err; 4314 4315 msg.msg_addr_low = lower_16_bits(addr); 4316 msg.msg_addr_high = upper_16_bits(addr); 4317 msg.opcode = ice_sbq_msg_wr; 4318 msg.dest_dev = ice_sbq_dev_phy_0; 4319 msg.data = val; 4320 4321 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 4322 if (err) { 4323 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 4324 err); 4325 return err; 4326 } 4327 4328 return 0; 4329 } 4330 4331 /** 4332 * ice_read_phy_tstamp_ll_e810 - Read a PHY timestamp registers through the FW 4333 * @hw: pointer to the HW struct 4334 * @idx: the timestamp index to read 4335 * @hi: 8 bit timestamp high value 4336 * @lo: 32 bit timestamp low value 4337 * 4338 * Read a 8bit timestamp high value and 32 bit timestamp low value out of the 4339 * timestamp block of the external PHY on the E810 device using the low latency 4340 * timestamp read. 4341 */ 4342 static int 4343 ice_read_phy_tstamp_ll_e810(struct ice_hw *hw, u8 idx, u8 *hi, u32 *lo) 4344 { 4345 struct ice_e810_params *params = &hw->ptp.phy.e810; 4346 unsigned long flags; 4347 u32 val; 4348 int err; 4349 4350 spin_lock_irqsave(¶ms->atqbal_wq.lock, flags); 4351 4352 /* Wait for any pending in-progress low latency interrupt */ 4353 err = wait_event_interruptible_locked_irq(params->atqbal_wq, 4354 !(params->atqbal_flags & 4355 ATQBAL_FLAGS_INTR_IN_PROGRESS)); 4356 if (err) { 4357 spin_unlock_irqrestore(¶ms->atqbal_wq.lock, flags); 4358 return err; 4359 } 4360 4361 /* Write TS index to read to the PF register so the FW can read it */ 4362 val = FIELD_PREP(REG_LL_PROXY_H_TS_IDX, idx) | REG_LL_PROXY_H_EXEC; 4363 wr32(hw, REG_LL_PROXY_H, val); 4364 4365 /* Read the register repeatedly until the FW provides us the TS */ 4366 err = read_poll_timeout_atomic(rd32, val, 4367 !FIELD_GET(REG_LL_PROXY_H_EXEC, val), 10, 4368 REG_LL_PROXY_H_TIMEOUT_US, false, hw, 4369 REG_LL_PROXY_H); 4370 if (err) { 4371 ice_debug(hw, ICE_DBG_PTP, "Failed to read PTP timestamp using low latency read\n"); 4372 spin_unlock_irqrestore(¶ms->atqbal_wq.lock, flags); 4373 return err; 4374 } 4375 4376 /* High 8 bit value of the TS is on the bits 16:23 */ 4377 *hi = FIELD_GET(REG_LL_PROXY_H_TS_HIGH, val); 4378 4379 /* Read the low 32 bit value and set the TS valid bit */ 4380 *lo = rd32(hw, REG_LL_PROXY_L) | TS_VALID; 4381 4382 spin_unlock_irqrestore(¶ms->atqbal_wq.lock, flags); 4383 4384 return 0; 4385 } 4386 4387 /** 4388 * ice_read_phy_tstamp_sbq_e810 - Read a PHY timestamp registers through the sbq 4389 * @hw: pointer to the HW struct 4390 * @lport: the lport to read from 4391 * @idx: the timestamp index to read 4392 * @hi: 8 bit timestamp high value 4393 * @lo: 32 bit timestamp low value 4394 * 4395 * Read a 8bit timestamp high value and 32 bit timestamp low value out of the 4396 * timestamp block of the external PHY on the E810 device using sideband queue. 4397 */ 4398 static int 4399 ice_read_phy_tstamp_sbq_e810(struct ice_hw *hw, u8 lport, u8 idx, u8 *hi, 4400 u32 *lo) 4401 { 4402 u32 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); 4403 u32 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); 4404 u32 lo_val, hi_val; 4405 int err; 4406 4407 err = ice_read_phy_reg_e810(hw, lo_addr, &lo_val); 4408 if (err) { 4409 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 4410 err); 4411 return err; 4412 } 4413 4414 err = ice_read_phy_reg_e810(hw, hi_addr, &hi_val); 4415 if (err) { 4416 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 4417 err); 4418 return err; 4419 } 4420 4421 *lo = lo_val; 4422 *hi = (u8)hi_val; 4423 4424 return 0; 4425 } 4426 4427 /** 4428 * ice_read_phy_tstamp_e810 - Read a PHY timestamp out of the external PHY 4429 * @hw: pointer to the HW struct 4430 * @lport: the lport to read from 4431 * @idx: the timestamp index to read 4432 * @tstamp: on return, the 40bit timestamp value 4433 * 4434 * Read a 40bit timestamp value out of the timestamp block of the external PHY 4435 * on the E810 device. 4436 */ 4437 static int 4438 ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) 4439 { 4440 u32 lo = 0; 4441 u8 hi = 0; 4442 int err; 4443 4444 if (hw->dev_caps.ts_dev_info.ts_ll_read) 4445 err = ice_read_phy_tstamp_ll_e810(hw, idx, &hi, &lo); 4446 else 4447 err = ice_read_phy_tstamp_sbq_e810(hw, lport, idx, &hi, &lo); 4448 4449 if (err) 4450 return err; 4451 4452 /* For E810 devices, the timestamp is reported with the lower 32 bits 4453 * in the low register, and the upper 8 bits in the high register. 4454 */ 4455 *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) | 4456 FIELD_PREP(PHY_EXT_40B_LOW_M, lo); 4457 4458 return 0; 4459 } 4460 4461 /** 4462 * ice_clear_phy_tstamp_e810 - Clear a timestamp from the external PHY 4463 * @hw: pointer to the HW struct 4464 * @lport: the lport to read from 4465 * @idx: the timestamp index to reset 4466 * 4467 * Read the timestamp and then forcibly overwrite its value to clear the valid 4468 * bit from the timestamp block of the external PHY on the E810 device. 4469 * 4470 * This function should only be called on an idx whose bit is set according to 4471 * ice_get_phy_tx_tstamp_ready(). 4472 */ 4473 static int ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx) 4474 { 4475 u32 lo_addr, hi_addr; 4476 u64 unused_tstamp; 4477 int err; 4478 4479 err = ice_read_phy_tstamp_e810(hw, lport, idx, &unused_tstamp); 4480 if (err) { 4481 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for lport %u, idx %u, err %d\n", 4482 lport, idx, err); 4483 return err; 4484 } 4485 4486 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); 4487 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); 4488 4489 err = ice_write_phy_reg_e810(hw, lo_addr, 0); 4490 if (err) { 4491 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for lport %u, idx %u, err %d\n", 4492 lport, idx, err); 4493 return err; 4494 } 4495 4496 err = ice_write_phy_reg_e810(hw, hi_addr, 0); 4497 if (err) { 4498 ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register for lport %u, idx %u, err %d\n", 4499 lport, idx, err); 4500 return err; 4501 } 4502 4503 return 0; 4504 } 4505 4506 /** 4507 * ice_ptp_init_phc_e810 - Perform E810 specific PHC initialization 4508 * @hw: pointer to HW struct 4509 * 4510 * Perform E810-specific PTP hardware clock initialization steps. 4511 * 4512 * Return: 0 on success, other error codes when failed to initialize TimeSync 4513 */ 4514 static int ice_ptp_init_phc_e810(struct ice_hw *hw) 4515 { 4516 u8 tmr_idx; 4517 int err; 4518 4519 ice_ptp_cfg_sync_delay(hw, ICE_E810_E830_SYNC_DELAY); 4520 4521 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 4522 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_ENA(tmr_idx), 4523 GLTSYN_ENA_TSYN_ENA_M); 4524 if (err) 4525 ice_debug(hw, ICE_DBG_PTP, "PTP failed in ena_phy_time_syn %d\n", 4526 err); 4527 4528 return err; 4529 } 4530 4531 /** 4532 * ice_ptp_prep_phy_time_e810 - Prepare PHY port with initial time 4533 * @hw: Board private structure 4534 * @time: Time to initialize the PHY port clock to 4535 * 4536 * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the 4537 * initial clock time. The time will not actually be programmed until the 4538 * driver issues an ICE_PTP_INIT_TIME command. 4539 * 4540 * The time value is the upper 32 bits of the PHY timer, usually in units of 4541 * nominal nanoseconds. 4542 */ 4543 static int ice_ptp_prep_phy_time_e810(struct ice_hw *hw, u32 time) 4544 { 4545 u8 tmr_idx; 4546 int err; 4547 4548 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 4549 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_0(tmr_idx), 0); 4550 if (err) { 4551 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_0, err %d\n", 4552 err); 4553 return err; 4554 } 4555 4556 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_L(tmr_idx), time); 4557 if (err) { 4558 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_L, err %d\n", 4559 err); 4560 return err; 4561 } 4562 4563 return 0; 4564 } 4565 4566 /** 4567 * ice_ptp_prep_phy_adj_ll_e810 - Prep PHY ports for a time adjustment 4568 * @hw: pointer to HW struct 4569 * @adj: adjustment value to program 4570 * 4571 * Use the low latency firmware interface to program PHY time adjustment to 4572 * all PHY ports. 4573 * 4574 * Return: 0 on success, -EBUSY on timeout 4575 */ 4576 static int ice_ptp_prep_phy_adj_ll_e810(struct ice_hw *hw, s32 adj) 4577 { 4578 const u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 4579 struct ice_e810_params *params = &hw->ptp.phy.e810; 4580 u32 val; 4581 int err; 4582 4583 spin_lock_irq(¶ms->atqbal_wq.lock); 4584 4585 /* Wait for any pending in-progress low latency interrupt */ 4586 err = wait_event_interruptible_locked_irq(params->atqbal_wq, 4587 !(params->atqbal_flags & 4588 ATQBAL_FLAGS_INTR_IN_PROGRESS)); 4589 if (err) { 4590 spin_unlock_irq(¶ms->atqbal_wq.lock); 4591 return err; 4592 } 4593 4594 wr32(hw, REG_LL_PROXY_L, adj); 4595 val = FIELD_PREP(REG_LL_PROXY_H_PHY_TMR_CMD_M, REG_LL_PROXY_H_PHY_TMR_CMD_ADJ) | 4596 FIELD_PREP(REG_LL_PROXY_H_PHY_TMR_IDX_M, tmr_idx) | REG_LL_PROXY_H_EXEC; 4597 wr32(hw, REG_LL_PROXY_H, val); 4598 4599 /* Read the register repeatedly until the FW indicates completion */ 4600 err = read_poll_timeout_atomic(rd32, val, 4601 !FIELD_GET(REG_LL_PROXY_H_EXEC, val), 4602 10, REG_LL_PROXY_H_TIMEOUT_US, false, hw, 4603 REG_LL_PROXY_H); 4604 if (err) { 4605 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY timer adjustment using low latency interface\n"); 4606 spin_unlock_irq(¶ms->atqbal_wq.lock); 4607 return err; 4608 } 4609 4610 spin_unlock_irq(¶ms->atqbal_wq.lock); 4611 4612 return 0; 4613 } 4614 4615 /** 4616 * ice_ptp_prep_phy_adj_e810 - Prep PHY port for a time adjustment 4617 * @hw: pointer to HW struct 4618 * @adj: adjustment value to program 4619 * 4620 * Prepare the PHY port for an atomic adjustment by programming the PHY 4621 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual adjustment 4622 * is completed by issuing an ICE_PTP_ADJ_TIME sync command. 4623 * 4624 * The adjustment value only contains the portion used for the upper 32bits of 4625 * the PHY timer, usually in units of nominal nanoseconds. Negative 4626 * adjustments are supported using 2s complement arithmetic. 4627 */ 4628 static int ice_ptp_prep_phy_adj_e810(struct ice_hw *hw, s32 adj) 4629 { 4630 u8 tmr_idx; 4631 int err; 4632 4633 if (hw->dev_caps.ts_dev_info.ll_phy_tmr_update) 4634 return ice_ptp_prep_phy_adj_ll_e810(hw, adj); 4635 4636 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 4637 4638 /* Adjustments are represented as signed 2's complement values in 4639 * nanoseconds. Sub-nanosecond adjustment is not supported. 4640 */ 4641 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), 0); 4642 if (err) { 4643 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_L, err %d\n", 4644 err); 4645 return err; 4646 } 4647 4648 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), adj); 4649 if (err) { 4650 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_H, err %d\n", 4651 err); 4652 return err; 4653 } 4654 4655 return 0; 4656 } 4657 4658 /** 4659 * ice_ptp_prep_phy_incval_ll_e810 - Prep PHY ports increment value change 4660 * @hw: pointer to HW struct 4661 * @incval: The new 40bit increment value to prepare 4662 * 4663 * Use the low latency firmware interface to program PHY time increment value 4664 * for all PHY ports. 4665 * 4666 * Return: 0 on success, -EBUSY on timeout 4667 */ 4668 static int ice_ptp_prep_phy_incval_ll_e810(struct ice_hw *hw, u64 incval) 4669 { 4670 const u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 4671 struct ice_e810_params *params = &hw->ptp.phy.e810; 4672 u32 val; 4673 int err; 4674 4675 spin_lock_irq(¶ms->atqbal_wq.lock); 4676 4677 /* Wait for any pending in-progress low latency interrupt */ 4678 err = wait_event_interruptible_locked_irq(params->atqbal_wq, 4679 !(params->atqbal_flags & 4680 ATQBAL_FLAGS_INTR_IN_PROGRESS)); 4681 if (err) { 4682 spin_unlock_irq(¶ms->atqbal_wq.lock); 4683 return err; 4684 } 4685 4686 wr32(hw, REG_LL_PROXY_L, lower_32_bits(incval)); 4687 val = FIELD_PREP(REG_LL_PROXY_H_PHY_TMR_CMD_M, REG_LL_PROXY_H_PHY_TMR_CMD_FREQ) | 4688 FIELD_PREP(REG_LL_PROXY_H_TS_HIGH, (u8)upper_32_bits(incval)) | 4689 FIELD_PREP(REG_LL_PROXY_H_PHY_TMR_IDX_M, tmr_idx) | REG_LL_PROXY_H_EXEC; 4690 wr32(hw, REG_LL_PROXY_H, val); 4691 4692 /* Read the register repeatedly until the FW indicates completion */ 4693 err = read_poll_timeout_atomic(rd32, val, 4694 !FIELD_GET(REG_LL_PROXY_H_EXEC, val), 4695 10, REG_LL_PROXY_H_TIMEOUT_US, false, hw, 4696 REG_LL_PROXY_H); 4697 if (err) { 4698 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY timer increment using low latency interface\n"); 4699 spin_unlock_irq(¶ms->atqbal_wq.lock); 4700 return err; 4701 } 4702 4703 spin_unlock_irq(¶ms->atqbal_wq.lock); 4704 4705 return 0; 4706 } 4707 4708 /** 4709 * ice_ptp_prep_phy_incval_e810 - Prep PHY port increment value change 4710 * @hw: pointer to HW struct 4711 * @incval: The new 40bit increment value to prepare 4712 * 4713 * Prepare the PHY port for a new increment value by programming the PHY 4714 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual change is 4715 * completed by issuing an ICE_PTP_INIT_INCVAL command. 4716 */ 4717 static int ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval) 4718 { 4719 u32 high, low; 4720 u8 tmr_idx; 4721 int err; 4722 4723 if (hw->dev_caps.ts_dev_info.ll_phy_tmr_update) 4724 return ice_ptp_prep_phy_incval_ll_e810(hw, incval); 4725 4726 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 4727 low = lower_32_bits(incval); 4728 high = upper_32_bits(incval); 4729 4730 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), low); 4731 if (err) { 4732 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval to PHY SHADJ_L, err %d\n", 4733 err); 4734 return err; 4735 } 4736 4737 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), high); 4738 if (err) { 4739 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval PHY SHADJ_H, err %d\n", 4740 err); 4741 return err; 4742 } 4743 4744 return 0; 4745 } 4746 4747 /** 4748 * ice_ptp_port_cmd_e810 - Prepare all external PHYs for a timer command 4749 * @hw: pointer to HW struct 4750 * @cmd: Command to be sent to the port 4751 * 4752 * Prepare the external PHYs connected to this device for a timer sync 4753 * command. 4754 */ 4755 static int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 4756 { 4757 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 4758 4759 return ice_write_phy_reg_e810(hw, E810_ETH_GLTSYN_CMD, val); 4760 } 4761 4762 /** 4763 * ice_get_phy_tx_tstamp_ready_e810 - Read Tx memory status register 4764 * @hw: pointer to the HW struct 4765 * @port: the PHY port to read 4766 * @tstamp_ready: contents of the Tx memory status register 4767 * 4768 * E810 devices do not use a Tx memory status register. Instead simply 4769 * indicate that all timestamps are currently ready. 4770 */ 4771 static int 4772 ice_get_phy_tx_tstamp_ready_e810(struct ice_hw *hw, u8 port, u64 *tstamp_ready) 4773 { 4774 *tstamp_ready = 0xFFFFFFFFFFFFFFFF; 4775 return 0; 4776 } 4777 4778 /* E810 SMA functions 4779 * 4780 * The following functions operate specifically on E810 hardware and are used 4781 * to access the extended GPIOs available. 4782 */ 4783 4784 /** 4785 * ice_read_sma_ctrl 4786 * @hw: pointer to the hw struct 4787 * @data: pointer to data to be read from the GPIO controller 4788 * 4789 * Read the SMA controller state. It is connected to pins 3-7 of Port 1 of the 4790 * PCA9575 expander, so only bits 3-7 in data are valid. 4791 */ 4792 int ice_read_sma_ctrl(struct ice_hw *hw, u8 *data) 4793 { 4794 int status; 4795 u16 handle; 4796 u8 i; 4797 4798 status = ice_get_pca9575_handle(hw, &handle); 4799 if (status) 4800 return status; 4801 4802 *data = 0; 4803 4804 for (i = ICE_SMA_MIN_BIT; i <= ICE_SMA_MAX_BIT; i++) { 4805 bool pin; 4806 4807 status = ice_aq_get_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET, 4808 &pin, NULL); 4809 if (status) 4810 break; 4811 *data |= (u8)(!pin) << i; 4812 } 4813 4814 return status; 4815 } 4816 4817 /** 4818 * ice_write_sma_ctrl 4819 * @hw: pointer to the hw struct 4820 * @data: data to be written to the GPIO controller 4821 * 4822 * Write the data to the SMA controller. It is connected to pins 3-7 of Port 1 4823 * of the PCA9575 expander, so only bits 3-7 in data are valid. 4824 */ 4825 int ice_write_sma_ctrl(struct ice_hw *hw, u8 data) 4826 { 4827 int status; 4828 u16 handle; 4829 u8 i; 4830 4831 status = ice_get_pca9575_handle(hw, &handle); 4832 if (status) 4833 return status; 4834 4835 for (i = ICE_SMA_MIN_BIT; i <= ICE_SMA_MAX_BIT; i++) { 4836 bool pin; 4837 4838 pin = !(data & (1 << i)); 4839 status = ice_aq_set_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET, 4840 pin, NULL); 4841 if (status) 4842 break; 4843 } 4844 4845 return status; 4846 } 4847 4848 /** 4849 * ice_ptp_read_sdp_ac - read SDP available connections section from NVM 4850 * @hw: pointer to the HW struct 4851 * @entries: returns the SDP available connections section from NVM 4852 * @num_entries: returns the number of valid entries 4853 * 4854 * Return: 0 on success, negative error code if NVM read failed or section does 4855 * not exist or is corrupted 4856 */ 4857 int ice_ptp_read_sdp_ac(struct ice_hw *hw, __le16 *entries, uint *num_entries) 4858 { 4859 __le16 data; 4860 u32 offset; 4861 int err; 4862 4863 err = ice_acquire_nvm(hw, ICE_RES_READ); 4864 if (err) 4865 goto exit; 4866 4867 /* Read the offset of SDP_AC */ 4868 offset = ICE_AQC_NVM_SDP_AC_PTR_OFFSET; 4869 err = ice_aq_read_nvm(hw, 0, offset, sizeof(data), &data, false, true, 4870 NULL); 4871 if (err) 4872 goto exit; 4873 4874 /* Check if section exist */ 4875 offset = FIELD_GET(ICE_AQC_NVM_SDP_AC_PTR_M, le16_to_cpu(data)); 4876 if (offset == ICE_AQC_NVM_SDP_AC_PTR_INVAL) { 4877 err = -EINVAL; 4878 goto exit; 4879 } 4880 4881 if (offset & ICE_AQC_NVM_SDP_AC_PTR_TYPE_M) { 4882 offset &= ICE_AQC_NVM_SDP_AC_PTR_M; 4883 offset *= ICE_AQC_NVM_SECTOR_UNIT; 4884 } else { 4885 offset *= sizeof(data); 4886 } 4887 4888 /* Skip reading section length and read the number of valid entries */ 4889 offset += sizeof(data); 4890 err = ice_aq_read_nvm(hw, 0, offset, sizeof(data), &data, false, true, 4891 NULL); 4892 if (err) 4893 goto exit; 4894 *num_entries = le16_to_cpu(data); 4895 4896 /* Read SDP configuration section */ 4897 offset += sizeof(data); 4898 err = ice_aq_read_nvm(hw, 0, offset, *num_entries * sizeof(data), 4899 entries, false, true, NULL); 4900 4901 exit: 4902 if (err) 4903 dev_dbg(ice_hw_to_dev(hw), "Failed to configure SDP connection section\n"); 4904 ice_release_nvm(hw); 4905 return err; 4906 } 4907 4908 /** 4909 * ice_ptp_init_phy_e810 - initialize PHY parameters 4910 * @ptp: pointer to the PTP HW struct 4911 */ 4912 static void ice_ptp_init_phy_e810(struct ice_ptp_hw *ptp) 4913 { 4914 ptp->num_lports = 8; 4915 ptp->ports_per_phy = 4; 4916 4917 init_waitqueue_head(&ptp->phy.e810.atqbal_wq); 4918 } 4919 4920 /* E830 functions 4921 * 4922 * The following functions operate on the E830 series devices. 4923 * 4924 */ 4925 4926 /** 4927 * ice_ptp_init_phc_e830 - Perform E830 specific PHC initialization 4928 * @hw: pointer to HW struct 4929 * 4930 * Perform E830-specific PTP hardware clock initialization steps. 4931 */ 4932 static void ice_ptp_init_phc_e830(const struct ice_hw *hw) 4933 { 4934 ice_ptp_cfg_sync_delay(hw, ICE_E810_E830_SYNC_DELAY); 4935 } 4936 4937 /** 4938 * ice_ptp_write_direct_incval_e830 - Prep PHY port increment value change 4939 * @hw: pointer to HW struct 4940 * @incval: The new 40bit increment value to prepare 4941 * 4942 * Prepare the PHY port for a new increment value by programming the PHC 4943 * GLTSYN_INCVAL_L and GLTSYN_INCVAL_H registers. The actual change is 4944 * completed by FW automatically. 4945 */ 4946 static void ice_ptp_write_direct_incval_e830(const struct ice_hw *hw, 4947 u64 incval) 4948 { 4949 u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 4950 4951 wr32(hw, GLTSYN_INCVAL_L(tmr_idx), lower_32_bits(incval)); 4952 wr32(hw, GLTSYN_INCVAL_H(tmr_idx), upper_32_bits(incval)); 4953 } 4954 4955 /** 4956 * ice_ptp_write_direct_phc_time_e830 - Prepare PHY port with initial time 4957 * @hw: Board private structure 4958 * @time: Time to initialize the PHY port clock to 4959 * 4960 * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the 4961 * initial clock time. The time will not actually be programmed until the 4962 * driver issues an ICE_PTP_INIT_TIME command. 4963 * 4964 * The time value is the upper 32 bits of the PHY timer, usually in units of 4965 * nominal nanoseconds. 4966 */ 4967 static void ice_ptp_write_direct_phc_time_e830(const struct ice_hw *hw, 4968 u64 time) 4969 { 4970 u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 4971 4972 wr32(hw, GLTSYN_TIME_0(tmr_idx), 0); 4973 wr32(hw, GLTSYN_TIME_L(tmr_idx), lower_32_bits(time)); 4974 wr32(hw, GLTSYN_TIME_H(tmr_idx), upper_32_bits(time)); 4975 } 4976 4977 /** 4978 * ice_ptp_port_cmd_e830 - Prepare all external PHYs for a timer command 4979 * @hw: pointer to HW struct 4980 * @cmd: Command to be sent to the port 4981 * 4982 * Prepare the external PHYs connected to this device for a timer sync 4983 * command. 4984 * 4985 * Return: 0 on success, negative error code when PHY write failed 4986 */ 4987 static int ice_ptp_port_cmd_e830(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 4988 { 4989 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 4990 4991 return ice_write_phy_reg_e810(hw, E830_ETH_GLTSYN_CMD, val); 4992 } 4993 4994 /** 4995 * ice_read_phy_tstamp_e830 - Read a PHY timestamp out of the external PHY 4996 * @hw: pointer to the HW struct 4997 * @idx: the timestamp index to read 4998 * @tstamp: on return, the 40bit timestamp value 4999 * 5000 * Read a 40bit timestamp value out of the timestamp block of the external PHY 5001 * on the E830 device. 5002 */ 5003 static void ice_read_phy_tstamp_e830(const struct ice_hw *hw, u8 idx, 5004 u64 *tstamp) 5005 { 5006 u32 hi, lo; 5007 5008 hi = rd32(hw, E830_PRTTSYN_TXTIME_H(idx)); 5009 lo = rd32(hw, E830_PRTTSYN_TXTIME_L(idx)); 5010 5011 /* For E830 devices, the timestamp is reported with the lower 32 bits 5012 * in the low register, and the upper 8 bits in the high register. 5013 */ 5014 *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) | 5015 FIELD_PREP(PHY_EXT_40B_LOW_M, lo); 5016 } 5017 5018 /** 5019 * ice_get_phy_tx_tstamp_ready_e830 - Read Tx memory status register 5020 * @hw: pointer to the HW struct 5021 * @port: the PHY port to read 5022 * @tstamp_ready: contents of the Tx memory status register 5023 */ 5024 static void ice_get_phy_tx_tstamp_ready_e830(const struct ice_hw *hw, u8 port, 5025 u64 *tstamp_ready) 5026 { 5027 *tstamp_ready = rd32(hw, E830_PRTMAC_TS_TX_MEM_VALID_H); 5028 *tstamp_ready <<= 32; 5029 *tstamp_ready |= rd32(hw, E830_PRTMAC_TS_TX_MEM_VALID_L); 5030 } 5031 5032 /** 5033 * ice_ptp_init_phy_e830 - initialize PHY parameters 5034 * @ptp: pointer to the PTP HW struct 5035 */ 5036 static void ice_ptp_init_phy_e830(struct ice_ptp_hw *ptp) 5037 { 5038 ptp->num_lports = 8; 5039 ptp->ports_per_phy = 4; 5040 } 5041 5042 /* Device agnostic functions 5043 * 5044 * The following functions implement shared behavior common to all devices, 5045 * possibly calling a device specific implementation where necessary. 5046 */ 5047 5048 /** 5049 * ice_ptp_lock - Acquire PTP global semaphore register lock 5050 * @hw: pointer to the HW struct 5051 * 5052 * Acquire the global PTP hardware semaphore lock. Returns true if the lock 5053 * was acquired, false otherwise. 5054 * 5055 * The PFTSYN_SEM register sets the busy bit on read, returning the previous 5056 * value. If software sees the busy bit cleared, this means that this function 5057 * acquired the lock (and the busy bit is now set). If software sees the busy 5058 * bit set, it means that another function acquired the lock. 5059 * 5060 * Software must clear the busy bit with a write to release the lock for other 5061 * functions when done. 5062 */ 5063 bool ice_ptp_lock(struct ice_hw *hw) 5064 { 5065 u32 hw_lock; 5066 int i; 5067 5068 #define MAX_TRIES 15 5069 5070 for (i = 0; i < MAX_TRIES; i++) { 5071 hw_lock = rd32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id)); 5072 hw_lock = hw_lock & PFTSYN_SEM_BUSY_M; 5073 if (hw_lock) { 5074 /* Somebody is holding the lock */ 5075 usleep_range(5000, 6000); 5076 continue; 5077 } 5078 5079 break; 5080 } 5081 5082 return !hw_lock; 5083 } 5084 5085 /** 5086 * ice_ptp_unlock - Release PTP global semaphore register lock 5087 * @hw: pointer to the HW struct 5088 * 5089 * Release the global PTP hardware semaphore lock. This is done by writing to 5090 * the PFTSYN_SEM register. 5091 */ 5092 void ice_ptp_unlock(struct ice_hw *hw) 5093 { 5094 wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0); 5095 } 5096 5097 /** 5098 * ice_ptp_init_hw - Initialize hw based on device type 5099 * @hw: pointer to the HW structure 5100 * 5101 * Determine the PHY model for the device, and initialize hw 5102 * for use by other functions. 5103 */ 5104 void ice_ptp_init_hw(struct ice_hw *hw) 5105 { 5106 struct ice_ptp_hw *ptp = &hw->ptp; 5107 5108 switch (hw->mac_type) { 5109 case ICE_MAC_E810: 5110 ice_ptp_init_phy_e810(ptp); 5111 break; 5112 case ICE_MAC_E830: 5113 ice_ptp_init_phy_e830(ptp); 5114 break; 5115 case ICE_MAC_GENERIC: 5116 ice_ptp_init_phy_e82x(ptp); 5117 break; 5118 case ICE_MAC_GENERIC_3K_E825: 5119 ice_ptp_init_phy_e825(hw); 5120 break; 5121 default: 5122 return; 5123 } 5124 } 5125 5126 /** 5127 * ice_ptp_write_port_cmd - Prepare a single PHY port for a timer command 5128 * @hw: pointer to HW struct 5129 * @port: Port to which cmd has to be sent 5130 * @cmd: Command to be sent to the port 5131 * 5132 * Prepare one port for the upcoming timer sync command. Do not use this for 5133 * programming only a single port, instead use ice_ptp_one_port_cmd() to 5134 * ensure non-modified ports get properly initialized to ICE_PTP_NOP. 5135 * 5136 * Return: 5137 * * %0 - success 5138 * %-EBUSY - PHY type not supported 5139 * * %other - failed to write port command 5140 */ 5141 static int ice_ptp_write_port_cmd(struct ice_hw *hw, u8 port, 5142 enum ice_ptp_tmr_cmd cmd) 5143 { 5144 switch (hw->mac_type) { 5145 case ICE_MAC_GENERIC: 5146 return ice_ptp_write_port_cmd_e82x(hw, port, cmd); 5147 case ICE_MAC_GENERIC_3K_E825: 5148 return ice_ptp_write_port_cmd_eth56g(hw, port, cmd); 5149 default: 5150 return -EOPNOTSUPP; 5151 } 5152 } 5153 5154 /** 5155 * ice_ptp_one_port_cmd - Program one PHY port for a timer command 5156 * @hw: pointer to HW struct 5157 * @configured_port: the port that should execute the command 5158 * @configured_cmd: the command to be executed on the configured port 5159 * 5160 * Prepare one port for executing a timer command, while preparing all other 5161 * ports to ICE_PTP_NOP. This allows executing a command on a single port 5162 * while ensuring all other ports do not execute stale commands. 5163 * 5164 * Return: 5165 * * %0 - success 5166 * * %other - failed to write port command 5167 */ 5168 int ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port, 5169 enum ice_ptp_tmr_cmd configured_cmd) 5170 { 5171 u32 port; 5172 5173 for (port = 0; port < hw->ptp.num_lports; port++) { 5174 int err; 5175 5176 /* Program the configured port with the configured command, 5177 * program all other ports with ICE_PTP_NOP. 5178 */ 5179 if (port == configured_port) 5180 err = ice_ptp_write_port_cmd(hw, port, configured_cmd); 5181 else 5182 err = ice_ptp_write_port_cmd(hw, port, ICE_PTP_NOP); 5183 5184 if (err) 5185 return err; 5186 } 5187 5188 return 0; 5189 } 5190 5191 /** 5192 * ice_ptp_port_cmd - Prepare PHY ports for a timer sync command 5193 * @hw: pointer to HW struct 5194 * @cmd: the timer command to setup 5195 * 5196 * Prepare all PHY ports on this device for the requested timer command. For 5197 * some families this can be done in one shot, but for other families each 5198 * port must be configured individually. 5199 * 5200 * Return: 5201 * * %0 - success 5202 * * %other - failed to write port command 5203 */ 5204 static int ice_ptp_port_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 5205 { 5206 u32 port; 5207 5208 /* PHY models which can program all ports simultaneously */ 5209 switch (hw->mac_type) { 5210 case ICE_MAC_E810: 5211 return ice_ptp_port_cmd_e810(hw, cmd); 5212 case ICE_MAC_E830: 5213 return ice_ptp_port_cmd_e830(hw, cmd); 5214 default: 5215 break; 5216 } 5217 5218 /* PHY models which require programming each port separately */ 5219 for (port = 0; port < hw->ptp.num_lports; port++) { 5220 int err; 5221 5222 err = ice_ptp_write_port_cmd(hw, port, cmd); 5223 if (err) 5224 return err; 5225 } 5226 5227 return 0; 5228 } 5229 5230 /** 5231 * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command 5232 * @hw: pointer to HW struct 5233 * @cmd: the command to issue 5234 * 5235 * Prepare the source timer and PHY timers and then trigger the requested 5236 * command. This causes the shadow registers previously written in preparation 5237 * for the command to be synchronously applied to both the source and PHY 5238 * timers. 5239 */ 5240 static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 5241 { 5242 int err; 5243 5244 /* First, prepare the source timer */ 5245 ice_ptp_src_cmd(hw, cmd); 5246 5247 /* Next, prepare the ports */ 5248 err = ice_ptp_port_cmd(hw, cmd); 5249 if (err) { 5250 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for timer command %u, err %d\n", 5251 cmd, err); 5252 return err; 5253 } 5254 5255 /* Write the sync command register to drive both source and PHY timer 5256 * commands synchronously 5257 */ 5258 ice_ptp_exec_tmr_cmd(hw); 5259 5260 return 0; 5261 } 5262 5263 /** 5264 * ice_ptp_init_time - Initialize device time to provided value 5265 * @hw: pointer to HW struct 5266 * @time: 64bits of time (GLTSYN_TIME_L and GLTSYN_TIME_H) 5267 * 5268 * Initialize the device to the specified time provided. This requires a three 5269 * step process: 5270 * 5271 * 1) write the new init time to the source timer shadow registers 5272 * 2) write the new init time to the PHY timer shadow registers 5273 * 3) issue an init_time timer command to synchronously switch both the source 5274 * and port timers to the new init time value at the next clock cycle. 5275 */ 5276 int ice_ptp_init_time(struct ice_hw *hw, u64 time) 5277 { 5278 u8 tmr_idx; 5279 int err; 5280 5281 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5282 5283 /* Source timers */ 5284 /* For E830 we don't need to use shadow registers, its automatic */ 5285 if (hw->mac_type == ICE_MAC_E830) { 5286 ice_ptp_write_direct_phc_time_e830(hw, time); 5287 return 0; 5288 } 5289 5290 wr32(hw, GLTSYN_SHTIME_L(tmr_idx), lower_32_bits(time)); 5291 wr32(hw, GLTSYN_SHTIME_H(tmr_idx), upper_32_bits(time)); 5292 wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0); 5293 5294 /* PHY timers */ 5295 /* Fill Rx and Tx ports and send msg to PHY */ 5296 switch (hw->mac_type) { 5297 case ICE_MAC_E810: 5298 err = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF); 5299 break; 5300 case ICE_MAC_GENERIC: 5301 err = ice_ptp_prep_phy_time_e82x(hw, time & 0xFFFFFFFF); 5302 break; 5303 case ICE_MAC_GENERIC_3K_E825: 5304 err = ice_ptp_prep_phy_time_eth56g(hw, 5305 (u32)(time & 0xFFFFFFFF)); 5306 break; 5307 default: 5308 err = -EOPNOTSUPP; 5309 } 5310 5311 if (err) 5312 return err; 5313 5314 return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_TIME); 5315 } 5316 5317 /** 5318 * ice_ptp_write_incval - Program PHC with new increment value 5319 * @hw: pointer to HW struct 5320 * @incval: Source timer increment value per clock cycle 5321 * 5322 * Program the PHC with a new increment value. This requires a three-step 5323 * process: 5324 * 5325 * 1) Write the increment value to the source timer shadow registers 5326 * 2) Write the increment value to the PHY timer shadow registers 5327 * 3) Issue an ICE_PTP_INIT_INCVAL timer command to synchronously switch both 5328 * the source and port timers to the new increment value at the next clock 5329 * cycle. 5330 */ 5331 int ice_ptp_write_incval(struct ice_hw *hw, u64 incval) 5332 { 5333 u8 tmr_idx; 5334 int err; 5335 5336 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5337 5338 /* For E830 we don't need to use shadow registers, its automatic */ 5339 if (hw->mac_type == ICE_MAC_E830) { 5340 ice_ptp_write_direct_incval_e830(hw, incval); 5341 return 0; 5342 } 5343 5344 /* Shadow Adjust */ 5345 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), lower_32_bits(incval)); 5346 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), upper_32_bits(incval)); 5347 5348 switch (hw->mac_type) { 5349 case ICE_MAC_E810: 5350 err = ice_ptp_prep_phy_incval_e810(hw, incval); 5351 break; 5352 case ICE_MAC_GENERIC: 5353 err = ice_ptp_prep_phy_incval_e82x(hw, incval); 5354 break; 5355 case ICE_MAC_GENERIC_3K_E825: 5356 err = ice_ptp_prep_phy_incval_eth56g(hw, incval); 5357 break; 5358 default: 5359 err = -EOPNOTSUPP; 5360 } 5361 5362 if (err) 5363 return err; 5364 5365 return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_INCVAL); 5366 } 5367 5368 /** 5369 * ice_ptp_write_incval_locked - Program new incval while holding semaphore 5370 * @hw: pointer to HW struct 5371 * @incval: Source timer increment value per clock cycle 5372 * 5373 * Program a new PHC incval while holding the PTP semaphore. 5374 */ 5375 int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval) 5376 { 5377 int err; 5378 5379 if (!ice_ptp_lock(hw)) 5380 return -EBUSY; 5381 5382 err = ice_ptp_write_incval(hw, incval); 5383 5384 ice_ptp_unlock(hw); 5385 5386 return err; 5387 } 5388 5389 /** 5390 * ice_ptp_adj_clock - Adjust PHC clock time atomically 5391 * @hw: pointer to HW struct 5392 * @adj: Adjustment in nanoseconds 5393 * 5394 * Perform an atomic adjustment of the PHC time by the specified number of 5395 * nanoseconds. This requires a three-step process: 5396 * 5397 * 1) Write the adjustment to the source timer shadow registers 5398 * 2) Write the adjustment to the PHY timer shadow registers 5399 * 3) Issue an ICE_PTP_ADJ_TIME timer command to synchronously apply the 5400 * adjustment to both the source and port timers at the next clock cycle. 5401 */ 5402 int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj) 5403 { 5404 u8 tmr_idx; 5405 int err; 5406 5407 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5408 5409 /* Write the desired clock adjustment into the GLTSYN_SHADJ register. 5410 * For an ICE_PTP_ADJ_TIME command, this set of registers represents 5411 * the value to add to the clock time. It supports subtraction by 5412 * interpreting the value as a 2's complement integer. 5413 */ 5414 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0); 5415 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj); 5416 5417 switch (hw->mac_type) { 5418 case ICE_MAC_E810: 5419 err = ice_ptp_prep_phy_adj_e810(hw, adj); 5420 break; 5421 case ICE_MAC_E830: 5422 /* E830 sync PHYs automatically after setting GLTSYN_SHADJ */ 5423 return 0; 5424 case ICE_MAC_GENERIC: 5425 err = ice_ptp_prep_phy_adj_e82x(hw, adj); 5426 break; 5427 case ICE_MAC_GENERIC_3K_E825: 5428 err = ice_ptp_prep_phy_adj_eth56g(hw, adj); 5429 break; 5430 default: 5431 err = -EOPNOTSUPP; 5432 } 5433 5434 if (err) 5435 return err; 5436 5437 return ice_ptp_tmr_cmd(hw, ICE_PTP_ADJ_TIME); 5438 } 5439 5440 /** 5441 * ice_read_phy_tstamp - Read a PHY timestamp from the timestamo block 5442 * @hw: pointer to the HW struct 5443 * @block: the block to read from 5444 * @idx: the timestamp index to read 5445 * @tstamp: on return, the 40bit timestamp value 5446 * 5447 * Read a 40bit timestamp value out of the timestamp block. For E822 devices, 5448 * the block is the quad to read from. For E810 devices, the block is the 5449 * logical port to read from. 5450 */ 5451 int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp) 5452 { 5453 switch (hw->mac_type) { 5454 case ICE_MAC_E810: 5455 return ice_read_phy_tstamp_e810(hw, block, idx, tstamp); 5456 case ICE_MAC_E830: 5457 ice_read_phy_tstamp_e830(hw, idx, tstamp); 5458 return 0; 5459 case ICE_MAC_GENERIC: 5460 return ice_read_phy_tstamp_e82x(hw, block, idx, tstamp); 5461 case ICE_MAC_GENERIC_3K_E825: 5462 return ice_read_ptp_tstamp_eth56g(hw, block, idx, tstamp); 5463 default: 5464 return -EOPNOTSUPP; 5465 } 5466 } 5467 5468 /** 5469 * ice_clear_phy_tstamp - Clear a timestamp from the timestamp block 5470 * @hw: pointer to the HW struct 5471 * @block: the block to read from 5472 * @idx: the timestamp index to reset 5473 * 5474 * Clear a timestamp from the timestamp block, discarding its value without 5475 * returning it. This resets the memory status bit for the timestamp index 5476 * allowing it to be reused for another timestamp in the future. 5477 * 5478 * For E822 devices, the block number is the PHY quad to clear from. For E810 5479 * devices, the block number is the logical port to clear from. 5480 * 5481 * This function must only be called on a timestamp index whose valid bit is 5482 * set according to ice_get_phy_tx_tstamp_ready(). 5483 */ 5484 int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx) 5485 { 5486 switch (hw->mac_type) { 5487 case ICE_MAC_E810: 5488 return ice_clear_phy_tstamp_e810(hw, block, idx); 5489 case ICE_MAC_GENERIC: 5490 return ice_clear_phy_tstamp_e82x(hw, block, idx); 5491 case ICE_MAC_GENERIC_3K_E825: 5492 return ice_clear_ptp_tstamp_eth56g(hw, block, idx); 5493 default: 5494 return -EOPNOTSUPP; 5495 } 5496 } 5497 5498 /** 5499 * ice_get_pf_c827_idx - find and return the C827 index for the current pf 5500 * @hw: pointer to the hw struct 5501 * @idx: index of the found C827 PHY 5502 * Return: 5503 * * 0 - success 5504 * * negative - failure 5505 */ 5506 static int ice_get_pf_c827_idx(struct ice_hw *hw, u8 *idx) 5507 { 5508 struct ice_aqc_get_link_topo cmd; 5509 u8 node_part_number; 5510 u16 node_handle; 5511 int status; 5512 u8 ctx; 5513 5514 if (hw->mac_type != ICE_MAC_E810) 5515 return -ENODEV; 5516 5517 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) { 5518 *idx = C827_0; 5519 return 0; 5520 } 5521 5522 memset(&cmd, 0, sizeof(cmd)); 5523 5524 ctx = ICE_AQC_LINK_TOPO_NODE_TYPE_PHY << ICE_AQC_LINK_TOPO_NODE_TYPE_S; 5525 ctx |= ICE_AQC_LINK_TOPO_NODE_CTX_PORT << ICE_AQC_LINK_TOPO_NODE_CTX_S; 5526 cmd.addr.topo_params.node_type_ctx = ctx; 5527 5528 status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number, 5529 &node_handle); 5530 if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827) 5531 return -ENOENT; 5532 5533 if (node_handle == E810C_QSFP_C827_0_HANDLE) 5534 *idx = C827_0; 5535 else if (node_handle == E810C_QSFP_C827_1_HANDLE) 5536 *idx = C827_1; 5537 else 5538 return -EIO; 5539 5540 return 0; 5541 } 5542 5543 /** 5544 * ice_ptp_reset_ts_memory - Reset timestamp memory for all blocks 5545 * @hw: pointer to the HW struct 5546 */ 5547 void ice_ptp_reset_ts_memory(struct ice_hw *hw) 5548 { 5549 switch (hw->mac_type) { 5550 case ICE_MAC_GENERIC: 5551 ice_ptp_reset_ts_memory_e82x(hw); 5552 break; 5553 case ICE_MAC_GENERIC_3K_E825: 5554 ice_ptp_reset_ts_memory_eth56g(hw); 5555 break; 5556 case ICE_MAC_E810: 5557 default: 5558 return; 5559 } 5560 } 5561 5562 /** 5563 * ice_ptp_init_phc - Initialize PTP hardware clock 5564 * @hw: pointer to the HW struct 5565 * 5566 * Perform the steps required to initialize the PTP hardware clock. 5567 */ 5568 int ice_ptp_init_phc(struct ice_hw *hw) 5569 { 5570 u8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5571 5572 /* Enable source clocks */ 5573 wr32(hw, GLTSYN_ENA(src_idx), GLTSYN_ENA_TSYN_ENA_M); 5574 5575 /* Clear event err indications for auxiliary pins */ 5576 (void)rd32(hw, GLTSYN_STAT(src_idx)); 5577 5578 switch (hw->mac_type) { 5579 case ICE_MAC_E810: 5580 return ice_ptp_init_phc_e810(hw); 5581 case ICE_MAC_E830: 5582 ice_ptp_init_phc_e830(hw); 5583 return 0; 5584 case ICE_MAC_GENERIC: 5585 return ice_ptp_init_phc_e82x(hw); 5586 case ICE_MAC_GENERIC_3K_E825: 5587 return ice_ptp_init_phc_e825(hw); 5588 default: 5589 return -EOPNOTSUPP; 5590 } 5591 } 5592 5593 /** 5594 * ice_get_phy_tx_tstamp_ready - Read PHY Tx memory status indication 5595 * @hw: pointer to the HW struct 5596 * @block: the timestamp block to check 5597 * @tstamp_ready: storage for the PHY Tx memory status information 5598 * 5599 * Check the PHY for Tx timestamp memory status. This reports a 64 bit value 5600 * which indicates which timestamps in the block may be captured. A set bit 5601 * means the timestamp can be read. An unset bit means the timestamp is not 5602 * ready and software should avoid reading the register. 5603 */ 5604 int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready) 5605 { 5606 switch (hw->mac_type) { 5607 case ICE_MAC_E810: 5608 return ice_get_phy_tx_tstamp_ready_e810(hw, block, 5609 tstamp_ready); 5610 case ICE_MAC_E830: 5611 ice_get_phy_tx_tstamp_ready_e830(hw, block, tstamp_ready); 5612 return 0; 5613 case ICE_MAC_GENERIC: 5614 return ice_get_phy_tx_tstamp_ready_e82x(hw, block, 5615 tstamp_ready); 5616 case ICE_MAC_GENERIC_3K_E825: 5617 return ice_get_phy_tx_tstamp_ready_eth56g(hw, block, 5618 tstamp_ready); 5619 default: 5620 return -EOPNOTSUPP; 5621 } 5622 } 5623 5624 /** 5625 * ice_cgu_get_pin_desc_e823 - get pin description array 5626 * @hw: pointer to the hw struct 5627 * @input: if request is done against input or output pin 5628 * @size: number of inputs/outputs 5629 * 5630 * Return: pointer to pin description array associated to given hw. 5631 */ 5632 static const struct ice_cgu_pin_desc * 5633 ice_cgu_get_pin_desc_e823(struct ice_hw *hw, bool input, int *size) 5634 { 5635 static const struct ice_cgu_pin_desc *t; 5636 5637 if (hw->cgu_part_number == 5638 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032) { 5639 if (input) { 5640 t = ice_e823_zl_cgu_inputs; 5641 *size = ARRAY_SIZE(ice_e823_zl_cgu_inputs); 5642 } else { 5643 t = ice_e823_zl_cgu_outputs; 5644 *size = ARRAY_SIZE(ice_e823_zl_cgu_outputs); 5645 } 5646 } else if (hw->cgu_part_number == 5647 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384) { 5648 if (input) { 5649 t = ice_e823_si_cgu_inputs; 5650 *size = ARRAY_SIZE(ice_e823_si_cgu_inputs); 5651 } else { 5652 t = ice_e823_si_cgu_outputs; 5653 *size = ARRAY_SIZE(ice_e823_si_cgu_outputs); 5654 } 5655 } else { 5656 t = NULL; 5657 *size = 0; 5658 } 5659 5660 return t; 5661 } 5662 5663 /** 5664 * ice_cgu_get_pin_desc - get pin description array 5665 * @hw: pointer to the hw struct 5666 * @input: if request is done against input or output pins 5667 * @size: size of array returned by function 5668 * 5669 * Return: pointer to pin description array associated to given hw. 5670 */ 5671 static const struct ice_cgu_pin_desc * 5672 ice_cgu_get_pin_desc(struct ice_hw *hw, bool input, int *size) 5673 { 5674 const struct ice_cgu_pin_desc *t = NULL; 5675 5676 switch (hw->device_id) { 5677 case ICE_DEV_ID_E810C_SFP: 5678 if (input) { 5679 t = ice_e810t_sfp_cgu_inputs; 5680 *size = ARRAY_SIZE(ice_e810t_sfp_cgu_inputs); 5681 } else { 5682 t = ice_e810t_sfp_cgu_outputs; 5683 *size = ARRAY_SIZE(ice_e810t_sfp_cgu_outputs); 5684 } 5685 break; 5686 case ICE_DEV_ID_E810C_QSFP: 5687 if (input) { 5688 t = ice_e810t_qsfp_cgu_inputs; 5689 *size = ARRAY_SIZE(ice_e810t_qsfp_cgu_inputs); 5690 } else { 5691 t = ice_e810t_qsfp_cgu_outputs; 5692 *size = ARRAY_SIZE(ice_e810t_qsfp_cgu_outputs); 5693 } 5694 break; 5695 case ICE_DEV_ID_E823L_10G_BASE_T: 5696 case ICE_DEV_ID_E823L_1GBE: 5697 case ICE_DEV_ID_E823L_BACKPLANE: 5698 case ICE_DEV_ID_E823L_QSFP: 5699 case ICE_DEV_ID_E823L_SFP: 5700 case ICE_DEV_ID_E823C_10G_BASE_T: 5701 case ICE_DEV_ID_E823C_BACKPLANE: 5702 case ICE_DEV_ID_E823C_QSFP: 5703 case ICE_DEV_ID_E823C_SFP: 5704 case ICE_DEV_ID_E823C_SGMII: 5705 t = ice_cgu_get_pin_desc_e823(hw, input, size); 5706 break; 5707 default: 5708 break; 5709 } 5710 5711 return t; 5712 } 5713 5714 /** 5715 * ice_cgu_get_num_pins - get pin description array size 5716 * @hw: pointer to the hw struct 5717 * @input: if request is done against input or output pins 5718 * 5719 * Return: size of pin description array for given hw. 5720 */ 5721 int ice_cgu_get_num_pins(struct ice_hw *hw, bool input) 5722 { 5723 const struct ice_cgu_pin_desc *t; 5724 int size; 5725 5726 t = ice_cgu_get_pin_desc(hw, input, &size); 5727 if (t) 5728 return size; 5729 5730 return 0; 5731 } 5732 5733 /** 5734 * ice_cgu_get_pin_type - get pin's type 5735 * @hw: pointer to the hw struct 5736 * @pin: pin index 5737 * @input: if request is done against input or output pin 5738 * 5739 * Return: type of a pin. 5740 */ 5741 enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool input) 5742 { 5743 const struct ice_cgu_pin_desc *t; 5744 int t_size; 5745 5746 t = ice_cgu_get_pin_desc(hw, input, &t_size); 5747 5748 if (!t) 5749 return 0; 5750 5751 if (pin >= t_size) 5752 return 0; 5753 5754 return t[pin].type; 5755 } 5756 5757 /** 5758 * ice_cgu_get_pin_freq_supp - get pin's supported frequency 5759 * @hw: pointer to the hw struct 5760 * @pin: pin index 5761 * @input: if request is done against input or output pin 5762 * @num: output number of supported frequencies 5763 * 5764 * Get frequency supported number and array of supported frequencies. 5765 * 5766 * Return: array of supported frequencies for given pin. 5767 */ 5768 struct dpll_pin_frequency * 5769 ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num) 5770 { 5771 const struct ice_cgu_pin_desc *t; 5772 int t_size; 5773 5774 *num = 0; 5775 t = ice_cgu_get_pin_desc(hw, input, &t_size); 5776 if (!t) 5777 return NULL; 5778 if (pin >= t_size) 5779 return NULL; 5780 *num = t[pin].freq_supp_num; 5781 5782 return t[pin].freq_supp; 5783 } 5784 5785 /** 5786 * ice_cgu_get_pin_name - get pin's name 5787 * @hw: pointer to the hw struct 5788 * @pin: pin index 5789 * @input: if request is done against input or output pin 5790 * 5791 * Return: 5792 * * null terminated char array with name 5793 * * NULL in case of failure 5794 */ 5795 const char *ice_cgu_get_pin_name(struct ice_hw *hw, u8 pin, bool input) 5796 { 5797 const struct ice_cgu_pin_desc *t; 5798 int t_size; 5799 5800 t = ice_cgu_get_pin_desc(hw, input, &t_size); 5801 5802 if (!t) 5803 return NULL; 5804 5805 if (pin >= t_size) 5806 return NULL; 5807 5808 return t[pin].name; 5809 } 5810 5811 /** 5812 * ice_get_cgu_state - get the state of the DPLL 5813 * @hw: pointer to the hw struct 5814 * @dpll_idx: Index of internal DPLL unit 5815 * @last_dpll_state: last known state of DPLL 5816 * @pin: pointer to a buffer for returning currently active pin 5817 * @ref_state: reference clock state 5818 * @eec_mode: eec mode of the DPLL 5819 * @phase_offset: pointer to a buffer for returning phase offset 5820 * @dpll_state: state of the DPLL (output) 5821 * 5822 * This function will read the state of the DPLL(dpll_idx). Non-null 5823 * 'pin', 'ref_state', 'eec_mode' and 'phase_offset' parameters are used to 5824 * retrieve currently active pin, state, mode and phase_offset respectively. 5825 * 5826 * Return: state of the DPLL 5827 */ 5828 int ice_get_cgu_state(struct ice_hw *hw, u8 dpll_idx, 5829 enum dpll_lock_status last_dpll_state, u8 *pin, 5830 u8 *ref_state, u8 *eec_mode, s64 *phase_offset, 5831 enum dpll_lock_status *dpll_state) 5832 { 5833 u8 hw_ref_state, hw_dpll_state, hw_eec_mode, hw_config; 5834 s64 hw_phase_offset; 5835 int status; 5836 5837 status = ice_aq_get_cgu_dpll_status(hw, dpll_idx, &hw_ref_state, 5838 &hw_dpll_state, &hw_config, 5839 &hw_phase_offset, &hw_eec_mode); 5840 if (status) 5841 return status; 5842 5843 if (pin) 5844 /* current ref pin in dpll_state_refsel_status_X register */ 5845 *pin = hw_config & ICE_AQC_GET_CGU_DPLL_CONFIG_CLK_REF_SEL; 5846 if (phase_offset) 5847 *phase_offset = hw_phase_offset; 5848 if (ref_state) 5849 *ref_state = hw_ref_state; 5850 if (eec_mode) 5851 *eec_mode = hw_eec_mode; 5852 if (!dpll_state) 5853 return 0; 5854 5855 /* According to ZL DPLL documentation, once state reach LOCKED_HO_ACQ 5856 * it would never return to FREERUN. This aligns to ITU-T G.781 5857 * Recommendation. We cannot report HOLDOVER as HO memory is cleared 5858 * while switching to another reference. 5859 * Only for situations where previous state was either: "LOCKED without 5860 * HO_ACQ" or "HOLDOVER" we actually back to FREERUN. 5861 */ 5862 if (hw_dpll_state & ICE_AQC_GET_CGU_DPLL_STATUS_STATE_LOCK) { 5863 if (hw_dpll_state & ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO_READY) 5864 *dpll_state = DPLL_LOCK_STATUS_LOCKED_HO_ACQ; 5865 else 5866 *dpll_state = DPLL_LOCK_STATUS_LOCKED; 5867 } else if (last_dpll_state == DPLL_LOCK_STATUS_LOCKED_HO_ACQ || 5868 last_dpll_state == DPLL_LOCK_STATUS_HOLDOVER) { 5869 *dpll_state = DPLL_LOCK_STATUS_HOLDOVER; 5870 } else { 5871 *dpll_state = DPLL_LOCK_STATUS_UNLOCKED; 5872 } 5873 5874 return 0; 5875 } 5876 5877 /** 5878 * ice_get_cgu_rclk_pin_info - get info on available recovered clock pins 5879 * @hw: pointer to the hw struct 5880 * @base_idx: returns index of first recovered clock pin on device 5881 * @pin_num: returns number of recovered clock pins available on device 5882 * 5883 * Based on hw provide caller info about recovery clock pins available on the 5884 * board. 5885 * 5886 * Return: 5887 * * 0 - success, information is valid 5888 * * negative - failure, information is not valid 5889 */ 5890 int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num) 5891 { 5892 u8 phy_idx; 5893 int ret; 5894 5895 switch (hw->device_id) { 5896 case ICE_DEV_ID_E810C_SFP: 5897 case ICE_DEV_ID_E810C_QSFP: 5898 5899 ret = ice_get_pf_c827_idx(hw, &phy_idx); 5900 if (ret) 5901 return ret; 5902 *base_idx = E810T_CGU_INPUT_C827(phy_idx, ICE_RCLKA_PIN); 5903 *pin_num = ICE_E810_RCLK_PINS_NUM; 5904 ret = 0; 5905 break; 5906 case ICE_DEV_ID_E823L_10G_BASE_T: 5907 case ICE_DEV_ID_E823L_1GBE: 5908 case ICE_DEV_ID_E823L_BACKPLANE: 5909 case ICE_DEV_ID_E823L_QSFP: 5910 case ICE_DEV_ID_E823L_SFP: 5911 case ICE_DEV_ID_E823C_10G_BASE_T: 5912 case ICE_DEV_ID_E823C_BACKPLANE: 5913 case ICE_DEV_ID_E823C_QSFP: 5914 case ICE_DEV_ID_E823C_SFP: 5915 case ICE_DEV_ID_E823C_SGMII: 5916 *pin_num = ICE_E82X_RCLK_PINS_NUM; 5917 ret = 0; 5918 if (hw->cgu_part_number == 5919 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032) 5920 *base_idx = ZL_REF1P; 5921 else if (hw->cgu_part_number == 5922 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384) 5923 *base_idx = SI_REF1P; 5924 else 5925 ret = -ENODEV; 5926 5927 break; 5928 default: 5929 ret = -ENODEV; 5930 break; 5931 } 5932 5933 return ret; 5934 } 5935 5936 /** 5937 * ice_cgu_get_output_pin_state_caps - get output pin state capabilities 5938 * @hw: pointer to the hw struct 5939 * @pin_id: id of a pin 5940 * @caps: capabilities to modify 5941 * 5942 * Return: 5943 * * 0 - success, state capabilities were modified 5944 * * negative - failure, capabilities were not modified 5945 */ 5946 int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id, 5947 unsigned long *caps) 5948 { 5949 bool can_change = true; 5950 5951 switch (hw->device_id) { 5952 case ICE_DEV_ID_E810C_SFP: 5953 if (pin_id == ZL_OUT2 || pin_id == ZL_OUT3) 5954 can_change = false; 5955 break; 5956 case ICE_DEV_ID_E810C_QSFP: 5957 if (pin_id == ZL_OUT2 || pin_id == ZL_OUT3 || pin_id == ZL_OUT4) 5958 can_change = false; 5959 break; 5960 case ICE_DEV_ID_E823L_10G_BASE_T: 5961 case ICE_DEV_ID_E823L_1GBE: 5962 case ICE_DEV_ID_E823L_BACKPLANE: 5963 case ICE_DEV_ID_E823L_QSFP: 5964 case ICE_DEV_ID_E823L_SFP: 5965 case ICE_DEV_ID_E823C_10G_BASE_T: 5966 case ICE_DEV_ID_E823C_BACKPLANE: 5967 case ICE_DEV_ID_E823C_QSFP: 5968 case ICE_DEV_ID_E823C_SFP: 5969 case ICE_DEV_ID_E823C_SGMII: 5970 if (hw->cgu_part_number == 5971 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032 && 5972 pin_id == ZL_OUT2) 5973 can_change = false; 5974 else if (hw->cgu_part_number == 5975 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384 && 5976 pin_id == SI_OUT1) 5977 can_change = false; 5978 break; 5979 default: 5980 return -EINVAL; 5981 } 5982 if (can_change) 5983 *caps |= DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE; 5984 else 5985 *caps &= ~DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE; 5986 5987 return 0; 5988 } 5989