1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (C) 2021, Intel Corporation. */ 3 4 #include <linux/delay.h> 5 #include <linux/iopoll.h> 6 #include "ice_common.h" 7 #include "ice_ptp_hw.h" 8 #include "ice_ptp_consts.h" 9 #include "ice_cgu_regs.h" 10 11 static struct dpll_pin_frequency ice_cgu_pin_freq_common[] = { 12 DPLL_PIN_FREQUENCY_1PPS, 13 DPLL_PIN_FREQUENCY_10MHZ, 14 }; 15 16 static struct dpll_pin_frequency ice_cgu_pin_freq_1_hz[] = { 17 DPLL_PIN_FREQUENCY_1PPS, 18 }; 19 20 static struct dpll_pin_frequency ice_cgu_pin_freq_10_mhz[] = { 21 DPLL_PIN_FREQUENCY_10MHZ, 22 }; 23 24 static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_inputs[] = { 25 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR, 26 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 27 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR, 28 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 29 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, }, 30 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, }, 31 { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT, 32 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 33 { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT, 34 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 35 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS, 36 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 37 }; 38 39 static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_inputs[] = { 40 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR, 41 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 42 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR, 43 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 44 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, }, 45 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, }, 46 { "C827_1-RCLKA", ZL_REF2P, DPLL_PIN_TYPE_MUX, }, 47 { "C827_1-RCLKB", ZL_REF2N, DPLL_PIN_TYPE_MUX, }, 48 { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT, 49 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 50 { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT, 51 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 52 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS, 53 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 54 }; 55 56 static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_outputs[] = { 57 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT, 58 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 59 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT, 60 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 61 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, }, 62 { "MAC-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, }, 63 { "CVL-SDP21", ZL_OUT4, DPLL_PIN_TYPE_EXT, 64 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 65 { "CVL-SDP23", ZL_OUT5, DPLL_PIN_TYPE_EXT, 66 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 67 }; 68 69 static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_outputs[] = { 70 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT, 71 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 72 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT, 73 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 74 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 75 { "PHY2-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 76 { "MAC-CLK", ZL_OUT4, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 77 { "CVL-SDP21", ZL_OUT5, DPLL_PIN_TYPE_EXT, 78 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 79 { "CVL-SDP23", ZL_OUT6, DPLL_PIN_TYPE_EXT, 80 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 81 }; 82 83 static const struct ice_cgu_pin_desc ice_e823_si_cgu_inputs[] = { 84 { "NONE", SI_REF0P, 0, 0 }, 85 { "NONE", SI_REF0N, 0, 0 }, 86 { "SYNCE0_DP", SI_REF1P, DPLL_PIN_TYPE_MUX, 0 }, 87 { "SYNCE0_DN", SI_REF1N, DPLL_PIN_TYPE_MUX, 0 }, 88 { "EXT_CLK_SYNC", SI_REF2P, DPLL_PIN_TYPE_EXT, 89 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 90 { "NONE", SI_REF2N, 0, 0 }, 91 { "EXT_PPS_OUT", SI_REF3, DPLL_PIN_TYPE_EXT, 92 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 93 { "INT_PPS_OUT", SI_REF4, DPLL_PIN_TYPE_EXT, 94 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 95 }; 96 97 static const struct ice_cgu_pin_desc ice_e823_si_cgu_outputs[] = { 98 { "1588-TIME_SYNC", SI_OUT0, DPLL_PIN_TYPE_EXT, 99 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 100 { "PHY-CLK", SI_OUT1, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 101 { "10MHZ-SMA2", SI_OUT2, DPLL_PIN_TYPE_EXT, 102 ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz }, 103 { "PPS-SMA1", SI_OUT3, DPLL_PIN_TYPE_EXT, 104 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 105 }; 106 107 static const struct ice_cgu_pin_desc ice_e823_zl_cgu_inputs[] = { 108 { "NONE", ZL_REF0P, 0, 0 }, 109 { "INT_PPS_OUT", ZL_REF0N, DPLL_PIN_TYPE_EXT, 110 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 111 { "SYNCE0_DP", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0 }, 112 { "SYNCE0_DN", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0 }, 113 { "NONE", ZL_REF2P, 0, 0 }, 114 { "NONE", ZL_REF2N, 0, 0 }, 115 { "EXT_CLK_SYNC", ZL_REF3P, DPLL_PIN_TYPE_EXT, 116 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 117 { "NONE", ZL_REF3N, 0, 0 }, 118 { "EXT_PPS_OUT", ZL_REF4P, DPLL_PIN_TYPE_EXT, 119 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 120 { "OCXO", ZL_REF4N, DPLL_PIN_TYPE_INT_OSCILLATOR, 0 }, 121 }; 122 123 static const struct ice_cgu_pin_desc ice_e823_zl_cgu_outputs[] = { 124 { "PPS-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT, 125 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 126 { "10MHZ-SMA2", ZL_OUT1, DPLL_PIN_TYPE_EXT, 127 ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz }, 128 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 129 { "1588-TIME_REF", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 130 { "CPK-TIME_SYNC", ZL_OUT4, DPLL_PIN_TYPE_EXT, 131 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 132 { "NONE", ZL_OUT5, 0, 0 }, 133 }; 134 135 /* Low level functions for interacting with and managing the device clock used 136 * for the Precision Time Protocol. 137 * 138 * The ice hardware represents the current time using three registers: 139 * 140 * GLTSYN_TIME_H GLTSYN_TIME_L GLTSYN_TIME_R 141 * +---------------+ +---------------+ +---------------+ 142 * | 32 bits | | 32 bits | | 32 bits | 143 * +---------------+ +---------------+ +---------------+ 144 * 145 * The registers are incremented every clock tick using a 40bit increment 146 * value defined over two registers: 147 * 148 * GLTSYN_INCVAL_H GLTSYN_INCVAL_L 149 * +---------------+ +---------------+ 150 * | 8 bit s | | 32 bits | 151 * +---------------+ +---------------+ 152 * 153 * The increment value is added to the GLSTYN_TIME_R and GLSTYN_TIME_L 154 * registers every clock source tick. Depending on the specific device 155 * configuration, the clock source frequency could be one of a number of 156 * values. 157 * 158 * For E810 devices, the increment frequency is 812.5 MHz 159 * 160 * For E822 devices the clock can be derived from different sources, and the 161 * increment has an effective frequency of one of the following: 162 * - 823.4375 MHz 163 * - 783.36 MHz 164 * - 796.875 MHz 165 * - 816 MHz 166 * - 830.078125 MHz 167 * - 783.36 MHz 168 * 169 * The hardware captures timestamps in the PHY for incoming packets, and for 170 * outgoing packets on request. To support this, the PHY maintains a timer 171 * that matches the lower 64 bits of the global source timer. 172 * 173 * In order to ensure that the PHY timers and the source timer are equivalent, 174 * shadow registers are used to prepare the desired initial values. A special 175 * sync command is issued to trigger copying from the shadow registers into 176 * the appropriate source and PHY registers simultaneously. 177 * 178 * The driver supports devices which have different PHYs with subtly different 179 * mechanisms to program and control the timers. We divide the devices into 180 * families named after the first major device, E810 and similar devices, and 181 * E822 and similar devices. 182 * 183 * - E822 based devices have additional support for fine grained Vernier 184 * calibration which requires significant setup 185 * - The layout of timestamp data in the PHY register blocks is different 186 * - The way timer synchronization commands are issued is different. 187 * 188 * To support this, very low level functions have an e810 or e822 suffix 189 * indicating what type of device they work on. Higher level abstractions for 190 * tasks that can be done on both devices do not have the suffix and will 191 * correctly look up the appropriate low level function when running. 192 * 193 * Functions which only make sense on a single device family may not have 194 * a suitable generic implementation 195 */ 196 197 /** 198 * ice_get_ptp_src_clock_index - determine source clock index 199 * @hw: pointer to HW struct 200 * 201 * Determine the source clock index currently in use, based on device 202 * capabilities reported during initialization. 203 */ 204 u8 ice_get_ptp_src_clock_index(struct ice_hw *hw) 205 { 206 return hw->func_caps.ts_func_info.tmr_index_assoc; 207 } 208 209 /** 210 * ice_ptp_read_src_incval - Read source timer increment value 211 * @hw: pointer to HW struct 212 * 213 * Read the increment value of the source timer and return it. 214 */ 215 static u64 ice_ptp_read_src_incval(struct ice_hw *hw) 216 { 217 u32 lo, hi; 218 u8 tmr_idx; 219 220 tmr_idx = ice_get_ptp_src_clock_index(hw); 221 222 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 223 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 224 225 return ((u64)(hi & INCVAL_HIGH_M) << 32) | lo; 226 } 227 228 /** 229 * ice_read_cgu_reg_e82x - Read a CGU register 230 * @hw: pointer to the HW struct 231 * @addr: Register address to read 232 * @val: storage for register value read 233 * 234 * Read the contents of a register of the Clock Generation Unit. Only 235 * applicable to E822 devices. 236 * 237 * Return: 0 on success, other error codes when failed to read from CGU 238 */ 239 static int ice_read_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 *val) 240 { 241 struct ice_sbq_msg_input cgu_msg = { 242 .opcode = ice_sbq_msg_rd, 243 .dest_dev = cgu, 244 .msg_addr_low = addr 245 }; 246 int err; 247 248 err = ice_sbq_rw_reg(hw, &cgu_msg, ICE_AQ_FLAG_RD); 249 if (err) { 250 ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n", 251 addr, err); 252 return err; 253 } 254 255 *val = cgu_msg.data; 256 257 return 0; 258 } 259 260 /** 261 * ice_write_cgu_reg_e82x - Write a CGU register 262 * @hw: pointer to the HW struct 263 * @addr: Register address to write 264 * @val: value to write into the register 265 * 266 * Write the specified value to a register of the Clock Generation Unit. Only 267 * applicable to E822 devices. 268 * 269 * Return: 0 on success, other error codes when failed to write to CGU 270 */ 271 static int ice_write_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 val) 272 { 273 struct ice_sbq_msg_input cgu_msg = { 274 .opcode = ice_sbq_msg_wr, 275 .dest_dev = cgu, 276 .msg_addr_low = addr, 277 .data = val 278 }; 279 int err; 280 281 err = ice_sbq_rw_reg(hw, &cgu_msg, ICE_AQ_FLAG_RD); 282 if (err) { 283 ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n", 284 addr, err); 285 return err; 286 } 287 288 return err; 289 } 290 291 /** 292 * ice_clk_freq_str - Convert time_ref_freq to string 293 * @clk_freq: Clock frequency 294 * 295 * Return: specified TIME_REF clock frequency converted to a string 296 */ 297 static const char *ice_clk_freq_str(enum ice_time_ref_freq clk_freq) 298 { 299 switch (clk_freq) { 300 case ICE_TIME_REF_FREQ_25_000: 301 return "25 MHz"; 302 case ICE_TIME_REF_FREQ_122_880: 303 return "122.88 MHz"; 304 case ICE_TIME_REF_FREQ_125_000: 305 return "125 MHz"; 306 case ICE_TIME_REF_FREQ_153_600: 307 return "153.6 MHz"; 308 case ICE_TIME_REF_FREQ_156_250: 309 return "156.25 MHz"; 310 case ICE_TIME_REF_FREQ_245_760: 311 return "245.76 MHz"; 312 default: 313 return "Unknown"; 314 } 315 } 316 317 /** 318 * ice_clk_src_str - Convert time_ref_src to string 319 * @clk_src: Clock source 320 * 321 * Return: specified clock source converted to its string name 322 */ 323 static const char *ice_clk_src_str(enum ice_clk_src clk_src) 324 { 325 switch (clk_src) { 326 case ICE_CLK_SRC_TCXO: 327 return "TCXO"; 328 case ICE_CLK_SRC_TIME_REF: 329 return "TIME_REF"; 330 default: 331 return "Unknown"; 332 } 333 } 334 335 /** 336 * ice_cfg_cgu_pll_e82x - Configure the Clock Generation Unit 337 * @hw: pointer to the HW struct 338 * @clk_freq: Clock frequency to program 339 * @clk_src: Clock source to select (TIME_REF, or TCXO) 340 * 341 * Configure the Clock Generation Unit with the desired clock frequency and 342 * time reference, enabling the PLL which drives the PTP hardware clock. 343 * 344 * Return: 345 * * %0 - success 346 * * %-EINVAL - input parameters are incorrect 347 * * %-EBUSY - failed to lock TS PLL 348 * * %other - CGU read/write failure 349 */ 350 static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw, 351 enum ice_time_ref_freq clk_freq, 352 enum ice_clk_src clk_src) 353 { 354 union tspll_ro_bwm_lf bwm_lf; 355 union nac_cgu_dword19 dw19; 356 union nac_cgu_dword22 dw22; 357 union nac_cgu_dword24 dw24; 358 union nac_cgu_dword9 dw9; 359 int err; 360 361 if (clk_freq >= NUM_ICE_TIME_REF_FREQ) { 362 dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n", 363 clk_freq); 364 return -EINVAL; 365 } 366 367 if (clk_src >= NUM_ICE_CLK_SRC) { 368 dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n", 369 clk_src); 370 return -EINVAL; 371 } 372 373 if (clk_src == ICE_CLK_SRC_TCXO && 374 clk_freq != ICE_TIME_REF_FREQ_25_000) { 375 dev_warn(ice_hw_to_dev(hw), 376 "TCXO only supports 25 MHz frequency\n"); 377 return -EINVAL; 378 } 379 380 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val); 381 if (err) 382 return err; 383 384 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val); 385 if (err) 386 return err; 387 388 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val); 389 if (err) 390 return err; 391 392 /* Log the current clock configuration */ 393 ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", 394 dw24.ts_pll_enable ? "enabled" : "disabled", 395 ice_clk_src_str(dw24.time_ref_sel), 396 ice_clk_freq_str(dw9.time_ref_freq_sel), 397 bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked"); 398 399 /* Disable the PLL before changing the clock source or frequency */ 400 if (dw24.ts_pll_enable) { 401 dw24.ts_pll_enable = 0; 402 403 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val); 404 if (err) 405 return err; 406 } 407 408 /* Set the frequency */ 409 dw9.time_ref_freq_sel = clk_freq; 410 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val); 411 if (err) 412 return err; 413 414 /* Configure the TS PLL feedback divisor */ 415 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val); 416 if (err) 417 return err; 418 419 dw19.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div; 420 dw19.tspll_ndivratio = 1; 421 422 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val); 423 if (err) 424 return err; 425 426 /* Configure the TS PLL post divisor */ 427 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val); 428 if (err) 429 return err; 430 431 dw22.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div; 432 dw22.time1588clk_sel_div2 = 0; 433 434 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val); 435 if (err) 436 return err; 437 438 /* Configure the TS PLL pre divisor and clock source */ 439 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val); 440 if (err) 441 return err; 442 443 dw24.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div; 444 dw24.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div; 445 dw24.time_ref_sel = clk_src; 446 447 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val); 448 if (err) 449 return err; 450 451 /* Finally, enable the PLL */ 452 dw24.ts_pll_enable = 1; 453 454 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val); 455 if (err) 456 return err; 457 458 /* Wait to verify if the PLL locks */ 459 usleep_range(1000, 5000); 460 461 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val); 462 if (err) 463 return err; 464 465 if (!bwm_lf.plllock_true_lock_cri) { 466 dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n"); 467 return -EBUSY; 468 } 469 470 /* Log the current clock configuration */ 471 ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", 472 dw24.ts_pll_enable ? "enabled" : "disabled", 473 ice_clk_src_str(dw24.time_ref_sel), 474 ice_clk_freq_str(dw9.time_ref_freq_sel), 475 bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked"); 476 477 return 0; 478 } 479 480 /** 481 * ice_cfg_cgu_pll_e825c - Configure the Clock Generation Unit for E825-C 482 * @hw: pointer to the HW struct 483 * @clk_freq: Clock frequency to program 484 * @clk_src: Clock source to select (TIME_REF, or TCXO) 485 * 486 * Configure the Clock Generation Unit with the desired clock frequency and 487 * time reference, enabling the PLL which drives the PTP hardware clock. 488 * 489 * Return: 490 * * %0 - success 491 * * %-EINVAL - input parameters are incorrect 492 * * %-EBUSY - failed to lock TS PLL 493 * * %other - CGU read/write failure 494 */ 495 static int ice_cfg_cgu_pll_e825c(struct ice_hw *hw, 496 enum ice_time_ref_freq clk_freq, 497 enum ice_clk_src clk_src) 498 { 499 union tspll_ro_lock_e825c ro_lock; 500 union nac_cgu_dword16_e825c dw16; 501 union nac_cgu_dword23_e825c dw23; 502 union nac_cgu_dword19 dw19; 503 union nac_cgu_dword22 dw22; 504 union nac_cgu_dword24 dw24; 505 union nac_cgu_dword9 dw9; 506 int err; 507 508 if (clk_freq >= NUM_ICE_TIME_REF_FREQ) { 509 dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n", 510 clk_freq); 511 return -EINVAL; 512 } 513 514 if (clk_src >= NUM_ICE_CLK_SRC) { 515 dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n", 516 clk_src); 517 return -EINVAL; 518 } 519 520 if (clk_src == ICE_CLK_SRC_TCXO && 521 clk_freq != ICE_TIME_REF_FREQ_156_250) { 522 dev_warn(ice_hw_to_dev(hw), 523 "TCXO only supports 156.25 MHz frequency\n"); 524 return -EINVAL; 525 } 526 527 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val); 528 if (err) 529 return err; 530 531 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val); 532 if (err) 533 return err; 534 535 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD16_E825C, &dw16.val); 536 if (err) 537 return err; 538 539 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val); 540 if (err) 541 return err; 542 543 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val); 544 if (err) 545 return err; 546 547 /* Log the current clock configuration */ 548 ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", 549 dw24.ts_pll_enable ? "enabled" : "disabled", 550 ice_clk_src_str(dw23.time_ref_sel), 551 ice_clk_freq_str(dw9.time_ref_freq_sel), 552 ro_lock.plllock_true_lock_cri ? "locked" : "unlocked"); 553 554 /* Disable the PLL before changing the clock source or frequency */ 555 if (dw23.ts_pll_enable) { 556 dw23.ts_pll_enable = 0; 557 558 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, 559 dw23.val); 560 if (err) 561 return err; 562 } 563 564 /* Set the frequency */ 565 dw9.time_ref_freq_sel = clk_freq; 566 567 /* Enable the correct receiver */ 568 if (clk_src == ICE_CLK_SRC_TCXO) { 569 dw9.time_ref_en = 0; 570 dw9.clk_eref0_en = 1; 571 } else { 572 dw9.time_ref_en = 1; 573 dw9.clk_eref0_en = 0; 574 } 575 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val); 576 if (err) 577 return err; 578 579 /* Choose the referenced frequency */ 580 dw16.tspll_ck_refclkfreq = 581 e825c_cgu_params[clk_freq].tspll_ck_refclkfreq; 582 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD16_E825C, dw16.val); 583 if (err) 584 return err; 585 586 /* Configure the TS PLL feedback divisor */ 587 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val); 588 if (err) 589 return err; 590 591 dw19.tspll_fbdiv_intgr = 592 e825c_cgu_params[clk_freq].tspll_fbdiv_intgr; 593 dw19.tspll_ndivratio = 594 e825c_cgu_params[clk_freq].tspll_ndivratio; 595 596 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val); 597 if (err) 598 return err; 599 600 /* Configure the TS PLL post divisor */ 601 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val); 602 if (err) 603 return err; 604 605 /* These two are constant for E825C */ 606 dw22.time1588clk_div = 5; 607 dw22.time1588clk_sel_div2 = 0; 608 609 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val); 610 if (err) 611 return err; 612 613 /* Configure the TS PLL pre divisor and clock source */ 614 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val); 615 if (err) 616 return err; 617 618 dw23.ref1588_ck_div = 619 e825c_cgu_params[clk_freq].ref1588_ck_div; 620 dw23.time_ref_sel = clk_src; 621 622 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val); 623 if (err) 624 return err; 625 626 dw24.tspll_fbdiv_frac = 627 e825c_cgu_params[clk_freq].tspll_fbdiv_frac; 628 629 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val); 630 if (err) 631 return err; 632 633 /* Finally, enable the PLL */ 634 dw23.ts_pll_enable = 1; 635 636 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val); 637 if (err) 638 return err; 639 640 /* Wait to verify if the PLL locks */ 641 usleep_range(1000, 5000); 642 643 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val); 644 if (err) 645 return err; 646 647 if (!ro_lock.plllock_true_lock_cri) { 648 dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n"); 649 return -EBUSY; 650 } 651 652 /* Log the current clock configuration */ 653 ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", 654 dw24.ts_pll_enable ? "enabled" : "disabled", 655 ice_clk_src_str(dw23.time_ref_sel), 656 ice_clk_freq_str(dw9.time_ref_freq_sel), 657 ro_lock.plllock_true_lock_cri ? "locked" : "unlocked"); 658 659 return 0; 660 } 661 662 /** 663 * ice_cfg_cgu_pll_dis_sticky_bits_e82x - disable TS PLL sticky bits 664 * @hw: pointer to the HW struct 665 * 666 * Configure the Clock Generation Unit TS PLL sticky bits so they don't latch on 667 * losing TS PLL lock, but always show current state. 668 * 669 * Return: 0 on success, other error codes when failed to read/write CGU 670 */ 671 static int ice_cfg_cgu_pll_dis_sticky_bits_e82x(struct ice_hw *hw) 672 { 673 union tspll_cntr_bist_settings cntr_bist; 674 int err; 675 676 err = ice_read_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS, 677 &cntr_bist.val); 678 if (err) 679 return err; 680 681 /* Disable sticky lock detection so lock err reported is accurate */ 682 cntr_bist.i_plllock_sel_0 = 0; 683 cntr_bist.i_plllock_sel_1 = 0; 684 685 return ice_write_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS, 686 cntr_bist.val); 687 } 688 689 /** 690 * ice_cfg_cgu_pll_dis_sticky_bits_e825c - disable TS PLL sticky bits for E825-C 691 * @hw: pointer to the HW struct 692 * 693 * Configure the Clock Generation Unit TS PLL sticky bits so they don't latch on 694 * losing TS PLL lock, but always show current state. 695 * 696 * Return: 0 on success, other error codes when failed to read/write CGU 697 */ 698 static int ice_cfg_cgu_pll_dis_sticky_bits_e825c(struct ice_hw *hw) 699 { 700 union tspll_bw_tdc_e825c bw_tdc; 701 int err; 702 703 err = ice_read_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C, &bw_tdc.val); 704 if (err) 705 return err; 706 707 bw_tdc.i_plllock_sel_1_0 = 0; 708 709 return ice_write_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C, bw_tdc.val); 710 } 711 712 /** 713 * ice_init_cgu_e82x - Initialize CGU with settings from firmware 714 * @hw: pointer to the HW structure 715 * 716 * Initialize the Clock Generation Unit of the E822 device. 717 * 718 * Return: 0 on success, other error codes when failed to read/write/cfg CGU 719 */ 720 static int ice_init_cgu_e82x(struct ice_hw *hw) 721 { 722 struct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info; 723 int err; 724 725 /* Disable sticky lock detection so lock err reported is accurate */ 726 if (ice_is_e825c(hw)) 727 err = ice_cfg_cgu_pll_dis_sticky_bits_e825c(hw); 728 else 729 err = ice_cfg_cgu_pll_dis_sticky_bits_e82x(hw); 730 if (err) 731 return err; 732 733 /* Configure the CGU PLL using the parameters from the function 734 * capabilities. 735 */ 736 if (ice_is_e825c(hw)) 737 err = ice_cfg_cgu_pll_e825c(hw, ts_info->time_ref, 738 (enum ice_clk_src)ts_info->clk_src); 739 else 740 err = ice_cfg_cgu_pll_e82x(hw, ts_info->time_ref, 741 (enum ice_clk_src)ts_info->clk_src); 742 743 return err; 744 } 745 746 /** 747 * ice_ptp_tmr_cmd_to_src_reg - Convert to source timer command value 748 * @hw: pointer to HW struct 749 * @cmd: Timer command 750 * 751 * Return: the source timer command register value for the given PTP timer 752 * command. 753 */ 754 static u32 ice_ptp_tmr_cmd_to_src_reg(struct ice_hw *hw, 755 enum ice_ptp_tmr_cmd cmd) 756 { 757 u32 cmd_val, tmr_idx; 758 759 switch (cmd) { 760 case ICE_PTP_INIT_TIME: 761 cmd_val = GLTSYN_CMD_INIT_TIME; 762 break; 763 case ICE_PTP_INIT_INCVAL: 764 cmd_val = GLTSYN_CMD_INIT_INCVAL; 765 break; 766 case ICE_PTP_ADJ_TIME: 767 cmd_val = GLTSYN_CMD_ADJ_TIME; 768 break; 769 case ICE_PTP_ADJ_TIME_AT_TIME: 770 cmd_val = GLTSYN_CMD_ADJ_INIT_TIME; 771 break; 772 case ICE_PTP_NOP: 773 case ICE_PTP_READ_TIME: 774 cmd_val = GLTSYN_CMD_READ_TIME; 775 break; 776 default: 777 dev_warn(ice_hw_to_dev(hw), 778 "Ignoring unrecognized timer command %u\n", cmd); 779 cmd_val = 0; 780 } 781 782 tmr_idx = ice_get_ptp_src_clock_index(hw); 783 784 return tmr_idx << SEL_CPK_SRC | cmd_val; 785 } 786 787 /** 788 * ice_ptp_tmr_cmd_to_port_reg- Convert to port timer command value 789 * @hw: pointer to HW struct 790 * @cmd: Timer command 791 * 792 * Note that some hardware families use a different command register value for 793 * the PHY ports, while other hardware families use the same register values 794 * as the source timer. 795 * 796 * Return: the PHY port timer command register value for the given PTP timer 797 * command. 798 */ 799 static u32 ice_ptp_tmr_cmd_to_port_reg(struct ice_hw *hw, 800 enum ice_ptp_tmr_cmd cmd) 801 { 802 u32 cmd_val, tmr_idx; 803 804 /* Certain hardware families share the same register values for the 805 * port register and source timer register. 806 */ 807 switch (hw->ptp.phy_model) { 808 case ICE_PHY_E810: 809 return ice_ptp_tmr_cmd_to_src_reg(hw, cmd) & TS_CMD_MASK_E810; 810 default: 811 break; 812 } 813 814 switch (cmd) { 815 case ICE_PTP_INIT_TIME: 816 cmd_val = PHY_CMD_INIT_TIME; 817 break; 818 case ICE_PTP_INIT_INCVAL: 819 cmd_val = PHY_CMD_INIT_INCVAL; 820 break; 821 case ICE_PTP_ADJ_TIME: 822 cmd_val = PHY_CMD_ADJ_TIME; 823 break; 824 case ICE_PTP_ADJ_TIME_AT_TIME: 825 cmd_val = PHY_CMD_ADJ_TIME_AT_TIME; 826 break; 827 case ICE_PTP_READ_TIME: 828 cmd_val = PHY_CMD_READ_TIME; 829 break; 830 case ICE_PTP_NOP: 831 cmd_val = 0; 832 break; 833 default: 834 dev_warn(ice_hw_to_dev(hw), 835 "Ignoring unrecognized timer command %u\n", cmd); 836 cmd_val = 0; 837 } 838 839 tmr_idx = ice_get_ptp_src_clock_index(hw); 840 841 return tmr_idx << SEL_PHY_SRC | cmd_val; 842 } 843 844 /** 845 * ice_ptp_src_cmd - Prepare source timer for a timer command 846 * @hw: pointer to HW structure 847 * @cmd: Timer command 848 * 849 * Prepare the source timer for an upcoming timer sync command. 850 */ 851 void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 852 { 853 u32 cmd_val = ice_ptp_tmr_cmd_to_src_reg(hw, cmd); 854 855 wr32(hw, GLTSYN_CMD, cmd_val); 856 } 857 858 /** 859 * ice_ptp_exec_tmr_cmd - Execute all prepared timer commands 860 * @hw: pointer to HW struct 861 * 862 * Write the SYNC_EXEC_CMD bit to the GLTSYN_CMD_SYNC register, and flush the 863 * write immediately. This triggers the hardware to begin executing all of the 864 * source and PHY timer commands synchronously. 865 */ 866 static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw) 867 { 868 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 869 870 guard(spinlock)(&pf->adapter->ptp_gltsyn_time_lock); 871 wr32(hw, GLTSYN_CMD_SYNC, SYNC_EXEC_CMD); 872 ice_flush(hw); 873 } 874 875 /* 56G PHY device functions 876 * 877 * The following functions operate on devices with the ETH 56G PHY. 878 */ 879 880 /** 881 * ice_write_phy_eth56g - Write a PHY port register 882 * @hw: pointer to the HW struct 883 * @phy_idx: PHY index 884 * @addr: PHY register address 885 * @val: Value to write 886 * 887 * Return: 0 on success, other error codes when failed to write to PHY 888 */ 889 static int ice_write_phy_eth56g(struct ice_hw *hw, u8 phy_idx, u32 addr, 890 u32 val) 891 { 892 struct ice_sbq_msg_input phy_msg; 893 int err; 894 895 phy_msg.opcode = ice_sbq_msg_wr; 896 897 phy_msg.msg_addr_low = lower_16_bits(addr); 898 phy_msg.msg_addr_high = upper_16_bits(addr); 899 900 phy_msg.data = val; 901 phy_msg.dest_dev = hw->ptp.phy.eth56g.phy_addr[phy_idx]; 902 903 err = ice_sbq_rw_reg(hw, &phy_msg, ICE_AQ_FLAG_RD); 904 905 if (err) 906 ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n", 907 err); 908 909 return err; 910 } 911 912 /** 913 * ice_read_phy_eth56g - Read a PHY port register 914 * @hw: pointer to the HW struct 915 * @phy_idx: PHY index 916 * @addr: PHY register address 917 * @val: Value to write 918 * 919 * Return: 0 on success, other error codes when failed to read from PHY 920 */ 921 static int ice_read_phy_eth56g(struct ice_hw *hw, u8 phy_idx, u32 addr, 922 u32 *val) 923 { 924 struct ice_sbq_msg_input phy_msg; 925 int err; 926 927 phy_msg.opcode = ice_sbq_msg_rd; 928 929 phy_msg.msg_addr_low = lower_16_bits(addr); 930 phy_msg.msg_addr_high = upper_16_bits(addr); 931 932 phy_msg.data = 0; 933 phy_msg.dest_dev = hw->ptp.phy.eth56g.phy_addr[phy_idx]; 934 935 err = ice_sbq_rw_reg(hw, &phy_msg, ICE_AQ_FLAG_RD); 936 if (err) { 937 ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n", 938 err); 939 return err; 940 } 941 942 *val = phy_msg.data; 943 944 return 0; 945 } 946 947 /** 948 * ice_phy_res_address_eth56g - Calculate a PHY port register address 949 * @port: Port number to be written 950 * @res_type: resource type (register/memory) 951 * @offset: Offset from PHY port register base 952 * @addr: The result address 953 * 954 * Return: 955 * * %0 - success 956 * * %EINVAL - invalid port number or resource type 957 */ 958 static int ice_phy_res_address_eth56g(u8 port, enum eth56g_res_type res_type, 959 u32 offset, u32 *addr) 960 { 961 u8 lane = port % ICE_PORTS_PER_QUAD; 962 u8 phy = ICE_GET_QUAD_NUM(port); 963 964 if (res_type >= NUM_ETH56G_PHY_RES) 965 return -EINVAL; 966 967 *addr = eth56g_phy_res[res_type].base[phy] + 968 lane * eth56g_phy_res[res_type].step + offset; 969 return 0; 970 } 971 972 /** 973 * ice_write_port_eth56g - Write a PHY port register 974 * @hw: pointer to the HW struct 975 * @offset: PHY register offset 976 * @port: Port number 977 * @val: Value to write 978 * @res_type: resource type (register/memory) 979 * 980 * Return: 981 * * %0 - success 982 * * %EINVAL - invalid port number or resource type 983 * * %other - failed to write to PHY 984 */ 985 static int ice_write_port_eth56g(struct ice_hw *hw, u8 port, u32 offset, 986 u32 val, enum eth56g_res_type res_type) 987 { 988 u8 phy_port = port % hw->ptp.ports_per_phy; 989 u8 phy_idx = port / hw->ptp.ports_per_phy; 990 u32 addr; 991 int err; 992 993 if (port >= hw->ptp.num_lports) 994 return -EINVAL; 995 996 err = ice_phy_res_address_eth56g(phy_port, res_type, offset, &addr); 997 if (err) 998 return err; 999 1000 return ice_write_phy_eth56g(hw, phy_idx, addr, val); 1001 } 1002 1003 /** 1004 * ice_read_port_eth56g - Read a PHY port register 1005 * @hw: pointer to the HW struct 1006 * @offset: PHY register offset 1007 * @port: Port number 1008 * @val: Value to write 1009 * @res_type: resource type (register/memory) 1010 * 1011 * Return: 1012 * * %0 - success 1013 * * %EINVAL - invalid port number or resource type 1014 * * %other - failed to read from PHY 1015 */ 1016 static int ice_read_port_eth56g(struct ice_hw *hw, u8 port, u32 offset, 1017 u32 *val, enum eth56g_res_type res_type) 1018 { 1019 u8 phy_port = port % hw->ptp.ports_per_phy; 1020 u8 phy_idx = port / hw->ptp.ports_per_phy; 1021 u32 addr; 1022 int err; 1023 1024 if (port >= hw->ptp.num_lports) 1025 return -EINVAL; 1026 1027 err = ice_phy_res_address_eth56g(phy_port, res_type, offset, &addr); 1028 if (err) 1029 return err; 1030 1031 return ice_read_phy_eth56g(hw, phy_idx, addr, val); 1032 } 1033 1034 /** 1035 * ice_write_ptp_reg_eth56g - Write a PHY port register 1036 * @hw: pointer to the HW struct 1037 * @port: Port number to be written 1038 * @offset: Offset from PHY port register base 1039 * @val: Value to write 1040 * 1041 * Return: 1042 * * %0 - success 1043 * * %EINVAL - invalid port number or resource type 1044 * * %other - failed to write to PHY 1045 */ 1046 static int ice_write_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1047 u32 val) 1048 { 1049 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_PTP); 1050 } 1051 1052 /** 1053 * ice_write_mac_reg_eth56g - Write a MAC PHY port register 1054 * parameter 1055 * @hw: pointer to the HW struct 1056 * @port: Port number to be written 1057 * @offset: Offset from PHY port register base 1058 * @val: Value to write 1059 * 1060 * Return: 1061 * * %0 - success 1062 * * %EINVAL - invalid port number or resource type 1063 * * %other - failed to write to PHY 1064 */ 1065 static int ice_write_mac_reg_eth56g(struct ice_hw *hw, u8 port, u32 offset, 1066 u32 val) 1067 { 1068 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_MAC); 1069 } 1070 1071 /** 1072 * ice_write_xpcs_reg_eth56g - Write a PHY port register 1073 * @hw: pointer to the HW struct 1074 * @port: Port number to be written 1075 * @offset: Offset from PHY port register base 1076 * @val: Value to write 1077 * 1078 * Return: 1079 * * %0 - success 1080 * * %EINVAL - invalid port number or resource type 1081 * * %other - failed to write to PHY 1082 */ 1083 static int ice_write_xpcs_reg_eth56g(struct ice_hw *hw, u8 port, u32 offset, 1084 u32 val) 1085 { 1086 return ice_write_port_eth56g(hw, port, offset, val, 1087 ETH56G_PHY_REG_XPCS); 1088 } 1089 1090 /** 1091 * ice_read_ptp_reg_eth56g - Read a PHY port register 1092 * @hw: pointer to the HW struct 1093 * @port: Port number to be read 1094 * @offset: Offset from PHY port register base 1095 * @val: Pointer to the value to read (out param) 1096 * 1097 * Return: 1098 * * %0 - success 1099 * * %EINVAL - invalid port number or resource type 1100 * * %other - failed to read from PHY 1101 */ 1102 static int ice_read_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1103 u32 *val) 1104 { 1105 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_PTP); 1106 } 1107 1108 /** 1109 * ice_read_mac_reg_eth56g - Read a PHY port register 1110 * @hw: pointer to the HW struct 1111 * @port: Port number to be read 1112 * @offset: Offset from PHY port register base 1113 * @val: Pointer to the value to read (out param) 1114 * 1115 * Return: 1116 * * %0 - success 1117 * * %EINVAL - invalid port number or resource type 1118 * * %other - failed to read from PHY 1119 */ 1120 static int ice_read_mac_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1121 u32 *val) 1122 { 1123 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_MAC); 1124 } 1125 1126 /** 1127 * ice_read_gpcs_reg_eth56g - Read a PHY port register 1128 * @hw: pointer to the HW struct 1129 * @port: Port number to be read 1130 * @offset: Offset from PHY port register base 1131 * @val: Pointer to the value to read (out param) 1132 * 1133 * Return: 1134 * * %0 - success 1135 * * %EINVAL - invalid port number or resource type 1136 * * %other - failed to read from PHY 1137 */ 1138 static int ice_read_gpcs_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1139 u32 *val) 1140 { 1141 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_GPCS); 1142 } 1143 1144 /** 1145 * ice_read_port_mem_eth56g - Read a PHY port memory location 1146 * @hw: pointer to the HW struct 1147 * @port: Port number to be read 1148 * @offset: Offset from PHY port register base 1149 * @val: Pointer to the value to read (out param) 1150 * 1151 * Return: 1152 * * %0 - success 1153 * * %EINVAL - invalid port number or resource type 1154 * * %other - failed to read from PHY 1155 */ 1156 static int ice_read_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1157 u32 *val) 1158 { 1159 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_MEM_PTP); 1160 } 1161 1162 /** 1163 * ice_write_port_mem_eth56g - Write a PHY port memory location 1164 * @hw: pointer to the HW struct 1165 * @port: Port number to be read 1166 * @offset: Offset from PHY port register base 1167 * @val: Pointer to the value to read (out param) 1168 * 1169 * Return: 1170 * * %0 - success 1171 * * %EINVAL - invalid port number or resource type 1172 * * %other - failed to write to PHY 1173 */ 1174 static int ice_write_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1175 u32 val) 1176 { 1177 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_MEM_PTP); 1178 } 1179 1180 /** 1181 * ice_is_64b_phy_reg_eth56g - Check if this is a 64bit PHY register 1182 * @low_addr: the low address to check 1183 * @high_addr: on return, contains the high address of the 64bit register 1184 * 1185 * Write the appropriate high register offset to use. 1186 * 1187 * Return: true if the provided low address is one of the known 64bit PHY values 1188 * represented as two 32bit registers, false otherwise. 1189 */ 1190 static bool ice_is_64b_phy_reg_eth56g(u16 low_addr, u16 *high_addr) 1191 { 1192 switch (low_addr) { 1193 case PHY_REG_TX_TIMER_INC_PRE_L: 1194 *high_addr = PHY_REG_TX_TIMER_INC_PRE_U; 1195 return true; 1196 case PHY_REG_RX_TIMER_INC_PRE_L: 1197 *high_addr = PHY_REG_RX_TIMER_INC_PRE_U; 1198 return true; 1199 case PHY_REG_TX_CAPTURE_L: 1200 *high_addr = PHY_REG_TX_CAPTURE_U; 1201 return true; 1202 case PHY_REG_RX_CAPTURE_L: 1203 *high_addr = PHY_REG_RX_CAPTURE_U; 1204 return true; 1205 case PHY_REG_TOTAL_TX_OFFSET_L: 1206 *high_addr = PHY_REG_TOTAL_TX_OFFSET_U; 1207 return true; 1208 case PHY_REG_TOTAL_RX_OFFSET_L: 1209 *high_addr = PHY_REG_TOTAL_RX_OFFSET_U; 1210 return true; 1211 case PHY_REG_TX_MEMORY_STATUS_L: 1212 *high_addr = PHY_REG_TX_MEMORY_STATUS_U; 1213 return true; 1214 default: 1215 return false; 1216 } 1217 } 1218 1219 /** 1220 * ice_is_40b_phy_reg_eth56g - Check if this is a 40bit PHY register 1221 * @low_addr: the low address to check 1222 * @high_addr: on return, contains the high address of the 40bit value 1223 * 1224 * Write the appropriate high register offset to use. 1225 * 1226 * Return: true if the provided low address is one of the known 40bit PHY 1227 * values split into two registers with the lower 8 bits in the low register and 1228 * the upper 32 bits in the high register, false otherwise. 1229 */ 1230 static bool ice_is_40b_phy_reg_eth56g(u16 low_addr, u16 *high_addr) 1231 { 1232 switch (low_addr) { 1233 case PHY_REG_TIMETUS_L: 1234 *high_addr = PHY_REG_TIMETUS_U; 1235 return true; 1236 case PHY_PCS_REF_TUS_L: 1237 *high_addr = PHY_PCS_REF_TUS_U; 1238 return true; 1239 case PHY_PCS_REF_INC_L: 1240 *high_addr = PHY_PCS_REF_INC_U; 1241 return true; 1242 default: 1243 return false; 1244 } 1245 } 1246 1247 /** 1248 * ice_read_64b_phy_reg_eth56g - Read a 64bit value from PHY registers 1249 * @hw: pointer to the HW struct 1250 * @port: PHY port to read from 1251 * @low_addr: offset of the lower register to read from 1252 * @val: on return, the contents of the 64bit value from the PHY registers 1253 * @res_type: resource type 1254 * 1255 * Check if the caller has specified a known 40 bit register offset and read 1256 * the two registers associated with a 40bit value and return it in the val 1257 * pointer. 1258 * 1259 * Return: 1260 * * %0 - success 1261 * * %EINVAL - not a 64 bit register 1262 * * %other - failed to read from PHY 1263 */ 1264 static int ice_read_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, 1265 u64 *val, enum eth56g_res_type res_type) 1266 { 1267 u16 high_addr; 1268 u32 lo, hi; 1269 int err; 1270 1271 if (!ice_is_64b_phy_reg_eth56g(low_addr, &high_addr)) 1272 return -EINVAL; 1273 1274 err = ice_read_port_eth56g(hw, port, low_addr, &lo, res_type); 1275 if (err) { 1276 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register %#08x\n, err %d", 1277 low_addr, err); 1278 return err; 1279 } 1280 1281 err = ice_read_port_eth56g(hw, port, high_addr, &hi, res_type); 1282 if (err) { 1283 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register %#08x\n, err %d", 1284 high_addr, err); 1285 return err; 1286 } 1287 1288 *val = ((u64)hi << 32) | lo; 1289 1290 return 0; 1291 } 1292 1293 /** 1294 * ice_read_64b_ptp_reg_eth56g - Read a 64bit value from PHY registers 1295 * @hw: pointer to the HW struct 1296 * @port: PHY port to read from 1297 * @low_addr: offset of the lower register to read from 1298 * @val: on return, the contents of the 64bit value from the PHY registers 1299 * 1300 * Check if the caller has specified a known 40 bit register offset and read 1301 * the two registers associated with a 40bit value and return it in the val 1302 * pointer. 1303 * 1304 * Return: 1305 * * %0 - success 1306 * * %EINVAL - not a 64 bit register 1307 * * %other - failed to read from PHY 1308 */ 1309 static int ice_read_64b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, 1310 u64 *val) 1311 { 1312 return ice_read_64b_phy_reg_eth56g(hw, port, low_addr, val, 1313 ETH56G_PHY_REG_PTP); 1314 } 1315 1316 /** 1317 * ice_write_40b_phy_reg_eth56g - Write a 40b value to the PHY 1318 * @hw: pointer to the HW struct 1319 * @port: port to write to 1320 * @low_addr: offset of the low register 1321 * @val: 40b value to write 1322 * @res_type: resource type 1323 * 1324 * Check if the caller has specified a known 40 bit register offset and write 1325 * provided 40b value to the two associated registers by splitting it up into 1326 * two chunks, the lower 8 bits and the upper 32 bits. 1327 * 1328 * Return: 1329 * * %0 - success 1330 * * %EINVAL - not a 40 bit register 1331 * * %other - failed to write to PHY 1332 */ 1333 static int ice_write_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port, 1334 u16 low_addr, u64 val, 1335 enum eth56g_res_type res_type) 1336 { 1337 u16 high_addr; 1338 u32 lo, hi; 1339 int err; 1340 1341 if (!ice_is_40b_phy_reg_eth56g(low_addr, &high_addr)) 1342 return -EINVAL; 1343 1344 lo = FIELD_GET(P_REG_40B_LOW_M, val); 1345 hi = (u32)(val >> P_REG_40B_HIGH_S); 1346 1347 err = ice_write_port_eth56g(hw, port, low_addr, lo, res_type); 1348 if (err) { 1349 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 1350 low_addr, err); 1351 return err; 1352 } 1353 1354 err = ice_write_port_eth56g(hw, port, high_addr, hi, res_type); 1355 if (err) { 1356 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 1357 high_addr, err); 1358 return err; 1359 } 1360 1361 return 0; 1362 } 1363 1364 /** 1365 * ice_write_40b_ptp_reg_eth56g - Write a 40b value to the PHY 1366 * @hw: pointer to the HW struct 1367 * @port: port to write to 1368 * @low_addr: offset of the low register 1369 * @val: 40b value to write 1370 * 1371 * Check if the caller has specified a known 40 bit register offset and write 1372 * provided 40b value to the two associated registers by splitting it up into 1373 * two chunks, the lower 8 bits and the upper 32 bits. 1374 * 1375 * Return: 1376 * * %0 - success 1377 * * %EINVAL - not a 40 bit register 1378 * * %other - failed to write to PHY 1379 */ 1380 static int ice_write_40b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, 1381 u16 low_addr, u64 val) 1382 { 1383 return ice_write_40b_phy_reg_eth56g(hw, port, low_addr, val, 1384 ETH56G_PHY_REG_PTP); 1385 } 1386 1387 /** 1388 * ice_write_64b_phy_reg_eth56g - Write a 64bit value to PHY registers 1389 * @hw: pointer to the HW struct 1390 * @port: PHY port to read from 1391 * @low_addr: offset of the lower register to read from 1392 * @val: the contents of the 64bit value to write to PHY 1393 * @res_type: resource type 1394 * 1395 * Check if the caller has specified a known 64 bit register offset and write 1396 * the 64bit value to the two associated 32bit PHY registers. 1397 * 1398 * Return: 1399 * * %0 - success 1400 * * %EINVAL - not a 64 bit register 1401 * * %other - failed to write to PHY 1402 */ 1403 static int ice_write_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, 1404 u16 low_addr, u64 val, 1405 enum eth56g_res_type res_type) 1406 { 1407 u16 high_addr; 1408 u32 lo, hi; 1409 int err; 1410 1411 if (!ice_is_64b_phy_reg_eth56g(low_addr, &high_addr)) 1412 return -EINVAL; 1413 1414 lo = lower_32_bits(val); 1415 hi = upper_32_bits(val); 1416 1417 err = ice_write_port_eth56g(hw, port, low_addr, lo, res_type); 1418 if (err) { 1419 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 1420 low_addr, err); 1421 return err; 1422 } 1423 1424 err = ice_write_port_eth56g(hw, port, high_addr, hi, res_type); 1425 if (err) { 1426 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 1427 high_addr, err); 1428 return err; 1429 } 1430 1431 return 0; 1432 } 1433 1434 /** 1435 * ice_write_64b_ptp_reg_eth56g - Write a 64bit value to PHY registers 1436 * @hw: pointer to the HW struct 1437 * @port: PHY port to read from 1438 * @low_addr: offset of the lower register to read from 1439 * @val: the contents of the 64bit value to write to PHY 1440 * 1441 * Check if the caller has specified a known 64 bit register offset and write 1442 * the 64bit value to the two associated 32bit PHY registers. 1443 * 1444 * Return: 1445 * * %0 - success 1446 * * %EINVAL - not a 64 bit register 1447 * * %other - failed to write to PHY 1448 */ 1449 static int ice_write_64b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, 1450 u16 low_addr, u64 val) 1451 { 1452 return ice_write_64b_phy_reg_eth56g(hw, port, low_addr, val, 1453 ETH56G_PHY_REG_PTP); 1454 } 1455 1456 /** 1457 * ice_read_ptp_tstamp_eth56g - Read a PHY timestamp out of the port memory 1458 * @hw: pointer to the HW struct 1459 * @port: the port to read from 1460 * @idx: the timestamp index to read 1461 * @tstamp: on return, the 40bit timestamp value 1462 * 1463 * Read a 40bit timestamp value out of the two associated entries in the 1464 * port memory block of the internal PHYs of the 56G devices. 1465 * 1466 * Return: 1467 * * %0 - success 1468 * * %other - failed to read from PHY 1469 */ 1470 static int ice_read_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx, 1471 u64 *tstamp) 1472 { 1473 u16 lo_addr, hi_addr; 1474 u32 lo, hi; 1475 int err; 1476 1477 lo_addr = (u16)PHY_TSTAMP_L(idx); 1478 hi_addr = (u16)PHY_TSTAMP_U(idx); 1479 1480 err = ice_read_port_mem_eth56g(hw, port, lo_addr, &lo); 1481 if (err) { 1482 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 1483 err); 1484 return err; 1485 } 1486 1487 err = ice_read_port_mem_eth56g(hw, port, hi_addr, &hi); 1488 if (err) { 1489 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 1490 err); 1491 return err; 1492 } 1493 1494 /* For 56G based internal PHYs, the timestamp is reported with the 1495 * lower 8 bits in the low register, and the upper 32 bits in the high 1496 * register. 1497 */ 1498 *tstamp = ((u64)hi) << TS_PHY_HIGH_S | ((u64)lo & TS_PHY_LOW_M); 1499 1500 return 0; 1501 } 1502 1503 /** 1504 * ice_clear_ptp_tstamp_eth56g - Clear a timestamp from the quad block 1505 * @hw: pointer to the HW struct 1506 * @port: the quad to read from 1507 * @idx: the timestamp index to reset 1508 * 1509 * Read and then forcibly clear the timestamp index to ensure the valid bit is 1510 * cleared and the timestamp status bit is reset in the PHY port memory of 1511 * internal PHYs of the 56G devices. 1512 * 1513 * To directly clear the contents of the timestamp block entirely, discarding 1514 * all timestamp data at once, software should instead use 1515 * ice_ptp_reset_ts_memory_quad_eth56g(). 1516 * 1517 * This function should only be called on an idx whose bit is set according to 1518 * ice_get_phy_tx_tstamp_ready(). 1519 * 1520 * Return: 1521 * * %0 - success 1522 * * %other - failed to write to PHY 1523 */ 1524 static int ice_clear_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx) 1525 { 1526 u64 unused_tstamp; 1527 u16 lo_addr; 1528 int err; 1529 1530 /* Read the timestamp register to ensure the timestamp status bit is 1531 * cleared. 1532 */ 1533 err = ice_read_ptp_tstamp_eth56g(hw, port, idx, &unused_tstamp); 1534 if (err) { 1535 ice_debug(hw, ICE_DBG_PTP, "Failed to read the PHY timestamp register for port %u, idx %u, err %d\n", 1536 port, idx, err); 1537 } 1538 1539 lo_addr = (u16)PHY_TSTAMP_L(idx); 1540 1541 err = ice_write_port_mem_eth56g(hw, port, lo_addr, 0); 1542 if (err) { 1543 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for port %u, idx %u, err %d\n", 1544 port, idx, err); 1545 return err; 1546 } 1547 1548 return 0; 1549 } 1550 1551 /** 1552 * ice_ptp_reset_ts_memory_eth56g - Clear all timestamps from the port block 1553 * @hw: pointer to the HW struct 1554 */ 1555 static void ice_ptp_reset_ts_memory_eth56g(struct ice_hw *hw) 1556 { 1557 unsigned int port; 1558 1559 for (port = 0; port < hw->ptp.num_lports; port++) { 1560 ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L, 1561 0); 1562 ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_U, 1563 0); 1564 } 1565 } 1566 1567 /** 1568 * ice_ptp_prep_port_time_eth56g - Prepare one PHY port with initial time 1569 * @hw: pointer to the HW struct 1570 * @port: port number 1571 * @time: time to initialize the PHY port clocks to 1572 * 1573 * Write a new initial time value into registers of a specific PHY port. 1574 * 1575 * Return: 1576 * * %0 - success 1577 * * %other - failed to write to PHY 1578 */ 1579 static int ice_ptp_prep_port_time_eth56g(struct ice_hw *hw, u8 port, 1580 u64 time) 1581 { 1582 int err; 1583 1584 /* Tx case */ 1585 err = ice_write_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_L, 1586 time); 1587 if (err) 1588 return err; 1589 1590 /* Rx case */ 1591 return ice_write_64b_ptp_reg_eth56g(hw, port, 1592 PHY_REG_RX_TIMER_INC_PRE_L, time); 1593 } 1594 1595 /** 1596 * ice_ptp_prep_phy_time_eth56g - Prepare PHY port with initial time 1597 * @hw: pointer to the HW struct 1598 * @time: Time to initialize the PHY port clocks to 1599 * 1600 * Program the PHY port registers with a new initial time value. The port 1601 * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync 1602 * command. The time value is the upper 32 bits of the PHY timer, usually in 1603 * units of nominal nanoseconds. 1604 * 1605 * Return: 1606 * * %0 - success 1607 * * %other - failed to write to PHY 1608 */ 1609 static int ice_ptp_prep_phy_time_eth56g(struct ice_hw *hw, u32 time) 1610 { 1611 u64 phy_time; 1612 u8 port; 1613 1614 /* The time represents the upper 32 bits of the PHY timer, so we need 1615 * to shift to account for this when programming. 1616 */ 1617 phy_time = (u64)time << 32; 1618 1619 for (port = 0; port < hw->ptp.num_lports; port++) { 1620 int err; 1621 1622 err = ice_ptp_prep_port_time_eth56g(hw, port, phy_time); 1623 if (err) { 1624 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n", 1625 port, err); 1626 return err; 1627 } 1628 } 1629 1630 return 0; 1631 } 1632 1633 /** 1634 * ice_ptp_prep_port_adj_eth56g - Prepare a single port for time adjust 1635 * @hw: pointer to HW struct 1636 * @port: Port number to be programmed 1637 * @time: time in cycles to adjust the port clocks 1638 * 1639 * Program the port for an atomic adjustment by writing the Tx and Rx timer 1640 * registers. The atomic adjustment won't be completed until the driver issues 1641 * an ICE_PTP_ADJ_TIME command. 1642 * 1643 * Note that time is not in units of nanoseconds. It is in clock time 1644 * including the lower sub-nanosecond portion of the port timer. 1645 * 1646 * Negative adjustments are supported using 2s complement arithmetic. 1647 * 1648 * Return: 1649 * * %0 - success 1650 * * %other - failed to write to PHY 1651 */ 1652 static int ice_ptp_prep_port_adj_eth56g(struct ice_hw *hw, u8 port, s64 time) 1653 { 1654 u32 l_time, u_time; 1655 int err; 1656 1657 l_time = lower_32_bits(time); 1658 u_time = upper_32_bits(time); 1659 1660 /* Tx case */ 1661 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_L, 1662 l_time); 1663 if (err) 1664 goto exit_err; 1665 1666 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_U, 1667 u_time); 1668 if (err) 1669 goto exit_err; 1670 1671 /* Rx case */ 1672 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TIMER_INC_PRE_L, 1673 l_time); 1674 if (err) 1675 goto exit_err; 1676 1677 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TIMER_INC_PRE_U, 1678 u_time); 1679 if (err) 1680 goto exit_err; 1681 1682 return 0; 1683 1684 exit_err: 1685 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n", 1686 port, err); 1687 return err; 1688 } 1689 1690 /** 1691 * ice_ptp_prep_phy_adj_eth56g - Prep PHY ports for a time adjustment 1692 * @hw: pointer to HW struct 1693 * @adj: adjustment in nanoseconds 1694 * 1695 * Prepare the PHY ports for an atomic time adjustment by programming the PHY 1696 * Tx and Rx port registers. The actual adjustment is completed by issuing an 1697 * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command. 1698 * 1699 * Return: 1700 * * %0 - success 1701 * * %other - failed to write to PHY 1702 */ 1703 static int ice_ptp_prep_phy_adj_eth56g(struct ice_hw *hw, s32 adj) 1704 { 1705 s64 cycles; 1706 u8 port; 1707 1708 /* The port clock supports adjustment of the sub-nanosecond portion of 1709 * the clock (lowest 32 bits). We shift the provided adjustment in 1710 * nanoseconds by 32 to calculate the appropriate adjustment to program 1711 * into the PHY ports. 1712 */ 1713 cycles = (s64)adj << 32; 1714 1715 for (port = 0; port < hw->ptp.num_lports; port++) { 1716 int err; 1717 1718 err = ice_ptp_prep_port_adj_eth56g(hw, port, cycles); 1719 if (err) 1720 return err; 1721 } 1722 1723 return 0; 1724 } 1725 1726 /** 1727 * ice_ptp_prep_phy_incval_eth56g - Prepare PHY ports for time adjustment 1728 * @hw: pointer to HW struct 1729 * @incval: new increment value to prepare 1730 * 1731 * Prepare each of the PHY ports for a new increment value by programming the 1732 * port's TIMETUS registers. The new increment value will be updated after 1733 * issuing an ICE_PTP_INIT_INCVAL command. 1734 * 1735 * Return: 1736 * * %0 - success 1737 * * %other - failed to write to PHY 1738 */ 1739 static int ice_ptp_prep_phy_incval_eth56g(struct ice_hw *hw, u64 incval) 1740 { 1741 u8 port; 1742 1743 for (port = 0; port < hw->ptp.num_lports; port++) { 1744 int err; 1745 1746 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_REG_TIMETUS_L, 1747 incval); 1748 if (err) { 1749 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n", 1750 port, err); 1751 return err; 1752 } 1753 } 1754 1755 return 0; 1756 } 1757 1758 /** 1759 * ice_ptp_read_port_capture_eth56g - Read a port's local time capture 1760 * @hw: pointer to HW struct 1761 * @port: Port number to read 1762 * @tx_ts: on return, the Tx port time capture 1763 * @rx_ts: on return, the Rx port time capture 1764 * 1765 * Read the port's Tx and Rx local time capture values. 1766 * 1767 * Return: 1768 * * %0 - success 1769 * * %other - failed to read from PHY 1770 */ 1771 static int ice_ptp_read_port_capture_eth56g(struct ice_hw *hw, u8 port, 1772 u64 *tx_ts, u64 *rx_ts) 1773 { 1774 int err; 1775 1776 /* Tx case */ 1777 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_CAPTURE_L, 1778 tx_ts); 1779 if (err) { 1780 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n", 1781 err); 1782 return err; 1783 } 1784 1785 ice_debug(hw, ICE_DBG_PTP, "tx_init = %#016llx\n", *tx_ts); 1786 1787 /* Rx case */ 1788 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_RX_CAPTURE_L, 1789 rx_ts); 1790 if (err) { 1791 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n", 1792 err); 1793 return err; 1794 } 1795 1796 ice_debug(hw, ICE_DBG_PTP, "rx_init = %#016llx\n", *rx_ts); 1797 1798 return 0; 1799 } 1800 1801 /** 1802 * ice_ptp_write_port_cmd_eth56g - Prepare a single PHY port for a timer command 1803 * @hw: pointer to HW struct 1804 * @port: Port to which cmd has to be sent 1805 * @cmd: Command to be sent to the port 1806 * 1807 * Prepare the requested port for an upcoming timer sync command. 1808 * 1809 * Return: 1810 * * %0 - success 1811 * * %other - failed to write to PHY 1812 */ 1813 static int ice_ptp_write_port_cmd_eth56g(struct ice_hw *hw, u8 port, 1814 enum ice_ptp_tmr_cmd cmd) 1815 { 1816 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 1817 int err; 1818 1819 /* Tx case */ 1820 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TMR_CMD, val); 1821 if (err) { 1822 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n", 1823 err); 1824 return err; 1825 } 1826 1827 /* Rx case */ 1828 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TMR_CMD, val); 1829 if (err) { 1830 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n", 1831 err); 1832 return err; 1833 } 1834 1835 return 0; 1836 } 1837 1838 /** 1839 * ice_phy_get_speed_eth56g - Get link speed based on PHY link type 1840 * @li: pointer to link information struct 1841 * 1842 * Return: simplified ETH56G PHY speed 1843 */ 1844 static enum ice_eth56g_link_spd 1845 ice_phy_get_speed_eth56g(struct ice_link_status *li) 1846 { 1847 u16 speed = ice_get_link_speed_based_on_phy_type(li->phy_type_low, 1848 li->phy_type_high); 1849 1850 switch (speed) { 1851 case ICE_AQ_LINK_SPEED_1000MB: 1852 return ICE_ETH56G_LNK_SPD_1G; 1853 case ICE_AQ_LINK_SPEED_2500MB: 1854 return ICE_ETH56G_LNK_SPD_2_5G; 1855 case ICE_AQ_LINK_SPEED_10GB: 1856 return ICE_ETH56G_LNK_SPD_10G; 1857 case ICE_AQ_LINK_SPEED_25GB: 1858 return ICE_ETH56G_LNK_SPD_25G; 1859 case ICE_AQ_LINK_SPEED_40GB: 1860 return ICE_ETH56G_LNK_SPD_40G; 1861 case ICE_AQ_LINK_SPEED_50GB: 1862 switch (li->phy_type_low) { 1863 case ICE_PHY_TYPE_LOW_50GBASE_SR: 1864 case ICE_PHY_TYPE_LOW_50GBASE_FR: 1865 case ICE_PHY_TYPE_LOW_50GBASE_LR: 1866 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 1867 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 1868 case ICE_PHY_TYPE_LOW_50G_AUI1: 1869 return ICE_ETH56G_LNK_SPD_50G; 1870 default: 1871 return ICE_ETH56G_LNK_SPD_50G2; 1872 } 1873 case ICE_AQ_LINK_SPEED_100GB: 1874 if (li->phy_type_high || 1875 li->phy_type_low == ICE_PHY_TYPE_LOW_100GBASE_SR2) 1876 return ICE_ETH56G_LNK_SPD_100G2; 1877 else 1878 return ICE_ETH56G_LNK_SPD_100G; 1879 default: 1880 return ICE_ETH56G_LNK_SPD_1G; 1881 } 1882 } 1883 1884 /** 1885 * ice_phy_cfg_parpcs_eth56g - Configure TUs per PAR/PCS clock cycle 1886 * @hw: pointer to the HW struct 1887 * @port: port to configure 1888 * 1889 * Configure the number of TUs for the PAR and PCS clocks used as part of the 1890 * timestamp calibration process. 1891 * 1892 * Return: 1893 * * %0 - success 1894 * * %other - PHY read/write failed 1895 */ 1896 static int ice_phy_cfg_parpcs_eth56g(struct ice_hw *hw, u8 port) 1897 { 1898 u8 port_blk = port & ~(ICE_PORTS_PER_QUAD - 1); 1899 u32 val; 1900 int err; 1901 1902 err = ice_write_xpcs_reg_eth56g(hw, port, PHY_VENDOR_TXLANE_THRESH, 1903 ICE_ETH56G_NOMINAL_THRESH4); 1904 if (err) { 1905 ice_debug(hw, ICE_DBG_PTP, "Failed to read VENDOR_TXLANE_THRESH, status: %d", 1906 err); 1907 return err; 1908 } 1909 1910 switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) { 1911 case ICE_ETH56G_LNK_SPD_1G: 1912 case ICE_ETH56G_LNK_SPD_2_5G: 1913 err = ice_read_ptp_reg_eth56g(hw, port_blk, 1914 PHY_GPCS_CONFIG_REG0, &val); 1915 if (err) { 1916 ice_debug(hw, ICE_DBG_PTP, "Failed to read PHY_GPCS_CONFIG_REG0, status: %d", 1917 err); 1918 return err; 1919 } 1920 1921 val &= ~PHY_GPCS_CONFIG_REG0_TX_THR_M; 1922 val |= FIELD_PREP(PHY_GPCS_CONFIG_REG0_TX_THR_M, 1923 ICE_ETH56G_NOMINAL_TX_THRESH); 1924 1925 err = ice_write_ptp_reg_eth56g(hw, port_blk, 1926 PHY_GPCS_CONFIG_REG0, val); 1927 if (err) { 1928 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_GPCS_CONFIG_REG0, status: %d", 1929 err); 1930 return err; 1931 } 1932 break; 1933 default: 1934 break; 1935 } 1936 1937 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_PCS_REF_TUS_L, 1938 ICE_ETH56G_NOMINAL_PCS_REF_TUS); 1939 if (err) { 1940 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_PCS_REF_TUS, status: %d", 1941 err); 1942 return err; 1943 } 1944 1945 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_PCS_REF_INC_L, 1946 ICE_ETH56G_NOMINAL_PCS_REF_INC); 1947 if (err) { 1948 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_PCS_REF_INC, status: %d", 1949 err); 1950 return err; 1951 } 1952 1953 return 0; 1954 } 1955 1956 /** 1957 * ice_phy_cfg_ptp_1step_eth56g - Configure 1-step PTP settings 1958 * @hw: Pointer to the HW struct 1959 * @port: Port to configure 1960 * 1961 * Return: 1962 * * %0 - success 1963 * * %other - PHY read/write failed 1964 */ 1965 int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port) 1966 { 1967 u8 port_blk = port & ~(ICE_PORTS_PER_QUAD - 1); 1968 u8 blk_port = port & (ICE_PORTS_PER_QUAD - 1); 1969 bool enable, sfd_ena; 1970 u32 val, peer_delay; 1971 int err; 1972 1973 enable = hw->ptp.phy.eth56g.onestep_ena; 1974 peer_delay = hw->ptp.phy.eth56g.peer_delay; 1975 sfd_ena = hw->ptp.phy.eth56g.sfd_ena; 1976 1977 /* PHY_PTP_1STEP_CONFIG */ 1978 err = ice_read_ptp_reg_eth56g(hw, port_blk, PHY_PTP_1STEP_CONFIG, &val); 1979 if (err) 1980 return err; 1981 1982 if (enable) 1983 val |= blk_port; 1984 else 1985 val &= ~blk_port; 1986 1987 val &= ~(PHY_PTP_1STEP_T1S_UP64_M | PHY_PTP_1STEP_T1S_DELTA_M); 1988 1989 err = ice_write_ptp_reg_eth56g(hw, port_blk, PHY_PTP_1STEP_CONFIG, val); 1990 if (err) 1991 return err; 1992 1993 /* PHY_PTP_1STEP_PEER_DELAY */ 1994 val = FIELD_PREP(PHY_PTP_1STEP_PD_DELAY_M, peer_delay); 1995 if (peer_delay) 1996 val |= PHY_PTP_1STEP_PD_ADD_PD_M; 1997 val |= PHY_PTP_1STEP_PD_DLY_V_M; 1998 err = ice_write_ptp_reg_eth56g(hw, port_blk, 1999 PHY_PTP_1STEP_PEER_DELAY(blk_port), val); 2000 if (err) 2001 return err; 2002 2003 val &= ~PHY_PTP_1STEP_PD_DLY_V_M; 2004 err = ice_write_ptp_reg_eth56g(hw, port_blk, 2005 PHY_PTP_1STEP_PEER_DELAY(blk_port), val); 2006 if (err) 2007 return err; 2008 2009 /* PHY_MAC_XIF_MODE */ 2010 err = ice_read_mac_reg_eth56g(hw, port, PHY_MAC_XIF_MODE, &val); 2011 if (err) 2012 return err; 2013 2014 val &= ~(PHY_MAC_XIF_1STEP_ENA_M | PHY_MAC_XIF_TS_BIN_MODE_M | 2015 PHY_MAC_XIF_TS_SFD_ENA_M | PHY_MAC_XIF_GMII_TS_SEL_M); 2016 2017 switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) { 2018 case ICE_ETH56G_LNK_SPD_1G: 2019 case ICE_ETH56G_LNK_SPD_2_5G: 2020 val |= PHY_MAC_XIF_GMII_TS_SEL_M; 2021 break; 2022 default: 2023 break; 2024 } 2025 2026 val |= FIELD_PREP(PHY_MAC_XIF_1STEP_ENA_M, enable) | 2027 FIELD_PREP(PHY_MAC_XIF_TS_BIN_MODE_M, enable) | 2028 FIELD_PREP(PHY_MAC_XIF_TS_SFD_ENA_M, sfd_ena); 2029 2030 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_XIF_MODE, val); 2031 } 2032 2033 /** 2034 * mul_u32_u32_fx_q9 - Multiply two u32 fixed point Q9 values 2035 * @a: multiplier value 2036 * @b: multiplicand value 2037 * 2038 * Return: result of multiplication 2039 */ 2040 static u32 mul_u32_u32_fx_q9(u32 a, u32 b) 2041 { 2042 return (u32)(((u64)a * b) >> ICE_ETH56G_MAC_CFG_FRAC_W); 2043 } 2044 2045 /** 2046 * add_u32_u32_fx - Add two u32 fixed point values and discard overflow 2047 * @a: first value 2048 * @b: second value 2049 * 2050 * Return: result of addition 2051 */ 2052 static u32 add_u32_u32_fx(u32 a, u32 b) 2053 { 2054 return lower_32_bits(((u64)a + b)); 2055 } 2056 2057 /** 2058 * ice_ptp_calc_bitslip_eth56g - Calculate bitslip value 2059 * @hw: pointer to the HW struct 2060 * @port: port to configure 2061 * @bs: bitslip multiplier 2062 * @fc: FC-FEC enabled 2063 * @rs: RS-FEC enabled 2064 * @spd: link speed 2065 * 2066 * Return: calculated bitslip value 2067 */ 2068 static u32 ice_ptp_calc_bitslip_eth56g(struct ice_hw *hw, u8 port, u32 bs, 2069 bool fc, bool rs, 2070 enum ice_eth56g_link_spd spd) 2071 { 2072 u8 port_offset = port & (ICE_PORTS_PER_QUAD - 1); 2073 u8 port_blk = port & ~(ICE_PORTS_PER_QUAD - 1); 2074 u32 bitslip; 2075 int err; 2076 2077 if (!bs || rs) 2078 return 0; 2079 2080 if (spd == ICE_ETH56G_LNK_SPD_1G || spd == ICE_ETH56G_LNK_SPD_2_5G) 2081 err = ice_read_gpcs_reg_eth56g(hw, port, PHY_GPCS_BITSLIP, 2082 &bitslip); 2083 else 2084 err = ice_read_ptp_reg_eth56g(hw, port_blk, 2085 PHY_REG_SD_BIT_SLIP(port_offset), 2086 &bitslip); 2087 if (err) 2088 return 0; 2089 2090 if (spd == ICE_ETH56G_LNK_SPD_1G && !bitslip) { 2091 /* Bitslip register value of 0 corresponds to 10 so substitute 2092 * it for calculations 2093 */ 2094 bitslip = 10; 2095 } else if (spd == ICE_ETH56G_LNK_SPD_10G || 2096 spd == ICE_ETH56G_LNK_SPD_25G) { 2097 if (fc) 2098 bitslip = bitslip * 2 + 32; 2099 else 2100 bitslip = (u32)((s32)bitslip * -1 + 20); 2101 } 2102 2103 bitslip <<= ICE_ETH56G_MAC_CFG_FRAC_W; 2104 return mul_u32_u32_fx_q9(bitslip, bs); 2105 } 2106 2107 /** 2108 * ice_ptp_calc_deskew_eth56g - Calculate deskew value 2109 * @hw: pointer to the HW struct 2110 * @port: port to configure 2111 * @ds: deskew multiplier 2112 * @rs: RS-FEC enabled 2113 * @spd: link speed 2114 * 2115 * Return: calculated deskew value 2116 */ 2117 static u32 ice_ptp_calc_deskew_eth56g(struct ice_hw *hw, u8 port, u32 ds, 2118 bool rs, enum ice_eth56g_link_spd spd) 2119 { 2120 u32 deskew_i, deskew_f; 2121 int err; 2122 2123 if (!ds) 2124 return 0; 2125 2126 read_poll_timeout(ice_read_ptp_reg_eth56g, err, 2127 FIELD_GET(PHY_REG_DESKEW_0_VALID, deskew_i), 500, 2128 50 * USEC_PER_MSEC, false, hw, port, PHY_REG_DESKEW_0, 2129 &deskew_i); 2130 if (err) 2131 return err; 2132 2133 deskew_f = FIELD_GET(PHY_REG_DESKEW_0_RLEVEL_FRAC, deskew_i); 2134 deskew_i = FIELD_GET(PHY_REG_DESKEW_0_RLEVEL, deskew_i); 2135 2136 if (rs && spd == ICE_ETH56G_LNK_SPD_50G2) 2137 ds = 0x633; /* 3.1 */ 2138 else if (rs && spd == ICE_ETH56G_LNK_SPD_100G) 2139 ds = 0x31b; /* 1.552 */ 2140 2141 deskew_i = FIELD_PREP(ICE_ETH56G_MAC_CFG_RX_OFFSET_INT, deskew_i); 2142 /* Shift 3 fractional bits to the end of the integer part */ 2143 deskew_f <<= ICE_ETH56G_MAC_CFG_FRAC_W - PHY_REG_DESKEW_0_RLEVEL_FRAC_W; 2144 return mul_u32_u32_fx_q9(deskew_i | deskew_f, ds); 2145 } 2146 2147 /** 2148 * ice_phy_set_offsets_eth56g - Set Tx/Rx offset values 2149 * @hw: pointer to the HW struct 2150 * @port: port to configure 2151 * @spd: link speed 2152 * @cfg: structure to store output values 2153 * @fc: FC-FEC enabled 2154 * @rs: RS-FEC enabled 2155 * 2156 * Return: 2157 * * %0 - success 2158 * * %other - failed to write to PHY 2159 */ 2160 static int ice_phy_set_offsets_eth56g(struct ice_hw *hw, u8 port, 2161 enum ice_eth56g_link_spd spd, 2162 const struct ice_eth56g_mac_reg_cfg *cfg, 2163 bool fc, bool rs) 2164 { 2165 u32 rx_offset, tx_offset, bs_ds; 2166 bool onestep, sfd; 2167 2168 onestep = hw->ptp.phy.eth56g.onestep_ena; 2169 sfd = hw->ptp.phy.eth56g.sfd_ena; 2170 bs_ds = cfg->rx_offset.bs_ds; 2171 2172 if (fc) 2173 rx_offset = cfg->rx_offset.fc; 2174 else if (rs) 2175 rx_offset = cfg->rx_offset.rs; 2176 else 2177 rx_offset = cfg->rx_offset.no_fec; 2178 2179 rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.serdes); 2180 if (sfd) 2181 rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.sfd); 2182 2183 if (spd < ICE_ETH56G_LNK_SPD_40G) 2184 bs_ds = ice_ptp_calc_bitslip_eth56g(hw, port, bs_ds, fc, rs, 2185 spd); 2186 else 2187 bs_ds = ice_ptp_calc_deskew_eth56g(hw, port, bs_ds, rs, spd); 2188 rx_offset = add_u32_u32_fx(rx_offset, bs_ds); 2189 rx_offset &= ICE_ETH56G_MAC_CFG_RX_OFFSET_INT | 2190 ICE_ETH56G_MAC_CFG_RX_OFFSET_FRAC; 2191 2192 if (fc) 2193 tx_offset = cfg->tx_offset.fc; 2194 else if (rs) 2195 tx_offset = cfg->tx_offset.rs; 2196 else 2197 tx_offset = cfg->tx_offset.no_fec; 2198 tx_offset += cfg->tx_offset.serdes + cfg->tx_offset.sfd * sfd + 2199 cfg->tx_offset.onestep * onestep; 2200 2201 ice_write_mac_reg_eth56g(hw, port, PHY_MAC_RX_OFFSET, rx_offset); 2202 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TX_OFFSET, tx_offset); 2203 } 2204 2205 /** 2206 * ice_phy_cfg_mac_eth56g - Configure MAC for PTP 2207 * @hw: Pointer to the HW struct 2208 * @port: Port to configure 2209 * 2210 * Return: 2211 * * %0 - success 2212 * * %other - failed to write to PHY 2213 */ 2214 static int ice_phy_cfg_mac_eth56g(struct ice_hw *hw, u8 port) 2215 { 2216 const struct ice_eth56g_mac_reg_cfg *cfg; 2217 enum ice_eth56g_link_spd spd; 2218 struct ice_link_status *li; 2219 bool fc = false; 2220 bool rs = false; 2221 bool onestep; 2222 u32 val; 2223 int err; 2224 2225 onestep = hw->ptp.phy.eth56g.onestep_ena; 2226 li = &hw->port_info->phy.link_info; 2227 spd = ice_phy_get_speed_eth56g(li); 2228 if (!!(li->an_info & ICE_AQ_FEC_EN)) { 2229 if (spd == ICE_ETH56G_LNK_SPD_10G) { 2230 fc = true; 2231 } else { 2232 fc = !!(li->fec_info & ICE_AQ_LINK_25G_KR_FEC_EN); 2233 rs = !!(li->fec_info & ~ICE_AQ_LINK_25G_KR_FEC_EN); 2234 } 2235 } 2236 cfg = ð56g_mac_cfg[spd]; 2237 2238 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_RX_MODULO, 0); 2239 if (err) 2240 return err; 2241 2242 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TX_MODULO, 0); 2243 if (err) 2244 return err; 2245 2246 val = FIELD_PREP(PHY_MAC_TSU_CFG_TX_MODE_M, 2247 cfg->tx_mode.def + rs * cfg->tx_mode.rs) | 2248 FIELD_PREP(PHY_MAC_TSU_CFG_TX_MII_MK_DLY_M, cfg->tx_mk_dly) | 2249 FIELD_PREP(PHY_MAC_TSU_CFG_TX_MII_CW_DLY_M, 2250 cfg->tx_cw_dly.def + 2251 onestep * cfg->tx_cw_dly.onestep) | 2252 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MODE_M, 2253 cfg->rx_mode.def + rs * cfg->rx_mode.rs) | 2254 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MII_MK_DLY_M, 2255 cfg->rx_mk_dly.def + rs * cfg->rx_mk_dly.rs) | 2256 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MII_CW_DLY_M, 2257 cfg->rx_cw_dly.def + rs * cfg->rx_cw_dly.rs) | 2258 FIELD_PREP(PHY_MAC_TSU_CFG_BLKS_PER_CLK_M, cfg->blks_per_clk); 2259 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TSU_CONFIG, val); 2260 if (err) 2261 return err; 2262 2263 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_BLOCKTIME, 2264 cfg->blktime); 2265 if (err) 2266 return err; 2267 2268 err = ice_phy_set_offsets_eth56g(hw, port, spd, cfg, fc, rs); 2269 if (err) 2270 return err; 2271 2272 if (spd == ICE_ETH56G_LNK_SPD_25G && !rs) 2273 val = 0; 2274 else 2275 val = cfg->mktime; 2276 2277 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_MARKERTIME, val); 2278 } 2279 2280 /** 2281 * ice_phy_cfg_intr_eth56g - Configure TX timestamp interrupt 2282 * @hw: pointer to the HW struct 2283 * @port: the timestamp port 2284 * @ena: enable or disable interrupt 2285 * @threshold: interrupt threshold 2286 * 2287 * Configure TX timestamp interrupt for the specified port 2288 * 2289 * Return: 2290 * * %0 - success 2291 * * %other - PHY read/write failed 2292 */ 2293 int ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold) 2294 { 2295 int err; 2296 u32 val; 2297 2298 err = ice_read_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, &val); 2299 if (err) 2300 return err; 2301 2302 if (ena) { 2303 val |= PHY_TS_INT_CONFIG_ENA_M; 2304 val &= ~PHY_TS_INT_CONFIG_THRESHOLD_M; 2305 val |= FIELD_PREP(PHY_TS_INT_CONFIG_THRESHOLD_M, threshold); 2306 } else { 2307 val &= ~PHY_TS_INT_CONFIG_ENA_M; 2308 } 2309 2310 return ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, val); 2311 } 2312 2313 /** 2314 * ice_read_phy_and_phc_time_eth56g - Simultaneously capture PHC and PHY time 2315 * @hw: pointer to the HW struct 2316 * @port: the PHY port to read 2317 * @phy_time: on return, the 64bit PHY timer value 2318 * @phc_time: on return, the lower 64bits of PHC time 2319 * 2320 * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY 2321 * and PHC timer values. 2322 * 2323 * Return: 2324 * * %0 - success 2325 * * %other - PHY read/write failed 2326 */ 2327 static int ice_read_phy_and_phc_time_eth56g(struct ice_hw *hw, u8 port, 2328 u64 *phy_time, u64 *phc_time) 2329 { 2330 u64 tx_time, rx_time; 2331 u32 zo, lo; 2332 u8 tmr_idx; 2333 int err; 2334 2335 tmr_idx = ice_get_ptp_src_clock_index(hw); 2336 2337 /* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */ 2338 ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME); 2339 2340 /* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */ 2341 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME); 2342 if (err) 2343 return err; 2344 2345 /* Issue the sync to start the ICE_PTP_READ_TIME capture */ 2346 ice_ptp_exec_tmr_cmd(hw); 2347 2348 /* Read the captured PHC time from the shadow time registers */ 2349 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx)); 2350 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx)); 2351 *phc_time = (u64)lo << 32 | zo; 2352 2353 /* Read the captured PHY time from the PHY shadow registers */ 2354 err = ice_ptp_read_port_capture_eth56g(hw, port, &tx_time, &rx_time); 2355 if (err) 2356 return err; 2357 2358 /* If the PHY Tx and Rx timers don't match, log a warning message. 2359 * Note that this should not happen in normal circumstances since the 2360 * driver always programs them together. 2361 */ 2362 if (tx_time != rx_time) 2363 dev_warn(ice_hw_to_dev(hw), "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n", 2364 port, tx_time, rx_time); 2365 2366 *phy_time = tx_time; 2367 2368 return 0; 2369 } 2370 2371 /** 2372 * ice_sync_phy_timer_eth56g - Synchronize the PHY timer with PHC timer 2373 * @hw: pointer to the HW struct 2374 * @port: the PHY port to synchronize 2375 * 2376 * Perform an adjustment to ensure that the PHY and PHC timers are in sync. 2377 * This is done by issuing a ICE_PTP_READ_TIME command which triggers a 2378 * simultaneous read of the PHY timer and PHC timer. Then we use the 2379 * difference to calculate an appropriate 2s complement addition to add 2380 * to the PHY timer in order to ensure it reads the same value as the 2381 * primary PHC timer. 2382 * 2383 * Return: 2384 * * %0 - success 2385 * * %-EBUSY- failed to acquire PTP semaphore 2386 * * %other - PHY read/write failed 2387 */ 2388 static int ice_sync_phy_timer_eth56g(struct ice_hw *hw, u8 port) 2389 { 2390 u64 phc_time, phy_time, difference; 2391 int err; 2392 2393 if (!ice_ptp_lock(hw)) { 2394 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n"); 2395 return -EBUSY; 2396 } 2397 2398 err = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time, &phc_time); 2399 if (err) 2400 goto err_unlock; 2401 2402 /* Calculate the amount required to add to the port time in order for 2403 * it to match the PHC time. 2404 * 2405 * Note that the port adjustment is done using 2s complement 2406 * arithmetic. This is convenient since it means that we can simply 2407 * calculate the difference between the PHC time and the port time, 2408 * and it will be interpreted correctly. 2409 */ 2410 2411 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 2412 difference = phc_time - phy_time; 2413 2414 err = ice_ptp_prep_port_adj_eth56g(hw, port, (s64)difference); 2415 if (err) 2416 goto err_unlock; 2417 2418 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME); 2419 if (err) 2420 goto err_unlock; 2421 2422 /* Issue the sync to activate the time adjustment */ 2423 ice_ptp_exec_tmr_cmd(hw); 2424 2425 /* Re-capture the timer values to flush the command registers and 2426 * verify that the time was properly adjusted. 2427 */ 2428 err = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time, &phc_time); 2429 if (err) 2430 goto err_unlock; 2431 2432 dev_info(ice_hw_to_dev(hw), 2433 "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n", 2434 port, phy_time, phc_time); 2435 2436 err_unlock: 2437 ice_ptp_unlock(hw); 2438 return err; 2439 } 2440 2441 /** 2442 * ice_stop_phy_timer_eth56g - Stop the PHY clock timer 2443 * @hw: pointer to the HW struct 2444 * @port: the PHY port to stop 2445 * @soft_reset: if true, hold the SOFT_RESET bit of PHY_REG_PS 2446 * 2447 * Stop the clock of a PHY port. This must be done as part of the flow to 2448 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 2449 * initialized or when link speed changes. 2450 * 2451 * Return: 2452 * * %0 - success 2453 * * %other - failed to write to PHY 2454 */ 2455 int ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset) 2456 { 2457 int err; 2458 2459 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 0); 2460 if (err) 2461 return err; 2462 2463 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 0); 2464 if (err) 2465 return err; 2466 2467 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port); 2468 2469 return 0; 2470 } 2471 2472 /** 2473 * ice_start_phy_timer_eth56g - Start the PHY clock timer 2474 * @hw: pointer to the HW struct 2475 * @port: the PHY port to start 2476 * 2477 * Start the clock of a PHY port. This must be done as part of the flow to 2478 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 2479 * initialized or when link speed changes. 2480 * 2481 * Return: 2482 * * %0 - success 2483 * * %other - PHY read/write failed 2484 */ 2485 int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port) 2486 { 2487 u32 lo, hi; 2488 u64 incval; 2489 u8 tmr_idx; 2490 int err; 2491 2492 tmr_idx = ice_get_ptp_src_clock_index(hw); 2493 2494 err = ice_stop_phy_timer_eth56g(hw, port, false); 2495 if (err) 2496 return err; 2497 2498 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 2499 2500 err = ice_phy_cfg_parpcs_eth56g(hw, port); 2501 if (err) 2502 return err; 2503 2504 err = ice_phy_cfg_ptp_1step_eth56g(hw, port); 2505 if (err) 2506 return err; 2507 2508 err = ice_phy_cfg_mac_eth56g(hw, port); 2509 if (err) 2510 return err; 2511 2512 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 2513 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 2514 incval = (u64)hi << 32 | lo; 2515 2516 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_REG_TIMETUS_L, incval); 2517 if (err) 2518 return err; 2519 2520 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL); 2521 if (err) 2522 return err; 2523 2524 ice_ptp_exec_tmr_cmd(hw); 2525 2526 err = ice_sync_phy_timer_eth56g(hw, port); 2527 if (err) 2528 return err; 2529 2530 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 1); 2531 if (err) 2532 return err; 2533 2534 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 1); 2535 if (err) 2536 return err; 2537 2538 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port); 2539 2540 return 0; 2541 } 2542 2543 /** 2544 * ice_sb_access_ena_eth56g - Enable SB devices (PHY and others) access 2545 * @hw: pointer to HW struct 2546 * @enable: Enable or disable access 2547 * 2548 * Enable sideband devices (PHY and others) access. 2549 */ 2550 static void ice_sb_access_ena_eth56g(struct ice_hw *hw, bool enable) 2551 { 2552 u32 val = rd32(hw, PF_SB_REM_DEV_CTL); 2553 2554 if (enable) 2555 val |= BIT(eth56g_phy_0) | BIT(cgu) | BIT(eth56g_phy_1); 2556 else 2557 val &= ~(BIT(eth56g_phy_0) | BIT(cgu) | BIT(eth56g_phy_1)); 2558 2559 wr32(hw, PF_SB_REM_DEV_CTL, val); 2560 } 2561 2562 /** 2563 * ice_ptp_init_phc_eth56g - Perform E82X specific PHC initialization 2564 * @hw: pointer to HW struct 2565 * 2566 * Perform PHC initialization steps specific to E82X devices. 2567 * 2568 * Return: 2569 * * %0 - success 2570 * * %other - failed to initialize CGU 2571 */ 2572 static int ice_ptp_init_phc_eth56g(struct ice_hw *hw) 2573 { 2574 ice_sb_access_ena_eth56g(hw, true); 2575 /* Initialize the Clock Generation Unit */ 2576 return ice_init_cgu_e82x(hw); 2577 } 2578 2579 /** 2580 * ice_ptp_read_tx_hwtstamp_status_eth56g - Get TX timestamp status 2581 * @hw: pointer to the HW struct 2582 * @ts_status: the timestamp mask pointer 2583 * 2584 * Read the PHY Tx timestamp status mask indicating which ports have Tx 2585 * timestamps available. 2586 * 2587 * Return: 2588 * * %0 - success 2589 * * %other - failed to read from PHY 2590 */ 2591 int ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status) 2592 { 2593 const struct ice_eth56g_params *params = &hw->ptp.phy.eth56g; 2594 u8 phy, mask; 2595 u32 status; 2596 2597 mask = (1 << hw->ptp.ports_per_phy) - 1; 2598 *ts_status = 0; 2599 2600 for (phy = 0; phy < params->num_phys; phy++) { 2601 int err; 2602 2603 err = ice_read_phy_eth56g(hw, phy, PHY_PTP_INT_STATUS, &status); 2604 if (err) 2605 return err; 2606 2607 *ts_status |= (status & mask) << (phy * hw->ptp.ports_per_phy); 2608 } 2609 2610 ice_debug(hw, ICE_DBG_PTP, "PHY interrupt err: %x\n", *ts_status); 2611 2612 return 0; 2613 } 2614 2615 /** 2616 * ice_get_phy_tx_tstamp_ready_eth56g - Read the Tx memory status register 2617 * @hw: pointer to the HW struct 2618 * @port: the PHY port to read from 2619 * @tstamp_ready: contents of the Tx memory status register 2620 * 2621 * Read the PHY_REG_TX_MEMORY_STATUS register indicating which timestamps in 2622 * the PHY are ready. A set bit means the corresponding timestamp is valid and 2623 * ready to be captured from the PHY timestamp block. 2624 * 2625 * Return: 2626 * * %0 - success 2627 * * %other - failed to read from PHY 2628 */ 2629 static int ice_get_phy_tx_tstamp_ready_eth56g(struct ice_hw *hw, u8 port, 2630 u64 *tstamp_ready) 2631 { 2632 int err; 2633 2634 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L, 2635 tstamp_ready); 2636 if (err) { 2637 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS for port %u, err %d\n", 2638 port, err); 2639 return err; 2640 } 2641 2642 return 0; 2643 } 2644 2645 /** 2646 * ice_is_muxed_topo - detect breakout 2x50G topology for E825C 2647 * @hw: pointer to the HW struct 2648 * 2649 * Return: true if it's 2x50 breakout topology, false otherwise 2650 */ 2651 static bool ice_is_muxed_topo(struct ice_hw *hw) 2652 { 2653 u8 link_topo; 2654 bool mux; 2655 u32 val; 2656 2657 val = rd32(hw, GLGEN_SWITCH_MODE_CONFIG); 2658 mux = FIELD_GET(GLGEN_SWITCH_MODE_CONFIG_25X4_QUAD_M, val); 2659 val = rd32(hw, GLGEN_MAC_LINK_TOPO); 2660 link_topo = FIELD_GET(GLGEN_MAC_LINK_TOPO_LINK_TOPO_M, val); 2661 2662 return (mux && link_topo == ICE_LINK_TOPO_UP_TO_2_LINKS); 2663 } 2664 2665 /** 2666 * ice_ptp_init_phy_e825c - initialize PHY parameters 2667 * @hw: pointer to the HW struct 2668 */ 2669 static void ice_ptp_init_phy_e825c(struct ice_hw *hw) 2670 { 2671 struct ice_ptp_hw *ptp = &hw->ptp; 2672 struct ice_eth56g_params *params; 2673 u8 phy; 2674 2675 ptp->phy_model = ICE_PHY_ETH56G; 2676 params = &ptp->phy.eth56g; 2677 params->onestep_ena = false; 2678 params->peer_delay = 0; 2679 params->sfd_ena = false; 2680 params->phy_addr[0] = eth56g_phy_0; 2681 params->phy_addr[1] = eth56g_phy_1; 2682 params->num_phys = 2; 2683 ptp->ports_per_phy = 4; 2684 ptp->num_lports = params->num_phys * ptp->ports_per_phy; 2685 2686 ice_sb_access_ena_eth56g(hw, true); 2687 for (phy = 0; phy < params->num_phys; phy++) { 2688 u32 phy_rev; 2689 int err; 2690 2691 err = ice_read_phy_eth56g(hw, phy, PHY_REG_REVISION, &phy_rev); 2692 if (err || phy_rev != PHY_REVISION_ETH56G) { 2693 ptp->phy_model = ICE_PHY_UNSUP; 2694 return; 2695 } 2696 } 2697 2698 ptp->is_2x50g_muxed_topo = ice_is_muxed_topo(hw); 2699 } 2700 2701 /* E822 family functions 2702 * 2703 * The following functions operate on the E822 family of devices. 2704 */ 2705 2706 /** 2707 * ice_fill_phy_msg_e82x - Fill message data for a PHY register access 2708 * @hw: pointer to the HW struct 2709 * @msg: the PHY message buffer to fill in 2710 * @port: the port to access 2711 * @offset: the register offset 2712 */ 2713 static void ice_fill_phy_msg_e82x(struct ice_hw *hw, 2714 struct ice_sbq_msg_input *msg, u8 port, 2715 u16 offset) 2716 { 2717 int phy_port, phy, quadtype; 2718 2719 phy_port = port % hw->ptp.ports_per_phy; 2720 phy = port / hw->ptp.ports_per_phy; 2721 quadtype = ICE_GET_QUAD_NUM(port) % 2722 ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy); 2723 2724 if (quadtype == 0) { 2725 msg->msg_addr_low = P_Q0_L(P_0_BASE + offset, phy_port); 2726 msg->msg_addr_high = P_Q0_H(P_0_BASE + offset, phy_port); 2727 } else { 2728 msg->msg_addr_low = P_Q1_L(P_4_BASE + offset, phy_port); 2729 msg->msg_addr_high = P_Q1_H(P_4_BASE + offset, phy_port); 2730 } 2731 2732 if (phy == 0) 2733 msg->dest_dev = rmn_0; 2734 else if (phy == 1) 2735 msg->dest_dev = rmn_1; 2736 else 2737 msg->dest_dev = rmn_2; 2738 } 2739 2740 /** 2741 * ice_is_64b_phy_reg_e82x - Check if this is a 64bit PHY register 2742 * @low_addr: the low address to check 2743 * @high_addr: on return, contains the high address of the 64bit register 2744 * 2745 * Checks if the provided low address is one of the known 64bit PHY values 2746 * represented as two 32bit registers. If it is, return the appropriate high 2747 * register offset to use. 2748 */ 2749 static bool ice_is_64b_phy_reg_e82x(u16 low_addr, u16 *high_addr) 2750 { 2751 switch (low_addr) { 2752 case P_REG_PAR_PCS_TX_OFFSET_L: 2753 *high_addr = P_REG_PAR_PCS_TX_OFFSET_U; 2754 return true; 2755 case P_REG_PAR_PCS_RX_OFFSET_L: 2756 *high_addr = P_REG_PAR_PCS_RX_OFFSET_U; 2757 return true; 2758 case P_REG_PAR_TX_TIME_L: 2759 *high_addr = P_REG_PAR_TX_TIME_U; 2760 return true; 2761 case P_REG_PAR_RX_TIME_L: 2762 *high_addr = P_REG_PAR_RX_TIME_U; 2763 return true; 2764 case P_REG_TOTAL_TX_OFFSET_L: 2765 *high_addr = P_REG_TOTAL_TX_OFFSET_U; 2766 return true; 2767 case P_REG_TOTAL_RX_OFFSET_L: 2768 *high_addr = P_REG_TOTAL_RX_OFFSET_U; 2769 return true; 2770 case P_REG_UIX66_10G_40G_L: 2771 *high_addr = P_REG_UIX66_10G_40G_U; 2772 return true; 2773 case P_REG_UIX66_25G_100G_L: 2774 *high_addr = P_REG_UIX66_25G_100G_U; 2775 return true; 2776 case P_REG_TX_CAPTURE_L: 2777 *high_addr = P_REG_TX_CAPTURE_U; 2778 return true; 2779 case P_REG_RX_CAPTURE_L: 2780 *high_addr = P_REG_RX_CAPTURE_U; 2781 return true; 2782 case P_REG_TX_TIMER_INC_PRE_L: 2783 *high_addr = P_REG_TX_TIMER_INC_PRE_U; 2784 return true; 2785 case P_REG_RX_TIMER_INC_PRE_L: 2786 *high_addr = P_REG_RX_TIMER_INC_PRE_U; 2787 return true; 2788 default: 2789 return false; 2790 } 2791 } 2792 2793 /** 2794 * ice_is_40b_phy_reg_e82x - Check if this is a 40bit PHY register 2795 * @low_addr: the low address to check 2796 * @high_addr: on return, contains the high address of the 40bit value 2797 * 2798 * Checks if the provided low address is one of the known 40bit PHY values 2799 * split into two registers with the lower 8 bits in the low register and the 2800 * upper 32 bits in the high register. If it is, return the appropriate high 2801 * register offset to use. 2802 */ 2803 static bool ice_is_40b_phy_reg_e82x(u16 low_addr, u16 *high_addr) 2804 { 2805 switch (low_addr) { 2806 case P_REG_TIMETUS_L: 2807 *high_addr = P_REG_TIMETUS_U; 2808 return true; 2809 case P_REG_PAR_RX_TUS_L: 2810 *high_addr = P_REG_PAR_RX_TUS_U; 2811 return true; 2812 case P_REG_PAR_TX_TUS_L: 2813 *high_addr = P_REG_PAR_TX_TUS_U; 2814 return true; 2815 case P_REG_PCS_RX_TUS_L: 2816 *high_addr = P_REG_PCS_RX_TUS_U; 2817 return true; 2818 case P_REG_PCS_TX_TUS_L: 2819 *high_addr = P_REG_PCS_TX_TUS_U; 2820 return true; 2821 case P_REG_DESK_PAR_RX_TUS_L: 2822 *high_addr = P_REG_DESK_PAR_RX_TUS_U; 2823 return true; 2824 case P_REG_DESK_PAR_TX_TUS_L: 2825 *high_addr = P_REG_DESK_PAR_TX_TUS_U; 2826 return true; 2827 case P_REG_DESK_PCS_RX_TUS_L: 2828 *high_addr = P_REG_DESK_PCS_RX_TUS_U; 2829 return true; 2830 case P_REG_DESK_PCS_TX_TUS_L: 2831 *high_addr = P_REG_DESK_PCS_TX_TUS_U; 2832 return true; 2833 default: 2834 return false; 2835 } 2836 } 2837 2838 /** 2839 * ice_read_phy_reg_e82x - Read a PHY register 2840 * @hw: pointer to the HW struct 2841 * @port: PHY port to read from 2842 * @offset: PHY register offset to read 2843 * @val: on return, the contents read from the PHY 2844 * 2845 * Read a PHY register for the given port over the device sideband queue. 2846 */ 2847 static int 2848 ice_read_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 *val) 2849 { 2850 struct ice_sbq_msg_input msg = {0}; 2851 int err; 2852 2853 ice_fill_phy_msg_e82x(hw, &msg, port, offset); 2854 msg.opcode = ice_sbq_msg_rd; 2855 2856 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 2857 if (err) { 2858 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2859 err); 2860 return err; 2861 } 2862 2863 *val = msg.data; 2864 2865 return 0; 2866 } 2867 2868 /** 2869 * ice_read_64b_phy_reg_e82x - Read a 64bit value from PHY registers 2870 * @hw: pointer to the HW struct 2871 * @port: PHY port to read from 2872 * @low_addr: offset of the lower register to read from 2873 * @val: on return, the contents of the 64bit value from the PHY registers 2874 * 2875 * Reads the two registers associated with a 64bit value and returns it in the 2876 * val pointer. The offset always specifies the lower register offset to use. 2877 * The high offset is looked up. This function only operates on registers 2878 * known to be two parts of a 64bit value. 2879 */ 2880 static int 2881 ice_read_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val) 2882 { 2883 u32 low, high; 2884 u16 high_addr; 2885 int err; 2886 2887 /* Only operate on registers known to be split into two 32bit 2888 * registers. 2889 */ 2890 if (!ice_is_64b_phy_reg_e82x(low_addr, &high_addr)) { 2891 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n", 2892 low_addr); 2893 return -EINVAL; 2894 } 2895 2896 err = ice_read_phy_reg_e82x(hw, port, low_addr, &low); 2897 if (err) { 2898 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, err %d", 2899 low_addr, err); 2900 return err; 2901 } 2902 2903 err = ice_read_phy_reg_e82x(hw, port, high_addr, &high); 2904 if (err) { 2905 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, err %d", 2906 high_addr, err); 2907 return err; 2908 } 2909 2910 *val = (u64)high << 32 | low; 2911 2912 return 0; 2913 } 2914 2915 /** 2916 * ice_write_phy_reg_e82x - Write a PHY register 2917 * @hw: pointer to the HW struct 2918 * @port: PHY port to write to 2919 * @offset: PHY register offset to write 2920 * @val: The value to write to the register 2921 * 2922 * Write a PHY register for the given port over the device sideband queue. 2923 */ 2924 static int 2925 ice_write_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 val) 2926 { 2927 struct ice_sbq_msg_input msg = {0}; 2928 int err; 2929 2930 ice_fill_phy_msg_e82x(hw, &msg, port, offset); 2931 msg.opcode = ice_sbq_msg_wr; 2932 msg.data = val; 2933 2934 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 2935 if (err) { 2936 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2937 err); 2938 return err; 2939 } 2940 2941 return 0; 2942 } 2943 2944 /** 2945 * ice_write_40b_phy_reg_e82x - Write a 40b value to the PHY 2946 * @hw: pointer to the HW struct 2947 * @port: port to write to 2948 * @low_addr: offset of the low register 2949 * @val: 40b value to write 2950 * 2951 * Write the provided 40b value to the two associated registers by splitting 2952 * it up into two chunks, the lower 8 bits and the upper 32 bits. 2953 */ 2954 static int 2955 ice_write_40b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) 2956 { 2957 u32 low, high; 2958 u16 high_addr; 2959 int err; 2960 2961 /* Only operate on registers known to be split into a lower 8 bit 2962 * register and an upper 32 bit register. 2963 */ 2964 if (!ice_is_40b_phy_reg_e82x(low_addr, &high_addr)) { 2965 ice_debug(hw, ICE_DBG_PTP, "Invalid 40b register addr 0x%08x\n", 2966 low_addr); 2967 return -EINVAL; 2968 } 2969 low = FIELD_GET(P_REG_40B_LOW_M, val); 2970 high = (u32)(val >> P_REG_40B_HIGH_S); 2971 2972 err = ice_write_phy_reg_e82x(hw, port, low_addr, low); 2973 if (err) { 2974 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 2975 low_addr, err); 2976 return err; 2977 } 2978 2979 err = ice_write_phy_reg_e82x(hw, port, high_addr, high); 2980 if (err) { 2981 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 2982 high_addr, err); 2983 return err; 2984 } 2985 2986 return 0; 2987 } 2988 2989 /** 2990 * ice_write_64b_phy_reg_e82x - Write a 64bit value to PHY registers 2991 * @hw: pointer to the HW struct 2992 * @port: PHY port to read from 2993 * @low_addr: offset of the lower register to read from 2994 * @val: the contents of the 64bit value to write to PHY 2995 * 2996 * Write the 64bit value to the two associated 32bit PHY registers. The offset 2997 * is always specified as the lower register, and the high address is looked 2998 * up. This function only operates on registers known to be two parts of 2999 * a 64bit value. 3000 */ 3001 static int 3002 ice_write_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) 3003 { 3004 u32 low, high; 3005 u16 high_addr; 3006 int err; 3007 3008 /* Only operate on registers known to be split into two 32bit 3009 * registers. 3010 */ 3011 if (!ice_is_64b_phy_reg_e82x(low_addr, &high_addr)) { 3012 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n", 3013 low_addr); 3014 return -EINVAL; 3015 } 3016 3017 low = lower_32_bits(val); 3018 high = upper_32_bits(val); 3019 3020 err = ice_write_phy_reg_e82x(hw, port, low_addr, low); 3021 if (err) { 3022 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 3023 low_addr, err); 3024 return err; 3025 } 3026 3027 err = ice_write_phy_reg_e82x(hw, port, high_addr, high); 3028 if (err) { 3029 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 3030 high_addr, err); 3031 return err; 3032 } 3033 3034 return 0; 3035 } 3036 3037 /** 3038 * ice_fill_quad_msg_e82x - Fill message data for quad register access 3039 * @hw: pointer to the HW struct 3040 * @msg: the PHY message buffer to fill in 3041 * @quad: the quad to access 3042 * @offset: the register offset 3043 * 3044 * Fill a message buffer for accessing a register in a quad shared between 3045 * multiple PHYs. 3046 * 3047 * Return: 3048 * * %0 - OK 3049 * * %-EINVAL - invalid quad number 3050 */ 3051 static int ice_fill_quad_msg_e82x(struct ice_hw *hw, 3052 struct ice_sbq_msg_input *msg, u8 quad, 3053 u16 offset) 3054 { 3055 u32 addr; 3056 3057 if (quad >= ICE_GET_QUAD_NUM(hw->ptp.num_lports)) 3058 return -EINVAL; 3059 3060 msg->dest_dev = rmn_0; 3061 3062 if (!(quad % ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy))) 3063 addr = Q_0_BASE + offset; 3064 else 3065 addr = Q_1_BASE + offset; 3066 3067 msg->msg_addr_low = lower_16_bits(addr); 3068 msg->msg_addr_high = upper_16_bits(addr); 3069 3070 return 0; 3071 } 3072 3073 /** 3074 * ice_read_quad_reg_e82x - Read a PHY quad register 3075 * @hw: pointer to the HW struct 3076 * @quad: quad to read from 3077 * @offset: quad register offset to read 3078 * @val: on return, the contents read from the quad 3079 * 3080 * Read a quad register over the device sideband queue. Quad registers are 3081 * shared between multiple PHYs. 3082 */ 3083 int 3084 ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val) 3085 { 3086 struct ice_sbq_msg_input msg = {0}; 3087 int err; 3088 3089 err = ice_fill_quad_msg_e82x(hw, &msg, quad, offset); 3090 if (err) 3091 return err; 3092 3093 msg.opcode = ice_sbq_msg_rd; 3094 3095 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 3096 if (err) { 3097 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 3098 err); 3099 return err; 3100 } 3101 3102 *val = msg.data; 3103 3104 return 0; 3105 } 3106 3107 /** 3108 * ice_write_quad_reg_e82x - Write a PHY quad register 3109 * @hw: pointer to the HW struct 3110 * @quad: quad to write to 3111 * @offset: quad register offset to write 3112 * @val: The value to write to the register 3113 * 3114 * Write a quad register over the device sideband queue. Quad registers are 3115 * shared between multiple PHYs. 3116 */ 3117 int 3118 ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val) 3119 { 3120 struct ice_sbq_msg_input msg = {0}; 3121 int err; 3122 3123 err = ice_fill_quad_msg_e82x(hw, &msg, quad, offset); 3124 if (err) 3125 return err; 3126 3127 msg.opcode = ice_sbq_msg_wr; 3128 msg.data = val; 3129 3130 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 3131 if (err) { 3132 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 3133 err); 3134 return err; 3135 } 3136 3137 return 0; 3138 } 3139 3140 /** 3141 * ice_read_phy_tstamp_e82x - Read a PHY timestamp out of the quad block 3142 * @hw: pointer to the HW struct 3143 * @quad: the quad to read from 3144 * @idx: the timestamp index to read 3145 * @tstamp: on return, the 40bit timestamp value 3146 * 3147 * Read a 40bit timestamp value out of the two associated registers in the 3148 * quad memory block that is shared between the internal PHYs of the E822 3149 * family of devices. 3150 */ 3151 static int 3152 ice_read_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp) 3153 { 3154 u16 lo_addr, hi_addr; 3155 u32 lo, hi; 3156 int err; 3157 3158 lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx); 3159 hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx); 3160 3161 err = ice_read_quad_reg_e82x(hw, quad, lo_addr, &lo); 3162 if (err) { 3163 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 3164 err); 3165 return err; 3166 } 3167 3168 err = ice_read_quad_reg_e82x(hw, quad, hi_addr, &hi); 3169 if (err) { 3170 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 3171 err); 3172 return err; 3173 } 3174 3175 /* For E822 based internal PHYs, the timestamp is reported with the 3176 * lower 8 bits in the low register, and the upper 32 bits in the high 3177 * register. 3178 */ 3179 *tstamp = FIELD_PREP(TS_PHY_HIGH_M, hi) | FIELD_PREP(TS_PHY_LOW_M, lo); 3180 3181 return 0; 3182 } 3183 3184 /** 3185 * ice_clear_phy_tstamp_e82x - Clear a timestamp from the quad block 3186 * @hw: pointer to the HW struct 3187 * @quad: the quad to read from 3188 * @idx: the timestamp index to reset 3189 * 3190 * Read the timestamp out of the quad to clear its timestamp status bit from 3191 * the PHY quad block that is shared between the internal PHYs of the E822 3192 * devices. 3193 * 3194 * Note that unlike E810, software cannot directly write to the quad memory 3195 * bank registers. E822 relies on the ice_get_phy_tx_tstamp_ready() function 3196 * to determine which timestamps are valid. Reading a timestamp auto-clears 3197 * the valid bit. 3198 * 3199 * To directly clear the contents of the timestamp block entirely, discarding 3200 * all timestamp data at once, software should instead use 3201 * ice_ptp_reset_ts_memory_quad_e82x(). 3202 * 3203 * This function should only be called on an idx whose bit is set according to 3204 * ice_get_phy_tx_tstamp_ready(). 3205 */ 3206 static int 3207 ice_clear_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx) 3208 { 3209 u64 unused_tstamp; 3210 int err; 3211 3212 err = ice_read_phy_tstamp_e82x(hw, quad, idx, &unused_tstamp); 3213 if (err) { 3214 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for quad %u, idx %u, err %d\n", 3215 quad, idx, err); 3216 return err; 3217 } 3218 3219 return 0; 3220 } 3221 3222 /** 3223 * ice_ptp_reset_ts_memory_quad_e82x - Clear all timestamps from the quad block 3224 * @hw: pointer to the HW struct 3225 * @quad: the quad to read from 3226 * 3227 * Clear all timestamps from the PHY quad block that is shared between the 3228 * internal PHYs on the E822 devices. 3229 */ 3230 void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad) 3231 { 3232 ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M); 3233 ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M); 3234 } 3235 3236 /** 3237 * ice_ptp_reset_ts_memory_e82x - Clear all timestamps from all quad blocks 3238 * @hw: pointer to the HW struct 3239 */ 3240 static void ice_ptp_reset_ts_memory_e82x(struct ice_hw *hw) 3241 { 3242 unsigned int quad; 3243 3244 for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports); quad++) 3245 ice_ptp_reset_ts_memory_quad_e82x(hw, quad); 3246 } 3247 3248 /** 3249 * ice_ptp_set_vernier_wl - Set the window length for vernier calibration 3250 * @hw: pointer to the HW struct 3251 * 3252 * Set the window length used for the vernier port calibration process. 3253 */ 3254 static int ice_ptp_set_vernier_wl(struct ice_hw *hw) 3255 { 3256 u8 port; 3257 3258 for (port = 0; port < hw->ptp.num_lports; port++) { 3259 int err; 3260 3261 err = ice_write_phy_reg_e82x(hw, port, P_REG_WL, 3262 PTP_VERNIER_WL); 3263 if (err) { 3264 ice_debug(hw, ICE_DBG_PTP, "Failed to set vernier window length for port %u, err %d\n", 3265 port, err); 3266 return err; 3267 } 3268 } 3269 3270 return 0; 3271 } 3272 3273 /** 3274 * ice_ptp_init_phc_e82x - Perform E822 specific PHC initialization 3275 * @hw: pointer to HW struct 3276 * 3277 * Perform PHC initialization steps specific to E822 devices. 3278 */ 3279 static int ice_ptp_init_phc_e82x(struct ice_hw *hw) 3280 { 3281 int err; 3282 u32 val; 3283 3284 /* Enable reading switch and PHY registers over the sideband queue */ 3285 #define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1) 3286 #define PF_SB_REM_DEV_CTL_PHY0 BIT(2) 3287 val = rd32(hw, PF_SB_REM_DEV_CTL); 3288 val |= (PF_SB_REM_DEV_CTL_SWITCH_READ | PF_SB_REM_DEV_CTL_PHY0); 3289 wr32(hw, PF_SB_REM_DEV_CTL, val); 3290 3291 /* Initialize the Clock Generation Unit */ 3292 err = ice_init_cgu_e82x(hw); 3293 if (err) 3294 return err; 3295 3296 /* Set window length for all the ports */ 3297 return ice_ptp_set_vernier_wl(hw); 3298 } 3299 3300 /** 3301 * ice_ptp_prep_phy_time_e82x - Prepare PHY port with initial time 3302 * @hw: pointer to the HW struct 3303 * @time: Time to initialize the PHY port clocks to 3304 * 3305 * Program the PHY port registers with a new initial time value. The port 3306 * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync 3307 * command. The time value is the upper 32 bits of the PHY timer, usually in 3308 * units of nominal nanoseconds. 3309 */ 3310 static int 3311 ice_ptp_prep_phy_time_e82x(struct ice_hw *hw, u32 time) 3312 { 3313 u64 phy_time; 3314 u8 port; 3315 int err; 3316 3317 /* The time represents the upper 32 bits of the PHY timer, so we need 3318 * to shift to account for this when programming. 3319 */ 3320 phy_time = (u64)time << 32; 3321 3322 for (port = 0; port < hw->ptp.num_lports; port++) { 3323 /* Tx case */ 3324 err = ice_write_64b_phy_reg_e82x(hw, port, 3325 P_REG_TX_TIMER_INC_PRE_L, 3326 phy_time); 3327 if (err) 3328 goto exit_err; 3329 3330 /* Rx case */ 3331 err = ice_write_64b_phy_reg_e82x(hw, port, 3332 P_REG_RX_TIMER_INC_PRE_L, 3333 phy_time); 3334 if (err) 3335 goto exit_err; 3336 } 3337 3338 return 0; 3339 3340 exit_err: 3341 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n", 3342 port, err); 3343 3344 return err; 3345 } 3346 3347 /** 3348 * ice_ptp_prep_port_adj_e82x - Prepare a single port for time adjust 3349 * @hw: pointer to HW struct 3350 * @port: Port number to be programmed 3351 * @time: time in cycles to adjust the port Tx and Rx clocks 3352 * 3353 * Program the port for an atomic adjustment by writing the Tx and Rx timer 3354 * registers. The atomic adjustment won't be completed until the driver issues 3355 * an ICE_PTP_ADJ_TIME command. 3356 * 3357 * Note that time is not in units of nanoseconds. It is in clock time 3358 * including the lower sub-nanosecond portion of the port timer. 3359 * 3360 * Negative adjustments are supported using 2s complement arithmetic. 3361 */ 3362 static int 3363 ice_ptp_prep_port_adj_e82x(struct ice_hw *hw, u8 port, s64 time) 3364 { 3365 u32 l_time, u_time; 3366 int err; 3367 3368 l_time = lower_32_bits(time); 3369 u_time = upper_32_bits(time); 3370 3371 /* Tx case */ 3372 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TIMER_INC_PRE_L, 3373 l_time); 3374 if (err) 3375 goto exit_err; 3376 3377 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TIMER_INC_PRE_U, 3378 u_time); 3379 if (err) 3380 goto exit_err; 3381 3382 /* Rx case */ 3383 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TIMER_INC_PRE_L, 3384 l_time); 3385 if (err) 3386 goto exit_err; 3387 3388 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TIMER_INC_PRE_U, 3389 u_time); 3390 if (err) 3391 goto exit_err; 3392 3393 return 0; 3394 3395 exit_err: 3396 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n", 3397 port, err); 3398 return err; 3399 } 3400 3401 /** 3402 * ice_ptp_prep_phy_adj_e82x - Prep PHY ports for a time adjustment 3403 * @hw: pointer to HW struct 3404 * @adj: adjustment in nanoseconds 3405 * 3406 * Prepare the PHY ports for an atomic time adjustment by programming the PHY 3407 * Tx and Rx port registers. The actual adjustment is completed by issuing an 3408 * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command. 3409 */ 3410 static int 3411 ice_ptp_prep_phy_adj_e82x(struct ice_hw *hw, s32 adj) 3412 { 3413 s64 cycles; 3414 u8 port; 3415 3416 /* The port clock supports adjustment of the sub-nanosecond portion of 3417 * the clock. We shift the provided adjustment in nanoseconds to 3418 * calculate the appropriate adjustment to program into the PHY ports. 3419 */ 3420 if (adj > 0) 3421 cycles = (s64)adj << 32; 3422 else 3423 cycles = -(((s64)-adj) << 32); 3424 3425 for (port = 0; port < hw->ptp.num_lports; port++) { 3426 int err; 3427 3428 err = ice_ptp_prep_port_adj_e82x(hw, port, cycles); 3429 if (err) 3430 return err; 3431 } 3432 3433 return 0; 3434 } 3435 3436 /** 3437 * ice_ptp_prep_phy_incval_e82x - Prepare PHY ports for time adjustment 3438 * @hw: pointer to HW struct 3439 * @incval: new increment value to prepare 3440 * 3441 * Prepare each of the PHY ports for a new increment value by programming the 3442 * port's TIMETUS registers. The new increment value will be updated after 3443 * issuing an ICE_PTP_INIT_INCVAL command. 3444 */ 3445 static int 3446 ice_ptp_prep_phy_incval_e82x(struct ice_hw *hw, u64 incval) 3447 { 3448 int err; 3449 u8 port; 3450 3451 for (port = 0; port < hw->ptp.num_lports; port++) { 3452 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L, 3453 incval); 3454 if (err) 3455 goto exit_err; 3456 } 3457 3458 return 0; 3459 3460 exit_err: 3461 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n", 3462 port, err); 3463 3464 return err; 3465 } 3466 3467 /** 3468 * ice_ptp_read_port_capture - Read a port's local time capture 3469 * @hw: pointer to HW struct 3470 * @port: Port number to read 3471 * @tx_ts: on return, the Tx port time capture 3472 * @rx_ts: on return, the Rx port time capture 3473 * 3474 * Read the port's Tx and Rx local time capture values. 3475 * 3476 * Note this has no equivalent for the E810 devices. 3477 */ 3478 static int 3479 ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts) 3480 { 3481 int err; 3482 3483 /* Tx case */ 3484 err = ice_read_64b_phy_reg_e82x(hw, port, P_REG_TX_CAPTURE_L, tx_ts); 3485 if (err) { 3486 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n", 3487 err); 3488 return err; 3489 } 3490 3491 ice_debug(hw, ICE_DBG_PTP, "tx_init = 0x%016llx\n", 3492 (unsigned long long)*tx_ts); 3493 3494 /* Rx case */ 3495 err = ice_read_64b_phy_reg_e82x(hw, port, P_REG_RX_CAPTURE_L, rx_ts); 3496 if (err) { 3497 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n", 3498 err); 3499 return err; 3500 } 3501 3502 ice_debug(hw, ICE_DBG_PTP, "rx_init = 0x%016llx\n", 3503 (unsigned long long)*rx_ts); 3504 3505 return 0; 3506 } 3507 3508 /** 3509 * ice_ptp_write_port_cmd_e82x - Prepare a single PHY port for a timer command 3510 * @hw: pointer to HW struct 3511 * @port: Port to which cmd has to be sent 3512 * @cmd: Command to be sent to the port 3513 * 3514 * Prepare the requested port for an upcoming timer sync command. 3515 * 3516 * Note there is no equivalent of this operation on E810, as that device 3517 * always handles all external PHYs internally. 3518 * 3519 * Return: 3520 * * %0 - success 3521 * * %other - failed to write to PHY 3522 */ 3523 static int ice_ptp_write_port_cmd_e82x(struct ice_hw *hw, u8 port, 3524 enum ice_ptp_tmr_cmd cmd) 3525 { 3526 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 3527 int err; 3528 3529 /* Tx case */ 3530 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TMR_CMD, val); 3531 if (err) { 3532 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n", 3533 err); 3534 return err; 3535 } 3536 3537 /* Rx case */ 3538 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TMR_CMD, 3539 val | TS_CMD_RX_TYPE); 3540 if (err) { 3541 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n", 3542 err); 3543 return err; 3544 } 3545 3546 return 0; 3547 } 3548 3549 /* E822 Vernier calibration functions 3550 * 3551 * The following functions are used as part of the vernier calibration of 3552 * a port. This calibration increases the precision of the timestamps on the 3553 * port. 3554 */ 3555 3556 /** 3557 * ice_phy_get_speed_and_fec_e82x - Get link speed and FEC based on serdes mode 3558 * @hw: pointer to HW struct 3559 * @port: the port to read from 3560 * @link_out: if non-NULL, holds link speed on success 3561 * @fec_out: if non-NULL, holds FEC algorithm on success 3562 * 3563 * Read the serdes data for the PHY port and extract the link speed and FEC 3564 * algorithm. 3565 */ 3566 static int 3567 ice_phy_get_speed_and_fec_e82x(struct ice_hw *hw, u8 port, 3568 enum ice_ptp_link_spd *link_out, 3569 enum ice_ptp_fec_mode *fec_out) 3570 { 3571 enum ice_ptp_link_spd link; 3572 enum ice_ptp_fec_mode fec; 3573 u32 serdes; 3574 int err; 3575 3576 err = ice_read_phy_reg_e82x(hw, port, P_REG_LINK_SPEED, &serdes); 3577 if (err) { 3578 ice_debug(hw, ICE_DBG_PTP, "Failed to read serdes info\n"); 3579 return err; 3580 } 3581 3582 /* Determine the FEC algorithm */ 3583 fec = (enum ice_ptp_fec_mode)P_REG_LINK_SPEED_FEC_MODE(serdes); 3584 3585 serdes &= P_REG_LINK_SPEED_SERDES_M; 3586 3587 /* Determine the link speed */ 3588 if (fec == ICE_PTP_FEC_MODE_RS_FEC) { 3589 switch (serdes) { 3590 case ICE_PTP_SERDES_25G: 3591 link = ICE_PTP_LNK_SPD_25G_RS; 3592 break; 3593 case ICE_PTP_SERDES_50G: 3594 link = ICE_PTP_LNK_SPD_50G_RS; 3595 break; 3596 case ICE_PTP_SERDES_100G: 3597 link = ICE_PTP_LNK_SPD_100G_RS; 3598 break; 3599 default: 3600 return -EIO; 3601 } 3602 } else { 3603 switch (serdes) { 3604 case ICE_PTP_SERDES_1G: 3605 link = ICE_PTP_LNK_SPD_1G; 3606 break; 3607 case ICE_PTP_SERDES_10G: 3608 link = ICE_PTP_LNK_SPD_10G; 3609 break; 3610 case ICE_PTP_SERDES_25G: 3611 link = ICE_PTP_LNK_SPD_25G; 3612 break; 3613 case ICE_PTP_SERDES_40G: 3614 link = ICE_PTP_LNK_SPD_40G; 3615 break; 3616 case ICE_PTP_SERDES_50G: 3617 link = ICE_PTP_LNK_SPD_50G; 3618 break; 3619 default: 3620 return -EIO; 3621 } 3622 } 3623 3624 if (link_out) 3625 *link_out = link; 3626 if (fec_out) 3627 *fec_out = fec; 3628 3629 return 0; 3630 } 3631 3632 /** 3633 * ice_phy_cfg_lane_e82x - Configure PHY quad for single/multi-lane timestamp 3634 * @hw: pointer to HW struct 3635 * @port: to configure the quad for 3636 */ 3637 static void ice_phy_cfg_lane_e82x(struct ice_hw *hw, u8 port) 3638 { 3639 enum ice_ptp_link_spd link_spd; 3640 int err; 3641 u32 val; 3642 u8 quad; 3643 3644 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, NULL); 3645 if (err) { 3646 ice_debug(hw, ICE_DBG_PTP, "Failed to get PHY link speed, err %d\n", 3647 err); 3648 return; 3649 } 3650 3651 quad = ICE_GET_QUAD_NUM(port); 3652 3653 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val); 3654 if (err) { 3655 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEM_GLB_CFG, err %d\n", 3656 err); 3657 return; 3658 } 3659 3660 if (link_spd >= ICE_PTP_LNK_SPD_40G) 3661 val &= ~Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M; 3662 else 3663 val |= Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M; 3664 3665 err = ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val); 3666 if (err) { 3667 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_MEM_GBL_CFG, err %d\n", 3668 err); 3669 return; 3670 } 3671 } 3672 3673 /** 3674 * ice_phy_cfg_uix_e82x - Configure Serdes UI to TU conversion for E822 3675 * @hw: pointer to the HW structure 3676 * @port: the port to configure 3677 * 3678 * Program the conversion ration of Serdes clock "unit intervals" (UIs) to PHC 3679 * hardware clock time units (TUs). That is, determine the number of TUs per 3680 * serdes unit interval, and program the UIX registers with this conversion. 3681 * 3682 * This conversion is used as part of the calibration process when determining 3683 * the additional error of a timestamp vs the real time of transmission or 3684 * receipt of the packet. 3685 * 3686 * Hardware uses the number of TUs per 66 UIs, written to the UIX registers 3687 * for the two main serdes clock rates, 10G/40G and 25G/100G serdes clocks. 3688 * 3689 * To calculate the conversion ratio, we use the following facts: 3690 * 3691 * a) the clock frequency in Hz (cycles per second) 3692 * b) the number of TUs per cycle (the increment value of the clock) 3693 * c) 1 second per 1 billion nanoseconds 3694 * d) the duration of 66 UIs in nanoseconds 3695 * 3696 * Given these facts, we can use the following table to work out what ratios 3697 * to multiply in order to get the number of TUs per 66 UIs: 3698 * 3699 * cycles | 1 second | incval (TUs) | nanoseconds 3700 * -------+--------------+--------------+------------- 3701 * second | 1 billion ns | cycle | 66 UIs 3702 * 3703 * To perform the multiplication using integers without too much loss of 3704 * precision, we can take use the following equation: 3705 * 3706 * (freq * incval * 6600 LINE_UI ) / ( 100 * 1 billion) 3707 * 3708 * We scale up to using 6600 UI instead of 66 in order to avoid fractional 3709 * nanosecond UIs (66 UI at 10G/40G is 6.4 ns) 3710 * 3711 * The increment value has a maximum expected range of about 34 bits, while 3712 * the frequency value is about 29 bits. Multiplying these values shouldn't 3713 * overflow the 64 bits. However, we must then further multiply them again by 3714 * the Serdes unit interval duration. To avoid overflow here, we split the 3715 * overall divide by 1e11 into a divide by 256 (shift down by 8 bits) and 3716 * a divide by 390,625,000. This does lose some precision, but avoids 3717 * miscalculation due to arithmetic overflow. 3718 */ 3719 static int ice_phy_cfg_uix_e82x(struct ice_hw *hw, u8 port) 3720 { 3721 u64 cur_freq, clk_incval, tu_per_sec, uix; 3722 int err; 3723 3724 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3725 clk_incval = ice_ptp_read_src_incval(hw); 3726 3727 /* Calculate TUs per second divided by 256 */ 3728 tu_per_sec = (cur_freq * clk_incval) >> 8; 3729 3730 #define LINE_UI_10G_40G 640 /* 6600 UIs is 640 nanoseconds at 10Gb/40Gb */ 3731 #define LINE_UI_25G_100G 256 /* 6600 UIs is 256 nanoseconds at 25Gb/100Gb */ 3732 3733 /* Program the 10Gb/40Gb conversion ratio */ 3734 uix = div_u64(tu_per_sec * LINE_UI_10G_40G, 390625000); 3735 3736 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_UIX66_10G_40G_L, 3737 uix); 3738 if (err) { 3739 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_10G_40G, err %d\n", 3740 err); 3741 return err; 3742 } 3743 3744 /* Program the 25Gb/100Gb conversion ratio */ 3745 uix = div_u64(tu_per_sec * LINE_UI_25G_100G, 390625000); 3746 3747 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_UIX66_25G_100G_L, 3748 uix); 3749 if (err) { 3750 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_25G_100G, err %d\n", 3751 err); 3752 return err; 3753 } 3754 3755 return 0; 3756 } 3757 3758 /** 3759 * ice_phy_cfg_parpcs_e82x - Configure TUs per PAR/PCS clock cycle 3760 * @hw: pointer to the HW struct 3761 * @port: port to configure 3762 * 3763 * Configure the number of TUs for the PAR and PCS clocks used as part of the 3764 * timestamp calibration process. This depends on the link speed, as the PHY 3765 * uses different markers depending on the speed. 3766 * 3767 * 1Gb/10Gb/25Gb: 3768 * - Tx/Rx PAR/PCS markers 3769 * 3770 * 25Gb RS: 3771 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers 3772 * 3773 * 40Gb/50Gb: 3774 * - Tx/Rx PAR/PCS markers 3775 * - Rx Deskew PAR/PCS markers 3776 * 3777 * 50G RS and 100GB RS: 3778 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers 3779 * - Rx Deskew PAR/PCS markers 3780 * - Tx PAR/PCS markers 3781 * 3782 * To calculate the conversion, we use the PHC clock frequency (cycles per 3783 * second), the increment value (TUs per cycle), and the related PHY clock 3784 * frequency to calculate the TUs per unit of the PHY link clock. The 3785 * following table shows how the units convert: 3786 * 3787 * cycles | TUs | second 3788 * -------+-------+-------- 3789 * second | cycle | cycles 3790 * 3791 * For each conversion register, look up the appropriate frequency from the 3792 * e822 PAR/PCS table and calculate the TUs per unit of that clock. Program 3793 * this to the appropriate register, preparing hardware to perform timestamp 3794 * calibration to calculate the total Tx or Rx offset to adjust the timestamp 3795 * in order to calibrate for the internal PHY delays. 3796 * 3797 * Note that the increment value ranges up to ~34 bits, and the clock 3798 * frequency is ~29 bits, so multiplying them together should fit within the 3799 * 64 bit arithmetic. 3800 */ 3801 static int ice_phy_cfg_parpcs_e82x(struct ice_hw *hw, u8 port) 3802 { 3803 u64 cur_freq, clk_incval, tu_per_sec, phy_tus; 3804 enum ice_ptp_link_spd link_spd; 3805 enum ice_ptp_fec_mode fec_mode; 3806 int err; 3807 3808 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode); 3809 if (err) 3810 return err; 3811 3812 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3813 clk_incval = ice_ptp_read_src_incval(hw); 3814 3815 /* Calculate TUs per cycle of the PHC clock */ 3816 tu_per_sec = cur_freq * clk_incval; 3817 3818 /* For each PHY conversion register, look up the appropriate link 3819 * speed frequency and determine the TUs per that clock's cycle time. 3820 * Split this into a high and low value and then program the 3821 * appropriate register. If that link speed does not use the 3822 * associated register, write zeros to clear it instead. 3823 */ 3824 3825 /* P_REG_PAR_TX_TUS */ 3826 if (e822_vernier[link_spd].tx_par_clk) 3827 phy_tus = div_u64(tu_per_sec, 3828 e822_vernier[link_spd].tx_par_clk); 3829 else 3830 phy_tus = 0; 3831 3832 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PAR_TX_TUS_L, 3833 phy_tus); 3834 if (err) 3835 return err; 3836 3837 /* P_REG_PAR_RX_TUS */ 3838 if (e822_vernier[link_spd].rx_par_clk) 3839 phy_tus = div_u64(tu_per_sec, 3840 e822_vernier[link_spd].rx_par_clk); 3841 else 3842 phy_tus = 0; 3843 3844 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PAR_RX_TUS_L, 3845 phy_tus); 3846 if (err) 3847 return err; 3848 3849 /* P_REG_PCS_TX_TUS */ 3850 if (e822_vernier[link_spd].tx_pcs_clk) 3851 phy_tus = div_u64(tu_per_sec, 3852 e822_vernier[link_spd].tx_pcs_clk); 3853 else 3854 phy_tus = 0; 3855 3856 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PCS_TX_TUS_L, 3857 phy_tus); 3858 if (err) 3859 return err; 3860 3861 /* P_REG_PCS_RX_TUS */ 3862 if (e822_vernier[link_spd].rx_pcs_clk) 3863 phy_tus = div_u64(tu_per_sec, 3864 e822_vernier[link_spd].rx_pcs_clk); 3865 else 3866 phy_tus = 0; 3867 3868 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PCS_RX_TUS_L, 3869 phy_tus); 3870 if (err) 3871 return err; 3872 3873 /* P_REG_DESK_PAR_TX_TUS */ 3874 if (e822_vernier[link_spd].tx_desk_rsgb_par) 3875 phy_tus = div_u64(tu_per_sec, 3876 e822_vernier[link_spd].tx_desk_rsgb_par); 3877 else 3878 phy_tus = 0; 3879 3880 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PAR_TX_TUS_L, 3881 phy_tus); 3882 if (err) 3883 return err; 3884 3885 /* P_REG_DESK_PAR_RX_TUS */ 3886 if (e822_vernier[link_spd].rx_desk_rsgb_par) 3887 phy_tus = div_u64(tu_per_sec, 3888 e822_vernier[link_spd].rx_desk_rsgb_par); 3889 else 3890 phy_tus = 0; 3891 3892 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PAR_RX_TUS_L, 3893 phy_tus); 3894 if (err) 3895 return err; 3896 3897 /* P_REG_DESK_PCS_TX_TUS */ 3898 if (e822_vernier[link_spd].tx_desk_rsgb_pcs) 3899 phy_tus = div_u64(tu_per_sec, 3900 e822_vernier[link_spd].tx_desk_rsgb_pcs); 3901 else 3902 phy_tus = 0; 3903 3904 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PCS_TX_TUS_L, 3905 phy_tus); 3906 if (err) 3907 return err; 3908 3909 /* P_REG_DESK_PCS_RX_TUS */ 3910 if (e822_vernier[link_spd].rx_desk_rsgb_pcs) 3911 phy_tus = div_u64(tu_per_sec, 3912 e822_vernier[link_spd].rx_desk_rsgb_pcs); 3913 else 3914 phy_tus = 0; 3915 3916 return ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PCS_RX_TUS_L, 3917 phy_tus); 3918 } 3919 3920 /** 3921 * ice_calc_fixed_tx_offset_e82x - Calculated Fixed Tx offset for a port 3922 * @hw: pointer to the HW struct 3923 * @link_spd: the Link speed to calculate for 3924 * 3925 * Calculate the fixed offset due to known static latency data. 3926 */ 3927 static u64 3928 ice_calc_fixed_tx_offset_e82x(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) 3929 { 3930 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset; 3931 3932 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3933 clk_incval = ice_ptp_read_src_incval(hw); 3934 3935 /* Calculate TUs per second */ 3936 tu_per_sec = cur_freq * clk_incval; 3937 3938 /* Calculate number of TUs to add for the fixed Tx latency. Since the 3939 * latency measurement is in 1/100th of a nanosecond, we need to 3940 * multiply by tu_per_sec and then divide by 1e11. This calculation 3941 * overflows 64 bit integer arithmetic, so break it up into two 3942 * divisions by 1e4 first then by 1e7. 3943 */ 3944 fixed_offset = div_u64(tu_per_sec, 10000); 3945 fixed_offset *= e822_vernier[link_spd].tx_fixed_delay; 3946 fixed_offset = div_u64(fixed_offset, 10000000); 3947 3948 return fixed_offset; 3949 } 3950 3951 /** 3952 * ice_phy_cfg_tx_offset_e82x - Configure total Tx timestamp offset 3953 * @hw: pointer to the HW struct 3954 * @port: the PHY port to configure 3955 * 3956 * Program the P_REG_TOTAL_TX_OFFSET register with the total number of TUs to 3957 * adjust Tx timestamps by. This is calculated by combining some known static 3958 * latency along with the Vernier offset computations done by hardware. 3959 * 3960 * This function will not return successfully until the Tx offset calculations 3961 * have been completed, which requires waiting until at least one packet has 3962 * been transmitted by the device. It is safe to call this function 3963 * periodically until calibration succeeds, as it will only program the offset 3964 * once. 3965 * 3966 * To avoid overflow, when calculating the offset based on the known static 3967 * latency values, we use measurements in 1/100th of a nanosecond, and divide 3968 * the TUs per second up front. This avoids overflow while allowing 3969 * calculation of the adjustment using integer arithmetic. 3970 * 3971 * Returns zero on success, -EBUSY if the hardware vernier offset 3972 * calibration has not completed, or another error code on failure. 3973 */ 3974 int ice_phy_cfg_tx_offset_e82x(struct ice_hw *hw, u8 port) 3975 { 3976 enum ice_ptp_link_spd link_spd; 3977 enum ice_ptp_fec_mode fec_mode; 3978 u64 total_offset, val; 3979 int err; 3980 u32 reg; 3981 3982 /* Nothing to do if we've already programmed the offset */ 3983 err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_OR, ®); 3984 if (err) { 3985 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OR for port %u, err %d\n", 3986 port, err); 3987 return err; 3988 } 3989 3990 if (reg) 3991 return 0; 3992 3993 err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_OV_STATUS, ®); 3994 if (err) { 3995 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OV_STATUS for port %u, err %d\n", 3996 port, err); 3997 return err; 3998 } 3999 4000 if (!(reg & P_REG_TX_OV_STATUS_OV_M)) 4001 return -EBUSY; 4002 4003 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode); 4004 if (err) 4005 return err; 4006 4007 total_offset = ice_calc_fixed_tx_offset_e82x(hw, link_spd); 4008 4009 /* Read the first Vernier offset from the PHY register and add it to 4010 * the total offset. 4011 */ 4012 if (link_spd == ICE_PTP_LNK_SPD_1G || 4013 link_spd == ICE_PTP_LNK_SPD_10G || 4014 link_spd == ICE_PTP_LNK_SPD_25G || 4015 link_spd == ICE_PTP_LNK_SPD_25G_RS || 4016 link_spd == ICE_PTP_LNK_SPD_40G || 4017 link_spd == ICE_PTP_LNK_SPD_50G) { 4018 err = ice_read_64b_phy_reg_e82x(hw, port, 4019 P_REG_PAR_PCS_TX_OFFSET_L, 4020 &val); 4021 if (err) 4022 return err; 4023 4024 total_offset += val; 4025 } 4026 4027 /* For Tx, we only need to use the second Vernier offset for 4028 * multi-lane link speeds with RS-FEC. The lanes will always be 4029 * aligned. 4030 */ 4031 if (link_spd == ICE_PTP_LNK_SPD_50G_RS || 4032 link_spd == ICE_PTP_LNK_SPD_100G_RS) { 4033 err = ice_read_64b_phy_reg_e82x(hw, port, 4034 P_REG_PAR_TX_TIME_L, 4035 &val); 4036 if (err) 4037 return err; 4038 4039 total_offset += val; 4040 } 4041 4042 /* Now that the total offset has been calculated, program it to the 4043 * PHY and indicate that the Tx offset is ready. After this, 4044 * timestamps will be enabled. 4045 */ 4046 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_TOTAL_TX_OFFSET_L, 4047 total_offset); 4048 if (err) 4049 return err; 4050 4051 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 1); 4052 if (err) 4053 return err; 4054 4055 dev_info(ice_hw_to_dev(hw), "Port=%d Tx vernier offset calibration complete\n", 4056 port); 4057 4058 return 0; 4059 } 4060 4061 /** 4062 * ice_phy_calc_pmd_adj_e82x - Calculate PMD adjustment for Rx 4063 * @hw: pointer to the HW struct 4064 * @port: the PHY port to adjust for 4065 * @link_spd: the current link speed of the PHY 4066 * @fec_mode: the current FEC mode of the PHY 4067 * @pmd_adj: on return, the amount to adjust the Rx total offset by 4068 * 4069 * Calculates the adjustment to Rx timestamps due to PMD alignment in the PHY. 4070 * This varies by link speed and FEC mode. The value calculated accounts for 4071 * various delays caused when receiving a packet. 4072 */ 4073 static int 4074 ice_phy_calc_pmd_adj_e82x(struct ice_hw *hw, u8 port, 4075 enum ice_ptp_link_spd link_spd, 4076 enum ice_ptp_fec_mode fec_mode, u64 *pmd_adj) 4077 { 4078 u64 cur_freq, clk_incval, tu_per_sec, mult, adj; 4079 u8 pmd_align; 4080 u32 val; 4081 int err; 4082 4083 err = ice_read_phy_reg_e82x(hw, port, P_REG_PMD_ALIGNMENT, &val); 4084 if (err) { 4085 ice_debug(hw, ICE_DBG_PTP, "Failed to read PMD alignment, err %d\n", 4086 err); 4087 return err; 4088 } 4089 4090 pmd_align = (u8)val; 4091 4092 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 4093 clk_incval = ice_ptp_read_src_incval(hw); 4094 4095 /* Calculate TUs per second */ 4096 tu_per_sec = cur_freq * clk_incval; 4097 4098 /* The PMD alignment adjustment measurement depends on the link speed, 4099 * and whether FEC is enabled. For each link speed, the alignment 4100 * adjustment is calculated by dividing a value by the length of 4101 * a Time Unit in nanoseconds. 4102 * 4103 * 1G: align == 4 ? 10 * 0.8 : (align + 6 % 10) * 0.8 4104 * 10G: align == 65 ? 0 : (align * 0.1 * 32/33) 4105 * 10G w/FEC: align * 0.1 * 32/33 4106 * 25G: align == 65 ? 0 : (align * 0.4 * 32/33) 4107 * 25G w/FEC: align * 0.4 * 32/33 4108 * 40G: align == 65 ? 0 : (align * 0.1 * 32/33) 4109 * 40G w/FEC: align * 0.1 * 32/33 4110 * 50G: align == 65 ? 0 : (align * 0.4 * 32/33) 4111 * 50G w/FEC: align * 0.8 * 32/33 4112 * 4113 * For RS-FEC, if align is < 17 then we must also add 1.6 * 32/33. 4114 * 4115 * To allow for calculating this value using integer arithmetic, we 4116 * instead start with the number of TUs per second, (inverse of the 4117 * length of a Time Unit in nanoseconds), multiply by a value based 4118 * on the PMD alignment register, and then divide by the right value 4119 * calculated based on the table above. To avoid integer overflow this 4120 * division is broken up into a step of dividing by 125 first. 4121 */ 4122 if (link_spd == ICE_PTP_LNK_SPD_1G) { 4123 if (pmd_align == 4) 4124 mult = 10; 4125 else 4126 mult = (pmd_align + 6) % 10; 4127 } else if (link_spd == ICE_PTP_LNK_SPD_10G || 4128 link_spd == ICE_PTP_LNK_SPD_25G || 4129 link_spd == ICE_PTP_LNK_SPD_40G || 4130 link_spd == ICE_PTP_LNK_SPD_50G) { 4131 /* If Clause 74 FEC, always calculate PMD adjust */ 4132 if (pmd_align != 65 || fec_mode == ICE_PTP_FEC_MODE_CLAUSE74) 4133 mult = pmd_align; 4134 else 4135 mult = 0; 4136 } else if (link_spd == ICE_PTP_LNK_SPD_25G_RS || 4137 link_spd == ICE_PTP_LNK_SPD_50G_RS || 4138 link_spd == ICE_PTP_LNK_SPD_100G_RS) { 4139 if (pmd_align < 17) 4140 mult = pmd_align + 40; 4141 else 4142 mult = pmd_align; 4143 } else { 4144 ice_debug(hw, ICE_DBG_PTP, "Unknown link speed %d, skipping PMD adjustment\n", 4145 link_spd); 4146 mult = 0; 4147 } 4148 4149 /* In some cases, there's no need to adjust for the PMD alignment */ 4150 if (!mult) { 4151 *pmd_adj = 0; 4152 return 0; 4153 } 4154 4155 /* Calculate the adjustment by multiplying TUs per second by the 4156 * appropriate multiplier and divisor. To avoid overflow, we first 4157 * divide by 125, and then handle remaining divisor based on the link 4158 * speed pmd_adj_divisor value. 4159 */ 4160 adj = div_u64(tu_per_sec, 125); 4161 adj *= mult; 4162 adj = div_u64(adj, e822_vernier[link_spd].pmd_adj_divisor); 4163 4164 /* Finally, for 25G-RS and 50G-RS, a further adjustment for the Rx 4165 * cycle count is necessary. 4166 */ 4167 if (link_spd == ICE_PTP_LNK_SPD_25G_RS) { 4168 u64 cycle_adj; 4169 u8 rx_cycle; 4170 4171 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_40_TO_160_CNT, 4172 &val); 4173 if (err) { 4174 ice_debug(hw, ICE_DBG_PTP, "Failed to read 25G-RS Rx cycle count, err %d\n", 4175 err); 4176 return err; 4177 } 4178 4179 rx_cycle = val & P_REG_RX_40_TO_160_CNT_RXCYC_M; 4180 if (rx_cycle) { 4181 mult = (4 - rx_cycle) * 40; 4182 4183 cycle_adj = div_u64(tu_per_sec, 125); 4184 cycle_adj *= mult; 4185 cycle_adj = div_u64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor); 4186 4187 adj += cycle_adj; 4188 } 4189 } else if (link_spd == ICE_PTP_LNK_SPD_50G_RS) { 4190 u64 cycle_adj; 4191 u8 rx_cycle; 4192 4193 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_80_TO_160_CNT, 4194 &val); 4195 if (err) { 4196 ice_debug(hw, ICE_DBG_PTP, "Failed to read 50G-RS Rx cycle count, err %d\n", 4197 err); 4198 return err; 4199 } 4200 4201 rx_cycle = val & P_REG_RX_80_TO_160_CNT_RXCYC_M; 4202 if (rx_cycle) { 4203 mult = rx_cycle * 40; 4204 4205 cycle_adj = div_u64(tu_per_sec, 125); 4206 cycle_adj *= mult; 4207 cycle_adj = div_u64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor); 4208 4209 adj += cycle_adj; 4210 } 4211 } 4212 4213 /* Return the calculated adjustment */ 4214 *pmd_adj = adj; 4215 4216 return 0; 4217 } 4218 4219 /** 4220 * ice_calc_fixed_rx_offset_e82x - Calculated the fixed Rx offset for a port 4221 * @hw: pointer to HW struct 4222 * @link_spd: The Link speed to calculate for 4223 * 4224 * Determine the fixed Rx latency for a given link speed. 4225 */ 4226 static u64 4227 ice_calc_fixed_rx_offset_e82x(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) 4228 { 4229 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset; 4230 4231 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 4232 clk_incval = ice_ptp_read_src_incval(hw); 4233 4234 /* Calculate TUs per second */ 4235 tu_per_sec = cur_freq * clk_incval; 4236 4237 /* Calculate number of TUs to add for the fixed Rx latency. Since the 4238 * latency measurement is in 1/100th of a nanosecond, we need to 4239 * multiply by tu_per_sec and then divide by 1e11. This calculation 4240 * overflows 64 bit integer arithmetic, so break it up into two 4241 * divisions by 1e4 first then by 1e7. 4242 */ 4243 fixed_offset = div_u64(tu_per_sec, 10000); 4244 fixed_offset *= e822_vernier[link_spd].rx_fixed_delay; 4245 fixed_offset = div_u64(fixed_offset, 10000000); 4246 4247 return fixed_offset; 4248 } 4249 4250 /** 4251 * ice_phy_cfg_rx_offset_e82x - Configure total Rx timestamp offset 4252 * @hw: pointer to the HW struct 4253 * @port: the PHY port to configure 4254 * 4255 * Program the P_REG_TOTAL_RX_OFFSET register with the number of Time Units to 4256 * adjust Rx timestamps by. This combines calculations from the Vernier offset 4257 * measurements taken in hardware with some data about known fixed delay as 4258 * well as adjusting for multi-lane alignment delay. 4259 * 4260 * This function will not return successfully until the Rx offset calculations 4261 * have been completed, which requires waiting until at least one packet has 4262 * been received by the device. It is safe to call this function periodically 4263 * until calibration succeeds, as it will only program the offset once. 4264 * 4265 * This function must be called only after the offset registers are valid, 4266 * i.e. after the Vernier calibration wait has passed, to ensure that the PHY 4267 * has measured the offset. 4268 * 4269 * To avoid overflow, when calculating the offset based on the known static 4270 * latency values, we use measurements in 1/100th of a nanosecond, and divide 4271 * the TUs per second up front. This avoids overflow while allowing 4272 * calculation of the adjustment using integer arithmetic. 4273 * 4274 * Returns zero on success, -EBUSY if the hardware vernier offset 4275 * calibration has not completed, or another error code on failure. 4276 */ 4277 int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port) 4278 { 4279 enum ice_ptp_link_spd link_spd; 4280 enum ice_ptp_fec_mode fec_mode; 4281 u64 total_offset, pmd, val; 4282 int err; 4283 u32 reg; 4284 4285 /* Nothing to do if we've already programmed the offset */ 4286 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_OR, ®); 4287 if (err) { 4288 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OR for port %u, err %d\n", 4289 port, err); 4290 return err; 4291 } 4292 4293 if (reg) 4294 return 0; 4295 4296 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_OV_STATUS, ®); 4297 if (err) { 4298 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OV_STATUS for port %u, err %d\n", 4299 port, err); 4300 return err; 4301 } 4302 4303 if (!(reg & P_REG_RX_OV_STATUS_OV_M)) 4304 return -EBUSY; 4305 4306 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode); 4307 if (err) 4308 return err; 4309 4310 total_offset = ice_calc_fixed_rx_offset_e82x(hw, link_spd); 4311 4312 /* Read the first Vernier offset from the PHY register and add it to 4313 * the total offset. 4314 */ 4315 err = ice_read_64b_phy_reg_e82x(hw, port, 4316 P_REG_PAR_PCS_RX_OFFSET_L, 4317 &val); 4318 if (err) 4319 return err; 4320 4321 total_offset += val; 4322 4323 /* For Rx, all multi-lane link speeds include a second Vernier 4324 * calibration, because the lanes might not be aligned. 4325 */ 4326 if (link_spd == ICE_PTP_LNK_SPD_40G || 4327 link_spd == ICE_PTP_LNK_SPD_50G || 4328 link_spd == ICE_PTP_LNK_SPD_50G_RS || 4329 link_spd == ICE_PTP_LNK_SPD_100G_RS) { 4330 err = ice_read_64b_phy_reg_e82x(hw, port, 4331 P_REG_PAR_RX_TIME_L, 4332 &val); 4333 if (err) 4334 return err; 4335 4336 total_offset += val; 4337 } 4338 4339 /* In addition, Rx must account for the PMD alignment */ 4340 err = ice_phy_calc_pmd_adj_e82x(hw, port, link_spd, fec_mode, &pmd); 4341 if (err) 4342 return err; 4343 4344 /* For RS-FEC, this adjustment adds delay, but for other modes, it 4345 * subtracts delay. 4346 */ 4347 if (fec_mode == ICE_PTP_FEC_MODE_RS_FEC) 4348 total_offset += pmd; 4349 else 4350 total_offset -= pmd; 4351 4352 /* Now that the total offset has been calculated, program it to the 4353 * PHY and indicate that the Rx offset is ready. After this, 4354 * timestamps will be enabled. 4355 */ 4356 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_TOTAL_RX_OFFSET_L, 4357 total_offset); 4358 if (err) 4359 return err; 4360 4361 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 1); 4362 if (err) 4363 return err; 4364 4365 dev_info(ice_hw_to_dev(hw), "Port=%d Rx vernier offset calibration complete\n", 4366 port); 4367 4368 return 0; 4369 } 4370 4371 /** 4372 * ice_ptp_clear_phy_offset_ready_e82x - Clear PHY TX_/RX_OFFSET_READY registers 4373 * @hw: pointer to the HW struct 4374 * 4375 * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted 4376 * and received timestamps as invalid. 4377 * 4378 * Return: 0 on success, other error codes when failed to write to PHY 4379 */ 4380 int ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw *hw) 4381 { 4382 u8 port; 4383 4384 for (port = 0; port < hw->ptp.num_lports; port++) { 4385 int err; 4386 4387 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0); 4388 if (err) { 4389 dev_warn(ice_hw_to_dev(hw), 4390 "Failed to clear PHY TX_OFFSET_READY register\n"); 4391 return err; 4392 } 4393 4394 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0); 4395 if (err) { 4396 dev_warn(ice_hw_to_dev(hw), 4397 "Failed to clear PHY RX_OFFSET_READY register\n"); 4398 return err; 4399 } 4400 } 4401 4402 return 0; 4403 } 4404 4405 /** 4406 * ice_read_phy_and_phc_time_e82x - Simultaneously capture PHC and PHY time 4407 * @hw: pointer to the HW struct 4408 * @port: the PHY port to read 4409 * @phy_time: on return, the 64bit PHY timer value 4410 * @phc_time: on return, the lower 64bits of PHC time 4411 * 4412 * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY 4413 * and PHC timer values. 4414 */ 4415 static int 4416 ice_read_phy_and_phc_time_e82x(struct ice_hw *hw, u8 port, u64 *phy_time, 4417 u64 *phc_time) 4418 { 4419 u64 tx_time, rx_time; 4420 u32 zo, lo; 4421 u8 tmr_idx; 4422 int err; 4423 4424 tmr_idx = ice_get_ptp_src_clock_index(hw); 4425 4426 /* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */ 4427 ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME); 4428 4429 /* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */ 4430 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME); 4431 if (err) 4432 return err; 4433 4434 /* Issue the sync to start the ICE_PTP_READ_TIME capture */ 4435 ice_ptp_exec_tmr_cmd(hw); 4436 4437 /* Read the captured PHC time from the shadow time registers */ 4438 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx)); 4439 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx)); 4440 *phc_time = (u64)lo << 32 | zo; 4441 4442 /* Read the captured PHY time from the PHY shadow registers */ 4443 err = ice_ptp_read_port_capture(hw, port, &tx_time, &rx_time); 4444 if (err) 4445 return err; 4446 4447 /* If the PHY Tx and Rx timers don't match, log a warning message. 4448 * Note that this should not happen in normal circumstances since the 4449 * driver always programs them together. 4450 */ 4451 if (tx_time != rx_time) 4452 dev_warn(ice_hw_to_dev(hw), 4453 "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n", 4454 port, (unsigned long long)tx_time, 4455 (unsigned long long)rx_time); 4456 4457 *phy_time = tx_time; 4458 4459 return 0; 4460 } 4461 4462 /** 4463 * ice_sync_phy_timer_e82x - Synchronize the PHY timer with PHC timer 4464 * @hw: pointer to the HW struct 4465 * @port: the PHY port to synchronize 4466 * 4467 * Perform an adjustment to ensure that the PHY and PHC timers are in sync. 4468 * This is done by issuing a ICE_PTP_READ_TIME command which triggers a 4469 * simultaneous read of the PHY timer and PHC timer. Then we use the 4470 * difference to calculate an appropriate 2s complement addition to add 4471 * to the PHY timer in order to ensure it reads the same value as the 4472 * primary PHC timer. 4473 */ 4474 static int ice_sync_phy_timer_e82x(struct ice_hw *hw, u8 port) 4475 { 4476 u64 phc_time, phy_time, difference; 4477 int err; 4478 4479 if (!ice_ptp_lock(hw)) { 4480 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n"); 4481 return -EBUSY; 4482 } 4483 4484 err = ice_read_phy_and_phc_time_e82x(hw, port, &phy_time, &phc_time); 4485 if (err) 4486 goto err_unlock; 4487 4488 /* Calculate the amount required to add to the port time in order for 4489 * it to match the PHC time. 4490 * 4491 * Note that the port adjustment is done using 2s complement 4492 * arithmetic. This is convenient since it means that we can simply 4493 * calculate the difference between the PHC time and the port time, 4494 * and it will be interpreted correctly. 4495 */ 4496 difference = phc_time - phy_time; 4497 4498 err = ice_ptp_prep_port_adj_e82x(hw, port, (s64)difference); 4499 if (err) 4500 goto err_unlock; 4501 4502 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME); 4503 if (err) 4504 goto err_unlock; 4505 4506 /* Do not perform any action on the main timer */ 4507 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 4508 4509 /* Issue the sync to activate the time adjustment */ 4510 ice_ptp_exec_tmr_cmd(hw); 4511 4512 /* Re-capture the timer values to flush the command registers and 4513 * verify that the time was properly adjusted. 4514 */ 4515 err = ice_read_phy_and_phc_time_e82x(hw, port, &phy_time, &phc_time); 4516 if (err) 4517 goto err_unlock; 4518 4519 dev_info(ice_hw_to_dev(hw), 4520 "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n", 4521 port, (unsigned long long)phy_time, 4522 (unsigned long long)phc_time); 4523 4524 ice_ptp_unlock(hw); 4525 4526 return 0; 4527 4528 err_unlock: 4529 ice_ptp_unlock(hw); 4530 return err; 4531 } 4532 4533 /** 4534 * ice_stop_phy_timer_e82x - Stop the PHY clock timer 4535 * @hw: pointer to the HW struct 4536 * @port: the PHY port to stop 4537 * @soft_reset: if true, hold the SOFT_RESET bit of P_REG_PS 4538 * 4539 * Stop the clock of a PHY port. This must be done as part of the flow to 4540 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 4541 * initialized or when link speed changes. 4542 */ 4543 int 4544 ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset) 4545 { 4546 int err; 4547 u32 val; 4548 4549 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0); 4550 if (err) 4551 return err; 4552 4553 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0); 4554 if (err) 4555 return err; 4556 4557 err = ice_read_phy_reg_e82x(hw, port, P_REG_PS, &val); 4558 if (err) 4559 return err; 4560 4561 val &= ~P_REG_PS_START_M; 4562 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4563 if (err) 4564 return err; 4565 4566 val &= ~P_REG_PS_ENA_CLK_M; 4567 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4568 if (err) 4569 return err; 4570 4571 if (soft_reset) { 4572 val |= P_REG_PS_SFT_RESET_M; 4573 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4574 if (err) 4575 return err; 4576 } 4577 4578 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port); 4579 4580 return 0; 4581 } 4582 4583 /** 4584 * ice_start_phy_timer_e82x - Start the PHY clock timer 4585 * @hw: pointer to the HW struct 4586 * @port: the PHY port to start 4587 * 4588 * Start the clock of a PHY port. This must be done as part of the flow to 4589 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 4590 * initialized or when link speed changes. 4591 * 4592 * Hardware will take Vernier measurements on Tx or Rx of packets. 4593 */ 4594 int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port) 4595 { 4596 u32 lo, hi, val; 4597 u64 incval; 4598 u8 tmr_idx; 4599 int err; 4600 4601 tmr_idx = ice_get_ptp_src_clock_index(hw); 4602 4603 err = ice_stop_phy_timer_e82x(hw, port, false); 4604 if (err) 4605 return err; 4606 4607 ice_phy_cfg_lane_e82x(hw, port); 4608 4609 err = ice_phy_cfg_uix_e82x(hw, port); 4610 if (err) 4611 return err; 4612 4613 err = ice_phy_cfg_parpcs_e82x(hw, port); 4614 if (err) 4615 return err; 4616 4617 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 4618 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 4619 incval = (u64)hi << 32 | lo; 4620 4621 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L, incval); 4622 if (err) 4623 return err; 4624 4625 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL); 4626 if (err) 4627 return err; 4628 4629 /* Do not perform any action on the main timer */ 4630 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 4631 4632 ice_ptp_exec_tmr_cmd(hw); 4633 4634 err = ice_read_phy_reg_e82x(hw, port, P_REG_PS, &val); 4635 if (err) 4636 return err; 4637 4638 val |= P_REG_PS_SFT_RESET_M; 4639 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4640 if (err) 4641 return err; 4642 4643 val |= P_REG_PS_START_M; 4644 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4645 if (err) 4646 return err; 4647 4648 val &= ~P_REG_PS_SFT_RESET_M; 4649 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4650 if (err) 4651 return err; 4652 4653 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL); 4654 if (err) 4655 return err; 4656 4657 ice_ptp_exec_tmr_cmd(hw); 4658 4659 val |= P_REG_PS_ENA_CLK_M; 4660 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4661 if (err) 4662 return err; 4663 4664 val |= P_REG_PS_LOAD_OFFSET_M; 4665 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4666 if (err) 4667 return err; 4668 4669 ice_ptp_exec_tmr_cmd(hw); 4670 4671 err = ice_sync_phy_timer_e82x(hw, port); 4672 if (err) 4673 return err; 4674 4675 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port); 4676 4677 return 0; 4678 } 4679 4680 /** 4681 * ice_get_phy_tx_tstamp_ready_e82x - Read Tx memory status register 4682 * @hw: pointer to the HW struct 4683 * @quad: the timestamp quad to read from 4684 * @tstamp_ready: contents of the Tx memory status register 4685 * 4686 * Read the Q_REG_TX_MEMORY_STATUS register indicating which timestamps in 4687 * the PHY are ready. A set bit means the corresponding timestamp is valid and 4688 * ready to be captured from the PHY timestamp block. 4689 */ 4690 static int 4691 ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw *hw, u8 quad, u64 *tstamp_ready) 4692 { 4693 u32 hi, lo; 4694 int err; 4695 4696 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_U, &hi); 4697 if (err) { 4698 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_U for quad %u, err %d\n", 4699 quad, err); 4700 return err; 4701 } 4702 4703 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_L, &lo); 4704 if (err) { 4705 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_L for quad %u, err %d\n", 4706 quad, err); 4707 return err; 4708 } 4709 4710 *tstamp_ready = (u64)hi << 32 | (u64)lo; 4711 4712 return 0; 4713 } 4714 4715 /** 4716 * ice_phy_cfg_intr_e82x - Configure TX timestamp interrupt 4717 * @hw: pointer to the HW struct 4718 * @quad: the timestamp quad 4719 * @ena: enable or disable interrupt 4720 * @threshold: interrupt threshold 4721 * 4722 * Configure TX timestamp interrupt for the specified quad 4723 * 4724 * Return: 0 on success, other error codes when failed to read/write quad 4725 */ 4726 4727 int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold) 4728 { 4729 int err; 4730 u32 val; 4731 4732 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val); 4733 if (err) 4734 return err; 4735 4736 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M; 4737 if (ena) { 4738 val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M; 4739 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M; 4740 val |= FIELD_PREP(Q_REG_TX_MEM_GBL_CFG_INTR_THR_M, threshold); 4741 } 4742 4743 return ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val); 4744 } 4745 4746 /** 4747 * ice_ptp_init_phy_e82x - initialize PHY parameters 4748 * @ptp: pointer to the PTP HW struct 4749 */ 4750 static void ice_ptp_init_phy_e82x(struct ice_ptp_hw *ptp) 4751 { 4752 ptp->phy_model = ICE_PHY_E82X; 4753 ptp->num_lports = 8; 4754 ptp->ports_per_phy = 8; 4755 } 4756 4757 /* E810 functions 4758 * 4759 * The following functions operate on the E810 series devices which use 4760 * a separate external PHY. 4761 */ 4762 4763 /** 4764 * ice_read_phy_reg_e810 - Read register from external PHY on E810 4765 * @hw: pointer to the HW struct 4766 * @addr: the address to read from 4767 * @val: On return, the value read from the PHY 4768 * 4769 * Read a register from the external PHY on the E810 device. 4770 */ 4771 static int ice_read_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 *val) 4772 { 4773 struct ice_sbq_msg_input msg = {0}; 4774 int err; 4775 4776 msg.msg_addr_low = lower_16_bits(addr); 4777 msg.msg_addr_high = upper_16_bits(addr); 4778 msg.opcode = ice_sbq_msg_rd; 4779 msg.dest_dev = rmn_0; 4780 4781 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 4782 if (err) { 4783 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 4784 err); 4785 return err; 4786 } 4787 4788 *val = msg.data; 4789 4790 return 0; 4791 } 4792 4793 /** 4794 * ice_write_phy_reg_e810 - Write register on external PHY on E810 4795 * @hw: pointer to the HW struct 4796 * @addr: the address to writem to 4797 * @val: the value to write to the PHY 4798 * 4799 * Write a value to a register of the external PHY on the E810 device. 4800 */ 4801 static int ice_write_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 val) 4802 { 4803 struct ice_sbq_msg_input msg = {0}; 4804 int err; 4805 4806 msg.msg_addr_low = lower_16_bits(addr); 4807 msg.msg_addr_high = upper_16_bits(addr); 4808 msg.opcode = ice_sbq_msg_wr; 4809 msg.dest_dev = rmn_0; 4810 msg.data = val; 4811 4812 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 4813 if (err) { 4814 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 4815 err); 4816 return err; 4817 } 4818 4819 return 0; 4820 } 4821 4822 /** 4823 * ice_read_phy_tstamp_ll_e810 - Read a PHY timestamp registers through the FW 4824 * @hw: pointer to the HW struct 4825 * @idx: the timestamp index to read 4826 * @hi: 8 bit timestamp high value 4827 * @lo: 32 bit timestamp low value 4828 * 4829 * Read a 8bit timestamp high value and 32 bit timestamp low value out of the 4830 * timestamp block of the external PHY on the E810 device using the low latency 4831 * timestamp read. 4832 */ 4833 static int 4834 ice_read_phy_tstamp_ll_e810(struct ice_hw *hw, u8 idx, u8 *hi, u32 *lo) 4835 { 4836 u32 val; 4837 u8 i; 4838 4839 /* Write TS index to read to the PF register so the FW can read it */ 4840 val = FIELD_PREP(TS_LL_READ_TS_IDX, idx) | TS_LL_READ_TS; 4841 wr32(hw, PF_SB_ATQBAL, val); 4842 4843 /* Read the register repeatedly until the FW provides us the TS */ 4844 for (i = TS_LL_READ_RETRIES; i > 0; i--) { 4845 val = rd32(hw, PF_SB_ATQBAL); 4846 4847 /* When the bit is cleared, the TS is ready in the register */ 4848 if (!(FIELD_GET(TS_LL_READ_TS, val))) { 4849 /* High 8 bit value of the TS is on the bits 16:23 */ 4850 *hi = FIELD_GET(TS_LL_READ_TS_HIGH, val); 4851 4852 /* Read the low 32 bit value and set the TS valid bit */ 4853 *lo = rd32(hw, PF_SB_ATQBAH) | TS_VALID; 4854 return 0; 4855 } 4856 4857 udelay(10); 4858 } 4859 4860 /* FW failed to provide the TS in time */ 4861 ice_debug(hw, ICE_DBG_PTP, "Failed to read PTP timestamp using low latency read\n"); 4862 return -EINVAL; 4863 } 4864 4865 /** 4866 * ice_read_phy_tstamp_sbq_e810 - Read a PHY timestamp registers through the sbq 4867 * @hw: pointer to the HW struct 4868 * @lport: the lport to read from 4869 * @idx: the timestamp index to read 4870 * @hi: 8 bit timestamp high value 4871 * @lo: 32 bit timestamp low value 4872 * 4873 * Read a 8bit timestamp high value and 32 bit timestamp low value out of the 4874 * timestamp block of the external PHY on the E810 device using sideband queue. 4875 */ 4876 static int 4877 ice_read_phy_tstamp_sbq_e810(struct ice_hw *hw, u8 lport, u8 idx, u8 *hi, 4878 u32 *lo) 4879 { 4880 u32 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); 4881 u32 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); 4882 u32 lo_val, hi_val; 4883 int err; 4884 4885 err = ice_read_phy_reg_e810(hw, lo_addr, &lo_val); 4886 if (err) { 4887 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 4888 err); 4889 return err; 4890 } 4891 4892 err = ice_read_phy_reg_e810(hw, hi_addr, &hi_val); 4893 if (err) { 4894 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 4895 err); 4896 return err; 4897 } 4898 4899 *lo = lo_val; 4900 *hi = (u8)hi_val; 4901 4902 return 0; 4903 } 4904 4905 /** 4906 * ice_read_phy_tstamp_e810 - Read a PHY timestamp out of the external PHY 4907 * @hw: pointer to the HW struct 4908 * @lport: the lport to read from 4909 * @idx: the timestamp index to read 4910 * @tstamp: on return, the 40bit timestamp value 4911 * 4912 * Read a 40bit timestamp value out of the timestamp block of the external PHY 4913 * on the E810 device. 4914 */ 4915 static int 4916 ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) 4917 { 4918 u32 lo = 0; 4919 u8 hi = 0; 4920 int err; 4921 4922 if (hw->dev_caps.ts_dev_info.ts_ll_read) 4923 err = ice_read_phy_tstamp_ll_e810(hw, idx, &hi, &lo); 4924 else 4925 err = ice_read_phy_tstamp_sbq_e810(hw, lport, idx, &hi, &lo); 4926 4927 if (err) 4928 return err; 4929 4930 /* For E810 devices, the timestamp is reported with the lower 32 bits 4931 * in the low register, and the upper 8 bits in the high register. 4932 */ 4933 *tstamp = ((u64)hi) << TS_HIGH_S | ((u64)lo & TS_LOW_M); 4934 4935 return 0; 4936 } 4937 4938 /** 4939 * ice_clear_phy_tstamp_e810 - Clear a timestamp from the external PHY 4940 * @hw: pointer to the HW struct 4941 * @lport: the lport to read from 4942 * @idx: the timestamp index to reset 4943 * 4944 * Read the timestamp and then forcibly overwrite its value to clear the valid 4945 * bit from the timestamp block of the external PHY on the E810 device. 4946 * 4947 * This function should only be called on an idx whose bit is set according to 4948 * ice_get_phy_tx_tstamp_ready(). 4949 */ 4950 static int ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx) 4951 { 4952 u32 lo_addr, hi_addr; 4953 u64 unused_tstamp; 4954 int err; 4955 4956 err = ice_read_phy_tstamp_e810(hw, lport, idx, &unused_tstamp); 4957 if (err) { 4958 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for lport %u, idx %u, err %d\n", 4959 lport, idx, err); 4960 return err; 4961 } 4962 4963 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); 4964 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); 4965 4966 err = ice_write_phy_reg_e810(hw, lo_addr, 0); 4967 if (err) { 4968 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for lport %u, idx %u, err %d\n", 4969 lport, idx, err); 4970 return err; 4971 } 4972 4973 err = ice_write_phy_reg_e810(hw, hi_addr, 0); 4974 if (err) { 4975 ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register for lport %u, idx %u, err %d\n", 4976 lport, idx, err); 4977 return err; 4978 } 4979 4980 return 0; 4981 } 4982 4983 /** 4984 * ice_ptp_init_phc_e810 - Perform E810 specific PHC initialization 4985 * @hw: pointer to HW struct 4986 * 4987 * Perform E810-specific PTP hardware clock initialization steps. 4988 * 4989 * Return: 0 on success, other error codes when failed to initialize TimeSync 4990 */ 4991 static int ice_ptp_init_phc_e810(struct ice_hw *hw) 4992 { 4993 u8 tmr_idx; 4994 int err; 4995 4996 /* Ensure synchronization delay is zero */ 4997 wr32(hw, GLTSYN_SYNC_DLAY, 0); 4998 4999 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5000 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_ENA(tmr_idx), 5001 GLTSYN_ENA_TSYN_ENA_M); 5002 if (err) 5003 ice_debug(hw, ICE_DBG_PTP, "PTP failed in ena_phy_time_syn %d\n", 5004 err); 5005 5006 return err; 5007 } 5008 5009 /** 5010 * ice_ptp_prep_phy_time_e810 - Prepare PHY port with initial time 5011 * @hw: Board private structure 5012 * @time: Time to initialize the PHY port clock to 5013 * 5014 * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the 5015 * initial clock time. The time will not actually be programmed until the 5016 * driver issues an ICE_PTP_INIT_TIME command. 5017 * 5018 * The time value is the upper 32 bits of the PHY timer, usually in units of 5019 * nominal nanoseconds. 5020 */ 5021 static int ice_ptp_prep_phy_time_e810(struct ice_hw *hw, u32 time) 5022 { 5023 u8 tmr_idx; 5024 int err; 5025 5026 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5027 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_0(tmr_idx), 0); 5028 if (err) { 5029 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_0, err %d\n", 5030 err); 5031 return err; 5032 } 5033 5034 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_L(tmr_idx), time); 5035 if (err) { 5036 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_L, err %d\n", 5037 err); 5038 return err; 5039 } 5040 5041 return 0; 5042 } 5043 5044 /** 5045 * ice_ptp_prep_phy_adj_e810 - Prep PHY port for a time adjustment 5046 * @hw: pointer to HW struct 5047 * @adj: adjustment value to program 5048 * 5049 * Prepare the PHY port for an atomic adjustment by programming the PHY 5050 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual adjustment 5051 * is completed by issuing an ICE_PTP_ADJ_TIME sync command. 5052 * 5053 * The adjustment value only contains the portion used for the upper 32bits of 5054 * the PHY timer, usually in units of nominal nanoseconds. Negative 5055 * adjustments are supported using 2s complement arithmetic. 5056 */ 5057 static int ice_ptp_prep_phy_adj_e810(struct ice_hw *hw, s32 adj) 5058 { 5059 u8 tmr_idx; 5060 int err; 5061 5062 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5063 5064 /* Adjustments are represented as signed 2's complement values in 5065 * nanoseconds. Sub-nanosecond adjustment is not supported. 5066 */ 5067 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), 0); 5068 if (err) { 5069 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_L, err %d\n", 5070 err); 5071 return err; 5072 } 5073 5074 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), adj); 5075 if (err) { 5076 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_H, err %d\n", 5077 err); 5078 return err; 5079 } 5080 5081 return 0; 5082 } 5083 5084 /** 5085 * ice_ptp_prep_phy_incval_e810 - Prep PHY port increment value change 5086 * @hw: pointer to HW struct 5087 * @incval: The new 40bit increment value to prepare 5088 * 5089 * Prepare the PHY port for a new increment value by programming the PHY 5090 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual change is 5091 * completed by issuing an ICE_PTP_INIT_INCVAL command. 5092 */ 5093 static int ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval) 5094 { 5095 u32 high, low; 5096 u8 tmr_idx; 5097 int err; 5098 5099 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5100 low = lower_32_bits(incval); 5101 high = upper_32_bits(incval); 5102 5103 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), low); 5104 if (err) { 5105 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval to PHY SHADJ_L, err %d\n", 5106 err); 5107 return err; 5108 } 5109 5110 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), high); 5111 if (err) { 5112 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval PHY SHADJ_H, err %d\n", 5113 err); 5114 return err; 5115 } 5116 5117 return 0; 5118 } 5119 5120 /** 5121 * ice_ptp_port_cmd_e810 - Prepare all external PHYs for a timer command 5122 * @hw: pointer to HW struct 5123 * @cmd: Command to be sent to the port 5124 * 5125 * Prepare the external PHYs connected to this device for a timer sync 5126 * command. 5127 */ 5128 static int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 5129 { 5130 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 5131 5132 return ice_write_phy_reg_e810(hw, E810_ETH_GLTSYN_CMD, val); 5133 } 5134 5135 /** 5136 * ice_get_phy_tx_tstamp_ready_e810 - Read Tx memory status register 5137 * @hw: pointer to the HW struct 5138 * @port: the PHY port to read 5139 * @tstamp_ready: contents of the Tx memory status register 5140 * 5141 * E810 devices do not use a Tx memory status register. Instead simply 5142 * indicate that all timestamps are currently ready. 5143 */ 5144 static int 5145 ice_get_phy_tx_tstamp_ready_e810(struct ice_hw *hw, u8 port, u64 *tstamp_ready) 5146 { 5147 *tstamp_ready = 0xFFFFFFFFFFFFFFFF; 5148 return 0; 5149 } 5150 5151 /* E810T SMA functions 5152 * 5153 * The following functions operate specifically on E810T hardware and are used 5154 * to access the extended GPIOs available. 5155 */ 5156 5157 /** 5158 * ice_get_pca9575_handle 5159 * @hw: pointer to the hw struct 5160 * @pca9575_handle: GPIO controller's handle 5161 * 5162 * Find and return the GPIO controller's handle in the netlist. 5163 * When found - the value will be cached in the hw structure and following calls 5164 * will return cached value 5165 */ 5166 static int 5167 ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) 5168 { 5169 struct ice_aqc_get_link_topo *cmd; 5170 struct ice_aq_desc desc; 5171 int status; 5172 u8 idx; 5173 5174 /* If handle was read previously return cached value */ 5175 if (hw->io_expander_handle) { 5176 *pca9575_handle = hw->io_expander_handle; 5177 return 0; 5178 } 5179 5180 /* If handle was not detected read it from the netlist */ 5181 cmd = &desc.params.get_link_topo; 5182 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 5183 5184 /* Set node type to GPIO controller */ 5185 cmd->addr.topo_params.node_type_ctx = 5186 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & 5187 ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL); 5188 5189 #define SW_PCA9575_SFP_TOPO_IDX 2 5190 #define SW_PCA9575_QSFP_TOPO_IDX 1 5191 5192 /* Check if the SW IO expander controlling SMA exists in the netlist. */ 5193 if (hw->device_id == ICE_DEV_ID_E810C_SFP) 5194 idx = SW_PCA9575_SFP_TOPO_IDX; 5195 else if (hw->device_id == ICE_DEV_ID_E810C_QSFP) 5196 idx = SW_PCA9575_QSFP_TOPO_IDX; 5197 else 5198 return -EOPNOTSUPP; 5199 5200 cmd->addr.topo_params.index = idx; 5201 5202 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5203 if (status) 5204 return -EOPNOTSUPP; 5205 5206 /* Verify if we found the right IO expander type */ 5207 if (desc.params.get_link_topo.node_part_num != 5208 ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575) 5209 return -EOPNOTSUPP; 5210 5211 /* If present save the handle and return it */ 5212 hw->io_expander_handle = 5213 le16_to_cpu(desc.params.get_link_topo.addr.handle); 5214 *pca9575_handle = hw->io_expander_handle; 5215 5216 return 0; 5217 } 5218 5219 /** 5220 * ice_read_sma_ctrl_e810t 5221 * @hw: pointer to the hw struct 5222 * @data: pointer to data to be read from the GPIO controller 5223 * 5224 * Read the SMA controller state. It is connected to pins 3-7 of Port 1 of the 5225 * PCA9575 expander, so only bits 3-7 in data are valid. 5226 */ 5227 int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data) 5228 { 5229 int status; 5230 u16 handle; 5231 u8 i; 5232 5233 status = ice_get_pca9575_handle(hw, &handle); 5234 if (status) 5235 return status; 5236 5237 *data = 0; 5238 5239 for (i = ICE_SMA_MIN_BIT_E810T; i <= ICE_SMA_MAX_BIT_E810T; i++) { 5240 bool pin; 5241 5242 status = ice_aq_get_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET, 5243 &pin, NULL); 5244 if (status) 5245 break; 5246 *data |= (u8)(!pin) << i; 5247 } 5248 5249 return status; 5250 } 5251 5252 /** 5253 * ice_write_sma_ctrl_e810t 5254 * @hw: pointer to the hw struct 5255 * @data: data to be written to the GPIO controller 5256 * 5257 * Write the data to the SMA controller. It is connected to pins 3-7 of Port 1 5258 * of the PCA9575 expander, so only bits 3-7 in data are valid. 5259 */ 5260 int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data) 5261 { 5262 int status; 5263 u16 handle; 5264 u8 i; 5265 5266 status = ice_get_pca9575_handle(hw, &handle); 5267 if (status) 5268 return status; 5269 5270 for (i = ICE_SMA_MIN_BIT_E810T; i <= ICE_SMA_MAX_BIT_E810T; i++) { 5271 bool pin; 5272 5273 pin = !(data & (1 << i)); 5274 status = ice_aq_set_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET, 5275 pin, NULL); 5276 if (status) 5277 break; 5278 } 5279 5280 return status; 5281 } 5282 5283 /** 5284 * ice_read_pca9575_reg_e810t 5285 * @hw: pointer to the hw struct 5286 * @offset: GPIO controller register offset 5287 * @data: pointer to data to be read from the GPIO controller 5288 * 5289 * Read the register from the GPIO controller 5290 */ 5291 int ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data) 5292 { 5293 struct ice_aqc_link_topo_addr link_topo; 5294 __le16 addr; 5295 u16 handle; 5296 int err; 5297 5298 memset(&link_topo, 0, sizeof(link_topo)); 5299 5300 err = ice_get_pca9575_handle(hw, &handle); 5301 if (err) 5302 return err; 5303 5304 link_topo.handle = cpu_to_le16(handle); 5305 link_topo.topo_params.node_type_ctx = 5306 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, 5307 ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED); 5308 5309 addr = cpu_to_le16((u16)offset); 5310 5311 return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL); 5312 } 5313 5314 /** 5315 * ice_ptp_init_phy_e810 - initialize PHY parameters 5316 * @ptp: pointer to the PTP HW struct 5317 */ 5318 static void ice_ptp_init_phy_e810(struct ice_ptp_hw *ptp) 5319 { 5320 ptp->phy_model = ICE_PHY_E810; 5321 ptp->num_lports = 8; 5322 ptp->ports_per_phy = 4; 5323 } 5324 5325 /* Device agnostic functions 5326 * 5327 * The following functions implement shared behavior common to both E822 and 5328 * E810 devices, possibly calling a device specific implementation where 5329 * necessary. 5330 */ 5331 5332 /** 5333 * ice_ptp_lock - Acquire PTP global semaphore register lock 5334 * @hw: pointer to the HW struct 5335 * 5336 * Acquire the global PTP hardware semaphore lock. Returns true if the lock 5337 * was acquired, false otherwise. 5338 * 5339 * The PFTSYN_SEM register sets the busy bit on read, returning the previous 5340 * value. If software sees the busy bit cleared, this means that this function 5341 * acquired the lock (and the busy bit is now set). If software sees the busy 5342 * bit set, it means that another function acquired the lock. 5343 * 5344 * Software must clear the busy bit with a write to release the lock for other 5345 * functions when done. 5346 */ 5347 bool ice_ptp_lock(struct ice_hw *hw) 5348 { 5349 u32 hw_lock; 5350 int i; 5351 5352 #define MAX_TRIES 15 5353 5354 for (i = 0; i < MAX_TRIES; i++) { 5355 hw_lock = rd32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id)); 5356 hw_lock = hw_lock & PFTSYN_SEM_BUSY_M; 5357 if (hw_lock) { 5358 /* Somebody is holding the lock */ 5359 usleep_range(5000, 6000); 5360 continue; 5361 } 5362 5363 break; 5364 } 5365 5366 return !hw_lock; 5367 } 5368 5369 /** 5370 * ice_ptp_unlock - Release PTP global semaphore register lock 5371 * @hw: pointer to the HW struct 5372 * 5373 * Release the global PTP hardware semaphore lock. This is done by writing to 5374 * the PFTSYN_SEM register. 5375 */ 5376 void ice_ptp_unlock(struct ice_hw *hw) 5377 { 5378 wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0); 5379 } 5380 5381 /** 5382 * ice_ptp_init_hw - Initialize hw based on device type 5383 * @hw: pointer to the HW structure 5384 * 5385 * Determine the PHY model for the device, and initialize hw 5386 * for use by other functions. 5387 */ 5388 void ice_ptp_init_hw(struct ice_hw *hw) 5389 { 5390 struct ice_ptp_hw *ptp = &hw->ptp; 5391 5392 if (ice_is_e822(hw) || ice_is_e823(hw)) 5393 ice_ptp_init_phy_e82x(ptp); 5394 else if (ice_is_e810(hw)) 5395 ice_ptp_init_phy_e810(ptp); 5396 else if (ice_is_e825c(hw)) 5397 ice_ptp_init_phy_e825c(hw); 5398 else 5399 ptp->phy_model = ICE_PHY_UNSUP; 5400 } 5401 5402 /** 5403 * ice_ptp_write_port_cmd - Prepare a single PHY port for a timer command 5404 * @hw: pointer to HW struct 5405 * @port: Port to which cmd has to be sent 5406 * @cmd: Command to be sent to the port 5407 * 5408 * Prepare one port for the upcoming timer sync command. Do not use this for 5409 * programming only a single port, instead use ice_ptp_one_port_cmd() to 5410 * ensure non-modified ports get properly initialized to ICE_PTP_NOP. 5411 * 5412 * Return: 5413 * * %0 - success 5414 * %-EBUSY - PHY type not supported 5415 * * %other - failed to write port command 5416 */ 5417 static int ice_ptp_write_port_cmd(struct ice_hw *hw, u8 port, 5418 enum ice_ptp_tmr_cmd cmd) 5419 { 5420 switch (hw->ptp.phy_model) { 5421 case ICE_PHY_ETH56G: 5422 return ice_ptp_write_port_cmd_eth56g(hw, port, cmd); 5423 case ICE_PHY_E82X: 5424 return ice_ptp_write_port_cmd_e82x(hw, port, cmd); 5425 default: 5426 return -EOPNOTSUPP; 5427 } 5428 } 5429 5430 /** 5431 * ice_ptp_one_port_cmd - Program one PHY port for a timer command 5432 * @hw: pointer to HW struct 5433 * @configured_port: the port that should execute the command 5434 * @configured_cmd: the command to be executed on the configured port 5435 * 5436 * Prepare one port for executing a timer command, while preparing all other 5437 * ports to ICE_PTP_NOP. This allows executing a command on a single port 5438 * while ensuring all other ports do not execute stale commands. 5439 * 5440 * Return: 5441 * * %0 - success 5442 * * %other - failed to write port command 5443 */ 5444 int ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port, 5445 enum ice_ptp_tmr_cmd configured_cmd) 5446 { 5447 u32 port; 5448 5449 for (port = 0; port < hw->ptp.num_lports; port++) { 5450 int err; 5451 5452 /* Program the configured port with the configured command, 5453 * program all other ports with ICE_PTP_NOP. 5454 */ 5455 if (port == configured_port) 5456 err = ice_ptp_write_port_cmd(hw, port, configured_cmd); 5457 else 5458 err = ice_ptp_write_port_cmd(hw, port, ICE_PTP_NOP); 5459 5460 if (err) 5461 return err; 5462 } 5463 5464 return 0; 5465 } 5466 5467 /** 5468 * ice_ptp_port_cmd - Prepare PHY ports for a timer sync command 5469 * @hw: pointer to HW struct 5470 * @cmd: the timer command to setup 5471 * 5472 * Prepare all PHY ports on this device for the requested timer command. For 5473 * some families this can be done in one shot, but for other families each 5474 * port must be configured individually. 5475 * 5476 * Return: 5477 * * %0 - success 5478 * * %other - failed to write port command 5479 */ 5480 static int ice_ptp_port_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 5481 { 5482 u32 port; 5483 5484 /* PHY models which can program all ports simultaneously */ 5485 switch (hw->ptp.phy_model) { 5486 case ICE_PHY_E810: 5487 return ice_ptp_port_cmd_e810(hw, cmd); 5488 default: 5489 break; 5490 } 5491 5492 /* PHY models which require programming each port separately */ 5493 for (port = 0; port < hw->ptp.num_lports; port++) { 5494 int err; 5495 5496 err = ice_ptp_write_port_cmd(hw, port, cmd); 5497 if (err) 5498 return err; 5499 } 5500 5501 return 0; 5502 } 5503 5504 /** 5505 * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command 5506 * @hw: pointer to HW struct 5507 * @cmd: the command to issue 5508 * 5509 * Prepare the source timer and PHY timers and then trigger the requested 5510 * command. This causes the shadow registers previously written in preparation 5511 * for the command to be synchronously applied to both the source and PHY 5512 * timers. 5513 */ 5514 static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 5515 { 5516 int err; 5517 5518 /* First, prepare the source timer */ 5519 ice_ptp_src_cmd(hw, cmd); 5520 5521 /* Next, prepare the ports */ 5522 err = ice_ptp_port_cmd(hw, cmd); 5523 if (err) { 5524 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for timer command %u, err %d\n", 5525 cmd, err); 5526 return err; 5527 } 5528 5529 /* Write the sync command register to drive both source and PHY timer 5530 * commands synchronously 5531 */ 5532 ice_ptp_exec_tmr_cmd(hw); 5533 5534 return 0; 5535 } 5536 5537 /** 5538 * ice_ptp_init_time - Initialize device time to provided value 5539 * @hw: pointer to HW struct 5540 * @time: 64bits of time (GLTSYN_TIME_L and GLTSYN_TIME_H) 5541 * 5542 * Initialize the device to the specified time provided. This requires a three 5543 * step process: 5544 * 5545 * 1) write the new init time to the source timer shadow registers 5546 * 2) write the new init time to the PHY timer shadow registers 5547 * 3) issue an init_time timer command to synchronously switch both the source 5548 * and port timers to the new init time value at the next clock cycle. 5549 */ 5550 int ice_ptp_init_time(struct ice_hw *hw, u64 time) 5551 { 5552 u8 tmr_idx; 5553 int err; 5554 5555 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5556 5557 /* Source timers */ 5558 wr32(hw, GLTSYN_SHTIME_L(tmr_idx), lower_32_bits(time)); 5559 wr32(hw, GLTSYN_SHTIME_H(tmr_idx), upper_32_bits(time)); 5560 wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0); 5561 5562 /* PHY timers */ 5563 /* Fill Rx and Tx ports and send msg to PHY */ 5564 switch (hw->ptp.phy_model) { 5565 case ICE_PHY_ETH56G: 5566 err = ice_ptp_prep_phy_time_eth56g(hw, 5567 (u32)(time & 0xFFFFFFFF)); 5568 break; 5569 case ICE_PHY_E810: 5570 err = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF); 5571 break; 5572 case ICE_PHY_E82X: 5573 err = ice_ptp_prep_phy_time_e82x(hw, time & 0xFFFFFFFF); 5574 break; 5575 default: 5576 err = -EOPNOTSUPP; 5577 } 5578 5579 if (err) 5580 return err; 5581 5582 return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_TIME); 5583 } 5584 5585 /** 5586 * ice_ptp_write_incval - Program PHC with new increment value 5587 * @hw: pointer to HW struct 5588 * @incval: Source timer increment value per clock cycle 5589 * 5590 * Program the PHC with a new increment value. This requires a three-step 5591 * process: 5592 * 5593 * 1) Write the increment value to the source timer shadow registers 5594 * 2) Write the increment value to the PHY timer shadow registers 5595 * 3) Issue an ICE_PTP_INIT_INCVAL timer command to synchronously switch both 5596 * the source and port timers to the new increment value at the next clock 5597 * cycle. 5598 */ 5599 int ice_ptp_write_incval(struct ice_hw *hw, u64 incval) 5600 { 5601 u8 tmr_idx; 5602 int err; 5603 5604 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5605 5606 /* Shadow Adjust */ 5607 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), lower_32_bits(incval)); 5608 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), upper_32_bits(incval)); 5609 5610 switch (hw->ptp.phy_model) { 5611 case ICE_PHY_ETH56G: 5612 err = ice_ptp_prep_phy_incval_eth56g(hw, incval); 5613 break; 5614 case ICE_PHY_E810: 5615 err = ice_ptp_prep_phy_incval_e810(hw, incval); 5616 break; 5617 case ICE_PHY_E82X: 5618 err = ice_ptp_prep_phy_incval_e82x(hw, incval); 5619 break; 5620 default: 5621 err = -EOPNOTSUPP; 5622 } 5623 5624 if (err) 5625 return err; 5626 5627 return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_INCVAL); 5628 } 5629 5630 /** 5631 * ice_ptp_write_incval_locked - Program new incval while holding semaphore 5632 * @hw: pointer to HW struct 5633 * @incval: Source timer increment value per clock cycle 5634 * 5635 * Program a new PHC incval while holding the PTP semaphore. 5636 */ 5637 int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval) 5638 { 5639 int err; 5640 5641 if (!ice_ptp_lock(hw)) 5642 return -EBUSY; 5643 5644 err = ice_ptp_write_incval(hw, incval); 5645 5646 ice_ptp_unlock(hw); 5647 5648 return err; 5649 } 5650 5651 /** 5652 * ice_ptp_adj_clock - Adjust PHC clock time atomically 5653 * @hw: pointer to HW struct 5654 * @adj: Adjustment in nanoseconds 5655 * 5656 * Perform an atomic adjustment of the PHC time by the specified number of 5657 * nanoseconds. This requires a three-step process: 5658 * 5659 * 1) Write the adjustment to the source timer shadow registers 5660 * 2) Write the adjustment to the PHY timer shadow registers 5661 * 3) Issue an ICE_PTP_ADJ_TIME timer command to synchronously apply the 5662 * adjustment to both the source and port timers at the next clock cycle. 5663 */ 5664 int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj) 5665 { 5666 u8 tmr_idx; 5667 int err; 5668 5669 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5670 5671 /* Write the desired clock adjustment into the GLTSYN_SHADJ register. 5672 * For an ICE_PTP_ADJ_TIME command, this set of registers represents 5673 * the value to add to the clock time. It supports subtraction by 5674 * interpreting the value as a 2's complement integer. 5675 */ 5676 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0); 5677 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj); 5678 5679 switch (hw->ptp.phy_model) { 5680 case ICE_PHY_ETH56G: 5681 err = ice_ptp_prep_phy_adj_eth56g(hw, adj); 5682 break; 5683 case ICE_PHY_E810: 5684 err = ice_ptp_prep_phy_adj_e810(hw, adj); 5685 break; 5686 case ICE_PHY_E82X: 5687 err = ice_ptp_prep_phy_adj_e82x(hw, adj); 5688 break; 5689 default: 5690 err = -EOPNOTSUPP; 5691 } 5692 5693 if (err) 5694 return err; 5695 5696 return ice_ptp_tmr_cmd(hw, ICE_PTP_ADJ_TIME); 5697 } 5698 5699 /** 5700 * ice_read_phy_tstamp - Read a PHY timestamp from the timestamo block 5701 * @hw: pointer to the HW struct 5702 * @block: the block to read from 5703 * @idx: the timestamp index to read 5704 * @tstamp: on return, the 40bit timestamp value 5705 * 5706 * Read a 40bit timestamp value out of the timestamp block. For E822 devices, 5707 * the block is the quad to read from. For E810 devices, the block is the 5708 * logical port to read from. 5709 */ 5710 int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp) 5711 { 5712 switch (hw->ptp.phy_model) { 5713 case ICE_PHY_ETH56G: 5714 return ice_read_ptp_tstamp_eth56g(hw, block, idx, tstamp); 5715 case ICE_PHY_E810: 5716 return ice_read_phy_tstamp_e810(hw, block, idx, tstamp); 5717 case ICE_PHY_E82X: 5718 return ice_read_phy_tstamp_e82x(hw, block, idx, tstamp); 5719 default: 5720 return -EOPNOTSUPP; 5721 } 5722 } 5723 5724 /** 5725 * ice_clear_phy_tstamp - Clear a timestamp from the timestamp block 5726 * @hw: pointer to the HW struct 5727 * @block: the block to read from 5728 * @idx: the timestamp index to reset 5729 * 5730 * Clear a timestamp from the timestamp block, discarding its value without 5731 * returning it. This resets the memory status bit for the timestamp index 5732 * allowing it to be reused for another timestamp in the future. 5733 * 5734 * For E822 devices, the block number is the PHY quad to clear from. For E810 5735 * devices, the block number is the logical port to clear from. 5736 * 5737 * This function must only be called on a timestamp index whose valid bit is 5738 * set according to ice_get_phy_tx_tstamp_ready(). 5739 */ 5740 int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx) 5741 { 5742 switch (hw->ptp.phy_model) { 5743 case ICE_PHY_ETH56G: 5744 return ice_clear_ptp_tstamp_eth56g(hw, block, idx); 5745 case ICE_PHY_E810: 5746 return ice_clear_phy_tstamp_e810(hw, block, idx); 5747 case ICE_PHY_E82X: 5748 return ice_clear_phy_tstamp_e82x(hw, block, idx); 5749 default: 5750 return -EOPNOTSUPP; 5751 } 5752 } 5753 5754 /** 5755 * ice_get_pf_c827_idx - find and return the C827 index for the current pf 5756 * @hw: pointer to the hw struct 5757 * @idx: index of the found C827 PHY 5758 * Return: 5759 * * 0 - success 5760 * * negative - failure 5761 */ 5762 static int ice_get_pf_c827_idx(struct ice_hw *hw, u8 *idx) 5763 { 5764 struct ice_aqc_get_link_topo cmd; 5765 u8 node_part_number; 5766 u16 node_handle; 5767 int status; 5768 u8 ctx; 5769 5770 if (hw->mac_type != ICE_MAC_E810) 5771 return -ENODEV; 5772 5773 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) { 5774 *idx = C827_0; 5775 return 0; 5776 } 5777 5778 memset(&cmd, 0, sizeof(cmd)); 5779 5780 ctx = ICE_AQC_LINK_TOPO_NODE_TYPE_PHY << ICE_AQC_LINK_TOPO_NODE_TYPE_S; 5781 ctx |= ICE_AQC_LINK_TOPO_NODE_CTX_PORT << ICE_AQC_LINK_TOPO_NODE_CTX_S; 5782 cmd.addr.topo_params.node_type_ctx = ctx; 5783 5784 status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number, 5785 &node_handle); 5786 if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827) 5787 return -ENOENT; 5788 5789 if (node_handle == E810C_QSFP_C827_0_HANDLE) 5790 *idx = C827_0; 5791 else if (node_handle == E810C_QSFP_C827_1_HANDLE) 5792 *idx = C827_1; 5793 else 5794 return -EIO; 5795 5796 return 0; 5797 } 5798 5799 /** 5800 * ice_ptp_reset_ts_memory - Reset timestamp memory for all blocks 5801 * @hw: pointer to the HW struct 5802 */ 5803 void ice_ptp_reset_ts_memory(struct ice_hw *hw) 5804 { 5805 switch (hw->ptp.phy_model) { 5806 case ICE_PHY_ETH56G: 5807 ice_ptp_reset_ts_memory_eth56g(hw); 5808 break; 5809 case ICE_PHY_E82X: 5810 ice_ptp_reset_ts_memory_e82x(hw); 5811 break; 5812 case ICE_PHY_E810: 5813 default: 5814 return; 5815 } 5816 } 5817 5818 /** 5819 * ice_ptp_init_phc - Initialize PTP hardware clock 5820 * @hw: pointer to the HW struct 5821 * 5822 * Perform the steps required to initialize the PTP hardware clock. 5823 */ 5824 int ice_ptp_init_phc(struct ice_hw *hw) 5825 { 5826 u8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5827 5828 /* Enable source clocks */ 5829 wr32(hw, GLTSYN_ENA(src_idx), GLTSYN_ENA_TSYN_ENA_M); 5830 5831 /* Clear event err indications for auxiliary pins */ 5832 (void)rd32(hw, GLTSYN_STAT(src_idx)); 5833 5834 switch (hw->ptp.phy_model) { 5835 case ICE_PHY_ETH56G: 5836 return ice_ptp_init_phc_eth56g(hw); 5837 case ICE_PHY_E810: 5838 return ice_ptp_init_phc_e810(hw); 5839 case ICE_PHY_E82X: 5840 return ice_ptp_init_phc_e82x(hw); 5841 default: 5842 return -EOPNOTSUPP; 5843 } 5844 } 5845 5846 /** 5847 * ice_get_phy_tx_tstamp_ready - Read PHY Tx memory status indication 5848 * @hw: pointer to the HW struct 5849 * @block: the timestamp block to check 5850 * @tstamp_ready: storage for the PHY Tx memory status information 5851 * 5852 * Check the PHY for Tx timestamp memory status. This reports a 64 bit value 5853 * which indicates which timestamps in the block may be captured. A set bit 5854 * means the timestamp can be read. An unset bit means the timestamp is not 5855 * ready and software should avoid reading the register. 5856 */ 5857 int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready) 5858 { 5859 switch (hw->ptp.phy_model) { 5860 case ICE_PHY_ETH56G: 5861 return ice_get_phy_tx_tstamp_ready_eth56g(hw, block, 5862 tstamp_ready); 5863 case ICE_PHY_E810: 5864 return ice_get_phy_tx_tstamp_ready_e810(hw, block, 5865 tstamp_ready); 5866 case ICE_PHY_E82X: 5867 return ice_get_phy_tx_tstamp_ready_e82x(hw, block, 5868 tstamp_ready); 5869 break; 5870 default: 5871 return -EOPNOTSUPP; 5872 } 5873 } 5874 5875 /** 5876 * ice_cgu_get_pin_desc_e823 - get pin description array 5877 * @hw: pointer to the hw struct 5878 * @input: if request is done against input or output pin 5879 * @size: number of inputs/outputs 5880 * 5881 * Return: pointer to pin description array associated to given hw. 5882 */ 5883 static const struct ice_cgu_pin_desc * 5884 ice_cgu_get_pin_desc_e823(struct ice_hw *hw, bool input, int *size) 5885 { 5886 static const struct ice_cgu_pin_desc *t; 5887 5888 if (hw->cgu_part_number == 5889 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032) { 5890 if (input) { 5891 t = ice_e823_zl_cgu_inputs; 5892 *size = ARRAY_SIZE(ice_e823_zl_cgu_inputs); 5893 } else { 5894 t = ice_e823_zl_cgu_outputs; 5895 *size = ARRAY_SIZE(ice_e823_zl_cgu_outputs); 5896 } 5897 } else if (hw->cgu_part_number == 5898 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384) { 5899 if (input) { 5900 t = ice_e823_si_cgu_inputs; 5901 *size = ARRAY_SIZE(ice_e823_si_cgu_inputs); 5902 } else { 5903 t = ice_e823_si_cgu_outputs; 5904 *size = ARRAY_SIZE(ice_e823_si_cgu_outputs); 5905 } 5906 } else { 5907 t = NULL; 5908 *size = 0; 5909 } 5910 5911 return t; 5912 } 5913 5914 /** 5915 * ice_cgu_get_pin_desc - get pin description array 5916 * @hw: pointer to the hw struct 5917 * @input: if request is done against input or output pins 5918 * @size: size of array returned by function 5919 * 5920 * Return: pointer to pin description array associated to given hw. 5921 */ 5922 static const struct ice_cgu_pin_desc * 5923 ice_cgu_get_pin_desc(struct ice_hw *hw, bool input, int *size) 5924 { 5925 const struct ice_cgu_pin_desc *t = NULL; 5926 5927 switch (hw->device_id) { 5928 case ICE_DEV_ID_E810C_SFP: 5929 if (input) { 5930 t = ice_e810t_sfp_cgu_inputs; 5931 *size = ARRAY_SIZE(ice_e810t_sfp_cgu_inputs); 5932 } else { 5933 t = ice_e810t_sfp_cgu_outputs; 5934 *size = ARRAY_SIZE(ice_e810t_sfp_cgu_outputs); 5935 } 5936 break; 5937 case ICE_DEV_ID_E810C_QSFP: 5938 if (input) { 5939 t = ice_e810t_qsfp_cgu_inputs; 5940 *size = ARRAY_SIZE(ice_e810t_qsfp_cgu_inputs); 5941 } else { 5942 t = ice_e810t_qsfp_cgu_outputs; 5943 *size = ARRAY_SIZE(ice_e810t_qsfp_cgu_outputs); 5944 } 5945 break; 5946 case ICE_DEV_ID_E823L_10G_BASE_T: 5947 case ICE_DEV_ID_E823L_1GBE: 5948 case ICE_DEV_ID_E823L_BACKPLANE: 5949 case ICE_DEV_ID_E823L_QSFP: 5950 case ICE_DEV_ID_E823L_SFP: 5951 case ICE_DEV_ID_E823C_10G_BASE_T: 5952 case ICE_DEV_ID_E823C_BACKPLANE: 5953 case ICE_DEV_ID_E823C_QSFP: 5954 case ICE_DEV_ID_E823C_SFP: 5955 case ICE_DEV_ID_E823C_SGMII: 5956 t = ice_cgu_get_pin_desc_e823(hw, input, size); 5957 break; 5958 default: 5959 break; 5960 } 5961 5962 return t; 5963 } 5964 5965 /** 5966 * ice_cgu_get_num_pins - get pin description array size 5967 * @hw: pointer to the hw struct 5968 * @input: if request is done against input or output pins 5969 * 5970 * Return: size of pin description array for given hw. 5971 */ 5972 int ice_cgu_get_num_pins(struct ice_hw *hw, bool input) 5973 { 5974 const struct ice_cgu_pin_desc *t; 5975 int size; 5976 5977 t = ice_cgu_get_pin_desc(hw, input, &size); 5978 if (t) 5979 return size; 5980 5981 return 0; 5982 } 5983 5984 /** 5985 * ice_cgu_get_pin_type - get pin's type 5986 * @hw: pointer to the hw struct 5987 * @pin: pin index 5988 * @input: if request is done against input or output pin 5989 * 5990 * Return: type of a pin. 5991 */ 5992 enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool input) 5993 { 5994 const struct ice_cgu_pin_desc *t; 5995 int t_size; 5996 5997 t = ice_cgu_get_pin_desc(hw, input, &t_size); 5998 5999 if (!t) 6000 return 0; 6001 6002 if (pin >= t_size) 6003 return 0; 6004 6005 return t[pin].type; 6006 } 6007 6008 /** 6009 * ice_cgu_get_pin_freq_supp - get pin's supported frequency 6010 * @hw: pointer to the hw struct 6011 * @pin: pin index 6012 * @input: if request is done against input or output pin 6013 * @num: output number of supported frequencies 6014 * 6015 * Get frequency supported number and array of supported frequencies. 6016 * 6017 * Return: array of supported frequencies for given pin. 6018 */ 6019 struct dpll_pin_frequency * 6020 ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num) 6021 { 6022 const struct ice_cgu_pin_desc *t; 6023 int t_size; 6024 6025 *num = 0; 6026 t = ice_cgu_get_pin_desc(hw, input, &t_size); 6027 if (!t) 6028 return NULL; 6029 if (pin >= t_size) 6030 return NULL; 6031 *num = t[pin].freq_supp_num; 6032 6033 return t[pin].freq_supp; 6034 } 6035 6036 /** 6037 * ice_cgu_get_pin_name - get pin's name 6038 * @hw: pointer to the hw struct 6039 * @pin: pin index 6040 * @input: if request is done against input or output pin 6041 * 6042 * Return: 6043 * * null terminated char array with name 6044 * * NULL in case of failure 6045 */ 6046 const char *ice_cgu_get_pin_name(struct ice_hw *hw, u8 pin, bool input) 6047 { 6048 const struct ice_cgu_pin_desc *t; 6049 int t_size; 6050 6051 t = ice_cgu_get_pin_desc(hw, input, &t_size); 6052 6053 if (!t) 6054 return NULL; 6055 6056 if (pin >= t_size) 6057 return NULL; 6058 6059 return t[pin].name; 6060 } 6061 6062 /** 6063 * ice_get_cgu_state - get the state of the DPLL 6064 * @hw: pointer to the hw struct 6065 * @dpll_idx: Index of internal DPLL unit 6066 * @last_dpll_state: last known state of DPLL 6067 * @pin: pointer to a buffer for returning currently active pin 6068 * @ref_state: reference clock state 6069 * @eec_mode: eec mode of the DPLL 6070 * @phase_offset: pointer to a buffer for returning phase offset 6071 * @dpll_state: state of the DPLL (output) 6072 * 6073 * This function will read the state of the DPLL(dpll_idx). Non-null 6074 * 'pin', 'ref_state', 'eec_mode' and 'phase_offset' parameters are used to 6075 * retrieve currently active pin, state, mode and phase_offset respectively. 6076 * 6077 * Return: state of the DPLL 6078 */ 6079 int ice_get_cgu_state(struct ice_hw *hw, u8 dpll_idx, 6080 enum dpll_lock_status last_dpll_state, u8 *pin, 6081 u8 *ref_state, u8 *eec_mode, s64 *phase_offset, 6082 enum dpll_lock_status *dpll_state) 6083 { 6084 u8 hw_ref_state, hw_dpll_state, hw_eec_mode, hw_config; 6085 s64 hw_phase_offset; 6086 int status; 6087 6088 status = ice_aq_get_cgu_dpll_status(hw, dpll_idx, &hw_ref_state, 6089 &hw_dpll_state, &hw_config, 6090 &hw_phase_offset, &hw_eec_mode); 6091 if (status) 6092 return status; 6093 6094 if (pin) 6095 /* current ref pin in dpll_state_refsel_status_X register */ 6096 *pin = hw_config & ICE_AQC_GET_CGU_DPLL_CONFIG_CLK_REF_SEL; 6097 if (phase_offset) 6098 *phase_offset = hw_phase_offset; 6099 if (ref_state) 6100 *ref_state = hw_ref_state; 6101 if (eec_mode) 6102 *eec_mode = hw_eec_mode; 6103 if (!dpll_state) 6104 return 0; 6105 6106 /* According to ZL DPLL documentation, once state reach LOCKED_HO_ACQ 6107 * it would never return to FREERUN. This aligns to ITU-T G.781 6108 * Recommendation. We cannot report HOLDOVER as HO memory is cleared 6109 * while switching to another reference. 6110 * Only for situations where previous state was either: "LOCKED without 6111 * HO_ACQ" or "HOLDOVER" we actually back to FREERUN. 6112 */ 6113 if (hw_dpll_state & ICE_AQC_GET_CGU_DPLL_STATUS_STATE_LOCK) { 6114 if (hw_dpll_state & ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO_READY) 6115 *dpll_state = DPLL_LOCK_STATUS_LOCKED_HO_ACQ; 6116 else 6117 *dpll_state = DPLL_LOCK_STATUS_LOCKED; 6118 } else if (last_dpll_state == DPLL_LOCK_STATUS_LOCKED_HO_ACQ || 6119 last_dpll_state == DPLL_LOCK_STATUS_HOLDOVER) { 6120 *dpll_state = DPLL_LOCK_STATUS_HOLDOVER; 6121 } else { 6122 *dpll_state = DPLL_LOCK_STATUS_UNLOCKED; 6123 } 6124 6125 return 0; 6126 } 6127 6128 /** 6129 * ice_get_cgu_rclk_pin_info - get info on available recovered clock pins 6130 * @hw: pointer to the hw struct 6131 * @base_idx: returns index of first recovered clock pin on device 6132 * @pin_num: returns number of recovered clock pins available on device 6133 * 6134 * Based on hw provide caller info about recovery clock pins available on the 6135 * board. 6136 * 6137 * Return: 6138 * * 0 - success, information is valid 6139 * * negative - failure, information is not valid 6140 */ 6141 int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num) 6142 { 6143 u8 phy_idx; 6144 int ret; 6145 6146 switch (hw->device_id) { 6147 case ICE_DEV_ID_E810C_SFP: 6148 case ICE_DEV_ID_E810C_QSFP: 6149 6150 ret = ice_get_pf_c827_idx(hw, &phy_idx); 6151 if (ret) 6152 return ret; 6153 *base_idx = E810T_CGU_INPUT_C827(phy_idx, ICE_RCLKA_PIN); 6154 *pin_num = ICE_E810_RCLK_PINS_NUM; 6155 ret = 0; 6156 break; 6157 case ICE_DEV_ID_E823L_10G_BASE_T: 6158 case ICE_DEV_ID_E823L_1GBE: 6159 case ICE_DEV_ID_E823L_BACKPLANE: 6160 case ICE_DEV_ID_E823L_QSFP: 6161 case ICE_DEV_ID_E823L_SFP: 6162 case ICE_DEV_ID_E823C_10G_BASE_T: 6163 case ICE_DEV_ID_E823C_BACKPLANE: 6164 case ICE_DEV_ID_E823C_QSFP: 6165 case ICE_DEV_ID_E823C_SFP: 6166 case ICE_DEV_ID_E823C_SGMII: 6167 *pin_num = ICE_E82X_RCLK_PINS_NUM; 6168 ret = 0; 6169 if (hw->cgu_part_number == 6170 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032) 6171 *base_idx = ZL_REF1P; 6172 else if (hw->cgu_part_number == 6173 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384) 6174 *base_idx = SI_REF1P; 6175 else 6176 ret = -ENODEV; 6177 6178 break; 6179 default: 6180 ret = -ENODEV; 6181 break; 6182 } 6183 6184 return ret; 6185 } 6186 6187 /** 6188 * ice_cgu_get_output_pin_state_caps - get output pin state capabilities 6189 * @hw: pointer to the hw struct 6190 * @pin_id: id of a pin 6191 * @caps: capabilities to modify 6192 * 6193 * Return: 6194 * * 0 - success, state capabilities were modified 6195 * * negative - failure, capabilities were not modified 6196 */ 6197 int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id, 6198 unsigned long *caps) 6199 { 6200 bool can_change = true; 6201 6202 switch (hw->device_id) { 6203 case ICE_DEV_ID_E810C_SFP: 6204 if (pin_id == ZL_OUT2 || pin_id == ZL_OUT3) 6205 can_change = false; 6206 break; 6207 case ICE_DEV_ID_E810C_QSFP: 6208 if (pin_id == ZL_OUT2 || pin_id == ZL_OUT3 || pin_id == ZL_OUT4) 6209 can_change = false; 6210 break; 6211 case ICE_DEV_ID_E823L_10G_BASE_T: 6212 case ICE_DEV_ID_E823L_1GBE: 6213 case ICE_DEV_ID_E823L_BACKPLANE: 6214 case ICE_DEV_ID_E823L_QSFP: 6215 case ICE_DEV_ID_E823L_SFP: 6216 case ICE_DEV_ID_E823C_10G_BASE_T: 6217 case ICE_DEV_ID_E823C_BACKPLANE: 6218 case ICE_DEV_ID_E823C_QSFP: 6219 case ICE_DEV_ID_E823C_SFP: 6220 case ICE_DEV_ID_E823C_SGMII: 6221 if (hw->cgu_part_number == 6222 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032 && 6223 pin_id == ZL_OUT2) 6224 can_change = false; 6225 else if (hw->cgu_part_number == 6226 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384 && 6227 pin_id == SI_OUT1) 6228 can_change = false; 6229 break; 6230 default: 6231 return -EINVAL; 6232 } 6233 if (can_change) 6234 *caps |= DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE; 6235 else 6236 *caps &= ~DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE; 6237 6238 return 0; 6239 } 6240