1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (C) 2021, Intel Corporation. */ 3 4 #include <linux/delay.h> 5 #include <linux/iopoll.h> 6 #include "ice_common.h" 7 #include "ice_ptp_hw.h" 8 #include "ice_ptp_consts.h" 9 #include "ice_cgu_regs.h" 10 11 static struct dpll_pin_frequency ice_cgu_pin_freq_common[] = { 12 DPLL_PIN_FREQUENCY_1PPS, 13 DPLL_PIN_FREQUENCY_10MHZ, 14 }; 15 16 static struct dpll_pin_frequency ice_cgu_pin_freq_1_hz[] = { 17 DPLL_PIN_FREQUENCY_1PPS, 18 }; 19 20 static struct dpll_pin_frequency ice_cgu_pin_freq_10_mhz[] = { 21 DPLL_PIN_FREQUENCY_10MHZ, 22 }; 23 24 static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_inputs[] = { 25 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR, 26 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 27 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR, 28 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 29 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, }, 30 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, }, 31 { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT, 32 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 33 { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT, 34 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 35 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS, 36 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 37 }; 38 39 static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_inputs[] = { 40 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR, 41 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 42 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR, 43 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 44 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, }, 45 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, }, 46 { "C827_1-RCLKA", ZL_REF2P, DPLL_PIN_TYPE_MUX, }, 47 { "C827_1-RCLKB", ZL_REF2N, DPLL_PIN_TYPE_MUX, }, 48 { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT, 49 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 50 { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT, 51 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 52 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS, 53 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 54 }; 55 56 static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_outputs[] = { 57 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT, 58 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 59 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT, 60 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 61 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, }, 62 { "MAC-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, }, 63 { "CVL-SDP21", ZL_OUT4, DPLL_PIN_TYPE_EXT, 64 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 65 { "CVL-SDP23", ZL_OUT5, DPLL_PIN_TYPE_EXT, 66 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 67 }; 68 69 static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_outputs[] = { 70 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT, 71 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 72 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT, 73 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 74 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 75 { "PHY2-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 76 { "MAC-CLK", ZL_OUT4, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 77 { "CVL-SDP21", ZL_OUT5, DPLL_PIN_TYPE_EXT, 78 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 79 { "CVL-SDP23", ZL_OUT6, DPLL_PIN_TYPE_EXT, 80 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 81 }; 82 83 static const struct ice_cgu_pin_desc ice_e823_si_cgu_inputs[] = { 84 { "NONE", SI_REF0P, 0, 0 }, 85 { "NONE", SI_REF0N, 0, 0 }, 86 { "SYNCE0_DP", SI_REF1P, DPLL_PIN_TYPE_MUX, 0 }, 87 { "SYNCE0_DN", SI_REF1N, DPLL_PIN_TYPE_MUX, 0 }, 88 { "EXT_CLK_SYNC", SI_REF2P, DPLL_PIN_TYPE_EXT, 89 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 90 { "NONE", SI_REF2N, 0, 0 }, 91 { "EXT_PPS_OUT", SI_REF3, DPLL_PIN_TYPE_EXT, 92 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 93 { "INT_PPS_OUT", SI_REF4, DPLL_PIN_TYPE_EXT, 94 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 95 }; 96 97 static const struct ice_cgu_pin_desc ice_e823_si_cgu_outputs[] = { 98 { "1588-TIME_SYNC", SI_OUT0, DPLL_PIN_TYPE_EXT, 99 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 100 { "PHY-CLK", SI_OUT1, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 101 { "10MHZ-SMA2", SI_OUT2, DPLL_PIN_TYPE_EXT, 102 ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz }, 103 { "PPS-SMA1", SI_OUT3, DPLL_PIN_TYPE_EXT, 104 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 105 }; 106 107 static const struct ice_cgu_pin_desc ice_e823_zl_cgu_inputs[] = { 108 { "NONE", ZL_REF0P, 0, 0 }, 109 { "INT_PPS_OUT", ZL_REF0N, DPLL_PIN_TYPE_EXT, 110 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 111 { "SYNCE0_DP", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0 }, 112 { "SYNCE0_DN", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0 }, 113 { "NONE", ZL_REF2P, 0, 0 }, 114 { "NONE", ZL_REF2N, 0, 0 }, 115 { "EXT_CLK_SYNC", ZL_REF3P, DPLL_PIN_TYPE_EXT, 116 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 117 { "NONE", ZL_REF3N, 0, 0 }, 118 { "EXT_PPS_OUT", ZL_REF4P, DPLL_PIN_TYPE_EXT, 119 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 120 { "OCXO", ZL_REF4N, DPLL_PIN_TYPE_INT_OSCILLATOR, 0 }, 121 }; 122 123 static const struct ice_cgu_pin_desc ice_e823_zl_cgu_outputs[] = { 124 { "PPS-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT, 125 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 126 { "10MHZ-SMA2", ZL_OUT1, DPLL_PIN_TYPE_EXT, 127 ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz }, 128 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 129 { "1588-TIME_REF", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 130 { "CPK-TIME_SYNC", ZL_OUT4, DPLL_PIN_TYPE_EXT, 131 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 132 { "NONE", ZL_OUT5, 0, 0 }, 133 }; 134 135 /* Low level functions for interacting with and managing the device clock used 136 * for the Precision Time Protocol. 137 * 138 * The ice hardware represents the current time using three registers: 139 * 140 * GLTSYN_TIME_H GLTSYN_TIME_L GLTSYN_TIME_R 141 * +---------------+ +---------------+ +---------------+ 142 * | 32 bits | | 32 bits | | 32 bits | 143 * +---------------+ +---------------+ +---------------+ 144 * 145 * The registers are incremented every clock tick using a 40bit increment 146 * value defined over two registers: 147 * 148 * GLTSYN_INCVAL_H GLTSYN_INCVAL_L 149 * +---------------+ +---------------+ 150 * | 8 bit s | | 32 bits | 151 * +---------------+ +---------------+ 152 * 153 * The increment value is added to the GLSTYN_TIME_R and GLSTYN_TIME_L 154 * registers every clock source tick. Depending on the specific device 155 * configuration, the clock source frequency could be one of a number of 156 * values. 157 * 158 * For E810 devices, the increment frequency is 812.5 MHz 159 * 160 * For E822 devices the clock can be derived from different sources, and the 161 * increment has an effective frequency of one of the following: 162 * - 823.4375 MHz 163 * - 783.36 MHz 164 * - 796.875 MHz 165 * - 816 MHz 166 * - 830.078125 MHz 167 * - 783.36 MHz 168 * 169 * The hardware captures timestamps in the PHY for incoming packets, and for 170 * outgoing packets on request. To support this, the PHY maintains a timer 171 * that matches the lower 64 bits of the global source timer. 172 * 173 * In order to ensure that the PHY timers and the source timer are equivalent, 174 * shadow registers are used to prepare the desired initial values. A special 175 * sync command is issued to trigger copying from the shadow registers into 176 * the appropriate source and PHY registers simultaneously. 177 * 178 * The driver supports devices which have different PHYs with subtly different 179 * mechanisms to program and control the timers. We divide the devices into 180 * families named after the first major device, E810 and similar devices, and 181 * E822 and similar devices. 182 * 183 * - E822 based devices have additional support for fine grained Vernier 184 * calibration which requires significant setup 185 * - The layout of timestamp data in the PHY register blocks is different 186 * - The way timer synchronization commands are issued is different. 187 * 188 * To support this, very low level functions have an e810 or e822 suffix 189 * indicating what type of device they work on. Higher level abstractions for 190 * tasks that can be done on both devices do not have the suffix and will 191 * correctly look up the appropriate low level function when running. 192 * 193 * Functions which only make sense on a single device family may not have 194 * a suitable generic implementation 195 */ 196 197 /** 198 * ice_get_ptp_src_clock_index - determine source clock index 199 * @hw: pointer to HW struct 200 * 201 * Determine the source clock index currently in use, based on device 202 * capabilities reported during initialization. 203 */ 204 u8 ice_get_ptp_src_clock_index(struct ice_hw *hw) 205 { 206 return hw->func_caps.ts_func_info.tmr_index_assoc; 207 } 208 209 /** 210 * ice_ptp_read_src_incval - Read source timer increment value 211 * @hw: pointer to HW struct 212 * 213 * Read the increment value of the source timer and return it. 214 */ 215 static u64 ice_ptp_read_src_incval(struct ice_hw *hw) 216 { 217 u32 lo, hi; 218 u8 tmr_idx; 219 220 tmr_idx = ice_get_ptp_src_clock_index(hw); 221 222 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 223 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 224 225 return ((u64)(hi & INCVAL_HIGH_M) << 32) | lo; 226 } 227 228 /** 229 * ice_read_cgu_reg_e82x - Read a CGU register 230 * @hw: pointer to the HW struct 231 * @addr: Register address to read 232 * @val: storage for register value read 233 * 234 * Read the contents of a register of the Clock Generation Unit. Only 235 * applicable to E822 devices. 236 * 237 * Return: 0 on success, other error codes when failed to read from CGU 238 */ 239 static int ice_read_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 *val) 240 { 241 struct ice_sbq_msg_input cgu_msg = { 242 .opcode = ice_sbq_msg_rd, 243 .dest_dev = cgu, 244 .msg_addr_low = addr 245 }; 246 int err; 247 248 err = ice_sbq_rw_reg(hw, &cgu_msg, ICE_AQ_FLAG_RD); 249 if (err) { 250 ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n", 251 addr, err); 252 return err; 253 } 254 255 *val = cgu_msg.data; 256 257 return 0; 258 } 259 260 /** 261 * ice_write_cgu_reg_e82x - Write a CGU register 262 * @hw: pointer to the HW struct 263 * @addr: Register address to write 264 * @val: value to write into the register 265 * 266 * Write the specified value to a register of the Clock Generation Unit. Only 267 * applicable to E822 devices. 268 * 269 * Return: 0 on success, other error codes when failed to write to CGU 270 */ 271 static int ice_write_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 val) 272 { 273 struct ice_sbq_msg_input cgu_msg = { 274 .opcode = ice_sbq_msg_wr, 275 .dest_dev = cgu, 276 .msg_addr_low = addr, 277 .data = val 278 }; 279 int err; 280 281 err = ice_sbq_rw_reg(hw, &cgu_msg, ICE_AQ_FLAG_RD); 282 if (err) { 283 ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n", 284 addr, err); 285 return err; 286 } 287 288 return err; 289 } 290 291 /** 292 * ice_clk_freq_str - Convert time_ref_freq to string 293 * @clk_freq: Clock frequency 294 * 295 * Return: specified TIME_REF clock frequency converted to a string 296 */ 297 static const char *ice_clk_freq_str(enum ice_time_ref_freq clk_freq) 298 { 299 switch (clk_freq) { 300 case ICE_TIME_REF_FREQ_25_000: 301 return "25 MHz"; 302 case ICE_TIME_REF_FREQ_122_880: 303 return "122.88 MHz"; 304 case ICE_TIME_REF_FREQ_125_000: 305 return "125 MHz"; 306 case ICE_TIME_REF_FREQ_153_600: 307 return "153.6 MHz"; 308 case ICE_TIME_REF_FREQ_156_250: 309 return "156.25 MHz"; 310 case ICE_TIME_REF_FREQ_245_760: 311 return "245.76 MHz"; 312 default: 313 return "Unknown"; 314 } 315 } 316 317 /** 318 * ice_clk_src_str - Convert time_ref_src to string 319 * @clk_src: Clock source 320 * 321 * Return: specified clock source converted to its string name 322 */ 323 static const char *ice_clk_src_str(enum ice_clk_src clk_src) 324 { 325 switch (clk_src) { 326 case ICE_CLK_SRC_TCXO: 327 return "TCXO"; 328 case ICE_CLK_SRC_TIME_REF: 329 return "TIME_REF"; 330 default: 331 return "Unknown"; 332 } 333 } 334 335 /** 336 * ice_cfg_cgu_pll_e82x - Configure the Clock Generation Unit 337 * @hw: pointer to the HW struct 338 * @clk_freq: Clock frequency to program 339 * @clk_src: Clock source to select (TIME_REF, or TCXO) 340 * 341 * Configure the Clock Generation Unit with the desired clock frequency and 342 * time reference, enabling the PLL which drives the PTP hardware clock. 343 * 344 * Return: 345 * * %0 - success 346 * * %-EINVAL - input parameters are incorrect 347 * * %-EBUSY - failed to lock TS PLL 348 * * %other - CGU read/write failure 349 */ 350 static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw, 351 enum ice_time_ref_freq clk_freq, 352 enum ice_clk_src clk_src) 353 { 354 union tspll_ro_bwm_lf bwm_lf; 355 union nac_cgu_dword19 dw19; 356 union nac_cgu_dword22 dw22; 357 union nac_cgu_dword24 dw24; 358 union nac_cgu_dword9 dw9; 359 int err; 360 361 if (clk_freq >= NUM_ICE_TIME_REF_FREQ) { 362 dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n", 363 clk_freq); 364 return -EINVAL; 365 } 366 367 if (clk_src >= NUM_ICE_CLK_SRC) { 368 dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n", 369 clk_src); 370 return -EINVAL; 371 } 372 373 if (clk_src == ICE_CLK_SRC_TCXO && 374 clk_freq != ICE_TIME_REF_FREQ_25_000) { 375 dev_warn(ice_hw_to_dev(hw), 376 "TCXO only supports 25 MHz frequency\n"); 377 return -EINVAL; 378 } 379 380 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val); 381 if (err) 382 return err; 383 384 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val); 385 if (err) 386 return err; 387 388 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val); 389 if (err) 390 return err; 391 392 /* Log the current clock configuration */ 393 ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", 394 dw24.ts_pll_enable ? "enabled" : "disabled", 395 ice_clk_src_str(dw24.time_ref_sel), 396 ice_clk_freq_str(dw9.time_ref_freq_sel), 397 bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked"); 398 399 /* Disable the PLL before changing the clock source or frequency */ 400 if (dw24.ts_pll_enable) { 401 dw24.ts_pll_enable = 0; 402 403 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val); 404 if (err) 405 return err; 406 } 407 408 /* Set the frequency */ 409 dw9.time_ref_freq_sel = clk_freq; 410 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val); 411 if (err) 412 return err; 413 414 /* Configure the TS PLL feedback divisor */ 415 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val); 416 if (err) 417 return err; 418 419 dw19.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div; 420 dw19.tspll_ndivratio = 1; 421 422 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val); 423 if (err) 424 return err; 425 426 /* Configure the TS PLL post divisor */ 427 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val); 428 if (err) 429 return err; 430 431 dw22.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div; 432 dw22.time1588clk_sel_div2 = 0; 433 434 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val); 435 if (err) 436 return err; 437 438 /* Configure the TS PLL pre divisor and clock source */ 439 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val); 440 if (err) 441 return err; 442 443 dw24.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div; 444 dw24.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div; 445 dw24.time_ref_sel = clk_src; 446 447 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val); 448 if (err) 449 return err; 450 451 /* Finally, enable the PLL */ 452 dw24.ts_pll_enable = 1; 453 454 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val); 455 if (err) 456 return err; 457 458 /* Wait to verify if the PLL locks */ 459 usleep_range(1000, 5000); 460 461 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val); 462 if (err) 463 return err; 464 465 if (!bwm_lf.plllock_true_lock_cri) { 466 dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n"); 467 return -EBUSY; 468 } 469 470 /* Log the current clock configuration */ 471 ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", 472 dw24.ts_pll_enable ? "enabled" : "disabled", 473 ice_clk_src_str(dw24.time_ref_sel), 474 ice_clk_freq_str(dw9.time_ref_freq_sel), 475 bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked"); 476 477 return 0; 478 } 479 480 /** 481 * ice_cfg_cgu_pll_e825c - Configure the Clock Generation Unit for E825-C 482 * @hw: pointer to the HW struct 483 * @clk_freq: Clock frequency to program 484 * @clk_src: Clock source to select (TIME_REF, or TCXO) 485 * 486 * Configure the Clock Generation Unit with the desired clock frequency and 487 * time reference, enabling the PLL which drives the PTP hardware clock. 488 * 489 * Return: 490 * * %0 - success 491 * * %-EINVAL - input parameters are incorrect 492 * * %-EBUSY - failed to lock TS PLL 493 * * %other - CGU read/write failure 494 */ 495 static int ice_cfg_cgu_pll_e825c(struct ice_hw *hw, 496 enum ice_time_ref_freq clk_freq, 497 enum ice_clk_src clk_src) 498 { 499 union tspll_ro_lock_e825c ro_lock; 500 union nac_cgu_dword16_e825c dw16; 501 union nac_cgu_dword23_e825c dw23; 502 union nac_cgu_dword19 dw19; 503 union nac_cgu_dword22 dw22; 504 union nac_cgu_dword24 dw24; 505 union nac_cgu_dword9 dw9; 506 int err; 507 508 if (clk_freq >= NUM_ICE_TIME_REF_FREQ) { 509 dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n", 510 clk_freq); 511 return -EINVAL; 512 } 513 514 if (clk_src >= NUM_ICE_CLK_SRC) { 515 dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n", 516 clk_src); 517 return -EINVAL; 518 } 519 520 if (clk_src == ICE_CLK_SRC_TCXO && 521 clk_freq != ICE_TIME_REF_FREQ_156_250) { 522 dev_warn(ice_hw_to_dev(hw), 523 "TCXO only supports 156.25 MHz frequency\n"); 524 return -EINVAL; 525 } 526 527 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val); 528 if (err) 529 return err; 530 531 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val); 532 if (err) 533 return err; 534 535 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD16_E825C, &dw16.val); 536 if (err) 537 return err; 538 539 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val); 540 if (err) 541 return err; 542 543 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val); 544 if (err) 545 return err; 546 547 /* Log the current clock configuration */ 548 ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", 549 dw24.ts_pll_enable ? "enabled" : "disabled", 550 ice_clk_src_str(dw23.time_ref_sel), 551 ice_clk_freq_str(dw9.time_ref_freq_sel), 552 ro_lock.plllock_true_lock_cri ? "locked" : "unlocked"); 553 554 /* Disable the PLL before changing the clock source or frequency */ 555 if (dw23.ts_pll_enable) { 556 dw23.ts_pll_enable = 0; 557 558 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, 559 dw23.val); 560 if (err) 561 return err; 562 } 563 564 /* Set the frequency */ 565 dw9.time_ref_freq_sel = clk_freq; 566 567 /* Enable the correct receiver */ 568 if (clk_src == ICE_CLK_SRC_TCXO) { 569 dw9.time_ref_en = 0; 570 dw9.clk_eref0_en = 1; 571 } else { 572 dw9.time_ref_en = 1; 573 dw9.clk_eref0_en = 0; 574 } 575 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val); 576 if (err) 577 return err; 578 579 /* Choose the referenced frequency */ 580 dw16.tspll_ck_refclkfreq = 581 e825c_cgu_params[clk_freq].tspll_ck_refclkfreq; 582 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD16_E825C, dw16.val); 583 if (err) 584 return err; 585 586 /* Configure the TS PLL feedback divisor */ 587 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val); 588 if (err) 589 return err; 590 591 dw19.tspll_fbdiv_intgr = 592 e825c_cgu_params[clk_freq].tspll_fbdiv_intgr; 593 dw19.tspll_ndivratio = 594 e825c_cgu_params[clk_freq].tspll_ndivratio; 595 596 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val); 597 if (err) 598 return err; 599 600 /* Configure the TS PLL post divisor */ 601 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val); 602 if (err) 603 return err; 604 605 /* These two are constant for E825C */ 606 dw22.time1588clk_div = 5; 607 dw22.time1588clk_sel_div2 = 0; 608 609 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val); 610 if (err) 611 return err; 612 613 /* Configure the TS PLL pre divisor and clock source */ 614 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val); 615 if (err) 616 return err; 617 618 dw23.ref1588_ck_div = 619 e825c_cgu_params[clk_freq].ref1588_ck_div; 620 dw23.time_ref_sel = clk_src; 621 622 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val); 623 if (err) 624 return err; 625 626 dw24.tspll_fbdiv_frac = 627 e825c_cgu_params[clk_freq].tspll_fbdiv_frac; 628 629 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val); 630 if (err) 631 return err; 632 633 /* Finally, enable the PLL */ 634 dw23.ts_pll_enable = 1; 635 636 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val); 637 if (err) 638 return err; 639 640 /* Wait to verify if the PLL locks */ 641 usleep_range(1000, 5000); 642 643 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val); 644 if (err) 645 return err; 646 647 if (!ro_lock.plllock_true_lock_cri) { 648 dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n"); 649 return -EBUSY; 650 } 651 652 /* Log the current clock configuration */ 653 ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", 654 dw24.ts_pll_enable ? "enabled" : "disabled", 655 ice_clk_src_str(dw23.time_ref_sel), 656 ice_clk_freq_str(dw9.time_ref_freq_sel), 657 ro_lock.plllock_true_lock_cri ? "locked" : "unlocked"); 658 659 return 0; 660 } 661 662 #define ICE_ONE_PPS_OUT_AMP_MAX 3 663 664 /** 665 * ice_cgu_cfg_pps_out - Configure 1PPS output from CGU 666 * @hw: pointer to the HW struct 667 * @enable: true to enable 1PPS output, false to disable it 668 * 669 * Return: 0 on success, other negative error code when CGU read/write failed 670 */ 671 int ice_cgu_cfg_pps_out(struct ice_hw *hw, bool enable) 672 { 673 union nac_cgu_dword9 dw9; 674 int err; 675 676 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val); 677 if (err) 678 return err; 679 680 dw9.one_pps_out_en = enable; 681 dw9.one_pps_out_amp = enable * ICE_ONE_PPS_OUT_AMP_MAX; 682 return ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val); 683 } 684 685 /** 686 * ice_cfg_cgu_pll_dis_sticky_bits_e82x - disable TS PLL sticky bits 687 * @hw: pointer to the HW struct 688 * 689 * Configure the Clock Generation Unit TS PLL sticky bits so they don't latch on 690 * losing TS PLL lock, but always show current state. 691 * 692 * Return: 0 on success, other error codes when failed to read/write CGU 693 */ 694 static int ice_cfg_cgu_pll_dis_sticky_bits_e82x(struct ice_hw *hw) 695 { 696 union tspll_cntr_bist_settings cntr_bist; 697 int err; 698 699 err = ice_read_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS, 700 &cntr_bist.val); 701 if (err) 702 return err; 703 704 /* Disable sticky lock detection so lock err reported is accurate */ 705 cntr_bist.i_plllock_sel_0 = 0; 706 cntr_bist.i_plllock_sel_1 = 0; 707 708 return ice_write_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS, 709 cntr_bist.val); 710 } 711 712 /** 713 * ice_cfg_cgu_pll_dis_sticky_bits_e825c - disable TS PLL sticky bits for E825-C 714 * @hw: pointer to the HW struct 715 * 716 * Configure the Clock Generation Unit TS PLL sticky bits so they don't latch on 717 * losing TS PLL lock, but always show current state. 718 * 719 * Return: 0 on success, other error codes when failed to read/write CGU 720 */ 721 static int ice_cfg_cgu_pll_dis_sticky_bits_e825c(struct ice_hw *hw) 722 { 723 union tspll_bw_tdc_e825c bw_tdc; 724 int err; 725 726 err = ice_read_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C, &bw_tdc.val); 727 if (err) 728 return err; 729 730 bw_tdc.i_plllock_sel_1_0 = 0; 731 732 return ice_write_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C, bw_tdc.val); 733 } 734 735 /** 736 * ice_init_cgu_e82x - Initialize CGU with settings from firmware 737 * @hw: pointer to the HW structure 738 * 739 * Initialize the Clock Generation Unit of the E822 device. 740 * 741 * Return: 0 on success, other error codes when failed to read/write/cfg CGU 742 */ 743 static int ice_init_cgu_e82x(struct ice_hw *hw) 744 { 745 struct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info; 746 int err; 747 748 /* Disable sticky lock detection so lock err reported is accurate */ 749 if (ice_is_e825c(hw)) 750 err = ice_cfg_cgu_pll_dis_sticky_bits_e825c(hw); 751 else 752 err = ice_cfg_cgu_pll_dis_sticky_bits_e82x(hw); 753 if (err) 754 return err; 755 756 /* Configure the CGU PLL using the parameters from the function 757 * capabilities. 758 */ 759 if (ice_is_e825c(hw)) 760 err = ice_cfg_cgu_pll_e825c(hw, ts_info->time_ref, 761 (enum ice_clk_src)ts_info->clk_src); 762 else 763 err = ice_cfg_cgu_pll_e82x(hw, ts_info->time_ref, 764 (enum ice_clk_src)ts_info->clk_src); 765 766 return err; 767 } 768 769 /** 770 * ice_ptp_tmr_cmd_to_src_reg - Convert to source timer command value 771 * @hw: pointer to HW struct 772 * @cmd: Timer command 773 * 774 * Return: the source timer command register value for the given PTP timer 775 * command. 776 */ 777 static u32 ice_ptp_tmr_cmd_to_src_reg(struct ice_hw *hw, 778 enum ice_ptp_tmr_cmd cmd) 779 { 780 u32 cmd_val, tmr_idx; 781 782 switch (cmd) { 783 case ICE_PTP_INIT_TIME: 784 cmd_val = GLTSYN_CMD_INIT_TIME; 785 break; 786 case ICE_PTP_INIT_INCVAL: 787 cmd_val = GLTSYN_CMD_INIT_INCVAL; 788 break; 789 case ICE_PTP_ADJ_TIME: 790 cmd_val = GLTSYN_CMD_ADJ_TIME; 791 break; 792 case ICE_PTP_ADJ_TIME_AT_TIME: 793 cmd_val = GLTSYN_CMD_ADJ_INIT_TIME; 794 break; 795 case ICE_PTP_NOP: 796 case ICE_PTP_READ_TIME: 797 cmd_val = GLTSYN_CMD_READ_TIME; 798 break; 799 default: 800 dev_warn(ice_hw_to_dev(hw), 801 "Ignoring unrecognized timer command %u\n", cmd); 802 cmd_val = 0; 803 } 804 805 tmr_idx = ice_get_ptp_src_clock_index(hw); 806 807 return tmr_idx << SEL_CPK_SRC | cmd_val; 808 } 809 810 /** 811 * ice_ptp_tmr_cmd_to_port_reg- Convert to port timer command value 812 * @hw: pointer to HW struct 813 * @cmd: Timer command 814 * 815 * Note that some hardware families use a different command register value for 816 * the PHY ports, while other hardware families use the same register values 817 * as the source timer. 818 * 819 * Return: the PHY port timer command register value for the given PTP timer 820 * command. 821 */ 822 static u32 ice_ptp_tmr_cmd_to_port_reg(struct ice_hw *hw, 823 enum ice_ptp_tmr_cmd cmd) 824 { 825 u32 cmd_val, tmr_idx; 826 827 /* Certain hardware families share the same register values for the 828 * port register and source timer register. 829 */ 830 switch (ice_get_phy_model(hw)) { 831 case ICE_PHY_E810: 832 return ice_ptp_tmr_cmd_to_src_reg(hw, cmd) & TS_CMD_MASK_E810; 833 default: 834 break; 835 } 836 837 switch (cmd) { 838 case ICE_PTP_INIT_TIME: 839 cmd_val = PHY_CMD_INIT_TIME; 840 break; 841 case ICE_PTP_INIT_INCVAL: 842 cmd_val = PHY_CMD_INIT_INCVAL; 843 break; 844 case ICE_PTP_ADJ_TIME: 845 cmd_val = PHY_CMD_ADJ_TIME; 846 break; 847 case ICE_PTP_ADJ_TIME_AT_TIME: 848 cmd_val = PHY_CMD_ADJ_TIME_AT_TIME; 849 break; 850 case ICE_PTP_READ_TIME: 851 cmd_val = PHY_CMD_READ_TIME; 852 break; 853 case ICE_PTP_NOP: 854 cmd_val = 0; 855 break; 856 default: 857 dev_warn(ice_hw_to_dev(hw), 858 "Ignoring unrecognized timer command %u\n", cmd); 859 cmd_val = 0; 860 } 861 862 tmr_idx = ice_get_ptp_src_clock_index(hw); 863 864 return tmr_idx << SEL_PHY_SRC | cmd_val; 865 } 866 867 /** 868 * ice_ptp_src_cmd - Prepare source timer for a timer command 869 * @hw: pointer to HW structure 870 * @cmd: Timer command 871 * 872 * Prepare the source timer for an upcoming timer sync command. 873 */ 874 void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 875 { 876 u32 cmd_val = ice_ptp_tmr_cmd_to_src_reg(hw, cmd); 877 878 wr32(hw, GLTSYN_CMD, cmd_val); 879 } 880 881 /** 882 * ice_ptp_exec_tmr_cmd - Execute all prepared timer commands 883 * @hw: pointer to HW struct 884 * 885 * Write the SYNC_EXEC_CMD bit to the GLTSYN_CMD_SYNC register, and flush the 886 * write immediately. This triggers the hardware to begin executing all of the 887 * source and PHY timer commands synchronously. 888 */ 889 static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw) 890 { 891 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 892 893 guard(spinlock)(&pf->adapter->ptp_gltsyn_time_lock); 894 wr32(hw, GLTSYN_CMD_SYNC, SYNC_EXEC_CMD); 895 ice_flush(hw); 896 } 897 898 /* 56G PHY device functions 899 * 900 * The following functions operate on devices with the ETH 56G PHY. 901 */ 902 903 /** 904 * ice_write_phy_eth56g - Write a PHY port register 905 * @hw: pointer to the HW struct 906 * @phy_idx: PHY index 907 * @addr: PHY register address 908 * @val: Value to write 909 * 910 * Return: 0 on success, other error codes when failed to write to PHY 911 */ 912 static int ice_write_phy_eth56g(struct ice_hw *hw, u8 phy_idx, u32 addr, 913 u32 val) 914 { 915 struct ice_sbq_msg_input phy_msg; 916 int err; 917 918 phy_msg.opcode = ice_sbq_msg_wr; 919 920 phy_msg.msg_addr_low = lower_16_bits(addr); 921 phy_msg.msg_addr_high = upper_16_bits(addr); 922 923 phy_msg.data = val; 924 phy_msg.dest_dev = hw->ptp.phy.eth56g.phy_addr[phy_idx]; 925 926 err = ice_sbq_rw_reg(hw, &phy_msg, ICE_AQ_FLAG_RD); 927 928 if (err) 929 ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n", 930 err); 931 932 return err; 933 } 934 935 /** 936 * ice_read_phy_eth56g - Read a PHY port register 937 * @hw: pointer to the HW struct 938 * @phy_idx: PHY index 939 * @addr: PHY register address 940 * @val: Value to write 941 * 942 * Return: 0 on success, other error codes when failed to read from PHY 943 */ 944 static int ice_read_phy_eth56g(struct ice_hw *hw, u8 phy_idx, u32 addr, 945 u32 *val) 946 { 947 struct ice_sbq_msg_input phy_msg; 948 int err; 949 950 phy_msg.opcode = ice_sbq_msg_rd; 951 952 phy_msg.msg_addr_low = lower_16_bits(addr); 953 phy_msg.msg_addr_high = upper_16_bits(addr); 954 955 phy_msg.data = 0; 956 phy_msg.dest_dev = hw->ptp.phy.eth56g.phy_addr[phy_idx]; 957 958 err = ice_sbq_rw_reg(hw, &phy_msg, ICE_AQ_FLAG_RD); 959 if (err) { 960 ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n", 961 err); 962 return err; 963 } 964 965 *val = phy_msg.data; 966 967 return 0; 968 } 969 970 /** 971 * ice_phy_res_address_eth56g - Calculate a PHY port register address 972 * @port: Port number to be written 973 * @res_type: resource type (register/memory) 974 * @offset: Offset from PHY port register base 975 * @addr: The result address 976 * 977 * Return: 978 * * %0 - success 979 * * %EINVAL - invalid port number or resource type 980 */ 981 static int ice_phy_res_address_eth56g(u8 port, enum eth56g_res_type res_type, 982 u32 offset, u32 *addr) 983 { 984 u8 lane = port % ICE_PORTS_PER_QUAD; 985 u8 phy = ICE_GET_QUAD_NUM(port); 986 987 if (res_type >= NUM_ETH56G_PHY_RES) 988 return -EINVAL; 989 990 *addr = eth56g_phy_res[res_type].base[phy] + 991 lane * eth56g_phy_res[res_type].step + offset; 992 return 0; 993 } 994 995 /** 996 * ice_write_port_eth56g - Write a PHY port register 997 * @hw: pointer to the HW struct 998 * @offset: PHY register offset 999 * @port: Port number 1000 * @val: Value to write 1001 * @res_type: resource type (register/memory) 1002 * 1003 * Return: 1004 * * %0 - success 1005 * * %EINVAL - invalid port number or resource type 1006 * * %other - failed to write to PHY 1007 */ 1008 static int ice_write_port_eth56g(struct ice_hw *hw, u8 port, u32 offset, 1009 u32 val, enum eth56g_res_type res_type) 1010 { 1011 u8 phy_port = port % hw->ptp.ports_per_phy; 1012 u8 phy_idx = port / hw->ptp.ports_per_phy; 1013 u32 addr; 1014 int err; 1015 1016 if (port >= hw->ptp.num_lports) 1017 return -EINVAL; 1018 1019 err = ice_phy_res_address_eth56g(phy_port, res_type, offset, &addr); 1020 if (err) 1021 return err; 1022 1023 return ice_write_phy_eth56g(hw, phy_idx, addr, val); 1024 } 1025 1026 /** 1027 * ice_read_port_eth56g - Read a PHY port register 1028 * @hw: pointer to the HW struct 1029 * @offset: PHY register offset 1030 * @port: Port number 1031 * @val: Value to write 1032 * @res_type: resource type (register/memory) 1033 * 1034 * Return: 1035 * * %0 - success 1036 * * %EINVAL - invalid port number or resource type 1037 * * %other - failed to read from PHY 1038 */ 1039 static int ice_read_port_eth56g(struct ice_hw *hw, u8 port, u32 offset, 1040 u32 *val, enum eth56g_res_type res_type) 1041 { 1042 u8 phy_port = port % hw->ptp.ports_per_phy; 1043 u8 phy_idx = port / hw->ptp.ports_per_phy; 1044 u32 addr; 1045 int err; 1046 1047 if (port >= hw->ptp.num_lports) 1048 return -EINVAL; 1049 1050 err = ice_phy_res_address_eth56g(phy_port, res_type, offset, &addr); 1051 if (err) 1052 return err; 1053 1054 return ice_read_phy_eth56g(hw, phy_idx, addr, val); 1055 } 1056 1057 /** 1058 * ice_write_ptp_reg_eth56g - Write a PHY port register 1059 * @hw: pointer to the HW struct 1060 * @port: Port number to be written 1061 * @offset: Offset from PHY port register base 1062 * @val: Value to write 1063 * 1064 * Return: 1065 * * %0 - success 1066 * * %EINVAL - invalid port number or resource type 1067 * * %other - failed to write to PHY 1068 */ 1069 static int ice_write_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1070 u32 val) 1071 { 1072 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_PTP); 1073 } 1074 1075 /** 1076 * ice_write_mac_reg_eth56g - Write a MAC PHY port register 1077 * parameter 1078 * @hw: pointer to the HW struct 1079 * @port: Port number to be written 1080 * @offset: Offset from PHY port register base 1081 * @val: Value to write 1082 * 1083 * Return: 1084 * * %0 - success 1085 * * %EINVAL - invalid port number or resource type 1086 * * %other - failed to write to PHY 1087 */ 1088 static int ice_write_mac_reg_eth56g(struct ice_hw *hw, u8 port, u32 offset, 1089 u32 val) 1090 { 1091 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_MAC); 1092 } 1093 1094 /** 1095 * ice_write_xpcs_reg_eth56g - Write a PHY port register 1096 * @hw: pointer to the HW struct 1097 * @port: Port number to be written 1098 * @offset: Offset from PHY port register base 1099 * @val: Value to write 1100 * 1101 * Return: 1102 * * %0 - success 1103 * * %EINVAL - invalid port number or resource type 1104 * * %other - failed to write to PHY 1105 */ 1106 static int ice_write_xpcs_reg_eth56g(struct ice_hw *hw, u8 port, u32 offset, 1107 u32 val) 1108 { 1109 return ice_write_port_eth56g(hw, port, offset, val, 1110 ETH56G_PHY_REG_XPCS); 1111 } 1112 1113 /** 1114 * ice_read_ptp_reg_eth56g - Read a PHY port register 1115 * @hw: pointer to the HW struct 1116 * @port: Port number to be read 1117 * @offset: Offset from PHY port register base 1118 * @val: Pointer to the value to read (out param) 1119 * 1120 * Return: 1121 * * %0 - success 1122 * * %EINVAL - invalid port number or resource type 1123 * * %other - failed to read from PHY 1124 */ 1125 static int ice_read_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1126 u32 *val) 1127 { 1128 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_PTP); 1129 } 1130 1131 /** 1132 * ice_read_mac_reg_eth56g - Read a PHY port register 1133 * @hw: pointer to the HW struct 1134 * @port: Port number to be read 1135 * @offset: Offset from PHY port register base 1136 * @val: Pointer to the value to read (out param) 1137 * 1138 * Return: 1139 * * %0 - success 1140 * * %EINVAL - invalid port number or resource type 1141 * * %other - failed to read from PHY 1142 */ 1143 static int ice_read_mac_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1144 u32 *val) 1145 { 1146 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_MAC); 1147 } 1148 1149 /** 1150 * ice_read_gpcs_reg_eth56g - Read a PHY port register 1151 * @hw: pointer to the HW struct 1152 * @port: Port number to be read 1153 * @offset: Offset from PHY port register base 1154 * @val: Pointer to the value to read (out param) 1155 * 1156 * Return: 1157 * * %0 - success 1158 * * %EINVAL - invalid port number or resource type 1159 * * %other - failed to read from PHY 1160 */ 1161 static int ice_read_gpcs_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1162 u32 *val) 1163 { 1164 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_GPCS); 1165 } 1166 1167 /** 1168 * ice_read_port_mem_eth56g - Read a PHY port memory location 1169 * @hw: pointer to the HW struct 1170 * @port: Port number to be read 1171 * @offset: Offset from PHY port register base 1172 * @val: Pointer to the value to read (out param) 1173 * 1174 * Return: 1175 * * %0 - success 1176 * * %EINVAL - invalid port number or resource type 1177 * * %other - failed to read from PHY 1178 */ 1179 static int ice_read_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1180 u32 *val) 1181 { 1182 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_MEM_PTP); 1183 } 1184 1185 /** 1186 * ice_write_port_mem_eth56g - Write a PHY port memory location 1187 * @hw: pointer to the HW struct 1188 * @port: Port number to be read 1189 * @offset: Offset from PHY port register base 1190 * @val: Pointer to the value to read (out param) 1191 * 1192 * Return: 1193 * * %0 - success 1194 * * %EINVAL - invalid port number or resource type 1195 * * %other - failed to write to PHY 1196 */ 1197 static int ice_write_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1198 u32 val) 1199 { 1200 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_MEM_PTP); 1201 } 1202 1203 /** 1204 * ice_is_64b_phy_reg_eth56g - Check if this is a 64bit PHY register 1205 * @low_addr: the low address to check 1206 * @high_addr: on return, contains the high address of the 64bit register 1207 * 1208 * Write the appropriate high register offset to use. 1209 * 1210 * Return: true if the provided low address is one of the known 64bit PHY values 1211 * represented as two 32bit registers, false otherwise. 1212 */ 1213 static bool ice_is_64b_phy_reg_eth56g(u16 low_addr, u16 *high_addr) 1214 { 1215 switch (low_addr) { 1216 case PHY_REG_TX_TIMER_INC_PRE_L: 1217 *high_addr = PHY_REG_TX_TIMER_INC_PRE_U; 1218 return true; 1219 case PHY_REG_RX_TIMER_INC_PRE_L: 1220 *high_addr = PHY_REG_RX_TIMER_INC_PRE_U; 1221 return true; 1222 case PHY_REG_TX_CAPTURE_L: 1223 *high_addr = PHY_REG_TX_CAPTURE_U; 1224 return true; 1225 case PHY_REG_RX_CAPTURE_L: 1226 *high_addr = PHY_REG_RX_CAPTURE_U; 1227 return true; 1228 case PHY_REG_TOTAL_TX_OFFSET_L: 1229 *high_addr = PHY_REG_TOTAL_TX_OFFSET_U; 1230 return true; 1231 case PHY_REG_TOTAL_RX_OFFSET_L: 1232 *high_addr = PHY_REG_TOTAL_RX_OFFSET_U; 1233 return true; 1234 case PHY_REG_TX_MEMORY_STATUS_L: 1235 *high_addr = PHY_REG_TX_MEMORY_STATUS_U; 1236 return true; 1237 default: 1238 return false; 1239 } 1240 } 1241 1242 /** 1243 * ice_is_40b_phy_reg_eth56g - Check if this is a 40bit PHY register 1244 * @low_addr: the low address to check 1245 * @high_addr: on return, contains the high address of the 40bit value 1246 * 1247 * Write the appropriate high register offset to use. 1248 * 1249 * Return: true if the provided low address is one of the known 40bit PHY 1250 * values split into two registers with the lower 8 bits in the low register and 1251 * the upper 32 bits in the high register, false otherwise. 1252 */ 1253 static bool ice_is_40b_phy_reg_eth56g(u16 low_addr, u16 *high_addr) 1254 { 1255 switch (low_addr) { 1256 case PHY_REG_TIMETUS_L: 1257 *high_addr = PHY_REG_TIMETUS_U; 1258 return true; 1259 case PHY_PCS_REF_TUS_L: 1260 *high_addr = PHY_PCS_REF_TUS_U; 1261 return true; 1262 case PHY_PCS_REF_INC_L: 1263 *high_addr = PHY_PCS_REF_INC_U; 1264 return true; 1265 default: 1266 return false; 1267 } 1268 } 1269 1270 /** 1271 * ice_read_64b_phy_reg_eth56g - Read a 64bit value from PHY registers 1272 * @hw: pointer to the HW struct 1273 * @port: PHY port to read from 1274 * @low_addr: offset of the lower register to read from 1275 * @val: on return, the contents of the 64bit value from the PHY registers 1276 * @res_type: resource type 1277 * 1278 * Check if the caller has specified a known 40 bit register offset and read 1279 * the two registers associated with a 40bit value and return it in the val 1280 * pointer. 1281 * 1282 * Return: 1283 * * %0 - success 1284 * * %EINVAL - not a 64 bit register 1285 * * %other - failed to read from PHY 1286 */ 1287 static int ice_read_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, 1288 u64 *val, enum eth56g_res_type res_type) 1289 { 1290 u16 high_addr; 1291 u32 lo, hi; 1292 int err; 1293 1294 if (!ice_is_64b_phy_reg_eth56g(low_addr, &high_addr)) 1295 return -EINVAL; 1296 1297 err = ice_read_port_eth56g(hw, port, low_addr, &lo, res_type); 1298 if (err) { 1299 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register %#08x\n, err %d", 1300 low_addr, err); 1301 return err; 1302 } 1303 1304 err = ice_read_port_eth56g(hw, port, high_addr, &hi, res_type); 1305 if (err) { 1306 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register %#08x\n, err %d", 1307 high_addr, err); 1308 return err; 1309 } 1310 1311 *val = ((u64)hi << 32) | lo; 1312 1313 return 0; 1314 } 1315 1316 /** 1317 * ice_read_64b_ptp_reg_eth56g - Read a 64bit value from PHY registers 1318 * @hw: pointer to the HW struct 1319 * @port: PHY port to read from 1320 * @low_addr: offset of the lower register to read from 1321 * @val: on return, the contents of the 64bit value from the PHY registers 1322 * 1323 * Check if the caller has specified a known 40 bit register offset and read 1324 * the two registers associated with a 40bit value and return it in the val 1325 * pointer. 1326 * 1327 * Return: 1328 * * %0 - success 1329 * * %EINVAL - not a 64 bit register 1330 * * %other - failed to read from PHY 1331 */ 1332 static int ice_read_64b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, 1333 u64 *val) 1334 { 1335 return ice_read_64b_phy_reg_eth56g(hw, port, low_addr, val, 1336 ETH56G_PHY_REG_PTP); 1337 } 1338 1339 /** 1340 * ice_write_40b_phy_reg_eth56g - Write a 40b value to the PHY 1341 * @hw: pointer to the HW struct 1342 * @port: port to write to 1343 * @low_addr: offset of the low register 1344 * @val: 40b value to write 1345 * @res_type: resource type 1346 * 1347 * Check if the caller has specified a known 40 bit register offset and write 1348 * provided 40b value to the two associated registers by splitting it up into 1349 * two chunks, the lower 8 bits and the upper 32 bits. 1350 * 1351 * Return: 1352 * * %0 - success 1353 * * %EINVAL - not a 40 bit register 1354 * * %other - failed to write to PHY 1355 */ 1356 static int ice_write_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port, 1357 u16 low_addr, u64 val, 1358 enum eth56g_res_type res_type) 1359 { 1360 u16 high_addr; 1361 u32 lo, hi; 1362 int err; 1363 1364 if (!ice_is_40b_phy_reg_eth56g(low_addr, &high_addr)) 1365 return -EINVAL; 1366 1367 lo = FIELD_GET(P_REG_40B_LOW_M, val); 1368 hi = (u32)(val >> P_REG_40B_HIGH_S); 1369 1370 err = ice_write_port_eth56g(hw, port, low_addr, lo, res_type); 1371 if (err) { 1372 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 1373 low_addr, err); 1374 return err; 1375 } 1376 1377 err = ice_write_port_eth56g(hw, port, high_addr, hi, res_type); 1378 if (err) { 1379 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 1380 high_addr, err); 1381 return err; 1382 } 1383 1384 return 0; 1385 } 1386 1387 /** 1388 * ice_write_40b_ptp_reg_eth56g - Write a 40b value to the PHY 1389 * @hw: pointer to the HW struct 1390 * @port: port to write to 1391 * @low_addr: offset of the low register 1392 * @val: 40b value to write 1393 * 1394 * Check if the caller has specified a known 40 bit register offset and write 1395 * provided 40b value to the two associated registers by splitting it up into 1396 * two chunks, the lower 8 bits and the upper 32 bits. 1397 * 1398 * Return: 1399 * * %0 - success 1400 * * %EINVAL - not a 40 bit register 1401 * * %other - failed to write to PHY 1402 */ 1403 static int ice_write_40b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, 1404 u16 low_addr, u64 val) 1405 { 1406 return ice_write_40b_phy_reg_eth56g(hw, port, low_addr, val, 1407 ETH56G_PHY_REG_PTP); 1408 } 1409 1410 /** 1411 * ice_write_64b_phy_reg_eth56g - Write a 64bit value to PHY registers 1412 * @hw: pointer to the HW struct 1413 * @port: PHY port to read from 1414 * @low_addr: offset of the lower register to read from 1415 * @val: the contents of the 64bit value to write to PHY 1416 * @res_type: resource type 1417 * 1418 * Check if the caller has specified a known 64 bit register offset and write 1419 * the 64bit value to the two associated 32bit PHY registers. 1420 * 1421 * Return: 1422 * * %0 - success 1423 * * %EINVAL - not a 64 bit register 1424 * * %other - failed to write to PHY 1425 */ 1426 static int ice_write_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, 1427 u16 low_addr, u64 val, 1428 enum eth56g_res_type res_type) 1429 { 1430 u16 high_addr; 1431 u32 lo, hi; 1432 int err; 1433 1434 if (!ice_is_64b_phy_reg_eth56g(low_addr, &high_addr)) 1435 return -EINVAL; 1436 1437 lo = lower_32_bits(val); 1438 hi = upper_32_bits(val); 1439 1440 err = ice_write_port_eth56g(hw, port, low_addr, lo, res_type); 1441 if (err) { 1442 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 1443 low_addr, err); 1444 return err; 1445 } 1446 1447 err = ice_write_port_eth56g(hw, port, high_addr, hi, res_type); 1448 if (err) { 1449 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 1450 high_addr, err); 1451 return err; 1452 } 1453 1454 return 0; 1455 } 1456 1457 /** 1458 * ice_write_64b_ptp_reg_eth56g - Write a 64bit value to PHY registers 1459 * @hw: pointer to the HW struct 1460 * @port: PHY port to read from 1461 * @low_addr: offset of the lower register to read from 1462 * @val: the contents of the 64bit value to write to PHY 1463 * 1464 * Check if the caller has specified a known 64 bit register offset and write 1465 * the 64bit value to the two associated 32bit PHY registers. 1466 * 1467 * Return: 1468 * * %0 - success 1469 * * %EINVAL - not a 64 bit register 1470 * * %other - failed to write to PHY 1471 */ 1472 static int ice_write_64b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, 1473 u16 low_addr, u64 val) 1474 { 1475 return ice_write_64b_phy_reg_eth56g(hw, port, low_addr, val, 1476 ETH56G_PHY_REG_PTP); 1477 } 1478 1479 /** 1480 * ice_read_ptp_tstamp_eth56g - Read a PHY timestamp out of the port memory 1481 * @hw: pointer to the HW struct 1482 * @port: the port to read from 1483 * @idx: the timestamp index to read 1484 * @tstamp: on return, the 40bit timestamp value 1485 * 1486 * Read a 40bit timestamp value out of the two associated entries in the 1487 * port memory block of the internal PHYs of the 56G devices. 1488 * 1489 * Return: 1490 * * %0 - success 1491 * * %other - failed to read from PHY 1492 */ 1493 static int ice_read_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx, 1494 u64 *tstamp) 1495 { 1496 u16 lo_addr, hi_addr; 1497 u32 lo, hi; 1498 int err; 1499 1500 lo_addr = (u16)PHY_TSTAMP_L(idx); 1501 hi_addr = (u16)PHY_TSTAMP_U(idx); 1502 1503 err = ice_read_port_mem_eth56g(hw, port, lo_addr, &lo); 1504 if (err) { 1505 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 1506 err); 1507 return err; 1508 } 1509 1510 err = ice_read_port_mem_eth56g(hw, port, hi_addr, &hi); 1511 if (err) { 1512 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 1513 err); 1514 return err; 1515 } 1516 1517 /* For 56G based internal PHYs, the timestamp is reported with the 1518 * lower 8 bits in the low register, and the upper 32 bits in the high 1519 * register. 1520 */ 1521 *tstamp = ((u64)hi) << TS_PHY_HIGH_S | ((u64)lo & TS_PHY_LOW_M); 1522 1523 return 0; 1524 } 1525 1526 /** 1527 * ice_clear_ptp_tstamp_eth56g - Clear a timestamp from the quad block 1528 * @hw: pointer to the HW struct 1529 * @port: the quad to read from 1530 * @idx: the timestamp index to reset 1531 * 1532 * Read and then forcibly clear the timestamp index to ensure the valid bit is 1533 * cleared and the timestamp status bit is reset in the PHY port memory of 1534 * internal PHYs of the 56G devices. 1535 * 1536 * To directly clear the contents of the timestamp block entirely, discarding 1537 * all timestamp data at once, software should instead use 1538 * ice_ptp_reset_ts_memory_quad_eth56g(). 1539 * 1540 * This function should only be called on an idx whose bit is set according to 1541 * ice_get_phy_tx_tstamp_ready(). 1542 * 1543 * Return: 1544 * * %0 - success 1545 * * %other - failed to write to PHY 1546 */ 1547 static int ice_clear_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx) 1548 { 1549 u64 unused_tstamp; 1550 u16 lo_addr; 1551 int err; 1552 1553 /* Read the timestamp register to ensure the timestamp status bit is 1554 * cleared. 1555 */ 1556 err = ice_read_ptp_tstamp_eth56g(hw, port, idx, &unused_tstamp); 1557 if (err) { 1558 ice_debug(hw, ICE_DBG_PTP, "Failed to read the PHY timestamp register for port %u, idx %u, err %d\n", 1559 port, idx, err); 1560 } 1561 1562 lo_addr = (u16)PHY_TSTAMP_L(idx); 1563 1564 err = ice_write_port_mem_eth56g(hw, port, lo_addr, 0); 1565 if (err) { 1566 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for port %u, idx %u, err %d\n", 1567 port, idx, err); 1568 return err; 1569 } 1570 1571 return 0; 1572 } 1573 1574 /** 1575 * ice_ptp_reset_ts_memory_eth56g - Clear all timestamps from the port block 1576 * @hw: pointer to the HW struct 1577 */ 1578 static void ice_ptp_reset_ts_memory_eth56g(struct ice_hw *hw) 1579 { 1580 unsigned int port; 1581 1582 for (port = 0; port < hw->ptp.num_lports; port++) { 1583 ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L, 1584 0); 1585 ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_U, 1586 0); 1587 } 1588 } 1589 1590 /** 1591 * ice_ptp_prep_port_time_eth56g - Prepare one PHY port with initial time 1592 * @hw: pointer to the HW struct 1593 * @port: port number 1594 * @time: time to initialize the PHY port clocks to 1595 * 1596 * Write a new initial time value into registers of a specific PHY port. 1597 * 1598 * Return: 1599 * * %0 - success 1600 * * %other - failed to write to PHY 1601 */ 1602 static int ice_ptp_prep_port_time_eth56g(struct ice_hw *hw, u8 port, 1603 u64 time) 1604 { 1605 int err; 1606 1607 /* Tx case */ 1608 err = ice_write_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_L, 1609 time); 1610 if (err) 1611 return err; 1612 1613 /* Rx case */ 1614 return ice_write_64b_ptp_reg_eth56g(hw, port, 1615 PHY_REG_RX_TIMER_INC_PRE_L, time); 1616 } 1617 1618 /** 1619 * ice_ptp_prep_phy_time_eth56g - Prepare PHY port with initial time 1620 * @hw: pointer to the HW struct 1621 * @time: Time to initialize the PHY port clocks to 1622 * 1623 * Program the PHY port registers with a new initial time value. The port 1624 * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync 1625 * command. The time value is the upper 32 bits of the PHY timer, usually in 1626 * units of nominal nanoseconds. 1627 * 1628 * Return: 1629 * * %0 - success 1630 * * %other - failed to write to PHY 1631 */ 1632 static int ice_ptp_prep_phy_time_eth56g(struct ice_hw *hw, u32 time) 1633 { 1634 u64 phy_time; 1635 u8 port; 1636 1637 /* The time represents the upper 32 bits of the PHY timer, so we need 1638 * to shift to account for this when programming. 1639 */ 1640 phy_time = (u64)time << 32; 1641 1642 for (port = 0; port < hw->ptp.num_lports; port++) { 1643 int err; 1644 1645 err = ice_ptp_prep_port_time_eth56g(hw, port, phy_time); 1646 if (err) { 1647 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n", 1648 port, err); 1649 return err; 1650 } 1651 } 1652 1653 return 0; 1654 } 1655 1656 /** 1657 * ice_ptp_prep_port_adj_eth56g - Prepare a single port for time adjust 1658 * @hw: pointer to HW struct 1659 * @port: Port number to be programmed 1660 * @time: time in cycles to adjust the port clocks 1661 * 1662 * Program the port for an atomic adjustment by writing the Tx and Rx timer 1663 * registers. The atomic adjustment won't be completed until the driver issues 1664 * an ICE_PTP_ADJ_TIME command. 1665 * 1666 * Note that time is not in units of nanoseconds. It is in clock time 1667 * including the lower sub-nanosecond portion of the port timer. 1668 * 1669 * Negative adjustments are supported using 2s complement arithmetic. 1670 * 1671 * Return: 1672 * * %0 - success 1673 * * %other - failed to write to PHY 1674 */ 1675 static int ice_ptp_prep_port_adj_eth56g(struct ice_hw *hw, u8 port, s64 time) 1676 { 1677 u32 l_time, u_time; 1678 int err; 1679 1680 l_time = lower_32_bits(time); 1681 u_time = upper_32_bits(time); 1682 1683 /* Tx case */ 1684 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_L, 1685 l_time); 1686 if (err) 1687 goto exit_err; 1688 1689 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_U, 1690 u_time); 1691 if (err) 1692 goto exit_err; 1693 1694 /* Rx case */ 1695 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TIMER_INC_PRE_L, 1696 l_time); 1697 if (err) 1698 goto exit_err; 1699 1700 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TIMER_INC_PRE_U, 1701 u_time); 1702 if (err) 1703 goto exit_err; 1704 1705 return 0; 1706 1707 exit_err: 1708 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n", 1709 port, err); 1710 return err; 1711 } 1712 1713 /** 1714 * ice_ptp_prep_phy_adj_eth56g - Prep PHY ports for a time adjustment 1715 * @hw: pointer to HW struct 1716 * @adj: adjustment in nanoseconds 1717 * 1718 * Prepare the PHY ports for an atomic time adjustment by programming the PHY 1719 * Tx and Rx port registers. The actual adjustment is completed by issuing an 1720 * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command. 1721 * 1722 * Return: 1723 * * %0 - success 1724 * * %other - failed to write to PHY 1725 */ 1726 static int ice_ptp_prep_phy_adj_eth56g(struct ice_hw *hw, s32 adj) 1727 { 1728 s64 cycles; 1729 u8 port; 1730 1731 /* The port clock supports adjustment of the sub-nanosecond portion of 1732 * the clock (lowest 32 bits). We shift the provided adjustment in 1733 * nanoseconds by 32 to calculate the appropriate adjustment to program 1734 * into the PHY ports. 1735 */ 1736 cycles = (s64)adj << 32; 1737 1738 for (port = 0; port < hw->ptp.num_lports; port++) { 1739 int err; 1740 1741 err = ice_ptp_prep_port_adj_eth56g(hw, port, cycles); 1742 if (err) 1743 return err; 1744 } 1745 1746 return 0; 1747 } 1748 1749 /** 1750 * ice_ptp_prep_phy_incval_eth56g - Prepare PHY ports for time adjustment 1751 * @hw: pointer to HW struct 1752 * @incval: new increment value to prepare 1753 * 1754 * Prepare each of the PHY ports for a new increment value by programming the 1755 * port's TIMETUS registers. The new increment value will be updated after 1756 * issuing an ICE_PTP_INIT_INCVAL command. 1757 * 1758 * Return: 1759 * * %0 - success 1760 * * %other - failed to write to PHY 1761 */ 1762 static int ice_ptp_prep_phy_incval_eth56g(struct ice_hw *hw, u64 incval) 1763 { 1764 u8 port; 1765 1766 for (port = 0; port < hw->ptp.num_lports; port++) { 1767 int err; 1768 1769 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_REG_TIMETUS_L, 1770 incval); 1771 if (err) { 1772 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n", 1773 port, err); 1774 return err; 1775 } 1776 } 1777 1778 return 0; 1779 } 1780 1781 /** 1782 * ice_ptp_read_port_capture_eth56g - Read a port's local time capture 1783 * @hw: pointer to HW struct 1784 * @port: Port number to read 1785 * @tx_ts: on return, the Tx port time capture 1786 * @rx_ts: on return, the Rx port time capture 1787 * 1788 * Read the port's Tx and Rx local time capture values. 1789 * 1790 * Return: 1791 * * %0 - success 1792 * * %other - failed to read from PHY 1793 */ 1794 static int ice_ptp_read_port_capture_eth56g(struct ice_hw *hw, u8 port, 1795 u64 *tx_ts, u64 *rx_ts) 1796 { 1797 int err; 1798 1799 /* Tx case */ 1800 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_CAPTURE_L, 1801 tx_ts); 1802 if (err) { 1803 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n", 1804 err); 1805 return err; 1806 } 1807 1808 ice_debug(hw, ICE_DBG_PTP, "tx_init = %#016llx\n", *tx_ts); 1809 1810 /* Rx case */ 1811 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_RX_CAPTURE_L, 1812 rx_ts); 1813 if (err) { 1814 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n", 1815 err); 1816 return err; 1817 } 1818 1819 ice_debug(hw, ICE_DBG_PTP, "rx_init = %#016llx\n", *rx_ts); 1820 1821 return 0; 1822 } 1823 1824 /** 1825 * ice_ptp_write_port_cmd_eth56g - Prepare a single PHY port for a timer command 1826 * @hw: pointer to HW struct 1827 * @port: Port to which cmd has to be sent 1828 * @cmd: Command to be sent to the port 1829 * 1830 * Prepare the requested port for an upcoming timer sync command. 1831 * 1832 * Return: 1833 * * %0 - success 1834 * * %other - failed to write to PHY 1835 */ 1836 static int ice_ptp_write_port_cmd_eth56g(struct ice_hw *hw, u8 port, 1837 enum ice_ptp_tmr_cmd cmd) 1838 { 1839 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 1840 int err; 1841 1842 /* Tx case */ 1843 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TMR_CMD, val); 1844 if (err) { 1845 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n", 1846 err); 1847 return err; 1848 } 1849 1850 /* Rx case */ 1851 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TMR_CMD, val); 1852 if (err) { 1853 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n", 1854 err); 1855 return err; 1856 } 1857 1858 return 0; 1859 } 1860 1861 /** 1862 * ice_phy_get_speed_eth56g - Get link speed based on PHY link type 1863 * @li: pointer to link information struct 1864 * 1865 * Return: simplified ETH56G PHY speed 1866 */ 1867 static enum ice_eth56g_link_spd 1868 ice_phy_get_speed_eth56g(struct ice_link_status *li) 1869 { 1870 u16 speed = ice_get_link_speed_based_on_phy_type(li->phy_type_low, 1871 li->phy_type_high); 1872 1873 switch (speed) { 1874 case ICE_AQ_LINK_SPEED_1000MB: 1875 return ICE_ETH56G_LNK_SPD_1G; 1876 case ICE_AQ_LINK_SPEED_2500MB: 1877 return ICE_ETH56G_LNK_SPD_2_5G; 1878 case ICE_AQ_LINK_SPEED_10GB: 1879 return ICE_ETH56G_LNK_SPD_10G; 1880 case ICE_AQ_LINK_SPEED_25GB: 1881 return ICE_ETH56G_LNK_SPD_25G; 1882 case ICE_AQ_LINK_SPEED_40GB: 1883 return ICE_ETH56G_LNK_SPD_40G; 1884 case ICE_AQ_LINK_SPEED_50GB: 1885 switch (li->phy_type_low) { 1886 case ICE_PHY_TYPE_LOW_50GBASE_SR: 1887 case ICE_PHY_TYPE_LOW_50GBASE_FR: 1888 case ICE_PHY_TYPE_LOW_50GBASE_LR: 1889 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 1890 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 1891 case ICE_PHY_TYPE_LOW_50G_AUI1: 1892 return ICE_ETH56G_LNK_SPD_50G; 1893 default: 1894 return ICE_ETH56G_LNK_SPD_50G2; 1895 } 1896 case ICE_AQ_LINK_SPEED_100GB: 1897 if (li->phy_type_high || 1898 li->phy_type_low == ICE_PHY_TYPE_LOW_100GBASE_SR2) 1899 return ICE_ETH56G_LNK_SPD_100G2; 1900 else 1901 return ICE_ETH56G_LNK_SPD_100G; 1902 default: 1903 return ICE_ETH56G_LNK_SPD_1G; 1904 } 1905 } 1906 1907 /** 1908 * ice_phy_cfg_parpcs_eth56g - Configure TUs per PAR/PCS clock cycle 1909 * @hw: pointer to the HW struct 1910 * @port: port to configure 1911 * 1912 * Configure the number of TUs for the PAR and PCS clocks used as part of the 1913 * timestamp calibration process. 1914 * 1915 * Return: 1916 * * %0 - success 1917 * * %other - PHY read/write failed 1918 */ 1919 static int ice_phy_cfg_parpcs_eth56g(struct ice_hw *hw, u8 port) 1920 { 1921 u8 port_blk = port & ~(ICE_PORTS_PER_QUAD - 1); 1922 u32 val; 1923 int err; 1924 1925 err = ice_write_xpcs_reg_eth56g(hw, port, PHY_VENDOR_TXLANE_THRESH, 1926 ICE_ETH56G_NOMINAL_THRESH4); 1927 if (err) { 1928 ice_debug(hw, ICE_DBG_PTP, "Failed to read VENDOR_TXLANE_THRESH, status: %d", 1929 err); 1930 return err; 1931 } 1932 1933 switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) { 1934 case ICE_ETH56G_LNK_SPD_1G: 1935 case ICE_ETH56G_LNK_SPD_2_5G: 1936 err = ice_read_ptp_reg_eth56g(hw, port_blk, 1937 PHY_GPCS_CONFIG_REG0, &val); 1938 if (err) { 1939 ice_debug(hw, ICE_DBG_PTP, "Failed to read PHY_GPCS_CONFIG_REG0, status: %d", 1940 err); 1941 return err; 1942 } 1943 1944 val &= ~PHY_GPCS_CONFIG_REG0_TX_THR_M; 1945 val |= FIELD_PREP(PHY_GPCS_CONFIG_REG0_TX_THR_M, 1946 ICE_ETH56G_NOMINAL_TX_THRESH); 1947 1948 err = ice_write_ptp_reg_eth56g(hw, port_blk, 1949 PHY_GPCS_CONFIG_REG0, val); 1950 if (err) { 1951 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_GPCS_CONFIG_REG0, status: %d", 1952 err); 1953 return err; 1954 } 1955 break; 1956 default: 1957 break; 1958 } 1959 1960 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_PCS_REF_TUS_L, 1961 ICE_ETH56G_NOMINAL_PCS_REF_TUS); 1962 if (err) { 1963 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_PCS_REF_TUS, status: %d", 1964 err); 1965 return err; 1966 } 1967 1968 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_PCS_REF_INC_L, 1969 ICE_ETH56G_NOMINAL_PCS_REF_INC); 1970 if (err) { 1971 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_PCS_REF_INC, status: %d", 1972 err); 1973 return err; 1974 } 1975 1976 return 0; 1977 } 1978 1979 /** 1980 * ice_phy_cfg_ptp_1step_eth56g - Configure 1-step PTP settings 1981 * @hw: Pointer to the HW struct 1982 * @port: Port to configure 1983 * 1984 * Return: 1985 * * %0 - success 1986 * * %other - PHY read/write failed 1987 */ 1988 int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port) 1989 { 1990 u8 port_blk = port & ~(ICE_PORTS_PER_QUAD - 1); 1991 u8 blk_port = port & (ICE_PORTS_PER_QUAD - 1); 1992 bool enable, sfd_ena; 1993 u32 val, peer_delay; 1994 int err; 1995 1996 enable = hw->ptp.phy.eth56g.onestep_ena; 1997 peer_delay = hw->ptp.phy.eth56g.peer_delay; 1998 sfd_ena = hw->ptp.phy.eth56g.sfd_ena; 1999 2000 /* PHY_PTP_1STEP_CONFIG */ 2001 err = ice_read_ptp_reg_eth56g(hw, port_blk, PHY_PTP_1STEP_CONFIG, &val); 2002 if (err) 2003 return err; 2004 2005 if (enable) 2006 val |= blk_port; 2007 else 2008 val &= ~blk_port; 2009 2010 val &= ~(PHY_PTP_1STEP_T1S_UP64_M | PHY_PTP_1STEP_T1S_DELTA_M); 2011 2012 err = ice_write_ptp_reg_eth56g(hw, port_blk, PHY_PTP_1STEP_CONFIG, val); 2013 if (err) 2014 return err; 2015 2016 /* PHY_PTP_1STEP_PEER_DELAY */ 2017 val = FIELD_PREP(PHY_PTP_1STEP_PD_DELAY_M, peer_delay); 2018 if (peer_delay) 2019 val |= PHY_PTP_1STEP_PD_ADD_PD_M; 2020 val |= PHY_PTP_1STEP_PD_DLY_V_M; 2021 err = ice_write_ptp_reg_eth56g(hw, port_blk, 2022 PHY_PTP_1STEP_PEER_DELAY(blk_port), val); 2023 if (err) 2024 return err; 2025 2026 val &= ~PHY_PTP_1STEP_PD_DLY_V_M; 2027 err = ice_write_ptp_reg_eth56g(hw, port_blk, 2028 PHY_PTP_1STEP_PEER_DELAY(blk_port), val); 2029 if (err) 2030 return err; 2031 2032 /* PHY_MAC_XIF_MODE */ 2033 err = ice_read_mac_reg_eth56g(hw, port, PHY_MAC_XIF_MODE, &val); 2034 if (err) 2035 return err; 2036 2037 val &= ~(PHY_MAC_XIF_1STEP_ENA_M | PHY_MAC_XIF_TS_BIN_MODE_M | 2038 PHY_MAC_XIF_TS_SFD_ENA_M | PHY_MAC_XIF_GMII_TS_SEL_M); 2039 2040 switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) { 2041 case ICE_ETH56G_LNK_SPD_1G: 2042 case ICE_ETH56G_LNK_SPD_2_5G: 2043 val |= PHY_MAC_XIF_GMII_TS_SEL_M; 2044 break; 2045 default: 2046 break; 2047 } 2048 2049 val |= FIELD_PREP(PHY_MAC_XIF_1STEP_ENA_M, enable) | 2050 FIELD_PREP(PHY_MAC_XIF_TS_BIN_MODE_M, enable) | 2051 FIELD_PREP(PHY_MAC_XIF_TS_SFD_ENA_M, sfd_ena); 2052 2053 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_XIF_MODE, val); 2054 } 2055 2056 /** 2057 * mul_u32_u32_fx_q9 - Multiply two u32 fixed point Q9 values 2058 * @a: multiplier value 2059 * @b: multiplicand value 2060 * 2061 * Return: result of multiplication 2062 */ 2063 static u32 mul_u32_u32_fx_q9(u32 a, u32 b) 2064 { 2065 return (u32)(((u64)a * b) >> ICE_ETH56G_MAC_CFG_FRAC_W); 2066 } 2067 2068 /** 2069 * add_u32_u32_fx - Add two u32 fixed point values and discard overflow 2070 * @a: first value 2071 * @b: second value 2072 * 2073 * Return: result of addition 2074 */ 2075 static u32 add_u32_u32_fx(u32 a, u32 b) 2076 { 2077 return lower_32_bits(((u64)a + b)); 2078 } 2079 2080 /** 2081 * ice_ptp_calc_bitslip_eth56g - Calculate bitslip value 2082 * @hw: pointer to the HW struct 2083 * @port: port to configure 2084 * @bs: bitslip multiplier 2085 * @fc: FC-FEC enabled 2086 * @rs: RS-FEC enabled 2087 * @spd: link speed 2088 * 2089 * Return: calculated bitslip value 2090 */ 2091 static u32 ice_ptp_calc_bitslip_eth56g(struct ice_hw *hw, u8 port, u32 bs, 2092 bool fc, bool rs, 2093 enum ice_eth56g_link_spd spd) 2094 { 2095 u8 port_offset = port & (ICE_PORTS_PER_QUAD - 1); 2096 u8 port_blk = port & ~(ICE_PORTS_PER_QUAD - 1); 2097 u32 bitslip; 2098 int err; 2099 2100 if (!bs || rs) 2101 return 0; 2102 2103 if (spd == ICE_ETH56G_LNK_SPD_1G || spd == ICE_ETH56G_LNK_SPD_2_5G) 2104 err = ice_read_gpcs_reg_eth56g(hw, port, PHY_GPCS_BITSLIP, 2105 &bitslip); 2106 else 2107 err = ice_read_ptp_reg_eth56g(hw, port_blk, 2108 PHY_REG_SD_BIT_SLIP(port_offset), 2109 &bitslip); 2110 if (err) 2111 return 0; 2112 2113 if (spd == ICE_ETH56G_LNK_SPD_1G && !bitslip) { 2114 /* Bitslip register value of 0 corresponds to 10 so substitute 2115 * it for calculations 2116 */ 2117 bitslip = 10; 2118 } else if (spd == ICE_ETH56G_LNK_SPD_10G || 2119 spd == ICE_ETH56G_LNK_SPD_25G) { 2120 if (fc) 2121 bitslip = bitslip * 2 + 32; 2122 else 2123 bitslip = (u32)((s32)bitslip * -1 + 20); 2124 } 2125 2126 bitslip <<= ICE_ETH56G_MAC_CFG_FRAC_W; 2127 return mul_u32_u32_fx_q9(bitslip, bs); 2128 } 2129 2130 /** 2131 * ice_ptp_calc_deskew_eth56g - Calculate deskew value 2132 * @hw: pointer to the HW struct 2133 * @port: port to configure 2134 * @ds: deskew multiplier 2135 * @rs: RS-FEC enabled 2136 * @spd: link speed 2137 * 2138 * Return: calculated deskew value 2139 */ 2140 static u32 ice_ptp_calc_deskew_eth56g(struct ice_hw *hw, u8 port, u32 ds, 2141 bool rs, enum ice_eth56g_link_spd spd) 2142 { 2143 u32 deskew_i, deskew_f; 2144 int err; 2145 2146 if (!ds) 2147 return 0; 2148 2149 read_poll_timeout(ice_read_ptp_reg_eth56g, err, 2150 FIELD_GET(PHY_REG_DESKEW_0_VALID, deskew_i), 500, 2151 50 * USEC_PER_MSEC, false, hw, port, PHY_REG_DESKEW_0, 2152 &deskew_i); 2153 if (err) 2154 return err; 2155 2156 deskew_f = FIELD_GET(PHY_REG_DESKEW_0_RLEVEL_FRAC, deskew_i); 2157 deskew_i = FIELD_GET(PHY_REG_DESKEW_0_RLEVEL, deskew_i); 2158 2159 if (rs && spd == ICE_ETH56G_LNK_SPD_50G2) 2160 ds = 0x633; /* 3.1 */ 2161 else if (rs && spd == ICE_ETH56G_LNK_SPD_100G) 2162 ds = 0x31b; /* 1.552 */ 2163 2164 deskew_i = FIELD_PREP(ICE_ETH56G_MAC_CFG_RX_OFFSET_INT, deskew_i); 2165 /* Shift 3 fractional bits to the end of the integer part */ 2166 deskew_f <<= ICE_ETH56G_MAC_CFG_FRAC_W - PHY_REG_DESKEW_0_RLEVEL_FRAC_W; 2167 return mul_u32_u32_fx_q9(deskew_i | deskew_f, ds); 2168 } 2169 2170 /** 2171 * ice_phy_set_offsets_eth56g - Set Tx/Rx offset values 2172 * @hw: pointer to the HW struct 2173 * @port: port to configure 2174 * @spd: link speed 2175 * @cfg: structure to store output values 2176 * @fc: FC-FEC enabled 2177 * @rs: RS-FEC enabled 2178 * 2179 * Return: 2180 * * %0 - success 2181 * * %other - failed to write to PHY 2182 */ 2183 static int ice_phy_set_offsets_eth56g(struct ice_hw *hw, u8 port, 2184 enum ice_eth56g_link_spd spd, 2185 const struct ice_eth56g_mac_reg_cfg *cfg, 2186 bool fc, bool rs) 2187 { 2188 u32 rx_offset, tx_offset, bs_ds; 2189 bool onestep, sfd; 2190 2191 onestep = hw->ptp.phy.eth56g.onestep_ena; 2192 sfd = hw->ptp.phy.eth56g.sfd_ena; 2193 bs_ds = cfg->rx_offset.bs_ds; 2194 2195 if (fc) 2196 rx_offset = cfg->rx_offset.fc; 2197 else if (rs) 2198 rx_offset = cfg->rx_offset.rs; 2199 else 2200 rx_offset = cfg->rx_offset.no_fec; 2201 2202 rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.serdes); 2203 if (sfd) 2204 rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.sfd); 2205 2206 if (spd < ICE_ETH56G_LNK_SPD_40G) 2207 bs_ds = ice_ptp_calc_bitslip_eth56g(hw, port, bs_ds, fc, rs, 2208 spd); 2209 else 2210 bs_ds = ice_ptp_calc_deskew_eth56g(hw, port, bs_ds, rs, spd); 2211 rx_offset = add_u32_u32_fx(rx_offset, bs_ds); 2212 rx_offset &= ICE_ETH56G_MAC_CFG_RX_OFFSET_INT | 2213 ICE_ETH56G_MAC_CFG_RX_OFFSET_FRAC; 2214 2215 if (fc) 2216 tx_offset = cfg->tx_offset.fc; 2217 else if (rs) 2218 tx_offset = cfg->tx_offset.rs; 2219 else 2220 tx_offset = cfg->tx_offset.no_fec; 2221 tx_offset += cfg->tx_offset.serdes + cfg->tx_offset.sfd * sfd + 2222 cfg->tx_offset.onestep * onestep; 2223 2224 ice_write_mac_reg_eth56g(hw, port, PHY_MAC_RX_OFFSET, rx_offset); 2225 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TX_OFFSET, tx_offset); 2226 } 2227 2228 /** 2229 * ice_phy_cfg_mac_eth56g - Configure MAC for PTP 2230 * @hw: Pointer to the HW struct 2231 * @port: Port to configure 2232 * 2233 * Return: 2234 * * %0 - success 2235 * * %other - failed to write to PHY 2236 */ 2237 static int ice_phy_cfg_mac_eth56g(struct ice_hw *hw, u8 port) 2238 { 2239 const struct ice_eth56g_mac_reg_cfg *cfg; 2240 enum ice_eth56g_link_spd spd; 2241 struct ice_link_status *li; 2242 bool fc = false; 2243 bool rs = false; 2244 bool onestep; 2245 u32 val; 2246 int err; 2247 2248 onestep = hw->ptp.phy.eth56g.onestep_ena; 2249 li = &hw->port_info->phy.link_info; 2250 spd = ice_phy_get_speed_eth56g(li); 2251 if (!!(li->an_info & ICE_AQ_FEC_EN)) { 2252 if (spd == ICE_ETH56G_LNK_SPD_10G) { 2253 fc = true; 2254 } else { 2255 fc = !!(li->fec_info & ICE_AQ_LINK_25G_KR_FEC_EN); 2256 rs = !!(li->fec_info & ~ICE_AQ_LINK_25G_KR_FEC_EN); 2257 } 2258 } 2259 cfg = ð56g_mac_cfg[spd]; 2260 2261 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_RX_MODULO, 0); 2262 if (err) 2263 return err; 2264 2265 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TX_MODULO, 0); 2266 if (err) 2267 return err; 2268 2269 val = FIELD_PREP(PHY_MAC_TSU_CFG_TX_MODE_M, 2270 cfg->tx_mode.def + rs * cfg->tx_mode.rs) | 2271 FIELD_PREP(PHY_MAC_TSU_CFG_TX_MII_MK_DLY_M, cfg->tx_mk_dly) | 2272 FIELD_PREP(PHY_MAC_TSU_CFG_TX_MII_CW_DLY_M, 2273 cfg->tx_cw_dly.def + 2274 onestep * cfg->tx_cw_dly.onestep) | 2275 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MODE_M, 2276 cfg->rx_mode.def + rs * cfg->rx_mode.rs) | 2277 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MII_MK_DLY_M, 2278 cfg->rx_mk_dly.def + rs * cfg->rx_mk_dly.rs) | 2279 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MII_CW_DLY_M, 2280 cfg->rx_cw_dly.def + rs * cfg->rx_cw_dly.rs) | 2281 FIELD_PREP(PHY_MAC_TSU_CFG_BLKS_PER_CLK_M, cfg->blks_per_clk); 2282 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TSU_CONFIG, val); 2283 if (err) 2284 return err; 2285 2286 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_BLOCKTIME, 2287 cfg->blktime); 2288 if (err) 2289 return err; 2290 2291 err = ice_phy_set_offsets_eth56g(hw, port, spd, cfg, fc, rs); 2292 if (err) 2293 return err; 2294 2295 if (spd == ICE_ETH56G_LNK_SPD_25G && !rs) 2296 val = 0; 2297 else 2298 val = cfg->mktime; 2299 2300 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_MARKERTIME, val); 2301 } 2302 2303 /** 2304 * ice_phy_cfg_intr_eth56g - Configure TX timestamp interrupt 2305 * @hw: pointer to the HW struct 2306 * @port: the timestamp port 2307 * @ena: enable or disable interrupt 2308 * @threshold: interrupt threshold 2309 * 2310 * Configure TX timestamp interrupt for the specified port 2311 * 2312 * Return: 2313 * * %0 - success 2314 * * %other - PHY read/write failed 2315 */ 2316 int ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold) 2317 { 2318 int err; 2319 u32 val; 2320 2321 err = ice_read_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, &val); 2322 if (err) 2323 return err; 2324 2325 if (ena) { 2326 val |= PHY_TS_INT_CONFIG_ENA_M; 2327 val &= ~PHY_TS_INT_CONFIG_THRESHOLD_M; 2328 val |= FIELD_PREP(PHY_TS_INT_CONFIG_THRESHOLD_M, threshold); 2329 } else { 2330 val &= ~PHY_TS_INT_CONFIG_ENA_M; 2331 } 2332 2333 return ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, val); 2334 } 2335 2336 /** 2337 * ice_read_phy_and_phc_time_eth56g - Simultaneously capture PHC and PHY time 2338 * @hw: pointer to the HW struct 2339 * @port: the PHY port to read 2340 * @phy_time: on return, the 64bit PHY timer value 2341 * @phc_time: on return, the lower 64bits of PHC time 2342 * 2343 * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY 2344 * and PHC timer values. 2345 * 2346 * Return: 2347 * * %0 - success 2348 * * %other - PHY read/write failed 2349 */ 2350 static int ice_read_phy_and_phc_time_eth56g(struct ice_hw *hw, u8 port, 2351 u64 *phy_time, u64 *phc_time) 2352 { 2353 u64 tx_time, rx_time; 2354 u32 zo, lo; 2355 u8 tmr_idx; 2356 int err; 2357 2358 tmr_idx = ice_get_ptp_src_clock_index(hw); 2359 2360 /* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */ 2361 ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME); 2362 2363 /* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */ 2364 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME); 2365 if (err) 2366 return err; 2367 2368 /* Issue the sync to start the ICE_PTP_READ_TIME capture */ 2369 ice_ptp_exec_tmr_cmd(hw); 2370 2371 /* Read the captured PHC time from the shadow time registers */ 2372 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx)); 2373 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx)); 2374 *phc_time = (u64)lo << 32 | zo; 2375 2376 /* Read the captured PHY time from the PHY shadow registers */ 2377 err = ice_ptp_read_port_capture_eth56g(hw, port, &tx_time, &rx_time); 2378 if (err) 2379 return err; 2380 2381 /* If the PHY Tx and Rx timers don't match, log a warning message. 2382 * Note that this should not happen in normal circumstances since the 2383 * driver always programs them together. 2384 */ 2385 if (tx_time != rx_time) 2386 dev_warn(ice_hw_to_dev(hw), "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n", 2387 port, tx_time, rx_time); 2388 2389 *phy_time = tx_time; 2390 2391 return 0; 2392 } 2393 2394 /** 2395 * ice_sync_phy_timer_eth56g - Synchronize the PHY timer with PHC timer 2396 * @hw: pointer to the HW struct 2397 * @port: the PHY port to synchronize 2398 * 2399 * Perform an adjustment to ensure that the PHY and PHC timers are in sync. 2400 * This is done by issuing a ICE_PTP_READ_TIME command which triggers a 2401 * simultaneous read of the PHY timer and PHC timer. Then we use the 2402 * difference to calculate an appropriate 2s complement addition to add 2403 * to the PHY timer in order to ensure it reads the same value as the 2404 * primary PHC timer. 2405 * 2406 * Return: 2407 * * %0 - success 2408 * * %-EBUSY- failed to acquire PTP semaphore 2409 * * %other - PHY read/write failed 2410 */ 2411 static int ice_sync_phy_timer_eth56g(struct ice_hw *hw, u8 port) 2412 { 2413 u64 phc_time, phy_time, difference; 2414 int err; 2415 2416 if (!ice_ptp_lock(hw)) { 2417 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n"); 2418 return -EBUSY; 2419 } 2420 2421 err = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time, &phc_time); 2422 if (err) 2423 goto err_unlock; 2424 2425 /* Calculate the amount required to add to the port time in order for 2426 * it to match the PHC time. 2427 * 2428 * Note that the port adjustment is done using 2s complement 2429 * arithmetic. This is convenient since it means that we can simply 2430 * calculate the difference between the PHC time and the port time, 2431 * and it will be interpreted correctly. 2432 */ 2433 2434 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 2435 difference = phc_time - phy_time; 2436 2437 err = ice_ptp_prep_port_adj_eth56g(hw, port, (s64)difference); 2438 if (err) 2439 goto err_unlock; 2440 2441 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME); 2442 if (err) 2443 goto err_unlock; 2444 2445 /* Issue the sync to activate the time adjustment */ 2446 ice_ptp_exec_tmr_cmd(hw); 2447 2448 /* Re-capture the timer values to flush the command registers and 2449 * verify that the time was properly adjusted. 2450 */ 2451 err = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time, &phc_time); 2452 if (err) 2453 goto err_unlock; 2454 2455 dev_info(ice_hw_to_dev(hw), 2456 "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n", 2457 port, phy_time, phc_time); 2458 2459 err_unlock: 2460 ice_ptp_unlock(hw); 2461 return err; 2462 } 2463 2464 /** 2465 * ice_stop_phy_timer_eth56g - Stop the PHY clock timer 2466 * @hw: pointer to the HW struct 2467 * @port: the PHY port to stop 2468 * @soft_reset: if true, hold the SOFT_RESET bit of PHY_REG_PS 2469 * 2470 * Stop the clock of a PHY port. This must be done as part of the flow to 2471 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 2472 * initialized or when link speed changes. 2473 * 2474 * Return: 2475 * * %0 - success 2476 * * %other - failed to write to PHY 2477 */ 2478 int ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset) 2479 { 2480 int err; 2481 2482 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 0); 2483 if (err) 2484 return err; 2485 2486 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 0); 2487 if (err) 2488 return err; 2489 2490 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port); 2491 2492 return 0; 2493 } 2494 2495 /** 2496 * ice_start_phy_timer_eth56g - Start the PHY clock timer 2497 * @hw: pointer to the HW struct 2498 * @port: the PHY port to start 2499 * 2500 * Start the clock of a PHY port. This must be done as part of the flow to 2501 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 2502 * initialized or when link speed changes. 2503 * 2504 * Return: 2505 * * %0 - success 2506 * * %other - PHY read/write failed 2507 */ 2508 int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port) 2509 { 2510 u32 lo, hi; 2511 u64 incval; 2512 u8 tmr_idx; 2513 int err; 2514 2515 tmr_idx = ice_get_ptp_src_clock_index(hw); 2516 2517 err = ice_stop_phy_timer_eth56g(hw, port, false); 2518 if (err) 2519 return err; 2520 2521 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 2522 2523 err = ice_phy_cfg_parpcs_eth56g(hw, port); 2524 if (err) 2525 return err; 2526 2527 err = ice_phy_cfg_ptp_1step_eth56g(hw, port); 2528 if (err) 2529 return err; 2530 2531 err = ice_phy_cfg_mac_eth56g(hw, port); 2532 if (err) 2533 return err; 2534 2535 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 2536 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 2537 incval = (u64)hi << 32 | lo; 2538 2539 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_REG_TIMETUS_L, incval); 2540 if (err) 2541 return err; 2542 2543 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL); 2544 if (err) 2545 return err; 2546 2547 ice_ptp_exec_tmr_cmd(hw); 2548 2549 err = ice_sync_phy_timer_eth56g(hw, port); 2550 if (err) 2551 return err; 2552 2553 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 1); 2554 if (err) 2555 return err; 2556 2557 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 1); 2558 if (err) 2559 return err; 2560 2561 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port); 2562 2563 return 0; 2564 } 2565 2566 /** 2567 * ice_sb_access_ena_eth56g - Enable SB devices (PHY and others) access 2568 * @hw: pointer to HW struct 2569 * @enable: Enable or disable access 2570 * 2571 * Enable sideband devices (PHY and others) access. 2572 */ 2573 static void ice_sb_access_ena_eth56g(struct ice_hw *hw, bool enable) 2574 { 2575 u32 val = rd32(hw, PF_SB_REM_DEV_CTL); 2576 2577 if (enable) 2578 val |= BIT(eth56g_phy_0) | BIT(cgu) | BIT(eth56g_phy_1); 2579 else 2580 val &= ~(BIT(eth56g_phy_0) | BIT(cgu) | BIT(eth56g_phy_1)); 2581 2582 wr32(hw, PF_SB_REM_DEV_CTL, val); 2583 } 2584 2585 /** 2586 * ice_ptp_init_phc_eth56g - Perform E82X specific PHC initialization 2587 * @hw: pointer to HW struct 2588 * 2589 * Perform PHC initialization steps specific to E82X devices. 2590 * 2591 * Return: 2592 * * %0 - success 2593 * * %other - failed to initialize CGU 2594 */ 2595 static int ice_ptp_init_phc_eth56g(struct ice_hw *hw) 2596 { 2597 ice_sb_access_ena_eth56g(hw, true); 2598 /* Initialize the Clock Generation Unit */ 2599 return ice_init_cgu_e82x(hw); 2600 } 2601 2602 /** 2603 * ice_ptp_read_tx_hwtstamp_status_eth56g - Get TX timestamp status 2604 * @hw: pointer to the HW struct 2605 * @ts_status: the timestamp mask pointer 2606 * 2607 * Read the PHY Tx timestamp status mask indicating which ports have Tx 2608 * timestamps available. 2609 * 2610 * Return: 2611 * * %0 - success 2612 * * %other - failed to read from PHY 2613 */ 2614 int ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status) 2615 { 2616 const struct ice_eth56g_params *params = &hw->ptp.phy.eth56g; 2617 u8 phy, mask; 2618 u32 status; 2619 2620 mask = (1 << hw->ptp.ports_per_phy) - 1; 2621 *ts_status = 0; 2622 2623 for (phy = 0; phy < params->num_phys; phy++) { 2624 int err; 2625 2626 err = ice_read_phy_eth56g(hw, phy, PHY_PTP_INT_STATUS, &status); 2627 if (err) 2628 return err; 2629 2630 *ts_status |= (status & mask) << (phy * hw->ptp.ports_per_phy); 2631 } 2632 2633 ice_debug(hw, ICE_DBG_PTP, "PHY interrupt err: %x\n", *ts_status); 2634 2635 return 0; 2636 } 2637 2638 /** 2639 * ice_get_phy_tx_tstamp_ready_eth56g - Read the Tx memory status register 2640 * @hw: pointer to the HW struct 2641 * @port: the PHY port to read from 2642 * @tstamp_ready: contents of the Tx memory status register 2643 * 2644 * Read the PHY_REG_TX_MEMORY_STATUS register indicating which timestamps in 2645 * the PHY are ready. A set bit means the corresponding timestamp is valid and 2646 * ready to be captured from the PHY timestamp block. 2647 * 2648 * Return: 2649 * * %0 - success 2650 * * %other - failed to read from PHY 2651 */ 2652 static int ice_get_phy_tx_tstamp_ready_eth56g(struct ice_hw *hw, u8 port, 2653 u64 *tstamp_ready) 2654 { 2655 int err; 2656 2657 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L, 2658 tstamp_ready); 2659 if (err) { 2660 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS for port %u, err %d\n", 2661 port, err); 2662 return err; 2663 } 2664 2665 return 0; 2666 } 2667 2668 /** 2669 * ice_is_muxed_topo - detect breakout 2x50G topology for E825C 2670 * @hw: pointer to the HW struct 2671 * 2672 * Return: true if it's 2x50 breakout topology, false otherwise 2673 */ 2674 static bool ice_is_muxed_topo(struct ice_hw *hw) 2675 { 2676 u8 link_topo; 2677 bool mux; 2678 u32 val; 2679 2680 val = rd32(hw, GLGEN_SWITCH_MODE_CONFIG); 2681 mux = FIELD_GET(GLGEN_SWITCH_MODE_CONFIG_25X4_QUAD_M, val); 2682 val = rd32(hw, GLGEN_MAC_LINK_TOPO); 2683 link_topo = FIELD_GET(GLGEN_MAC_LINK_TOPO_LINK_TOPO_M, val); 2684 2685 return (mux && link_topo == ICE_LINK_TOPO_UP_TO_2_LINKS); 2686 } 2687 2688 /** 2689 * ice_ptp_init_phy_e825c - initialize PHY parameters 2690 * @hw: pointer to the HW struct 2691 */ 2692 static void ice_ptp_init_phy_e825c(struct ice_hw *hw) 2693 { 2694 struct ice_ptp_hw *ptp = &hw->ptp; 2695 struct ice_eth56g_params *params; 2696 u8 phy; 2697 2698 ptp->phy_model = ICE_PHY_ETH56G; 2699 params = &ptp->phy.eth56g; 2700 params->onestep_ena = false; 2701 params->peer_delay = 0; 2702 params->sfd_ena = false; 2703 params->phy_addr[0] = eth56g_phy_0; 2704 params->phy_addr[1] = eth56g_phy_1; 2705 params->num_phys = 2; 2706 ptp->ports_per_phy = 4; 2707 ptp->num_lports = params->num_phys * ptp->ports_per_phy; 2708 2709 ice_sb_access_ena_eth56g(hw, true); 2710 for (phy = 0; phy < params->num_phys; phy++) { 2711 u32 phy_rev; 2712 int err; 2713 2714 err = ice_read_phy_eth56g(hw, phy, PHY_REG_REVISION, &phy_rev); 2715 if (err || phy_rev != PHY_REVISION_ETH56G) { 2716 ptp->phy_model = ICE_PHY_UNSUP; 2717 return; 2718 } 2719 } 2720 2721 ptp->is_2x50g_muxed_topo = ice_is_muxed_topo(hw); 2722 } 2723 2724 /* E822 family functions 2725 * 2726 * The following functions operate on the E822 family of devices. 2727 */ 2728 2729 /** 2730 * ice_fill_phy_msg_e82x - Fill message data for a PHY register access 2731 * @hw: pointer to the HW struct 2732 * @msg: the PHY message buffer to fill in 2733 * @port: the port to access 2734 * @offset: the register offset 2735 */ 2736 static void ice_fill_phy_msg_e82x(struct ice_hw *hw, 2737 struct ice_sbq_msg_input *msg, u8 port, 2738 u16 offset) 2739 { 2740 int phy_port, phy, quadtype; 2741 2742 phy_port = port % hw->ptp.ports_per_phy; 2743 phy = port / hw->ptp.ports_per_phy; 2744 quadtype = ICE_GET_QUAD_NUM(port) % 2745 ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy); 2746 2747 if (quadtype == 0) { 2748 msg->msg_addr_low = P_Q0_L(P_0_BASE + offset, phy_port); 2749 msg->msg_addr_high = P_Q0_H(P_0_BASE + offset, phy_port); 2750 } else { 2751 msg->msg_addr_low = P_Q1_L(P_4_BASE + offset, phy_port); 2752 msg->msg_addr_high = P_Q1_H(P_4_BASE + offset, phy_port); 2753 } 2754 2755 if (phy == 0) 2756 msg->dest_dev = rmn_0; 2757 else if (phy == 1) 2758 msg->dest_dev = rmn_1; 2759 else 2760 msg->dest_dev = rmn_2; 2761 } 2762 2763 /** 2764 * ice_is_64b_phy_reg_e82x - Check if this is a 64bit PHY register 2765 * @low_addr: the low address to check 2766 * @high_addr: on return, contains the high address of the 64bit register 2767 * 2768 * Checks if the provided low address is one of the known 64bit PHY values 2769 * represented as two 32bit registers. If it is, return the appropriate high 2770 * register offset to use. 2771 */ 2772 static bool ice_is_64b_phy_reg_e82x(u16 low_addr, u16 *high_addr) 2773 { 2774 switch (low_addr) { 2775 case P_REG_PAR_PCS_TX_OFFSET_L: 2776 *high_addr = P_REG_PAR_PCS_TX_OFFSET_U; 2777 return true; 2778 case P_REG_PAR_PCS_RX_OFFSET_L: 2779 *high_addr = P_REG_PAR_PCS_RX_OFFSET_U; 2780 return true; 2781 case P_REG_PAR_TX_TIME_L: 2782 *high_addr = P_REG_PAR_TX_TIME_U; 2783 return true; 2784 case P_REG_PAR_RX_TIME_L: 2785 *high_addr = P_REG_PAR_RX_TIME_U; 2786 return true; 2787 case P_REG_TOTAL_TX_OFFSET_L: 2788 *high_addr = P_REG_TOTAL_TX_OFFSET_U; 2789 return true; 2790 case P_REG_TOTAL_RX_OFFSET_L: 2791 *high_addr = P_REG_TOTAL_RX_OFFSET_U; 2792 return true; 2793 case P_REG_UIX66_10G_40G_L: 2794 *high_addr = P_REG_UIX66_10G_40G_U; 2795 return true; 2796 case P_REG_UIX66_25G_100G_L: 2797 *high_addr = P_REG_UIX66_25G_100G_U; 2798 return true; 2799 case P_REG_TX_CAPTURE_L: 2800 *high_addr = P_REG_TX_CAPTURE_U; 2801 return true; 2802 case P_REG_RX_CAPTURE_L: 2803 *high_addr = P_REG_RX_CAPTURE_U; 2804 return true; 2805 case P_REG_TX_TIMER_INC_PRE_L: 2806 *high_addr = P_REG_TX_TIMER_INC_PRE_U; 2807 return true; 2808 case P_REG_RX_TIMER_INC_PRE_L: 2809 *high_addr = P_REG_RX_TIMER_INC_PRE_U; 2810 return true; 2811 default: 2812 return false; 2813 } 2814 } 2815 2816 /** 2817 * ice_is_40b_phy_reg_e82x - Check if this is a 40bit PHY register 2818 * @low_addr: the low address to check 2819 * @high_addr: on return, contains the high address of the 40bit value 2820 * 2821 * Checks if the provided low address is one of the known 40bit PHY values 2822 * split into two registers with the lower 8 bits in the low register and the 2823 * upper 32 bits in the high register. If it is, return the appropriate high 2824 * register offset to use. 2825 */ 2826 static bool ice_is_40b_phy_reg_e82x(u16 low_addr, u16 *high_addr) 2827 { 2828 switch (low_addr) { 2829 case P_REG_TIMETUS_L: 2830 *high_addr = P_REG_TIMETUS_U; 2831 return true; 2832 case P_REG_PAR_RX_TUS_L: 2833 *high_addr = P_REG_PAR_RX_TUS_U; 2834 return true; 2835 case P_REG_PAR_TX_TUS_L: 2836 *high_addr = P_REG_PAR_TX_TUS_U; 2837 return true; 2838 case P_REG_PCS_RX_TUS_L: 2839 *high_addr = P_REG_PCS_RX_TUS_U; 2840 return true; 2841 case P_REG_PCS_TX_TUS_L: 2842 *high_addr = P_REG_PCS_TX_TUS_U; 2843 return true; 2844 case P_REG_DESK_PAR_RX_TUS_L: 2845 *high_addr = P_REG_DESK_PAR_RX_TUS_U; 2846 return true; 2847 case P_REG_DESK_PAR_TX_TUS_L: 2848 *high_addr = P_REG_DESK_PAR_TX_TUS_U; 2849 return true; 2850 case P_REG_DESK_PCS_RX_TUS_L: 2851 *high_addr = P_REG_DESK_PCS_RX_TUS_U; 2852 return true; 2853 case P_REG_DESK_PCS_TX_TUS_L: 2854 *high_addr = P_REG_DESK_PCS_TX_TUS_U; 2855 return true; 2856 default: 2857 return false; 2858 } 2859 } 2860 2861 /** 2862 * ice_read_phy_reg_e82x - Read a PHY register 2863 * @hw: pointer to the HW struct 2864 * @port: PHY port to read from 2865 * @offset: PHY register offset to read 2866 * @val: on return, the contents read from the PHY 2867 * 2868 * Read a PHY register for the given port over the device sideband queue. 2869 */ 2870 static int 2871 ice_read_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 *val) 2872 { 2873 struct ice_sbq_msg_input msg = {0}; 2874 int err; 2875 2876 ice_fill_phy_msg_e82x(hw, &msg, port, offset); 2877 msg.opcode = ice_sbq_msg_rd; 2878 2879 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 2880 if (err) { 2881 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2882 err); 2883 return err; 2884 } 2885 2886 *val = msg.data; 2887 2888 return 0; 2889 } 2890 2891 /** 2892 * ice_read_64b_phy_reg_e82x - Read a 64bit value from PHY registers 2893 * @hw: pointer to the HW struct 2894 * @port: PHY port to read from 2895 * @low_addr: offset of the lower register to read from 2896 * @val: on return, the contents of the 64bit value from the PHY registers 2897 * 2898 * Reads the two registers associated with a 64bit value and returns it in the 2899 * val pointer. The offset always specifies the lower register offset to use. 2900 * The high offset is looked up. This function only operates on registers 2901 * known to be two parts of a 64bit value. 2902 */ 2903 static int 2904 ice_read_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val) 2905 { 2906 u32 low, high; 2907 u16 high_addr; 2908 int err; 2909 2910 /* Only operate on registers known to be split into two 32bit 2911 * registers. 2912 */ 2913 if (!ice_is_64b_phy_reg_e82x(low_addr, &high_addr)) { 2914 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n", 2915 low_addr); 2916 return -EINVAL; 2917 } 2918 2919 err = ice_read_phy_reg_e82x(hw, port, low_addr, &low); 2920 if (err) { 2921 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, err %d", 2922 low_addr, err); 2923 return err; 2924 } 2925 2926 err = ice_read_phy_reg_e82x(hw, port, high_addr, &high); 2927 if (err) { 2928 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, err %d", 2929 high_addr, err); 2930 return err; 2931 } 2932 2933 *val = (u64)high << 32 | low; 2934 2935 return 0; 2936 } 2937 2938 /** 2939 * ice_write_phy_reg_e82x - Write a PHY register 2940 * @hw: pointer to the HW struct 2941 * @port: PHY port to write to 2942 * @offset: PHY register offset to write 2943 * @val: The value to write to the register 2944 * 2945 * Write a PHY register for the given port over the device sideband queue. 2946 */ 2947 static int 2948 ice_write_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 val) 2949 { 2950 struct ice_sbq_msg_input msg = {0}; 2951 int err; 2952 2953 ice_fill_phy_msg_e82x(hw, &msg, port, offset); 2954 msg.opcode = ice_sbq_msg_wr; 2955 msg.data = val; 2956 2957 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 2958 if (err) { 2959 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2960 err); 2961 return err; 2962 } 2963 2964 return 0; 2965 } 2966 2967 /** 2968 * ice_write_40b_phy_reg_e82x - Write a 40b value to the PHY 2969 * @hw: pointer to the HW struct 2970 * @port: port to write to 2971 * @low_addr: offset of the low register 2972 * @val: 40b value to write 2973 * 2974 * Write the provided 40b value to the two associated registers by splitting 2975 * it up into two chunks, the lower 8 bits and the upper 32 bits. 2976 */ 2977 static int 2978 ice_write_40b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) 2979 { 2980 u32 low, high; 2981 u16 high_addr; 2982 int err; 2983 2984 /* Only operate on registers known to be split into a lower 8 bit 2985 * register and an upper 32 bit register. 2986 */ 2987 if (!ice_is_40b_phy_reg_e82x(low_addr, &high_addr)) { 2988 ice_debug(hw, ICE_DBG_PTP, "Invalid 40b register addr 0x%08x\n", 2989 low_addr); 2990 return -EINVAL; 2991 } 2992 low = FIELD_GET(P_REG_40B_LOW_M, val); 2993 high = (u32)(val >> P_REG_40B_HIGH_S); 2994 2995 err = ice_write_phy_reg_e82x(hw, port, low_addr, low); 2996 if (err) { 2997 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 2998 low_addr, err); 2999 return err; 3000 } 3001 3002 err = ice_write_phy_reg_e82x(hw, port, high_addr, high); 3003 if (err) { 3004 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 3005 high_addr, err); 3006 return err; 3007 } 3008 3009 return 0; 3010 } 3011 3012 /** 3013 * ice_write_64b_phy_reg_e82x - Write a 64bit value to PHY registers 3014 * @hw: pointer to the HW struct 3015 * @port: PHY port to read from 3016 * @low_addr: offset of the lower register to read from 3017 * @val: the contents of the 64bit value to write to PHY 3018 * 3019 * Write the 64bit value to the two associated 32bit PHY registers. The offset 3020 * is always specified as the lower register, and the high address is looked 3021 * up. This function only operates on registers known to be two parts of 3022 * a 64bit value. 3023 */ 3024 static int 3025 ice_write_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) 3026 { 3027 u32 low, high; 3028 u16 high_addr; 3029 int err; 3030 3031 /* Only operate on registers known to be split into two 32bit 3032 * registers. 3033 */ 3034 if (!ice_is_64b_phy_reg_e82x(low_addr, &high_addr)) { 3035 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n", 3036 low_addr); 3037 return -EINVAL; 3038 } 3039 3040 low = lower_32_bits(val); 3041 high = upper_32_bits(val); 3042 3043 err = ice_write_phy_reg_e82x(hw, port, low_addr, low); 3044 if (err) { 3045 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 3046 low_addr, err); 3047 return err; 3048 } 3049 3050 err = ice_write_phy_reg_e82x(hw, port, high_addr, high); 3051 if (err) { 3052 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 3053 high_addr, err); 3054 return err; 3055 } 3056 3057 return 0; 3058 } 3059 3060 /** 3061 * ice_fill_quad_msg_e82x - Fill message data for quad register access 3062 * @hw: pointer to the HW struct 3063 * @msg: the PHY message buffer to fill in 3064 * @quad: the quad to access 3065 * @offset: the register offset 3066 * 3067 * Fill a message buffer for accessing a register in a quad shared between 3068 * multiple PHYs. 3069 * 3070 * Return: 3071 * * %0 - OK 3072 * * %-EINVAL - invalid quad number 3073 */ 3074 static int ice_fill_quad_msg_e82x(struct ice_hw *hw, 3075 struct ice_sbq_msg_input *msg, u8 quad, 3076 u16 offset) 3077 { 3078 u32 addr; 3079 3080 if (quad >= ICE_GET_QUAD_NUM(hw->ptp.num_lports)) 3081 return -EINVAL; 3082 3083 msg->dest_dev = rmn_0; 3084 3085 if (!(quad % ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy))) 3086 addr = Q_0_BASE + offset; 3087 else 3088 addr = Q_1_BASE + offset; 3089 3090 msg->msg_addr_low = lower_16_bits(addr); 3091 msg->msg_addr_high = upper_16_bits(addr); 3092 3093 return 0; 3094 } 3095 3096 /** 3097 * ice_read_quad_reg_e82x - Read a PHY quad register 3098 * @hw: pointer to the HW struct 3099 * @quad: quad to read from 3100 * @offset: quad register offset to read 3101 * @val: on return, the contents read from the quad 3102 * 3103 * Read a quad register over the device sideband queue. Quad registers are 3104 * shared between multiple PHYs. 3105 */ 3106 int 3107 ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val) 3108 { 3109 struct ice_sbq_msg_input msg = {0}; 3110 int err; 3111 3112 err = ice_fill_quad_msg_e82x(hw, &msg, quad, offset); 3113 if (err) 3114 return err; 3115 3116 msg.opcode = ice_sbq_msg_rd; 3117 3118 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 3119 if (err) { 3120 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 3121 err); 3122 return err; 3123 } 3124 3125 *val = msg.data; 3126 3127 return 0; 3128 } 3129 3130 /** 3131 * ice_write_quad_reg_e82x - Write a PHY quad register 3132 * @hw: pointer to the HW struct 3133 * @quad: quad to write to 3134 * @offset: quad register offset to write 3135 * @val: The value to write to the register 3136 * 3137 * Write a quad register over the device sideband queue. Quad registers are 3138 * shared between multiple PHYs. 3139 */ 3140 int 3141 ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val) 3142 { 3143 struct ice_sbq_msg_input msg = {0}; 3144 int err; 3145 3146 err = ice_fill_quad_msg_e82x(hw, &msg, quad, offset); 3147 if (err) 3148 return err; 3149 3150 msg.opcode = ice_sbq_msg_wr; 3151 msg.data = val; 3152 3153 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 3154 if (err) { 3155 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 3156 err); 3157 return err; 3158 } 3159 3160 return 0; 3161 } 3162 3163 /** 3164 * ice_read_phy_tstamp_e82x - Read a PHY timestamp out of the quad block 3165 * @hw: pointer to the HW struct 3166 * @quad: the quad to read from 3167 * @idx: the timestamp index to read 3168 * @tstamp: on return, the 40bit timestamp value 3169 * 3170 * Read a 40bit timestamp value out of the two associated registers in the 3171 * quad memory block that is shared between the internal PHYs of the E822 3172 * family of devices. 3173 */ 3174 static int 3175 ice_read_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp) 3176 { 3177 u16 lo_addr, hi_addr; 3178 u32 lo, hi; 3179 int err; 3180 3181 lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx); 3182 hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx); 3183 3184 err = ice_read_quad_reg_e82x(hw, quad, lo_addr, &lo); 3185 if (err) { 3186 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 3187 err); 3188 return err; 3189 } 3190 3191 err = ice_read_quad_reg_e82x(hw, quad, hi_addr, &hi); 3192 if (err) { 3193 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 3194 err); 3195 return err; 3196 } 3197 3198 /* For E822 based internal PHYs, the timestamp is reported with the 3199 * lower 8 bits in the low register, and the upper 32 bits in the high 3200 * register. 3201 */ 3202 *tstamp = FIELD_PREP(TS_PHY_HIGH_M, hi) | FIELD_PREP(TS_PHY_LOW_M, lo); 3203 3204 return 0; 3205 } 3206 3207 /** 3208 * ice_clear_phy_tstamp_e82x - Clear a timestamp from the quad block 3209 * @hw: pointer to the HW struct 3210 * @quad: the quad to read from 3211 * @idx: the timestamp index to reset 3212 * 3213 * Read the timestamp out of the quad to clear its timestamp status bit from 3214 * the PHY quad block that is shared between the internal PHYs of the E822 3215 * devices. 3216 * 3217 * Note that unlike E810, software cannot directly write to the quad memory 3218 * bank registers. E822 relies on the ice_get_phy_tx_tstamp_ready() function 3219 * to determine which timestamps are valid. Reading a timestamp auto-clears 3220 * the valid bit. 3221 * 3222 * To directly clear the contents of the timestamp block entirely, discarding 3223 * all timestamp data at once, software should instead use 3224 * ice_ptp_reset_ts_memory_quad_e82x(). 3225 * 3226 * This function should only be called on an idx whose bit is set according to 3227 * ice_get_phy_tx_tstamp_ready(). 3228 */ 3229 static int 3230 ice_clear_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx) 3231 { 3232 u64 unused_tstamp; 3233 int err; 3234 3235 err = ice_read_phy_tstamp_e82x(hw, quad, idx, &unused_tstamp); 3236 if (err) { 3237 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for quad %u, idx %u, err %d\n", 3238 quad, idx, err); 3239 return err; 3240 } 3241 3242 return 0; 3243 } 3244 3245 /** 3246 * ice_ptp_reset_ts_memory_quad_e82x - Clear all timestamps from the quad block 3247 * @hw: pointer to the HW struct 3248 * @quad: the quad to read from 3249 * 3250 * Clear all timestamps from the PHY quad block that is shared between the 3251 * internal PHYs on the E822 devices. 3252 */ 3253 void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad) 3254 { 3255 ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M); 3256 ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M); 3257 } 3258 3259 /** 3260 * ice_ptp_reset_ts_memory_e82x - Clear all timestamps from all quad blocks 3261 * @hw: pointer to the HW struct 3262 */ 3263 static void ice_ptp_reset_ts_memory_e82x(struct ice_hw *hw) 3264 { 3265 unsigned int quad; 3266 3267 for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports); quad++) 3268 ice_ptp_reset_ts_memory_quad_e82x(hw, quad); 3269 } 3270 3271 /** 3272 * ice_ptp_set_vernier_wl - Set the window length for vernier calibration 3273 * @hw: pointer to the HW struct 3274 * 3275 * Set the window length used for the vernier port calibration process. 3276 */ 3277 static int ice_ptp_set_vernier_wl(struct ice_hw *hw) 3278 { 3279 u8 port; 3280 3281 for (port = 0; port < hw->ptp.num_lports; port++) { 3282 int err; 3283 3284 err = ice_write_phy_reg_e82x(hw, port, P_REG_WL, 3285 PTP_VERNIER_WL); 3286 if (err) { 3287 ice_debug(hw, ICE_DBG_PTP, "Failed to set vernier window length for port %u, err %d\n", 3288 port, err); 3289 return err; 3290 } 3291 } 3292 3293 return 0; 3294 } 3295 3296 /** 3297 * ice_ptp_init_phc_e82x - Perform E822 specific PHC initialization 3298 * @hw: pointer to HW struct 3299 * 3300 * Perform PHC initialization steps specific to E822 devices. 3301 */ 3302 static int ice_ptp_init_phc_e82x(struct ice_hw *hw) 3303 { 3304 int err; 3305 u32 val; 3306 3307 /* Enable reading switch and PHY registers over the sideband queue */ 3308 #define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1) 3309 #define PF_SB_REM_DEV_CTL_PHY0 BIT(2) 3310 val = rd32(hw, PF_SB_REM_DEV_CTL); 3311 val |= (PF_SB_REM_DEV_CTL_SWITCH_READ | PF_SB_REM_DEV_CTL_PHY0); 3312 wr32(hw, PF_SB_REM_DEV_CTL, val); 3313 3314 /* Initialize the Clock Generation Unit */ 3315 err = ice_init_cgu_e82x(hw); 3316 if (err) 3317 return err; 3318 3319 /* Set window length for all the ports */ 3320 return ice_ptp_set_vernier_wl(hw); 3321 } 3322 3323 /** 3324 * ice_ptp_prep_phy_time_e82x - Prepare PHY port with initial time 3325 * @hw: pointer to the HW struct 3326 * @time: Time to initialize the PHY port clocks to 3327 * 3328 * Program the PHY port registers with a new initial time value. The port 3329 * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync 3330 * command. The time value is the upper 32 bits of the PHY timer, usually in 3331 * units of nominal nanoseconds. 3332 */ 3333 static int 3334 ice_ptp_prep_phy_time_e82x(struct ice_hw *hw, u32 time) 3335 { 3336 u64 phy_time; 3337 u8 port; 3338 int err; 3339 3340 /* The time represents the upper 32 bits of the PHY timer, so we need 3341 * to shift to account for this when programming. 3342 */ 3343 phy_time = (u64)time << 32; 3344 3345 for (port = 0; port < hw->ptp.num_lports; port++) { 3346 /* Tx case */ 3347 err = ice_write_64b_phy_reg_e82x(hw, port, 3348 P_REG_TX_TIMER_INC_PRE_L, 3349 phy_time); 3350 if (err) 3351 goto exit_err; 3352 3353 /* Rx case */ 3354 err = ice_write_64b_phy_reg_e82x(hw, port, 3355 P_REG_RX_TIMER_INC_PRE_L, 3356 phy_time); 3357 if (err) 3358 goto exit_err; 3359 } 3360 3361 return 0; 3362 3363 exit_err: 3364 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n", 3365 port, err); 3366 3367 return err; 3368 } 3369 3370 /** 3371 * ice_ptp_prep_port_adj_e82x - Prepare a single port for time adjust 3372 * @hw: pointer to HW struct 3373 * @port: Port number to be programmed 3374 * @time: time in cycles to adjust the port Tx and Rx clocks 3375 * 3376 * Program the port for an atomic adjustment by writing the Tx and Rx timer 3377 * registers. The atomic adjustment won't be completed until the driver issues 3378 * an ICE_PTP_ADJ_TIME command. 3379 * 3380 * Note that time is not in units of nanoseconds. It is in clock time 3381 * including the lower sub-nanosecond portion of the port timer. 3382 * 3383 * Negative adjustments are supported using 2s complement arithmetic. 3384 */ 3385 static int 3386 ice_ptp_prep_port_adj_e82x(struct ice_hw *hw, u8 port, s64 time) 3387 { 3388 u32 l_time, u_time; 3389 int err; 3390 3391 l_time = lower_32_bits(time); 3392 u_time = upper_32_bits(time); 3393 3394 /* Tx case */ 3395 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TIMER_INC_PRE_L, 3396 l_time); 3397 if (err) 3398 goto exit_err; 3399 3400 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TIMER_INC_PRE_U, 3401 u_time); 3402 if (err) 3403 goto exit_err; 3404 3405 /* Rx case */ 3406 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TIMER_INC_PRE_L, 3407 l_time); 3408 if (err) 3409 goto exit_err; 3410 3411 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TIMER_INC_PRE_U, 3412 u_time); 3413 if (err) 3414 goto exit_err; 3415 3416 return 0; 3417 3418 exit_err: 3419 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n", 3420 port, err); 3421 return err; 3422 } 3423 3424 /** 3425 * ice_ptp_prep_phy_adj_e82x - Prep PHY ports for a time adjustment 3426 * @hw: pointer to HW struct 3427 * @adj: adjustment in nanoseconds 3428 * 3429 * Prepare the PHY ports for an atomic time adjustment by programming the PHY 3430 * Tx and Rx port registers. The actual adjustment is completed by issuing an 3431 * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command. 3432 */ 3433 static int 3434 ice_ptp_prep_phy_adj_e82x(struct ice_hw *hw, s32 adj) 3435 { 3436 s64 cycles; 3437 u8 port; 3438 3439 /* The port clock supports adjustment of the sub-nanosecond portion of 3440 * the clock. We shift the provided adjustment in nanoseconds to 3441 * calculate the appropriate adjustment to program into the PHY ports. 3442 */ 3443 if (adj > 0) 3444 cycles = (s64)adj << 32; 3445 else 3446 cycles = -(((s64)-adj) << 32); 3447 3448 for (port = 0; port < hw->ptp.num_lports; port++) { 3449 int err; 3450 3451 err = ice_ptp_prep_port_adj_e82x(hw, port, cycles); 3452 if (err) 3453 return err; 3454 } 3455 3456 return 0; 3457 } 3458 3459 /** 3460 * ice_ptp_prep_phy_incval_e82x - Prepare PHY ports for time adjustment 3461 * @hw: pointer to HW struct 3462 * @incval: new increment value to prepare 3463 * 3464 * Prepare each of the PHY ports for a new increment value by programming the 3465 * port's TIMETUS registers. The new increment value will be updated after 3466 * issuing an ICE_PTP_INIT_INCVAL command. 3467 */ 3468 static int 3469 ice_ptp_prep_phy_incval_e82x(struct ice_hw *hw, u64 incval) 3470 { 3471 int err; 3472 u8 port; 3473 3474 for (port = 0; port < hw->ptp.num_lports; port++) { 3475 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L, 3476 incval); 3477 if (err) 3478 goto exit_err; 3479 } 3480 3481 return 0; 3482 3483 exit_err: 3484 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n", 3485 port, err); 3486 3487 return err; 3488 } 3489 3490 /** 3491 * ice_ptp_read_port_capture - Read a port's local time capture 3492 * @hw: pointer to HW struct 3493 * @port: Port number to read 3494 * @tx_ts: on return, the Tx port time capture 3495 * @rx_ts: on return, the Rx port time capture 3496 * 3497 * Read the port's Tx and Rx local time capture values. 3498 * 3499 * Note this has no equivalent for the E810 devices. 3500 */ 3501 static int 3502 ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts) 3503 { 3504 int err; 3505 3506 /* Tx case */ 3507 err = ice_read_64b_phy_reg_e82x(hw, port, P_REG_TX_CAPTURE_L, tx_ts); 3508 if (err) { 3509 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n", 3510 err); 3511 return err; 3512 } 3513 3514 ice_debug(hw, ICE_DBG_PTP, "tx_init = 0x%016llx\n", 3515 (unsigned long long)*tx_ts); 3516 3517 /* Rx case */ 3518 err = ice_read_64b_phy_reg_e82x(hw, port, P_REG_RX_CAPTURE_L, rx_ts); 3519 if (err) { 3520 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n", 3521 err); 3522 return err; 3523 } 3524 3525 ice_debug(hw, ICE_DBG_PTP, "rx_init = 0x%016llx\n", 3526 (unsigned long long)*rx_ts); 3527 3528 return 0; 3529 } 3530 3531 /** 3532 * ice_ptp_write_port_cmd_e82x - Prepare a single PHY port for a timer command 3533 * @hw: pointer to HW struct 3534 * @port: Port to which cmd has to be sent 3535 * @cmd: Command to be sent to the port 3536 * 3537 * Prepare the requested port for an upcoming timer sync command. 3538 * 3539 * Note there is no equivalent of this operation on E810, as that device 3540 * always handles all external PHYs internally. 3541 * 3542 * Return: 3543 * * %0 - success 3544 * * %other - failed to write to PHY 3545 */ 3546 static int ice_ptp_write_port_cmd_e82x(struct ice_hw *hw, u8 port, 3547 enum ice_ptp_tmr_cmd cmd) 3548 { 3549 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 3550 int err; 3551 3552 /* Tx case */ 3553 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TMR_CMD, val); 3554 if (err) { 3555 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n", 3556 err); 3557 return err; 3558 } 3559 3560 /* Rx case */ 3561 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TMR_CMD, 3562 val | TS_CMD_RX_TYPE); 3563 if (err) { 3564 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n", 3565 err); 3566 return err; 3567 } 3568 3569 return 0; 3570 } 3571 3572 /* E822 Vernier calibration functions 3573 * 3574 * The following functions are used as part of the vernier calibration of 3575 * a port. This calibration increases the precision of the timestamps on the 3576 * port. 3577 */ 3578 3579 /** 3580 * ice_phy_get_speed_and_fec_e82x - Get link speed and FEC based on serdes mode 3581 * @hw: pointer to HW struct 3582 * @port: the port to read from 3583 * @link_out: if non-NULL, holds link speed on success 3584 * @fec_out: if non-NULL, holds FEC algorithm on success 3585 * 3586 * Read the serdes data for the PHY port and extract the link speed and FEC 3587 * algorithm. 3588 */ 3589 static int 3590 ice_phy_get_speed_and_fec_e82x(struct ice_hw *hw, u8 port, 3591 enum ice_ptp_link_spd *link_out, 3592 enum ice_ptp_fec_mode *fec_out) 3593 { 3594 enum ice_ptp_link_spd link; 3595 enum ice_ptp_fec_mode fec; 3596 u32 serdes; 3597 int err; 3598 3599 err = ice_read_phy_reg_e82x(hw, port, P_REG_LINK_SPEED, &serdes); 3600 if (err) { 3601 ice_debug(hw, ICE_DBG_PTP, "Failed to read serdes info\n"); 3602 return err; 3603 } 3604 3605 /* Determine the FEC algorithm */ 3606 fec = (enum ice_ptp_fec_mode)P_REG_LINK_SPEED_FEC_MODE(serdes); 3607 3608 serdes &= P_REG_LINK_SPEED_SERDES_M; 3609 3610 /* Determine the link speed */ 3611 if (fec == ICE_PTP_FEC_MODE_RS_FEC) { 3612 switch (serdes) { 3613 case ICE_PTP_SERDES_25G: 3614 link = ICE_PTP_LNK_SPD_25G_RS; 3615 break; 3616 case ICE_PTP_SERDES_50G: 3617 link = ICE_PTP_LNK_SPD_50G_RS; 3618 break; 3619 case ICE_PTP_SERDES_100G: 3620 link = ICE_PTP_LNK_SPD_100G_RS; 3621 break; 3622 default: 3623 return -EIO; 3624 } 3625 } else { 3626 switch (serdes) { 3627 case ICE_PTP_SERDES_1G: 3628 link = ICE_PTP_LNK_SPD_1G; 3629 break; 3630 case ICE_PTP_SERDES_10G: 3631 link = ICE_PTP_LNK_SPD_10G; 3632 break; 3633 case ICE_PTP_SERDES_25G: 3634 link = ICE_PTP_LNK_SPD_25G; 3635 break; 3636 case ICE_PTP_SERDES_40G: 3637 link = ICE_PTP_LNK_SPD_40G; 3638 break; 3639 case ICE_PTP_SERDES_50G: 3640 link = ICE_PTP_LNK_SPD_50G; 3641 break; 3642 default: 3643 return -EIO; 3644 } 3645 } 3646 3647 if (link_out) 3648 *link_out = link; 3649 if (fec_out) 3650 *fec_out = fec; 3651 3652 return 0; 3653 } 3654 3655 /** 3656 * ice_phy_cfg_lane_e82x - Configure PHY quad for single/multi-lane timestamp 3657 * @hw: pointer to HW struct 3658 * @port: to configure the quad for 3659 */ 3660 static void ice_phy_cfg_lane_e82x(struct ice_hw *hw, u8 port) 3661 { 3662 enum ice_ptp_link_spd link_spd; 3663 int err; 3664 u32 val; 3665 u8 quad; 3666 3667 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, NULL); 3668 if (err) { 3669 ice_debug(hw, ICE_DBG_PTP, "Failed to get PHY link speed, err %d\n", 3670 err); 3671 return; 3672 } 3673 3674 quad = ICE_GET_QUAD_NUM(port); 3675 3676 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val); 3677 if (err) { 3678 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEM_GLB_CFG, err %d\n", 3679 err); 3680 return; 3681 } 3682 3683 if (link_spd >= ICE_PTP_LNK_SPD_40G) 3684 val &= ~Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M; 3685 else 3686 val |= Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M; 3687 3688 err = ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val); 3689 if (err) { 3690 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_MEM_GBL_CFG, err %d\n", 3691 err); 3692 return; 3693 } 3694 } 3695 3696 /** 3697 * ice_phy_cfg_uix_e82x - Configure Serdes UI to TU conversion for E822 3698 * @hw: pointer to the HW structure 3699 * @port: the port to configure 3700 * 3701 * Program the conversion ration of Serdes clock "unit intervals" (UIs) to PHC 3702 * hardware clock time units (TUs). That is, determine the number of TUs per 3703 * serdes unit interval, and program the UIX registers with this conversion. 3704 * 3705 * This conversion is used as part of the calibration process when determining 3706 * the additional error of a timestamp vs the real time of transmission or 3707 * receipt of the packet. 3708 * 3709 * Hardware uses the number of TUs per 66 UIs, written to the UIX registers 3710 * for the two main serdes clock rates, 10G/40G and 25G/100G serdes clocks. 3711 * 3712 * To calculate the conversion ratio, we use the following facts: 3713 * 3714 * a) the clock frequency in Hz (cycles per second) 3715 * b) the number of TUs per cycle (the increment value of the clock) 3716 * c) 1 second per 1 billion nanoseconds 3717 * d) the duration of 66 UIs in nanoseconds 3718 * 3719 * Given these facts, we can use the following table to work out what ratios 3720 * to multiply in order to get the number of TUs per 66 UIs: 3721 * 3722 * cycles | 1 second | incval (TUs) | nanoseconds 3723 * -------+--------------+--------------+------------- 3724 * second | 1 billion ns | cycle | 66 UIs 3725 * 3726 * To perform the multiplication using integers without too much loss of 3727 * precision, we can take use the following equation: 3728 * 3729 * (freq * incval * 6600 LINE_UI ) / ( 100 * 1 billion) 3730 * 3731 * We scale up to using 6600 UI instead of 66 in order to avoid fractional 3732 * nanosecond UIs (66 UI at 10G/40G is 6.4 ns) 3733 * 3734 * The increment value has a maximum expected range of about 34 bits, while 3735 * the frequency value is about 29 bits. Multiplying these values shouldn't 3736 * overflow the 64 bits. However, we must then further multiply them again by 3737 * the Serdes unit interval duration. To avoid overflow here, we split the 3738 * overall divide by 1e11 into a divide by 256 (shift down by 8 bits) and 3739 * a divide by 390,625,000. This does lose some precision, but avoids 3740 * miscalculation due to arithmetic overflow. 3741 */ 3742 static int ice_phy_cfg_uix_e82x(struct ice_hw *hw, u8 port) 3743 { 3744 u64 cur_freq, clk_incval, tu_per_sec, uix; 3745 int err; 3746 3747 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3748 clk_incval = ice_ptp_read_src_incval(hw); 3749 3750 /* Calculate TUs per second divided by 256 */ 3751 tu_per_sec = (cur_freq * clk_incval) >> 8; 3752 3753 #define LINE_UI_10G_40G 640 /* 6600 UIs is 640 nanoseconds at 10Gb/40Gb */ 3754 #define LINE_UI_25G_100G 256 /* 6600 UIs is 256 nanoseconds at 25Gb/100Gb */ 3755 3756 /* Program the 10Gb/40Gb conversion ratio */ 3757 uix = div_u64(tu_per_sec * LINE_UI_10G_40G, 390625000); 3758 3759 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_UIX66_10G_40G_L, 3760 uix); 3761 if (err) { 3762 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_10G_40G, err %d\n", 3763 err); 3764 return err; 3765 } 3766 3767 /* Program the 25Gb/100Gb conversion ratio */ 3768 uix = div_u64(tu_per_sec * LINE_UI_25G_100G, 390625000); 3769 3770 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_UIX66_25G_100G_L, 3771 uix); 3772 if (err) { 3773 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_25G_100G, err %d\n", 3774 err); 3775 return err; 3776 } 3777 3778 return 0; 3779 } 3780 3781 /** 3782 * ice_phy_cfg_parpcs_e82x - Configure TUs per PAR/PCS clock cycle 3783 * @hw: pointer to the HW struct 3784 * @port: port to configure 3785 * 3786 * Configure the number of TUs for the PAR and PCS clocks used as part of the 3787 * timestamp calibration process. This depends on the link speed, as the PHY 3788 * uses different markers depending on the speed. 3789 * 3790 * 1Gb/10Gb/25Gb: 3791 * - Tx/Rx PAR/PCS markers 3792 * 3793 * 25Gb RS: 3794 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers 3795 * 3796 * 40Gb/50Gb: 3797 * - Tx/Rx PAR/PCS markers 3798 * - Rx Deskew PAR/PCS markers 3799 * 3800 * 50G RS and 100GB RS: 3801 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers 3802 * - Rx Deskew PAR/PCS markers 3803 * - Tx PAR/PCS markers 3804 * 3805 * To calculate the conversion, we use the PHC clock frequency (cycles per 3806 * second), the increment value (TUs per cycle), and the related PHY clock 3807 * frequency to calculate the TUs per unit of the PHY link clock. The 3808 * following table shows how the units convert: 3809 * 3810 * cycles | TUs | second 3811 * -------+-------+-------- 3812 * second | cycle | cycles 3813 * 3814 * For each conversion register, look up the appropriate frequency from the 3815 * e822 PAR/PCS table and calculate the TUs per unit of that clock. Program 3816 * this to the appropriate register, preparing hardware to perform timestamp 3817 * calibration to calculate the total Tx or Rx offset to adjust the timestamp 3818 * in order to calibrate for the internal PHY delays. 3819 * 3820 * Note that the increment value ranges up to ~34 bits, and the clock 3821 * frequency is ~29 bits, so multiplying them together should fit within the 3822 * 64 bit arithmetic. 3823 */ 3824 static int ice_phy_cfg_parpcs_e82x(struct ice_hw *hw, u8 port) 3825 { 3826 u64 cur_freq, clk_incval, tu_per_sec, phy_tus; 3827 enum ice_ptp_link_spd link_spd; 3828 enum ice_ptp_fec_mode fec_mode; 3829 int err; 3830 3831 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode); 3832 if (err) 3833 return err; 3834 3835 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3836 clk_incval = ice_ptp_read_src_incval(hw); 3837 3838 /* Calculate TUs per cycle of the PHC clock */ 3839 tu_per_sec = cur_freq * clk_incval; 3840 3841 /* For each PHY conversion register, look up the appropriate link 3842 * speed frequency and determine the TUs per that clock's cycle time. 3843 * Split this into a high and low value and then program the 3844 * appropriate register. If that link speed does not use the 3845 * associated register, write zeros to clear it instead. 3846 */ 3847 3848 /* P_REG_PAR_TX_TUS */ 3849 if (e822_vernier[link_spd].tx_par_clk) 3850 phy_tus = div_u64(tu_per_sec, 3851 e822_vernier[link_spd].tx_par_clk); 3852 else 3853 phy_tus = 0; 3854 3855 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PAR_TX_TUS_L, 3856 phy_tus); 3857 if (err) 3858 return err; 3859 3860 /* P_REG_PAR_RX_TUS */ 3861 if (e822_vernier[link_spd].rx_par_clk) 3862 phy_tus = div_u64(tu_per_sec, 3863 e822_vernier[link_spd].rx_par_clk); 3864 else 3865 phy_tus = 0; 3866 3867 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PAR_RX_TUS_L, 3868 phy_tus); 3869 if (err) 3870 return err; 3871 3872 /* P_REG_PCS_TX_TUS */ 3873 if (e822_vernier[link_spd].tx_pcs_clk) 3874 phy_tus = div_u64(tu_per_sec, 3875 e822_vernier[link_spd].tx_pcs_clk); 3876 else 3877 phy_tus = 0; 3878 3879 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PCS_TX_TUS_L, 3880 phy_tus); 3881 if (err) 3882 return err; 3883 3884 /* P_REG_PCS_RX_TUS */ 3885 if (e822_vernier[link_spd].rx_pcs_clk) 3886 phy_tus = div_u64(tu_per_sec, 3887 e822_vernier[link_spd].rx_pcs_clk); 3888 else 3889 phy_tus = 0; 3890 3891 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PCS_RX_TUS_L, 3892 phy_tus); 3893 if (err) 3894 return err; 3895 3896 /* P_REG_DESK_PAR_TX_TUS */ 3897 if (e822_vernier[link_spd].tx_desk_rsgb_par) 3898 phy_tus = div_u64(tu_per_sec, 3899 e822_vernier[link_spd].tx_desk_rsgb_par); 3900 else 3901 phy_tus = 0; 3902 3903 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PAR_TX_TUS_L, 3904 phy_tus); 3905 if (err) 3906 return err; 3907 3908 /* P_REG_DESK_PAR_RX_TUS */ 3909 if (e822_vernier[link_spd].rx_desk_rsgb_par) 3910 phy_tus = div_u64(tu_per_sec, 3911 e822_vernier[link_spd].rx_desk_rsgb_par); 3912 else 3913 phy_tus = 0; 3914 3915 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PAR_RX_TUS_L, 3916 phy_tus); 3917 if (err) 3918 return err; 3919 3920 /* P_REG_DESK_PCS_TX_TUS */ 3921 if (e822_vernier[link_spd].tx_desk_rsgb_pcs) 3922 phy_tus = div_u64(tu_per_sec, 3923 e822_vernier[link_spd].tx_desk_rsgb_pcs); 3924 else 3925 phy_tus = 0; 3926 3927 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PCS_TX_TUS_L, 3928 phy_tus); 3929 if (err) 3930 return err; 3931 3932 /* P_REG_DESK_PCS_RX_TUS */ 3933 if (e822_vernier[link_spd].rx_desk_rsgb_pcs) 3934 phy_tus = div_u64(tu_per_sec, 3935 e822_vernier[link_spd].rx_desk_rsgb_pcs); 3936 else 3937 phy_tus = 0; 3938 3939 return ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PCS_RX_TUS_L, 3940 phy_tus); 3941 } 3942 3943 /** 3944 * ice_calc_fixed_tx_offset_e82x - Calculated Fixed Tx offset for a port 3945 * @hw: pointer to the HW struct 3946 * @link_spd: the Link speed to calculate for 3947 * 3948 * Calculate the fixed offset due to known static latency data. 3949 */ 3950 static u64 3951 ice_calc_fixed_tx_offset_e82x(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) 3952 { 3953 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset; 3954 3955 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3956 clk_incval = ice_ptp_read_src_incval(hw); 3957 3958 /* Calculate TUs per second */ 3959 tu_per_sec = cur_freq * clk_incval; 3960 3961 /* Calculate number of TUs to add for the fixed Tx latency. Since the 3962 * latency measurement is in 1/100th of a nanosecond, we need to 3963 * multiply by tu_per_sec and then divide by 1e11. This calculation 3964 * overflows 64 bit integer arithmetic, so break it up into two 3965 * divisions by 1e4 first then by 1e7. 3966 */ 3967 fixed_offset = div_u64(tu_per_sec, 10000); 3968 fixed_offset *= e822_vernier[link_spd].tx_fixed_delay; 3969 fixed_offset = div_u64(fixed_offset, 10000000); 3970 3971 return fixed_offset; 3972 } 3973 3974 /** 3975 * ice_phy_cfg_tx_offset_e82x - Configure total Tx timestamp offset 3976 * @hw: pointer to the HW struct 3977 * @port: the PHY port to configure 3978 * 3979 * Program the P_REG_TOTAL_TX_OFFSET register with the total number of TUs to 3980 * adjust Tx timestamps by. This is calculated by combining some known static 3981 * latency along with the Vernier offset computations done by hardware. 3982 * 3983 * This function will not return successfully until the Tx offset calculations 3984 * have been completed, which requires waiting until at least one packet has 3985 * been transmitted by the device. It is safe to call this function 3986 * periodically until calibration succeeds, as it will only program the offset 3987 * once. 3988 * 3989 * To avoid overflow, when calculating the offset based on the known static 3990 * latency values, we use measurements in 1/100th of a nanosecond, and divide 3991 * the TUs per second up front. This avoids overflow while allowing 3992 * calculation of the adjustment using integer arithmetic. 3993 * 3994 * Returns zero on success, -EBUSY if the hardware vernier offset 3995 * calibration has not completed, or another error code on failure. 3996 */ 3997 int ice_phy_cfg_tx_offset_e82x(struct ice_hw *hw, u8 port) 3998 { 3999 enum ice_ptp_link_spd link_spd; 4000 enum ice_ptp_fec_mode fec_mode; 4001 u64 total_offset, val; 4002 int err; 4003 u32 reg; 4004 4005 /* Nothing to do if we've already programmed the offset */ 4006 err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_OR, ®); 4007 if (err) { 4008 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OR for port %u, err %d\n", 4009 port, err); 4010 return err; 4011 } 4012 4013 if (reg) 4014 return 0; 4015 4016 err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_OV_STATUS, ®); 4017 if (err) { 4018 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OV_STATUS for port %u, err %d\n", 4019 port, err); 4020 return err; 4021 } 4022 4023 if (!(reg & P_REG_TX_OV_STATUS_OV_M)) 4024 return -EBUSY; 4025 4026 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode); 4027 if (err) 4028 return err; 4029 4030 total_offset = ice_calc_fixed_tx_offset_e82x(hw, link_spd); 4031 4032 /* Read the first Vernier offset from the PHY register and add it to 4033 * the total offset. 4034 */ 4035 if (link_spd == ICE_PTP_LNK_SPD_1G || 4036 link_spd == ICE_PTP_LNK_SPD_10G || 4037 link_spd == ICE_PTP_LNK_SPD_25G || 4038 link_spd == ICE_PTP_LNK_SPD_25G_RS || 4039 link_spd == ICE_PTP_LNK_SPD_40G || 4040 link_spd == ICE_PTP_LNK_SPD_50G) { 4041 err = ice_read_64b_phy_reg_e82x(hw, port, 4042 P_REG_PAR_PCS_TX_OFFSET_L, 4043 &val); 4044 if (err) 4045 return err; 4046 4047 total_offset += val; 4048 } 4049 4050 /* For Tx, we only need to use the second Vernier offset for 4051 * multi-lane link speeds with RS-FEC. The lanes will always be 4052 * aligned. 4053 */ 4054 if (link_spd == ICE_PTP_LNK_SPD_50G_RS || 4055 link_spd == ICE_PTP_LNK_SPD_100G_RS) { 4056 err = ice_read_64b_phy_reg_e82x(hw, port, 4057 P_REG_PAR_TX_TIME_L, 4058 &val); 4059 if (err) 4060 return err; 4061 4062 total_offset += val; 4063 } 4064 4065 /* Now that the total offset has been calculated, program it to the 4066 * PHY and indicate that the Tx offset is ready. After this, 4067 * timestamps will be enabled. 4068 */ 4069 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_TOTAL_TX_OFFSET_L, 4070 total_offset); 4071 if (err) 4072 return err; 4073 4074 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 1); 4075 if (err) 4076 return err; 4077 4078 dev_info(ice_hw_to_dev(hw), "Port=%d Tx vernier offset calibration complete\n", 4079 port); 4080 4081 return 0; 4082 } 4083 4084 /** 4085 * ice_phy_calc_pmd_adj_e82x - Calculate PMD adjustment for Rx 4086 * @hw: pointer to the HW struct 4087 * @port: the PHY port to adjust for 4088 * @link_spd: the current link speed of the PHY 4089 * @fec_mode: the current FEC mode of the PHY 4090 * @pmd_adj: on return, the amount to adjust the Rx total offset by 4091 * 4092 * Calculates the adjustment to Rx timestamps due to PMD alignment in the PHY. 4093 * This varies by link speed and FEC mode. The value calculated accounts for 4094 * various delays caused when receiving a packet. 4095 */ 4096 static int 4097 ice_phy_calc_pmd_adj_e82x(struct ice_hw *hw, u8 port, 4098 enum ice_ptp_link_spd link_spd, 4099 enum ice_ptp_fec_mode fec_mode, u64 *pmd_adj) 4100 { 4101 u64 cur_freq, clk_incval, tu_per_sec, mult, adj; 4102 u8 pmd_align; 4103 u32 val; 4104 int err; 4105 4106 err = ice_read_phy_reg_e82x(hw, port, P_REG_PMD_ALIGNMENT, &val); 4107 if (err) { 4108 ice_debug(hw, ICE_DBG_PTP, "Failed to read PMD alignment, err %d\n", 4109 err); 4110 return err; 4111 } 4112 4113 pmd_align = (u8)val; 4114 4115 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 4116 clk_incval = ice_ptp_read_src_incval(hw); 4117 4118 /* Calculate TUs per second */ 4119 tu_per_sec = cur_freq * clk_incval; 4120 4121 /* The PMD alignment adjustment measurement depends on the link speed, 4122 * and whether FEC is enabled. For each link speed, the alignment 4123 * adjustment is calculated by dividing a value by the length of 4124 * a Time Unit in nanoseconds. 4125 * 4126 * 1G: align == 4 ? 10 * 0.8 : (align + 6 % 10) * 0.8 4127 * 10G: align == 65 ? 0 : (align * 0.1 * 32/33) 4128 * 10G w/FEC: align * 0.1 * 32/33 4129 * 25G: align == 65 ? 0 : (align * 0.4 * 32/33) 4130 * 25G w/FEC: align * 0.4 * 32/33 4131 * 40G: align == 65 ? 0 : (align * 0.1 * 32/33) 4132 * 40G w/FEC: align * 0.1 * 32/33 4133 * 50G: align == 65 ? 0 : (align * 0.4 * 32/33) 4134 * 50G w/FEC: align * 0.8 * 32/33 4135 * 4136 * For RS-FEC, if align is < 17 then we must also add 1.6 * 32/33. 4137 * 4138 * To allow for calculating this value using integer arithmetic, we 4139 * instead start with the number of TUs per second, (inverse of the 4140 * length of a Time Unit in nanoseconds), multiply by a value based 4141 * on the PMD alignment register, and then divide by the right value 4142 * calculated based on the table above. To avoid integer overflow this 4143 * division is broken up into a step of dividing by 125 first. 4144 */ 4145 if (link_spd == ICE_PTP_LNK_SPD_1G) { 4146 if (pmd_align == 4) 4147 mult = 10; 4148 else 4149 mult = (pmd_align + 6) % 10; 4150 } else if (link_spd == ICE_PTP_LNK_SPD_10G || 4151 link_spd == ICE_PTP_LNK_SPD_25G || 4152 link_spd == ICE_PTP_LNK_SPD_40G || 4153 link_spd == ICE_PTP_LNK_SPD_50G) { 4154 /* If Clause 74 FEC, always calculate PMD adjust */ 4155 if (pmd_align != 65 || fec_mode == ICE_PTP_FEC_MODE_CLAUSE74) 4156 mult = pmd_align; 4157 else 4158 mult = 0; 4159 } else if (link_spd == ICE_PTP_LNK_SPD_25G_RS || 4160 link_spd == ICE_PTP_LNK_SPD_50G_RS || 4161 link_spd == ICE_PTP_LNK_SPD_100G_RS) { 4162 if (pmd_align < 17) 4163 mult = pmd_align + 40; 4164 else 4165 mult = pmd_align; 4166 } else { 4167 ice_debug(hw, ICE_DBG_PTP, "Unknown link speed %d, skipping PMD adjustment\n", 4168 link_spd); 4169 mult = 0; 4170 } 4171 4172 /* In some cases, there's no need to adjust for the PMD alignment */ 4173 if (!mult) { 4174 *pmd_adj = 0; 4175 return 0; 4176 } 4177 4178 /* Calculate the adjustment by multiplying TUs per second by the 4179 * appropriate multiplier and divisor. To avoid overflow, we first 4180 * divide by 125, and then handle remaining divisor based on the link 4181 * speed pmd_adj_divisor value. 4182 */ 4183 adj = div_u64(tu_per_sec, 125); 4184 adj *= mult; 4185 adj = div_u64(adj, e822_vernier[link_spd].pmd_adj_divisor); 4186 4187 /* Finally, for 25G-RS and 50G-RS, a further adjustment for the Rx 4188 * cycle count is necessary. 4189 */ 4190 if (link_spd == ICE_PTP_LNK_SPD_25G_RS) { 4191 u64 cycle_adj; 4192 u8 rx_cycle; 4193 4194 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_40_TO_160_CNT, 4195 &val); 4196 if (err) { 4197 ice_debug(hw, ICE_DBG_PTP, "Failed to read 25G-RS Rx cycle count, err %d\n", 4198 err); 4199 return err; 4200 } 4201 4202 rx_cycle = val & P_REG_RX_40_TO_160_CNT_RXCYC_M; 4203 if (rx_cycle) { 4204 mult = (4 - rx_cycle) * 40; 4205 4206 cycle_adj = div_u64(tu_per_sec, 125); 4207 cycle_adj *= mult; 4208 cycle_adj = div_u64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor); 4209 4210 adj += cycle_adj; 4211 } 4212 } else if (link_spd == ICE_PTP_LNK_SPD_50G_RS) { 4213 u64 cycle_adj; 4214 u8 rx_cycle; 4215 4216 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_80_TO_160_CNT, 4217 &val); 4218 if (err) { 4219 ice_debug(hw, ICE_DBG_PTP, "Failed to read 50G-RS Rx cycle count, err %d\n", 4220 err); 4221 return err; 4222 } 4223 4224 rx_cycle = val & P_REG_RX_80_TO_160_CNT_RXCYC_M; 4225 if (rx_cycle) { 4226 mult = rx_cycle * 40; 4227 4228 cycle_adj = div_u64(tu_per_sec, 125); 4229 cycle_adj *= mult; 4230 cycle_adj = div_u64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor); 4231 4232 adj += cycle_adj; 4233 } 4234 } 4235 4236 /* Return the calculated adjustment */ 4237 *pmd_adj = adj; 4238 4239 return 0; 4240 } 4241 4242 /** 4243 * ice_calc_fixed_rx_offset_e82x - Calculated the fixed Rx offset for a port 4244 * @hw: pointer to HW struct 4245 * @link_spd: The Link speed to calculate for 4246 * 4247 * Determine the fixed Rx latency for a given link speed. 4248 */ 4249 static u64 4250 ice_calc_fixed_rx_offset_e82x(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) 4251 { 4252 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset; 4253 4254 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 4255 clk_incval = ice_ptp_read_src_incval(hw); 4256 4257 /* Calculate TUs per second */ 4258 tu_per_sec = cur_freq * clk_incval; 4259 4260 /* Calculate number of TUs to add for the fixed Rx latency. Since the 4261 * latency measurement is in 1/100th of a nanosecond, we need to 4262 * multiply by tu_per_sec and then divide by 1e11. This calculation 4263 * overflows 64 bit integer arithmetic, so break it up into two 4264 * divisions by 1e4 first then by 1e7. 4265 */ 4266 fixed_offset = div_u64(tu_per_sec, 10000); 4267 fixed_offset *= e822_vernier[link_spd].rx_fixed_delay; 4268 fixed_offset = div_u64(fixed_offset, 10000000); 4269 4270 return fixed_offset; 4271 } 4272 4273 /** 4274 * ice_phy_cfg_rx_offset_e82x - Configure total Rx timestamp offset 4275 * @hw: pointer to the HW struct 4276 * @port: the PHY port to configure 4277 * 4278 * Program the P_REG_TOTAL_RX_OFFSET register with the number of Time Units to 4279 * adjust Rx timestamps by. This combines calculations from the Vernier offset 4280 * measurements taken in hardware with some data about known fixed delay as 4281 * well as adjusting for multi-lane alignment delay. 4282 * 4283 * This function will not return successfully until the Rx offset calculations 4284 * have been completed, which requires waiting until at least one packet has 4285 * been received by the device. It is safe to call this function periodically 4286 * until calibration succeeds, as it will only program the offset once. 4287 * 4288 * This function must be called only after the offset registers are valid, 4289 * i.e. after the Vernier calibration wait has passed, to ensure that the PHY 4290 * has measured the offset. 4291 * 4292 * To avoid overflow, when calculating the offset based on the known static 4293 * latency values, we use measurements in 1/100th of a nanosecond, and divide 4294 * the TUs per second up front. This avoids overflow while allowing 4295 * calculation of the adjustment using integer arithmetic. 4296 * 4297 * Returns zero on success, -EBUSY if the hardware vernier offset 4298 * calibration has not completed, or another error code on failure. 4299 */ 4300 int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port) 4301 { 4302 enum ice_ptp_link_spd link_spd; 4303 enum ice_ptp_fec_mode fec_mode; 4304 u64 total_offset, pmd, val; 4305 int err; 4306 u32 reg; 4307 4308 /* Nothing to do if we've already programmed the offset */ 4309 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_OR, ®); 4310 if (err) { 4311 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OR for port %u, err %d\n", 4312 port, err); 4313 return err; 4314 } 4315 4316 if (reg) 4317 return 0; 4318 4319 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_OV_STATUS, ®); 4320 if (err) { 4321 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OV_STATUS for port %u, err %d\n", 4322 port, err); 4323 return err; 4324 } 4325 4326 if (!(reg & P_REG_RX_OV_STATUS_OV_M)) 4327 return -EBUSY; 4328 4329 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode); 4330 if (err) 4331 return err; 4332 4333 total_offset = ice_calc_fixed_rx_offset_e82x(hw, link_spd); 4334 4335 /* Read the first Vernier offset from the PHY register and add it to 4336 * the total offset. 4337 */ 4338 err = ice_read_64b_phy_reg_e82x(hw, port, 4339 P_REG_PAR_PCS_RX_OFFSET_L, 4340 &val); 4341 if (err) 4342 return err; 4343 4344 total_offset += val; 4345 4346 /* For Rx, all multi-lane link speeds include a second Vernier 4347 * calibration, because the lanes might not be aligned. 4348 */ 4349 if (link_spd == ICE_PTP_LNK_SPD_40G || 4350 link_spd == ICE_PTP_LNK_SPD_50G || 4351 link_spd == ICE_PTP_LNK_SPD_50G_RS || 4352 link_spd == ICE_PTP_LNK_SPD_100G_RS) { 4353 err = ice_read_64b_phy_reg_e82x(hw, port, 4354 P_REG_PAR_RX_TIME_L, 4355 &val); 4356 if (err) 4357 return err; 4358 4359 total_offset += val; 4360 } 4361 4362 /* In addition, Rx must account for the PMD alignment */ 4363 err = ice_phy_calc_pmd_adj_e82x(hw, port, link_spd, fec_mode, &pmd); 4364 if (err) 4365 return err; 4366 4367 /* For RS-FEC, this adjustment adds delay, but for other modes, it 4368 * subtracts delay. 4369 */ 4370 if (fec_mode == ICE_PTP_FEC_MODE_RS_FEC) 4371 total_offset += pmd; 4372 else 4373 total_offset -= pmd; 4374 4375 /* Now that the total offset has been calculated, program it to the 4376 * PHY and indicate that the Rx offset is ready. After this, 4377 * timestamps will be enabled. 4378 */ 4379 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_TOTAL_RX_OFFSET_L, 4380 total_offset); 4381 if (err) 4382 return err; 4383 4384 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 1); 4385 if (err) 4386 return err; 4387 4388 dev_info(ice_hw_to_dev(hw), "Port=%d Rx vernier offset calibration complete\n", 4389 port); 4390 4391 return 0; 4392 } 4393 4394 /** 4395 * ice_ptp_clear_phy_offset_ready_e82x - Clear PHY TX_/RX_OFFSET_READY registers 4396 * @hw: pointer to the HW struct 4397 * 4398 * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted 4399 * and received timestamps as invalid. 4400 * 4401 * Return: 0 on success, other error codes when failed to write to PHY 4402 */ 4403 int ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw *hw) 4404 { 4405 u8 port; 4406 4407 for (port = 0; port < hw->ptp.num_lports; port++) { 4408 int err; 4409 4410 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0); 4411 if (err) { 4412 dev_warn(ice_hw_to_dev(hw), 4413 "Failed to clear PHY TX_OFFSET_READY register\n"); 4414 return err; 4415 } 4416 4417 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0); 4418 if (err) { 4419 dev_warn(ice_hw_to_dev(hw), 4420 "Failed to clear PHY RX_OFFSET_READY register\n"); 4421 return err; 4422 } 4423 } 4424 4425 return 0; 4426 } 4427 4428 /** 4429 * ice_read_phy_and_phc_time_e82x - Simultaneously capture PHC and PHY time 4430 * @hw: pointer to the HW struct 4431 * @port: the PHY port to read 4432 * @phy_time: on return, the 64bit PHY timer value 4433 * @phc_time: on return, the lower 64bits of PHC time 4434 * 4435 * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY 4436 * and PHC timer values. 4437 */ 4438 static int 4439 ice_read_phy_and_phc_time_e82x(struct ice_hw *hw, u8 port, u64 *phy_time, 4440 u64 *phc_time) 4441 { 4442 u64 tx_time, rx_time; 4443 u32 zo, lo; 4444 u8 tmr_idx; 4445 int err; 4446 4447 tmr_idx = ice_get_ptp_src_clock_index(hw); 4448 4449 /* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */ 4450 ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME); 4451 4452 /* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */ 4453 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME); 4454 if (err) 4455 return err; 4456 4457 /* Issue the sync to start the ICE_PTP_READ_TIME capture */ 4458 ice_ptp_exec_tmr_cmd(hw); 4459 4460 /* Read the captured PHC time from the shadow time registers */ 4461 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx)); 4462 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx)); 4463 *phc_time = (u64)lo << 32 | zo; 4464 4465 /* Read the captured PHY time from the PHY shadow registers */ 4466 err = ice_ptp_read_port_capture(hw, port, &tx_time, &rx_time); 4467 if (err) 4468 return err; 4469 4470 /* If the PHY Tx and Rx timers don't match, log a warning message. 4471 * Note that this should not happen in normal circumstances since the 4472 * driver always programs them together. 4473 */ 4474 if (tx_time != rx_time) 4475 dev_warn(ice_hw_to_dev(hw), 4476 "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n", 4477 port, (unsigned long long)tx_time, 4478 (unsigned long long)rx_time); 4479 4480 *phy_time = tx_time; 4481 4482 return 0; 4483 } 4484 4485 /** 4486 * ice_sync_phy_timer_e82x - Synchronize the PHY timer with PHC timer 4487 * @hw: pointer to the HW struct 4488 * @port: the PHY port to synchronize 4489 * 4490 * Perform an adjustment to ensure that the PHY and PHC timers are in sync. 4491 * This is done by issuing a ICE_PTP_READ_TIME command which triggers a 4492 * simultaneous read of the PHY timer and PHC timer. Then we use the 4493 * difference to calculate an appropriate 2s complement addition to add 4494 * to the PHY timer in order to ensure it reads the same value as the 4495 * primary PHC timer. 4496 */ 4497 static int ice_sync_phy_timer_e82x(struct ice_hw *hw, u8 port) 4498 { 4499 u64 phc_time, phy_time, difference; 4500 int err; 4501 4502 if (!ice_ptp_lock(hw)) { 4503 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n"); 4504 return -EBUSY; 4505 } 4506 4507 err = ice_read_phy_and_phc_time_e82x(hw, port, &phy_time, &phc_time); 4508 if (err) 4509 goto err_unlock; 4510 4511 /* Calculate the amount required to add to the port time in order for 4512 * it to match the PHC time. 4513 * 4514 * Note that the port adjustment is done using 2s complement 4515 * arithmetic. This is convenient since it means that we can simply 4516 * calculate the difference between the PHC time and the port time, 4517 * and it will be interpreted correctly. 4518 */ 4519 difference = phc_time - phy_time; 4520 4521 err = ice_ptp_prep_port_adj_e82x(hw, port, (s64)difference); 4522 if (err) 4523 goto err_unlock; 4524 4525 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME); 4526 if (err) 4527 goto err_unlock; 4528 4529 /* Do not perform any action on the main timer */ 4530 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 4531 4532 /* Issue the sync to activate the time adjustment */ 4533 ice_ptp_exec_tmr_cmd(hw); 4534 4535 /* Re-capture the timer values to flush the command registers and 4536 * verify that the time was properly adjusted. 4537 */ 4538 err = ice_read_phy_and_phc_time_e82x(hw, port, &phy_time, &phc_time); 4539 if (err) 4540 goto err_unlock; 4541 4542 dev_info(ice_hw_to_dev(hw), 4543 "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n", 4544 port, (unsigned long long)phy_time, 4545 (unsigned long long)phc_time); 4546 4547 ice_ptp_unlock(hw); 4548 4549 return 0; 4550 4551 err_unlock: 4552 ice_ptp_unlock(hw); 4553 return err; 4554 } 4555 4556 /** 4557 * ice_stop_phy_timer_e82x - Stop the PHY clock timer 4558 * @hw: pointer to the HW struct 4559 * @port: the PHY port to stop 4560 * @soft_reset: if true, hold the SOFT_RESET bit of P_REG_PS 4561 * 4562 * Stop the clock of a PHY port. This must be done as part of the flow to 4563 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 4564 * initialized or when link speed changes. 4565 */ 4566 int 4567 ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset) 4568 { 4569 int err; 4570 u32 val; 4571 4572 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0); 4573 if (err) 4574 return err; 4575 4576 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0); 4577 if (err) 4578 return err; 4579 4580 err = ice_read_phy_reg_e82x(hw, port, P_REG_PS, &val); 4581 if (err) 4582 return err; 4583 4584 val &= ~P_REG_PS_START_M; 4585 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4586 if (err) 4587 return err; 4588 4589 val &= ~P_REG_PS_ENA_CLK_M; 4590 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4591 if (err) 4592 return err; 4593 4594 if (soft_reset) { 4595 val |= P_REG_PS_SFT_RESET_M; 4596 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4597 if (err) 4598 return err; 4599 } 4600 4601 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port); 4602 4603 return 0; 4604 } 4605 4606 /** 4607 * ice_start_phy_timer_e82x - Start the PHY clock timer 4608 * @hw: pointer to the HW struct 4609 * @port: the PHY port to start 4610 * 4611 * Start the clock of a PHY port. This must be done as part of the flow to 4612 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 4613 * initialized or when link speed changes. 4614 * 4615 * Hardware will take Vernier measurements on Tx or Rx of packets. 4616 */ 4617 int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port) 4618 { 4619 u32 lo, hi, val; 4620 u64 incval; 4621 u8 tmr_idx; 4622 int err; 4623 4624 tmr_idx = ice_get_ptp_src_clock_index(hw); 4625 4626 err = ice_stop_phy_timer_e82x(hw, port, false); 4627 if (err) 4628 return err; 4629 4630 ice_phy_cfg_lane_e82x(hw, port); 4631 4632 err = ice_phy_cfg_uix_e82x(hw, port); 4633 if (err) 4634 return err; 4635 4636 err = ice_phy_cfg_parpcs_e82x(hw, port); 4637 if (err) 4638 return err; 4639 4640 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 4641 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 4642 incval = (u64)hi << 32 | lo; 4643 4644 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L, incval); 4645 if (err) 4646 return err; 4647 4648 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL); 4649 if (err) 4650 return err; 4651 4652 /* Do not perform any action on the main timer */ 4653 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 4654 4655 ice_ptp_exec_tmr_cmd(hw); 4656 4657 err = ice_read_phy_reg_e82x(hw, port, P_REG_PS, &val); 4658 if (err) 4659 return err; 4660 4661 val |= P_REG_PS_SFT_RESET_M; 4662 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4663 if (err) 4664 return err; 4665 4666 val |= P_REG_PS_START_M; 4667 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4668 if (err) 4669 return err; 4670 4671 val &= ~P_REG_PS_SFT_RESET_M; 4672 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4673 if (err) 4674 return err; 4675 4676 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL); 4677 if (err) 4678 return err; 4679 4680 ice_ptp_exec_tmr_cmd(hw); 4681 4682 val |= P_REG_PS_ENA_CLK_M; 4683 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4684 if (err) 4685 return err; 4686 4687 val |= P_REG_PS_LOAD_OFFSET_M; 4688 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4689 if (err) 4690 return err; 4691 4692 ice_ptp_exec_tmr_cmd(hw); 4693 4694 err = ice_sync_phy_timer_e82x(hw, port); 4695 if (err) 4696 return err; 4697 4698 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port); 4699 4700 return 0; 4701 } 4702 4703 /** 4704 * ice_get_phy_tx_tstamp_ready_e82x - Read Tx memory status register 4705 * @hw: pointer to the HW struct 4706 * @quad: the timestamp quad to read from 4707 * @tstamp_ready: contents of the Tx memory status register 4708 * 4709 * Read the Q_REG_TX_MEMORY_STATUS register indicating which timestamps in 4710 * the PHY are ready. A set bit means the corresponding timestamp is valid and 4711 * ready to be captured from the PHY timestamp block. 4712 */ 4713 static int 4714 ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw *hw, u8 quad, u64 *tstamp_ready) 4715 { 4716 u32 hi, lo; 4717 int err; 4718 4719 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_U, &hi); 4720 if (err) { 4721 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_U for quad %u, err %d\n", 4722 quad, err); 4723 return err; 4724 } 4725 4726 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_L, &lo); 4727 if (err) { 4728 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_L for quad %u, err %d\n", 4729 quad, err); 4730 return err; 4731 } 4732 4733 *tstamp_ready = (u64)hi << 32 | (u64)lo; 4734 4735 return 0; 4736 } 4737 4738 /** 4739 * ice_phy_cfg_intr_e82x - Configure TX timestamp interrupt 4740 * @hw: pointer to the HW struct 4741 * @quad: the timestamp quad 4742 * @ena: enable or disable interrupt 4743 * @threshold: interrupt threshold 4744 * 4745 * Configure TX timestamp interrupt for the specified quad 4746 * 4747 * Return: 0 on success, other error codes when failed to read/write quad 4748 */ 4749 4750 int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold) 4751 { 4752 int err; 4753 u32 val; 4754 4755 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val); 4756 if (err) 4757 return err; 4758 4759 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M; 4760 if (ena) { 4761 val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M; 4762 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M; 4763 val |= FIELD_PREP(Q_REG_TX_MEM_GBL_CFG_INTR_THR_M, threshold); 4764 } 4765 4766 return ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val); 4767 } 4768 4769 /** 4770 * ice_ptp_init_phy_e82x - initialize PHY parameters 4771 * @ptp: pointer to the PTP HW struct 4772 */ 4773 static void ice_ptp_init_phy_e82x(struct ice_ptp_hw *ptp) 4774 { 4775 ptp->phy_model = ICE_PHY_E82X; 4776 ptp->num_lports = 8; 4777 ptp->ports_per_phy = 8; 4778 } 4779 4780 /* E810 functions 4781 * 4782 * The following functions operate on the E810 series devices which use 4783 * a separate external PHY. 4784 */ 4785 4786 /** 4787 * ice_read_phy_reg_e810 - Read register from external PHY on E810 4788 * @hw: pointer to the HW struct 4789 * @addr: the address to read from 4790 * @val: On return, the value read from the PHY 4791 * 4792 * Read a register from the external PHY on the E810 device. 4793 */ 4794 static int ice_read_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 *val) 4795 { 4796 struct ice_sbq_msg_input msg = {0}; 4797 int err; 4798 4799 msg.msg_addr_low = lower_16_bits(addr); 4800 msg.msg_addr_high = upper_16_bits(addr); 4801 msg.opcode = ice_sbq_msg_rd; 4802 msg.dest_dev = rmn_0; 4803 4804 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 4805 if (err) { 4806 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 4807 err); 4808 return err; 4809 } 4810 4811 *val = msg.data; 4812 4813 return 0; 4814 } 4815 4816 /** 4817 * ice_write_phy_reg_e810 - Write register on external PHY on E810 4818 * @hw: pointer to the HW struct 4819 * @addr: the address to writem to 4820 * @val: the value to write to the PHY 4821 * 4822 * Write a value to a register of the external PHY on the E810 device. 4823 */ 4824 static int ice_write_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 val) 4825 { 4826 struct ice_sbq_msg_input msg = {0}; 4827 int err; 4828 4829 msg.msg_addr_low = lower_16_bits(addr); 4830 msg.msg_addr_high = upper_16_bits(addr); 4831 msg.opcode = ice_sbq_msg_wr; 4832 msg.dest_dev = rmn_0; 4833 msg.data = val; 4834 4835 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 4836 if (err) { 4837 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 4838 err); 4839 return err; 4840 } 4841 4842 return 0; 4843 } 4844 4845 /** 4846 * ice_read_phy_tstamp_ll_e810 - Read a PHY timestamp registers through the FW 4847 * @hw: pointer to the HW struct 4848 * @idx: the timestamp index to read 4849 * @hi: 8 bit timestamp high value 4850 * @lo: 32 bit timestamp low value 4851 * 4852 * Read a 8bit timestamp high value and 32 bit timestamp low value out of the 4853 * timestamp block of the external PHY on the E810 device using the low latency 4854 * timestamp read. 4855 */ 4856 static int 4857 ice_read_phy_tstamp_ll_e810(struct ice_hw *hw, u8 idx, u8 *hi, u32 *lo) 4858 { 4859 u32 val; 4860 u8 i; 4861 4862 /* Write TS index to read to the PF register so the FW can read it */ 4863 val = FIELD_PREP(TS_LL_READ_TS_IDX, idx) | TS_LL_READ_TS; 4864 wr32(hw, PF_SB_ATQBAL, val); 4865 4866 /* Read the register repeatedly until the FW provides us the TS */ 4867 for (i = TS_LL_READ_RETRIES; i > 0; i--) { 4868 val = rd32(hw, PF_SB_ATQBAL); 4869 4870 /* When the bit is cleared, the TS is ready in the register */ 4871 if (!(FIELD_GET(TS_LL_READ_TS, val))) { 4872 /* High 8 bit value of the TS is on the bits 16:23 */ 4873 *hi = FIELD_GET(TS_LL_READ_TS_HIGH, val); 4874 4875 /* Read the low 32 bit value and set the TS valid bit */ 4876 *lo = rd32(hw, PF_SB_ATQBAH) | TS_VALID; 4877 return 0; 4878 } 4879 4880 udelay(10); 4881 } 4882 4883 /* FW failed to provide the TS in time */ 4884 ice_debug(hw, ICE_DBG_PTP, "Failed to read PTP timestamp using low latency read\n"); 4885 return -EINVAL; 4886 } 4887 4888 /** 4889 * ice_read_phy_tstamp_sbq_e810 - Read a PHY timestamp registers through the sbq 4890 * @hw: pointer to the HW struct 4891 * @lport: the lport to read from 4892 * @idx: the timestamp index to read 4893 * @hi: 8 bit timestamp high value 4894 * @lo: 32 bit timestamp low value 4895 * 4896 * Read a 8bit timestamp high value and 32 bit timestamp low value out of the 4897 * timestamp block of the external PHY on the E810 device using sideband queue. 4898 */ 4899 static int 4900 ice_read_phy_tstamp_sbq_e810(struct ice_hw *hw, u8 lport, u8 idx, u8 *hi, 4901 u32 *lo) 4902 { 4903 u32 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); 4904 u32 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); 4905 u32 lo_val, hi_val; 4906 int err; 4907 4908 err = ice_read_phy_reg_e810(hw, lo_addr, &lo_val); 4909 if (err) { 4910 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 4911 err); 4912 return err; 4913 } 4914 4915 err = ice_read_phy_reg_e810(hw, hi_addr, &hi_val); 4916 if (err) { 4917 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 4918 err); 4919 return err; 4920 } 4921 4922 *lo = lo_val; 4923 *hi = (u8)hi_val; 4924 4925 return 0; 4926 } 4927 4928 /** 4929 * ice_read_phy_tstamp_e810 - Read a PHY timestamp out of the external PHY 4930 * @hw: pointer to the HW struct 4931 * @lport: the lport to read from 4932 * @idx: the timestamp index to read 4933 * @tstamp: on return, the 40bit timestamp value 4934 * 4935 * Read a 40bit timestamp value out of the timestamp block of the external PHY 4936 * on the E810 device. 4937 */ 4938 static int 4939 ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) 4940 { 4941 u32 lo = 0; 4942 u8 hi = 0; 4943 int err; 4944 4945 if (hw->dev_caps.ts_dev_info.ts_ll_read) 4946 err = ice_read_phy_tstamp_ll_e810(hw, idx, &hi, &lo); 4947 else 4948 err = ice_read_phy_tstamp_sbq_e810(hw, lport, idx, &hi, &lo); 4949 4950 if (err) 4951 return err; 4952 4953 /* For E810 devices, the timestamp is reported with the lower 32 bits 4954 * in the low register, and the upper 8 bits in the high register. 4955 */ 4956 *tstamp = ((u64)hi) << TS_HIGH_S | ((u64)lo & TS_LOW_M); 4957 4958 return 0; 4959 } 4960 4961 /** 4962 * ice_clear_phy_tstamp_e810 - Clear a timestamp from the external PHY 4963 * @hw: pointer to the HW struct 4964 * @lport: the lport to read from 4965 * @idx: the timestamp index to reset 4966 * 4967 * Read the timestamp and then forcibly overwrite its value to clear the valid 4968 * bit from the timestamp block of the external PHY on the E810 device. 4969 * 4970 * This function should only be called on an idx whose bit is set according to 4971 * ice_get_phy_tx_tstamp_ready(). 4972 */ 4973 static int ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx) 4974 { 4975 u32 lo_addr, hi_addr; 4976 u64 unused_tstamp; 4977 int err; 4978 4979 err = ice_read_phy_tstamp_e810(hw, lport, idx, &unused_tstamp); 4980 if (err) { 4981 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for lport %u, idx %u, err %d\n", 4982 lport, idx, err); 4983 return err; 4984 } 4985 4986 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); 4987 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); 4988 4989 err = ice_write_phy_reg_e810(hw, lo_addr, 0); 4990 if (err) { 4991 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for lport %u, idx %u, err %d\n", 4992 lport, idx, err); 4993 return err; 4994 } 4995 4996 err = ice_write_phy_reg_e810(hw, hi_addr, 0); 4997 if (err) { 4998 ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register for lport %u, idx %u, err %d\n", 4999 lport, idx, err); 5000 return err; 5001 } 5002 5003 return 0; 5004 } 5005 5006 /** 5007 * ice_ptp_init_phc_e810 - Perform E810 specific PHC initialization 5008 * @hw: pointer to HW struct 5009 * 5010 * Perform E810-specific PTP hardware clock initialization steps. 5011 * 5012 * Return: 0 on success, other error codes when failed to initialize TimeSync 5013 */ 5014 static int ice_ptp_init_phc_e810(struct ice_hw *hw) 5015 { 5016 u8 tmr_idx; 5017 int err; 5018 5019 /* Ensure synchronization delay is zero */ 5020 wr32(hw, GLTSYN_SYNC_DLAY, 0); 5021 5022 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5023 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_ENA(tmr_idx), 5024 GLTSYN_ENA_TSYN_ENA_M); 5025 if (err) 5026 ice_debug(hw, ICE_DBG_PTP, "PTP failed in ena_phy_time_syn %d\n", 5027 err); 5028 5029 return err; 5030 } 5031 5032 /** 5033 * ice_ptp_prep_phy_time_e810 - Prepare PHY port with initial time 5034 * @hw: Board private structure 5035 * @time: Time to initialize the PHY port clock to 5036 * 5037 * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the 5038 * initial clock time. The time will not actually be programmed until the 5039 * driver issues an ICE_PTP_INIT_TIME command. 5040 * 5041 * The time value is the upper 32 bits of the PHY timer, usually in units of 5042 * nominal nanoseconds. 5043 */ 5044 static int ice_ptp_prep_phy_time_e810(struct ice_hw *hw, u32 time) 5045 { 5046 u8 tmr_idx; 5047 int err; 5048 5049 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5050 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_0(tmr_idx), 0); 5051 if (err) { 5052 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_0, err %d\n", 5053 err); 5054 return err; 5055 } 5056 5057 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_L(tmr_idx), time); 5058 if (err) { 5059 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_L, err %d\n", 5060 err); 5061 return err; 5062 } 5063 5064 return 0; 5065 } 5066 5067 /** 5068 * ice_ptp_prep_phy_adj_e810 - Prep PHY port for a time adjustment 5069 * @hw: pointer to HW struct 5070 * @adj: adjustment value to program 5071 * 5072 * Prepare the PHY port for an atomic adjustment by programming the PHY 5073 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual adjustment 5074 * is completed by issuing an ICE_PTP_ADJ_TIME sync command. 5075 * 5076 * The adjustment value only contains the portion used for the upper 32bits of 5077 * the PHY timer, usually in units of nominal nanoseconds. Negative 5078 * adjustments are supported using 2s complement arithmetic. 5079 */ 5080 static int ice_ptp_prep_phy_adj_e810(struct ice_hw *hw, s32 adj) 5081 { 5082 u8 tmr_idx; 5083 int err; 5084 5085 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5086 5087 /* Adjustments are represented as signed 2's complement values in 5088 * nanoseconds. Sub-nanosecond adjustment is not supported. 5089 */ 5090 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), 0); 5091 if (err) { 5092 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_L, err %d\n", 5093 err); 5094 return err; 5095 } 5096 5097 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), adj); 5098 if (err) { 5099 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_H, err %d\n", 5100 err); 5101 return err; 5102 } 5103 5104 return 0; 5105 } 5106 5107 /** 5108 * ice_ptp_prep_phy_incval_e810 - Prep PHY port increment value change 5109 * @hw: pointer to HW struct 5110 * @incval: The new 40bit increment value to prepare 5111 * 5112 * Prepare the PHY port for a new increment value by programming the PHY 5113 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual change is 5114 * completed by issuing an ICE_PTP_INIT_INCVAL command. 5115 */ 5116 static int ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval) 5117 { 5118 u32 high, low; 5119 u8 tmr_idx; 5120 int err; 5121 5122 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5123 low = lower_32_bits(incval); 5124 high = upper_32_bits(incval); 5125 5126 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), low); 5127 if (err) { 5128 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval to PHY SHADJ_L, err %d\n", 5129 err); 5130 return err; 5131 } 5132 5133 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), high); 5134 if (err) { 5135 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval PHY SHADJ_H, err %d\n", 5136 err); 5137 return err; 5138 } 5139 5140 return 0; 5141 } 5142 5143 /** 5144 * ice_ptp_port_cmd_e810 - Prepare all external PHYs for a timer command 5145 * @hw: pointer to HW struct 5146 * @cmd: Command to be sent to the port 5147 * 5148 * Prepare the external PHYs connected to this device for a timer sync 5149 * command. 5150 */ 5151 static int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 5152 { 5153 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 5154 5155 return ice_write_phy_reg_e810(hw, E810_ETH_GLTSYN_CMD, val); 5156 } 5157 5158 /** 5159 * ice_get_phy_tx_tstamp_ready_e810 - Read Tx memory status register 5160 * @hw: pointer to the HW struct 5161 * @port: the PHY port to read 5162 * @tstamp_ready: contents of the Tx memory status register 5163 * 5164 * E810 devices do not use a Tx memory status register. Instead simply 5165 * indicate that all timestamps are currently ready. 5166 */ 5167 static int 5168 ice_get_phy_tx_tstamp_ready_e810(struct ice_hw *hw, u8 port, u64 *tstamp_ready) 5169 { 5170 *tstamp_ready = 0xFFFFFFFFFFFFFFFF; 5171 return 0; 5172 } 5173 5174 /* E810 SMA functions 5175 * 5176 * The following functions operate specifically on E810 hardware and are used 5177 * to access the extended GPIOs available. 5178 */ 5179 5180 /** 5181 * ice_get_pca9575_handle 5182 * @hw: pointer to the hw struct 5183 * @pca9575_handle: GPIO controller's handle 5184 * 5185 * Find and return the GPIO controller's handle in the netlist. 5186 * When found - the value will be cached in the hw structure and following calls 5187 * will return cached value 5188 */ 5189 static int 5190 ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) 5191 { 5192 struct ice_aqc_get_link_topo *cmd; 5193 struct ice_aq_desc desc; 5194 int status; 5195 u8 idx; 5196 5197 /* If handle was read previously return cached value */ 5198 if (hw->io_expander_handle) { 5199 *pca9575_handle = hw->io_expander_handle; 5200 return 0; 5201 } 5202 5203 /* If handle was not detected read it from the netlist */ 5204 cmd = &desc.params.get_link_topo; 5205 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 5206 5207 /* Set node type to GPIO controller */ 5208 cmd->addr.topo_params.node_type_ctx = 5209 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & 5210 ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL); 5211 5212 #define SW_PCA9575_SFP_TOPO_IDX 2 5213 #define SW_PCA9575_QSFP_TOPO_IDX 1 5214 5215 /* Check if the SW IO expander controlling SMA exists in the netlist. */ 5216 if (hw->device_id == ICE_DEV_ID_E810C_SFP) 5217 idx = SW_PCA9575_SFP_TOPO_IDX; 5218 else if (hw->device_id == ICE_DEV_ID_E810C_QSFP) 5219 idx = SW_PCA9575_QSFP_TOPO_IDX; 5220 else 5221 return -EOPNOTSUPP; 5222 5223 cmd->addr.topo_params.index = idx; 5224 5225 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5226 if (status) 5227 return -EOPNOTSUPP; 5228 5229 /* Verify if we found the right IO expander type */ 5230 if (desc.params.get_link_topo.node_part_num != 5231 ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575) 5232 return -EOPNOTSUPP; 5233 5234 /* If present save the handle and return it */ 5235 hw->io_expander_handle = 5236 le16_to_cpu(desc.params.get_link_topo.addr.handle); 5237 *pca9575_handle = hw->io_expander_handle; 5238 5239 return 0; 5240 } 5241 5242 /** 5243 * ice_read_sma_ctrl 5244 * @hw: pointer to the hw struct 5245 * @data: pointer to data to be read from the GPIO controller 5246 * 5247 * Read the SMA controller state. It is connected to pins 3-7 of Port 1 of the 5248 * PCA9575 expander, so only bits 3-7 in data are valid. 5249 */ 5250 int ice_read_sma_ctrl(struct ice_hw *hw, u8 *data) 5251 { 5252 int status; 5253 u16 handle; 5254 u8 i; 5255 5256 status = ice_get_pca9575_handle(hw, &handle); 5257 if (status) 5258 return status; 5259 5260 *data = 0; 5261 5262 for (i = ICE_SMA_MIN_BIT; i <= ICE_SMA_MAX_BIT; i++) { 5263 bool pin; 5264 5265 status = ice_aq_get_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET, 5266 &pin, NULL); 5267 if (status) 5268 break; 5269 *data |= (u8)(!pin) << i; 5270 } 5271 5272 return status; 5273 } 5274 5275 /** 5276 * ice_write_sma_ctrl 5277 * @hw: pointer to the hw struct 5278 * @data: data to be written to the GPIO controller 5279 * 5280 * Write the data to the SMA controller. It is connected to pins 3-7 of Port 1 5281 * of the PCA9575 expander, so only bits 3-7 in data are valid. 5282 */ 5283 int ice_write_sma_ctrl(struct ice_hw *hw, u8 data) 5284 { 5285 int status; 5286 u16 handle; 5287 u8 i; 5288 5289 status = ice_get_pca9575_handle(hw, &handle); 5290 if (status) 5291 return status; 5292 5293 for (i = ICE_SMA_MIN_BIT; i <= ICE_SMA_MAX_BIT; i++) { 5294 bool pin; 5295 5296 pin = !(data & (1 << i)); 5297 status = ice_aq_set_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET, 5298 pin, NULL); 5299 if (status) 5300 break; 5301 } 5302 5303 return status; 5304 } 5305 5306 /** 5307 * ice_read_pca9575_reg 5308 * @hw: pointer to the hw struct 5309 * @offset: GPIO controller register offset 5310 * @data: pointer to data to be read from the GPIO controller 5311 * 5312 * Read the register from the GPIO controller 5313 */ 5314 int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data) 5315 { 5316 struct ice_aqc_link_topo_addr link_topo; 5317 __le16 addr; 5318 u16 handle; 5319 int err; 5320 5321 memset(&link_topo, 0, sizeof(link_topo)); 5322 5323 err = ice_get_pca9575_handle(hw, &handle); 5324 if (err) 5325 return err; 5326 5327 link_topo.handle = cpu_to_le16(handle); 5328 link_topo.topo_params.node_type_ctx = 5329 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, 5330 ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED); 5331 5332 addr = cpu_to_le16((u16)offset); 5333 5334 return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL); 5335 } 5336 5337 /** 5338 * ice_ptp_read_sdp_ac - read SDP available connections section from NVM 5339 * @hw: pointer to the HW struct 5340 * @entries: returns the SDP available connections section from NVM 5341 * @num_entries: returns the number of valid entries 5342 * 5343 * Return: 0 on success, negative error code if NVM read failed or section does 5344 * not exist or is corrupted 5345 */ 5346 int ice_ptp_read_sdp_ac(struct ice_hw *hw, __le16 *entries, uint *num_entries) 5347 { 5348 __le16 data; 5349 u32 offset; 5350 int err; 5351 5352 err = ice_acquire_nvm(hw, ICE_RES_READ); 5353 if (err) 5354 goto exit; 5355 5356 /* Read the offset of SDP_AC */ 5357 offset = ICE_AQC_NVM_SDP_AC_PTR_OFFSET; 5358 err = ice_aq_read_nvm(hw, 0, offset, sizeof(data), &data, false, true, 5359 NULL); 5360 if (err) 5361 goto exit; 5362 5363 /* Check if section exist */ 5364 offset = FIELD_GET(ICE_AQC_NVM_SDP_AC_PTR_M, le16_to_cpu(data)); 5365 if (offset == ICE_AQC_NVM_SDP_AC_PTR_INVAL) { 5366 err = -EINVAL; 5367 goto exit; 5368 } 5369 5370 if (offset & ICE_AQC_NVM_SDP_AC_PTR_TYPE_M) { 5371 offset &= ICE_AQC_NVM_SDP_AC_PTR_M; 5372 offset *= ICE_AQC_NVM_SECTOR_UNIT; 5373 } else { 5374 offset *= sizeof(data); 5375 } 5376 5377 /* Skip reading section length and read the number of valid entries */ 5378 offset += sizeof(data); 5379 err = ice_aq_read_nvm(hw, 0, offset, sizeof(data), &data, false, true, 5380 NULL); 5381 if (err) 5382 goto exit; 5383 *num_entries = le16_to_cpu(data); 5384 5385 /* Read SDP configuration section */ 5386 offset += sizeof(data); 5387 err = ice_aq_read_nvm(hw, 0, offset, *num_entries * sizeof(data), 5388 entries, false, true, NULL); 5389 5390 exit: 5391 if (err) 5392 dev_dbg(ice_hw_to_dev(hw), "Failed to configure SDP connection section\n"); 5393 ice_release_nvm(hw); 5394 return err; 5395 } 5396 5397 /** 5398 * ice_ptp_init_phy_e810 - initialize PHY parameters 5399 * @ptp: pointer to the PTP HW struct 5400 */ 5401 static void ice_ptp_init_phy_e810(struct ice_ptp_hw *ptp) 5402 { 5403 ptp->phy_model = ICE_PHY_E810; 5404 ptp->num_lports = 8; 5405 ptp->ports_per_phy = 4; 5406 } 5407 5408 /* Device agnostic functions 5409 * 5410 * The following functions implement shared behavior common to both E822 and 5411 * E810 devices, possibly calling a device specific implementation where 5412 * necessary. 5413 */ 5414 5415 /** 5416 * ice_ptp_lock - Acquire PTP global semaphore register lock 5417 * @hw: pointer to the HW struct 5418 * 5419 * Acquire the global PTP hardware semaphore lock. Returns true if the lock 5420 * was acquired, false otherwise. 5421 * 5422 * The PFTSYN_SEM register sets the busy bit on read, returning the previous 5423 * value. If software sees the busy bit cleared, this means that this function 5424 * acquired the lock (and the busy bit is now set). If software sees the busy 5425 * bit set, it means that another function acquired the lock. 5426 * 5427 * Software must clear the busy bit with a write to release the lock for other 5428 * functions when done. 5429 */ 5430 bool ice_ptp_lock(struct ice_hw *hw) 5431 { 5432 u32 hw_lock; 5433 int i; 5434 5435 #define MAX_TRIES 15 5436 5437 for (i = 0; i < MAX_TRIES; i++) { 5438 hw_lock = rd32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id)); 5439 hw_lock = hw_lock & PFTSYN_SEM_BUSY_M; 5440 if (hw_lock) { 5441 /* Somebody is holding the lock */ 5442 usleep_range(5000, 6000); 5443 continue; 5444 } 5445 5446 break; 5447 } 5448 5449 return !hw_lock; 5450 } 5451 5452 /** 5453 * ice_ptp_unlock - Release PTP global semaphore register lock 5454 * @hw: pointer to the HW struct 5455 * 5456 * Release the global PTP hardware semaphore lock. This is done by writing to 5457 * the PFTSYN_SEM register. 5458 */ 5459 void ice_ptp_unlock(struct ice_hw *hw) 5460 { 5461 wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0); 5462 } 5463 5464 /** 5465 * ice_ptp_init_hw - Initialize hw based on device type 5466 * @hw: pointer to the HW structure 5467 * 5468 * Determine the PHY model for the device, and initialize hw 5469 * for use by other functions. 5470 */ 5471 void ice_ptp_init_hw(struct ice_hw *hw) 5472 { 5473 struct ice_ptp_hw *ptp = &hw->ptp; 5474 5475 if (ice_is_e822(hw) || ice_is_e823(hw)) 5476 ice_ptp_init_phy_e82x(ptp); 5477 else if (ice_is_e810(hw)) 5478 ice_ptp_init_phy_e810(ptp); 5479 else if (ice_is_e825c(hw)) 5480 ice_ptp_init_phy_e825c(hw); 5481 else 5482 ptp->phy_model = ICE_PHY_UNSUP; 5483 } 5484 5485 /** 5486 * ice_ptp_write_port_cmd - Prepare a single PHY port for a timer command 5487 * @hw: pointer to HW struct 5488 * @port: Port to which cmd has to be sent 5489 * @cmd: Command to be sent to the port 5490 * 5491 * Prepare one port for the upcoming timer sync command. Do not use this for 5492 * programming only a single port, instead use ice_ptp_one_port_cmd() to 5493 * ensure non-modified ports get properly initialized to ICE_PTP_NOP. 5494 * 5495 * Return: 5496 * * %0 - success 5497 * %-EBUSY - PHY type not supported 5498 * * %other - failed to write port command 5499 */ 5500 static int ice_ptp_write_port_cmd(struct ice_hw *hw, u8 port, 5501 enum ice_ptp_tmr_cmd cmd) 5502 { 5503 switch (ice_get_phy_model(hw)) { 5504 case ICE_PHY_ETH56G: 5505 return ice_ptp_write_port_cmd_eth56g(hw, port, cmd); 5506 case ICE_PHY_E82X: 5507 return ice_ptp_write_port_cmd_e82x(hw, port, cmd); 5508 default: 5509 return -EOPNOTSUPP; 5510 } 5511 } 5512 5513 /** 5514 * ice_ptp_one_port_cmd - Program one PHY port for a timer command 5515 * @hw: pointer to HW struct 5516 * @configured_port: the port that should execute the command 5517 * @configured_cmd: the command to be executed on the configured port 5518 * 5519 * Prepare one port for executing a timer command, while preparing all other 5520 * ports to ICE_PTP_NOP. This allows executing a command on a single port 5521 * while ensuring all other ports do not execute stale commands. 5522 * 5523 * Return: 5524 * * %0 - success 5525 * * %other - failed to write port command 5526 */ 5527 int ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port, 5528 enum ice_ptp_tmr_cmd configured_cmd) 5529 { 5530 u32 port; 5531 5532 for (port = 0; port < hw->ptp.num_lports; port++) { 5533 int err; 5534 5535 /* Program the configured port with the configured command, 5536 * program all other ports with ICE_PTP_NOP. 5537 */ 5538 if (port == configured_port) 5539 err = ice_ptp_write_port_cmd(hw, port, configured_cmd); 5540 else 5541 err = ice_ptp_write_port_cmd(hw, port, ICE_PTP_NOP); 5542 5543 if (err) 5544 return err; 5545 } 5546 5547 return 0; 5548 } 5549 5550 /** 5551 * ice_ptp_port_cmd - Prepare PHY ports for a timer sync command 5552 * @hw: pointer to HW struct 5553 * @cmd: the timer command to setup 5554 * 5555 * Prepare all PHY ports on this device for the requested timer command. For 5556 * some families this can be done in one shot, but for other families each 5557 * port must be configured individually. 5558 * 5559 * Return: 5560 * * %0 - success 5561 * * %other - failed to write port command 5562 */ 5563 static int ice_ptp_port_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 5564 { 5565 u32 port; 5566 5567 /* PHY models which can program all ports simultaneously */ 5568 switch (ice_get_phy_model(hw)) { 5569 case ICE_PHY_E810: 5570 return ice_ptp_port_cmd_e810(hw, cmd); 5571 default: 5572 break; 5573 } 5574 5575 /* PHY models which require programming each port separately */ 5576 for (port = 0; port < hw->ptp.num_lports; port++) { 5577 int err; 5578 5579 err = ice_ptp_write_port_cmd(hw, port, cmd); 5580 if (err) 5581 return err; 5582 } 5583 5584 return 0; 5585 } 5586 5587 /** 5588 * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command 5589 * @hw: pointer to HW struct 5590 * @cmd: the command to issue 5591 * 5592 * Prepare the source timer and PHY timers and then trigger the requested 5593 * command. This causes the shadow registers previously written in preparation 5594 * for the command to be synchronously applied to both the source and PHY 5595 * timers. 5596 */ 5597 static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 5598 { 5599 int err; 5600 5601 /* First, prepare the source timer */ 5602 ice_ptp_src_cmd(hw, cmd); 5603 5604 /* Next, prepare the ports */ 5605 err = ice_ptp_port_cmd(hw, cmd); 5606 if (err) { 5607 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for timer command %u, err %d\n", 5608 cmd, err); 5609 return err; 5610 } 5611 5612 /* Write the sync command register to drive both source and PHY timer 5613 * commands synchronously 5614 */ 5615 ice_ptp_exec_tmr_cmd(hw); 5616 5617 return 0; 5618 } 5619 5620 /** 5621 * ice_ptp_init_time - Initialize device time to provided value 5622 * @hw: pointer to HW struct 5623 * @time: 64bits of time (GLTSYN_TIME_L and GLTSYN_TIME_H) 5624 * 5625 * Initialize the device to the specified time provided. This requires a three 5626 * step process: 5627 * 5628 * 1) write the new init time to the source timer shadow registers 5629 * 2) write the new init time to the PHY timer shadow registers 5630 * 3) issue an init_time timer command to synchronously switch both the source 5631 * and port timers to the new init time value at the next clock cycle. 5632 */ 5633 int ice_ptp_init_time(struct ice_hw *hw, u64 time) 5634 { 5635 u8 tmr_idx; 5636 int err; 5637 5638 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5639 5640 /* Source timers */ 5641 wr32(hw, GLTSYN_SHTIME_L(tmr_idx), lower_32_bits(time)); 5642 wr32(hw, GLTSYN_SHTIME_H(tmr_idx), upper_32_bits(time)); 5643 wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0); 5644 5645 /* PHY timers */ 5646 /* Fill Rx and Tx ports and send msg to PHY */ 5647 switch (ice_get_phy_model(hw)) { 5648 case ICE_PHY_ETH56G: 5649 err = ice_ptp_prep_phy_time_eth56g(hw, 5650 (u32)(time & 0xFFFFFFFF)); 5651 break; 5652 case ICE_PHY_E810: 5653 err = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF); 5654 break; 5655 case ICE_PHY_E82X: 5656 err = ice_ptp_prep_phy_time_e82x(hw, time & 0xFFFFFFFF); 5657 break; 5658 default: 5659 err = -EOPNOTSUPP; 5660 } 5661 5662 if (err) 5663 return err; 5664 5665 return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_TIME); 5666 } 5667 5668 /** 5669 * ice_ptp_write_incval - Program PHC with new increment value 5670 * @hw: pointer to HW struct 5671 * @incval: Source timer increment value per clock cycle 5672 * 5673 * Program the PHC with a new increment value. This requires a three-step 5674 * process: 5675 * 5676 * 1) Write the increment value to the source timer shadow registers 5677 * 2) Write the increment value to the PHY timer shadow registers 5678 * 3) Issue an ICE_PTP_INIT_INCVAL timer command to synchronously switch both 5679 * the source and port timers to the new increment value at the next clock 5680 * cycle. 5681 */ 5682 int ice_ptp_write_incval(struct ice_hw *hw, u64 incval) 5683 { 5684 u8 tmr_idx; 5685 int err; 5686 5687 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5688 5689 /* Shadow Adjust */ 5690 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), lower_32_bits(incval)); 5691 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), upper_32_bits(incval)); 5692 5693 switch (ice_get_phy_model(hw)) { 5694 case ICE_PHY_ETH56G: 5695 err = ice_ptp_prep_phy_incval_eth56g(hw, incval); 5696 break; 5697 case ICE_PHY_E810: 5698 err = ice_ptp_prep_phy_incval_e810(hw, incval); 5699 break; 5700 case ICE_PHY_E82X: 5701 err = ice_ptp_prep_phy_incval_e82x(hw, incval); 5702 break; 5703 default: 5704 err = -EOPNOTSUPP; 5705 } 5706 5707 if (err) 5708 return err; 5709 5710 return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_INCVAL); 5711 } 5712 5713 /** 5714 * ice_ptp_write_incval_locked - Program new incval while holding semaphore 5715 * @hw: pointer to HW struct 5716 * @incval: Source timer increment value per clock cycle 5717 * 5718 * Program a new PHC incval while holding the PTP semaphore. 5719 */ 5720 int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval) 5721 { 5722 int err; 5723 5724 if (!ice_ptp_lock(hw)) 5725 return -EBUSY; 5726 5727 err = ice_ptp_write_incval(hw, incval); 5728 5729 ice_ptp_unlock(hw); 5730 5731 return err; 5732 } 5733 5734 /** 5735 * ice_ptp_adj_clock - Adjust PHC clock time atomically 5736 * @hw: pointer to HW struct 5737 * @adj: Adjustment in nanoseconds 5738 * 5739 * Perform an atomic adjustment of the PHC time by the specified number of 5740 * nanoseconds. This requires a three-step process: 5741 * 5742 * 1) Write the adjustment to the source timer shadow registers 5743 * 2) Write the adjustment to the PHY timer shadow registers 5744 * 3) Issue an ICE_PTP_ADJ_TIME timer command to synchronously apply the 5745 * adjustment to both the source and port timers at the next clock cycle. 5746 */ 5747 int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj) 5748 { 5749 u8 tmr_idx; 5750 int err; 5751 5752 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5753 5754 /* Write the desired clock adjustment into the GLTSYN_SHADJ register. 5755 * For an ICE_PTP_ADJ_TIME command, this set of registers represents 5756 * the value to add to the clock time. It supports subtraction by 5757 * interpreting the value as a 2's complement integer. 5758 */ 5759 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0); 5760 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj); 5761 5762 switch (ice_get_phy_model(hw)) { 5763 case ICE_PHY_ETH56G: 5764 err = ice_ptp_prep_phy_adj_eth56g(hw, adj); 5765 break; 5766 case ICE_PHY_E810: 5767 err = ice_ptp_prep_phy_adj_e810(hw, adj); 5768 break; 5769 case ICE_PHY_E82X: 5770 err = ice_ptp_prep_phy_adj_e82x(hw, adj); 5771 break; 5772 default: 5773 err = -EOPNOTSUPP; 5774 } 5775 5776 if (err) 5777 return err; 5778 5779 return ice_ptp_tmr_cmd(hw, ICE_PTP_ADJ_TIME); 5780 } 5781 5782 /** 5783 * ice_read_phy_tstamp - Read a PHY timestamp from the timestamo block 5784 * @hw: pointer to the HW struct 5785 * @block: the block to read from 5786 * @idx: the timestamp index to read 5787 * @tstamp: on return, the 40bit timestamp value 5788 * 5789 * Read a 40bit timestamp value out of the timestamp block. For E822 devices, 5790 * the block is the quad to read from. For E810 devices, the block is the 5791 * logical port to read from. 5792 */ 5793 int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp) 5794 { 5795 switch (ice_get_phy_model(hw)) { 5796 case ICE_PHY_ETH56G: 5797 return ice_read_ptp_tstamp_eth56g(hw, block, idx, tstamp); 5798 case ICE_PHY_E810: 5799 return ice_read_phy_tstamp_e810(hw, block, idx, tstamp); 5800 case ICE_PHY_E82X: 5801 return ice_read_phy_tstamp_e82x(hw, block, idx, tstamp); 5802 default: 5803 return -EOPNOTSUPP; 5804 } 5805 } 5806 5807 /** 5808 * ice_clear_phy_tstamp - Clear a timestamp from the timestamp block 5809 * @hw: pointer to the HW struct 5810 * @block: the block to read from 5811 * @idx: the timestamp index to reset 5812 * 5813 * Clear a timestamp from the timestamp block, discarding its value without 5814 * returning it. This resets the memory status bit for the timestamp index 5815 * allowing it to be reused for another timestamp in the future. 5816 * 5817 * For E822 devices, the block number is the PHY quad to clear from. For E810 5818 * devices, the block number is the logical port to clear from. 5819 * 5820 * This function must only be called on a timestamp index whose valid bit is 5821 * set according to ice_get_phy_tx_tstamp_ready(). 5822 */ 5823 int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx) 5824 { 5825 switch (ice_get_phy_model(hw)) { 5826 case ICE_PHY_ETH56G: 5827 return ice_clear_ptp_tstamp_eth56g(hw, block, idx); 5828 case ICE_PHY_E810: 5829 return ice_clear_phy_tstamp_e810(hw, block, idx); 5830 case ICE_PHY_E82X: 5831 return ice_clear_phy_tstamp_e82x(hw, block, idx); 5832 default: 5833 return -EOPNOTSUPP; 5834 } 5835 } 5836 5837 /** 5838 * ice_get_pf_c827_idx - find and return the C827 index for the current pf 5839 * @hw: pointer to the hw struct 5840 * @idx: index of the found C827 PHY 5841 * Return: 5842 * * 0 - success 5843 * * negative - failure 5844 */ 5845 static int ice_get_pf_c827_idx(struct ice_hw *hw, u8 *idx) 5846 { 5847 struct ice_aqc_get_link_topo cmd; 5848 u8 node_part_number; 5849 u16 node_handle; 5850 int status; 5851 u8 ctx; 5852 5853 if (hw->mac_type != ICE_MAC_E810) 5854 return -ENODEV; 5855 5856 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) { 5857 *idx = C827_0; 5858 return 0; 5859 } 5860 5861 memset(&cmd, 0, sizeof(cmd)); 5862 5863 ctx = ICE_AQC_LINK_TOPO_NODE_TYPE_PHY << ICE_AQC_LINK_TOPO_NODE_TYPE_S; 5864 ctx |= ICE_AQC_LINK_TOPO_NODE_CTX_PORT << ICE_AQC_LINK_TOPO_NODE_CTX_S; 5865 cmd.addr.topo_params.node_type_ctx = ctx; 5866 5867 status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number, 5868 &node_handle); 5869 if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827) 5870 return -ENOENT; 5871 5872 if (node_handle == E810C_QSFP_C827_0_HANDLE) 5873 *idx = C827_0; 5874 else if (node_handle == E810C_QSFP_C827_1_HANDLE) 5875 *idx = C827_1; 5876 else 5877 return -EIO; 5878 5879 return 0; 5880 } 5881 5882 /** 5883 * ice_ptp_reset_ts_memory - Reset timestamp memory for all blocks 5884 * @hw: pointer to the HW struct 5885 */ 5886 void ice_ptp_reset_ts_memory(struct ice_hw *hw) 5887 { 5888 switch (ice_get_phy_model(hw)) { 5889 case ICE_PHY_ETH56G: 5890 ice_ptp_reset_ts_memory_eth56g(hw); 5891 break; 5892 case ICE_PHY_E82X: 5893 ice_ptp_reset_ts_memory_e82x(hw); 5894 break; 5895 case ICE_PHY_E810: 5896 default: 5897 return; 5898 } 5899 } 5900 5901 /** 5902 * ice_ptp_init_phc - Initialize PTP hardware clock 5903 * @hw: pointer to the HW struct 5904 * 5905 * Perform the steps required to initialize the PTP hardware clock. 5906 */ 5907 int ice_ptp_init_phc(struct ice_hw *hw) 5908 { 5909 u8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5910 5911 /* Enable source clocks */ 5912 wr32(hw, GLTSYN_ENA(src_idx), GLTSYN_ENA_TSYN_ENA_M); 5913 5914 /* Clear event err indications for auxiliary pins */ 5915 (void)rd32(hw, GLTSYN_STAT(src_idx)); 5916 5917 switch (ice_get_phy_model(hw)) { 5918 case ICE_PHY_ETH56G: 5919 return ice_ptp_init_phc_eth56g(hw); 5920 case ICE_PHY_E810: 5921 return ice_ptp_init_phc_e810(hw); 5922 case ICE_PHY_E82X: 5923 return ice_ptp_init_phc_e82x(hw); 5924 default: 5925 return -EOPNOTSUPP; 5926 } 5927 } 5928 5929 /** 5930 * ice_get_phy_tx_tstamp_ready - Read PHY Tx memory status indication 5931 * @hw: pointer to the HW struct 5932 * @block: the timestamp block to check 5933 * @tstamp_ready: storage for the PHY Tx memory status information 5934 * 5935 * Check the PHY for Tx timestamp memory status. This reports a 64 bit value 5936 * which indicates which timestamps in the block may be captured. A set bit 5937 * means the timestamp can be read. An unset bit means the timestamp is not 5938 * ready and software should avoid reading the register. 5939 */ 5940 int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready) 5941 { 5942 switch (ice_get_phy_model(hw)) { 5943 case ICE_PHY_ETH56G: 5944 return ice_get_phy_tx_tstamp_ready_eth56g(hw, block, 5945 tstamp_ready); 5946 case ICE_PHY_E810: 5947 return ice_get_phy_tx_tstamp_ready_e810(hw, block, 5948 tstamp_ready); 5949 case ICE_PHY_E82X: 5950 return ice_get_phy_tx_tstamp_ready_e82x(hw, block, 5951 tstamp_ready); 5952 break; 5953 default: 5954 return -EOPNOTSUPP; 5955 } 5956 } 5957 5958 /** 5959 * ice_cgu_get_pin_desc_e823 - get pin description array 5960 * @hw: pointer to the hw struct 5961 * @input: if request is done against input or output pin 5962 * @size: number of inputs/outputs 5963 * 5964 * Return: pointer to pin description array associated to given hw. 5965 */ 5966 static const struct ice_cgu_pin_desc * 5967 ice_cgu_get_pin_desc_e823(struct ice_hw *hw, bool input, int *size) 5968 { 5969 static const struct ice_cgu_pin_desc *t; 5970 5971 if (hw->cgu_part_number == 5972 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032) { 5973 if (input) { 5974 t = ice_e823_zl_cgu_inputs; 5975 *size = ARRAY_SIZE(ice_e823_zl_cgu_inputs); 5976 } else { 5977 t = ice_e823_zl_cgu_outputs; 5978 *size = ARRAY_SIZE(ice_e823_zl_cgu_outputs); 5979 } 5980 } else if (hw->cgu_part_number == 5981 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384) { 5982 if (input) { 5983 t = ice_e823_si_cgu_inputs; 5984 *size = ARRAY_SIZE(ice_e823_si_cgu_inputs); 5985 } else { 5986 t = ice_e823_si_cgu_outputs; 5987 *size = ARRAY_SIZE(ice_e823_si_cgu_outputs); 5988 } 5989 } else { 5990 t = NULL; 5991 *size = 0; 5992 } 5993 5994 return t; 5995 } 5996 5997 /** 5998 * ice_cgu_get_pin_desc - get pin description array 5999 * @hw: pointer to the hw struct 6000 * @input: if request is done against input or output pins 6001 * @size: size of array returned by function 6002 * 6003 * Return: pointer to pin description array associated to given hw. 6004 */ 6005 static const struct ice_cgu_pin_desc * 6006 ice_cgu_get_pin_desc(struct ice_hw *hw, bool input, int *size) 6007 { 6008 const struct ice_cgu_pin_desc *t = NULL; 6009 6010 switch (hw->device_id) { 6011 case ICE_DEV_ID_E810C_SFP: 6012 if (input) { 6013 t = ice_e810t_sfp_cgu_inputs; 6014 *size = ARRAY_SIZE(ice_e810t_sfp_cgu_inputs); 6015 } else { 6016 t = ice_e810t_sfp_cgu_outputs; 6017 *size = ARRAY_SIZE(ice_e810t_sfp_cgu_outputs); 6018 } 6019 break; 6020 case ICE_DEV_ID_E810C_QSFP: 6021 if (input) { 6022 t = ice_e810t_qsfp_cgu_inputs; 6023 *size = ARRAY_SIZE(ice_e810t_qsfp_cgu_inputs); 6024 } else { 6025 t = ice_e810t_qsfp_cgu_outputs; 6026 *size = ARRAY_SIZE(ice_e810t_qsfp_cgu_outputs); 6027 } 6028 break; 6029 case ICE_DEV_ID_E823L_10G_BASE_T: 6030 case ICE_DEV_ID_E823L_1GBE: 6031 case ICE_DEV_ID_E823L_BACKPLANE: 6032 case ICE_DEV_ID_E823L_QSFP: 6033 case ICE_DEV_ID_E823L_SFP: 6034 case ICE_DEV_ID_E823C_10G_BASE_T: 6035 case ICE_DEV_ID_E823C_BACKPLANE: 6036 case ICE_DEV_ID_E823C_QSFP: 6037 case ICE_DEV_ID_E823C_SFP: 6038 case ICE_DEV_ID_E823C_SGMII: 6039 t = ice_cgu_get_pin_desc_e823(hw, input, size); 6040 break; 6041 default: 6042 break; 6043 } 6044 6045 return t; 6046 } 6047 6048 /** 6049 * ice_cgu_get_num_pins - get pin description array size 6050 * @hw: pointer to the hw struct 6051 * @input: if request is done against input or output pins 6052 * 6053 * Return: size of pin description array for given hw. 6054 */ 6055 int ice_cgu_get_num_pins(struct ice_hw *hw, bool input) 6056 { 6057 const struct ice_cgu_pin_desc *t; 6058 int size; 6059 6060 t = ice_cgu_get_pin_desc(hw, input, &size); 6061 if (t) 6062 return size; 6063 6064 return 0; 6065 } 6066 6067 /** 6068 * ice_cgu_get_pin_type - get pin's type 6069 * @hw: pointer to the hw struct 6070 * @pin: pin index 6071 * @input: if request is done against input or output pin 6072 * 6073 * Return: type of a pin. 6074 */ 6075 enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool input) 6076 { 6077 const struct ice_cgu_pin_desc *t; 6078 int t_size; 6079 6080 t = ice_cgu_get_pin_desc(hw, input, &t_size); 6081 6082 if (!t) 6083 return 0; 6084 6085 if (pin >= t_size) 6086 return 0; 6087 6088 return t[pin].type; 6089 } 6090 6091 /** 6092 * ice_cgu_get_pin_freq_supp - get pin's supported frequency 6093 * @hw: pointer to the hw struct 6094 * @pin: pin index 6095 * @input: if request is done against input or output pin 6096 * @num: output number of supported frequencies 6097 * 6098 * Get frequency supported number and array of supported frequencies. 6099 * 6100 * Return: array of supported frequencies for given pin. 6101 */ 6102 struct dpll_pin_frequency * 6103 ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num) 6104 { 6105 const struct ice_cgu_pin_desc *t; 6106 int t_size; 6107 6108 *num = 0; 6109 t = ice_cgu_get_pin_desc(hw, input, &t_size); 6110 if (!t) 6111 return NULL; 6112 if (pin >= t_size) 6113 return NULL; 6114 *num = t[pin].freq_supp_num; 6115 6116 return t[pin].freq_supp; 6117 } 6118 6119 /** 6120 * ice_cgu_get_pin_name - get pin's name 6121 * @hw: pointer to the hw struct 6122 * @pin: pin index 6123 * @input: if request is done against input or output pin 6124 * 6125 * Return: 6126 * * null terminated char array with name 6127 * * NULL in case of failure 6128 */ 6129 const char *ice_cgu_get_pin_name(struct ice_hw *hw, u8 pin, bool input) 6130 { 6131 const struct ice_cgu_pin_desc *t; 6132 int t_size; 6133 6134 t = ice_cgu_get_pin_desc(hw, input, &t_size); 6135 6136 if (!t) 6137 return NULL; 6138 6139 if (pin >= t_size) 6140 return NULL; 6141 6142 return t[pin].name; 6143 } 6144 6145 /** 6146 * ice_get_cgu_state - get the state of the DPLL 6147 * @hw: pointer to the hw struct 6148 * @dpll_idx: Index of internal DPLL unit 6149 * @last_dpll_state: last known state of DPLL 6150 * @pin: pointer to a buffer for returning currently active pin 6151 * @ref_state: reference clock state 6152 * @eec_mode: eec mode of the DPLL 6153 * @phase_offset: pointer to a buffer for returning phase offset 6154 * @dpll_state: state of the DPLL (output) 6155 * 6156 * This function will read the state of the DPLL(dpll_idx). Non-null 6157 * 'pin', 'ref_state', 'eec_mode' and 'phase_offset' parameters are used to 6158 * retrieve currently active pin, state, mode and phase_offset respectively. 6159 * 6160 * Return: state of the DPLL 6161 */ 6162 int ice_get_cgu_state(struct ice_hw *hw, u8 dpll_idx, 6163 enum dpll_lock_status last_dpll_state, u8 *pin, 6164 u8 *ref_state, u8 *eec_mode, s64 *phase_offset, 6165 enum dpll_lock_status *dpll_state) 6166 { 6167 u8 hw_ref_state, hw_dpll_state, hw_eec_mode, hw_config; 6168 s64 hw_phase_offset; 6169 int status; 6170 6171 status = ice_aq_get_cgu_dpll_status(hw, dpll_idx, &hw_ref_state, 6172 &hw_dpll_state, &hw_config, 6173 &hw_phase_offset, &hw_eec_mode); 6174 if (status) 6175 return status; 6176 6177 if (pin) 6178 /* current ref pin in dpll_state_refsel_status_X register */ 6179 *pin = hw_config & ICE_AQC_GET_CGU_DPLL_CONFIG_CLK_REF_SEL; 6180 if (phase_offset) 6181 *phase_offset = hw_phase_offset; 6182 if (ref_state) 6183 *ref_state = hw_ref_state; 6184 if (eec_mode) 6185 *eec_mode = hw_eec_mode; 6186 if (!dpll_state) 6187 return 0; 6188 6189 /* According to ZL DPLL documentation, once state reach LOCKED_HO_ACQ 6190 * it would never return to FREERUN. This aligns to ITU-T G.781 6191 * Recommendation. We cannot report HOLDOVER as HO memory is cleared 6192 * while switching to another reference. 6193 * Only for situations where previous state was either: "LOCKED without 6194 * HO_ACQ" or "HOLDOVER" we actually back to FREERUN. 6195 */ 6196 if (hw_dpll_state & ICE_AQC_GET_CGU_DPLL_STATUS_STATE_LOCK) { 6197 if (hw_dpll_state & ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO_READY) 6198 *dpll_state = DPLL_LOCK_STATUS_LOCKED_HO_ACQ; 6199 else 6200 *dpll_state = DPLL_LOCK_STATUS_LOCKED; 6201 } else if (last_dpll_state == DPLL_LOCK_STATUS_LOCKED_HO_ACQ || 6202 last_dpll_state == DPLL_LOCK_STATUS_HOLDOVER) { 6203 *dpll_state = DPLL_LOCK_STATUS_HOLDOVER; 6204 } else { 6205 *dpll_state = DPLL_LOCK_STATUS_UNLOCKED; 6206 } 6207 6208 return 0; 6209 } 6210 6211 /** 6212 * ice_get_cgu_rclk_pin_info - get info on available recovered clock pins 6213 * @hw: pointer to the hw struct 6214 * @base_idx: returns index of first recovered clock pin on device 6215 * @pin_num: returns number of recovered clock pins available on device 6216 * 6217 * Based on hw provide caller info about recovery clock pins available on the 6218 * board. 6219 * 6220 * Return: 6221 * * 0 - success, information is valid 6222 * * negative - failure, information is not valid 6223 */ 6224 int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num) 6225 { 6226 u8 phy_idx; 6227 int ret; 6228 6229 switch (hw->device_id) { 6230 case ICE_DEV_ID_E810C_SFP: 6231 case ICE_DEV_ID_E810C_QSFP: 6232 6233 ret = ice_get_pf_c827_idx(hw, &phy_idx); 6234 if (ret) 6235 return ret; 6236 *base_idx = E810T_CGU_INPUT_C827(phy_idx, ICE_RCLKA_PIN); 6237 *pin_num = ICE_E810_RCLK_PINS_NUM; 6238 ret = 0; 6239 break; 6240 case ICE_DEV_ID_E823L_10G_BASE_T: 6241 case ICE_DEV_ID_E823L_1GBE: 6242 case ICE_DEV_ID_E823L_BACKPLANE: 6243 case ICE_DEV_ID_E823L_QSFP: 6244 case ICE_DEV_ID_E823L_SFP: 6245 case ICE_DEV_ID_E823C_10G_BASE_T: 6246 case ICE_DEV_ID_E823C_BACKPLANE: 6247 case ICE_DEV_ID_E823C_QSFP: 6248 case ICE_DEV_ID_E823C_SFP: 6249 case ICE_DEV_ID_E823C_SGMII: 6250 *pin_num = ICE_E82X_RCLK_PINS_NUM; 6251 ret = 0; 6252 if (hw->cgu_part_number == 6253 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032) 6254 *base_idx = ZL_REF1P; 6255 else if (hw->cgu_part_number == 6256 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384) 6257 *base_idx = SI_REF1P; 6258 else 6259 ret = -ENODEV; 6260 6261 break; 6262 default: 6263 ret = -ENODEV; 6264 break; 6265 } 6266 6267 return ret; 6268 } 6269 6270 /** 6271 * ice_cgu_get_output_pin_state_caps - get output pin state capabilities 6272 * @hw: pointer to the hw struct 6273 * @pin_id: id of a pin 6274 * @caps: capabilities to modify 6275 * 6276 * Return: 6277 * * 0 - success, state capabilities were modified 6278 * * negative - failure, capabilities were not modified 6279 */ 6280 int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id, 6281 unsigned long *caps) 6282 { 6283 bool can_change = true; 6284 6285 switch (hw->device_id) { 6286 case ICE_DEV_ID_E810C_SFP: 6287 if (pin_id == ZL_OUT2 || pin_id == ZL_OUT3) 6288 can_change = false; 6289 break; 6290 case ICE_DEV_ID_E810C_QSFP: 6291 if (pin_id == ZL_OUT2 || pin_id == ZL_OUT3 || pin_id == ZL_OUT4) 6292 can_change = false; 6293 break; 6294 case ICE_DEV_ID_E823L_10G_BASE_T: 6295 case ICE_DEV_ID_E823L_1GBE: 6296 case ICE_DEV_ID_E823L_BACKPLANE: 6297 case ICE_DEV_ID_E823L_QSFP: 6298 case ICE_DEV_ID_E823L_SFP: 6299 case ICE_DEV_ID_E823C_10G_BASE_T: 6300 case ICE_DEV_ID_E823C_BACKPLANE: 6301 case ICE_DEV_ID_E823C_QSFP: 6302 case ICE_DEV_ID_E823C_SFP: 6303 case ICE_DEV_ID_E823C_SGMII: 6304 if (hw->cgu_part_number == 6305 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032 && 6306 pin_id == ZL_OUT2) 6307 can_change = false; 6308 else if (hw->cgu_part_number == 6309 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384 && 6310 pin_id == SI_OUT1) 6311 can_change = false; 6312 break; 6313 default: 6314 return -EINVAL; 6315 } 6316 if (can_change) 6317 *caps |= DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE; 6318 else 6319 *caps &= ~DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE; 6320 6321 return 0; 6322 } 6323