1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (C) 2021, Intel Corporation. */ 3 4 #include <linux/delay.h> 5 #include <linux/iopoll.h> 6 #include "ice_common.h" 7 #include "ice_ptp_hw.h" 8 #include "ice_ptp_consts.h" 9 #include "ice_cgu_regs.h" 10 11 static struct dpll_pin_frequency ice_cgu_pin_freq_common[] = { 12 DPLL_PIN_FREQUENCY_1PPS, 13 DPLL_PIN_FREQUENCY_10MHZ, 14 }; 15 16 static struct dpll_pin_frequency ice_cgu_pin_freq_1_hz[] = { 17 DPLL_PIN_FREQUENCY_1PPS, 18 }; 19 20 static struct dpll_pin_frequency ice_cgu_pin_freq_10_mhz[] = { 21 DPLL_PIN_FREQUENCY_10MHZ, 22 }; 23 24 static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_inputs[] = { 25 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR, 26 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 27 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR, 28 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 29 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, }, 30 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, }, 31 { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT, 32 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 33 { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT, 34 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 35 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS, 36 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 37 }; 38 39 static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_inputs[] = { 40 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR, 41 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 42 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR, 43 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 44 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, }, 45 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, }, 46 { "C827_1-RCLKA", ZL_REF2P, DPLL_PIN_TYPE_MUX, }, 47 { "C827_1-RCLKB", ZL_REF2N, DPLL_PIN_TYPE_MUX, }, 48 { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT, 49 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 50 { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT, 51 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 52 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS, 53 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 54 }; 55 56 static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_outputs[] = { 57 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT, 58 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 59 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT, 60 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 61 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, }, 62 { "MAC-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, }, 63 { "CVL-SDP21", ZL_OUT4, DPLL_PIN_TYPE_EXT, 64 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 65 { "CVL-SDP23", ZL_OUT5, DPLL_PIN_TYPE_EXT, 66 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 67 }; 68 69 static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_outputs[] = { 70 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT, 71 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 72 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT, 73 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 74 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 75 { "PHY2-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 76 { "MAC-CLK", ZL_OUT4, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 77 { "CVL-SDP21", ZL_OUT5, DPLL_PIN_TYPE_EXT, 78 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 79 { "CVL-SDP23", ZL_OUT6, DPLL_PIN_TYPE_EXT, 80 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 81 }; 82 83 static const struct ice_cgu_pin_desc ice_e823_si_cgu_inputs[] = { 84 { "NONE", SI_REF0P, 0, 0 }, 85 { "NONE", SI_REF0N, 0, 0 }, 86 { "SYNCE0_DP", SI_REF1P, DPLL_PIN_TYPE_MUX, 0 }, 87 { "SYNCE0_DN", SI_REF1N, DPLL_PIN_TYPE_MUX, 0 }, 88 { "EXT_CLK_SYNC", SI_REF2P, DPLL_PIN_TYPE_EXT, 89 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 90 { "NONE", SI_REF2N, 0, 0 }, 91 { "EXT_PPS_OUT", SI_REF3, DPLL_PIN_TYPE_EXT, 92 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 93 { "INT_PPS_OUT", SI_REF4, DPLL_PIN_TYPE_EXT, 94 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 95 }; 96 97 static const struct ice_cgu_pin_desc ice_e823_si_cgu_outputs[] = { 98 { "1588-TIME_SYNC", SI_OUT0, DPLL_PIN_TYPE_EXT, 99 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 100 { "PHY-CLK", SI_OUT1, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 101 { "10MHZ-SMA2", SI_OUT2, DPLL_PIN_TYPE_EXT, 102 ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz }, 103 { "PPS-SMA1", SI_OUT3, DPLL_PIN_TYPE_EXT, 104 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 105 }; 106 107 static const struct ice_cgu_pin_desc ice_e823_zl_cgu_inputs[] = { 108 { "NONE", ZL_REF0P, 0, 0 }, 109 { "INT_PPS_OUT", ZL_REF0N, DPLL_PIN_TYPE_EXT, 110 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 111 { "SYNCE0_DP", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0 }, 112 { "SYNCE0_DN", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0 }, 113 { "NONE", ZL_REF2P, 0, 0 }, 114 { "NONE", ZL_REF2N, 0, 0 }, 115 { "EXT_CLK_SYNC", ZL_REF3P, DPLL_PIN_TYPE_EXT, 116 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 117 { "NONE", ZL_REF3N, 0, 0 }, 118 { "EXT_PPS_OUT", ZL_REF4P, DPLL_PIN_TYPE_EXT, 119 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 120 { "OCXO", ZL_REF4N, DPLL_PIN_TYPE_INT_OSCILLATOR, 0 }, 121 }; 122 123 static const struct ice_cgu_pin_desc ice_e823_zl_cgu_outputs[] = { 124 { "PPS-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT, 125 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 126 { "10MHZ-SMA2", ZL_OUT1, DPLL_PIN_TYPE_EXT, 127 ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz }, 128 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 129 { "1588-TIME_REF", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 130 { "CPK-TIME_SYNC", ZL_OUT4, DPLL_PIN_TYPE_EXT, 131 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 132 { "NONE", ZL_OUT5, 0, 0 }, 133 }; 134 135 /* Low level functions for interacting with and managing the device clock used 136 * for the Precision Time Protocol. 137 * 138 * The ice hardware represents the current time using three registers: 139 * 140 * GLTSYN_TIME_H GLTSYN_TIME_L GLTSYN_TIME_R 141 * +---------------+ +---------------+ +---------------+ 142 * | 32 bits | | 32 bits | | 32 bits | 143 * +---------------+ +---------------+ +---------------+ 144 * 145 * The registers are incremented every clock tick using a 40bit increment 146 * value defined over two registers: 147 * 148 * GLTSYN_INCVAL_H GLTSYN_INCVAL_L 149 * +---------------+ +---------------+ 150 * | 8 bit s | | 32 bits | 151 * +---------------+ +---------------+ 152 * 153 * The increment value is added to the GLSTYN_TIME_R and GLSTYN_TIME_L 154 * registers every clock source tick. Depending on the specific device 155 * configuration, the clock source frequency could be one of a number of 156 * values. 157 * 158 * For E810 devices, the increment frequency is 812.5 MHz 159 * 160 * For E822 devices the clock can be derived from different sources, and the 161 * increment has an effective frequency of one of the following: 162 * - 823.4375 MHz 163 * - 783.36 MHz 164 * - 796.875 MHz 165 * - 816 MHz 166 * - 830.078125 MHz 167 * - 783.36 MHz 168 * 169 * The hardware captures timestamps in the PHY for incoming packets, and for 170 * outgoing packets on request. To support this, the PHY maintains a timer 171 * that matches the lower 64 bits of the global source timer. 172 * 173 * In order to ensure that the PHY timers and the source timer are equivalent, 174 * shadow registers are used to prepare the desired initial values. A special 175 * sync command is issued to trigger copying from the shadow registers into 176 * the appropriate source and PHY registers simultaneously. 177 * 178 * The driver supports devices which have different PHYs with subtly different 179 * mechanisms to program and control the timers. We divide the devices into 180 * families named after the first major device, E810 and similar devices, and 181 * E822 and similar devices. 182 * 183 * - E822 based devices have additional support for fine grained Vernier 184 * calibration which requires significant setup 185 * - The layout of timestamp data in the PHY register blocks is different 186 * - The way timer synchronization commands are issued is different. 187 * 188 * To support this, very low level functions have an e810 or e822 suffix 189 * indicating what type of device they work on. Higher level abstractions for 190 * tasks that can be done on both devices do not have the suffix and will 191 * correctly look up the appropriate low level function when running. 192 * 193 * Functions which only make sense on a single device family may not have 194 * a suitable generic implementation 195 */ 196 197 /** 198 * ice_get_ptp_src_clock_index - determine source clock index 199 * @hw: pointer to HW struct 200 * 201 * Determine the source clock index currently in use, based on device 202 * capabilities reported during initialization. 203 */ 204 u8 ice_get_ptp_src_clock_index(struct ice_hw *hw) 205 { 206 return hw->func_caps.ts_func_info.tmr_index_assoc; 207 } 208 209 /** 210 * ice_ptp_read_src_incval - Read source timer increment value 211 * @hw: pointer to HW struct 212 * 213 * Read the increment value of the source timer and return it. 214 */ 215 static u64 ice_ptp_read_src_incval(struct ice_hw *hw) 216 { 217 u32 lo, hi; 218 u8 tmr_idx; 219 220 tmr_idx = ice_get_ptp_src_clock_index(hw); 221 222 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 223 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 224 225 return ((u64)(hi & INCVAL_HIGH_M) << 32) | lo; 226 } 227 228 /** 229 * ice_read_cgu_reg_e82x - Read a CGU register 230 * @hw: pointer to the HW struct 231 * @addr: Register address to read 232 * @val: storage for register value read 233 * 234 * Read the contents of a register of the Clock Generation Unit. Only 235 * applicable to E822 devices. 236 * 237 * Return: 0 on success, other error codes when failed to read from CGU 238 */ 239 static int ice_read_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 *val) 240 { 241 struct ice_sbq_msg_input cgu_msg = { 242 .opcode = ice_sbq_msg_rd, 243 .dest_dev = ice_sbq_dev_cgu, 244 .msg_addr_low = addr 245 }; 246 int err; 247 248 err = ice_sbq_rw_reg(hw, &cgu_msg, ICE_AQ_FLAG_RD); 249 if (err) { 250 ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n", 251 addr, err); 252 return err; 253 } 254 255 *val = cgu_msg.data; 256 257 return 0; 258 } 259 260 /** 261 * ice_write_cgu_reg_e82x - Write a CGU register 262 * @hw: pointer to the HW struct 263 * @addr: Register address to write 264 * @val: value to write into the register 265 * 266 * Write the specified value to a register of the Clock Generation Unit. Only 267 * applicable to E822 devices. 268 * 269 * Return: 0 on success, other error codes when failed to write to CGU 270 */ 271 static int ice_write_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 val) 272 { 273 struct ice_sbq_msg_input cgu_msg = { 274 .opcode = ice_sbq_msg_wr, 275 .dest_dev = ice_sbq_dev_cgu, 276 .msg_addr_low = addr, 277 .data = val 278 }; 279 int err; 280 281 err = ice_sbq_rw_reg(hw, &cgu_msg, ICE_AQ_FLAG_RD); 282 if (err) { 283 ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n", 284 addr, err); 285 return err; 286 } 287 288 return err; 289 } 290 291 /** 292 * ice_clk_freq_str - Convert time_ref_freq to string 293 * @clk_freq: Clock frequency 294 * 295 * Return: specified TIME_REF clock frequency converted to a string 296 */ 297 static const char *ice_clk_freq_str(enum ice_time_ref_freq clk_freq) 298 { 299 switch (clk_freq) { 300 case ICE_TIME_REF_FREQ_25_000: 301 return "25 MHz"; 302 case ICE_TIME_REF_FREQ_122_880: 303 return "122.88 MHz"; 304 case ICE_TIME_REF_FREQ_125_000: 305 return "125 MHz"; 306 case ICE_TIME_REF_FREQ_153_600: 307 return "153.6 MHz"; 308 case ICE_TIME_REF_FREQ_156_250: 309 return "156.25 MHz"; 310 case ICE_TIME_REF_FREQ_245_760: 311 return "245.76 MHz"; 312 default: 313 return "Unknown"; 314 } 315 } 316 317 /** 318 * ice_clk_src_str - Convert time_ref_src to string 319 * @clk_src: Clock source 320 * 321 * Return: specified clock source converted to its string name 322 */ 323 static const char *ice_clk_src_str(enum ice_clk_src clk_src) 324 { 325 switch (clk_src) { 326 case ICE_CLK_SRC_TCXO: 327 return "TCXO"; 328 case ICE_CLK_SRC_TIME_REF: 329 return "TIME_REF"; 330 default: 331 return "Unknown"; 332 } 333 } 334 335 /** 336 * ice_cfg_cgu_pll_e82x - Configure the Clock Generation Unit 337 * @hw: pointer to the HW struct 338 * @clk_freq: Clock frequency to program 339 * @clk_src: Clock source to select (TIME_REF, or TCXO) 340 * 341 * Configure the Clock Generation Unit with the desired clock frequency and 342 * time reference, enabling the PLL which drives the PTP hardware clock. 343 * 344 * Return: 345 * * %0 - success 346 * * %-EINVAL - input parameters are incorrect 347 * * %-EBUSY - failed to lock TS PLL 348 * * %other - CGU read/write failure 349 */ 350 static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw, 351 enum ice_time_ref_freq clk_freq, 352 enum ice_clk_src clk_src) 353 { 354 union tspll_ro_bwm_lf bwm_lf; 355 union nac_cgu_dword19 dw19; 356 union nac_cgu_dword22 dw22; 357 union nac_cgu_dword24 dw24; 358 union nac_cgu_dword9 dw9; 359 int err; 360 361 if (clk_freq >= NUM_ICE_TIME_REF_FREQ) { 362 dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n", 363 clk_freq); 364 return -EINVAL; 365 } 366 367 if (clk_src >= NUM_ICE_CLK_SRC) { 368 dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n", 369 clk_src); 370 return -EINVAL; 371 } 372 373 if (clk_src == ICE_CLK_SRC_TCXO && 374 clk_freq != ICE_TIME_REF_FREQ_25_000) { 375 dev_warn(ice_hw_to_dev(hw), 376 "TCXO only supports 25 MHz frequency\n"); 377 return -EINVAL; 378 } 379 380 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val); 381 if (err) 382 return err; 383 384 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val); 385 if (err) 386 return err; 387 388 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val); 389 if (err) 390 return err; 391 392 /* Log the current clock configuration */ 393 ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", 394 str_enabled_disabled(dw24.ts_pll_enable), 395 ice_clk_src_str(dw24.time_ref_sel), 396 ice_clk_freq_str(dw9.time_ref_freq_sel), 397 bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked"); 398 399 /* Disable the PLL before changing the clock source or frequency */ 400 if (dw24.ts_pll_enable) { 401 dw24.ts_pll_enable = 0; 402 403 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val); 404 if (err) 405 return err; 406 } 407 408 /* Set the frequency */ 409 dw9.time_ref_freq_sel = clk_freq; 410 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val); 411 if (err) 412 return err; 413 414 /* Configure the TS PLL feedback divisor */ 415 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val); 416 if (err) 417 return err; 418 419 dw19.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div; 420 dw19.tspll_ndivratio = 1; 421 422 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val); 423 if (err) 424 return err; 425 426 /* Configure the TS PLL post divisor */ 427 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val); 428 if (err) 429 return err; 430 431 dw22.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div; 432 dw22.time1588clk_sel_div2 = 0; 433 434 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val); 435 if (err) 436 return err; 437 438 /* Configure the TS PLL pre divisor and clock source */ 439 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val); 440 if (err) 441 return err; 442 443 dw24.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div; 444 dw24.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div; 445 dw24.time_ref_sel = clk_src; 446 447 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val); 448 if (err) 449 return err; 450 451 /* Finally, enable the PLL */ 452 dw24.ts_pll_enable = 1; 453 454 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val); 455 if (err) 456 return err; 457 458 /* Wait to verify if the PLL locks */ 459 usleep_range(1000, 5000); 460 461 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val); 462 if (err) 463 return err; 464 465 if (!bwm_lf.plllock_true_lock_cri) { 466 dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n"); 467 return -EBUSY; 468 } 469 470 /* Log the current clock configuration */ 471 ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", 472 str_enabled_disabled(dw24.ts_pll_enable), 473 ice_clk_src_str(dw24.time_ref_sel), 474 ice_clk_freq_str(dw9.time_ref_freq_sel), 475 bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked"); 476 477 return 0; 478 } 479 480 /** 481 * ice_cfg_cgu_pll_e825c - Configure the Clock Generation Unit for E825-C 482 * @hw: pointer to the HW struct 483 * @clk_freq: Clock frequency to program 484 * @clk_src: Clock source to select (TIME_REF, or TCXO) 485 * 486 * Configure the Clock Generation Unit with the desired clock frequency and 487 * time reference, enabling the PLL which drives the PTP hardware clock. 488 * 489 * Return: 490 * * %0 - success 491 * * %-EINVAL - input parameters are incorrect 492 * * %-EBUSY - failed to lock TS PLL 493 * * %other - CGU read/write failure 494 */ 495 static int ice_cfg_cgu_pll_e825c(struct ice_hw *hw, 496 enum ice_time_ref_freq clk_freq, 497 enum ice_clk_src clk_src) 498 { 499 union tspll_ro_lock_e825c ro_lock; 500 union nac_cgu_dword16_e825c dw16; 501 union nac_cgu_dword23_e825c dw23; 502 union nac_cgu_dword19 dw19; 503 union nac_cgu_dword22 dw22; 504 union nac_cgu_dword24 dw24; 505 union nac_cgu_dword9 dw9; 506 int err; 507 508 if (clk_freq >= NUM_ICE_TIME_REF_FREQ) { 509 dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n", 510 clk_freq); 511 return -EINVAL; 512 } 513 514 if (clk_src >= NUM_ICE_CLK_SRC) { 515 dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n", 516 clk_src); 517 return -EINVAL; 518 } 519 520 if (clk_src == ICE_CLK_SRC_TCXO && 521 clk_freq != ICE_TIME_REF_FREQ_156_250) { 522 dev_warn(ice_hw_to_dev(hw), 523 "TCXO only supports 156.25 MHz frequency\n"); 524 return -EINVAL; 525 } 526 527 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val); 528 if (err) 529 return err; 530 531 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val); 532 if (err) 533 return err; 534 535 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD16_E825C, &dw16.val); 536 if (err) 537 return err; 538 539 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val); 540 if (err) 541 return err; 542 543 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val); 544 if (err) 545 return err; 546 547 /* Log the current clock configuration */ 548 ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", 549 str_enabled_disabled(dw24.ts_pll_enable), 550 ice_clk_src_str(dw23.time_ref_sel), 551 ice_clk_freq_str(dw9.time_ref_freq_sel), 552 ro_lock.plllock_true_lock_cri ? "locked" : "unlocked"); 553 554 /* Disable the PLL before changing the clock source or frequency */ 555 if (dw23.ts_pll_enable) { 556 dw23.ts_pll_enable = 0; 557 558 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, 559 dw23.val); 560 if (err) 561 return err; 562 } 563 564 /* Set the frequency */ 565 dw9.time_ref_freq_sel = clk_freq; 566 567 /* Enable the correct receiver */ 568 if (clk_src == ICE_CLK_SRC_TCXO) { 569 dw9.time_ref_en = 0; 570 dw9.clk_eref0_en = 1; 571 } else { 572 dw9.time_ref_en = 1; 573 dw9.clk_eref0_en = 0; 574 } 575 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val); 576 if (err) 577 return err; 578 579 /* Choose the referenced frequency */ 580 dw16.tspll_ck_refclkfreq = 581 e825c_cgu_params[clk_freq].tspll_ck_refclkfreq; 582 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD16_E825C, dw16.val); 583 if (err) 584 return err; 585 586 /* Configure the TS PLL feedback divisor */ 587 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val); 588 if (err) 589 return err; 590 591 dw19.tspll_fbdiv_intgr = 592 e825c_cgu_params[clk_freq].tspll_fbdiv_intgr; 593 dw19.tspll_ndivratio = 594 e825c_cgu_params[clk_freq].tspll_ndivratio; 595 596 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val); 597 if (err) 598 return err; 599 600 /* Configure the TS PLL post divisor */ 601 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val); 602 if (err) 603 return err; 604 605 /* These two are constant for E825C */ 606 dw22.time1588clk_div = 5; 607 dw22.time1588clk_sel_div2 = 0; 608 609 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val); 610 if (err) 611 return err; 612 613 /* Configure the TS PLL pre divisor and clock source */ 614 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val); 615 if (err) 616 return err; 617 618 dw23.ref1588_ck_div = 619 e825c_cgu_params[clk_freq].ref1588_ck_div; 620 dw23.time_ref_sel = clk_src; 621 622 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val); 623 if (err) 624 return err; 625 626 dw24.tspll_fbdiv_frac = 627 e825c_cgu_params[clk_freq].tspll_fbdiv_frac; 628 629 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val); 630 if (err) 631 return err; 632 633 /* Finally, enable the PLL */ 634 dw23.ts_pll_enable = 1; 635 636 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val); 637 if (err) 638 return err; 639 640 /* Wait to verify if the PLL locks */ 641 usleep_range(1000, 5000); 642 643 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val); 644 if (err) 645 return err; 646 647 if (!ro_lock.plllock_true_lock_cri) { 648 dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n"); 649 return -EBUSY; 650 } 651 652 /* Log the current clock configuration */ 653 ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", 654 str_enabled_disabled(dw24.ts_pll_enable), 655 ice_clk_src_str(dw23.time_ref_sel), 656 ice_clk_freq_str(dw9.time_ref_freq_sel), 657 ro_lock.plllock_true_lock_cri ? "locked" : "unlocked"); 658 659 return 0; 660 } 661 662 #define ICE_ONE_PPS_OUT_AMP_MAX 3 663 664 /** 665 * ice_cgu_cfg_pps_out - Configure 1PPS output from CGU 666 * @hw: pointer to the HW struct 667 * @enable: true to enable 1PPS output, false to disable it 668 * 669 * Return: 0 on success, other negative error code when CGU read/write failed 670 */ 671 int ice_cgu_cfg_pps_out(struct ice_hw *hw, bool enable) 672 { 673 union nac_cgu_dword9 dw9; 674 int err; 675 676 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val); 677 if (err) 678 return err; 679 680 dw9.one_pps_out_en = enable; 681 dw9.one_pps_out_amp = enable * ICE_ONE_PPS_OUT_AMP_MAX; 682 return ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val); 683 } 684 685 /** 686 * ice_cfg_cgu_pll_dis_sticky_bits_e82x - disable TS PLL sticky bits 687 * @hw: pointer to the HW struct 688 * 689 * Configure the Clock Generation Unit TS PLL sticky bits so they don't latch on 690 * losing TS PLL lock, but always show current state. 691 * 692 * Return: 0 on success, other error codes when failed to read/write CGU 693 */ 694 static int ice_cfg_cgu_pll_dis_sticky_bits_e82x(struct ice_hw *hw) 695 { 696 union tspll_cntr_bist_settings cntr_bist; 697 int err; 698 699 err = ice_read_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS, 700 &cntr_bist.val); 701 if (err) 702 return err; 703 704 /* Disable sticky lock detection so lock err reported is accurate */ 705 cntr_bist.i_plllock_sel_0 = 0; 706 cntr_bist.i_plllock_sel_1 = 0; 707 708 return ice_write_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS, 709 cntr_bist.val); 710 } 711 712 /** 713 * ice_cfg_cgu_pll_dis_sticky_bits_e825c - disable TS PLL sticky bits for E825-C 714 * @hw: pointer to the HW struct 715 * 716 * Configure the Clock Generation Unit TS PLL sticky bits so they don't latch on 717 * losing TS PLL lock, but always show current state. 718 * 719 * Return: 0 on success, other error codes when failed to read/write CGU 720 */ 721 static int ice_cfg_cgu_pll_dis_sticky_bits_e825c(struct ice_hw *hw) 722 { 723 union tspll_bw_tdc_e825c bw_tdc; 724 int err; 725 726 err = ice_read_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C, &bw_tdc.val); 727 if (err) 728 return err; 729 730 bw_tdc.i_plllock_sel_1_0 = 0; 731 732 return ice_write_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C, bw_tdc.val); 733 } 734 735 /** 736 * ice_init_cgu_e82x - Initialize CGU with settings from firmware 737 * @hw: pointer to the HW structure 738 * 739 * Initialize the Clock Generation Unit of the E822 device. 740 * 741 * Return: 0 on success, other error codes when failed to read/write/cfg CGU 742 */ 743 static int ice_init_cgu_e82x(struct ice_hw *hw) 744 { 745 struct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info; 746 int err; 747 748 /* Disable sticky lock detection so lock err reported is accurate */ 749 if (hw->mac_type == ICE_MAC_GENERIC_3K_E825) 750 err = ice_cfg_cgu_pll_dis_sticky_bits_e825c(hw); 751 else 752 err = ice_cfg_cgu_pll_dis_sticky_bits_e82x(hw); 753 if (err) 754 return err; 755 756 /* Configure the CGU PLL using the parameters from the function 757 * capabilities. 758 */ 759 if (hw->mac_type == ICE_MAC_GENERIC_3K_E825) 760 err = ice_cfg_cgu_pll_e825c(hw, ts_info->time_ref, 761 (enum ice_clk_src)ts_info->clk_src); 762 else 763 err = ice_cfg_cgu_pll_e82x(hw, ts_info->time_ref, 764 (enum ice_clk_src)ts_info->clk_src); 765 766 return err; 767 } 768 769 /** 770 * ice_ptp_tmr_cmd_to_src_reg - Convert to source timer command value 771 * @hw: pointer to HW struct 772 * @cmd: Timer command 773 * 774 * Return: the source timer command register value for the given PTP timer 775 * command. 776 */ 777 static u32 ice_ptp_tmr_cmd_to_src_reg(struct ice_hw *hw, 778 enum ice_ptp_tmr_cmd cmd) 779 { 780 u32 cmd_val, tmr_idx; 781 782 switch (cmd) { 783 case ICE_PTP_INIT_TIME: 784 cmd_val = GLTSYN_CMD_INIT_TIME; 785 break; 786 case ICE_PTP_INIT_INCVAL: 787 cmd_val = GLTSYN_CMD_INIT_INCVAL; 788 break; 789 case ICE_PTP_ADJ_TIME: 790 cmd_val = GLTSYN_CMD_ADJ_TIME; 791 break; 792 case ICE_PTP_ADJ_TIME_AT_TIME: 793 cmd_val = GLTSYN_CMD_ADJ_INIT_TIME; 794 break; 795 case ICE_PTP_NOP: 796 case ICE_PTP_READ_TIME: 797 cmd_val = GLTSYN_CMD_READ_TIME; 798 break; 799 default: 800 dev_warn(ice_hw_to_dev(hw), 801 "Ignoring unrecognized timer command %u\n", cmd); 802 cmd_val = 0; 803 } 804 805 tmr_idx = ice_get_ptp_src_clock_index(hw); 806 807 return tmr_idx << SEL_CPK_SRC | cmd_val; 808 } 809 810 /** 811 * ice_ptp_tmr_cmd_to_port_reg- Convert to port timer command value 812 * @hw: pointer to HW struct 813 * @cmd: Timer command 814 * 815 * Note that some hardware families use a different command register value for 816 * the PHY ports, while other hardware families use the same register values 817 * as the source timer. 818 * 819 * Return: the PHY port timer command register value for the given PTP timer 820 * command. 821 */ 822 static u32 ice_ptp_tmr_cmd_to_port_reg(struct ice_hw *hw, 823 enum ice_ptp_tmr_cmd cmd) 824 { 825 u32 cmd_val, tmr_idx; 826 827 /* Certain hardware families share the same register values for the 828 * port register and source timer register. 829 */ 830 switch (hw->mac_type) { 831 case ICE_MAC_E810: 832 case ICE_MAC_E830: 833 return ice_ptp_tmr_cmd_to_src_reg(hw, cmd) & TS_CMD_MASK_E810; 834 default: 835 break; 836 } 837 838 switch (cmd) { 839 case ICE_PTP_INIT_TIME: 840 cmd_val = PHY_CMD_INIT_TIME; 841 break; 842 case ICE_PTP_INIT_INCVAL: 843 cmd_val = PHY_CMD_INIT_INCVAL; 844 break; 845 case ICE_PTP_ADJ_TIME: 846 cmd_val = PHY_CMD_ADJ_TIME; 847 break; 848 case ICE_PTP_ADJ_TIME_AT_TIME: 849 cmd_val = PHY_CMD_ADJ_TIME_AT_TIME; 850 break; 851 case ICE_PTP_READ_TIME: 852 cmd_val = PHY_CMD_READ_TIME; 853 break; 854 case ICE_PTP_NOP: 855 cmd_val = 0; 856 break; 857 default: 858 dev_warn(ice_hw_to_dev(hw), 859 "Ignoring unrecognized timer command %u\n", cmd); 860 cmd_val = 0; 861 } 862 863 tmr_idx = ice_get_ptp_src_clock_index(hw); 864 865 return tmr_idx << SEL_PHY_SRC | cmd_val; 866 } 867 868 /** 869 * ice_ptp_src_cmd - Prepare source timer for a timer command 870 * @hw: pointer to HW structure 871 * @cmd: Timer command 872 * 873 * Prepare the source timer for an upcoming timer sync command. 874 */ 875 void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 876 { 877 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 878 u32 cmd_val = ice_ptp_tmr_cmd_to_src_reg(hw, cmd); 879 880 if (!ice_is_primary(hw)) 881 hw = ice_get_primary_hw(pf); 882 883 wr32(hw, GLTSYN_CMD, cmd_val); 884 } 885 886 /** 887 * ice_ptp_exec_tmr_cmd - Execute all prepared timer commands 888 * @hw: pointer to HW struct 889 * 890 * Write the SYNC_EXEC_CMD bit to the GLTSYN_CMD_SYNC register, and flush the 891 * write immediately. This triggers the hardware to begin executing all of the 892 * source and PHY timer commands synchronously. 893 */ 894 static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw) 895 { 896 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 897 898 if (!ice_is_primary(hw)) 899 hw = ice_get_primary_hw(pf); 900 901 guard(spinlock)(&pf->adapter->ptp_gltsyn_time_lock); 902 wr32(hw, GLTSYN_CMD_SYNC, SYNC_EXEC_CMD); 903 ice_flush(hw); 904 } 905 906 /** 907 * ice_ptp_cfg_sync_delay - Configure PHC to PHY synchronization delay 908 * @hw: pointer to HW struct 909 * @delay: delay between PHC and PHY SYNC command execution in nanoseconds 910 */ 911 static void ice_ptp_cfg_sync_delay(const struct ice_hw *hw, u32 delay) 912 { 913 wr32(hw, GLTSYN_SYNC_DLAY, delay); 914 ice_flush(hw); 915 } 916 917 /* 56G PHY device functions 918 * 919 * The following functions operate on devices with the ETH 56G PHY. 920 */ 921 922 /** 923 * ice_ptp_get_dest_dev_e825 - get destination PHY for given port number 924 * @hw: pointer to the HW struct 925 * @port: destination port 926 * 927 * Return: destination sideband queue PHY device. 928 */ 929 static enum ice_sbq_dev_id ice_ptp_get_dest_dev_e825(struct ice_hw *hw, 930 u8 port) 931 { 932 u8 curr_phy, tgt_phy; 933 934 tgt_phy = port >= hw->ptp.ports_per_phy; 935 curr_phy = hw->lane_num >= hw->ptp.ports_per_phy; 936 /* In the driver, lanes 4..7 are in fact 0..3 on a second PHY. 937 * On a single complex E825C, PHY 0 is always destination device phy_0 938 * and PHY 1 is phy_0_peer. 939 * On dual complex E825C, device phy_0 points to PHY on a current 940 * complex and phy_0_peer to PHY on a different complex. 941 */ 942 if ((!ice_is_dual(hw) && tgt_phy == 1) || 943 (ice_is_dual(hw) && tgt_phy != curr_phy)) 944 return ice_sbq_dev_phy_0_peer; 945 else 946 return ice_sbq_dev_phy_0; 947 } 948 949 /** 950 * ice_write_phy_eth56g - Write a PHY port register 951 * @hw: pointer to the HW struct 952 * @port: destination port 953 * @addr: PHY register address 954 * @val: Value to write 955 * 956 * Return: 0 on success, other error codes when failed to write to PHY 957 */ 958 static int ice_write_phy_eth56g(struct ice_hw *hw, u8 port, u32 addr, u32 val) 959 { 960 struct ice_sbq_msg_input msg = { 961 .dest_dev = ice_ptp_get_dest_dev_e825(hw, port), 962 .opcode = ice_sbq_msg_wr, 963 .msg_addr_low = lower_16_bits(addr), 964 .msg_addr_high = upper_16_bits(addr), 965 .data = val 966 }; 967 int err; 968 969 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 970 if (err) 971 ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n", 972 err); 973 974 return err; 975 } 976 977 /** 978 * ice_read_phy_eth56g - Read a PHY port register 979 * @hw: pointer to the HW struct 980 * @port: destination port 981 * @addr: PHY register address 982 * @val: Value to write 983 * 984 * Return: 0 on success, other error codes when failed to read from PHY 985 */ 986 static int ice_read_phy_eth56g(struct ice_hw *hw, u8 port, u32 addr, u32 *val) 987 { 988 struct ice_sbq_msg_input msg = { 989 .dest_dev = ice_ptp_get_dest_dev_e825(hw, port), 990 .opcode = ice_sbq_msg_rd, 991 .msg_addr_low = lower_16_bits(addr), 992 .msg_addr_high = upper_16_bits(addr) 993 }; 994 int err; 995 996 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 997 if (err) 998 ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n", 999 err); 1000 else 1001 *val = msg.data; 1002 1003 return err; 1004 } 1005 1006 /** 1007 * ice_phy_res_address_eth56g - Calculate a PHY port register address 1008 * @hw: pointer to the HW struct 1009 * @lane: Lane number to be written 1010 * @res_type: resource type (register/memory) 1011 * @offset: Offset from PHY port register base 1012 * @addr: The result address 1013 * 1014 * Return: 1015 * * %0 - success 1016 * * %EINVAL - invalid port number or resource type 1017 */ 1018 static int ice_phy_res_address_eth56g(struct ice_hw *hw, u8 lane, 1019 enum eth56g_res_type res_type, 1020 u32 offset, 1021 u32 *addr) 1022 { 1023 if (res_type >= NUM_ETH56G_PHY_RES) 1024 return -EINVAL; 1025 1026 /* Lanes 4..7 are in fact 0..3 on a second PHY */ 1027 lane %= hw->ptp.ports_per_phy; 1028 *addr = eth56g_phy_res[res_type].base_addr + 1029 lane * eth56g_phy_res[res_type].step + offset; 1030 1031 return 0; 1032 } 1033 1034 /** 1035 * ice_write_port_eth56g - Write a PHY port register 1036 * @hw: pointer to the HW struct 1037 * @offset: PHY register offset 1038 * @port: Port number 1039 * @val: Value to write 1040 * @res_type: resource type (register/memory) 1041 * 1042 * Return: 1043 * * %0 - success 1044 * * %EINVAL - invalid port number or resource type 1045 * * %other - failed to write to PHY 1046 */ 1047 static int ice_write_port_eth56g(struct ice_hw *hw, u8 port, u32 offset, 1048 u32 val, enum eth56g_res_type res_type) 1049 { 1050 u32 addr; 1051 int err; 1052 1053 if (port >= hw->ptp.num_lports) 1054 return -EINVAL; 1055 1056 err = ice_phy_res_address_eth56g(hw, port, res_type, offset, &addr); 1057 if (err) 1058 return err; 1059 1060 return ice_write_phy_eth56g(hw, port, addr, val); 1061 } 1062 1063 /** 1064 * ice_read_port_eth56g - Read a PHY port register 1065 * @hw: pointer to the HW struct 1066 * @offset: PHY register offset 1067 * @port: Port number 1068 * @val: Value to write 1069 * @res_type: resource type (register/memory) 1070 * 1071 * Return: 1072 * * %0 - success 1073 * * %EINVAL - invalid port number or resource type 1074 * * %other - failed to read from PHY 1075 */ 1076 static int ice_read_port_eth56g(struct ice_hw *hw, u8 port, u32 offset, 1077 u32 *val, enum eth56g_res_type res_type) 1078 { 1079 u32 addr; 1080 int err; 1081 1082 if (port >= hw->ptp.num_lports) 1083 return -EINVAL; 1084 1085 err = ice_phy_res_address_eth56g(hw, port, res_type, offset, &addr); 1086 if (err) 1087 return err; 1088 1089 return ice_read_phy_eth56g(hw, port, addr, val); 1090 } 1091 1092 /** 1093 * ice_write_ptp_reg_eth56g - Write a PHY port register 1094 * @hw: pointer to the HW struct 1095 * @port: Port number to be written 1096 * @offset: Offset from PHY port register base 1097 * @val: Value to write 1098 * 1099 * Return: 1100 * * %0 - success 1101 * * %EINVAL - invalid port number or resource type 1102 * * %other - failed to write to PHY 1103 */ 1104 static int ice_write_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1105 u32 val) 1106 { 1107 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_PTP); 1108 } 1109 1110 /** 1111 * ice_write_mac_reg_eth56g - Write a MAC PHY port register 1112 * parameter 1113 * @hw: pointer to the HW struct 1114 * @port: Port number to be written 1115 * @offset: Offset from PHY port register base 1116 * @val: Value to write 1117 * 1118 * Return: 1119 * * %0 - success 1120 * * %EINVAL - invalid port number or resource type 1121 * * %other - failed to write to PHY 1122 */ 1123 static int ice_write_mac_reg_eth56g(struct ice_hw *hw, u8 port, u32 offset, 1124 u32 val) 1125 { 1126 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_MAC); 1127 } 1128 1129 /** 1130 * ice_write_xpcs_reg_eth56g - Write a PHY port register 1131 * @hw: pointer to the HW struct 1132 * @port: Port number to be written 1133 * @offset: Offset from PHY port register base 1134 * @val: Value to write 1135 * 1136 * Return: 1137 * * %0 - success 1138 * * %EINVAL - invalid port number or resource type 1139 * * %other - failed to write to PHY 1140 */ 1141 static int ice_write_xpcs_reg_eth56g(struct ice_hw *hw, u8 port, u32 offset, 1142 u32 val) 1143 { 1144 return ice_write_port_eth56g(hw, port, offset, val, 1145 ETH56G_PHY_REG_XPCS); 1146 } 1147 1148 /** 1149 * ice_read_ptp_reg_eth56g - Read a PHY port register 1150 * @hw: pointer to the HW struct 1151 * @port: Port number to be read 1152 * @offset: Offset from PHY port register base 1153 * @val: Pointer to the value to read (out param) 1154 * 1155 * Return: 1156 * * %0 - success 1157 * * %EINVAL - invalid port number or resource type 1158 * * %other - failed to read from PHY 1159 */ 1160 static int ice_read_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1161 u32 *val) 1162 { 1163 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_PTP); 1164 } 1165 1166 /** 1167 * ice_read_mac_reg_eth56g - Read a PHY port register 1168 * @hw: pointer to the HW struct 1169 * @port: Port number to be read 1170 * @offset: Offset from PHY port register base 1171 * @val: Pointer to the value to read (out param) 1172 * 1173 * Return: 1174 * * %0 - success 1175 * * %EINVAL - invalid port number or resource type 1176 * * %other - failed to read from PHY 1177 */ 1178 static int ice_read_mac_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1179 u32 *val) 1180 { 1181 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_MAC); 1182 } 1183 1184 /** 1185 * ice_read_gpcs_reg_eth56g - Read a PHY port register 1186 * @hw: pointer to the HW struct 1187 * @port: Port number to be read 1188 * @offset: Offset from PHY port register base 1189 * @val: Pointer to the value to read (out param) 1190 * 1191 * Return: 1192 * * %0 - success 1193 * * %EINVAL - invalid port number or resource type 1194 * * %other - failed to read from PHY 1195 */ 1196 static int ice_read_gpcs_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1197 u32 *val) 1198 { 1199 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_GPCS); 1200 } 1201 1202 /** 1203 * ice_read_port_mem_eth56g - Read a PHY port memory location 1204 * @hw: pointer to the HW struct 1205 * @port: Port number to be read 1206 * @offset: Offset from PHY port register base 1207 * @val: Pointer to the value to read (out param) 1208 * 1209 * Return: 1210 * * %0 - success 1211 * * %EINVAL - invalid port number or resource type 1212 * * %other - failed to read from PHY 1213 */ 1214 static int ice_read_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1215 u32 *val) 1216 { 1217 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_MEM_PTP); 1218 } 1219 1220 /** 1221 * ice_write_port_mem_eth56g - Write a PHY port memory location 1222 * @hw: pointer to the HW struct 1223 * @port: Port number to be read 1224 * @offset: Offset from PHY port register base 1225 * @val: Pointer to the value to read (out param) 1226 * 1227 * Return: 1228 * * %0 - success 1229 * * %EINVAL - invalid port number or resource type 1230 * * %other - failed to write to PHY 1231 */ 1232 static int ice_write_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1233 u32 val) 1234 { 1235 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_MEM_PTP); 1236 } 1237 1238 /** 1239 * ice_write_quad_ptp_reg_eth56g - Write a PHY quad register 1240 * @hw: pointer to the HW struct 1241 * @offset: PHY register offset 1242 * @port: Port number 1243 * @val: Value to write 1244 * 1245 * Return: 1246 * * %0 - success 1247 * * %EIO - invalid port number or resource type 1248 * * %other - failed to write to PHY 1249 */ 1250 static int ice_write_quad_ptp_reg_eth56g(struct ice_hw *hw, u8 port, 1251 u32 offset, u32 val) 1252 { 1253 u32 addr; 1254 1255 if (port >= hw->ptp.num_lports) 1256 return -EIO; 1257 1258 addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base_addr + offset; 1259 1260 return ice_write_phy_eth56g(hw, port, addr, val); 1261 } 1262 1263 /** 1264 * ice_read_quad_ptp_reg_eth56g - Read a PHY quad register 1265 * @hw: pointer to the HW struct 1266 * @offset: PHY register offset 1267 * @port: Port number 1268 * @val: Value to read 1269 * 1270 * Return: 1271 * * %0 - success 1272 * * %EIO - invalid port number or resource type 1273 * * %other - failed to read from PHY 1274 */ 1275 static int ice_read_quad_ptp_reg_eth56g(struct ice_hw *hw, u8 port, 1276 u32 offset, u32 *val) 1277 { 1278 u32 addr; 1279 1280 if (port >= hw->ptp.num_lports) 1281 return -EIO; 1282 1283 addr = eth56g_phy_res[ETH56G_PHY_REG_PTP].base_addr + offset; 1284 1285 return ice_read_phy_eth56g(hw, port, addr, val); 1286 } 1287 1288 /** 1289 * ice_is_64b_phy_reg_eth56g - Check if this is a 64bit PHY register 1290 * @low_addr: the low address to check 1291 * @high_addr: on return, contains the high address of the 64bit register 1292 * 1293 * Write the appropriate high register offset to use. 1294 * 1295 * Return: true if the provided low address is one of the known 64bit PHY values 1296 * represented as two 32bit registers, false otherwise. 1297 */ 1298 static bool ice_is_64b_phy_reg_eth56g(u16 low_addr, u16 *high_addr) 1299 { 1300 switch (low_addr) { 1301 case PHY_REG_TX_TIMER_INC_PRE_L: 1302 *high_addr = PHY_REG_TX_TIMER_INC_PRE_U; 1303 return true; 1304 case PHY_REG_RX_TIMER_INC_PRE_L: 1305 *high_addr = PHY_REG_RX_TIMER_INC_PRE_U; 1306 return true; 1307 case PHY_REG_TX_CAPTURE_L: 1308 *high_addr = PHY_REG_TX_CAPTURE_U; 1309 return true; 1310 case PHY_REG_RX_CAPTURE_L: 1311 *high_addr = PHY_REG_RX_CAPTURE_U; 1312 return true; 1313 case PHY_REG_TOTAL_TX_OFFSET_L: 1314 *high_addr = PHY_REG_TOTAL_TX_OFFSET_U; 1315 return true; 1316 case PHY_REG_TOTAL_RX_OFFSET_L: 1317 *high_addr = PHY_REG_TOTAL_RX_OFFSET_U; 1318 return true; 1319 case PHY_REG_TX_MEMORY_STATUS_L: 1320 *high_addr = PHY_REG_TX_MEMORY_STATUS_U; 1321 return true; 1322 default: 1323 return false; 1324 } 1325 } 1326 1327 /** 1328 * ice_is_40b_phy_reg_eth56g - Check if this is a 40bit PHY register 1329 * @low_addr: the low address to check 1330 * @high_addr: on return, contains the high address of the 40bit value 1331 * 1332 * Write the appropriate high register offset to use. 1333 * 1334 * Return: true if the provided low address is one of the known 40bit PHY 1335 * values split into two registers with the lower 8 bits in the low register and 1336 * the upper 32 bits in the high register, false otherwise. 1337 */ 1338 static bool ice_is_40b_phy_reg_eth56g(u16 low_addr, u16 *high_addr) 1339 { 1340 switch (low_addr) { 1341 case PHY_REG_TIMETUS_L: 1342 *high_addr = PHY_REG_TIMETUS_U; 1343 return true; 1344 case PHY_PCS_REF_TUS_L: 1345 *high_addr = PHY_PCS_REF_TUS_U; 1346 return true; 1347 case PHY_PCS_REF_INC_L: 1348 *high_addr = PHY_PCS_REF_INC_U; 1349 return true; 1350 default: 1351 return false; 1352 } 1353 } 1354 1355 /** 1356 * ice_read_64b_phy_reg_eth56g - Read a 64bit value from PHY registers 1357 * @hw: pointer to the HW struct 1358 * @port: PHY port to read from 1359 * @low_addr: offset of the lower register to read from 1360 * @val: on return, the contents of the 64bit value from the PHY registers 1361 * @res_type: resource type 1362 * 1363 * Check if the caller has specified a known 40 bit register offset and read 1364 * the two registers associated with a 40bit value and return it in the val 1365 * pointer. 1366 * 1367 * Return: 1368 * * %0 - success 1369 * * %EINVAL - not a 64 bit register 1370 * * %other - failed to read from PHY 1371 */ 1372 static int ice_read_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, 1373 u64 *val, enum eth56g_res_type res_type) 1374 { 1375 u16 high_addr; 1376 u32 lo, hi; 1377 int err; 1378 1379 if (!ice_is_64b_phy_reg_eth56g(low_addr, &high_addr)) 1380 return -EINVAL; 1381 1382 err = ice_read_port_eth56g(hw, port, low_addr, &lo, res_type); 1383 if (err) { 1384 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register %#08x\n, err %d", 1385 low_addr, err); 1386 return err; 1387 } 1388 1389 err = ice_read_port_eth56g(hw, port, high_addr, &hi, res_type); 1390 if (err) { 1391 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register %#08x\n, err %d", 1392 high_addr, err); 1393 return err; 1394 } 1395 1396 *val = ((u64)hi << 32) | lo; 1397 1398 return 0; 1399 } 1400 1401 /** 1402 * ice_read_64b_ptp_reg_eth56g - Read a 64bit value from PHY registers 1403 * @hw: pointer to the HW struct 1404 * @port: PHY port to read from 1405 * @low_addr: offset of the lower register to read from 1406 * @val: on return, the contents of the 64bit value from the PHY registers 1407 * 1408 * Check if the caller has specified a known 40 bit register offset and read 1409 * the two registers associated with a 40bit value and return it in the val 1410 * pointer. 1411 * 1412 * Return: 1413 * * %0 - success 1414 * * %EINVAL - not a 64 bit register 1415 * * %other - failed to read from PHY 1416 */ 1417 static int ice_read_64b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, 1418 u64 *val) 1419 { 1420 return ice_read_64b_phy_reg_eth56g(hw, port, low_addr, val, 1421 ETH56G_PHY_REG_PTP); 1422 } 1423 1424 /** 1425 * ice_write_40b_phy_reg_eth56g - Write a 40b value to the PHY 1426 * @hw: pointer to the HW struct 1427 * @port: port to write to 1428 * @low_addr: offset of the low register 1429 * @val: 40b value to write 1430 * @res_type: resource type 1431 * 1432 * Check if the caller has specified a known 40 bit register offset and write 1433 * provided 40b value to the two associated registers by splitting it up into 1434 * two chunks, the lower 8 bits and the upper 32 bits. 1435 * 1436 * Return: 1437 * * %0 - success 1438 * * %EINVAL - not a 40 bit register 1439 * * %other - failed to write to PHY 1440 */ 1441 static int ice_write_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port, 1442 u16 low_addr, u64 val, 1443 enum eth56g_res_type res_type) 1444 { 1445 u16 high_addr; 1446 u32 lo, hi; 1447 int err; 1448 1449 if (!ice_is_40b_phy_reg_eth56g(low_addr, &high_addr)) 1450 return -EINVAL; 1451 1452 lo = FIELD_GET(P_REG_40B_LOW_M, val); 1453 hi = (u32)(val >> P_REG_40B_HIGH_S); 1454 1455 err = ice_write_port_eth56g(hw, port, low_addr, lo, res_type); 1456 if (err) { 1457 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 1458 low_addr, err); 1459 return err; 1460 } 1461 1462 err = ice_write_port_eth56g(hw, port, high_addr, hi, res_type); 1463 if (err) { 1464 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 1465 high_addr, err); 1466 return err; 1467 } 1468 1469 return 0; 1470 } 1471 1472 /** 1473 * ice_write_40b_ptp_reg_eth56g - Write a 40b value to the PHY 1474 * @hw: pointer to the HW struct 1475 * @port: port to write to 1476 * @low_addr: offset of the low register 1477 * @val: 40b value to write 1478 * 1479 * Check if the caller has specified a known 40 bit register offset and write 1480 * provided 40b value to the two associated registers by splitting it up into 1481 * two chunks, the lower 8 bits and the upper 32 bits. 1482 * 1483 * Return: 1484 * * %0 - success 1485 * * %EINVAL - not a 40 bit register 1486 * * %other - failed to write to PHY 1487 */ 1488 static int ice_write_40b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, 1489 u16 low_addr, u64 val) 1490 { 1491 return ice_write_40b_phy_reg_eth56g(hw, port, low_addr, val, 1492 ETH56G_PHY_REG_PTP); 1493 } 1494 1495 /** 1496 * ice_write_64b_phy_reg_eth56g - Write a 64bit value to PHY registers 1497 * @hw: pointer to the HW struct 1498 * @port: PHY port to read from 1499 * @low_addr: offset of the lower register to read from 1500 * @val: the contents of the 64bit value to write to PHY 1501 * @res_type: resource type 1502 * 1503 * Check if the caller has specified a known 64 bit register offset and write 1504 * the 64bit value to the two associated 32bit PHY registers. 1505 * 1506 * Return: 1507 * * %0 - success 1508 * * %EINVAL - not a 64 bit register 1509 * * %other - failed to write to PHY 1510 */ 1511 static int ice_write_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, 1512 u16 low_addr, u64 val, 1513 enum eth56g_res_type res_type) 1514 { 1515 u16 high_addr; 1516 u32 lo, hi; 1517 int err; 1518 1519 if (!ice_is_64b_phy_reg_eth56g(low_addr, &high_addr)) 1520 return -EINVAL; 1521 1522 lo = lower_32_bits(val); 1523 hi = upper_32_bits(val); 1524 1525 err = ice_write_port_eth56g(hw, port, low_addr, lo, res_type); 1526 if (err) { 1527 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 1528 low_addr, err); 1529 return err; 1530 } 1531 1532 err = ice_write_port_eth56g(hw, port, high_addr, hi, res_type); 1533 if (err) { 1534 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 1535 high_addr, err); 1536 return err; 1537 } 1538 1539 return 0; 1540 } 1541 1542 /** 1543 * ice_write_64b_ptp_reg_eth56g - Write a 64bit value to PHY registers 1544 * @hw: pointer to the HW struct 1545 * @port: PHY port to read from 1546 * @low_addr: offset of the lower register to read from 1547 * @val: the contents of the 64bit value to write to PHY 1548 * 1549 * Check if the caller has specified a known 64 bit register offset and write 1550 * the 64bit value to the two associated 32bit PHY registers. 1551 * 1552 * Return: 1553 * * %0 - success 1554 * * %EINVAL - not a 64 bit register 1555 * * %other - failed to write to PHY 1556 */ 1557 static int ice_write_64b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, 1558 u16 low_addr, u64 val) 1559 { 1560 return ice_write_64b_phy_reg_eth56g(hw, port, low_addr, val, 1561 ETH56G_PHY_REG_PTP); 1562 } 1563 1564 /** 1565 * ice_read_ptp_tstamp_eth56g - Read a PHY timestamp out of the port memory 1566 * @hw: pointer to the HW struct 1567 * @port: the port to read from 1568 * @idx: the timestamp index to read 1569 * @tstamp: on return, the 40bit timestamp value 1570 * 1571 * Read a 40bit timestamp value out of the two associated entries in the 1572 * port memory block of the internal PHYs of the 56G devices. 1573 * 1574 * Return: 1575 * * %0 - success 1576 * * %other - failed to read from PHY 1577 */ 1578 static int ice_read_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx, 1579 u64 *tstamp) 1580 { 1581 u16 lo_addr, hi_addr; 1582 u32 lo, hi; 1583 int err; 1584 1585 lo_addr = (u16)PHY_TSTAMP_L(idx); 1586 hi_addr = (u16)PHY_TSTAMP_U(idx); 1587 1588 err = ice_read_port_mem_eth56g(hw, port, lo_addr, &lo); 1589 if (err) { 1590 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 1591 err); 1592 return err; 1593 } 1594 1595 err = ice_read_port_mem_eth56g(hw, port, hi_addr, &hi); 1596 if (err) { 1597 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 1598 err); 1599 return err; 1600 } 1601 1602 /* For 56G based internal PHYs, the timestamp is reported with the 1603 * lower 8 bits in the low register, and the upper 32 bits in the high 1604 * register. 1605 */ 1606 *tstamp = FIELD_PREP(PHY_40B_HIGH_M, hi) | 1607 FIELD_PREP(PHY_40B_LOW_M, lo); 1608 return 0; 1609 } 1610 1611 /** 1612 * ice_clear_ptp_tstamp_eth56g - Clear a timestamp from the quad block 1613 * @hw: pointer to the HW struct 1614 * @port: the quad to read from 1615 * @idx: the timestamp index to reset 1616 * 1617 * Read and then forcibly clear the timestamp index to ensure the valid bit is 1618 * cleared and the timestamp status bit is reset in the PHY port memory of 1619 * internal PHYs of the 56G devices. 1620 * 1621 * To directly clear the contents of the timestamp block entirely, discarding 1622 * all timestamp data at once, software should instead use 1623 * ice_ptp_reset_ts_memory_quad_eth56g(). 1624 * 1625 * This function should only be called on an idx whose bit is set according to 1626 * ice_get_phy_tx_tstamp_ready(). 1627 * 1628 * Return: 1629 * * %0 - success 1630 * * %other - failed to write to PHY 1631 */ 1632 static int ice_clear_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx) 1633 { 1634 u64 unused_tstamp; 1635 u16 lo_addr; 1636 int err; 1637 1638 /* Read the timestamp register to ensure the timestamp status bit is 1639 * cleared. 1640 */ 1641 err = ice_read_ptp_tstamp_eth56g(hw, port, idx, &unused_tstamp); 1642 if (err) { 1643 ice_debug(hw, ICE_DBG_PTP, "Failed to read the PHY timestamp register for port %u, idx %u, err %d\n", 1644 port, idx, err); 1645 } 1646 1647 lo_addr = (u16)PHY_TSTAMP_L(idx); 1648 1649 err = ice_write_port_mem_eth56g(hw, port, lo_addr, 0); 1650 if (err) { 1651 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for port %u, idx %u, err %d\n", 1652 port, idx, err); 1653 return err; 1654 } 1655 1656 return 0; 1657 } 1658 1659 /** 1660 * ice_ptp_reset_ts_memory_eth56g - Clear all timestamps from the port block 1661 * @hw: pointer to the HW struct 1662 */ 1663 static void ice_ptp_reset_ts_memory_eth56g(struct ice_hw *hw) 1664 { 1665 unsigned int port; 1666 1667 for (port = 0; port < hw->ptp.num_lports; port++) { 1668 ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L, 1669 0); 1670 ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_U, 1671 0); 1672 } 1673 } 1674 1675 /** 1676 * ice_ptp_prep_port_time_eth56g - Prepare one PHY port with initial time 1677 * @hw: pointer to the HW struct 1678 * @port: port number 1679 * @time: time to initialize the PHY port clocks to 1680 * 1681 * Write a new initial time value into registers of a specific PHY port. 1682 * 1683 * Return: 1684 * * %0 - success 1685 * * %other - failed to write to PHY 1686 */ 1687 static int ice_ptp_prep_port_time_eth56g(struct ice_hw *hw, u8 port, 1688 u64 time) 1689 { 1690 int err; 1691 1692 /* Tx case */ 1693 err = ice_write_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_L, 1694 time); 1695 if (err) 1696 return err; 1697 1698 /* Rx case */ 1699 return ice_write_64b_ptp_reg_eth56g(hw, port, 1700 PHY_REG_RX_TIMER_INC_PRE_L, time); 1701 } 1702 1703 /** 1704 * ice_ptp_prep_phy_time_eth56g - Prepare PHY port with initial time 1705 * @hw: pointer to the HW struct 1706 * @time: Time to initialize the PHY port clocks to 1707 * 1708 * Program the PHY port registers with a new initial time value. The port 1709 * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync 1710 * command. The time value is the upper 32 bits of the PHY timer, usually in 1711 * units of nominal nanoseconds. 1712 * 1713 * Return: 1714 * * %0 - success 1715 * * %other - failed to write to PHY 1716 */ 1717 static int ice_ptp_prep_phy_time_eth56g(struct ice_hw *hw, u32 time) 1718 { 1719 u64 phy_time; 1720 u8 port; 1721 1722 /* The time represents the upper 32 bits of the PHY timer, so we need 1723 * to shift to account for this when programming. 1724 */ 1725 phy_time = (u64)time << 32; 1726 1727 for (port = 0; port < hw->ptp.num_lports; port++) { 1728 int err; 1729 1730 err = ice_ptp_prep_port_time_eth56g(hw, port, phy_time); 1731 if (err) { 1732 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n", 1733 port, err); 1734 return err; 1735 } 1736 } 1737 1738 return 0; 1739 } 1740 1741 /** 1742 * ice_ptp_prep_port_adj_eth56g - Prepare a single port for time adjust 1743 * @hw: pointer to HW struct 1744 * @port: Port number to be programmed 1745 * @time: time in cycles to adjust the port clocks 1746 * 1747 * Program the port for an atomic adjustment by writing the Tx and Rx timer 1748 * registers. The atomic adjustment won't be completed until the driver issues 1749 * an ICE_PTP_ADJ_TIME command. 1750 * 1751 * Note that time is not in units of nanoseconds. It is in clock time 1752 * including the lower sub-nanosecond portion of the port timer. 1753 * 1754 * Negative adjustments are supported using 2s complement arithmetic. 1755 * 1756 * Return: 1757 * * %0 - success 1758 * * %other - failed to write to PHY 1759 */ 1760 static int ice_ptp_prep_port_adj_eth56g(struct ice_hw *hw, u8 port, s64 time) 1761 { 1762 u32 l_time, u_time; 1763 int err; 1764 1765 l_time = lower_32_bits(time); 1766 u_time = upper_32_bits(time); 1767 1768 /* Tx case */ 1769 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_L, 1770 l_time); 1771 if (err) 1772 goto exit_err; 1773 1774 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_U, 1775 u_time); 1776 if (err) 1777 goto exit_err; 1778 1779 /* Rx case */ 1780 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TIMER_INC_PRE_L, 1781 l_time); 1782 if (err) 1783 goto exit_err; 1784 1785 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TIMER_INC_PRE_U, 1786 u_time); 1787 if (err) 1788 goto exit_err; 1789 1790 return 0; 1791 1792 exit_err: 1793 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n", 1794 port, err); 1795 return err; 1796 } 1797 1798 /** 1799 * ice_ptp_prep_phy_adj_eth56g - Prep PHY ports for a time adjustment 1800 * @hw: pointer to HW struct 1801 * @adj: adjustment in nanoseconds 1802 * 1803 * Prepare the PHY ports for an atomic time adjustment by programming the PHY 1804 * Tx and Rx port registers. The actual adjustment is completed by issuing an 1805 * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command. 1806 * 1807 * Return: 1808 * * %0 - success 1809 * * %other - failed to write to PHY 1810 */ 1811 static int ice_ptp_prep_phy_adj_eth56g(struct ice_hw *hw, s32 adj) 1812 { 1813 s64 cycles; 1814 u8 port; 1815 1816 /* The port clock supports adjustment of the sub-nanosecond portion of 1817 * the clock (lowest 32 bits). We shift the provided adjustment in 1818 * nanoseconds by 32 to calculate the appropriate adjustment to program 1819 * into the PHY ports. 1820 */ 1821 cycles = (s64)adj << 32; 1822 1823 for (port = 0; port < hw->ptp.num_lports; port++) { 1824 int err; 1825 1826 err = ice_ptp_prep_port_adj_eth56g(hw, port, cycles); 1827 if (err) 1828 return err; 1829 } 1830 1831 return 0; 1832 } 1833 1834 /** 1835 * ice_ptp_prep_phy_incval_eth56g - Prepare PHY ports for time adjustment 1836 * @hw: pointer to HW struct 1837 * @incval: new increment value to prepare 1838 * 1839 * Prepare each of the PHY ports for a new increment value by programming the 1840 * port's TIMETUS registers. The new increment value will be updated after 1841 * issuing an ICE_PTP_INIT_INCVAL command. 1842 * 1843 * Return: 1844 * * %0 - success 1845 * * %other - failed to write to PHY 1846 */ 1847 static int ice_ptp_prep_phy_incval_eth56g(struct ice_hw *hw, u64 incval) 1848 { 1849 u8 port; 1850 1851 for (port = 0; port < hw->ptp.num_lports; port++) { 1852 int err; 1853 1854 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_REG_TIMETUS_L, 1855 incval); 1856 if (err) { 1857 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n", 1858 port, err); 1859 return err; 1860 } 1861 } 1862 1863 return 0; 1864 } 1865 1866 /** 1867 * ice_ptp_read_port_capture_eth56g - Read a port's local time capture 1868 * @hw: pointer to HW struct 1869 * @port: Port number to read 1870 * @tx_ts: on return, the Tx port time capture 1871 * @rx_ts: on return, the Rx port time capture 1872 * 1873 * Read the port's Tx and Rx local time capture values. 1874 * 1875 * Return: 1876 * * %0 - success 1877 * * %other - failed to read from PHY 1878 */ 1879 static int ice_ptp_read_port_capture_eth56g(struct ice_hw *hw, u8 port, 1880 u64 *tx_ts, u64 *rx_ts) 1881 { 1882 int err; 1883 1884 /* Tx case */ 1885 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_CAPTURE_L, 1886 tx_ts); 1887 if (err) { 1888 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n", 1889 err); 1890 return err; 1891 } 1892 1893 ice_debug(hw, ICE_DBG_PTP, "tx_init = %#016llx\n", *tx_ts); 1894 1895 /* Rx case */ 1896 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_RX_CAPTURE_L, 1897 rx_ts); 1898 if (err) { 1899 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n", 1900 err); 1901 return err; 1902 } 1903 1904 ice_debug(hw, ICE_DBG_PTP, "rx_init = %#016llx\n", *rx_ts); 1905 1906 return 0; 1907 } 1908 1909 /** 1910 * ice_ptp_write_port_cmd_eth56g - Prepare a single PHY port for a timer command 1911 * @hw: pointer to HW struct 1912 * @port: Port to which cmd has to be sent 1913 * @cmd: Command to be sent to the port 1914 * 1915 * Prepare the requested port for an upcoming timer sync command. 1916 * 1917 * Return: 1918 * * %0 - success 1919 * * %other - failed to write to PHY 1920 */ 1921 static int ice_ptp_write_port_cmd_eth56g(struct ice_hw *hw, u8 port, 1922 enum ice_ptp_tmr_cmd cmd) 1923 { 1924 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 1925 int err; 1926 1927 /* Tx case */ 1928 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TMR_CMD, val); 1929 if (err) { 1930 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n", 1931 err); 1932 return err; 1933 } 1934 1935 /* Rx case */ 1936 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TMR_CMD, val); 1937 if (err) { 1938 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n", 1939 err); 1940 return err; 1941 } 1942 1943 return 0; 1944 } 1945 1946 /** 1947 * ice_phy_get_speed_eth56g - Get link speed based on PHY link type 1948 * @li: pointer to link information struct 1949 * 1950 * Return: simplified ETH56G PHY speed 1951 */ 1952 static enum ice_eth56g_link_spd 1953 ice_phy_get_speed_eth56g(struct ice_link_status *li) 1954 { 1955 u16 speed = ice_get_link_speed_based_on_phy_type(li->phy_type_low, 1956 li->phy_type_high); 1957 1958 switch (speed) { 1959 case ICE_AQ_LINK_SPEED_1000MB: 1960 return ICE_ETH56G_LNK_SPD_1G; 1961 case ICE_AQ_LINK_SPEED_2500MB: 1962 return ICE_ETH56G_LNK_SPD_2_5G; 1963 case ICE_AQ_LINK_SPEED_10GB: 1964 return ICE_ETH56G_LNK_SPD_10G; 1965 case ICE_AQ_LINK_SPEED_25GB: 1966 return ICE_ETH56G_LNK_SPD_25G; 1967 case ICE_AQ_LINK_SPEED_40GB: 1968 return ICE_ETH56G_LNK_SPD_40G; 1969 case ICE_AQ_LINK_SPEED_50GB: 1970 switch (li->phy_type_low) { 1971 case ICE_PHY_TYPE_LOW_50GBASE_SR: 1972 case ICE_PHY_TYPE_LOW_50GBASE_FR: 1973 case ICE_PHY_TYPE_LOW_50GBASE_LR: 1974 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 1975 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 1976 case ICE_PHY_TYPE_LOW_50G_AUI1: 1977 return ICE_ETH56G_LNK_SPD_50G; 1978 default: 1979 return ICE_ETH56G_LNK_SPD_50G2; 1980 } 1981 case ICE_AQ_LINK_SPEED_100GB: 1982 if (li->phy_type_high || 1983 li->phy_type_low == ICE_PHY_TYPE_LOW_100GBASE_SR2) 1984 return ICE_ETH56G_LNK_SPD_100G2; 1985 else 1986 return ICE_ETH56G_LNK_SPD_100G; 1987 default: 1988 return ICE_ETH56G_LNK_SPD_1G; 1989 } 1990 } 1991 1992 /** 1993 * ice_phy_cfg_parpcs_eth56g - Configure TUs per PAR/PCS clock cycle 1994 * @hw: pointer to the HW struct 1995 * @port: port to configure 1996 * 1997 * Configure the number of TUs for the PAR and PCS clocks used as part of the 1998 * timestamp calibration process. 1999 * 2000 * Return: 2001 * * %0 - success 2002 * * %other - PHY read/write failed 2003 */ 2004 static int ice_phy_cfg_parpcs_eth56g(struct ice_hw *hw, u8 port) 2005 { 2006 u32 val; 2007 int err; 2008 2009 err = ice_write_xpcs_reg_eth56g(hw, port, PHY_VENDOR_TXLANE_THRESH, 2010 ICE_ETH56G_NOMINAL_THRESH4); 2011 if (err) { 2012 ice_debug(hw, ICE_DBG_PTP, "Failed to read VENDOR_TXLANE_THRESH, status: %d", 2013 err); 2014 return err; 2015 } 2016 2017 switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) { 2018 case ICE_ETH56G_LNK_SPD_1G: 2019 case ICE_ETH56G_LNK_SPD_2_5G: 2020 err = ice_read_quad_ptp_reg_eth56g(hw, port, 2021 PHY_GPCS_CONFIG_REG0, &val); 2022 if (err) { 2023 ice_debug(hw, ICE_DBG_PTP, "Failed to read PHY_GPCS_CONFIG_REG0, status: %d", 2024 err); 2025 return err; 2026 } 2027 2028 val &= ~PHY_GPCS_CONFIG_REG0_TX_THR_M; 2029 val |= FIELD_PREP(PHY_GPCS_CONFIG_REG0_TX_THR_M, 2030 ICE_ETH56G_NOMINAL_TX_THRESH); 2031 2032 err = ice_write_quad_ptp_reg_eth56g(hw, port, 2033 PHY_GPCS_CONFIG_REG0, val); 2034 if (err) { 2035 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_GPCS_CONFIG_REG0, status: %d", 2036 err); 2037 return err; 2038 } 2039 break; 2040 default: 2041 break; 2042 } 2043 2044 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_PCS_REF_TUS_L, 2045 ICE_ETH56G_NOMINAL_PCS_REF_TUS); 2046 if (err) { 2047 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_PCS_REF_TUS, status: %d", 2048 err); 2049 return err; 2050 } 2051 2052 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_PCS_REF_INC_L, 2053 ICE_ETH56G_NOMINAL_PCS_REF_INC); 2054 if (err) { 2055 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_PCS_REF_INC, status: %d", 2056 err); 2057 return err; 2058 } 2059 2060 return 0; 2061 } 2062 2063 /** 2064 * ice_phy_cfg_ptp_1step_eth56g - Configure 1-step PTP settings 2065 * @hw: Pointer to the HW struct 2066 * @port: Port to configure 2067 * 2068 * Return: 2069 * * %0 - success 2070 * * %other - PHY read/write failed 2071 */ 2072 int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port) 2073 { 2074 u8 quad_lane = port % ICE_PORTS_PER_QUAD; 2075 u32 addr, val, peer_delay; 2076 bool enable, sfd_ena; 2077 int err; 2078 2079 enable = hw->ptp.phy.eth56g.onestep_ena; 2080 peer_delay = hw->ptp.phy.eth56g.peer_delay; 2081 sfd_ena = hw->ptp.phy.eth56g.sfd_ena; 2082 2083 addr = PHY_PTP_1STEP_CONFIG; 2084 err = ice_read_quad_ptp_reg_eth56g(hw, port, addr, &val); 2085 if (err) 2086 return err; 2087 2088 if (enable) 2089 val |= BIT(quad_lane); 2090 else 2091 val &= ~BIT(quad_lane); 2092 2093 val &= ~(PHY_PTP_1STEP_T1S_UP64_M | PHY_PTP_1STEP_T1S_DELTA_M); 2094 2095 err = ice_write_quad_ptp_reg_eth56g(hw, port, addr, val); 2096 if (err) 2097 return err; 2098 2099 addr = PHY_PTP_1STEP_PEER_DELAY(quad_lane); 2100 val = FIELD_PREP(PHY_PTP_1STEP_PD_DELAY_M, peer_delay); 2101 if (peer_delay) 2102 val |= PHY_PTP_1STEP_PD_ADD_PD_M; 2103 val |= PHY_PTP_1STEP_PD_DLY_V_M; 2104 err = ice_write_quad_ptp_reg_eth56g(hw, port, addr, val); 2105 if (err) 2106 return err; 2107 2108 val &= ~PHY_PTP_1STEP_PD_DLY_V_M; 2109 err = ice_write_quad_ptp_reg_eth56g(hw, port, addr, val); 2110 if (err) 2111 return err; 2112 2113 addr = PHY_MAC_XIF_MODE; 2114 err = ice_read_mac_reg_eth56g(hw, port, addr, &val); 2115 if (err) 2116 return err; 2117 2118 val &= ~(PHY_MAC_XIF_1STEP_ENA_M | PHY_MAC_XIF_TS_BIN_MODE_M | 2119 PHY_MAC_XIF_TS_SFD_ENA_M | PHY_MAC_XIF_GMII_TS_SEL_M); 2120 2121 switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) { 2122 case ICE_ETH56G_LNK_SPD_1G: 2123 case ICE_ETH56G_LNK_SPD_2_5G: 2124 val |= PHY_MAC_XIF_GMII_TS_SEL_M; 2125 break; 2126 default: 2127 break; 2128 } 2129 2130 val |= FIELD_PREP(PHY_MAC_XIF_1STEP_ENA_M, enable) | 2131 FIELD_PREP(PHY_MAC_XIF_TS_BIN_MODE_M, enable) | 2132 FIELD_PREP(PHY_MAC_XIF_TS_SFD_ENA_M, sfd_ena); 2133 2134 return ice_write_mac_reg_eth56g(hw, port, addr, val); 2135 } 2136 2137 /** 2138 * mul_u32_u32_fx_q9 - Multiply two u32 fixed point Q9 values 2139 * @a: multiplier value 2140 * @b: multiplicand value 2141 * 2142 * Return: result of multiplication 2143 */ 2144 static u32 mul_u32_u32_fx_q9(u32 a, u32 b) 2145 { 2146 return (u32)(((u64)a * b) >> ICE_ETH56G_MAC_CFG_FRAC_W); 2147 } 2148 2149 /** 2150 * add_u32_u32_fx - Add two u32 fixed point values and discard overflow 2151 * @a: first value 2152 * @b: second value 2153 * 2154 * Return: result of addition 2155 */ 2156 static u32 add_u32_u32_fx(u32 a, u32 b) 2157 { 2158 return lower_32_bits(((u64)a + b)); 2159 } 2160 2161 /** 2162 * ice_ptp_calc_bitslip_eth56g - Calculate bitslip value 2163 * @hw: pointer to the HW struct 2164 * @port: port to configure 2165 * @bs: bitslip multiplier 2166 * @fc: FC-FEC enabled 2167 * @rs: RS-FEC enabled 2168 * @spd: link speed 2169 * 2170 * Return: calculated bitslip value 2171 */ 2172 static u32 ice_ptp_calc_bitslip_eth56g(struct ice_hw *hw, u8 port, u32 bs, 2173 bool fc, bool rs, 2174 enum ice_eth56g_link_spd spd) 2175 { 2176 u32 bitslip; 2177 int err; 2178 2179 if (!bs || rs) 2180 return 0; 2181 2182 if (spd == ICE_ETH56G_LNK_SPD_1G || spd == ICE_ETH56G_LNK_SPD_2_5G) { 2183 err = ice_read_gpcs_reg_eth56g(hw, port, PHY_GPCS_BITSLIP, 2184 &bitslip); 2185 } else { 2186 u8 quad_lane = port % ICE_PORTS_PER_QUAD; 2187 u32 addr; 2188 2189 addr = PHY_REG_SD_BIT_SLIP(quad_lane); 2190 err = ice_read_quad_ptp_reg_eth56g(hw, port, addr, &bitslip); 2191 } 2192 if (err) 2193 return 0; 2194 2195 if (spd == ICE_ETH56G_LNK_SPD_1G && !bitslip) { 2196 /* Bitslip register value of 0 corresponds to 10 so substitute 2197 * it for calculations 2198 */ 2199 bitslip = 10; 2200 } else if (spd == ICE_ETH56G_LNK_SPD_10G || 2201 spd == ICE_ETH56G_LNK_SPD_25G) { 2202 if (fc) 2203 bitslip = bitslip * 2 + 32; 2204 else 2205 bitslip = (u32)((s32)bitslip * -1 + 20); 2206 } 2207 2208 bitslip <<= ICE_ETH56G_MAC_CFG_FRAC_W; 2209 return mul_u32_u32_fx_q9(bitslip, bs); 2210 } 2211 2212 /** 2213 * ice_ptp_calc_deskew_eth56g - Calculate deskew value 2214 * @hw: pointer to the HW struct 2215 * @port: port to configure 2216 * @ds: deskew multiplier 2217 * @rs: RS-FEC enabled 2218 * @spd: link speed 2219 * 2220 * Return: calculated deskew value 2221 */ 2222 static u32 ice_ptp_calc_deskew_eth56g(struct ice_hw *hw, u8 port, u32 ds, 2223 bool rs, enum ice_eth56g_link_spd spd) 2224 { 2225 u32 deskew_i, deskew_f; 2226 int err; 2227 2228 if (!ds) 2229 return 0; 2230 2231 read_poll_timeout(ice_read_ptp_reg_eth56g, err, 2232 FIELD_GET(PHY_REG_DESKEW_0_VALID, deskew_i), 500, 2233 50 * USEC_PER_MSEC, false, hw, port, PHY_REG_DESKEW_0, 2234 &deskew_i); 2235 if (err) 2236 return err; 2237 2238 deskew_f = FIELD_GET(PHY_REG_DESKEW_0_RLEVEL_FRAC, deskew_i); 2239 deskew_i = FIELD_GET(PHY_REG_DESKEW_0_RLEVEL, deskew_i); 2240 2241 if (rs && spd == ICE_ETH56G_LNK_SPD_50G2) 2242 ds = 0x633; /* 3.1 */ 2243 else if (rs && spd == ICE_ETH56G_LNK_SPD_100G) 2244 ds = 0x31b; /* 1.552 */ 2245 2246 deskew_i = FIELD_PREP(ICE_ETH56G_MAC_CFG_RX_OFFSET_INT, deskew_i); 2247 /* Shift 3 fractional bits to the end of the integer part */ 2248 deskew_f <<= ICE_ETH56G_MAC_CFG_FRAC_W - PHY_REG_DESKEW_0_RLEVEL_FRAC_W; 2249 return mul_u32_u32_fx_q9(deskew_i | deskew_f, ds); 2250 } 2251 2252 /** 2253 * ice_phy_set_offsets_eth56g - Set Tx/Rx offset values 2254 * @hw: pointer to the HW struct 2255 * @port: port to configure 2256 * @spd: link speed 2257 * @cfg: structure to store output values 2258 * @fc: FC-FEC enabled 2259 * @rs: RS-FEC enabled 2260 * 2261 * Return: 2262 * * %0 - success 2263 * * %other - failed to write to PHY 2264 */ 2265 static int ice_phy_set_offsets_eth56g(struct ice_hw *hw, u8 port, 2266 enum ice_eth56g_link_spd spd, 2267 const struct ice_eth56g_mac_reg_cfg *cfg, 2268 bool fc, bool rs) 2269 { 2270 u32 rx_offset, tx_offset, bs_ds; 2271 bool onestep, sfd; 2272 2273 onestep = hw->ptp.phy.eth56g.onestep_ena; 2274 sfd = hw->ptp.phy.eth56g.sfd_ena; 2275 bs_ds = cfg->rx_offset.bs_ds; 2276 2277 if (fc) 2278 rx_offset = cfg->rx_offset.fc; 2279 else if (rs) 2280 rx_offset = cfg->rx_offset.rs; 2281 else 2282 rx_offset = cfg->rx_offset.no_fec; 2283 2284 rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.serdes); 2285 if (sfd) 2286 rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.sfd); 2287 2288 if (spd < ICE_ETH56G_LNK_SPD_40G) 2289 bs_ds = ice_ptp_calc_bitslip_eth56g(hw, port, bs_ds, fc, rs, 2290 spd); 2291 else 2292 bs_ds = ice_ptp_calc_deskew_eth56g(hw, port, bs_ds, rs, spd); 2293 rx_offset = add_u32_u32_fx(rx_offset, bs_ds); 2294 rx_offset &= ICE_ETH56G_MAC_CFG_RX_OFFSET_INT | 2295 ICE_ETH56G_MAC_CFG_RX_OFFSET_FRAC; 2296 2297 if (fc) 2298 tx_offset = cfg->tx_offset.fc; 2299 else if (rs) 2300 tx_offset = cfg->tx_offset.rs; 2301 else 2302 tx_offset = cfg->tx_offset.no_fec; 2303 tx_offset += cfg->tx_offset.serdes + cfg->tx_offset.sfd * sfd + 2304 cfg->tx_offset.onestep * onestep; 2305 2306 ice_write_mac_reg_eth56g(hw, port, PHY_MAC_RX_OFFSET, rx_offset); 2307 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TX_OFFSET, tx_offset); 2308 } 2309 2310 /** 2311 * ice_phy_cfg_mac_eth56g - Configure MAC for PTP 2312 * @hw: Pointer to the HW struct 2313 * @port: Port to configure 2314 * 2315 * Return: 2316 * * %0 - success 2317 * * %other - failed to write to PHY 2318 */ 2319 static int ice_phy_cfg_mac_eth56g(struct ice_hw *hw, u8 port) 2320 { 2321 const struct ice_eth56g_mac_reg_cfg *cfg; 2322 enum ice_eth56g_link_spd spd; 2323 struct ice_link_status *li; 2324 bool fc = false; 2325 bool rs = false; 2326 bool onestep; 2327 u32 val; 2328 int err; 2329 2330 onestep = hw->ptp.phy.eth56g.onestep_ena; 2331 li = &hw->port_info->phy.link_info; 2332 spd = ice_phy_get_speed_eth56g(li); 2333 if (!!(li->an_info & ICE_AQ_FEC_EN)) { 2334 if (spd == ICE_ETH56G_LNK_SPD_10G) { 2335 fc = true; 2336 } else { 2337 fc = !!(li->fec_info & ICE_AQ_LINK_25G_KR_FEC_EN); 2338 rs = !!(li->fec_info & ~ICE_AQ_LINK_25G_KR_FEC_EN); 2339 } 2340 } 2341 cfg = ð56g_mac_cfg[spd]; 2342 2343 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_RX_MODULO, 0); 2344 if (err) 2345 return err; 2346 2347 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TX_MODULO, 0); 2348 if (err) 2349 return err; 2350 2351 val = FIELD_PREP(PHY_MAC_TSU_CFG_TX_MODE_M, 2352 cfg->tx_mode.def + rs * cfg->tx_mode.rs) | 2353 FIELD_PREP(PHY_MAC_TSU_CFG_TX_MII_MK_DLY_M, cfg->tx_mk_dly) | 2354 FIELD_PREP(PHY_MAC_TSU_CFG_TX_MII_CW_DLY_M, 2355 cfg->tx_cw_dly.def + 2356 onestep * cfg->tx_cw_dly.onestep) | 2357 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MODE_M, 2358 cfg->rx_mode.def + rs * cfg->rx_mode.rs) | 2359 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MII_MK_DLY_M, 2360 cfg->rx_mk_dly.def + rs * cfg->rx_mk_dly.rs) | 2361 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MII_CW_DLY_M, 2362 cfg->rx_cw_dly.def + rs * cfg->rx_cw_dly.rs) | 2363 FIELD_PREP(PHY_MAC_TSU_CFG_BLKS_PER_CLK_M, cfg->blks_per_clk); 2364 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TSU_CONFIG, val); 2365 if (err) 2366 return err; 2367 2368 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_BLOCKTIME, 2369 cfg->blktime); 2370 if (err) 2371 return err; 2372 2373 err = ice_phy_set_offsets_eth56g(hw, port, spd, cfg, fc, rs); 2374 if (err) 2375 return err; 2376 2377 if (spd == ICE_ETH56G_LNK_SPD_25G && !rs) 2378 val = 0; 2379 else 2380 val = cfg->mktime; 2381 2382 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_MARKERTIME, val); 2383 } 2384 2385 /** 2386 * ice_phy_cfg_intr_eth56g - Configure TX timestamp interrupt 2387 * @hw: pointer to the HW struct 2388 * @port: the timestamp port 2389 * @ena: enable or disable interrupt 2390 * @threshold: interrupt threshold 2391 * 2392 * Configure TX timestamp interrupt for the specified port 2393 * 2394 * Return: 2395 * * %0 - success 2396 * * %other - PHY read/write failed 2397 */ 2398 int ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold) 2399 { 2400 int err; 2401 u32 val; 2402 2403 err = ice_read_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, &val); 2404 if (err) 2405 return err; 2406 2407 if (ena) { 2408 val |= PHY_TS_INT_CONFIG_ENA_M; 2409 val &= ~PHY_TS_INT_CONFIG_THRESHOLD_M; 2410 val |= FIELD_PREP(PHY_TS_INT_CONFIG_THRESHOLD_M, threshold); 2411 } else { 2412 val &= ~PHY_TS_INT_CONFIG_ENA_M; 2413 } 2414 2415 return ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, val); 2416 } 2417 2418 /** 2419 * ice_read_phy_and_phc_time_eth56g - Simultaneously capture PHC and PHY time 2420 * @hw: pointer to the HW struct 2421 * @port: the PHY port to read 2422 * @phy_time: on return, the 64bit PHY timer value 2423 * @phc_time: on return, the lower 64bits of PHC time 2424 * 2425 * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY 2426 * and PHC timer values. 2427 * 2428 * Return: 2429 * * %0 - success 2430 * * %other - PHY read/write failed 2431 */ 2432 static int ice_read_phy_and_phc_time_eth56g(struct ice_hw *hw, u8 port, 2433 u64 *phy_time, u64 *phc_time) 2434 { 2435 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 2436 u64 tx_time, rx_time; 2437 u32 zo, lo; 2438 u8 tmr_idx; 2439 int err; 2440 2441 tmr_idx = ice_get_ptp_src_clock_index(hw); 2442 2443 /* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */ 2444 ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME); 2445 2446 /* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */ 2447 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME); 2448 if (err) 2449 return err; 2450 2451 /* Issue the sync to start the ICE_PTP_READ_TIME capture */ 2452 ice_ptp_exec_tmr_cmd(hw); 2453 2454 /* Read the captured PHC time from the shadow time registers */ 2455 if (ice_is_primary(hw)) { 2456 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx)); 2457 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx)); 2458 } else { 2459 zo = rd32(ice_get_primary_hw(pf), GLTSYN_SHTIME_0(tmr_idx)); 2460 lo = rd32(ice_get_primary_hw(pf), GLTSYN_SHTIME_L(tmr_idx)); 2461 } 2462 *phc_time = (u64)lo << 32 | zo; 2463 2464 /* Read the captured PHY time from the PHY shadow registers */ 2465 err = ice_ptp_read_port_capture_eth56g(hw, port, &tx_time, &rx_time); 2466 if (err) 2467 return err; 2468 2469 /* If the PHY Tx and Rx timers don't match, log a warning message. 2470 * Note that this should not happen in normal circumstances since the 2471 * driver always programs them together. 2472 */ 2473 if (tx_time != rx_time) 2474 dev_warn(ice_hw_to_dev(hw), "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n", 2475 port, tx_time, rx_time); 2476 2477 *phy_time = tx_time; 2478 2479 return 0; 2480 } 2481 2482 /** 2483 * ice_sync_phy_timer_eth56g - Synchronize the PHY timer with PHC timer 2484 * @hw: pointer to the HW struct 2485 * @port: the PHY port to synchronize 2486 * 2487 * Perform an adjustment to ensure that the PHY and PHC timers are in sync. 2488 * This is done by issuing a ICE_PTP_READ_TIME command which triggers a 2489 * simultaneous read of the PHY timer and PHC timer. Then we use the 2490 * difference to calculate an appropriate 2s complement addition to add 2491 * to the PHY timer in order to ensure it reads the same value as the 2492 * primary PHC timer. 2493 * 2494 * Return: 2495 * * %0 - success 2496 * * %-EBUSY- failed to acquire PTP semaphore 2497 * * %other - PHY read/write failed 2498 */ 2499 static int ice_sync_phy_timer_eth56g(struct ice_hw *hw, u8 port) 2500 { 2501 u64 phc_time, phy_time, difference; 2502 int err; 2503 2504 if (!ice_ptp_lock(hw)) { 2505 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n"); 2506 return -EBUSY; 2507 } 2508 2509 err = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time, &phc_time); 2510 if (err) 2511 goto err_unlock; 2512 2513 /* Calculate the amount required to add to the port time in order for 2514 * it to match the PHC time. 2515 * 2516 * Note that the port adjustment is done using 2s complement 2517 * arithmetic. This is convenient since it means that we can simply 2518 * calculate the difference between the PHC time and the port time, 2519 * and it will be interpreted correctly. 2520 */ 2521 2522 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 2523 difference = phc_time - phy_time; 2524 2525 err = ice_ptp_prep_port_adj_eth56g(hw, port, (s64)difference); 2526 if (err) 2527 goto err_unlock; 2528 2529 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME); 2530 if (err) 2531 goto err_unlock; 2532 2533 /* Issue the sync to activate the time adjustment */ 2534 ice_ptp_exec_tmr_cmd(hw); 2535 2536 /* Re-capture the timer values to flush the command registers and 2537 * verify that the time was properly adjusted. 2538 */ 2539 err = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time, &phc_time); 2540 if (err) 2541 goto err_unlock; 2542 2543 dev_info(ice_hw_to_dev(hw), 2544 "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n", 2545 port, phy_time, phc_time); 2546 2547 err_unlock: 2548 ice_ptp_unlock(hw); 2549 return err; 2550 } 2551 2552 /** 2553 * ice_stop_phy_timer_eth56g - Stop the PHY clock timer 2554 * @hw: pointer to the HW struct 2555 * @port: the PHY port to stop 2556 * @soft_reset: if true, hold the SOFT_RESET bit of PHY_REG_PS 2557 * 2558 * Stop the clock of a PHY port. This must be done as part of the flow to 2559 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 2560 * initialized or when link speed changes. 2561 * 2562 * Return: 2563 * * %0 - success 2564 * * %other - failed to write to PHY 2565 */ 2566 int ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset) 2567 { 2568 int err; 2569 2570 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 0); 2571 if (err) 2572 return err; 2573 2574 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 0); 2575 if (err) 2576 return err; 2577 2578 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port); 2579 2580 return 0; 2581 } 2582 2583 /** 2584 * ice_start_phy_timer_eth56g - Start the PHY clock timer 2585 * @hw: pointer to the HW struct 2586 * @port: the PHY port to start 2587 * 2588 * Start the clock of a PHY port. This must be done as part of the flow to 2589 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 2590 * initialized or when link speed changes. 2591 * 2592 * Return: 2593 * * %0 - success 2594 * * %other - PHY read/write failed 2595 */ 2596 int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port) 2597 { 2598 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 2599 u32 lo, hi; 2600 u64 incval; 2601 u8 tmr_idx; 2602 int err; 2603 2604 tmr_idx = ice_get_ptp_src_clock_index(hw); 2605 2606 err = ice_stop_phy_timer_eth56g(hw, port, false); 2607 if (err) 2608 return err; 2609 2610 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 2611 2612 err = ice_phy_cfg_parpcs_eth56g(hw, port); 2613 if (err) 2614 return err; 2615 2616 err = ice_phy_cfg_ptp_1step_eth56g(hw, port); 2617 if (err) 2618 return err; 2619 2620 err = ice_phy_cfg_mac_eth56g(hw, port); 2621 if (err) 2622 return err; 2623 2624 if (ice_is_primary(hw)) { 2625 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 2626 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 2627 } else { 2628 lo = rd32(ice_get_primary_hw(pf), GLTSYN_INCVAL_L(tmr_idx)); 2629 hi = rd32(ice_get_primary_hw(pf), GLTSYN_INCVAL_H(tmr_idx)); 2630 } 2631 incval = (u64)hi << 32 | lo; 2632 2633 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_REG_TIMETUS_L, incval); 2634 if (err) 2635 return err; 2636 2637 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL); 2638 if (err) 2639 return err; 2640 2641 ice_ptp_exec_tmr_cmd(hw); 2642 2643 err = ice_sync_phy_timer_eth56g(hw, port); 2644 if (err) 2645 return err; 2646 2647 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 1); 2648 if (err) 2649 return err; 2650 2651 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 1); 2652 if (err) 2653 return err; 2654 2655 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port); 2656 2657 return 0; 2658 } 2659 2660 /** 2661 * ice_ptp_init_phc_e825 - Perform E825 specific PHC initialization 2662 * @hw: pointer to HW struct 2663 * 2664 * Perform E825-specific PTP hardware clock initialization steps. 2665 * 2666 * Return: 0 on success, negative error code otherwise. 2667 */ 2668 static int ice_ptp_init_phc_e825(struct ice_hw *hw) 2669 { 2670 /* Initialize the Clock Generation Unit */ 2671 return ice_init_cgu_e82x(hw); 2672 } 2673 2674 /** 2675 * ice_ptp_read_tx_hwtstamp_status_eth56g - Get TX timestamp status 2676 * @hw: pointer to the HW struct 2677 * @ts_status: the timestamp mask pointer 2678 * 2679 * Read the PHY Tx timestamp status mask indicating which ports have Tx 2680 * timestamps available. 2681 * 2682 * Return: 2683 * * %0 - success 2684 * * %other - failed to read from PHY 2685 */ 2686 int ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status) 2687 { 2688 const struct ice_eth56g_params *params = &hw->ptp.phy.eth56g; 2689 u8 phy, mask; 2690 u32 status; 2691 2692 mask = (1 << hw->ptp.ports_per_phy) - 1; 2693 *ts_status = 0; 2694 2695 for (phy = 0; phy < params->num_phys; phy++) { 2696 int err; 2697 2698 err = ice_read_phy_eth56g(hw, phy, PHY_PTP_INT_STATUS, &status); 2699 if (err) 2700 return err; 2701 2702 *ts_status |= (status & mask) << (phy * hw->ptp.ports_per_phy); 2703 } 2704 2705 ice_debug(hw, ICE_DBG_PTP, "PHY interrupt err: %x\n", *ts_status); 2706 2707 return 0; 2708 } 2709 2710 /** 2711 * ice_get_phy_tx_tstamp_ready_eth56g - Read the Tx memory status register 2712 * @hw: pointer to the HW struct 2713 * @port: the PHY port to read from 2714 * @tstamp_ready: contents of the Tx memory status register 2715 * 2716 * Read the PHY_REG_TX_MEMORY_STATUS register indicating which timestamps in 2717 * the PHY are ready. A set bit means the corresponding timestamp is valid and 2718 * ready to be captured from the PHY timestamp block. 2719 * 2720 * Return: 2721 * * %0 - success 2722 * * %other - failed to read from PHY 2723 */ 2724 static int ice_get_phy_tx_tstamp_ready_eth56g(struct ice_hw *hw, u8 port, 2725 u64 *tstamp_ready) 2726 { 2727 int err; 2728 2729 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L, 2730 tstamp_ready); 2731 if (err) { 2732 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS for port %u, err %d\n", 2733 port, err); 2734 return err; 2735 } 2736 2737 return 0; 2738 } 2739 2740 /** 2741 * ice_ptp_init_phy_e825 - initialize PHY parameters 2742 * @hw: pointer to the HW struct 2743 */ 2744 static void ice_ptp_init_phy_e825(struct ice_hw *hw) 2745 { 2746 struct ice_ptp_hw *ptp = &hw->ptp; 2747 struct ice_eth56g_params *params; 2748 2749 params = &ptp->phy.eth56g; 2750 params->onestep_ena = false; 2751 params->peer_delay = 0; 2752 params->sfd_ena = false; 2753 params->num_phys = 2; 2754 ptp->ports_per_phy = 4; 2755 ptp->num_lports = params->num_phys * ptp->ports_per_phy; 2756 } 2757 2758 /* E822 family functions 2759 * 2760 * The following functions operate on the E822 family of devices. 2761 */ 2762 2763 /** 2764 * ice_fill_phy_msg_e82x - Fill message data for a PHY register access 2765 * @hw: pointer to the HW struct 2766 * @msg: the PHY message buffer to fill in 2767 * @port: the port to access 2768 * @offset: the register offset 2769 */ 2770 static void ice_fill_phy_msg_e82x(struct ice_hw *hw, 2771 struct ice_sbq_msg_input *msg, u8 port, 2772 u16 offset) 2773 { 2774 int phy_port, quadtype; 2775 2776 phy_port = port % hw->ptp.ports_per_phy; 2777 quadtype = ICE_GET_QUAD_NUM(port) % 2778 ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy); 2779 2780 if (quadtype == 0) { 2781 msg->msg_addr_low = P_Q0_L(P_0_BASE + offset, phy_port); 2782 msg->msg_addr_high = P_Q0_H(P_0_BASE + offset, phy_port); 2783 } else { 2784 msg->msg_addr_low = P_Q1_L(P_4_BASE + offset, phy_port); 2785 msg->msg_addr_high = P_Q1_H(P_4_BASE + offset, phy_port); 2786 } 2787 2788 msg->dest_dev = ice_sbq_dev_phy_0; 2789 } 2790 2791 /** 2792 * ice_is_64b_phy_reg_e82x - Check if this is a 64bit PHY register 2793 * @low_addr: the low address to check 2794 * @high_addr: on return, contains the high address of the 64bit register 2795 * 2796 * Checks if the provided low address is one of the known 64bit PHY values 2797 * represented as two 32bit registers. If it is, return the appropriate high 2798 * register offset to use. 2799 */ 2800 static bool ice_is_64b_phy_reg_e82x(u16 low_addr, u16 *high_addr) 2801 { 2802 switch (low_addr) { 2803 case P_REG_PAR_PCS_TX_OFFSET_L: 2804 *high_addr = P_REG_PAR_PCS_TX_OFFSET_U; 2805 return true; 2806 case P_REG_PAR_PCS_RX_OFFSET_L: 2807 *high_addr = P_REG_PAR_PCS_RX_OFFSET_U; 2808 return true; 2809 case P_REG_PAR_TX_TIME_L: 2810 *high_addr = P_REG_PAR_TX_TIME_U; 2811 return true; 2812 case P_REG_PAR_RX_TIME_L: 2813 *high_addr = P_REG_PAR_RX_TIME_U; 2814 return true; 2815 case P_REG_TOTAL_TX_OFFSET_L: 2816 *high_addr = P_REG_TOTAL_TX_OFFSET_U; 2817 return true; 2818 case P_REG_TOTAL_RX_OFFSET_L: 2819 *high_addr = P_REG_TOTAL_RX_OFFSET_U; 2820 return true; 2821 case P_REG_UIX66_10G_40G_L: 2822 *high_addr = P_REG_UIX66_10G_40G_U; 2823 return true; 2824 case P_REG_UIX66_25G_100G_L: 2825 *high_addr = P_REG_UIX66_25G_100G_U; 2826 return true; 2827 case P_REG_TX_CAPTURE_L: 2828 *high_addr = P_REG_TX_CAPTURE_U; 2829 return true; 2830 case P_REG_RX_CAPTURE_L: 2831 *high_addr = P_REG_RX_CAPTURE_U; 2832 return true; 2833 case P_REG_TX_TIMER_INC_PRE_L: 2834 *high_addr = P_REG_TX_TIMER_INC_PRE_U; 2835 return true; 2836 case P_REG_RX_TIMER_INC_PRE_L: 2837 *high_addr = P_REG_RX_TIMER_INC_PRE_U; 2838 return true; 2839 default: 2840 return false; 2841 } 2842 } 2843 2844 /** 2845 * ice_is_40b_phy_reg_e82x - Check if this is a 40bit PHY register 2846 * @low_addr: the low address to check 2847 * @high_addr: on return, contains the high address of the 40bit value 2848 * 2849 * Checks if the provided low address is one of the known 40bit PHY values 2850 * split into two registers with the lower 8 bits in the low register and the 2851 * upper 32 bits in the high register. If it is, return the appropriate high 2852 * register offset to use. 2853 */ 2854 static bool ice_is_40b_phy_reg_e82x(u16 low_addr, u16 *high_addr) 2855 { 2856 switch (low_addr) { 2857 case P_REG_TIMETUS_L: 2858 *high_addr = P_REG_TIMETUS_U; 2859 return true; 2860 case P_REG_PAR_RX_TUS_L: 2861 *high_addr = P_REG_PAR_RX_TUS_U; 2862 return true; 2863 case P_REG_PAR_TX_TUS_L: 2864 *high_addr = P_REG_PAR_TX_TUS_U; 2865 return true; 2866 case P_REG_PCS_RX_TUS_L: 2867 *high_addr = P_REG_PCS_RX_TUS_U; 2868 return true; 2869 case P_REG_PCS_TX_TUS_L: 2870 *high_addr = P_REG_PCS_TX_TUS_U; 2871 return true; 2872 case P_REG_DESK_PAR_RX_TUS_L: 2873 *high_addr = P_REG_DESK_PAR_RX_TUS_U; 2874 return true; 2875 case P_REG_DESK_PAR_TX_TUS_L: 2876 *high_addr = P_REG_DESK_PAR_TX_TUS_U; 2877 return true; 2878 case P_REG_DESK_PCS_RX_TUS_L: 2879 *high_addr = P_REG_DESK_PCS_RX_TUS_U; 2880 return true; 2881 case P_REG_DESK_PCS_TX_TUS_L: 2882 *high_addr = P_REG_DESK_PCS_TX_TUS_U; 2883 return true; 2884 default: 2885 return false; 2886 } 2887 } 2888 2889 /** 2890 * ice_read_phy_reg_e82x - Read a PHY register 2891 * @hw: pointer to the HW struct 2892 * @port: PHY port to read from 2893 * @offset: PHY register offset to read 2894 * @val: on return, the contents read from the PHY 2895 * 2896 * Read a PHY register for the given port over the device sideband queue. 2897 */ 2898 static int 2899 ice_read_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 *val) 2900 { 2901 struct ice_sbq_msg_input msg = {0}; 2902 int err; 2903 2904 ice_fill_phy_msg_e82x(hw, &msg, port, offset); 2905 msg.opcode = ice_sbq_msg_rd; 2906 2907 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 2908 if (err) { 2909 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2910 err); 2911 return err; 2912 } 2913 2914 *val = msg.data; 2915 2916 return 0; 2917 } 2918 2919 /** 2920 * ice_read_64b_phy_reg_e82x - Read a 64bit value from PHY registers 2921 * @hw: pointer to the HW struct 2922 * @port: PHY port to read from 2923 * @low_addr: offset of the lower register to read from 2924 * @val: on return, the contents of the 64bit value from the PHY registers 2925 * 2926 * Reads the two registers associated with a 64bit value and returns it in the 2927 * val pointer. The offset always specifies the lower register offset to use. 2928 * The high offset is looked up. This function only operates on registers 2929 * known to be two parts of a 64bit value. 2930 */ 2931 static int 2932 ice_read_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val) 2933 { 2934 u32 low, high; 2935 u16 high_addr; 2936 int err; 2937 2938 /* Only operate on registers known to be split into two 32bit 2939 * registers. 2940 */ 2941 if (!ice_is_64b_phy_reg_e82x(low_addr, &high_addr)) { 2942 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n", 2943 low_addr); 2944 return -EINVAL; 2945 } 2946 2947 err = ice_read_phy_reg_e82x(hw, port, low_addr, &low); 2948 if (err) { 2949 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, err %d", 2950 low_addr, err); 2951 return err; 2952 } 2953 2954 err = ice_read_phy_reg_e82x(hw, port, high_addr, &high); 2955 if (err) { 2956 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, err %d", 2957 high_addr, err); 2958 return err; 2959 } 2960 2961 *val = (u64)high << 32 | low; 2962 2963 return 0; 2964 } 2965 2966 /** 2967 * ice_write_phy_reg_e82x - Write a PHY register 2968 * @hw: pointer to the HW struct 2969 * @port: PHY port to write to 2970 * @offset: PHY register offset to write 2971 * @val: The value to write to the register 2972 * 2973 * Write a PHY register for the given port over the device sideband queue. 2974 */ 2975 static int 2976 ice_write_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 val) 2977 { 2978 struct ice_sbq_msg_input msg = {0}; 2979 int err; 2980 2981 ice_fill_phy_msg_e82x(hw, &msg, port, offset); 2982 msg.opcode = ice_sbq_msg_wr; 2983 msg.data = val; 2984 2985 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 2986 if (err) { 2987 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2988 err); 2989 return err; 2990 } 2991 2992 return 0; 2993 } 2994 2995 /** 2996 * ice_write_40b_phy_reg_e82x - Write a 40b value to the PHY 2997 * @hw: pointer to the HW struct 2998 * @port: port to write to 2999 * @low_addr: offset of the low register 3000 * @val: 40b value to write 3001 * 3002 * Write the provided 40b value to the two associated registers by splitting 3003 * it up into two chunks, the lower 8 bits and the upper 32 bits. 3004 */ 3005 static int 3006 ice_write_40b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) 3007 { 3008 u32 low, high; 3009 u16 high_addr; 3010 int err; 3011 3012 /* Only operate on registers known to be split into a lower 8 bit 3013 * register and an upper 32 bit register. 3014 */ 3015 if (!ice_is_40b_phy_reg_e82x(low_addr, &high_addr)) { 3016 ice_debug(hw, ICE_DBG_PTP, "Invalid 40b register addr 0x%08x\n", 3017 low_addr); 3018 return -EINVAL; 3019 } 3020 low = FIELD_GET(P_REG_40B_LOW_M, val); 3021 high = (u32)(val >> P_REG_40B_HIGH_S); 3022 3023 err = ice_write_phy_reg_e82x(hw, port, low_addr, low); 3024 if (err) { 3025 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 3026 low_addr, err); 3027 return err; 3028 } 3029 3030 err = ice_write_phy_reg_e82x(hw, port, high_addr, high); 3031 if (err) { 3032 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 3033 high_addr, err); 3034 return err; 3035 } 3036 3037 return 0; 3038 } 3039 3040 /** 3041 * ice_write_64b_phy_reg_e82x - Write a 64bit value to PHY registers 3042 * @hw: pointer to the HW struct 3043 * @port: PHY port to read from 3044 * @low_addr: offset of the lower register to read from 3045 * @val: the contents of the 64bit value to write to PHY 3046 * 3047 * Write the 64bit value to the two associated 32bit PHY registers. The offset 3048 * is always specified as the lower register, and the high address is looked 3049 * up. This function only operates on registers known to be two parts of 3050 * a 64bit value. 3051 */ 3052 static int 3053 ice_write_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) 3054 { 3055 u32 low, high; 3056 u16 high_addr; 3057 int err; 3058 3059 /* Only operate on registers known to be split into two 32bit 3060 * registers. 3061 */ 3062 if (!ice_is_64b_phy_reg_e82x(low_addr, &high_addr)) { 3063 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n", 3064 low_addr); 3065 return -EINVAL; 3066 } 3067 3068 low = lower_32_bits(val); 3069 high = upper_32_bits(val); 3070 3071 err = ice_write_phy_reg_e82x(hw, port, low_addr, low); 3072 if (err) { 3073 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 3074 low_addr, err); 3075 return err; 3076 } 3077 3078 err = ice_write_phy_reg_e82x(hw, port, high_addr, high); 3079 if (err) { 3080 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 3081 high_addr, err); 3082 return err; 3083 } 3084 3085 return 0; 3086 } 3087 3088 /** 3089 * ice_fill_quad_msg_e82x - Fill message data for quad register access 3090 * @hw: pointer to the HW struct 3091 * @msg: the PHY message buffer to fill in 3092 * @quad: the quad to access 3093 * @offset: the register offset 3094 * 3095 * Fill a message buffer for accessing a register in a quad shared between 3096 * multiple PHYs. 3097 * 3098 * Return: 3099 * * %0 - OK 3100 * * %-EINVAL - invalid quad number 3101 */ 3102 static int ice_fill_quad_msg_e82x(struct ice_hw *hw, 3103 struct ice_sbq_msg_input *msg, u8 quad, 3104 u16 offset) 3105 { 3106 u32 addr; 3107 3108 if (quad >= ICE_GET_QUAD_NUM(hw->ptp.num_lports)) 3109 return -EINVAL; 3110 3111 msg->dest_dev = ice_sbq_dev_phy_0; 3112 3113 if (!(quad % ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy))) 3114 addr = Q_0_BASE + offset; 3115 else 3116 addr = Q_1_BASE + offset; 3117 3118 msg->msg_addr_low = lower_16_bits(addr); 3119 msg->msg_addr_high = upper_16_bits(addr); 3120 3121 return 0; 3122 } 3123 3124 /** 3125 * ice_read_quad_reg_e82x - Read a PHY quad register 3126 * @hw: pointer to the HW struct 3127 * @quad: quad to read from 3128 * @offset: quad register offset to read 3129 * @val: on return, the contents read from the quad 3130 * 3131 * Read a quad register over the device sideband queue. Quad registers are 3132 * shared between multiple PHYs. 3133 */ 3134 int 3135 ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val) 3136 { 3137 struct ice_sbq_msg_input msg = {0}; 3138 int err; 3139 3140 err = ice_fill_quad_msg_e82x(hw, &msg, quad, offset); 3141 if (err) 3142 return err; 3143 3144 msg.opcode = ice_sbq_msg_rd; 3145 3146 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 3147 if (err) { 3148 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 3149 err); 3150 return err; 3151 } 3152 3153 *val = msg.data; 3154 3155 return 0; 3156 } 3157 3158 /** 3159 * ice_write_quad_reg_e82x - Write a PHY quad register 3160 * @hw: pointer to the HW struct 3161 * @quad: quad to write to 3162 * @offset: quad register offset to write 3163 * @val: The value to write to the register 3164 * 3165 * Write a quad register over the device sideband queue. Quad registers are 3166 * shared between multiple PHYs. 3167 */ 3168 int 3169 ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val) 3170 { 3171 struct ice_sbq_msg_input msg = {0}; 3172 int err; 3173 3174 err = ice_fill_quad_msg_e82x(hw, &msg, quad, offset); 3175 if (err) 3176 return err; 3177 3178 msg.opcode = ice_sbq_msg_wr; 3179 msg.data = val; 3180 3181 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 3182 if (err) { 3183 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 3184 err); 3185 return err; 3186 } 3187 3188 return 0; 3189 } 3190 3191 /** 3192 * ice_read_phy_tstamp_e82x - Read a PHY timestamp out of the quad block 3193 * @hw: pointer to the HW struct 3194 * @quad: the quad to read from 3195 * @idx: the timestamp index to read 3196 * @tstamp: on return, the 40bit timestamp value 3197 * 3198 * Read a 40bit timestamp value out of the two associated registers in the 3199 * quad memory block that is shared between the internal PHYs of the E822 3200 * family of devices. 3201 */ 3202 static int 3203 ice_read_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp) 3204 { 3205 u16 lo_addr, hi_addr; 3206 u32 lo, hi; 3207 int err; 3208 3209 lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx); 3210 hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx); 3211 3212 err = ice_read_quad_reg_e82x(hw, quad, lo_addr, &lo); 3213 if (err) { 3214 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 3215 err); 3216 return err; 3217 } 3218 3219 err = ice_read_quad_reg_e82x(hw, quad, hi_addr, &hi); 3220 if (err) { 3221 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 3222 err); 3223 return err; 3224 } 3225 3226 /* For E822 based internal PHYs, the timestamp is reported with the 3227 * lower 8 bits in the low register, and the upper 32 bits in the high 3228 * register. 3229 */ 3230 *tstamp = FIELD_PREP(PHY_40B_HIGH_M, hi) | 3231 FIELD_PREP(PHY_40B_LOW_M, lo); 3232 3233 return 0; 3234 } 3235 3236 /** 3237 * ice_clear_phy_tstamp_e82x - Clear a timestamp from the quad block 3238 * @hw: pointer to the HW struct 3239 * @quad: the quad to read from 3240 * @idx: the timestamp index to reset 3241 * 3242 * Read the timestamp out of the quad to clear its timestamp status bit from 3243 * the PHY quad block that is shared between the internal PHYs of the E822 3244 * devices. 3245 * 3246 * Note that unlike E810, software cannot directly write to the quad memory 3247 * bank registers. E822 relies on the ice_get_phy_tx_tstamp_ready() function 3248 * to determine which timestamps are valid. Reading a timestamp auto-clears 3249 * the valid bit. 3250 * 3251 * To directly clear the contents of the timestamp block entirely, discarding 3252 * all timestamp data at once, software should instead use 3253 * ice_ptp_reset_ts_memory_quad_e82x(). 3254 * 3255 * This function should only be called on an idx whose bit is set according to 3256 * ice_get_phy_tx_tstamp_ready(). 3257 */ 3258 static int 3259 ice_clear_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx) 3260 { 3261 u64 unused_tstamp; 3262 int err; 3263 3264 err = ice_read_phy_tstamp_e82x(hw, quad, idx, &unused_tstamp); 3265 if (err) { 3266 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for quad %u, idx %u, err %d\n", 3267 quad, idx, err); 3268 return err; 3269 } 3270 3271 return 0; 3272 } 3273 3274 /** 3275 * ice_ptp_reset_ts_memory_quad_e82x - Clear all timestamps from the quad block 3276 * @hw: pointer to the HW struct 3277 * @quad: the quad to read from 3278 * 3279 * Clear all timestamps from the PHY quad block that is shared between the 3280 * internal PHYs on the E822 devices. 3281 */ 3282 void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad) 3283 { 3284 ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M); 3285 ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M); 3286 } 3287 3288 /** 3289 * ice_ptp_reset_ts_memory_e82x - Clear all timestamps from all quad blocks 3290 * @hw: pointer to the HW struct 3291 */ 3292 static void ice_ptp_reset_ts_memory_e82x(struct ice_hw *hw) 3293 { 3294 unsigned int quad; 3295 3296 for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports); quad++) 3297 ice_ptp_reset_ts_memory_quad_e82x(hw, quad); 3298 } 3299 3300 /** 3301 * ice_ptp_set_vernier_wl - Set the window length for vernier calibration 3302 * @hw: pointer to the HW struct 3303 * 3304 * Set the window length used for the vernier port calibration process. 3305 */ 3306 static int ice_ptp_set_vernier_wl(struct ice_hw *hw) 3307 { 3308 u8 port; 3309 3310 for (port = 0; port < hw->ptp.num_lports; port++) { 3311 int err; 3312 3313 err = ice_write_phy_reg_e82x(hw, port, P_REG_WL, 3314 PTP_VERNIER_WL); 3315 if (err) { 3316 ice_debug(hw, ICE_DBG_PTP, "Failed to set vernier window length for port %u, err %d\n", 3317 port, err); 3318 return err; 3319 } 3320 } 3321 3322 return 0; 3323 } 3324 3325 /** 3326 * ice_ptp_init_phc_e82x - Perform E822 specific PHC initialization 3327 * @hw: pointer to HW struct 3328 * 3329 * Perform PHC initialization steps specific to E822 devices. 3330 */ 3331 static int ice_ptp_init_phc_e82x(struct ice_hw *hw) 3332 { 3333 int err; 3334 u32 val; 3335 3336 /* Enable reading switch and PHY registers over the sideband queue */ 3337 #define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1) 3338 #define PF_SB_REM_DEV_CTL_PHY0 BIT(2) 3339 val = rd32(hw, PF_SB_REM_DEV_CTL); 3340 val |= (PF_SB_REM_DEV_CTL_SWITCH_READ | PF_SB_REM_DEV_CTL_PHY0); 3341 wr32(hw, PF_SB_REM_DEV_CTL, val); 3342 3343 /* Initialize the Clock Generation Unit */ 3344 err = ice_init_cgu_e82x(hw); 3345 if (err) 3346 return err; 3347 3348 /* Set window length for all the ports */ 3349 return ice_ptp_set_vernier_wl(hw); 3350 } 3351 3352 /** 3353 * ice_ptp_prep_phy_time_e82x - Prepare PHY port with initial time 3354 * @hw: pointer to the HW struct 3355 * @time: Time to initialize the PHY port clocks to 3356 * 3357 * Program the PHY port registers with a new initial time value. The port 3358 * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync 3359 * command. The time value is the upper 32 bits of the PHY timer, usually in 3360 * units of nominal nanoseconds. 3361 */ 3362 static int 3363 ice_ptp_prep_phy_time_e82x(struct ice_hw *hw, u32 time) 3364 { 3365 u64 phy_time; 3366 u8 port; 3367 int err; 3368 3369 /* The time represents the upper 32 bits of the PHY timer, so we need 3370 * to shift to account for this when programming. 3371 */ 3372 phy_time = (u64)time << 32; 3373 3374 for (port = 0; port < hw->ptp.num_lports; port++) { 3375 /* Tx case */ 3376 err = ice_write_64b_phy_reg_e82x(hw, port, 3377 P_REG_TX_TIMER_INC_PRE_L, 3378 phy_time); 3379 if (err) 3380 goto exit_err; 3381 3382 /* Rx case */ 3383 err = ice_write_64b_phy_reg_e82x(hw, port, 3384 P_REG_RX_TIMER_INC_PRE_L, 3385 phy_time); 3386 if (err) 3387 goto exit_err; 3388 } 3389 3390 return 0; 3391 3392 exit_err: 3393 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n", 3394 port, err); 3395 3396 return err; 3397 } 3398 3399 /** 3400 * ice_ptp_prep_port_adj_e82x - Prepare a single port for time adjust 3401 * @hw: pointer to HW struct 3402 * @port: Port number to be programmed 3403 * @time: time in cycles to adjust the port Tx and Rx clocks 3404 * 3405 * Program the port for an atomic adjustment by writing the Tx and Rx timer 3406 * registers. The atomic adjustment won't be completed until the driver issues 3407 * an ICE_PTP_ADJ_TIME command. 3408 * 3409 * Note that time is not in units of nanoseconds. It is in clock time 3410 * including the lower sub-nanosecond portion of the port timer. 3411 * 3412 * Negative adjustments are supported using 2s complement arithmetic. 3413 */ 3414 static int 3415 ice_ptp_prep_port_adj_e82x(struct ice_hw *hw, u8 port, s64 time) 3416 { 3417 u32 l_time, u_time; 3418 int err; 3419 3420 l_time = lower_32_bits(time); 3421 u_time = upper_32_bits(time); 3422 3423 /* Tx case */ 3424 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TIMER_INC_PRE_L, 3425 l_time); 3426 if (err) 3427 goto exit_err; 3428 3429 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TIMER_INC_PRE_U, 3430 u_time); 3431 if (err) 3432 goto exit_err; 3433 3434 /* Rx case */ 3435 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TIMER_INC_PRE_L, 3436 l_time); 3437 if (err) 3438 goto exit_err; 3439 3440 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TIMER_INC_PRE_U, 3441 u_time); 3442 if (err) 3443 goto exit_err; 3444 3445 return 0; 3446 3447 exit_err: 3448 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n", 3449 port, err); 3450 return err; 3451 } 3452 3453 /** 3454 * ice_ptp_prep_phy_adj_e82x - Prep PHY ports for a time adjustment 3455 * @hw: pointer to HW struct 3456 * @adj: adjustment in nanoseconds 3457 * 3458 * Prepare the PHY ports for an atomic time adjustment by programming the PHY 3459 * Tx and Rx port registers. The actual adjustment is completed by issuing an 3460 * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command. 3461 */ 3462 static int 3463 ice_ptp_prep_phy_adj_e82x(struct ice_hw *hw, s32 adj) 3464 { 3465 s64 cycles; 3466 u8 port; 3467 3468 /* The port clock supports adjustment of the sub-nanosecond portion of 3469 * the clock. We shift the provided adjustment in nanoseconds to 3470 * calculate the appropriate adjustment to program into the PHY ports. 3471 */ 3472 if (adj > 0) 3473 cycles = (s64)adj << 32; 3474 else 3475 cycles = -(((s64)-adj) << 32); 3476 3477 for (port = 0; port < hw->ptp.num_lports; port++) { 3478 int err; 3479 3480 err = ice_ptp_prep_port_adj_e82x(hw, port, cycles); 3481 if (err) 3482 return err; 3483 } 3484 3485 return 0; 3486 } 3487 3488 /** 3489 * ice_ptp_prep_phy_incval_e82x - Prepare PHY ports for time adjustment 3490 * @hw: pointer to HW struct 3491 * @incval: new increment value to prepare 3492 * 3493 * Prepare each of the PHY ports for a new increment value by programming the 3494 * port's TIMETUS registers. The new increment value will be updated after 3495 * issuing an ICE_PTP_INIT_INCVAL command. 3496 */ 3497 static int 3498 ice_ptp_prep_phy_incval_e82x(struct ice_hw *hw, u64 incval) 3499 { 3500 int err; 3501 u8 port; 3502 3503 for (port = 0; port < hw->ptp.num_lports; port++) { 3504 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L, 3505 incval); 3506 if (err) 3507 goto exit_err; 3508 } 3509 3510 return 0; 3511 3512 exit_err: 3513 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n", 3514 port, err); 3515 3516 return err; 3517 } 3518 3519 /** 3520 * ice_ptp_read_port_capture - Read a port's local time capture 3521 * @hw: pointer to HW struct 3522 * @port: Port number to read 3523 * @tx_ts: on return, the Tx port time capture 3524 * @rx_ts: on return, the Rx port time capture 3525 * 3526 * Read the port's Tx and Rx local time capture values. 3527 * 3528 * Note this has no equivalent for the E810 devices. 3529 */ 3530 static int 3531 ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts) 3532 { 3533 int err; 3534 3535 /* Tx case */ 3536 err = ice_read_64b_phy_reg_e82x(hw, port, P_REG_TX_CAPTURE_L, tx_ts); 3537 if (err) { 3538 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n", 3539 err); 3540 return err; 3541 } 3542 3543 ice_debug(hw, ICE_DBG_PTP, "tx_init = 0x%016llx\n", 3544 (unsigned long long)*tx_ts); 3545 3546 /* Rx case */ 3547 err = ice_read_64b_phy_reg_e82x(hw, port, P_REG_RX_CAPTURE_L, rx_ts); 3548 if (err) { 3549 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n", 3550 err); 3551 return err; 3552 } 3553 3554 ice_debug(hw, ICE_DBG_PTP, "rx_init = 0x%016llx\n", 3555 (unsigned long long)*rx_ts); 3556 3557 return 0; 3558 } 3559 3560 /** 3561 * ice_ptp_write_port_cmd_e82x - Prepare a single PHY port for a timer command 3562 * @hw: pointer to HW struct 3563 * @port: Port to which cmd has to be sent 3564 * @cmd: Command to be sent to the port 3565 * 3566 * Prepare the requested port for an upcoming timer sync command. 3567 * 3568 * Note there is no equivalent of this operation on E810, as that device 3569 * always handles all external PHYs internally. 3570 * 3571 * Return: 3572 * * %0 - success 3573 * * %other - failed to write to PHY 3574 */ 3575 static int ice_ptp_write_port_cmd_e82x(struct ice_hw *hw, u8 port, 3576 enum ice_ptp_tmr_cmd cmd) 3577 { 3578 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 3579 int err; 3580 3581 /* Tx case */ 3582 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TMR_CMD, val); 3583 if (err) { 3584 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n", 3585 err); 3586 return err; 3587 } 3588 3589 /* Rx case */ 3590 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TMR_CMD, 3591 val | TS_CMD_RX_TYPE); 3592 if (err) { 3593 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n", 3594 err); 3595 return err; 3596 } 3597 3598 return 0; 3599 } 3600 3601 /* E822 Vernier calibration functions 3602 * 3603 * The following functions are used as part of the vernier calibration of 3604 * a port. This calibration increases the precision of the timestamps on the 3605 * port. 3606 */ 3607 3608 /** 3609 * ice_phy_get_speed_and_fec_e82x - Get link speed and FEC based on serdes mode 3610 * @hw: pointer to HW struct 3611 * @port: the port to read from 3612 * @link_out: if non-NULL, holds link speed on success 3613 * @fec_out: if non-NULL, holds FEC algorithm on success 3614 * 3615 * Read the serdes data for the PHY port and extract the link speed and FEC 3616 * algorithm. 3617 */ 3618 static int 3619 ice_phy_get_speed_and_fec_e82x(struct ice_hw *hw, u8 port, 3620 enum ice_ptp_link_spd *link_out, 3621 enum ice_ptp_fec_mode *fec_out) 3622 { 3623 enum ice_ptp_link_spd link; 3624 enum ice_ptp_fec_mode fec; 3625 u32 serdes; 3626 int err; 3627 3628 err = ice_read_phy_reg_e82x(hw, port, P_REG_LINK_SPEED, &serdes); 3629 if (err) { 3630 ice_debug(hw, ICE_DBG_PTP, "Failed to read serdes info\n"); 3631 return err; 3632 } 3633 3634 /* Determine the FEC algorithm */ 3635 fec = (enum ice_ptp_fec_mode)P_REG_LINK_SPEED_FEC_MODE(serdes); 3636 3637 serdes &= P_REG_LINK_SPEED_SERDES_M; 3638 3639 /* Determine the link speed */ 3640 if (fec == ICE_PTP_FEC_MODE_RS_FEC) { 3641 switch (serdes) { 3642 case ICE_PTP_SERDES_25G: 3643 link = ICE_PTP_LNK_SPD_25G_RS; 3644 break; 3645 case ICE_PTP_SERDES_50G: 3646 link = ICE_PTP_LNK_SPD_50G_RS; 3647 break; 3648 case ICE_PTP_SERDES_100G: 3649 link = ICE_PTP_LNK_SPD_100G_RS; 3650 break; 3651 default: 3652 return -EIO; 3653 } 3654 } else { 3655 switch (serdes) { 3656 case ICE_PTP_SERDES_1G: 3657 link = ICE_PTP_LNK_SPD_1G; 3658 break; 3659 case ICE_PTP_SERDES_10G: 3660 link = ICE_PTP_LNK_SPD_10G; 3661 break; 3662 case ICE_PTP_SERDES_25G: 3663 link = ICE_PTP_LNK_SPD_25G; 3664 break; 3665 case ICE_PTP_SERDES_40G: 3666 link = ICE_PTP_LNK_SPD_40G; 3667 break; 3668 case ICE_PTP_SERDES_50G: 3669 link = ICE_PTP_LNK_SPD_50G; 3670 break; 3671 default: 3672 return -EIO; 3673 } 3674 } 3675 3676 if (link_out) 3677 *link_out = link; 3678 if (fec_out) 3679 *fec_out = fec; 3680 3681 return 0; 3682 } 3683 3684 /** 3685 * ice_phy_cfg_lane_e82x - Configure PHY quad for single/multi-lane timestamp 3686 * @hw: pointer to HW struct 3687 * @port: to configure the quad for 3688 */ 3689 static void ice_phy_cfg_lane_e82x(struct ice_hw *hw, u8 port) 3690 { 3691 enum ice_ptp_link_spd link_spd; 3692 int err; 3693 u32 val; 3694 u8 quad; 3695 3696 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, NULL); 3697 if (err) { 3698 ice_debug(hw, ICE_DBG_PTP, "Failed to get PHY link speed, err %d\n", 3699 err); 3700 return; 3701 } 3702 3703 quad = ICE_GET_QUAD_NUM(port); 3704 3705 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val); 3706 if (err) { 3707 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEM_GLB_CFG, err %d\n", 3708 err); 3709 return; 3710 } 3711 3712 if (link_spd >= ICE_PTP_LNK_SPD_40G) 3713 val &= ~Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M; 3714 else 3715 val |= Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M; 3716 3717 err = ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val); 3718 if (err) { 3719 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_MEM_GBL_CFG, err %d\n", 3720 err); 3721 return; 3722 } 3723 } 3724 3725 /** 3726 * ice_phy_cfg_uix_e82x - Configure Serdes UI to TU conversion for E822 3727 * @hw: pointer to the HW structure 3728 * @port: the port to configure 3729 * 3730 * Program the conversion ration of Serdes clock "unit intervals" (UIs) to PHC 3731 * hardware clock time units (TUs). That is, determine the number of TUs per 3732 * serdes unit interval, and program the UIX registers with this conversion. 3733 * 3734 * This conversion is used as part of the calibration process when determining 3735 * the additional error of a timestamp vs the real time of transmission or 3736 * receipt of the packet. 3737 * 3738 * Hardware uses the number of TUs per 66 UIs, written to the UIX registers 3739 * for the two main serdes clock rates, 10G/40G and 25G/100G serdes clocks. 3740 * 3741 * To calculate the conversion ratio, we use the following facts: 3742 * 3743 * a) the clock frequency in Hz (cycles per second) 3744 * b) the number of TUs per cycle (the increment value of the clock) 3745 * c) 1 second per 1 billion nanoseconds 3746 * d) the duration of 66 UIs in nanoseconds 3747 * 3748 * Given these facts, we can use the following table to work out what ratios 3749 * to multiply in order to get the number of TUs per 66 UIs: 3750 * 3751 * cycles | 1 second | incval (TUs) | nanoseconds 3752 * -------+--------------+--------------+------------- 3753 * second | 1 billion ns | cycle | 66 UIs 3754 * 3755 * To perform the multiplication using integers without too much loss of 3756 * precision, we can take use the following equation: 3757 * 3758 * (freq * incval * 6600 LINE_UI ) / ( 100 * 1 billion) 3759 * 3760 * We scale up to using 6600 UI instead of 66 in order to avoid fractional 3761 * nanosecond UIs (66 UI at 10G/40G is 6.4 ns) 3762 * 3763 * The increment value has a maximum expected range of about 34 bits, while 3764 * the frequency value is about 29 bits. Multiplying these values shouldn't 3765 * overflow the 64 bits. However, we must then further multiply them again by 3766 * the Serdes unit interval duration. To avoid overflow here, we split the 3767 * overall divide by 1e11 into a divide by 256 (shift down by 8 bits) and 3768 * a divide by 390,625,000. This does lose some precision, but avoids 3769 * miscalculation due to arithmetic overflow. 3770 */ 3771 static int ice_phy_cfg_uix_e82x(struct ice_hw *hw, u8 port) 3772 { 3773 u64 cur_freq, clk_incval, tu_per_sec, uix; 3774 int err; 3775 3776 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3777 clk_incval = ice_ptp_read_src_incval(hw); 3778 3779 /* Calculate TUs per second divided by 256 */ 3780 tu_per_sec = (cur_freq * clk_incval) >> 8; 3781 3782 #define LINE_UI_10G_40G 640 /* 6600 UIs is 640 nanoseconds at 10Gb/40Gb */ 3783 #define LINE_UI_25G_100G 256 /* 6600 UIs is 256 nanoseconds at 25Gb/100Gb */ 3784 3785 /* Program the 10Gb/40Gb conversion ratio */ 3786 uix = div_u64(tu_per_sec * LINE_UI_10G_40G, 390625000); 3787 3788 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_UIX66_10G_40G_L, 3789 uix); 3790 if (err) { 3791 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_10G_40G, err %d\n", 3792 err); 3793 return err; 3794 } 3795 3796 /* Program the 25Gb/100Gb conversion ratio */ 3797 uix = div_u64(tu_per_sec * LINE_UI_25G_100G, 390625000); 3798 3799 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_UIX66_25G_100G_L, 3800 uix); 3801 if (err) { 3802 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_25G_100G, err %d\n", 3803 err); 3804 return err; 3805 } 3806 3807 return 0; 3808 } 3809 3810 /** 3811 * ice_phy_cfg_parpcs_e82x - Configure TUs per PAR/PCS clock cycle 3812 * @hw: pointer to the HW struct 3813 * @port: port to configure 3814 * 3815 * Configure the number of TUs for the PAR and PCS clocks used as part of the 3816 * timestamp calibration process. This depends on the link speed, as the PHY 3817 * uses different markers depending on the speed. 3818 * 3819 * 1Gb/10Gb/25Gb: 3820 * - Tx/Rx PAR/PCS markers 3821 * 3822 * 25Gb RS: 3823 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers 3824 * 3825 * 40Gb/50Gb: 3826 * - Tx/Rx PAR/PCS markers 3827 * - Rx Deskew PAR/PCS markers 3828 * 3829 * 50G RS and 100GB RS: 3830 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers 3831 * - Rx Deskew PAR/PCS markers 3832 * - Tx PAR/PCS markers 3833 * 3834 * To calculate the conversion, we use the PHC clock frequency (cycles per 3835 * second), the increment value (TUs per cycle), and the related PHY clock 3836 * frequency to calculate the TUs per unit of the PHY link clock. The 3837 * following table shows how the units convert: 3838 * 3839 * cycles | TUs | second 3840 * -------+-------+-------- 3841 * second | cycle | cycles 3842 * 3843 * For each conversion register, look up the appropriate frequency from the 3844 * e822 PAR/PCS table and calculate the TUs per unit of that clock. Program 3845 * this to the appropriate register, preparing hardware to perform timestamp 3846 * calibration to calculate the total Tx or Rx offset to adjust the timestamp 3847 * in order to calibrate for the internal PHY delays. 3848 * 3849 * Note that the increment value ranges up to ~34 bits, and the clock 3850 * frequency is ~29 bits, so multiplying them together should fit within the 3851 * 64 bit arithmetic. 3852 */ 3853 static int ice_phy_cfg_parpcs_e82x(struct ice_hw *hw, u8 port) 3854 { 3855 u64 cur_freq, clk_incval, tu_per_sec, phy_tus; 3856 enum ice_ptp_link_spd link_spd; 3857 enum ice_ptp_fec_mode fec_mode; 3858 int err; 3859 3860 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode); 3861 if (err) 3862 return err; 3863 3864 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3865 clk_incval = ice_ptp_read_src_incval(hw); 3866 3867 /* Calculate TUs per cycle of the PHC clock */ 3868 tu_per_sec = cur_freq * clk_incval; 3869 3870 /* For each PHY conversion register, look up the appropriate link 3871 * speed frequency and determine the TUs per that clock's cycle time. 3872 * Split this into a high and low value and then program the 3873 * appropriate register. If that link speed does not use the 3874 * associated register, write zeros to clear it instead. 3875 */ 3876 3877 /* P_REG_PAR_TX_TUS */ 3878 if (e822_vernier[link_spd].tx_par_clk) 3879 phy_tus = div_u64(tu_per_sec, 3880 e822_vernier[link_spd].tx_par_clk); 3881 else 3882 phy_tus = 0; 3883 3884 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PAR_TX_TUS_L, 3885 phy_tus); 3886 if (err) 3887 return err; 3888 3889 /* P_REG_PAR_RX_TUS */ 3890 if (e822_vernier[link_spd].rx_par_clk) 3891 phy_tus = div_u64(tu_per_sec, 3892 e822_vernier[link_spd].rx_par_clk); 3893 else 3894 phy_tus = 0; 3895 3896 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PAR_RX_TUS_L, 3897 phy_tus); 3898 if (err) 3899 return err; 3900 3901 /* P_REG_PCS_TX_TUS */ 3902 if (e822_vernier[link_spd].tx_pcs_clk) 3903 phy_tus = div_u64(tu_per_sec, 3904 e822_vernier[link_spd].tx_pcs_clk); 3905 else 3906 phy_tus = 0; 3907 3908 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PCS_TX_TUS_L, 3909 phy_tus); 3910 if (err) 3911 return err; 3912 3913 /* P_REG_PCS_RX_TUS */ 3914 if (e822_vernier[link_spd].rx_pcs_clk) 3915 phy_tus = div_u64(tu_per_sec, 3916 e822_vernier[link_spd].rx_pcs_clk); 3917 else 3918 phy_tus = 0; 3919 3920 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PCS_RX_TUS_L, 3921 phy_tus); 3922 if (err) 3923 return err; 3924 3925 /* P_REG_DESK_PAR_TX_TUS */ 3926 if (e822_vernier[link_spd].tx_desk_rsgb_par) 3927 phy_tus = div_u64(tu_per_sec, 3928 e822_vernier[link_spd].tx_desk_rsgb_par); 3929 else 3930 phy_tus = 0; 3931 3932 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PAR_TX_TUS_L, 3933 phy_tus); 3934 if (err) 3935 return err; 3936 3937 /* P_REG_DESK_PAR_RX_TUS */ 3938 if (e822_vernier[link_spd].rx_desk_rsgb_par) 3939 phy_tus = div_u64(tu_per_sec, 3940 e822_vernier[link_spd].rx_desk_rsgb_par); 3941 else 3942 phy_tus = 0; 3943 3944 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PAR_RX_TUS_L, 3945 phy_tus); 3946 if (err) 3947 return err; 3948 3949 /* P_REG_DESK_PCS_TX_TUS */ 3950 if (e822_vernier[link_spd].tx_desk_rsgb_pcs) 3951 phy_tus = div_u64(tu_per_sec, 3952 e822_vernier[link_spd].tx_desk_rsgb_pcs); 3953 else 3954 phy_tus = 0; 3955 3956 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PCS_TX_TUS_L, 3957 phy_tus); 3958 if (err) 3959 return err; 3960 3961 /* P_REG_DESK_PCS_RX_TUS */ 3962 if (e822_vernier[link_spd].rx_desk_rsgb_pcs) 3963 phy_tus = div_u64(tu_per_sec, 3964 e822_vernier[link_spd].rx_desk_rsgb_pcs); 3965 else 3966 phy_tus = 0; 3967 3968 return ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PCS_RX_TUS_L, 3969 phy_tus); 3970 } 3971 3972 /** 3973 * ice_calc_fixed_tx_offset_e82x - Calculated Fixed Tx offset for a port 3974 * @hw: pointer to the HW struct 3975 * @link_spd: the Link speed to calculate for 3976 * 3977 * Calculate the fixed offset due to known static latency data. 3978 */ 3979 static u64 3980 ice_calc_fixed_tx_offset_e82x(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) 3981 { 3982 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset; 3983 3984 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3985 clk_incval = ice_ptp_read_src_incval(hw); 3986 3987 /* Calculate TUs per second */ 3988 tu_per_sec = cur_freq * clk_incval; 3989 3990 /* Calculate number of TUs to add for the fixed Tx latency. Since the 3991 * latency measurement is in 1/100th of a nanosecond, we need to 3992 * multiply by tu_per_sec and then divide by 1e11. This calculation 3993 * overflows 64 bit integer arithmetic, so break it up into two 3994 * divisions by 1e4 first then by 1e7. 3995 */ 3996 fixed_offset = div_u64(tu_per_sec, 10000); 3997 fixed_offset *= e822_vernier[link_spd].tx_fixed_delay; 3998 fixed_offset = div_u64(fixed_offset, 10000000); 3999 4000 return fixed_offset; 4001 } 4002 4003 /** 4004 * ice_phy_cfg_tx_offset_e82x - Configure total Tx timestamp offset 4005 * @hw: pointer to the HW struct 4006 * @port: the PHY port to configure 4007 * 4008 * Program the P_REG_TOTAL_TX_OFFSET register with the total number of TUs to 4009 * adjust Tx timestamps by. This is calculated by combining some known static 4010 * latency along with the Vernier offset computations done by hardware. 4011 * 4012 * This function will not return successfully until the Tx offset calculations 4013 * have been completed, which requires waiting until at least one packet has 4014 * been transmitted by the device. It is safe to call this function 4015 * periodically until calibration succeeds, as it will only program the offset 4016 * once. 4017 * 4018 * To avoid overflow, when calculating the offset based on the known static 4019 * latency values, we use measurements in 1/100th of a nanosecond, and divide 4020 * the TUs per second up front. This avoids overflow while allowing 4021 * calculation of the adjustment using integer arithmetic. 4022 * 4023 * Returns zero on success, -EBUSY if the hardware vernier offset 4024 * calibration has not completed, or another error code on failure. 4025 */ 4026 int ice_phy_cfg_tx_offset_e82x(struct ice_hw *hw, u8 port) 4027 { 4028 enum ice_ptp_link_spd link_spd; 4029 enum ice_ptp_fec_mode fec_mode; 4030 u64 total_offset, val; 4031 int err; 4032 u32 reg; 4033 4034 /* Nothing to do if we've already programmed the offset */ 4035 err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_OR, ®); 4036 if (err) { 4037 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OR for port %u, err %d\n", 4038 port, err); 4039 return err; 4040 } 4041 4042 if (reg) 4043 return 0; 4044 4045 err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_OV_STATUS, ®); 4046 if (err) { 4047 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OV_STATUS for port %u, err %d\n", 4048 port, err); 4049 return err; 4050 } 4051 4052 if (!(reg & P_REG_TX_OV_STATUS_OV_M)) 4053 return -EBUSY; 4054 4055 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode); 4056 if (err) 4057 return err; 4058 4059 total_offset = ice_calc_fixed_tx_offset_e82x(hw, link_spd); 4060 4061 /* Read the first Vernier offset from the PHY register and add it to 4062 * the total offset. 4063 */ 4064 if (link_spd == ICE_PTP_LNK_SPD_1G || 4065 link_spd == ICE_PTP_LNK_SPD_10G || 4066 link_spd == ICE_PTP_LNK_SPD_25G || 4067 link_spd == ICE_PTP_LNK_SPD_25G_RS || 4068 link_spd == ICE_PTP_LNK_SPD_40G || 4069 link_spd == ICE_PTP_LNK_SPD_50G) { 4070 err = ice_read_64b_phy_reg_e82x(hw, port, 4071 P_REG_PAR_PCS_TX_OFFSET_L, 4072 &val); 4073 if (err) 4074 return err; 4075 4076 total_offset += val; 4077 } 4078 4079 /* For Tx, we only need to use the second Vernier offset for 4080 * multi-lane link speeds with RS-FEC. The lanes will always be 4081 * aligned. 4082 */ 4083 if (link_spd == ICE_PTP_LNK_SPD_50G_RS || 4084 link_spd == ICE_PTP_LNK_SPD_100G_RS) { 4085 err = ice_read_64b_phy_reg_e82x(hw, port, 4086 P_REG_PAR_TX_TIME_L, 4087 &val); 4088 if (err) 4089 return err; 4090 4091 total_offset += val; 4092 } 4093 4094 /* Now that the total offset has been calculated, program it to the 4095 * PHY and indicate that the Tx offset is ready. After this, 4096 * timestamps will be enabled. 4097 */ 4098 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_TOTAL_TX_OFFSET_L, 4099 total_offset); 4100 if (err) 4101 return err; 4102 4103 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 1); 4104 if (err) 4105 return err; 4106 4107 dev_info(ice_hw_to_dev(hw), "Port=%d Tx vernier offset calibration complete\n", 4108 port); 4109 4110 return 0; 4111 } 4112 4113 /** 4114 * ice_phy_calc_pmd_adj_e82x - Calculate PMD adjustment for Rx 4115 * @hw: pointer to the HW struct 4116 * @port: the PHY port to adjust for 4117 * @link_spd: the current link speed of the PHY 4118 * @fec_mode: the current FEC mode of the PHY 4119 * @pmd_adj: on return, the amount to adjust the Rx total offset by 4120 * 4121 * Calculates the adjustment to Rx timestamps due to PMD alignment in the PHY. 4122 * This varies by link speed and FEC mode. The value calculated accounts for 4123 * various delays caused when receiving a packet. 4124 */ 4125 static int 4126 ice_phy_calc_pmd_adj_e82x(struct ice_hw *hw, u8 port, 4127 enum ice_ptp_link_spd link_spd, 4128 enum ice_ptp_fec_mode fec_mode, u64 *pmd_adj) 4129 { 4130 u64 cur_freq, clk_incval, tu_per_sec, mult, adj; 4131 u8 pmd_align; 4132 u32 val; 4133 int err; 4134 4135 err = ice_read_phy_reg_e82x(hw, port, P_REG_PMD_ALIGNMENT, &val); 4136 if (err) { 4137 ice_debug(hw, ICE_DBG_PTP, "Failed to read PMD alignment, err %d\n", 4138 err); 4139 return err; 4140 } 4141 4142 pmd_align = (u8)val; 4143 4144 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 4145 clk_incval = ice_ptp_read_src_incval(hw); 4146 4147 /* Calculate TUs per second */ 4148 tu_per_sec = cur_freq * clk_incval; 4149 4150 /* The PMD alignment adjustment measurement depends on the link speed, 4151 * and whether FEC is enabled. For each link speed, the alignment 4152 * adjustment is calculated by dividing a value by the length of 4153 * a Time Unit in nanoseconds. 4154 * 4155 * 1G: align == 4 ? 10 * 0.8 : (align + 6 % 10) * 0.8 4156 * 10G: align == 65 ? 0 : (align * 0.1 * 32/33) 4157 * 10G w/FEC: align * 0.1 * 32/33 4158 * 25G: align == 65 ? 0 : (align * 0.4 * 32/33) 4159 * 25G w/FEC: align * 0.4 * 32/33 4160 * 40G: align == 65 ? 0 : (align * 0.1 * 32/33) 4161 * 40G w/FEC: align * 0.1 * 32/33 4162 * 50G: align == 65 ? 0 : (align * 0.4 * 32/33) 4163 * 50G w/FEC: align * 0.8 * 32/33 4164 * 4165 * For RS-FEC, if align is < 17 then we must also add 1.6 * 32/33. 4166 * 4167 * To allow for calculating this value using integer arithmetic, we 4168 * instead start with the number of TUs per second, (inverse of the 4169 * length of a Time Unit in nanoseconds), multiply by a value based 4170 * on the PMD alignment register, and then divide by the right value 4171 * calculated based on the table above. To avoid integer overflow this 4172 * division is broken up into a step of dividing by 125 first. 4173 */ 4174 if (link_spd == ICE_PTP_LNK_SPD_1G) { 4175 if (pmd_align == 4) 4176 mult = 10; 4177 else 4178 mult = (pmd_align + 6) % 10; 4179 } else if (link_spd == ICE_PTP_LNK_SPD_10G || 4180 link_spd == ICE_PTP_LNK_SPD_25G || 4181 link_spd == ICE_PTP_LNK_SPD_40G || 4182 link_spd == ICE_PTP_LNK_SPD_50G) { 4183 /* If Clause 74 FEC, always calculate PMD adjust */ 4184 if (pmd_align != 65 || fec_mode == ICE_PTP_FEC_MODE_CLAUSE74) 4185 mult = pmd_align; 4186 else 4187 mult = 0; 4188 } else if (link_spd == ICE_PTP_LNK_SPD_25G_RS || 4189 link_spd == ICE_PTP_LNK_SPD_50G_RS || 4190 link_spd == ICE_PTP_LNK_SPD_100G_RS) { 4191 if (pmd_align < 17) 4192 mult = pmd_align + 40; 4193 else 4194 mult = pmd_align; 4195 } else { 4196 ice_debug(hw, ICE_DBG_PTP, "Unknown link speed %d, skipping PMD adjustment\n", 4197 link_spd); 4198 mult = 0; 4199 } 4200 4201 /* In some cases, there's no need to adjust for the PMD alignment */ 4202 if (!mult) { 4203 *pmd_adj = 0; 4204 return 0; 4205 } 4206 4207 /* Calculate the adjustment by multiplying TUs per second by the 4208 * appropriate multiplier and divisor. To avoid overflow, we first 4209 * divide by 125, and then handle remaining divisor based on the link 4210 * speed pmd_adj_divisor value. 4211 */ 4212 adj = div_u64(tu_per_sec, 125); 4213 adj *= mult; 4214 adj = div_u64(adj, e822_vernier[link_spd].pmd_adj_divisor); 4215 4216 /* Finally, for 25G-RS and 50G-RS, a further adjustment for the Rx 4217 * cycle count is necessary. 4218 */ 4219 if (link_spd == ICE_PTP_LNK_SPD_25G_RS) { 4220 u64 cycle_adj; 4221 u8 rx_cycle; 4222 4223 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_40_TO_160_CNT, 4224 &val); 4225 if (err) { 4226 ice_debug(hw, ICE_DBG_PTP, "Failed to read 25G-RS Rx cycle count, err %d\n", 4227 err); 4228 return err; 4229 } 4230 4231 rx_cycle = val & P_REG_RX_40_TO_160_CNT_RXCYC_M; 4232 if (rx_cycle) { 4233 mult = (4 - rx_cycle) * 40; 4234 4235 cycle_adj = div_u64(tu_per_sec, 125); 4236 cycle_adj *= mult; 4237 cycle_adj = div_u64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor); 4238 4239 adj += cycle_adj; 4240 } 4241 } else if (link_spd == ICE_PTP_LNK_SPD_50G_RS) { 4242 u64 cycle_adj; 4243 u8 rx_cycle; 4244 4245 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_80_TO_160_CNT, 4246 &val); 4247 if (err) { 4248 ice_debug(hw, ICE_DBG_PTP, "Failed to read 50G-RS Rx cycle count, err %d\n", 4249 err); 4250 return err; 4251 } 4252 4253 rx_cycle = val & P_REG_RX_80_TO_160_CNT_RXCYC_M; 4254 if (rx_cycle) { 4255 mult = rx_cycle * 40; 4256 4257 cycle_adj = div_u64(tu_per_sec, 125); 4258 cycle_adj *= mult; 4259 cycle_adj = div_u64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor); 4260 4261 adj += cycle_adj; 4262 } 4263 } 4264 4265 /* Return the calculated adjustment */ 4266 *pmd_adj = adj; 4267 4268 return 0; 4269 } 4270 4271 /** 4272 * ice_calc_fixed_rx_offset_e82x - Calculated the fixed Rx offset for a port 4273 * @hw: pointer to HW struct 4274 * @link_spd: The Link speed to calculate for 4275 * 4276 * Determine the fixed Rx latency for a given link speed. 4277 */ 4278 static u64 4279 ice_calc_fixed_rx_offset_e82x(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) 4280 { 4281 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset; 4282 4283 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 4284 clk_incval = ice_ptp_read_src_incval(hw); 4285 4286 /* Calculate TUs per second */ 4287 tu_per_sec = cur_freq * clk_incval; 4288 4289 /* Calculate number of TUs to add for the fixed Rx latency. Since the 4290 * latency measurement is in 1/100th of a nanosecond, we need to 4291 * multiply by tu_per_sec and then divide by 1e11. This calculation 4292 * overflows 64 bit integer arithmetic, so break it up into two 4293 * divisions by 1e4 first then by 1e7. 4294 */ 4295 fixed_offset = div_u64(tu_per_sec, 10000); 4296 fixed_offset *= e822_vernier[link_spd].rx_fixed_delay; 4297 fixed_offset = div_u64(fixed_offset, 10000000); 4298 4299 return fixed_offset; 4300 } 4301 4302 /** 4303 * ice_phy_cfg_rx_offset_e82x - Configure total Rx timestamp offset 4304 * @hw: pointer to the HW struct 4305 * @port: the PHY port to configure 4306 * 4307 * Program the P_REG_TOTAL_RX_OFFSET register with the number of Time Units to 4308 * adjust Rx timestamps by. This combines calculations from the Vernier offset 4309 * measurements taken in hardware with some data about known fixed delay as 4310 * well as adjusting for multi-lane alignment delay. 4311 * 4312 * This function will not return successfully until the Rx offset calculations 4313 * have been completed, which requires waiting until at least one packet has 4314 * been received by the device. It is safe to call this function periodically 4315 * until calibration succeeds, as it will only program the offset once. 4316 * 4317 * This function must be called only after the offset registers are valid, 4318 * i.e. after the Vernier calibration wait has passed, to ensure that the PHY 4319 * has measured the offset. 4320 * 4321 * To avoid overflow, when calculating the offset based on the known static 4322 * latency values, we use measurements in 1/100th of a nanosecond, and divide 4323 * the TUs per second up front. This avoids overflow while allowing 4324 * calculation of the adjustment using integer arithmetic. 4325 * 4326 * Returns zero on success, -EBUSY if the hardware vernier offset 4327 * calibration has not completed, or another error code on failure. 4328 */ 4329 int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port) 4330 { 4331 enum ice_ptp_link_spd link_spd; 4332 enum ice_ptp_fec_mode fec_mode; 4333 u64 total_offset, pmd, val; 4334 int err; 4335 u32 reg; 4336 4337 /* Nothing to do if we've already programmed the offset */ 4338 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_OR, ®); 4339 if (err) { 4340 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OR for port %u, err %d\n", 4341 port, err); 4342 return err; 4343 } 4344 4345 if (reg) 4346 return 0; 4347 4348 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_OV_STATUS, ®); 4349 if (err) { 4350 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OV_STATUS for port %u, err %d\n", 4351 port, err); 4352 return err; 4353 } 4354 4355 if (!(reg & P_REG_RX_OV_STATUS_OV_M)) 4356 return -EBUSY; 4357 4358 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode); 4359 if (err) 4360 return err; 4361 4362 total_offset = ice_calc_fixed_rx_offset_e82x(hw, link_spd); 4363 4364 /* Read the first Vernier offset from the PHY register and add it to 4365 * the total offset. 4366 */ 4367 err = ice_read_64b_phy_reg_e82x(hw, port, 4368 P_REG_PAR_PCS_RX_OFFSET_L, 4369 &val); 4370 if (err) 4371 return err; 4372 4373 total_offset += val; 4374 4375 /* For Rx, all multi-lane link speeds include a second Vernier 4376 * calibration, because the lanes might not be aligned. 4377 */ 4378 if (link_spd == ICE_PTP_LNK_SPD_40G || 4379 link_spd == ICE_PTP_LNK_SPD_50G || 4380 link_spd == ICE_PTP_LNK_SPD_50G_RS || 4381 link_spd == ICE_PTP_LNK_SPD_100G_RS) { 4382 err = ice_read_64b_phy_reg_e82x(hw, port, 4383 P_REG_PAR_RX_TIME_L, 4384 &val); 4385 if (err) 4386 return err; 4387 4388 total_offset += val; 4389 } 4390 4391 /* In addition, Rx must account for the PMD alignment */ 4392 err = ice_phy_calc_pmd_adj_e82x(hw, port, link_spd, fec_mode, &pmd); 4393 if (err) 4394 return err; 4395 4396 /* For RS-FEC, this adjustment adds delay, but for other modes, it 4397 * subtracts delay. 4398 */ 4399 if (fec_mode == ICE_PTP_FEC_MODE_RS_FEC) 4400 total_offset += pmd; 4401 else 4402 total_offset -= pmd; 4403 4404 /* Now that the total offset has been calculated, program it to the 4405 * PHY and indicate that the Rx offset is ready. After this, 4406 * timestamps will be enabled. 4407 */ 4408 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_TOTAL_RX_OFFSET_L, 4409 total_offset); 4410 if (err) 4411 return err; 4412 4413 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 1); 4414 if (err) 4415 return err; 4416 4417 dev_info(ice_hw_to_dev(hw), "Port=%d Rx vernier offset calibration complete\n", 4418 port); 4419 4420 return 0; 4421 } 4422 4423 /** 4424 * ice_ptp_clear_phy_offset_ready_e82x - Clear PHY TX_/RX_OFFSET_READY registers 4425 * @hw: pointer to the HW struct 4426 * 4427 * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted 4428 * and received timestamps as invalid. 4429 * 4430 * Return: 0 on success, other error codes when failed to write to PHY 4431 */ 4432 int ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw *hw) 4433 { 4434 u8 port; 4435 4436 for (port = 0; port < hw->ptp.num_lports; port++) { 4437 int err; 4438 4439 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0); 4440 if (err) { 4441 dev_warn(ice_hw_to_dev(hw), 4442 "Failed to clear PHY TX_OFFSET_READY register\n"); 4443 return err; 4444 } 4445 4446 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0); 4447 if (err) { 4448 dev_warn(ice_hw_to_dev(hw), 4449 "Failed to clear PHY RX_OFFSET_READY register\n"); 4450 return err; 4451 } 4452 } 4453 4454 return 0; 4455 } 4456 4457 /** 4458 * ice_read_phy_and_phc_time_e82x - Simultaneously capture PHC and PHY time 4459 * @hw: pointer to the HW struct 4460 * @port: the PHY port to read 4461 * @phy_time: on return, the 64bit PHY timer value 4462 * @phc_time: on return, the lower 64bits of PHC time 4463 * 4464 * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY 4465 * and PHC timer values. 4466 */ 4467 static int 4468 ice_read_phy_and_phc_time_e82x(struct ice_hw *hw, u8 port, u64 *phy_time, 4469 u64 *phc_time) 4470 { 4471 u64 tx_time, rx_time; 4472 u32 zo, lo; 4473 u8 tmr_idx; 4474 int err; 4475 4476 tmr_idx = ice_get_ptp_src_clock_index(hw); 4477 4478 /* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */ 4479 ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME); 4480 4481 /* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */ 4482 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME); 4483 if (err) 4484 return err; 4485 4486 /* Issue the sync to start the ICE_PTP_READ_TIME capture */ 4487 ice_ptp_exec_tmr_cmd(hw); 4488 4489 /* Read the captured PHC time from the shadow time registers */ 4490 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx)); 4491 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx)); 4492 *phc_time = (u64)lo << 32 | zo; 4493 4494 /* Read the captured PHY time from the PHY shadow registers */ 4495 err = ice_ptp_read_port_capture(hw, port, &tx_time, &rx_time); 4496 if (err) 4497 return err; 4498 4499 /* If the PHY Tx and Rx timers don't match, log a warning message. 4500 * Note that this should not happen in normal circumstances since the 4501 * driver always programs them together. 4502 */ 4503 if (tx_time != rx_time) 4504 dev_warn(ice_hw_to_dev(hw), 4505 "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n", 4506 port, (unsigned long long)tx_time, 4507 (unsigned long long)rx_time); 4508 4509 *phy_time = tx_time; 4510 4511 return 0; 4512 } 4513 4514 /** 4515 * ice_sync_phy_timer_e82x - Synchronize the PHY timer with PHC timer 4516 * @hw: pointer to the HW struct 4517 * @port: the PHY port to synchronize 4518 * 4519 * Perform an adjustment to ensure that the PHY and PHC timers are in sync. 4520 * This is done by issuing a ICE_PTP_READ_TIME command which triggers a 4521 * simultaneous read of the PHY timer and PHC timer. Then we use the 4522 * difference to calculate an appropriate 2s complement addition to add 4523 * to the PHY timer in order to ensure it reads the same value as the 4524 * primary PHC timer. 4525 */ 4526 static int ice_sync_phy_timer_e82x(struct ice_hw *hw, u8 port) 4527 { 4528 u64 phc_time, phy_time, difference; 4529 int err; 4530 4531 if (!ice_ptp_lock(hw)) { 4532 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n"); 4533 return -EBUSY; 4534 } 4535 4536 err = ice_read_phy_and_phc_time_e82x(hw, port, &phy_time, &phc_time); 4537 if (err) 4538 goto err_unlock; 4539 4540 /* Calculate the amount required to add to the port time in order for 4541 * it to match the PHC time. 4542 * 4543 * Note that the port adjustment is done using 2s complement 4544 * arithmetic. This is convenient since it means that we can simply 4545 * calculate the difference between the PHC time and the port time, 4546 * and it will be interpreted correctly. 4547 */ 4548 difference = phc_time - phy_time; 4549 4550 err = ice_ptp_prep_port_adj_e82x(hw, port, (s64)difference); 4551 if (err) 4552 goto err_unlock; 4553 4554 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME); 4555 if (err) 4556 goto err_unlock; 4557 4558 /* Do not perform any action on the main timer */ 4559 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 4560 4561 /* Issue the sync to activate the time adjustment */ 4562 ice_ptp_exec_tmr_cmd(hw); 4563 4564 /* Re-capture the timer values to flush the command registers and 4565 * verify that the time was properly adjusted. 4566 */ 4567 err = ice_read_phy_and_phc_time_e82x(hw, port, &phy_time, &phc_time); 4568 if (err) 4569 goto err_unlock; 4570 4571 dev_info(ice_hw_to_dev(hw), 4572 "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n", 4573 port, (unsigned long long)phy_time, 4574 (unsigned long long)phc_time); 4575 4576 ice_ptp_unlock(hw); 4577 4578 return 0; 4579 4580 err_unlock: 4581 ice_ptp_unlock(hw); 4582 return err; 4583 } 4584 4585 /** 4586 * ice_stop_phy_timer_e82x - Stop the PHY clock timer 4587 * @hw: pointer to the HW struct 4588 * @port: the PHY port to stop 4589 * @soft_reset: if true, hold the SOFT_RESET bit of P_REG_PS 4590 * 4591 * Stop the clock of a PHY port. This must be done as part of the flow to 4592 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 4593 * initialized or when link speed changes. 4594 */ 4595 int 4596 ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset) 4597 { 4598 int err; 4599 u32 val; 4600 4601 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0); 4602 if (err) 4603 return err; 4604 4605 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0); 4606 if (err) 4607 return err; 4608 4609 err = ice_read_phy_reg_e82x(hw, port, P_REG_PS, &val); 4610 if (err) 4611 return err; 4612 4613 val &= ~P_REG_PS_START_M; 4614 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4615 if (err) 4616 return err; 4617 4618 val &= ~P_REG_PS_ENA_CLK_M; 4619 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4620 if (err) 4621 return err; 4622 4623 if (soft_reset) { 4624 val |= P_REG_PS_SFT_RESET_M; 4625 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4626 if (err) 4627 return err; 4628 } 4629 4630 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port); 4631 4632 return 0; 4633 } 4634 4635 /** 4636 * ice_start_phy_timer_e82x - Start the PHY clock timer 4637 * @hw: pointer to the HW struct 4638 * @port: the PHY port to start 4639 * 4640 * Start the clock of a PHY port. This must be done as part of the flow to 4641 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 4642 * initialized or when link speed changes. 4643 * 4644 * Hardware will take Vernier measurements on Tx or Rx of packets. 4645 */ 4646 int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port) 4647 { 4648 u32 lo, hi, val; 4649 u64 incval; 4650 u8 tmr_idx; 4651 int err; 4652 4653 tmr_idx = ice_get_ptp_src_clock_index(hw); 4654 4655 err = ice_stop_phy_timer_e82x(hw, port, false); 4656 if (err) 4657 return err; 4658 4659 ice_phy_cfg_lane_e82x(hw, port); 4660 4661 err = ice_phy_cfg_uix_e82x(hw, port); 4662 if (err) 4663 return err; 4664 4665 err = ice_phy_cfg_parpcs_e82x(hw, port); 4666 if (err) 4667 return err; 4668 4669 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 4670 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 4671 incval = (u64)hi << 32 | lo; 4672 4673 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L, incval); 4674 if (err) 4675 return err; 4676 4677 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL); 4678 if (err) 4679 return err; 4680 4681 /* Do not perform any action on the main timer */ 4682 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 4683 4684 ice_ptp_exec_tmr_cmd(hw); 4685 4686 err = ice_read_phy_reg_e82x(hw, port, P_REG_PS, &val); 4687 if (err) 4688 return err; 4689 4690 val |= P_REG_PS_SFT_RESET_M; 4691 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4692 if (err) 4693 return err; 4694 4695 val |= P_REG_PS_START_M; 4696 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4697 if (err) 4698 return err; 4699 4700 val &= ~P_REG_PS_SFT_RESET_M; 4701 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4702 if (err) 4703 return err; 4704 4705 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL); 4706 if (err) 4707 return err; 4708 4709 ice_ptp_exec_tmr_cmd(hw); 4710 4711 val |= P_REG_PS_ENA_CLK_M; 4712 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4713 if (err) 4714 return err; 4715 4716 val |= P_REG_PS_LOAD_OFFSET_M; 4717 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4718 if (err) 4719 return err; 4720 4721 ice_ptp_exec_tmr_cmd(hw); 4722 4723 err = ice_sync_phy_timer_e82x(hw, port); 4724 if (err) 4725 return err; 4726 4727 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port); 4728 4729 return 0; 4730 } 4731 4732 /** 4733 * ice_get_phy_tx_tstamp_ready_e82x - Read Tx memory status register 4734 * @hw: pointer to the HW struct 4735 * @quad: the timestamp quad to read from 4736 * @tstamp_ready: contents of the Tx memory status register 4737 * 4738 * Read the Q_REG_TX_MEMORY_STATUS register indicating which timestamps in 4739 * the PHY are ready. A set bit means the corresponding timestamp is valid and 4740 * ready to be captured from the PHY timestamp block. 4741 */ 4742 static int 4743 ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw *hw, u8 quad, u64 *tstamp_ready) 4744 { 4745 u32 hi, lo; 4746 int err; 4747 4748 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_U, &hi); 4749 if (err) { 4750 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_U for quad %u, err %d\n", 4751 quad, err); 4752 return err; 4753 } 4754 4755 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_L, &lo); 4756 if (err) { 4757 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_L for quad %u, err %d\n", 4758 quad, err); 4759 return err; 4760 } 4761 4762 *tstamp_ready = (u64)hi << 32 | (u64)lo; 4763 4764 return 0; 4765 } 4766 4767 /** 4768 * ice_phy_cfg_intr_e82x - Configure TX timestamp interrupt 4769 * @hw: pointer to the HW struct 4770 * @quad: the timestamp quad 4771 * @ena: enable or disable interrupt 4772 * @threshold: interrupt threshold 4773 * 4774 * Configure TX timestamp interrupt for the specified quad 4775 * 4776 * Return: 0 on success, other error codes when failed to read/write quad 4777 */ 4778 4779 int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold) 4780 { 4781 int err; 4782 u32 val; 4783 4784 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val); 4785 if (err) 4786 return err; 4787 4788 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M; 4789 if (ena) { 4790 val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M; 4791 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M; 4792 val |= FIELD_PREP(Q_REG_TX_MEM_GBL_CFG_INTR_THR_M, threshold); 4793 } 4794 4795 return ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val); 4796 } 4797 4798 /** 4799 * ice_ptp_init_phy_e82x - initialize PHY parameters 4800 * @ptp: pointer to the PTP HW struct 4801 */ 4802 static void ice_ptp_init_phy_e82x(struct ice_ptp_hw *ptp) 4803 { 4804 ptp->num_lports = 8; 4805 ptp->ports_per_phy = 8; 4806 } 4807 4808 /* E810 functions 4809 * 4810 * The following functions operate on the E810 series devices which use 4811 * a separate external PHY. 4812 */ 4813 4814 /** 4815 * ice_read_phy_reg_e810 - Read register from external PHY on E810 4816 * @hw: pointer to the HW struct 4817 * @addr: the address to read from 4818 * @val: On return, the value read from the PHY 4819 * 4820 * Read a register from the external PHY on the E810 device. 4821 */ 4822 static int ice_read_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 *val) 4823 { 4824 struct ice_sbq_msg_input msg = {0}; 4825 int err; 4826 4827 msg.msg_addr_low = lower_16_bits(addr); 4828 msg.msg_addr_high = upper_16_bits(addr); 4829 msg.opcode = ice_sbq_msg_rd; 4830 msg.dest_dev = ice_sbq_dev_phy_0; 4831 4832 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 4833 if (err) { 4834 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 4835 err); 4836 return err; 4837 } 4838 4839 *val = msg.data; 4840 4841 return 0; 4842 } 4843 4844 /** 4845 * ice_write_phy_reg_e810 - Write register on external PHY on E810 4846 * @hw: pointer to the HW struct 4847 * @addr: the address to writem to 4848 * @val: the value to write to the PHY 4849 * 4850 * Write a value to a register of the external PHY on the E810 device. 4851 */ 4852 static int ice_write_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 val) 4853 { 4854 struct ice_sbq_msg_input msg = {0}; 4855 int err; 4856 4857 msg.msg_addr_low = lower_16_bits(addr); 4858 msg.msg_addr_high = upper_16_bits(addr); 4859 msg.opcode = ice_sbq_msg_wr; 4860 msg.dest_dev = ice_sbq_dev_phy_0; 4861 msg.data = val; 4862 4863 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 4864 if (err) { 4865 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 4866 err); 4867 return err; 4868 } 4869 4870 return 0; 4871 } 4872 4873 /** 4874 * ice_read_phy_tstamp_ll_e810 - Read a PHY timestamp registers through the FW 4875 * @hw: pointer to the HW struct 4876 * @idx: the timestamp index to read 4877 * @hi: 8 bit timestamp high value 4878 * @lo: 32 bit timestamp low value 4879 * 4880 * Read a 8bit timestamp high value and 32 bit timestamp low value out of the 4881 * timestamp block of the external PHY on the E810 device using the low latency 4882 * timestamp read. 4883 */ 4884 static int 4885 ice_read_phy_tstamp_ll_e810(struct ice_hw *hw, u8 idx, u8 *hi, u32 *lo) 4886 { 4887 struct ice_e810_params *params = &hw->ptp.phy.e810; 4888 unsigned long flags; 4889 u32 val; 4890 int err; 4891 4892 spin_lock_irqsave(¶ms->atqbal_wq.lock, flags); 4893 4894 /* Wait for any pending in-progress low latency interrupt */ 4895 err = wait_event_interruptible_locked_irq(params->atqbal_wq, 4896 !(params->atqbal_flags & 4897 ATQBAL_FLAGS_INTR_IN_PROGRESS)); 4898 if (err) { 4899 spin_unlock_irqrestore(¶ms->atqbal_wq.lock, flags); 4900 return err; 4901 } 4902 4903 /* Write TS index to read to the PF register so the FW can read it */ 4904 val = FIELD_PREP(REG_LL_PROXY_H_TS_IDX, idx) | REG_LL_PROXY_H_EXEC; 4905 wr32(hw, REG_LL_PROXY_H, val); 4906 4907 /* Read the register repeatedly until the FW provides us the TS */ 4908 err = read_poll_timeout_atomic(rd32, val, 4909 !FIELD_GET(REG_LL_PROXY_H_EXEC, val), 10, 4910 REG_LL_PROXY_H_TIMEOUT_US, false, hw, 4911 REG_LL_PROXY_H); 4912 if (err) { 4913 ice_debug(hw, ICE_DBG_PTP, "Failed to read PTP timestamp using low latency read\n"); 4914 spin_unlock_irqrestore(¶ms->atqbal_wq.lock, flags); 4915 return err; 4916 } 4917 4918 /* High 8 bit value of the TS is on the bits 16:23 */ 4919 *hi = FIELD_GET(REG_LL_PROXY_H_TS_HIGH, val); 4920 4921 /* Read the low 32 bit value and set the TS valid bit */ 4922 *lo = rd32(hw, REG_LL_PROXY_L) | TS_VALID; 4923 4924 spin_unlock_irqrestore(¶ms->atqbal_wq.lock, flags); 4925 4926 return 0; 4927 } 4928 4929 /** 4930 * ice_read_phy_tstamp_sbq_e810 - Read a PHY timestamp registers through the sbq 4931 * @hw: pointer to the HW struct 4932 * @lport: the lport to read from 4933 * @idx: the timestamp index to read 4934 * @hi: 8 bit timestamp high value 4935 * @lo: 32 bit timestamp low value 4936 * 4937 * Read a 8bit timestamp high value and 32 bit timestamp low value out of the 4938 * timestamp block of the external PHY on the E810 device using sideband queue. 4939 */ 4940 static int 4941 ice_read_phy_tstamp_sbq_e810(struct ice_hw *hw, u8 lport, u8 idx, u8 *hi, 4942 u32 *lo) 4943 { 4944 u32 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); 4945 u32 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); 4946 u32 lo_val, hi_val; 4947 int err; 4948 4949 err = ice_read_phy_reg_e810(hw, lo_addr, &lo_val); 4950 if (err) { 4951 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 4952 err); 4953 return err; 4954 } 4955 4956 err = ice_read_phy_reg_e810(hw, hi_addr, &hi_val); 4957 if (err) { 4958 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 4959 err); 4960 return err; 4961 } 4962 4963 *lo = lo_val; 4964 *hi = (u8)hi_val; 4965 4966 return 0; 4967 } 4968 4969 /** 4970 * ice_read_phy_tstamp_e810 - Read a PHY timestamp out of the external PHY 4971 * @hw: pointer to the HW struct 4972 * @lport: the lport to read from 4973 * @idx: the timestamp index to read 4974 * @tstamp: on return, the 40bit timestamp value 4975 * 4976 * Read a 40bit timestamp value out of the timestamp block of the external PHY 4977 * on the E810 device. 4978 */ 4979 static int 4980 ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) 4981 { 4982 u32 lo = 0; 4983 u8 hi = 0; 4984 int err; 4985 4986 if (hw->dev_caps.ts_dev_info.ts_ll_read) 4987 err = ice_read_phy_tstamp_ll_e810(hw, idx, &hi, &lo); 4988 else 4989 err = ice_read_phy_tstamp_sbq_e810(hw, lport, idx, &hi, &lo); 4990 4991 if (err) 4992 return err; 4993 4994 /* For E810 devices, the timestamp is reported with the lower 32 bits 4995 * in the low register, and the upper 8 bits in the high register. 4996 */ 4997 *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) | 4998 FIELD_PREP(PHY_EXT_40B_LOW_M, lo); 4999 5000 return 0; 5001 } 5002 5003 /** 5004 * ice_clear_phy_tstamp_e810 - Clear a timestamp from the external PHY 5005 * @hw: pointer to the HW struct 5006 * @lport: the lport to read from 5007 * @idx: the timestamp index to reset 5008 * 5009 * Read the timestamp and then forcibly overwrite its value to clear the valid 5010 * bit from the timestamp block of the external PHY on the E810 device. 5011 * 5012 * This function should only be called on an idx whose bit is set according to 5013 * ice_get_phy_tx_tstamp_ready(). 5014 */ 5015 static int ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx) 5016 { 5017 u32 lo_addr, hi_addr; 5018 u64 unused_tstamp; 5019 int err; 5020 5021 err = ice_read_phy_tstamp_e810(hw, lport, idx, &unused_tstamp); 5022 if (err) { 5023 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for lport %u, idx %u, err %d\n", 5024 lport, idx, err); 5025 return err; 5026 } 5027 5028 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); 5029 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); 5030 5031 err = ice_write_phy_reg_e810(hw, lo_addr, 0); 5032 if (err) { 5033 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for lport %u, idx %u, err %d\n", 5034 lport, idx, err); 5035 return err; 5036 } 5037 5038 err = ice_write_phy_reg_e810(hw, hi_addr, 0); 5039 if (err) { 5040 ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register for lport %u, idx %u, err %d\n", 5041 lport, idx, err); 5042 return err; 5043 } 5044 5045 return 0; 5046 } 5047 5048 /** 5049 * ice_ptp_init_phc_e810 - Perform E810 specific PHC initialization 5050 * @hw: pointer to HW struct 5051 * 5052 * Perform E810-specific PTP hardware clock initialization steps. 5053 * 5054 * Return: 0 on success, other error codes when failed to initialize TimeSync 5055 */ 5056 static int ice_ptp_init_phc_e810(struct ice_hw *hw) 5057 { 5058 u8 tmr_idx; 5059 int err; 5060 5061 ice_ptp_cfg_sync_delay(hw, ICE_E810_E830_SYNC_DELAY); 5062 5063 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5064 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_ENA(tmr_idx), 5065 GLTSYN_ENA_TSYN_ENA_M); 5066 if (err) 5067 ice_debug(hw, ICE_DBG_PTP, "PTP failed in ena_phy_time_syn %d\n", 5068 err); 5069 5070 return err; 5071 } 5072 5073 /** 5074 * ice_ptp_prep_phy_time_e810 - Prepare PHY port with initial time 5075 * @hw: Board private structure 5076 * @time: Time to initialize the PHY port clock to 5077 * 5078 * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the 5079 * initial clock time. The time will not actually be programmed until the 5080 * driver issues an ICE_PTP_INIT_TIME command. 5081 * 5082 * The time value is the upper 32 bits of the PHY timer, usually in units of 5083 * nominal nanoseconds. 5084 */ 5085 static int ice_ptp_prep_phy_time_e810(struct ice_hw *hw, u32 time) 5086 { 5087 u8 tmr_idx; 5088 int err; 5089 5090 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5091 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_0(tmr_idx), 0); 5092 if (err) { 5093 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_0, err %d\n", 5094 err); 5095 return err; 5096 } 5097 5098 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_L(tmr_idx), time); 5099 if (err) { 5100 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_L, err %d\n", 5101 err); 5102 return err; 5103 } 5104 5105 return 0; 5106 } 5107 5108 /** 5109 * ice_ptp_prep_phy_adj_ll_e810 - Prep PHY ports for a time adjustment 5110 * @hw: pointer to HW struct 5111 * @adj: adjustment value to program 5112 * 5113 * Use the low latency firmware interface to program PHY time adjustment to 5114 * all PHY ports. 5115 * 5116 * Return: 0 on success, -EBUSY on timeout 5117 */ 5118 static int ice_ptp_prep_phy_adj_ll_e810(struct ice_hw *hw, s32 adj) 5119 { 5120 const u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5121 struct ice_e810_params *params = &hw->ptp.phy.e810; 5122 u32 val; 5123 int err; 5124 5125 spin_lock_irq(¶ms->atqbal_wq.lock); 5126 5127 /* Wait for any pending in-progress low latency interrupt */ 5128 err = wait_event_interruptible_locked_irq(params->atqbal_wq, 5129 !(params->atqbal_flags & 5130 ATQBAL_FLAGS_INTR_IN_PROGRESS)); 5131 if (err) { 5132 spin_unlock_irq(¶ms->atqbal_wq.lock); 5133 return err; 5134 } 5135 5136 wr32(hw, REG_LL_PROXY_L, adj); 5137 val = FIELD_PREP(REG_LL_PROXY_H_PHY_TMR_CMD_M, REG_LL_PROXY_H_PHY_TMR_CMD_ADJ) | 5138 FIELD_PREP(REG_LL_PROXY_H_PHY_TMR_IDX_M, tmr_idx) | REG_LL_PROXY_H_EXEC; 5139 wr32(hw, REG_LL_PROXY_H, val); 5140 5141 /* Read the register repeatedly until the FW indicates completion */ 5142 err = read_poll_timeout_atomic(rd32, val, 5143 !FIELD_GET(REG_LL_PROXY_H_EXEC, val), 5144 10, REG_LL_PROXY_H_TIMEOUT_US, false, hw, 5145 REG_LL_PROXY_H); 5146 if (err) { 5147 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY timer adjustment using low latency interface\n"); 5148 spin_unlock_irq(¶ms->atqbal_wq.lock); 5149 return err; 5150 } 5151 5152 spin_unlock_irq(¶ms->atqbal_wq.lock); 5153 5154 return 0; 5155 } 5156 5157 /** 5158 * ice_ptp_prep_phy_adj_e810 - Prep PHY port for a time adjustment 5159 * @hw: pointer to HW struct 5160 * @adj: adjustment value to program 5161 * 5162 * Prepare the PHY port for an atomic adjustment by programming the PHY 5163 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual adjustment 5164 * is completed by issuing an ICE_PTP_ADJ_TIME sync command. 5165 * 5166 * The adjustment value only contains the portion used for the upper 32bits of 5167 * the PHY timer, usually in units of nominal nanoseconds. Negative 5168 * adjustments are supported using 2s complement arithmetic. 5169 */ 5170 static int ice_ptp_prep_phy_adj_e810(struct ice_hw *hw, s32 adj) 5171 { 5172 u8 tmr_idx; 5173 int err; 5174 5175 if (hw->dev_caps.ts_dev_info.ll_phy_tmr_update) 5176 return ice_ptp_prep_phy_adj_ll_e810(hw, adj); 5177 5178 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5179 5180 /* Adjustments are represented as signed 2's complement values in 5181 * nanoseconds. Sub-nanosecond adjustment is not supported. 5182 */ 5183 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), 0); 5184 if (err) { 5185 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_L, err %d\n", 5186 err); 5187 return err; 5188 } 5189 5190 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), adj); 5191 if (err) { 5192 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_H, err %d\n", 5193 err); 5194 return err; 5195 } 5196 5197 return 0; 5198 } 5199 5200 /** 5201 * ice_ptp_prep_phy_incval_ll_e810 - Prep PHY ports increment value change 5202 * @hw: pointer to HW struct 5203 * @incval: The new 40bit increment value to prepare 5204 * 5205 * Use the low latency firmware interface to program PHY time increment value 5206 * for all PHY ports. 5207 * 5208 * Return: 0 on success, -EBUSY on timeout 5209 */ 5210 static int ice_ptp_prep_phy_incval_ll_e810(struct ice_hw *hw, u64 incval) 5211 { 5212 const u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5213 struct ice_e810_params *params = &hw->ptp.phy.e810; 5214 u32 val; 5215 int err; 5216 5217 spin_lock_irq(¶ms->atqbal_wq.lock); 5218 5219 /* Wait for any pending in-progress low latency interrupt */ 5220 err = wait_event_interruptible_locked_irq(params->atqbal_wq, 5221 !(params->atqbal_flags & 5222 ATQBAL_FLAGS_INTR_IN_PROGRESS)); 5223 if (err) { 5224 spin_unlock_irq(¶ms->atqbal_wq.lock); 5225 return err; 5226 } 5227 5228 wr32(hw, REG_LL_PROXY_L, lower_32_bits(incval)); 5229 val = FIELD_PREP(REG_LL_PROXY_H_PHY_TMR_CMD_M, REG_LL_PROXY_H_PHY_TMR_CMD_FREQ) | 5230 FIELD_PREP(REG_LL_PROXY_H_TS_HIGH, (u8)upper_32_bits(incval)) | 5231 FIELD_PREP(REG_LL_PROXY_H_PHY_TMR_IDX_M, tmr_idx) | REG_LL_PROXY_H_EXEC; 5232 wr32(hw, REG_LL_PROXY_H, val); 5233 5234 /* Read the register repeatedly until the FW indicates completion */ 5235 err = read_poll_timeout_atomic(rd32, val, 5236 !FIELD_GET(REG_LL_PROXY_H_EXEC, val), 5237 10, REG_LL_PROXY_H_TIMEOUT_US, false, hw, 5238 REG_LL_PROXY_H); 5239 if (err) { 5240 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY timer increment using low latency interface\n"); 5241 spin_unlock_irq(¶ms->atqbal_wq.lock); 5242 return err; 5243 } 5244 5245 spin_unlock_irq(¶ms->atqbal_wq.lock); 5246 5247 return 0; 5248 } 5249 5250 /** 5251 * ice_ptp_prep_phy_incval_e810 - Prep PHY port increment value change 5252 * @hw: pointer to HW struct 5253 * @incval: The new 40bit increment value to prepare 5254 * 5255 * Prepare the PHY port for a new increment value by programming the PHY 5256 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual change is 5257 * completed by issuing an ICE_PTP_INIT_INCVAL command. 5258 */ 5259 static int ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval) 5260 { 5261 u32 high, low; 5262 u8 tmr_idx; 5263 int err; 5264 5265 if (hw->dev_caps.ts_dev_info.ll_phy_tmr_update) 5266 return ice_ptp_prep_phy_incval_ll_e810(hw, incval); 5267 5268 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5269 low = lower_32_bits(incval); 5270 high = upper_32_bits(incval); 5271 5272 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), low); 5273 if (err) { 5274 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval to PHY SHADJ_L, err %d\n", 5275 err); 5276 return err; 5277 } 5278 5279 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), high); 5280 if (err) { 5281 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval PHY SHADJ_H, err %d\n", 5282 err); 5283 return err; 5284 } 5285 5286 return 0; 5287 } 5288 5289 /** 5290 * ice_ptp_port_cmd_e810 - Prepare all external PHYs for a timer command 5291 * @hw: pointer to HW struct 5292 * @cmd: Command to be sent to the port 5293 * 5294 * Prepare the external PHYs connected to this device for a timer sync 5295 * command. 5296 */ 5297 static int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 5298 { 5299 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 5300 5301 return ice_write_phy_reg_e810(hw, E810_ETH_GLTSYN_CMD, val); 5302 } 5303 5304 /** 5305 * ice_get_phy_tx_tstamp_ready_e810 - Read Tx memory status register 5306 * @hw: pointer to the HW struct 5307 * @port: the PHY port to read 5308 * @tstamp_ready: contents of the Tx memory status register 5309 * 5310 * E810 devices do not use a Tx memory status register. Instead simply 5311 * indicate that all timestamps are currently ready. 5312 */ 5313 static int 5314 ice_get_phy_tx_tstamp_ready_e810(struct ice_hw *hw, u8 port, u64 *tstamp_ready) 5315 { 5316 *tstamp_ready = 0xFFFFFFFFFFFFFFFF; 5317 return 0; 5318 } 5319 5320 /* E810 SMA functions 5321 * 5322 * The following functions operate specifically on E810 hardware and are used 5323 * to access the extended GPIOs available. 5324 */ 5325 5326 /** 5327 * ice_read_sma_ctrl 5328 * @hw: pointer to the hw struct 5329 * @data: pointer to data to be read from the GPIO controller 5330 * 5331 * Read the SMA controller state. It is connected to pins 3-7 of Port 1 of the 5332 * PCA9575 expander, so only bits 3-7 in data are valid. 5333 */ 5334 int ice_read_sma_ctrl(struct ice_hw *hw, u8 *data) 5335 { 5336 int status; 5337 u16 handle; 5338 u8 i; 5339 5340 status = ice_get_pca9575_handle(hw, &handle); 5341 if (status) 5342 return status; 5343 5344 *data = 0; 5345 5346 for (i = ICE_SMA_MIN_BIT; i <= ICE_SMA_MAX_BIT; i++) { 5347 bool pin; 5348 5349 status = ice_aq_get_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET, 5350 &pin, NULL); 5351 if (status) 5352 break; 5353 *data |= (u8)(!pin) << i; 5354 } 5355 5356 return status; 5357 } 5358 5359 /** 5360 * ice_write_sma_ctrl 5361 * @hw: pointer to the hw struct 5362 * @data: data to be written to the GPIO controller 5363 * 5364 * Write the data to the SMA controller. It is connected to pins 3-7 of Port 1 5365 * of the PCA9575 expander, so only bits 3-7 in data are valid. 5366 */ 5367 int ice_write_sma_ctrl(struct ice_hw *hw, u8 data) 5368 { 5369 int status; 5370 u16 handle; 5371 u8 i; 5372 5373 status = ice_get_pca9575_handle(hw, &handle); 5374 if (status) 5375 return status; 5376 5377 for (i = ICE_SMA_MIN_BIT; i <= ICE_SMA_MAX_BIT; i++) { 5378 bool pin; 5379 5380 pin = !(data & (1 << i)); 5381 status = ice_aq_set_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET, 5382 pin, NULL); 5383 if (status) 5384 break; 5385 } 5386 5387 return status; 5388 } 5389 5390 /** 5391 * ice_ptp_read_sdp_ac - read SDP available connections section from NVM 5392 * @hw: pointer to the HW struct 5393 * @entries: returns the SDP available connections section from NVM 5394 * @num_entries: returns the number of valid entries 5395 * 5396 * Return: 0 on success, negative error code if NVM read failed or section does 5397 * not exist or is corrupted 5398 */ 5399 int ice_ptp_read_sdp_ac(struct ice_hw *hw, __le16 *entries, uint *num_entries) 5400 { 5401 __le16 data; 5402 u32 offset; 5403 int err; 5404 5405 err = ice_acquire_nvm(hw, ICE_RES_READ); 5406 if (err) 5407 goto exit; 5408 5409 /* Read the offset of SDP_AC */ 5410 offset = ICE_AQC_NVM_SDP_AC_PTR_OFFSET; 5411 err = ice_aq_read_nvm(hw, 0, offset, sizeof(data), &data, false, true, 5412 NULL); 5413 if (err) 5414 goto exit; 5415 5416 /* Check if section exist */ 5417 offset = FIELD_GET(ICE_AQC_NVM_SDP_AC_PTR_M, le16_to_cpu(data)); 5418 if (offset == ICE_AQC_NVM_SDP_AC_PTR_INVAL) { 5419 err = -EINVAL; 5420 goto exit; 5421 } 5422 5423 if (offset & ICE_AQC_NVM_SDP_AC_PTR_TYPE_M) { 5424 offset &= ICE_AQC_NVM_SDP_AC_PTR_M; 5425 offset *= ICE_AQC_NVM_SECTOR_UNIT; 5426 } else { 5427 offset *= sizeof(data); 5428 } 5429 5430 /* Skip reading section length and read the number of valid entries */ 5431 offset += sizeof(data); 5432 err = ice_aq_read_nvm(hw, 0, offset, sizeof(data), &data, false, true, 5433 NULL); 5434 if (err) 5435 goto exit; 5436 *num_entries = le16_to_cpu(data); 5437 5438 /* Read SDP configuration section */ 5439 offset += sizeof(data); 5440 err = ice_aq_read_nvm(hw, 0, offset, *num_entries * sizeof(data), 5441 entries, false, true, NULL); 5442 5443 exit: 5444 if (err) 5445 dev_dbg(ice_hw_to_dev(hw), "Failed to configure SDP connection section\n"); 5446 ice_release_nvm(hw); 5447 return err; 5448 } 5449 5450 /** 5451 * ice_ptp_init_phy_e810 - initialize PHY parameters 5452 * @ptp: pointer to the PTP HW struct 5453 */ 5454 static void ice_ptp_init_phy_e810(struct ice_ptp_hw *ptp) 5455 { 5456 ptp->num_lports = 8; 5457 ptp->ports_per_phy = 4; 5458 5459 init_waitqueue_head(&ptp->phy.e810.atqbal_wq); 5460 } 5461 5462 /* E830 functions 5463 * 5464 * The following functions operate on the E830 series devices. 5465 * 5466 */ 5467 5468 /** 5469 * ice_ptp_init_phc_e830 - Perform E830 specific PHC initialization 5470 * @hw: pointer to HW struct 5471 * 5472 * Perform E830-specific PTP hardware clock initialization steps. 5473 */ 5474 static void ice_ptp_init_phc_e830(const struct ice_hw *hw) 5475 { 5476 ice_ptp_cfg_sync_delay(hw, ICE_E810_E830_SYNC_DELAY); 5477 } 5478 5479 /** 5480 * ice_ptp_write_direct_incval_e830 - Prep PHY port increment value change 5481 * @hw: pointer to HW struct 5482 * @incval: The new 40bit increment value to prepare 5483 * 5484 * Prepare the PHY port for a new increment value by programming the PHC 5485 * GLTSYN_INCVAL_L and GLTSYN_INCVAL_H registers. The actual change is 5486 * completed by FW automatically. 5487 */ 5488 static void ice_ptp_write_direct_incval_e830(const struct ice_hw *hw, 5489 u64 incval) 5490 { 5491 u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5492 5493 wr32(hw, GLTSYN_INCVAL_L(tmr_idx), lower_32_bits(incval)); 5494 wr32(hw, GLTSYN_INCVAL_H(tmr_idx), upper_32_bits(incval)); 5495 } 5496 5497 /** 5498 * ice_ptp_write_direct_phc_time_e830 - Prepare PHY port with initial time 5499 * @hw: Board private structure 5500 * @time: Time to initialize the PHY port clock to 5501 * 5502 * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the 5503 * initial clock time. The time will not actually be programmed until the 5504 * driver issues an ICE_PTP_INIT_TIME command. 5505 * 5506 * The time value is the upper 32 bits of the PHY timer, usually in units of 5507 * nominal nanoseconds. 5508 */ 5509 static void ice_ptp_write_direct_phc_time_e830(const struct ice_hw *hw, 5510 u64 time) 5511 { 5512 u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5513 5514 wr32(hw, GLTSYN_TIME_0(tmr_idx), 0); 5515 wr32(hw, GLTSYN_TIME_L(tmr_idx), lower_32_bits(time)); 5516 wr32(hw, GLTSYN_TIME_H(tmr_idx), upper_32_bits(time)); 5517 } 5518 5519 /** 5520 * ice_ptp_port_cmd_e830 - Prepare all external PHYs for a timer command 5521 * @hw: pointer to HW struct 5522 * @cmd: Command to be sent to the port 5523 * 5524 * Prepare the external PHYs connected to this device for a timer sync 5525 * command. 5526 * 5527 * Return: 0 on success, negative error code when PHY write failed 5528 */ 5529 static int ice_ptp_port_cmd_e830(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 5530 { 5531 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 5532 5533 return ice_write_phy_reg_e810(hw, E830_ETH_GLTSYN_CMD, val); 5534 } 5535 5536 /** 5537 * ice_read_phy_tstamp_e830 - Read a PHY timestamp out of the external PHY 5538 * @hw: pointer to the HW struct 5539 * @idx: the timestamp index to read 5540 * @tstamp: on return, the 40bit timestamp value 5541 * 5542 * Read a 40bit timestamp value out of the timestamp block of the external PHY 5543 * on the E830 device. 5544 */ 5545 static void ice_read_phy_tstamp_e830(const struct ice_hw *hw, u8 idx, 5546 u64 *tstamp) 5547 { 5548 u32 hi, lo; 5549 5550 hi = rd32(hw, E830_PRTTSYN_TXTIME_H(idx)); 5551 lo = rd32(hw, E830_PRTTSYN_TXTIME_L(idx)); 5552 5553 /* For E830 devices, the timestamp is reported with the lower 32 bits 5554 * in the low register, and the upper 8 bits in the high register. 5555 */ 5556 *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) | 5557 FIELD_PREP(PHY_EXT_40B_LOW_M, lo); 5558 } 5559 5560 /** 5561 * ice_get_phy_tx_tstamp_ready_e830 - Read Tx memory status register 5562 * @hw: pointer to the HW struct 5563 * @port: the PHY port to read 5564 * @tstamp_ready: contents of the Tx memory status register 5565 */ 5566 static void ice_get_phy_tx_tstamp_ready_e830(const struct ice_hw *hw, u8 port, 5567 u64 *tstamp_ready) 5568 { 5569 *tstamp_ready = rd32(hw, E830_PRTMAC_TS_TX_MEM_VALID_H); 5570 *tstamp_ready <<= 32; 5571 *tstamp_ready |= rd32(hw, E830_PRTMAC_TS_TX_MEM_VALID_L); 5572 } 5573 5574 /** 5575 * ice_ptp_init_phy_e830 - initialize PHY parameters 5576 * @ptp: pointer to the PTP HW struct 5577 */ 5578 static void ice_ptp_init_phy_e830(struct ice_ptp_hw *ptp) 5579 { 5580 ptp->num_lports = 8; 5581 ptp->ports_per_phy = 4; 5582 } 5583 5584 /* Device agnostic functions 5585 * 5586 * The following functions implement shared behavior common to all devices, 5587 * possibly calling a device specific implementation where necessary. 5588 */ 5589 5590 /** 5591 * ice_ptp_lock - Acquire PTP global semaphore register lock 5592 * @hw: pointer to the HW struct 5593 * 5594 * Acquire the global PTP hardware semaphore lock. Returns true if the lock 5595 * was acquired, false otherwise. 5596 * 5597 * The PFTSYN_SEM register sets the busy bit on read, returning the previous 5598 * value. If software sees the busy bit cleared, this means that this function 5599 * acquired the lock (and the busy bit is now set). If software sees the busy 5600 * bit set, it means that another function acquired the lock. 5601 * 5602 * Software must clear the busy bit with a write to release the lock for other 5603 * functions when done. 5604 */ 5605 bool ice_ptp_lock(struct ice_hw *hw) 5606 { 5607 u32 hw_lock; 5608 int i; 5609 5610 #define MAX_TRIES 15 5611 5612 for (i = 0; i < MAX_TRIES; i++) { 5613 hw_lock = rd32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id)); 5614 hw_lock = hw_lock & PFTSYN_SEM_BUSY_M; 5615 if (hw_lock) { 5616 /* Somebody is holding the lock */ 5617 usleep_range(5000, 6000); 5618 continue; 5619 } 5620 5621 break; 5622 } 5623 5624 return !hw_lock; 5625 } 5626 5627 /** 5628 * ice_ptp_unlock - Release PTP global semaphore register lock 5629 * @hw: pointer to the HW struct 5630 * 5631 * Release the global PTP hardware semaphore lock. This is done by writing to 5632 * the PFTSYN_SEM register. 5633 */ 5634 void ice_ptp_unlock(struct ice_hw *hw) 5635 { 5636 wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0); 5637 } 5638 5639 /** 5640 * ice_ptp_init_hw - Initialize hw based on device type 5641 * @hw: pointer to the HW structure 5642 * 5643 * Determine the PHY model for the device, and initialize hw 5644 * for use by other functions. 5645 */ 5646 void ice_ptp_init_hw(struct ice_hw *hw) 5647 { 5648 struct ice_ptp_hw *ptp = &hw->ptp; 5649 5650 switch (hw->mac_type) { 5651 case ICE_MAC_E810: 5652 ice_ptp_init_phy_e810(ptp); 5653 break; 5654 case ICE_MAC_E830: 5655 ice_ptp_init_phy_e830(ptp); 5656 break; 5657 case ICE_MAC_GENERIC: 5658 ice_ptp_init_phy_e82x(ptp); 5659 break; 5660 case ICE_MAC_GENERIC_3K_E825: 5661 ice_ptp_init_phy_e825(hw); 5662 break; 5663 default: 5664 return; 5665 } 5666 } 5667 5668 /** 5669 * ice_ptp_write_port_cmd - Prepare a single PHY port for a timer command 5670 * @hw: pointer to HW struct 5671 * @port: Port to which cmd has to be sent 5672 * @cmd: Command to be sent to the port 5673 * 5674 * Prepare one port for the upcoming timer sync command. Do not use this for 5675 * programming only a single port, instead use ice_ptp_one_port_cmd() to 5676 * ensure non-modified ports get properly initialized to ICE_PTP_NOP. 5677 * 5678 * Return: 5679 * * %0 - success 5680 * %-EBUSY - PHY type not supported 5681 * * %other - failed to write port command 5682 */ 5683 static int ice_ptp_write_port_cmd(struct ice_hw *hw, u8 port, 5684 enum ice_ptp_tmr_cmd cmd) 5685 { 5686 switch (hw->mac_type) { 5687 case ICE_MAC_GENERIC: 5688 return ice_ptp_write_port_cmd_e82x(hw, port, cmd); 5689 case ICE_MAC_GENERIC_3K_E825: 5690 return ice_ptp_write_port_cmd_eth56g(hw, port, cmd); 5691 default: 5692 return -EOPNOTSUPP; 5693 } 5694 } 5695 5696 /** 5697 * ice_ptp_one_port_cmd - Program one PHY port for a timer command 5698 * @hw: pointer to HW struct 5699 * @configured_port: the port that should execute the command 5700 * @configured_cmd: the command to be executed on the configured port 5701 * 5702 * Prepare one port for executing a timer command, while preparing all other 5703 * ports to ICE_PTP_NOP. This allows executing a command on a single port 5704 * while ensuring all other ports do not execute stale commands. 5705 * 5706 * Return: 5707 * * %0 - success 5708 * * %other - failed to write port command 5709 */ 5710 int ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port, 5711 enum ice_ptp_tmr_cmd configured_cmd) 5712 { 5713 u32 port; 5714 5715 for (port = 0; port < hw->ptp.num_lports; port++) { 5716 int err; 5717 5718 /* Program the configured port with the configured command, 5719 * program all other ports with ICE_PTP_NOP. 5720 */ 5721 if (port == configured_port) 5722 err = ice_ptp_write_port_cmd(hw, port, configured_cmd); 5723 else 5724 err = ice_ptp_write_port_cmd(hw, port, ICE_PTP_NOP); 5725 5726 if (err) 5727 return err; 5728 } 5729 5730 return 0; 5731 } 5732 5733 /** 5734 * ice_ptp_port_cmd - Prepare PHY ports for a timer sync command 5735 * @hw: pointer to HW struct 5736 * @cmd: the timer command to setup 5737 * 5738 * Prepare all PHY ports on this device for the requested timer command. For 5739 * some families this can be done in one shot, but for other families each 5740 * port must be configured individually. 5741 * 5742 * Return: 5743 * * %0 - success 5744 * * %other - failed to write port command 5745 */ 5746 static int ice_ptp_port_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 5747 { 5748 u32 port; 5749 5750 /* PHY models which can program all ports simultaneously */ 5751 switch (hw->mac_type) { 5752 case ICE_MAC_E810: 5753 return ice_ptp_port_cmd_e810(hw, cmd); 5754 case ICE_MAC_E830: 5755 return ice_ptp_port_cmd_e830(hw, cmd); 5756 default: 5757 break; 5758 } 5759 5760 /* PHY models which require programming each port separately */ 5761 for (port = 0; port < hw->ptp.num_lports; port++) { 5762 int err; 5763 5764 err = ice_ptp_write_port_cmd(hw, port, cmd); 5765 if (err) 5766 return err; 5767 } 5768 5769 return 0; 5770 } 5771 5772 /** 5773 * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command 5774 * @hw: pointer to HW struct 5775 * @cmd: the command to issue 5776 * 5777 * Prepare the source timer and PHY timers and then trigger the requested 5778 * command. This causes the shadow registers previously written in preparation 5779 * for the command to be synchronously applied to both the source and PHY 5780 * timers. 5781 */ 5782 static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 5783 { 5784 int err; 5785 5786 /* First, prepare the source timer */ 5787 ice_ptp_src_cmd(hw, cmd); 5788 5789 /* Next, prepare the ports */ 5790 err = ice_ptp_port_cmd(hw, cmd); 5791 if (err) { 5792 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for timer command %u, err %d\n", 5793 cmd, err); 5794 return err; 5795 } 5796 5797 /* Write the sync command register to drive both source and PHY timer 5798 * commands synchronously 5799 */ 5800 ice_ptp_exec_tmr_cmd(hw); 5801 5802 return 0; 5803 } 5804 5805 /** 5806 * ice_ptp_init_time - Initialize device time to provided value 5807 * @hw: pointer to HW struct 5808 * @time: 64bits of time (GLTSYN_TIME_L and GLTSYN_TIME_H) 5809 * 5810 * Initialize the device to the specified time provided. This requires a three 5811 * step process: 5812 * 5813 * 1) write the new init time to the source timer shadow registers 5814 * 2) write the new init time to the PHY timer shadow registers 5815 * 3) issue an init_time timer command to synchronously switch both the source 5816 * and port timers to the new init time value at the next clock cycle. 5817 */ 5818 int ice_ptp_init_time(struct ice_hw *hw, u64 time) 5819 { 5820 u8 tmr_idx; 5821 int err; 5822 5823 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5824 5825 /* Source timers */ 5826 /* For E830 we don't need to use shadow registers, its automatic */ 5827 if (hw->mac_type == ICE_MAC_E830) { 5828 ice_ptp_write_direct_phc_time_e830(hw, time); 5829 return 0; 5830 } 5831 5832 wr32(hw, GLTSYN_SHTIME_L(tmr_idx), lower_32_bits(time)); 5833 wr32(hw, GLTSYN_SHTIME_H(tmr_idx), upper_32_bits(time)); 5834 wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0); 5835 5836 /* PHY timers */ 5837 /* Fill Rx and Tx ports and send msg to PHY */ 5838 switch (hw->mac_type) { 5839 case ICE_MAC_E810: 5840 err = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF); 5841 break; 5842 case ICE_MAC_GENERIC: 5843 err = ice_ptp_prep_phy_time_e82x(hw, time & 0xFFFFFFFF); 5844 break; 5845 case ICE_MAC_GENERIC_3K_E825: 5846 err = ice_ptp_prep_phy_time_eth56g(hw, 5847 (u32)(time & 0xFFFFFFFF)); 5848 break; 5849 default: 5850 err = -EOPNOTSUPP; 5851 } 5852 5853 if (err) 5854 return err; 5855 5856 return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_TIME); 5857 } 5858 5859 /** 5860 * ice_ptp_write_incval - Program PHC with new increment value 5861 * @hw: pointer to HW struct 5862 * @incval: Source timer increment value per clock cycle 5863 * 5864 * Program the PHC with a new increment value. This requires a three-step 5865 * process: 5866 * 5867 * 1) Write the increment value to the source timer shadow registers 5868 * 2) Write the increment value to the PHY timer shadow registers 5869 * 3) Issue an ICE_PTP_INIT_INCVAL timer command to synchronously switch both 5870 * the source and port timers to the new increment value at the next clock 5871 * cycle. 5872 */ 5873 int ice_ptp_write_incval(struct ice_hw *hw, u64 incval) 5874 { 5875 u8 tmr_idx; 5876 int err; 5877 5878 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5879 5880 /* For E830 we don't need to use shadow registers, its automatic */ 5881 if (hw->mac_type == ICE_MAC_E830) { 5882 ice_ptp_write_direct_incval_e830(hw, incval); 5883 return 0; 5884 } 5885 5886 /* Shadow Adjust */ 5887 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), lower_32_bits(incval)); 5888 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), upper_32_bits(incval)); 5889 5890 switch (hw->mac_type) { 5891 case ICE_MAC_E810: 5892 err = ice_ptp_prep_phy_incval_e810(hw, incval); 5893 break; 5894 case ICE_MAC_GENERIC: 5895 err = ice_ptp_prep_phy_incval_e82x(hw, incval); 5896 break; 5897 case ICE_MAC_GENERIC_3K_E825: 5898 err = ice_ptp_prep_phy_incval_eth56g(hw, incval); 5899 break; 5900 default: 5901 err = -EOPNOTSUPP; 5902 } 5903 5904 if (err) 5905 return err; 5906 5907 return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_INCVAL); 5908 } 5909 5910 /** 5911 * ice_ptp_write_incval_locked - Program new incval while holding semaphore 5912 * @hw: pointer to HW struct 5913 * @incval: Source timer increment value per clock cycle 5914 * 5915 * Program a new PHC incval while holding the PTP semaphore. 5916 */ 5917 int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval) 5918 { 5919 int err; 5920 5921 if (!ice_ptp_lock(hw)) 5922 return -EBUSY; 5923 5924 err = ice_ptp_write_incval(hw, incval); 5925 5926 ice_ptp_unlock(hw); 5927 5928 return err; 5929 } 5930 5931 /** 5932 * ice_ptp_adj_clock - Adjust PHC clock time atomically 5933 * @hw: pointer to HW struct 5934 * @adj: Adjustment in nanoseconds 5935 * 5936 * Perform an atomic adjustment of the PHC time by the specified number of 5937 * nanoseconds. This requires a three-step process: 5938 * 5939 * 1) Write the adjustment to the source timer shadow registers 5940 * 2) Write the adjustment to the PHY timer shadow registers 5941 * 3) Issue an ICE_PTP_ADJ_TIME timer command to synchronously apply the 5942 * adjustment to both the source and port timers at the next clock cycle. 5943 */ 5944 int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj) 5945 { 5946 u8 tmr_idx; 5947 int err; 5948 5949 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5950 5951 /* Write the desired clock adjustment into the GLTSYN_SHADJ register. 5952 * For an ICE_PTP_ADJ_TIME command, this set of registers represents 5953 * the value to add to the clock time. It supports subtraction by 5954 * interpreting the value as a 2's complement integer. 5955 */ 5956 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0); 5957 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj); 5958 5959 switch (hw->mac_type) { 5960 case ICE_MAC_E810: 5961 err = ice_ptp_prep_phy_adj_e810(hw, adj); 5962 break; 5963 case ICE_MAC_E830: 5964 /* E830 sync PHYs automatically after setting GLTSYN_SHADJ */ 5965 return 0; 5966 case ICE_MAC_GENERIC: 5967 err = ice_ptp_prep_phy_adj_e82x(hw, adj); 5968 break; 5969 case ICE_MAC_GENERIC_3K_E825: 5970 err = ice_ptp_prep_phy_adj_eth56g(hw, adj); 5971 break; 5972 default: 5973 err = -EOPNOTSUPP; 5974 } 5975 5976 if (err) 5977 return err; 5978 5979 return ice_ptp_tmr_cmd(hw, ICE_PTP_ADJ_TIME); 5980 } 5981 5982 /** 5983 * ice_read_phy_tstamp - Read a PHY timestamp from the timestamo block 5984 * @hw: pointer to the HW struct 5985 * @block: the block to read from 5986 * @idx: the timestamp index to read 5987 * @tstamp: on return, the 40bit timestamp value 5988 * 5989 * Read a 40bit timestamp value out of the timestamp block. For E822 devices, 5990 * the block is the quad to read from. For E810 devices, the block is the 5991 * logical port to read from. 5992 */ 5993 int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp) 5994 { 5995 switch (hw->mac_type) { 5996 case ICE_MAC_E810: 5997 return ice_read_phy_tstamp_e810(hw, block, idx, tstamp); 5998 case ICE_MAC_E830: 5999 ice_read_phy_tstamp_e830(hw, idx, tstamp); 6000 return 0; 6001 case ICE_MAC_GENERIC: 6002 return ice_read_phy_tstamp_e82x(hw, block, idx, tstamp); 6003 case ICE_MAC_GENERIC_3K_E825: 6004 return ice_read_ptp_tstamp_eth56g(hw, block, idx, tstamp); 6005 default: 6006 return -EOPNOTSUPP; 6007 } 6008 } 6009 6010 /** 6011 * ice_clear_phy_tstamp - Clear a timestamp from the timestamp block 6012 * @hw: pointer to the HW struct 6013 * @block: the block to read from 6014 * @idx: the timestamp index to reset 6015 * 6016 * Clear a timestamp from the timestamp block, discarding its value without 6017 * returning it. This resets the memory status bit for the timestamp index 6018 * allowing it to be reused for another timestamp in the future. 6019 * 6020 * For E822 devices, the block number is the PHY quad to clear from. For E810 6021 * devices, the block number is the logical port to clear from. 6022 * 6023 * This function must only be called on a timestamp index whose valid bit is 6024 * set according to ice_get_phy_tx_tstamp_ready(). 6025 */ 6026 int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx) 6027 { 6028 switch (hw->mac_type) { 6029 case ICE_MAC_E810: 6030 return ice_clear_phy_tstamp_e810(hw, block, idx); 6031 case ICE_MAC_GENERIC: 6032 return ice_clear_phy_tstamp_e82x(hw, block, idx); 6033 case ICE_MAC_GENERIC_3K_E825: 6034 return ice_clear_ptp_tstamp_eth56g(hw, block, idx); 6035 default: 6036 return -EOPNOTSUPP; 6037 } 6038 } 6039 6040 /** 6041 * ice_get_pf_c827_idx - find and return the C827 index for the current pf 6042 * @hw: pointer to the hw struct 6043 * @idx: index of the found C827 PHY 6044 * Return: 6045 * * 0 - success 6046 * * negative - failure 6047 */ 6048 static int ice_get_pf_c827_idx(struct ice_hw *hw, u8 *idx) 6049 { 6050 struct ice_aqc_get_link_topo cmd; 6051 u8 node_part_number; 6052 u16 node_handle; 6053 int status; 6054 u8 ctx; 6055 6056 if (hw->mac_type != ICE_MAC_E810) 6057 return -ENODEV; 6058 6059 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) { 6060 *idx = C827_0; 6061 return 0; 6062 } 6063 6064 memset(&cmd, 0, sizeof(cmd)); 6065 6066 ctx = ICE_AQC_LINK_TOPO_NODE_TYPE_PHY << ICE_AQC_LINK_TOPO_NODE_TYPE_S; 6067 ctx |= ICE_AQC_LINK_TOPO_NODE_CTX_PORT << ICE_AQC_LINK_TOPO_NODE_CTX_S; 6068 cmd.addr.topo_params.node_type_ctx = ctx; 6069 6070 status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number, 6071 &node_handle); 6072 if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827) 6073 return -ENOENT; 6074 6075 if (node_handle == E810C_QSFP_C827_0_HANDLE) 6076 *idx = C827_0; 6077 else if (node_handle == E810C_QSFP_C827_1_HANDLE) 6078 *idx = C827_1; 6079 else 6080 return -EIO; 6081 6082 return 0; 6083 } 6084 6085 /** 6086 * ice_ptp_reset_ts_memory - Reset timestamp memory for all blocks 6087 * @hw: pointer to the HW struct 6088 */ 6089 void ice_ptp_reset_ts_memory(struct ice_hw *hw) 6090 { 6091 switch (hw->mac_type) { 6092 case ICE_MAC_GENERIC: 6093 ice_ptp_reset_ts_memory_e82x(hw); 6094 break; 6095 case ICE_MAC_GENERIC_3K_E825: 6096 ice_ptp_reset_ts_memory_eth56g(hw); 6097 break; 6098 case ICE_MAC_E810: 6099 default: 6100 return; 6101 } 6102 } 6103 6104 /** 6105 * ice_ptp_init_phc - Initialize PTP hardware clock 6106 * @hw: pointer to the HW struct 6107 * 6108 * Perform the steps required to initialize the PTP hardware clock. 6109 */ 6110 int ice_ptp_init_phc(struct ice_hw *hw) 6111 { 6112 u8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned; 6113 6114 /* Enable source clocks */ 6115 wr32(hw, GLTSYN_ENA(src_idx), GLTSYN_ENA_TSYN_ENA_M); 6116 6117 /* Clear event err indications for auxiliary pins */ 6118 (void)rd32(hw, GLTSYN_STAT(src_idx)); 6119 6120 switch (hw->mac_type) { 6121 case ICE_MAC_E810: 6122 return ice_ptp_init_phc_e810(hw); 6123 case ICE_MAC_E830: 6124 ice_ptp_init_phc_e830(hw); 6125 return 0; 6126 case ICE_MAC_GENERIC: 6127 return ice_ptp_init_phc_e82x(hw); 6128 case ICE_MAC_GENERIC_3K_E825: 6129 return ice_ptp_init_phc_e825(hw); 6130 default: 6131 return -EOPNOTSUPP; 6132 } 6133 } 6134 6135 /** 6136 * ice_get_phy_tx_tstamp_ready - Read PHY Tx memory status indication 6137 * @hw: pointer to the HW struct 6138 * @block: the timestamp block to check 6139 * @tstamp_ready: storage for the PHY Tx memory status information 6140 * 6141 * Check the PHY for Tx timestamp memory status. This reports a 64 bit value 6142 * which indicates which timestamps in the block may be captured. A set bit 6143 * means the timestamp can be read. An unset bit means the timestamp is not 6144 * ready and software should avoid reading the register. 6145 */ 6146 int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready) 6147 { 6148 switch (hw->mac_type) { 6149 case ICE_MAC_E810: 6150 return ice_get_phy_tx_tstamp_ready_e810(hw, block, 6151 tstamp_ready); 6152 case ICE_MAC_E830: 6153 ice_get_phy_tx_tstamp_ready_e830(hw, block, tstamp_ready); 6154 return 0; 6155 case ICE_MAC_GENERIC: 6156 return ice_get_phy_tx_tstamp_ready_e82x(hw, block, 6157 tstamp_ready); 6158 case ICE_MAC_GENERIC_3K_E825: 6159 return ice_get_phy_tx_tstamp_ready_eth56g(hw, block, 6160 tstamp_ready); 6161 default: 6162 return -EOPNOTSUPP; 6163 } 6164 } 6165 6166 /** 6167 * ice_cgu_get_pin_desc_e823 - get pin description array 6168 * @hw: pointer to the hw struct 6169 * @input: if request is done against input or output pin 6170 * @size: number of inputs/outputs 6171 * 6172 * Return: pointer to pin description array associated to given hw. 6173 */ 6174 static const struct ice_cgu_pin_desc * 6175 ice_cgu_get_pin_desc_e823(struct ice_hw *hw, bool input, int *size) 6176 { 6177 static const struct ice_cgu_pin_desc *t; 6178 6179 if (hw->cgu_part_number == 6180 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032) { 6181 if (input) { 6182 t = ice_e823_zl_cgu_inputs; 6183 *size = ARRAY_SIZE(ice_e823_zl_cgu_inputs); 6184 } else { 6185 t = ice_e823_zl_cgu_outputs; 6186 *size = ARRAY_SIZE(ice_e823_zl_cgu_outputs); 6187 } 6188 } else if (hw->cgu_part_number == 6189 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384) { 6190 if (input) { 6191 t = ice_e823_si_cgu_inputs; 6192 *size = ARRAY_SIZE(ice_e823_si_cgu_inputs); 6193 } else { 6194 t = ice_e823_si_cgu_outputs; 6195 *size = ARRAY_SIZE(ice_e823_si_cgu_outputs); 6196 } 6197 } else { 6198 t = NULL; 6199 *size = 0; 6200 } 6201 6202 return t; 6203 } 6204 6205 /** 6206 * ice_cgu_get_pin_desc - get pin description array 6207 * @hw: pointer to the hw struct 6208 * @input: if request is done against input or output pins 6209 * @size: size of array returned by function 6210 * 6211 * Return: pointer to pin description array associated to given hw. 6212 */ 6213 static const struct ice_cgu_pin_desc * 6214 ice_cgu_get_pin_desc(struct ice_hw *hw, bool input, int *size) 6215 { 6216 const struct ice_cgu_pin_desc *t = NULL; 6217 6218 switch (hw->device_id) { 6219 case ICE_DEV_ID_E810C_SFP: 6220 if (input) { 6221 t = ice_e810t_sfp_cgu_inputs; 6222 *size = ARRAY_SIZE(ice_e810t_sfp_cgu_inputs); 6223 } else { 6224 t = ice_e810t_sfp_cgu_outputs; 6225 *size = ARRAY_SIZE(ice_e810t_sfp_cgu_outputs); 6226 } 6227 break; 6228 case ICE_DEV_ID_E810C_QSFP: 6229 if (input) { 6230 t = ice_e810t_qsfp_cgu_inputs; 6231 *size = ARRAY_SIZE(ice_e810t_qsfp_cgu_inputs); 6232 } else { 6233 t = ice_e810t_qsfp_cgu_outputs; 6234 *size = ARRAY_SIZE(ice_e810t_qsfp_cgu_outputs); 6235 } 6236 break; 6237 case ICE_DEV_ID_E823L_10G_BASE_T: 6238 case ICE_DEV_ID_E823L_1GBE: 6239 case ICE_DEV_ID_E823L_BACKPLANE: 6240 case ICE_DEV_ID_E823L_QSFP: 6241 case ICE_DEV_ID_E823L_SFP: 6242 case ICE_DEV_ID_E823C_10G_BASE_T: 6243 case ICE_DEV_ID_E823C_BACKPLANE: 6244 case ICE_DEV_ID_E823C_QSFP: 6245 case ICE_DEV_ID_E823C_SFP: 6246 case ICE_DEV_ID_E823C_SGMII: 6247 t = ice_cgu_get_pin_desc_e823(hw, input, size); 6248 break; 6249 default: 6250 break; 6251 } 6252 6253 return t; 6254 } 6255 6256 /** 6257 * ice_cgu_get_num_pins - get pin description array size 6258 * @hw: pointer to the hw struct 6259 * @input: if request is done against input or output pins 6260 * 6261 * Return: size of pin description array for given hw. 6262 */ 6263 int ice_cgu_get_num_pins(struct ice_hw *hw, bool input) 6264 { 6265 const struct ice_cgu_pin_desc *t; 6266 int size; 6267 6268 t = ice_cgu_get_pin_desc(hw, input, &size); 6269 if (t) 6270 return size; 6271 6272 return 0; 6273 } 6274 6275 /** 6276 * ice_cgu_get_pin_type - get pin's type 6277 * @hw: pointer to the hw struct 6278 * @pin: pin index 6279 * @input: if request is done against input or output pin 6280 * 6281 * Return: type of a pin. 6282 */ 6283 enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool input) 6284 { 6285 const struct ice_cgu_pin_desc *t; 6286 int t_size; 6287 6288 t = ice_cgu_get_pin_desc(hw, input, &t_size); 6289 6290 if (!t) 6291 return 0; 6292 6293 if (pin >= t_size) 6294 return 0; 6295 6296 return t[pin].type; 6297 } 6298 6299 /** 6300 * ice_cgu_get_pin_freq_supp - get pin's supported frequency 6301 * @hw: pointer to the hw struct 6302 * @pin: pin index 6303 * @input: if request is done against input or output pin 6304 * @num: output number of supported frequencies 6305 * 6306 * Get frequency supported number and array of supported frequencies. 6307 * 6308 * Return: array of supported frequencies for given pin. 6309 */ 6310 struct dpll_pin_frequency * 6311 ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num) 6312 { 6313 const struct ice_cgu_pin_desc *t; 6314 int t_size; 6315 6316 *num = 0; 6317 t = ice_cgu_get_pin_desc(hw, input, &t_size); 6318 if (!t) 6319 return NULL; 6320 if (pin >= t_size) 6321 return NULL; 6322 *num = t[pin].freq_supp_num; 6323 6324 return t[pin].freq_supp; 6325 } 6326 6327 /** 6328 * ice_cgu_get_pin_name - get pin's name 6329 * @hw: pointer to the hw struct 6330 * @pin: pin index 6331 * @input: if request is done against input or output pin 6332 * 6333 * Return: 6334 * * null terminated char array with name 6335 * * NULL in case of failure 6336 */ 6337 const char *ice_cgu_get_pin_name(struct ice_hw *hw, u8 pin, bool input) 6338 { 6339 const struct ice_cgu_pin_desc *t; 6340 int t_size; 6341 6342 t = ice_cgu_get_pin_desc(hw, input, &t_size); 6343 6344 if (!t) 6345 return NULL; 6346 6347 if (pin >= t_size) 6348 return NULL; 6349 6350 return t[pin].name; 6351 } 6352 6353 /** 6354 * ice_get_cgu_state - get the state of the DPLL 6355 * @hw: pointer to the hw struct 6356 * @dpll_idx: Index of internal DPLL unit 6357 * @last_dpll_state: last known state of DPLL 6358 * @pin: pointer to a buffer for returning currently active pin 6359 * @ref_state: reference clock state 6360 * @eec_mode: eec mode of the DPLL 6361 * @phase_offset: pointer to a buffer for returning phase offset 6362 * @dpll_state: state of the DPLL (output) 6363 * 6364 * This function will read the state of the DPLL(dpll_idx). Non-null 6365 * 'pin', 'ref_state', 'eec_mode' and 'phase_offset' parameters are used to 6366 * retrieve currently active pin, state, mode and phase_offset respectively. 6367 * 6368 * Return: state of the DPLL 6369 */ 6370 int ice_get_cgu_state(struct ice_hw *hw, u8 dpll_idx, 6371 enum dpll_lock_status last_dpll_state, u8 *pin, 6372 u8 *ref_state, u8 *eec_mode, s64 *phase_offset, 6373 enum dpll_lock_status *dpll_state) 6374 { 6375 u8 hw_ref_state, hw_dpll_state, hw_eec_mode, hw_config; 6376 s64 hw_phase_offset; 6377 int status; 6378 6379 status = ice_aq_get_cgu_dpll_status(hw, dpll_idx, &hw_ref_state, 6380 &hw_dpll_state, &hw_config, 6381 &hw_phase_offset, &hw_eec_mode); 6382 if (status) 6383 return status; 6384 6385 if (pin) 6386 /* current ref pin in dpll_state_refsel_status_X register */ 6387 *pin = hw_config & ICE_AQC_GET_CGU_DPLL_CONFIG_CLK_REF_SEL; 6388 if (phase_offset) 6389 *phase_offset = hw_phase_offset; 6390 if (ref_state) 6391 *ref_state = hw_ref_state; 6392 if (eec_mode) 6393 *eec_mode = hw_eec_mode; 6394 if (!dpll_state) 6395 return 0; 6396 6397 /* According to ZL DPLL documentation, once state reach LOCKED_HO_ACQ 6398 * it would never return to FREERUN. This aligns to ITU-T G.781 6399 * Recommendation. We cannot report HOLDOVER as HO memory is cleared 6400 * while switching to another reference. 6401 * Only for situations where previous state was either: "LOCKED without 6402 * HO_ACQ" or "HOLDOVER" we actually back to FREERUN. 6403 */ 6404 if (hw_dpll_state & ICE_AQC_GET_CGU_DPLL_STATUS_STATE_LOCK) { 6405 if (hw_dpll_state & ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO_READY) 6406 *dpll_state = DPLL_LOCK_STATUS_LOCKED_HO_ACQ; 6407 else 6408 *dpll_state = DPLL_LOCK_STATUS_LOCKED; 6409 } else if (last_dpll_state == DPLL_LOCK_STATUS_LOCKED_HO_ACQ || 6410 last_dpll_state == DPLL_LOCK_STATUS_HOLDOVER) { 6411 *dpll_state = DPLL_LOCK_STATUS_HOLDOVER; 6412 } else { 6413 *dpll_state = DPLL_LOCK_STATUS_UNLOCKED; 6414 } 6415 6416 return 0; 6417 } 6418 6419 /** 6420 * ice_get_cgu_rclk_pin_info - get info on available recovered clock pins 6421 * @hw: pointer to the hw struct 6422 * @base_idx: returns index of first recovered clock pin on device 6423 * @pin_num: returns number of recovered clock pins available on device 6424 * 6425 * Based on hw provide caller info about recovery clock pins available on the 6426 * board. 6427 * 6428 * Return: 6429 * * 0 - success, information is valid 6430 * * negative - failure, information is not valid 6431 */ 6432 int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num) 6433 { 6434 u8 phy_idx; 6435 int ret; 6436 6437 switch (hw->device_id) { 6438 case ICE_DEV_ID_E810C_SFP: 6439 case ICE_DEV_ID_E810C_QSFP: 6440 6441 ret = ice_get_pf_c827_idx(hw, &phy_idx); 6442 if (ret) 6443 return ret; 6444 *base_idx = E810T_CGU_INPUT_C827(phy_idx, ICE_RCLKA_PIN); 6445 *pin_num = ICE_E810_RCLK_PINS_NUM; 6446 ret = 0; 6447 break; 6448 case ICE_DEV_ID_E823L_10G_BASE_T: 6449 case ICE_DEV_ID_E823L_1GBE: 6450 case ICE_DEV_ID_E823L_BACKPLANE: 6451 case ICE_DEV_ID_E823L_QSFP: 6452 case ICE_DEV_ID_E823L_SFP: 6453 case ICE_DEV_ID_E823C_10G_BASE_T: 6454 case ICE_DEV_ID_E823C_BACKPLANE: 6455 case ICE_DEV_ID_E823C_QSFP: 6456 case ICE_DEV_ID_E823C_SFP: 6457 case ICE_DEV_ID_E823C_SGMII: 6458 *pin_num = ICE_E82X_RCLK_PINS_NUM; 6459 ret = 0; 6460 if (hw->cgu_part_number == 6461 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032) 6462 *base_idx = ZL_REF1P; 6463 else if (hw->cgu_part_number == 6464 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384) 6465 *base_idx = SI_REF1P; 6466 else 6467 ret = -ENODEV; 6468 6469 break; 6470 default: 6471 ret = -ENODEV; 6472 break; 6473 } 6474 6475 return ret; 6476 } 6477 6478 /** 6479 * ice_cgu_get_output_pin_state_caps - get output pin state capabilities 6480 * @hw: pointer to the hw struct 6481 * @pin_id: id of a pin 6482 * @caps: capabilities to modify 6483 * 6484 * Return: 6485 * * 0 - success, state capabilities were modified 6486 * * negative - failure, capabilities were not modified 6487 */ 6488 int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id, 6489 unsigned long *caps) 6490 { 6491 bool can_change = true; 6492 6493 switch (hw->device_id) { 6494 case ICE_DEV_ID_E810C_SFP: 6495 if (pin_id == ZL_OUT2 || pin_id == ZL_OUT3) 6496 can_change = false; 6497 break; 6498 case ICE_DEV_ID_E810C_QSFP: 6499 if (pin_id == ZL_OUT2 || pin_id == ZL_OUT3 || pin_id == ZL_OUT4) 6500 can_change = false; 6501 break; 6502 case ICE_DEV_ID_E823L_10G_BASE_T: 6503 case ICE_DEV_ID_E823L_1GBE: 6504 case ICE_DEV_ID_E823L_BACKPLANE: 6505 case ICE_DEV_ID_E823L_QSFP: 6506 case ICE_DEV_ID_E823L_SFP: 6507 case ICE_DEV_ID_E823C_10G_BASE_T: 6508 case ICE_DEV_ID_E823C_BACKPLANE: 6509 case ICE_DEV_ID_E823C_QSFP: 6510 case ICE_DEV_ID_E823C_SFP: 6511 case ICE_DEV_ID_E823C_SGMII: 6512 if (hw->cgu_part_number == 6513 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032 && 6514 pin_id == ZL_OUT2) 6515 can_change = false; 6516 else if (hw->cgu_part_number == 6517 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384 && 6518 pin_id == SI_OUT1) 6519 can_change = false; 6520 break; 6521 default: 6522 return -EINVAL; 6523 } 6524 if (can_change) 6525 *caps |= DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE; 6526 else 6527 *caps &= ~DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE; 6528 6529 return 0; 6530 } 6531