1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (C) 2021, Intel Corporation. */ 3 4 #include <linux/delay.h> 5 #include <linux/iopoll.h> 6 #include "ice_common.h" 7 #include "ice_ptp_hw.h" 8 #include "ice_ptp_consts.h" 9 #include "ice_cgu_regs.h" 10 11 static struct dpll_pin_frequency ice_cgu_pin_freq_common[] = { 12 DPLL_PIN_FREQUENCY_1PPS, 13 DPLL_PIN_FREQUENCY_10MHZ, 14 }; 15 16 static struct dpll_pin_frequency ice_cgu_pin_freq_1_hz[] = { 17 DPLL_PIN_FREQUENCY_1PPS, 18 }; 19 20 static struct dpll_pin_frequency ice_cgu_pin_freq_10_mhz[] = { 21 DPLL_PIN_FREQUENCY_10MHZ, 22 }; 23 24 static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_inputs[] = { 25 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR, 26 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 27 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR, 28 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 29 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, }, 30 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, }, 31 { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT, 32 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 33 { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT, 34 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 35 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS, 36 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 37 { "OCXO", ZL_REF4N, DPLL_PIN_TYPE_INT_OSCILLATOR, 0, }, 38 }; 39 40 static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_inputs[] = { 41 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR, 42 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 43 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR, 44 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 45 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, }, 46 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, }, 47 { "C827_1-RCLKA", ZL_REF2P, DPLL_PIN_TYPE_MUX, }, 48 { "C827_1-RCLKB", ZL_REF2N, DPLL_PIN_TYPE_MUX, }, 49 { "SMA1", ZL_REF3P, DPLL_PIN_TYPE_EXT, 50 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 51 { "SMA2/U.FL2", ZL_REF3N, DPLL_PIN_TYPE_EXT, 52 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 53 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS, 54 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 55 { "OCXO", ZL_REF4N, DPLL_PIN_TYPE_INT_OSCILLATOR, }, 56 }; 57 58 static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_outputs[] = { 59 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT, 60 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 61 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT, 62 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 63 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, }, 64 { "MAC-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, }, 65 { "CVL-SDP21", ZL_OUT4, DPLL_PIN_TYPE_EXT, 66 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 67 { "CVL-SDP23", ZL_OUT5, DPLL_PIN_TYPE_EXT, 68 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 69 }; 70 71 static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_outputs[] = { 72 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT, 73 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 74 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT, 75 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 76 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 77 { "PHY2-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 78 { "MAC-CLK", ZL_OUT4, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 79 { "CVL-SDP21", ZL_OUT5, DPLL_PIN_TYPE_EXT, 80 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 81 { "CVL-SDP23", ZL_OUT6, DPLL_PIN_TYPE_EXT, 82 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 83 }; 84 85 static const struct ice_cgu_pin_desc ice_e823_si_cgu_inputs[] = { 86 { "NONE", SI_REF0P, 0, 0 }, 87 { "NONE", SI_REF0N, 0, 0 }, 88 { "SYNCE0_DP", SI_REF1P, DPLL_PIN_TYPE_MUX, 0 }, 89 { "SYNCE0_DN", SI_REF1N, DPLL_PIN_TYPE_MUX, 0 }, 90 { "EXT_CLK_SYNC", SI_REF2P, DPLL_PIN_TYPE_EXT, 91 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 92 { "NONE", SI_REF2N, 0, 0 }, 93 { "EXT_PPS_OUT", SI_REF3, DPLL_PIN_TYPE_EXT, 94 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 95 { "INT_PPS_OUT", SI_REF4, DPLL_PIN_TYPE_EXT, 96 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 97 }; 98 99 static const struct ice_cgu_pin_desc ice_e823_si_cgu_outputs[] = { 100 { "1588-TIME_SYNC", SI_OUT0, DPLL_PIN_TYPE_EXT, 101 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 102 { "PHY-CLK", SI_OUT1, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 103 { "10MHZ-SMA2", SI_OUT2, DPLL_PIN_TYPE_EXT, 104 ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz }, 105 { "PPS-SMA1", SI_OUT3, DPLL_PIN_TYPE_EXT, 106 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 107 }; 108 109 static const struct ice_cgu_pin_desc ice_e823_zl_cgu_inputs[] = { 110 { "NONE", ZL_REF0P, 0, 0 }, 111 { "INT_PPS_OUT", ZL_REF0N, DPLL_PIN_TYPE_EXT, 112 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 113 { "SYNCE0_DP", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0 }, 114 { "SYNCE0_DN", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0 }, 115 { "NONE", ZL_REF2P, 0, 0 }, 116 { "NONE", ZL_REF2N, 0, 0 }, 117 { "EXT_CLK_SYNC", ZL_REF3P, DPLL_PIN_TYPE_EXT, 118 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 119 { "NONE", ZL_REF3N, 0, 0 }, 120 { "EXT_PPS_OUT", ZL_REF4P, DPLL_PIN_TYPE_EXT, 121 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 122 { "OCXO", ZL_REF4N, DPLL_PIN_TYPE_INT_OSCILLATOR, 0 }, 123 }; 124 125 static const struct ice_cgu_pin_desc ice_e823_zl_cgu_outputs[] = { 126 { "PPS-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT, 127 ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz }, 128 { "10MHZ-SMA2", ZL_OUT1, DPLL_PIN_TYPE_EXT, 129 ARRAY_SIZE(ice_cgu_pin_freq_10_mhz), ice_cgu_pin_freq_10_mhz }, 130 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 131 { "1588-TIME_REF", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 }, 132 { "CPK-TIME_SYNC", ZL_OUT4, DPLL_PIN_TYPE_EXT, 133 ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common }, 134 { "NONE", ZL_OUT5, 0, 0 }, 135 }; 136 137 /* Low level functions for interacting with and managing the device clock used 138 * for the Precision Time Protocol. 139 * 140 * The ice hardware represents the current time using three registers: 141 * 142 * GLTSYN_TIME_H GLTSYN_TIME_L GLTSYN_TIME_R 143 * +---------------+ +---------------+ +---------------+ 144 * | 32 bits | | 32 bits | | 32 bits | 145 * +---------------+ +---------------+ +---------------+ 146 * 147 * The registers are incremented every clock tick using a 40bit increment 148 * value defined over two registers: 149 * 150 * GLTSYN_INCVAL_H GLTSYN_INCVAL_L 151 * +---------------+ +---------------+ 152 * | 8 bit s | | 32 bits | 153 * +---------------+ +---------------+ 154 * 155 * The increment value is added to the GLSTYN_TIME_R and GLSTYN_TIME_L 156 * registers every clock source tick. Depending on the specific device 157 * configuration, the clock source frequency could be one of a number of 158 * values. 159 * 160 * For E810 devices, the increment frequency is 812.5 MHz 161 * 162 * For E822 devices the clock can be derived from different sources, and the 163 * increment has an effective frequency of one of the following: 164 * - 823.4375 MHz 165 * - 783.36 MHz 166 * - 796.875 MHz 167 * - 816 MHz 168 * - 830.078125 MHz 169 * - 783.36 MHz 170 * 171 * The hardware captures timestamps in the PHY for incoming packets, and for 172 * outgoing packets on request. To support this, the PHY maintains a timer 173 * that matches the lower 64 bits of the global source timer. 174 * 175 * In order to ensure that the PHY timers and the source timer are equivalent, 176 * shadow registers are used to prepare the desired initial values. A special 177 * sync command is issued to trigger copying from the shadow registers into 178 * the appropriate source and PHY registers simultaneously. 179 * 180 * The driver supports devices which have different PHYs with subtly different 181 * mechanisms to program and control the timers. We divide the devices into 182 * families named after the first major device, E810 and similar devices, and 183 * E822 and similar devices. 184 * 185 * - E822 based devices have additional support for fine grained Vernier 186 * calibration which requires significant setup 187 * - The layout of timestamp data in the PHY register blocks is different 188 * - The way timer synchronization commands are issued is different. 189 * 190 * To support this, very low level functions have an e810 or e822 suffix 191 * indicating what type of device they work on. Higher level abstractions for 192 * tasks that can be done on both devices do not have the suffix and will 193 * correctly look up the appropriate low level function when running. 194 * 195 * Functions which only make sense on a single device family may not have 196 * a suitable generic implementation 197 */ 198 199 /** 200 * ice_get_ptp_src_clock_index - determine source clock index 201 * @hw: pointer to HW struct 202 * 203 * Determine the source clock index currently in use, based on device 204 * capabilities reported during initialization. 205 */ 206 u8 ice_get_ptp_src_clock_index(struct ice_hw *hw) 207 { 208 return hw->func_caps.ts_func_info.tmr_index_assoc; 209 } 210 211 /** 212 * ice_ptp_read_src_incval - Read source timer increment value 213 * @hw: pointer to HW struct 214 * 215 * Read the increment value of the source timer and return it. 216 */ 217 static u64 ice_ptp_read_src_incval(struct ice_hw *hw) 218 { 219 u32 lo, hi; 220 u8 tmr_idx; 221 222 tmr_idx = ice_get_ptp_src_clock_index(hw); 223 224 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 225 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 226 227 return ((u64)(hi & INCVAL_HIGH_M) << 32) | lo; 228 } 229 230 /** 231 * ice_read_cgu_reg_e82x - Read a CGU register 232 * @hw: pointer to the HW struct 233 * @addr: Register address to read 234 * @val: storage for register value read 235 * 236 * Read the contents of a register of the Clock Generation Unit. Only 237 * applicable to E822 devices. 238 * 239 * Return: 0 on success, other error codes when failed to read from CGU 240 */ 241 static int ice_read_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 *val) 242 { 243 struct ice_sbq_msg_input cgu_msg = { 244 .opcode = ice_sbq_msg_rd, 245 .dest_dev = cgu, 246 .msg_addr_low = addr 247 }; 248 int err; 249 250 err = ice_sbq_rw_reg(hw, &cgu_msg, ICE_AQ_FLAG_RD); 251 if (err) { 252 ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n", 253 addr, err); 254 return err; 255 } 256 257 *val = cgu_msg.data; 258 259 return 0; 260 } 261 262 /** 263 * ice_write_cgu_reg_e82x - Write a CGU register 264 * @hw: pointer to the HW struct 265 * @addr: Register address to write 266 * @val: value to write into the register 267 * 268 * Write the specified value to a register of the Clock Generation Unit. Only 269 * applicable to E822 devices. 270 * 271 * Return: 0 on success, other error codes when failed to write to CGU 272 */ 273 static int ice_write_cgu_reg_e82x(struct ice_hw *hw, u32 addr, u32 val) 274 { 275 struct ice_sbq_msg_input cgu_msg = { 276 .opcode = ice_sbq_msg_wr, 277 .dest_dev = cgu, 278 .msg_addr_low = addr, 279 .data = val 280 }; 281 int err; 282 283 err = ice_sbq_rw_reg(hw, &cgu_msg, ICE_AQ_FLAG_RD); 284 if (err) { 285 ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n", 286 addr, err); 287 return err; 288 } 289 290 return err; 291 } 292 293 /** 294 * ice_clk_freq_str - Convert time_ref_freq to string 295 * @clk_freq: Clock frequency 296 * 297 * Return: specified TIME_REF clock frequency converted to a string 298 */ 299 static const char *ice_clk_freq_str(enum ice_time_ref_freq clk_freq) 300 { 301 switch (clk_freq) { 302 case ICE_TIME_REF_FREQ_25_000: 303 return "25 MHz"; 304 case ICE_TIME_REF_FREQ_122_880: 305 return "122.88 MHz"; 306 case ICE_TIME_REF_FREQ_125_000: 307 return "125 MHz"; 308 case ICE_TIME_REF_FREQ_153_600: 309 return "153.6 MHz"; 310 case ICE_TIME_REF_FREQ_156_250: 311 return "156.25 MHz"; 312 case ICE_TIME_REF_FREQ_245_760: 313 return "245.76 MHz"; 314 default: 315 return "Unknown"; 316 } 317 } 318 319 /** 320 * ice_clk_src_str - Convert time_ref_src to string 321 * @clk_src: Clock source 322 * 323 * Return: specified clock source converted to its string name 324 */ 325 static const char *ice_clk_src_str(enum ice_clk_src clk_src) 326 { 327 switch (clk_src) { 328 case ICE_CLK_SRC_TCXO: 329 return "TCXO"; 330 case ICE_CLK_SRC_TIME_REF: 331 return "TIME_REF"; 332 default: 333 return "Unknown"; 334 } 335 } 336 337 /** 338 * ice_cfg_cgu_pll_e82x - Configure the Clock Generation Unit 339 * @hw: pointer to the HW struct 340 * @clk_freq: Clock frequency to program 341 * @clk_src: Clock source to select (TIME_REF, or TCXO) 342 * 343 * Configure the Clock Generation Unit with the desired clock frequency and 344 * time reference, enabling the PLL which drives the PTP hardware clock. 345 * 346 * Return: 347 * * %0 - success 348 * * %-EINVAL - input parameters are incorrect 349 * * %-EBUSY - failed to lock TS PLL 350 * * %other - CGU read/write failure 351 */ 352 static int ice_cfg_cgu_pll_e82x(struct ice_hw *hw, 353 enum ice_time_ref_freq clk_freq, 354 enum ice_clk_src clk_src) 355 { 356 union tspll_ro_bwm_lf bwm_lf; 357 union nac_cgu_dword19 dw19; 358 union nac_cgu_dword22 dw22; 359 union nac_cgu_dword24 dw24; 360 union nac_cgu_dword9 dw9; 361 int err; 362 363 if (clk_freq >= NUM_ICE_TIME_REF_FREQ) { 364 dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n", 365 clk_freq); 366 return -EINVAL; 367 } 368 369 if (clk_src >= NUM_ICE_CLK_SRC) { 370 dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n", 371 clk_src); 372 return -EINVAL; 373 } 374 375 if (clk_src == ICE_CLK_SRC_TCXO && 376 clk_freq != ICE_TIME_REF_FREQ_25_000) { 377 dev_warn(ice_hw_to_dev(hw), 378 "TCXO only supports 25 MHz frequency\n"); 379 return -EINVAL; 380 } 381 382 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val); 383 if (err) 384 return err; 385 386 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val); 387 if (err) 388 return err; 389 390 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val); 391 if (err) 392 return err; 393 394 /* Log the current clock configuration */ 395 ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", 396 dw24.ts_pll_enable ? "enabled" : "disabled", 397 ice_clk_src_str(dw24.time_ref_sel), 398 ice_clk_freq_str(dw9.time_ref_freq_sel), 399 bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked"); 400 401 /* Disable the PLL before changing the clock source or frequency */ 402 if (dw24.ts_pll_enable) { 403 dw24.ts_pll_enable = 0; 404 405 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val); 406 if (err) 407 return err; 408 } 409 410 /* Set the frequency */ 411 dw9.time_ref_freq_sel = clk_freq; 412 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val); 413 if (err) 414 return err; 415 416 /* Configure the TS PLL feedback divisor */ 417 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val); 418 if (err) 419 return err; 420 421 dw19.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div; 422 dw19.tspll_ndivratio = 1; 423 424 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val); 425 if (err) 426 return err; 427 428 /* Configure the TS PLL post divisor */ 429 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val); 430 if (err) 431 return err; 432 433 dw22.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div; 434 dw22.time1588clk_sel_div2 = 0; 435 436 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val); 437 if (err) 438 return err; 439 440 /* Configure the TS PLL pre divisor and clock source */ 441 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val); 442 if (err) 443 return err; 444 445 dw24.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div; 446 dw24.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div; 447 dw24.time_ref_sel = clk_src; 448 449 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val); 450 if (err) 451 return err; 452 453 /* Finally, enable the PLL */ 454 dw24.ts_pll_enable = 1; 455 456 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val); 457 if (err) 458 return err; 459 460 /* Wait to verify if the PLL locks */ 461 usleep_range(1000, 5000); 462 463 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_BWM_LF, &bwm_lf.val); 464 if (err) 465 return err; 466 467 if (!bwm_lf.plllock_true_lock_cri) { 468 dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n"); 469 return -EBUSY; 470 } 471 472 /* Log the current clock configuration */ 473 ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", 474 dw24.ts_pll_enable ? "enabled" : "disabled", 475 ice_clk_src_str(dw24.time_ref_sel), 476 ice_clk_freq_str(dw9.time_ref_freq_sel), 477 bwm_lf.plllock_true_lock_cri ? "locked" : "unlocked"); 478 479 return 0; 480 } 481 482 /** 483 * ice_cfg_cgu_pll_e825c - Configure the Clock Generation Unit for E825-C 484 * @hw: pointer to the HW struct 485 * @clk_freq: Clock frequency to program 486 * @clk_src: Clock source to select (TIME_REF, or TCXO) 487 * 488 * Configure the Clock Generation Unit with the desired clock frequency and 489 * time reference, enabling the PLL which drives the PTP hardware clock. 490 * 491 * Return: 492 * * %0 - success 493 * * %-EINVAL - input parameters are incorrect 494 * * %-EBUSY - failed to lock TS PLL 495 * * %other - CGU read/write failure 496 */ 497 static int ice_cfg_cgu_pll_e825c(struct ice_hw *hw, 498 enum ice_time_ref_freq clk_freq, 499 enum ice_clk_src clk_src) 500 { 501 union tspll_ro_lock_e825c ro_lock; 502 union nac_cgu_dword16_e825c dw16; 503 union nac_cgu_dword23_e825c dw23; 504 union nac_cgu_dword19 dw19; 505 union nac_cgu_dword22 dw22; 506 union nac_cgu_dword24 dw24; 507 union nac_cgu_dword9 dw9; 508 int err; 509 510 if (clk_freq >= NUM_ICE_TIME_REF_FREQ) { 511 dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n", 512 clk_freq); 513 return -EINVAL; 514 } 515 516 if (clk_src >= NUM_ICE_CLK_SRC) { 517 dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n", 518 clk_src); 519 return -EINVAL; 520 } 521 522 if (clk_src == ICE_CLK_SRC_TCXO && 523 clk_freq != ICE_TIME_REF_FREQ_156_250) { 524 dev_warn(ice_hw_to_dev(hw), 525 "TCXO only supports 156.25 MHz frequency\n"); 526 return -EINVAL; 527 } 528 529 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val); 530 if (err) 531 return err; 532 533 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD24, &dw24.val); 534 if (err) 535 return err; 536 537 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD16_E825C, &dw16.val); 538 if (err) 539 return err; 540 541 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val); 542 if (err) 543 return err; 544 545 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val); 546 if (err) 547 return err; 548 549 /* Log the current clock configuration */ 550 ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", 551 dw24.ts_pll_enable ? "enabled" : "disabled", 552 ice_clk_src_str(dw23.time_ref_sel), 553 ice_clk_freq_str(dw9.time_ref_freq_sel), 554 ro_lock.plllock_true_lock_cri ? "locked" : "unlocked"); 555 556 /* Disable the PLL before changing the clock source or frequency */ 557 if (dw23.ts_pll_enable) { 558 dw23.ts_pll_enable = 0; 559 560 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, 561 dw23.val); 562 if (err) 563 return err; 564 } 565 566 /* Set the frequency */ 567 dw9.time_ref_freq_sel = clk_freq; 568 569 /* Enable the correct receiver */ 570 if (clk_src == ICE_CLK_SRC_TCXO) { 571 dw9.time_ref_en = 0; 572 dw9.clk_eref0_en = 1; 573 } else { 574 dw9.time_ref_en = 1; 575 dw9.clk_eref0_en = 0; 576 } 577 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val); 578 if (err) 579 return err; 580 581 /* Choose the referenced frequency */ 582 dw16.tspll_ck_refclkfreq = 583 e825c_cgu_params[clk_freq].tspll_ck_refclkfreq; 584 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD16_E825C, dw16.val); 585 if (err) 586 return err; 587 588 /* Configure the TS PLL feedback divisor */ 589 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD19, &dw19.val); 590 if (err) 591 return err; 592 593 dw19.tspll_fbdiv_intgr = 594 e825c_cgu_params[clk_freq].tspll_fbdiv_intgr; 595 dw19.tspll_ndivratio = 596 e825c_cgu_params[clk_freq].tspll_ndivratio; 597 598 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD19, dw19.val); 599 if (err) 600 return err; 601 602 /* Configure the TS PLL post divisor */ 603 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD22, &dw22.val); 604 if (err) 605 return err; 606 607 /* These two are constant for E825C */ 608 dw22.time1588clk_div = 5; 609 dw22.time1588clk_sel_div2 = 0; 610 611 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD22, dw22.val); 612 if (err) 613 return err; 614 615 /* Configure the TS PLL pre divisor and clock source */ 616 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, &dw23.val); 617 if (err) 618 return err; 619 620 dw23.ref1588_ck_div = 621 e825c_cgu_params[clk_freq].ref1588_ck_div; 622 dw23.time_ref_sel = clk_src; 623 624 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val); 625 if (err) 626 return err; 627 628 dw24.tspll_fbdiv_frac = 629 e825c_cgu_params[clk_freq].tspll_fbdiv_frac; 630 631 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD24, dw24.val); 632 if (err) 633 return err; 634 635 /* Finally, enable the PLL */ 636 dw23.ts_pll_enable = 1; 637 638 err = ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD23_E825C, dw23.val); 639 if (err) 640 return err; 641 642 /* Wait to verify if the PLL locks */ 643 usleep_range(1000, 5000); 644 645 err = ice_read_cgu_reg_e82x(hw, TSPLL_RO_LOCK_E825C, &ro_lock.val); 646 if (err) 647 return err; 648 649 if (!ro_lock.plllock_true_lock_cri) { 650 dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n"); 651 return -EBUSY; 652 } 653 654 /* Log the current clock configuration */ 655 ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", 656 dw24.ts_pll_enable ? "enabled" : "disabled", 657 ice_clk_src_str(dw23.time_ref_sel), 658 ice_clk_freq_str(dw9.time_ref_freq_sel), 659 ro_lock.plllock_true_lock_cri ? "locked" : "unlocked"); 660 661 return 0; 662 } 663 664 #define ICE_ONE_PPS_OUT_AMP_MAX 3 665 666 /** 667 * ice_cgu_cfg_pps_out - Configure 1PPS output from CGU 668 * @hw: pointer to the HW struct 669 * @enable: true to enable 1PPS output, false to disable it 670 * 671 * Return: 0 on success, other negative error code when CGU read/write failed 672 */ 673 int ice_cgu_cfg_pps_out(struct ice_hw *hw, bool enable) 674 { 675 union nac_cgu_dword9 dw9; 676 int err; 677 678 err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val); 679 if (err) 680 return err; 681 682 dw9.one_pps_out_en = enable; 683 dw9.one_pps_out_amp = enable * ICE_ONE_PPS_OUT_AMP_MAX; 684 return ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val); 685 } 686 687 /** 688 * ice_cfg_cgu_pll_dis_sticky_bits_e82x - disable TS PLL sticky bits 689 * @hw: pointer to the HW struct 690 * 691 * Configure the Clock Generation Unit TS PLL sticky bits so they don't latch on 692 * losing TS PLL lock, but always show current state. 693 * 694 * Return: 0 on success, other error codes when failed to read/write CGU 695 */ 696 static int ice_cfg_cgu_pll_dis_sticky_bits_e82x(struct ice_hw *hw) 697 { 698 union tspll_cntr_bist_settings cntr_bist; 699 int err; 700 701 err = ice_read_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS, 702 &cntr_bist.val); 703 if (err) 704 return err; 705 706 /* Disable sticky lock detection so lock err reported is accurate */ 707 cntr_bist.i_plllock_sel_0 = 0; 708 cntr_bist.i_plllock_sel_1 = 0; 709 710 return ice_write_cgu_reg_e82x(hw, TSPLL_CNTR_BIST_SETTINGS, 711 cntr_bist.val); 712 } 713 714 /** 715 * ice_cfg_cgu_pll_dis_sticky_bits_e825c - disable TS PLL sticky bits for E825-C 716 * @hw: pointer to the HW struct 717 * 718 * Configure the Clock Generation Unit TS PLL sticky bits so they don't latch on 719 * losing TS PLL lock, but always show current state. 720 * 721 * Return: 0 on success, other error codes when failed to read/write CGU 722 */ 723 static int ice_cfg_cgu_pll_dis_sticky_bits_e825c(struct ice_hw *hw) 724 { 725 union tspll_bw_tdc_e825c bw_tdc; 726 int err; 727 728 err = ice_read_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C, &bw_tdc.val); 729 if (err) 730 return err; 731 732 bw_tdc.i_plllock_sel_1_0 = 0; 733 734 return ice_write_cgu_reg_e82x(hw, TSPLL_BW_TDC_E825C, bw_tdc.val); 735 } 736 737 /** 738 * ice_init_cgu_e82x - Initialize CGU with settings from firmware 739 * @hw: pointer to the HW structure 740 * 741 * Initialize the Clock Generation Unit of the E822 device. 742 * 743 * Return: 0 on success, other error codes when failed to read/write/cfg CGU 744 */ 745 static int ice_init_cgu_e82x(struct ice_hw *hw) 746 { 747 struct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info; 748 int err; 749 750 /* Disable sticky lock detection so lock err reported is accurate */ 751 if (ice_is_e825c(hw)) 752 err = ice_cfg_cgu_pll_dis_sticky_bits_e825c(hw); 753 else 754 err = ice_cfg_cgu_pll_dis_sticky_bits_e82x(hw); 755 if (err) 756 return err; 757 758 /* Configure the CGU PLL using the parameters from the function 759 * capabilities. 760 */ 761 if (ice_is_e825c(hw)) 762 err = ice_cfg_cgu_pll_e825c(hw, ts_info->time_ref, 763 (enum ice_clk_src)ts_info->clk_src); 764 else 765 err = ice_cfg_cgu_pll_e82x(hw, ts_info->time_ref, 766 (enum ice_clk_src)ts_info->clk_src); 767 768 return err; 769 } 770 771 /** 772 * ice_ptp_tmr_cmd_to_src_reg - Convert to source timer command value 773 * @hw: pointer to HW struct 774 * @cmd: Timer command 775 * 776 * Return: the source timer command register value for the given PTP timer 777 * command. 778 */ 779 static u32 ice_ptp_tmr_cmd_to_src_reg(struct ice_hw *hw, 780 enum ice_ptp_tmr_cmd cmd) 781 { 782 u32 cmd_val, tmr_idx; 783 784 switch (cmd) { 785 case ICE_PTP_INIT_TIME: 786 cmd_val = GLTSYN_CMD_INIT_TIME; 787 break; 788 case ICE_PTP_INIT_INCVAL: 789 cmd_val = GLTSYN_CMD_INIT_INCVAL; 790 break; 791 case ICE_PTP_ADJ_TIME: 792 cmd_val = GLTSYN_CMD_ADJ_TIME; 793 break; 794 case ICE_PTP_ADJ_TIME_AT_TIME: 795 cmd_val = GLTSYN_CMD_ADJ_INIT_TIME; 796 break; 797 case ICE_PTP_NOP: 798 case ICE_PTP_READ_TIME: 799 cmd_val = GLTSYN_CMD_READ_TIME; 800 break; 801 default: 802 dev_warn(ice_hw_to_dev(hw), 803 "Ignoring unrecognized timer command %u\n", cmd); 804 cmd_val = 0; 805 } 806 807 tmr_idx = ice_get_ptp_src_clock_index(hw); 808 809 return tmr_idx << SEL_CPK_SRC | cmd_val; 810 } 811 812 /** 813 * ice_ptp_tmr_cmd_to_port_reg- Convert to port timer command value 814 * @hw: pointer to HW struct 815 * @cmd: Timer command 816 * 817 * Note that some hardware families use a different command register value for 818 * the PHY ports, while other hardware families use the same register values 819 * as the source timer. 820 * 821 * Return: the PHY port timer command register value for the given PTP timer 822 * command. 823 */ 824 static u32 ice_ptp_tmr_cmd_to_port_reg(struct ice_hw *hw, 825 enum ice_ptp_tmr_cmd cmd) 826 { 827 u32 cmd_val, tmr_idx; 828 829 /* Certain hardware families share the same register values for the 830 * port register and source timer register. 831 */ 832 switch (ice_get_phy_model(hw)) { 833 case ICE_PHY_E810: 834 return ice_ptp_tmr_cmd_to_src_reg(hw, cmd) & TS_CMD_MASK_E810; 835 default: 836 break; 837 } 838 839 switch (cmd) { 840 case ICE_PTP_INIT_TIME: 841 cmd_val = PHY_CMD_INIT_TIME; 842 break; 843 case ICE_PTP_INIT_INCVAL: 844 cmd_val = PHY_CMD_INIT_INCVAL; 845 break; 846 case ICE_PTP_ADJ_TIME: 847 cmd_val = PHY_CMD_ADJ_TIME; 848 break; 849 case ICE_PTP_ADJ_TIME_AT_TIME: 850 cmd_val = PHY_CMD_ADJ_TIME_AT_TIME; 851 break; 852 case ICE_PTP_READ_TIME: 853 cmd_val = PHY_CMD_READ_TIME; 854 break; 855 case ICE_PTP_NOP: 856 cmd_val = 0; 857 break; 858 default: 859 dev_warn(ice_hw_to_dev(hw), 860 "Ignoring unrecognized timer command %u\n", cmd); 861 cmd_val = 0; 862 } 863 864 tmr_idx = ice_get_ptp_src_clock_index(hw); 865 866 return tmr_idx << SEL_PHY_SRC | cmd_val; 867 } 868 869 /** 870 * ice_ptp_src_cmd - Prepare source timer for a timer command 871 * @hw: pointer to HW structure 872 * @cmd: Timer command 873 * 874 * Prepare the source timer for an upcoming timer sync command. 875 */ 876 void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 877 { 878 u32 cmd_val = ice_ptp_tmr_cmd_to_src_reg(hw, cmd); 879 880 wr32(hw, GLTSYN_CMD, cmd_val); 881 } 882 883 /** 884 * ice_ptp_exec_tmr_cmd - Execute all prepared timer commands 885 * @hw: pointer to HW struct 886 * 887 * Write the SYNC_EXEC_CMD bit to the GLTSYN_CMD_SYNC register, and flush the 888 * write immediately. This triggers the hardware to begin executing all of the 889 * source and PHY timer commands synchronously. 890 */ 891 static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw) 892 { 893 struct ice_pf *pf = container_of(hw, struct ice_pf, hw); 894 895 guard(spinlock)(&pf->adapter->ptp_gltsyn_time_lock); 896 wr32(hw, GLTSYN_CMD_SYNC, SYNC_EXEC_CMD); 897 ice_flush(hw); 898 } 899 900 /* 56G PHY device functions 901 * 902 * The following functions operate on devices with the ETH 56G PHY. 903 */ 904 905 /** 906 * ice_write_phy_eth56g - Write a PHY port register 907 * @hw: pointer to the HW struct 908 * @phy_idx: PHY index 909 * @addr: PHY register address 910 * @val: Value to write 911 * 912 * Return: 0 on success, other error codes when failed to write to PHY 913 */ 914 static int ice_write_phy_eth56g(struct ice_hw *hw, u8 phy_idx, u32 addr, 915 u32 val) 916 { 917 struct ice_sbq_msg_input phy_msg; 918 int err; 919 920 phy_msg.opcode = ice_sbq_msg_wr; 921 922 phy_msg.msg_addr_low = lower_16_bits(addr); 923 phy_msg.msg_addr_high = upper_16_bits(addr); 924 925 phy_msg.data = val; 926 phy_msg.dest_dev = hw->ptp.phy.eth56g.phy_addr[phy_idx]; 927 928 err = ice_sbq_rw_reg(hw, &phy_msg, ICE_AQ_FLAG_RD); 929 930 if (err) 931 ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n", 932 err); 933 934 return err; 935 } 936 937 /** 938 * ice_read_phy_eth56g - Read a PHY port register 939 * @hw: pointer to the HW struct 940 * @phy_idx: PHY index 941 * @addr: PHY register address 942 * @val: Value to write 943 * 944 * Return: 0 on success, other error codes when failed to read from PHY 945 */ 946 static int ice_read_phy_eth56g(struct ice_hw *hw, u8 phy_idx, u32 addr, 947 u32 *val) 948 { 949 struct ice_sbq_msg_input phy_msg; 950 int err; 951 952 phy_msg.opcode = ice_sbq_msg_rd; 953 954 phy_msg.msg_addr_low = lower_16_bits(addr); 955 phy_msg.msg_addr_high = upper_16_bits(addr); 956 957 phy_msg.data = 0; 958 phy_msg.dest_dev = hw->ptp.phy.eth56g.phy_addr[phy_idx]; 959 960 err = ice_sbq_rw_reg(hw, &phy_msg, ICE_AQ_FLAG_RD); 961 if (err) { 962 ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n", 963 err); 964 return err; 965 } 966 967 *val = phy_msg.data; 968 969 return 0; 970 } 971 972 /** 973 * ice_phy_res_address_eth56g - Calculate a PHY port register address 974 * @port: Port number to be written 975 * @res_type: resource type (register/memory) 976 * @offset: Offset from PHY port register base 977 * @addr: The result address 978 * 979 * Return: 980 * * %0 - success 981 * * %EINVAL - invalid port number or resource type 982 */ 983 static int ice_phy_res_address_eth56g(u8 port, enum eth56g_res_type res_type, 984 u32 offset, u32 *addr) 985 { 986 u8 lane = port % ICE_PORTS_PER_QUAD; 987 u8 phy = ICE_GET_QUAD_NUM(port); 988 989 if (res_type >= NUM_ETH56G_PHY_RES) 990 return -EINVAL; 991 992 *addr = eth56g_phy_res[res_type].base[phy] + 993 lane * eth56g_phy_res[res_type].step + offset; 994 return 0; 995 } 996 997 /** 998 * ice_write_port_eth56g - Write a PHY port register 999 * @hw: pointer to the HW struct 1000 * @offset: PHY register offset 1001 * @port: Port number 1002 * @val: Value to write 1003 * @res_type: resource type (register/memory) 1004 * 1005 * Return: 1006 * * %0 - success 1007 * * %EINVAL - invalid port number or resource type 1008 * * %other - failed to write to PHY 1009 */ 1010 static int ice_write_port_eth56g(struct ice_hw *hw, u8 port, u32 offset, 1011 u32 val, enum eth56g_res_type res_type) 1012 { 1013 u8 phy_port = port % hw->ptp.ports_per_phy; 1014 u8 phy_idx = port / hw->ptp.ports_per_phy; 1015 u32 addr; 1016 int err; 1017 1018 if (port >= hw->ptp.num_lports) 1019 return -EINVAL; 1020 1021 err = ice_phy_res_address_eth56g(phy_port, res_type, offset, &addr); 1022 if (err) 1023 return err; 1024 1025 return ice_write_phy_eth56g(hw, phy_idx, addr, val); 1026 } 1027 1028 /** 1029 * ice_read_port_eth56g - Read a PHY port register 1030 * @hw: pointer to the HW struct 1031 * @offset: PHY register offset 1032 * @port: Port number 1033 * @val: Value to write 1034 * @res_type: resource type (register/memory) 1035 * 1036 * Return: 1037 * * %0 - success 1038 * * %EINVAL - invalid port number or resource type 1039 * * %other - failed to read from PHY 1040 */ 1041 static int ice_read_port_eth56g(struct ice_hw *hw, u8 port, u32 offset, 1042 u32 *val, enum eth56g_res_type res_type) 1043 { 1044 u8 phy_port = port % hw->ptp.ports_per_phy; 1045 u8 phy_idx = port / hw->ptp.ports_per_phy; 1046 u32 addr; 1047 int err; 1048 1049 if (port >= hw->ptp.num_lports) 1050 return -EINVAL; 1051 1052 err = ice_phy_res_address_eth56g(phy_port, res_type, offset, &addr); 1053 if (err) 1054 return err; 1055 1056 return ice_read_phy_eth56g(hw, phy_idx, addr, val); 1057 } 1058 1059 /** 1060 * ice_write_ptp_reg_eth56g - Write a PHY port register 1061 * @hw: pointer to the HW struct 1062 * @port: Port number to be written 1063 * @offset: Offset from PHY port register base 1064 * @val: Value to write 1065 * 1066 * Return: 1067 * * %0 - success 1068 * * %EINVAL - invalid port number or resource type 1069 * * %other - failed to write to PHY 1070 */ 1071 static int ice_write_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1072 u32 val) 1073 { 1074 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_PTP); 1075 } 1076 1077 /** 1078 * ice_write_mac_reg_eth56g - Write a MAC PHY port register 1079 * parameter 1080 * @hw: pointer to the HW struct 1081 * @port: Port number to be written 1082 * @offset: Offset from PHY port register base 1083 * @val: Value to write 1084 * 1085 * Return: 1086 * * %0 - success 1087 * * %EINVAL - invalid port number or resource type 1088 * * %other - failed to write to PHY 1089 */ 1090 static int ice_write_mac_reg_eth56g(struct ice_hw *hw, u8 port, u32 offset, 1091 u32 val) 1092 { 1093 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_MAC); 1094 } 1095 1096 /** 1097 * ice_write_xpcs_reg_eth56g - Write a PHY port register 1098 * @hw: pointer to the HW struct 1099 * @port: Port number to be written 1100 * @offset: Offset from PHY port register base 1101 * @val: Value to write 1102 * 1103 * Return: 1104 * * %0 - success 1105 * * %EINVAL - invalid port number or resource type 1106 * * %other - failed to write to PHY 1107 */ 1108 static int ice_write_xpcs_reg_eth56g(struct ice_hw *hw, u8 port, u32 offset, 1109 u32 val) 1110 { 1111 return ice_write_port_eth56g(hw, port, offset, val, 1112 ETH56G_PHY_REG_XPCS); 1113 } 1114 1115 /** 1116 * ice_read_ptp_reg_eth56g - Read a PHY port register 1117 * @hw: pointer to the HW struct 1118 * @port: Port number to be read 1119 * @offset: Offset from PHY port register base 1120 * @val: Pointer to the value to read (out param) 1121 * 1122 * Return: 1123 * * %0 - success 1124 * * %EINVAL - invalid port number or resource type 1125 * * %other - failed to read from PHY 1126 */ 1127 static int ice_read_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1128 u32 *val) 1129 { 1130 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_PTP); 1131 } 1132 1133 /** 1134 * ice_read_mac_reg_eth56g - Read a PHY port register 1135 * @hw: pointer to the HW struct 1136 * @port: Port number to be read 1137 * @offset: Offset from PHY port register base 1138 * @val: Pointer to the value to read (out param) 1139 * 1140 * Return: 1141 * * %0 - success 1142 * * %EINVAL - invalid port number or resource type 1143 * * %other - failed to read from PHY 1144 */ 1145 static int ice_read_mac_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1146 u32 *val) 1147 { 1148 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_MAC); 1149 } 1150 1151 /** 1152 * ice_read_gpcs_reg_eth56g - Read a PHY port register 1153 * @hw: pointer to the HW struct 1154 * @port: Port number to be read 1155 * @offset: Offset from PHY port register base 1156 * @val: Pointer to the value to read (out param) 1157 * 1158 * Return: 1159 * * %0 - success 1160 * * %EINVAL - invalid port number or resource type 1161 * * %other - failed to read from PHY 1162 */ 1163 static int ice_read_gpcs_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1164 u32 *val) 1165 { 1166 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_REG_GPCS); 1167 } 1168 1169 /** 1170 * ice_read_port_mem_eth56g - Read a PHY port memory location 1171 * @hw: pointer to the HW struct 1172 * @port: Port number to be read 1173 * @offset: Offset from PHY port register base 1174 * @val: Pointer to the value to read (out param) 1175 * 1176 * Return: 1177 * * %0 - success 1178 * * %EINVAL - invalid port number or resource type 1179 * * %other - failed to read from PHY 1180 */ 1181 static int ice_read_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1182 u32 *val) 1183 { 1184 return ice_read_port_eth56g(hw, port, offset, val, ETH56G_PHY_MEM_PTP); 1185 } 1186 1187 /** 1188 * ice_write_port_mem_eth56g - Write a PHY port memory location 1189 * @hw: pointer to the HW struct 1190 * @port: Port number to be read 1191 * @offset: Offset from PHY port register base 1192 * @val: Pointer to the value to read (out param) 1193 * 1194 * Return: 1195 * * %0 - success 1196 * * %EINVAL - invalid port number or resource type 1197 * * %other - failed to write to PHY 1198 */ 1199 static int ice_write_port_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset, 1200 u32 val) 1201 { 1202 return ice_write_port_eth56g(hw, port, offset, val, ETH56G_PHY_MEM_PTP); 1203 } 1204 1205 /** 1206 * ice_is_64b_phy_reg_eth56g - Check if this is a 64bit PHY register 1207 * @low_addr: the low address to check 1208 * @high_addr: on return, contains the high address of the 64bit register 1209 * 1210 * Write the appropriate high register offset to use. 1211 * 1212 * Return: true if the provided low address is one of the known 64bit PHY values 1213 * represented as two 32bit registers, false otherwise. 1214 */ 1215 static bool ice_is_64b_phy_reg_eth56g(u16 low_addr, u16 *high_addr) 1216 { 1217 switch (low_addr) { 1218 case PHY_REG_TX_TIMER_INC_PRE_L: 1219 *high_addr = PHY_REG_TX_TIMER_INC_PRE_U; 1220 return true; 1221 case PHY_REG_RX_TIMER_INC_PRE_L: 1222 *high_addr = PHY_REG_RX_TIMER_INC_PRE_U; 1223 return true; 1224 case PHY_REG_TX_CAPTURE_L: 1225 *high_addr = PHY_REG_TX_CAPTURE_U; 1226 return true; 1227 case PHY_REG_RX_CAPTURE_L: 1228 *high_addr = PHY_REG_RX_CAPTURE_U; 1229 return true; 1230 case PHY_REG_TOTAL_TX_OFFSET_L: 1231 *high_addr = PHY_REG_TOTAL_TX_OFFSET_U; 1232 return true; 1233 case PHY_REG_TOTAL_RX_OFFSET_L: 1234 *high_addr = PHY_REG_TOTAL_RX_OFFSET_U; 1235 return true; 1236 case PHY_REG_TX_MEMORY_STATUS_L: 1237 *high_addr = PHY_REG_TX_MEMORY_STATUS_U; 1238 return true; 1239 default: 1240 return false; 1241 } 1242 } 1243 1244 /** 1245 * ice_is_40b_phy_reg_eth56g - Check if this is a 40bit PHY register 1246 * @low_addr: the low address to check 1247 * @high_addr: on return, contains the high address of the 40bit value 1248 * 1249 * Write the appropriate high register offset to use. 1250 * 1251 * Return: true if the provided low address is one of the known 40bit PHY 1252 * values split into two registers with the lower 8 bits in the low register and 1253 * the upper 32 bits in the high register, false otherwise. 1254 */ 1255 static bool ice_is_40b_phy_reg_eth56g(u16 low_addr, u16 *high_addr) 1256 { 1257 switch (low_addr) { 1258 case PHY_REG_TIMETUS_L: 1259 *high_addr = PHY_REG_TIMETUS_U; 1260 return true; 1261 case PHY_PCS_REF_TUS_L: 1262 *high_addr = PHY_PCS_REF_TUS_U; 1263 return true; 1264 case PHY_PCS_REF_INC_L: 1265 *high_addr = PHY_PCS_REF_INC_U; 1266 return true; 1267 default: 1268 return false; 1269 } 1270 } 1271 1272 /** 1273 * ice_read_64b_phy_reg_eth56g - Read a 64bit value from PHY registers 1274 * @hw: pointer to the HW struct 1275 * @port: PHY port to read from 1276 * @low_addr: offset of the lower register to read from 1277 * @val: on return, the contents of the 64bit value from the PHY registers 1278 * @res_type: resource type 1279 * 1280 * Check if the caller has specified a known 40 bit register offset and read 1281 * the two registers associated with a 40bit value and return it in the val 1282 * pointer. 1283 * 1284 * Return: 1285 * * %0 - success 1286 * * %EINVAL - not a 64 bit register 1287 * * %other - failed to read from PHY 1288 */ 1289 static int ice_read_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, 1290 u64 *val, enum eth56g_res_type res_type) 1291 { 1292 u16 high_addr; 1293 u32 lo, hi; 1294 int err; 1295 1296 if (!ice_is_64b_phy_reg_eth56g(low_addr, &high_addr)) 1297 return -EINVAL; 1298 1299 err = ice_read_port_eth56g(hw, port, low_addr, &lo, res_type); 1300 if (err) { 1301 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register %#08x\n, err %d", 1302 low_addr, err); 1303 return err; 1304 } 1305 1306 err = ice_read_port_eth56g(hw, port, high_addr, &hi, res_type); 1307 if (err) { 1308 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register %#08x\n, err %d", 1309 high_addr, err); 1310 return err; 1311 } 1312 1313 *val = ((u64)hi << 32) | lo; 1314 1315 return 0; 1316 } 1317 1318 /** 1319 * ice_read_64b_ptp_reg_eth56g - Read a 64bit value from PHY registers 1320 * @hw: pointer to the HW struct 1321 * @port: PHY port to read from 1322 * @low_addr: offset of the lower register to read from 1323 * @val: on return, the contents of the 64bit value from the PHY registers 1324 * 1325 * Check if the caller has specified a known 40 bit register offset and read 1326 * the two registers associated with a 40bit value and return it in the val 1327 * pointer. 1328 * 1329 * Return: 1330 * * %0 - success 1331 * * %EINVAL - not a 64 bit register 1332 * * %other - failed to read from PHY 1333 */ 1334 static int ice_read_64b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, 1335 u64 *val) 1336 { 1337 return ice_read_64b_phy_reg_eth56g(hw, port, low_addr, val, 1338 ETH56G_PHY_REG_PTP); 1339 } 1340 1341 /** 1342 * ice_write_40b_phy_reg_eth56g - Write a 40b value to the PHY 1343 * @hw: pointer to the HW struct 1344 * @port: port to write to 1345 * @low_addr: offset of the low register 1346 * @val: 40b value to write 1347 * @res_type: resource type 1348 * 1349 * Check if the caller has specified a known 40 bit register offset and write 1350 * provided 40b value to the two associated registers by splitting it up into 1351 * two chunks, the lower 8 bits and the upper 32 bits. 1352 * 1353 * Return: 1354 * * %0 - success 1355 * * %EINVAL - not a 40 bit register 1356 * * %other - failed to write to PHY 1357 */ 1358 static int ice_write_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port, 1359 u16 low_addr, u64 val, 1360 enum eth56g_res_type res_type) 1361 { 1362 u16 high_addr; 1363 u32 lo, hi; 1364 int err; 1365 1366 if (!ice_is_40b_phy_reg_eth56g(low_addr, &high_addr)) 1367 return -EINVAL; 1368 1369 lo = FIELD_GET(P_REG_40B_LOW_M, val); 1370 hi = (u32)(val >> P_REG_40B_HIGH_S); 1371 1372 err = ice_write_port_eth56g(hw, port, low_addr, lo, res_type); 1373 if (err) { 1374 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 1375 low_addr, err); 1376 return err; 1377 } 1378 1379 err = ice_write_port_eth56g(hw, port, high_addr, hi, res_type); 1380 if (err) { 1381 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 1382 high_addr, err); 1383 return err; 1384 } 1385 1386 return 0; 1387 } 1388 1389 /** 1390 * ice_write_40b_ptp_reg_eth56g - Write a 40b value to the PHY 1391 * @hw: pointer to the HW struct 1392 * @port: port to write to 1393 * @low_addr: offset of the low register 1394 * @val: 40b value to write 1395 * 1396 * Check if the caller has specified a known 40 bit register offset and write 1397 * provided 40b value to the two associated registers by splitting it up into 1398 * two chunks, the lower 8 bits and the upper 32 bits. 1399 * 1400 * Return: 1401 * * %0 - success 1402 * * %EINVAL - not a 40 bit register 1403 * * %other - failed to write to PHY 1404 */ 1405 static int ice_write_40b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, 1406 u16 low_addr, u64 val) 1407 { 1408 return ice_write_40b_phy_reg_eth56g(hw, port, low_addr, val, 1409 ETH56G_PHY_REG_PTP); 1410 } 1411 1412 /** 1413 * ice_write_64b_phy_reg_eth56g - Write a 64bit value to PHY registers 1414 * @hw: pointer to the HW struct 1415 * @port: PHY port to read from 1416 * @low_addr: offset of the lower register to read from 1417 * @val: the contents of the 64bit value to write to PHY 1418 * @res_type: resource type 1419 * 1420 * Check if the caller has specified a known 64 bit register offset and write 1421 * the 64bit value to the two associated 32bit PHY registers. 1422 * 1423 * Return: 1424 * * %0 - success 1425 * * %EINVAL - not a 64 bit register 1426 * * %other - failed to write to PHY 1427 */ 1428 static int ice_write_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, 1429 u16 low_addr, u64 val, 1430 enum eth56g_res_type res_type) 1431 { 1432 u16 high_addr; 1433 u32 lo, hi; 1434 int err; 1435 1436 if (!ice_is_64b_phy_reg_eth56g(low_addr, &high_addr)) 1437 return -EINVAL; 1438 1439 lo = lower_32_bits(val); 1440 hi = upper_32_bits(val); 1441 1442 err = ice_write_port_eth56g(hw, port, low_addr, lo, res_type); 1443 if (err) { 1444 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 1445 low_addr, err); 1446 return err; 1447 } 1448 1449 err = ice_write_port_eth56g(hw, port, high_addr, hi, res_type); 1450 if (err) { 1451 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 1452 high_addr, err); 1453 return err; 1454 } 1455 1456 return 0; 1457 } 1458 1459 /** 1460 * ice_write_64b_ptp_reg_eth56g - Write a 64bit value to PHY registers 1461 * @hw: pointer to the HW struct 1462 * @port: PHY port to read from 1463 * @low_addr: offset of the lower register to read from 1464 * @val: the contents of the 64bit value to write to PHY 1465 * 1466 * Check if the caller has specified a known 64 bit register offset and write 1467 * the 64bit value to the two associated 32bit PHY registers. 1468 * 1469 * Return: 1470 * * %0 - success 1471 * * %EINVAL - not a 64 bit register 1472 * * %other - failed to write to PHY 1473 */ 1474 static int ice_write_64b_ptp_reg_eth56g(struct ice_hw *hw, u8 port, 1475 u16 low_addr, u64 val) 1476 { 1477 return ice_write_64b_phy_reg_eth56g(hw, port, low_addr, val, 1478 ETH56G_PHY_REG_PTP); 1479 } 1480 1481 /** 1482 * ice_read_ptp_tstamp_eth56g - Read a PHY timestamp out of the port memory 1483 * @hw: pointer to the HW struct 1484 * @port: the port to read from 1485 * @idx: the timestamp index to read 1486 * @tstamp: on return, the 40bit timestamp value 1487 * 1488 * Read a 40bit timestamp value out of the two associated entries in the 1489 * port memory block of the internal PHYs of the 56G devices. 1490 * 1491 * Return: 1492 * * %0 - success 1493 * * %other - failed to read from PHY 1494 */ 1495 static int ice_read_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx, 1496 u64 *tstamp) 1497 { 1498 u16 lo_addr, hi_addr; 1499 u32 lo, hi; 1500 int err; 1501 1502 lo_addr = (u16)PHY_TSTAMP_L(idx); 1503 hi_addr = (u16)PHY_TSTAMP_U(idx); 1504 1505 err = ice_read_port_mem_eth56g(hw, port, lo_addr, &lo); 1506 if (err) { 1507 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 1508 err); 1509 return err; 1510 } 1511 1512 err = ice_read_port_mem_eth56g(hw, port, hi_addr, &hi); 1513 if (err) { 1514 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 1515 err); 1516 return err; 1517 } 1518 1519 /* For 56G based internal PHYs, the timestamp is reported with the 1520 * lower 8 bits in the low register, and the upper 32 bits in the high 1521 * register. 1522 */ 1523 *tstamp = ((u64)hi) << TS_PHY_HIGH_S | ((u64)lo & TS_PHY_LOW_M); 1524 1525 return 0; 1526 } 1527 1528 /** 1529 * ice_clear_ptp_tstamp_eth56g - Clear a timestamp from the quad block 1530 * @hw: pointer to the HW struct 1531 * @port: the quad to read from 1532 * @idx: the timestamp index to reset 1533 * 1534 * Read and then forcibly clear the timestamp index to ensure the valid bit is 1535 * cleared and the timestamp status bit is reset in the PHY port memory of 1536 * internal PHYs of the 56G devices. 1537 * 1538 * To directly clear the contents of the timestamp block entirely, discarding 1539 * all timestamp data at once, software should instead use 1540 * ice_ptp_reset_ts_memory_quad_eth56g(). 1541 * 1542 * This function should only be called on an idx whose bit is set according to 1543 * ice_get_phy_tx_tstamp_ready(). 1544 * 1545 * Return: 1546 * * %0 - success 1547 * * %other - failed to write to PHY 1548 */ 1549 static int ice_clear_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx) 1550 { 1551 u64 unused_tstamp; 1552 u16 lo_addr; 1553 int err; 1554 1555 /* Read the timestamp register to ensure the timestamp status bit is 1556 * cleared. 1557 */ 1558 err = ice_read_ptp_tstamp_eth56g(hw, port, idx, &unused_tstamp); 1559 if (err) { 1560 ice_debug(hw, ICE_DBG_PTP, "Failed to read the PHY timestamp register for port %u, idx %u, err %d\n", 1561 port, idx, err); 1562 } 1563 1564 lo_addr = (u16)PHY_TSTAMP_L(idx); 1565 1566 err = ice_write_port_mem_eth56g(hw, port, lo_addr, 0); 1567 if (err) { 1568 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for port %u, idx %u, err %d\n", 1569 port, idx, err); 1570 return err; 1571 } 1572 1573 return 0; 1574 } 1575 1576 /** 1577 * ice_ptp_reset_ts_memory_eth56g - Clear all timestamps from the port block 1578 * @hw: pointer to the HW struct 1579 */ 1580 static void ice_ptp_reset_ts_memory_eth56g(struct ice_hw *hw) 1581 { 1582 unsigned int port; 1583 1584 for (port = 0; port < hw->ptp.num_lports; port++) { 1585 ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L, 1586 0); 1587 ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_U, 1588 0); 1589 } 1590 } 1591 1592 /** 1593 * ice_ptp_prep_port_time_eth56g - Prepare one PHY port with initial time 1594 * @hw: pointer to the HW struct 1595 * @port: port number 1596 * @time: time to initialize the PHY port clocks to 1597 * 1598 * Write a new initial time value into registers of a specific PHY port. 1599 * 1600 * Return: 1601 * * %0 - success 1602 * * %other - failed to write to PHY 1603 */ 1604 static int ice_ptp_prep_port_time_eth56g(struct ice_hw *hw, u8 port, 1605 u64 time) 1606 { 1607 int err; 1608 1609 /* Tx case */ 1610 err = ice_write_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_L, 1611 time); 1612 if (err) 1613 return err; 1614 1615 /* Rx case */ 1616 return ice_write_64b_ptp_reg_eth56g(hw, port, 1617 PHY_REG_RX_TIMER_INC_PRE_L, time); 1618 } 1619 1620 /** 1621 * ice_ptp_prep_phy_time_eth56g - Prepare PHY port with initial time 1622 * @hw: pointer to the HW struct 1623 * @time: Time to initialize the PHY port clocks to 1624 * 1625 * Program the PHY port registers with a new initial time value. The port 1626 * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync 1627 * command. The time value is the upper 32 bits of the PHY timer, usually in 1628 * units of nominal nanoseconds. 1629 * 1630 * Return: 1631 * * %0 - success 1632 * * %other - failed to write to PHY 1633 */ 1634 static int ice_ptp_prep_phy_time_eth56g(struct ice_hw *hw, u32 time) 1635 { 1636 u64 phy_time; 1637 u8 port; 1638 1639 /* The time represents the upper 32 bits of the PHY timer, so we need 1640 * to shift to account for this when programming. 1641 */ 1642 phy_time = (u64)time << 32; 1643 1644 for (port = 0; port < hw->ptp.num_lports; port++) { 1645 int err; 1646 1647 err = ice_ptp_prep_port_time_eth56g(hw, port, phy_time); 1648 if (err) { 1649 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n", 1650 port, err); 1651 return err; 1652 } 1653 } 1654 1655 return 0; 1656 } 1657 1658 /** 1659 * ice_ptp_prep_port_adj_eth56g - Prepare a single port for time adjust 1660 * @hw: pointer to HW struct 1661 * @port: Port number to be programmed 1662 * @time: time in cycles to adjust the port clocks 1663 * 1664 * Program the port for an atomic adjustment by writing the Tx and Rx timer 1665 * registers. The atomic adjustment won't be completed until the driver issues 1666 * an ICE_PTP_ADJ_TIME command. 1667 * 1668 * Note that time is not in units of nanoseconds. It is in clock time 1669 * including the lower sub-nanosecond portion of the port timer. 1670 * 1671 * Negative adjustments are supported using 2s complement arithmetic. 1672 * 1673 * Return: 1674 * * %0 - success 1675 * * %other - failed to write to PHY 1676 */ 1677 static int ice_ptp_prep_port_adj_eth56g(struct ice_hw *hw, u8 port, s64 time) 1678 { 1679 u32 l_time, u_time; 1680 int err; 1681 1682 l_time = lower_32_bits(time); 1683 u_time = upper_32_bits(time); 1684 1685 /* Tx case */ 1686 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_L, 1687 l_time); 1688 if (err) 1689 goto exit_err; 1690 1691 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TIMER_INC_PRE_U, 1692 u_time); 1693 if (err) 1694 goto exit_err; 1695 1696 /* Rx case */ 1697 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TIMER_INC_PRE_L, 1698 l_time); 1699 if (err) 1700 goto exit_err; 1701 1702 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TIMER_INC_PRE_U, 1703 u_time); 1704 if (err) 1705 goto exit_err; 1706 1707 return 0; 1708 1709 exit_err: 1710 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n", 1711 port, err); 1712 return err; 1713 } 1714 1715 /** 1716 * ice_ptp_prep_phy_adj_eth56g - Prep PHY ports for a time adjustment 1717 * @hw: pointer to HW struct 1718 * @adj: adjustment in nanoseconds 1719 * 1720 * Prepare the PHY ports for an atomic time adjustment by programming the PHY 1721 * Tx and Rx port registers. The actual adjustment is completed by issuing an 1722 * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command. 1723 * 1724 * Return: 1725 * * %0 - success 1726 * * %other - failed to write to PHY 1727 */ 1728 static int ice_ptp_prep_phy_adj_eth56g(struct ice_hw *hw, s32 adj) 1729 { 1730 s64 cycles; 1731 u8 port; 1732 1733 /* The port clock supports adjustment of the sub-nanosecond portion of 1734 * the clock (lowest 32 bits). We shift the provided adjustment in 1735 * nanoseconds by 32 to calculate the appropriate adjustment to program 1736 * into the PHY ports. 1737 */ 1738 cycles = (s64)adj << 32; 1739 1740 for (port = 0; port < hw->ptp.num_lports; port++) { 1741 int err; 1742 1743 err = ice_ptp_prep_port_adj_eth56g(hw, port, cycles); 1744 if (err) 1745 return err; 1746 } 1747 1748 return 0; 1749 } 1750 1751 /** 1752 * ice_ptp_prep_phy_incval_eth56g - Prepare PHY ports for time adjustment 1753 * @hw: pointer to HW struct 1754 * @incval: new increment value to prepare 1755 * 1756 * Prepare each of the PHY ports for a new increment value by programming the 1757 * port's TIMETUS registers. The new increment value will be updated after 1758 * issuing an ICE_PTP_INIT_INCVAL command. 1759 * 1760 * Return: 1761 * * %0 - success 1762 * * %other - failed to write to PHY 1763 */ 1764 static int ice_ptp_prep_phy_incval_eth56g(struct ice_hw *hw, u64 incval) 1765 { 1766 u8 port; 1767 1768 for (port = 0; port < hw->ptp.num_lports; port++) { 1769 int err; 1770 1771 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_REG_TIMETUS_L, 1772 incval); 1773 if (err) { 1774 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n", 1775 port, err); 1776 return err; 1777 } 1778 } 1779 1780 return 0; 1781 } 1782 1783 /** 1784 * ice_ptp_read_port_capture_eth56g - Read a port's local time capture 1785 * @hw: pointer to HW struct 1786 * @port: Port number to read 1787 * @tx_ts: on return, the Tx port time capture 1788 * @rx_ts: on return, the Rx port time capture 1789 * 1790 * Read the port's Tx and Rx local time capture values. 1791 * 1792 * Return: 1793 * * %0 - success 1794 * * %other - failed to read from PHY 1795 */ 1796 static int ice_ptp_read_port_capture_eth56g(struct ice_hw *hw, u8 port, 1797 u64 *tx_ts, u64 *rx_ts) 1798 { 1799 int err; 1800 1801 /* Tx case */ 1802 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_CAPTURE_L, 1803 tx_ts); 1804 if (err) { 1805 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n", 1806 err); 1807 return err; 1808 } 1809 1810 ice_debug(hw, ICE_DBG_PTP, "tx_init = %#016llx\n", *tx_ts); 1811 1812 /* Rx case */ 1813 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_RX_CAPTURE_L, 1814 rx_ts); 1815 if (err) { 1816 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n", 1817 err); 1818 return err; 1819 } 1820 1821 ice_debug(hw, ICE_DBG_PTP, "rx_init = %#016llx\n", *rx_ts); 1822 1823 return 0; 1824 } 1825 1826 /** 1827 * ice_ptp_write_port_cmd_eth56g - Prepare a single PHY port for a timer command 1828 * @hw: pointer to HW struct 1829 * @port: Port to which cmd has to be sent 1830 * @cmd: Command to be sent to the port 1831 * 1832 * Prepare the requested port for an upcoming timer sync command. 1833 * 1834 * Return: 1835 * * %0 - success 1836 * * %other - failed to write to PHY 1837 */ 1838 static int ice_ptp_write_port_cmd_eth56g(struct ice_hw *hw, u8 port, 1839 enum ice_ptp_tmr_cmd cmd) 1840 { 1841 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 1842 int err; 1843 1844 /* Tx case */ 1845 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_TMR_CMD, val); 1846 if (err) { 1847 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n", 1848 err); 1849 return err; 1850 } 1851 1852 /* Rx case */ 1853 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_TMR_CMD, val); 1854 if (err) { 1855 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n", 1856 err); 1857 return err; 1858 } 1859 1860 return 0; 1861 } 1862 1863 /** 1864 * ice_phy_get_speed_eth56g - Get link speed based on PHY link type 1865 * @li: pointer to link information struct 1866 * 1867 * Return: simplified ETH56G PHY speed 1868 */ 1869 static enum ice_eth56g_link_spd 1870 ice_phy_get_speed_eth56g(struct ice_link_status *li) 1871 { 1872 u16 speed = ice_get_link_speed_based_on_phy_type(li->phy_type_low, 1873 li->phy_type_high); 1874 1875 switch (speed) { 1876 case ICE_AQ_LINK_SPEED_1000MB: 1877 return ICE_ETH56G_LNK_SPD_1G; 1878 case ICE_AQ_LINK_SPEED_2500MB: 1879 return ICE_ETH56G_LNK_SPD_2_5G; 1880 case ICE_AQ_LINK_SPEED_10GB: 1881 return ICE_ETH56G_LNK_SPD_10G; 1882 case ICE_AQ_LINK_SPEED_25GB: 1883 return ICE_ETH56G_LNK_SPD_25G; 1884 case ICE_AQ_LINK_SPEED_40GB: 1885 return ICE_ETH56G_LNK_SPD_40G; 1886 case ICE_AQ_LINK_SPEED_50GB: 1887 switch (li->phy_type_low) { 1888 case ICE_PHY_TYPE_LOW_50GBASE_SR: 1889 case ICE_PHY_TYPE_LOW_50GBASE_FR: 1890 case ICE_PHY_TYPE_LOW_50GBASE_LR: 1891 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4: 1892 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC: 1893 case ICE_PHY_TYPE_LOW_50G_AUI1: 1894 return ICE_ETH56G_LNK_SPD_50G; 1895 default: 1896 return ICE_ETH56G_LNK_SPD_50G2; 1897 } 1898 case ICE_AQ_LINK_SPEED_100GB: 1899 if (li->phy_type_high || 1900 li->phy_type_low == ICE_PHY_TYPE_LOW_100GBASE_SR2) 1901 return ICE_ETH56G_LNK_SPD_100G2; 1902 else 1903 return ICE_ETH56G_LNK_SPD_100G; 1904 default: 1905 return ICE_ETH56G_LNK_SPD_1G; 1906 } 1907 } 1908 1909 /** 1910 * ice_phy_cfg_parpcs_eth56g - Configure TUs per PAR/PCS clock cycle 1911 * @hw: pointer to the HW struct 1912 * @port: port to configure 1913 * 1914 * Configure the number of TUs for the PAR and PCS clocks used as part of the 1915 * timestamp calibration process. 1916 * 1917 * Return: 1918 * * %0 - success 1919 * * %other - PHY read/write failed 1920 */ 1921 static int ice_phy_cfg_parpcs_eth56g(struct ice_hw *hw, u8 port) 1922 { 1923 u8 port_blk = port & ~(ICE_PORTS_PER_QUAD - 1); 1924 u32 val; 1925 int err; 1926 1927 err = ice_write_xpcs_reg_eth56g(hw, port, PHY_VENDOR_TXLANE_THRESH, 1928 ICE_ETH56G_NOMINAL_THRESH4); 1929 if (err) { 1930 ice_debug(hw, ICE_DBG_PTP, "Failed to read VENDOR_TXLANE_THRESH, status: %d", 1931 err); 1932 return err; 1933 } 1934 1935 switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) { 1936 case ICE_ETH56G_LNK_SPD_1G: 1937 case ICE_ETH56G_LNK_SPD_2_5G: 1938 err = ice_read_ptp_reg_eth56g(hw, port_blk, 1939 PHY_GPCS_CONFIG_REG0, &val); 1940 if (err) { 1941 ice_debug(hw, ICE_DBG_PTP, "Failed to read PHY_GPCS_CONFIG_REG0, status: %d", 1942 err); 1943 return err; 1944 } 1945 1946 val &= ~PHY_GPCS_CONFIG_REG0_TX_THR_M; 1947 val |= FIELD_PREP(PHY_GPCS_CONFIG_REG0_TX_THR_M, 1948 ICE_ETH56G_NOMINAL_TX_THRESH); 1949 1950 err = ice_write_ptp_reg_eth56g(hw, port_blk, 1951 PHY_GPCS_CONFIG_REG0, val); 1952 if (err) { 1953 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_GPCS_CONFIG_REG0, status: %d", 1954 err); 1955 return err; 1956 } 1957 break; 1958 default: 1959 break; 1960 } 1961 1962 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_PCS_REF_TUS_L, 1963 ICE_ETH56G_NOMINAL_PCS_REF_TUS); 1964 if (err) { 1965 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_PCS_REF_TUS, status: %d", 1966 err); 1967 return err; 1968 } 1969 1970 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_PCS_REF_INC_L, 1971 ICE_ETH56G_NOMINAL_PCS_REF_INC); 1972 if (err) { 1973 ice_debug(hw, ICE_DBG_PTP, "Failed to write PHY_PCS_REF_INC, status: %d", 1974 err); 1975 return err; 1976 } 1977 1978 return 0; 1979 } 1980 1981 /** 1982 * ice_phy_cfg_ptp_1step_eth56g - Configure 1-step PTP settings 1983 * @hw: Pointer to the HW struct 1984 * @port: Port to configure 1985 * 1986 * Return: 1987 * * %0 - success 1988 * * %other - PHY read/write failed 1989 */ 1990 int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port) 1991 { 1992 u8 port_blk = port & ~(ICE_PORTS_PER_QUAD - 1); 1993 u8 blk_port = port & (ICE_PORTS_PER_QUAD - 1); 1994 bool enable, sfd_ena; 1995 u32 val, peer_delay; 1996 int err; 1997 1998 enable = hw->ptp.phy.eth56g.onestep_ena; 1999 peer_delay = hw->ptp.phy.eth56g.peer_delay; 2000 sfd_ena = hw->ptp.phy.eth56g.sfd_ena; 2001 2002 /* PHY_PTP_1STEP_CONFIG */ 2003 err = ice_read_ptp_reg_eth56g(hw, port_blk, PHY_PTP_1STEP_CONFIG, &val); 2004 if (err) 2005 return err; 2006 2007 if (enable) 2008 val |= blk_port; 2009 else 2010 val &= ~blk_port; 2011 2012 val &= ~(PHY_PTP_1STEP_T1S_UP64_M | PHY_PTP_1STEP_T1S_DELTA_M); 2013 2014 err = ice_write_ptp_reg_eth56g(hw, port_blk, PHY_PTP_1STEP_CONFIG, val); 2015 if (err) 2016 return err; 2017 2018 /* PHY_PTP_1STEP_PEER_DELAY */ 2019 val = FIELD_PREP(PHY_PTP_1STEP_PD_DELAY_M, peer_delay); 2020 if (peer_delay) 2021 val |= PHY_PTP_1STEP_PD_ADD_PD_M; 2022 val |= PHY_PTP_1STEP_PD_DLY_V_M; 2023 err = ice_write_ptp_reg_eth56g(hw, port_blk, 2024 PHY_PTP_1STEP_PEER_DELAY(blk_port), val); 2025 if (err) 2026 return err; 2027 2028 val &= ~PHY_PTP_1STEP_PD_DLY_V_M; 2029 err = ice_write_ptp_reg_eth56g(hw, port_blk, 2030 PHY_PTP_1STEP_PEER_DELAY(blk_port), val); 2031 if (err) 2032 return err; 2033 2034 /* PHY_MAC_XIF_MODE */ 2035 err = ice_read_mac_reg_eth56g(hw, port, PHY_MAC_XIF_MODE, &val); 2036 if (err) 2037 return err; 2038 2039 val &= ~(PHY_MAC_XIF_1STEP_ENA_M | PHY_MAC_XIF_TS_BIN_MODE_M | 2040 PHY_MAC_XIF_TS_SFD_ENA_M | PHY_MAC_XIF_GMII_TS_SEL_M); 2041 2042 switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) { 2043 case ICE_ETH56G_LNK_SPD_1G: 2044 case ICE_ETH56G_LNK_SPD_2_5G: 2045 val |= PHY_MAC_XIF_GMII_TS_SEL_M; 2046 break; 2047 default: 2048 break; 2049 } 2050 2051 val |= FIELD_PREP(PHY_MAC_XIF_1STEP_ENA_M, enable) | 2052 FIELD_PREP(PHY_MAC_XIF_TS_BIN_MODE_M, enable) | 2053 FIELD_PREP(PHY_MAC_XIF_TS_SFD_ENA_M, sfd_ena); 2054 2055 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_XIF_MODE, val); 2056 } 2057 2058 /** 2059 * mul_u32_u32_fx_q9 - Multiply two u32 fixed point Q9 values 2060 * @a: multiplier value 2061 * @b: multiplicand value 2062 * 2063 * Return: result of multiplication 2064 */ 2065 static u32 mul_u32_u32_fx_q9(u32 a, u32 b) 2066 { 2067 return (u32)(((u64)a * b) >> ICE_ETH56G_MAC_CFG_FRAC_W); 2068 } 2069 2070 /** 2071 * add_u32_u32_fx - Add two u32 fixed point values and discard overflow 2072 * @a: first value 2073 * @b: second value 2074 * 2075 * Return: result of addition 2076 */ 2077 static u32 add_u32_u32_fx(u32 a, u32 b) 2078 { 2079 return lower_32_bits(((u64)a + b)); 2080 } 2081 2082 /** 2083 * ice_ptp_calc_bitslip_eth56g - Calculate bitslip value 2084 * @hw: pointer to the HW struct 2085 * @port: port to configure 2086 * @bs: bitslip multiplier 2087 * @fc: FC-FEC enabled 2088 * @rs: RS-FEC enabled 2089 * @spd: link speed 2090 * 2091 * Return: calculated bitslip value 2092 */ 2093 static u32 ice_ptp_calc_bitslip_eth56g(struct ice_hw *hw, u8 port, u32 bs, 2094 bool fc, bool rs, 2095 enum ice_eth56g_link_spd spd) 2096 { 2097 u8 port_offset = port & (ICE_PORTS_PER_QUAD - 1); 2098 u8 port_blk = port & ~(ICE_PORTS_PER_QUAD - 1); 2099 u32 bitslip; 2100 int err; 2101 2102 if (!bs || rs) 2103 return 0; 2104 2105 if (spd == ICE_ETH56G_LNK_SPD_1G || spd == ICE_ETH56G_LNK_SPD_2_5G) 2106 err = ice_read_gpcs_reg_eth56g(hw, port, PHY_GPCS_BITSLIP, 2107 &bitslip); 2108 else 2109 err = ice_read_ptp_reg_eth56g(hw, port_blk, 2110 PHY_REG_SD_BIT_SLIP(port_offset), 2111 &bitslip); 2112 if (err) 2113 return 0; 2114 2115 if (spd == ICE_ETH56G_LNK_SPD_1G && !bitslip) { 2116 /* Bitslip register value of 0 corresponds to 10 so substitute 2117 * it for calculations 2118 */ 2119 bitslip = 10; 2120 } else if (spd == ICE_ETH56G_LNK_SPD_10G || 2121 spd == ICE_ETH56G_LNK_SPD_25G) { 2122 if (fc) 2123 bitslip = bitslip * 2 + 32; 2124 else 2125 bitslip = (u32)((s32)bitslip * -1 + 20); 2126 } 2127 2128 bitslip <<= ICE_ETH56G_MAC_CFG_FRAC_W; 2129 return mul_u32_u32_fx_q9(bitslip, bs); 2130 } 2131 2132 /** 2133 * ice_ptp_calc_deskew_eth56g - Calculate deskew value 2134 * @hw: pointer to the HW struct 2135 * @port: port to configure 2136 * @ds: deskew multiplier 2137 * @rs: RS-FEC enabled 2138 * @spd: link speed 2139 * 2140 * Return: calculated deskew value 2141 */ 2142 static u32 ice_ptp_calc_deskew_eth56g(struct ice_hw *hw, u8 port, u32 ds, 2143 bool rs, enum ice_eth56g_link_spd spd) 2144 { 2145 u32 deskew_i, deskew_f; 2146 int err; 2147 2148 if (!ds) 2149 return 0; 2150 2151 read_poll_timeout(ice_read_ptp_reg_eth56g, err, 2152 FIELD_GET(PHY_REG_DESKEW_0_VALID, deskew_i), 500, 2153 50 * USEC_PER_MSEC, false, hw, port, PHY_REG_DESKEW_0, 2154 &deskew_i); 2155 if (err) 2156 return err; 2157 2158 deskew_f = FIELD_GET(PHY_REG_DESKEW_0_RLEVEL_FRAC, deskew_i); 2159 deskew_i = FIELD_GET(PHY_REG_DESKEW_0_RLEVEL, deskew_i); 2160 2161 if (rs && spd == ICE_ETH56G_LNK_SPD_50G2) 2162 ds = 0x633; /* 3.1 */ 2163 else if (rs && spd == ICE_ETH56G_LNK_SPD_100G) 2164 ds = 0x31b; /* 1.552 */ 2165 2166 deskew_i = FIELD_PREP(ICE_ETH56G_MAC_CFG_RX_OFFSET_INT, deskew_i); 2167 /* Shift 3 fractional bits to the end of the integer part */ 2168 deskew_f <<= ICE_ETH56G_MAC_CFG_FRAC_W - PHY_REG_DESKEW_0_RLEVEL_FRAC_W; 2169 return mul_u32_u32_fx_q9(deskew_i | deskew_f, ds); 2170 } 2171 2172 /** 2173 * ice_phy_set_offsets_eth56g - Set Tx/Rx offset values 2174 * @hw: pointer to the HW struct 2175 * @port: port to configure 2176 * @spd: link speed 2177 * @cfg: structure to store output values 2178 * @fc: FC-FEC enabled 2179 * @rs: RS-FEC enabled 2180 * 2181 * Return: 2182 * * %0 - success 2183 * * %other - failed to write to PHY 2184 */ 2185 static int ice_phy_set_offsets_eth56g(struct ice_hw *hw, u8 port, 2186 enum ice_eth56g_link_spd spd, 2187 const struct ice_eth56g_mac_reg_cfg *cfg, 2188 bool fc, bool rs) 2189 { 2190 u32 rx_offset, tx_offset, bs_ds; 2191 bool onestep, sfd; 2192 2193 onestep = hw->ptp.phy.eth56g.onestep_ena; 2194 sfd = hw->ptp.phy.eth56g.sfd_ena; 2195 bs_ds = cfg->rx_offset.bs_ds; 2196 2197 if (fc) 2198 rx_offset = cfg->rx_offset.fc; 2199 else if (rs) 2200 rx_offset = cfg->rx_offset.rs; 2201 else 2202 rx_offset = cfg->rx_offset.no_fec; 2203 2204 rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.serdes); 2205 if (sfd) 2206 rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.sfd); 2207 2208 if (spd < ICE_ETH56G_LNK_SPD_40G) 2209 bs_ds = ice_ptp_calc_bitslip_eth56g(hw, port, bs_ds, fc, rs, 2210 spd); 2211 else 2212 bs_ds = ice_ptp_calc_deskew_eth56g(hw, port, bs_ds, rs, spd); 2213 rx_offset = add_u32_u32_fx(rx_offset, bs_ds); 2214 rx_offset &= ICE_ETH56G_MAC_CFG_RX_OFFSET_INT | 2215 ICE_ETH56G_MAC_CFG_RX_OFFSET_FRAC; 2216 2217 if (fc) 2218 tx_offset = cfg->tx_offset.fc; 2219 else if (rs) 2220 tx_offset = cfg->tx_offset.rs; 2221 else 2222 tx_offset = cfg->tx_offset.no_fec; 2223 tx_offset += cfg->tx_offset.serdes + cfg->tx_offset.sfd * sfd + 2224 cfg->tx_offset.onestep * onestep; 2225 2226 ice_write_mac_reg_eth56g(hw, port, PHY_MAC_RX_OFFSET, rx_offset); 2227 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TX_OFFSET, tx_offset); 2228 } 2229 2230 /** 2231 * ice_phy_cfg_mac_eth56g - Configure MAC for PTP 2232 * @hw: Pointer to the HW struct 2233 * @port: Port to configure 2234 * 2235 * Return: 2236 * * %0 - success 2237 * * %other - failed to write to PHY 2238 */ 2239 static int ice_phy_cfg_mac_eth56g(struct ice_hw *hw, u8 port) 2240 { 2241 const struct ice_eth56g_mac_reg_cfg *cfg; 2242 enum ice_eth56g_link_spd spd; 2243 struct ice_link_status *li; 2244 bool fc = false; 2245 bool rs = false; 2246 bool onestep; 2247 u32 val; 2248 int err; 2249 2250 onestep = hw->ptp.phy.eth56g.onestep_ena; 2251 li = &hw->port_info->phy.link_info; 2252 spd = ice_phy_get_speed_eth56g(li); 2253 if (!!(li->an_info & ICE_AQ_FEC_EN)) { 2254 if (spd == ICE_ETH56G_LNK_SPD_10G) { 2255 fc = true; 2256 } else { 2257 fc = !!(li->fec_info & ICE_AQ_LINK_25G_KR_FEC_EN); 2258 rs = !!(li->fec_info & ~ICE_AQ_LINK_25G_KR_FEC_EN); 2259 } 2260 } 2261 cfg = ð56g_mac_cfg[spd]; 2262 2263 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_RX_MODULO, 0); 2264 if (err) 2265 return err; 2266 2267 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TX_MODULO, 0); 2268 if (err) 2269 return err; 2270 2271 val = FIELD_PREP(PHY_MAC_TSU_CFG_TX_MODE_M, 2272 cfg->tx_mode.def + rs * cfg->tx_mode.rs) | 2273 FIELD_PREP(PHY_MAC_TSU_CFG_TX_MII_MK_DLY_M, cfg->tx_mk_dly) | 2274 FIELD_PREP(PHY_MAC_TSU_CFG_TX_MII_CW_DLY_M, 2275 cfg->tx_cw_dly.def + 2276 onestep * cfg->tx_cw_dly.onestep) | 2277 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MODE_M, 2278 cfg->rx_mode.def + rs * cfg->rx_mode.rs) | 2279 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MII_MK_DLY_M, 2280 cfg->rx_mk_dly.def + rs * cfg->rx_mk_dly.rs) | 2281 FIELD_PREP(PHY_MAC_TSU_CFG_RX_MII_CW_DLY_M, 2282 cfg->rx_cw_dly.def + rs * cfg->rx_cw_dly.rs) | 2283 FIELD_PREP(PHY_MAC_TSU_CFG_BLKS_PER_CLK_M, cfg->blks_per_clk); 2284 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_TSU_CONFIG, val); 2285 if (err) 2286 return err; 2287 2288 err = ice_write_mac_reg_eth56g(hw, port, PHY_MAC_BLOCKTIME, 2289 cfg->blktime); 2290 if (err) 2291 return err; 2292 2293 err = ice_phy_set_offsets_eth56g(hw, port, spd, cfg, fc, rs); 2294 if (err) 2295 return err; 2296 2297 if (spd == ICE_ETH56G_LNK_SPD_25G && !rs) 2298 val = 0; 2299 else 2300 val = cfg->mktime; 2301 2302 return ice_write_mac_reg_eth56g(hw, port, PHY_MAC_MARKERTIME, val); 2303 } 2304 2305 /** 2306 * ice_phy_cfg_intr_eth56g - Configure TX timestamp interrupt 2307 * @hw: pointer to the HW struct 2308 * @port: the timestamp port 2309 * @ena: enable or disable interrupt 2310 * @threshold: interrupt threshold 2311 * 2312 * Configure TX timestamp interrupt for the specified port 2313 * 2314 * Return: 2315 * * %0 - success 2316 * * %other - PHY read/write failed 2317 */ 2318 int ice_phy_cfg_intr_eth56g(struct ice_hw *hw, u8 port, bool ena, u8 threshold) 2319 { 2320 int err; 2321 u32 val; 2322 2323 err = ice_read_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, &val); 2324 if (err) 2325 return err; 2326 2327 if (ena) { 2328 val |= PHY_TS_INT_CONFIG_ENA_M; 2329 val &= ~PHY_TS_INT_CONFIG_THRESHOLD_M; 2330 val |= FIELD_PREP(PHY_TS_INT_CONFIG_THRESHOLD_M, threshold); 2331 } else { 2332 val &= ~PHY_TS_INT_CONFIG_ENA_M; 2333 } 2334 2335 return ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TS_INT_CONFIG, val); 2336 } 2337 2338 /** 2339 * ice_read_phy_and_phc_time_eth56g - Simultaneously capture PHC and PHY time 2340 * @hw: pointer to the HW struct 2341 * @port: the PHY port to read 2342 * @phy_time: on return, the 64bit PHY timer value 2343 * @phc_time: on return, the lower 64bits of PHC time 2344 * 2345 * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY 2346 * and PHC timer values. 2347 * 2348 * Return: 2349 * * %0 - success 2350 * * %other - PHY read/write failed 2351 */ 2352 static int ice_read_phy_and_phc_time_eth56g(struct ice_hw *hw, u8 port, 2353 u64 *phy_time, u64 *phc_time) 2354 { 2355 u64 tx_time, rx_time; 2356 u32 zo, lo; 2357 u8 tmr_idx; 2358 int err; 2359 2360 tmr_idx = ice_get_ptp_src_clock_index(hw); 2361 2362 /* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */ 2363 ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME); 2364 2365 /* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */ 2366 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME); 2367 if (err) 2368 return err; 2369 2370 /* Issue the sync to start the ICE_PTP_READ_TIME capture */ 2371 ice_ptp_exec_tmr_cmd(hw); 2372 2373 /* Read the captured PHC time from the shadow time registers */ 2374 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx)); 2375 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx)); 2376 *phc_time = (u64)lo << 32 | zo; 2377 2378 /* Read the captured PHY time from the PHY shadow registers */ 2379 err = ice_ptp_read_port_capture_eth56g(hw, port, &tx_time, &rx_time); 2380 if (err) 2381 return err; 2382 2383 /* If the PHY Tx and Rx timers don't match, log a warning message. 2384 * Note that this should not happen in normal circumstances since the 2385 * driver always programs them together. 2386 */ 2387 if (tx_time != rx_time) 2388 dev_warn(ice_hw_to_dev(hw), "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n", 2389 port, tx_time, rx_time); 2390 2391 *phy_time = tx_time; 2392 2393 return 0; 2394 } 2395 2396 /** 2397 * ice_sync_phy_timer_eth56g - Synchronize the PHY timer with PHC timer 2398 * @hw: pointer to the HW struct 2399 * @port: the PHY port to synchronize 2400 * 2401 * Perform an adjustment to ensure that the PHY and PHC timers are in sync. 2402 * This is done by issuing a ICE_PTP_READ_TIME command which triggers a 2403 * simultaneous read of the PHY timer and PHC timer. Then we use the 2404 * difference to calculate an appropriate 2s complement addition to add 2405 * to the PHY timer in order to ensure it reads the same value as the 2406 * primary PHC timer. 2407 * 2408 * Return: 2409 * * %0 - success 2410 * * %-EBUSY- failed to acquire PTP semaphore 2411 * * %other - PHY read/write failed 2412 */ 2413 static int ice_sync_phy_timer_eth56g(struct ice_hw *hw, u8 port) 2414 { 2415 u64 phc_time, phy_time, difference; 2416 int err; 2417 2418 if (!ice_ptp_lock(hw)) { 2419 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n"); 2420 return -EBUSY; 2421 } 2422 2423 err = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time, &phc_time); 2424 if (err) 2425 goto err_unlock; 2426 2427 /* Calculate the amount required to add to the port time in order for 2428 * it to match the PHC time. 2429 * 2430 * Note that the port adjustment is done using 2s complement 2431 * arithmetic. This is convenient since it means that we can simply 2432 * calculate the difference between the PHC time and the port time, 2433 * and it will be interpreted correctly. 2434 */ 2435 2436 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 2437 difference = phc_time - phy_time; 2438 2439 err = ice_ptp_prep_port_adj_eth56g(hw, port, (s64)difference); 2440 if (err) 2441 goto err_unlock; 2442 2443 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME); 2444 if (err) 2445 goto err_unlock; 2446 2447 /* Issue the sync to activate the time adjustment */ 2448 ice_ptp_exec_tmr_cmd(hw); 2449 2450 /* Re-capture the timer values to flush the command registers and 2451 * verify that the time was properly adjusted. 2452 */ 2453 err = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time, &phc_time); 2454 if (err) 2455 goto err_unlock; 2456 2457 dev_info(ice_hw_to_dev(hw), 2458 "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n", 2459 port, phy_time, phc_time); 2460 2461 err_unlock: 2462 ice_ptp_unlock(hw); 2463 return err; 2464 } 2465 2466 /** 2467 * ice_stop_phy_timer_eth56g - Stop the PHY clock timer 2468 * @hw: pointer to the HW struct 2469 * @port: the PHY port to stop 2470 * @soft_reset: if true, hold the SOFT_RESET bit of PHY_REG_PS 2471 * 2472 * Stop the clock of a PHY port. This must be done as part of the flow to 2473 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 2474 * initialized or when link speed changes. 2475 * 2476 * Return: 2477 * * %0 - success 2478 * * %other - failed to write to PHY 2479 */ 2480 int ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset) 2481 { 2482 int err; 2483 2484 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 0); 2485 if (err) 2486 return err; 2487 2488 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 0); 2489 if (err) 2490 return err; 2491 2492 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port); 2493 2494 return 0; 2495 } 2496 2497 /** 2498 * ice_start_phy_timer_eth56g - Start the PHY clock timer 2499 * @hw: pointer to the HW struct 2500 * @port: the PHY port to start 2501 * 2502 * Start the clock of a PHY port. This must be done as part of the flow to 2503 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 2504 * initialized or when link speed changes. 2505 * 2506 * Return: 2507 * * %0 - success 2508 * * %other - PHY read/write failed 2509 */ 2510 int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port) 2511 { 2512 u32 lo, hi; 2513 u64 incval; 2514 u8 tmr_idx; 2515 int err; 2516 2517 tmr_idx = ice_get_ptp_src_clock_index(hw); 2518 2519 err = ice_stop_phy_timer_eth56g(hw, port, false); 2520 if (err) 2521 return err; 2522 2523 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 2524 2525 err = ice_phy_cfg_parpcs_eth56g(hw, port); 2526 if (err) 2527 return err; 2528 2529 err = ice_phy_cfg_ptp_1step_eth56g(hw, port); 2530 if (err) 2531 return err; 2532 2533 err = ice_phy_cfg_mac_eth56g(hw, port); 2534 if (err) 2535 return err; 2536 2537 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 2538 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 2539 incval = (u64)hi << 32 | lo; 2540 2541 err = ice_write_40b_ptp_reg_eth56g(hw, port, PHY_REG_TIMETUS_L, incval); 2542 if (err) 2543 return err; 2544 2545 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL); 2546 if (err) 2547 return err; 2548 2549 ice_ptp_exec_tmr_cmd(hw); 2550 2551 err = ice_sync_phy_timer_eth56g(hw, port); 2552 if (err) 2553 return err; 2554 2555 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 1); 2556 if (err) 2557 return err; 2558 2559 err = ice_write_ptp_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 1); 2560 if (err) 2561 return err; 2562 2563 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port); 2564 2565 return 0; 2566 } 2567 2568 /** 2569 * ice_sb_access_ena_eth56g - Enable SB devices (PHY and others) access 2570 * @hw: pointer to HW struct 2571 * @enable: Enable or disable access 2572 * 2573 * Enable sideband devices (PHY and others) access. 2574 */ 2575 static void ice_sb_access_ena_eth56g(struct ice_hw *hw, bool enable) 2576 { 2577 u32 val = rd32(hw, PF_SB_REM_DEV_CTL); 2578 2579 if (enable) 2580 val |= BIT(eth56g_phy_0) | BIT(cgu) | BIT(eth56g_phy_1); 2581 else 2582 val &= ~(BIT(eth56g_phy_0) | BIT(cgu) | BIT(eth56g_phy_1)); 2583 2584 wr32(hw, PF_SB_REM_DEV_CTL, val); 2585 } 2586 2587 /** 2588 * ice_ptp_init_phc_eth56g - Perform E82X specific PHC initialization 2589 * @hw: pointer to HW struct 2590 * 2591 * Perform PHC initialization steps specific to E82X devices. 2592 * 2593 * Return: 2594 * * %0 - success 2595 * * %other - failed to initialize CGU 2596 */ 2597 static int ice_ptp_init_phc_eth56g(struct ice_hw *hw) 2598 { 2599 ice_sb_access_ena_eth56g(hw, true); 2600 /* Initialize the Clock Generation Unit */ 2601 return ice_init_cgu_e82x(hw); 2602 } 2603 2604 /** 2605 * ice_ptp_read_tx_hwtstamp_status_eth56g - Get TX timestamp status 2606 * @hw: pointer to the HW struct 2607 * @ts_status: the timestamp mask pointer 2608 * 2609 * Read the PHY Tx timestamp status mask indicating which ports have Tx 2610 * timestamps available. 2611 * 2612 * Return: 2613 * * %0 - success 2614 * * %other - failed to read from PHY 2615 */ 2616 int ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status) 2617 { 2618 const struct ice_eth56g_params *params = &hw->ptp.phy.eth56g; 2619 u8 phy, mask; 2620 u32 status; 2621 2622 mask = (1 << hw->ptp.ports_per_phy) - 1; 2623 *ts_status = 0; 2624 2625 for (phy = 0; phy < params->num_phys; phy++) { 2626 int err; 2627 2628 err = ice_read_phy_eth56g(hw, phy, PHY_PTP_INT_STATUS, &status); 2629 if (err) 2630 return err; 2631 2632 *ts_status |= (status & mask) << (phy * hw->ptp.ports_per_phy); 2633 } 2634 2635 ice_debug(hw, ICE_DBG_PTP, "PHY interrupt err: %x\n", *ts_status); 2636 2637 return 0; 2638 } 2639 2640 /** 2641 * ice_get_phy_tx_tstamp_ready_eth56g - Read the Tx memory status register 2642 * @hw: pointer to the HW struct 2643 * @port: the PHY port to read from 2644 * @tstamp_ready: contents of the Tx memory status register 2645 * 2646 * Read the PHY_REG_TX_MEMORY_STATUS register indicating which timestamps in 2647 * the PHY are ready. A set bit means the corresponding timestamp is valid and 2648 * ready to be captured from the PHY timestamp block. 2649 * 2650 * Return: 2651 * * %0 - success 2652 * * %other - failed to read from PHY 2653 */ 2654 static int ice_get_phy_tx_tstamp_ready_eth56g(struct ice_hw *hw, u8 port, 2655 u64 *tstamp_ready) 2656 { 2657 int err; 2658 2659 err = ice_read_64b_ptp_reg_eth56g(hw, port, PHY_REG_TX_MEMORY_STATUS_L, 2660 tstamp_ready); 2661 if (err) { 2662 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS for port %u, err %d\n", 2663 port, err); 2664 return err; 2665 } 2666 2667 return 0; 2668 } 2669 2670 /** 2671 * ice_is_muxed_topo - detect breakout 2x50G topology for E825C 2672 * @hw: pointer to the HW struct 2673 * 2674 * Return: true if it's 2x50 breakout topology, false otherwise 2675 */ 2676 static bool ice_is_muxed_topo(struct ice_hw *hw) 2677 { 2678 u8 link_topo; 2679 bool mux; 2680 u32 val; 2681 2682 val = rd32(hw, GLGEN_SWITCH_MODE_CONFIG); 2683 mux = FIELD_GET(GLGEN_SWITCH_MODE_CONFIG_25X4_QUAD_M, val); 2684 val = rd32(hw, GLGEN_MAC_LINK_TOPO); 2685 link_topo = FIELD_GET(GLGEN_MAC_LINK_TOPO_LINK_TOPO_M, val); 2686 2687 return (mux && link_topo == ICE_LINK_TOPO_UP_TO_2_LINKS); 2688 } 2689 2690 /** 2691 * ice_ptp_init_phy_e825c - initialize PHY parameters 2692 * @hw: pointer to the HW struct 2693 */ 2694 static void ice_ptp_init_phy_e825c(struct ice_hw *hw) 2695 { 2696 struct ice_ptp_hw *ptp = &hw->ptp; 2697 struct ice_eth56g_params *params; 2698 u8 phy; 2699 2700 ptp->phy_model = ICE_PHY_ETH56G; 2701 params = &ptp->phy.eth56g; 2702 params->onestep_ena = false; 2703 params->peer_delay = 0; 2704 params->sfd_ena = false; 2705 params->phy_addr[0] = eth56g_phy_0; 2706 params->phy_addr[1] = eth56g_phy_1; 2707 params->num_phys = 2; 2708 ptp->ports_per_phy = 4; 2709 ptp->num_lports = params->num_phys * ptp->ports_per_phy; 2710 2711 ice_sb_access_ena_eth56g(hw, true); 2712 for (phy = 0; phy < params->num_phys; phy++) { 2713 u32 phy_rev; 2714 int err; 2715 2716 err = ice_read_phy_eth56g(hw, phy, PHY_REG_REVISION, &phy_rev); 2717 if (err || phy_rev != PHY_REVISION_ETH56G) { 2718 ptp->phy_model = ICE_PHY_UNSUP; 2719 return; 2720 } 2721 } 2722 2723 ptp->is_2x50g_muxed_topo = ice_is_muxed_topo(hw); 2724 } 2725 2726 /* E822 family functions 2727 * 2728 * The following functions operate on the E822 family of devices. 2729 */ 2730 2731 /** 2732 * ice_fill_phy_msg_e82x - Fill message data for a PHY register access 2733 * @hw: pointer to the HW struct 2734 * @msg: the PHY message buffer to fill in 2735 * @port: the port to access 2736 * @offset: the register offset 2737 */ 2738 static void ice_fill_phy_msg_e82x(struct ice_hw *hw, 2739 struct ice_sbq_msg_input *msg, u8 port, 2740 u16 offset) 2741 { 2742 int phy_port, phy, quadtype; 2743 2744 phy_port = port % hw->ptp.ports_per_phy; 2745 phy = port / hw->ptp.ports_per_phy; 2746 quadtype = ICE_GET_QUAD_NUM(port) % 2747 ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy); 2748 2749 if (quadtype == 0) { 2750 msg->msg_addr_low = P_Q0_L(P_0_BASE + offset, phy_port); 2751 msg->msg_addr_high = P_Q0_H(P_0_BASE + offset, phy_port); 2752 } else { 2753 msg->msg_addr_low = P_Q1_L(P_4_BASE + offset, phy_port); 2754 msg->msg_addr_high = P_Q1_H(P_4_BASE + offset, phy_port); 2755 } 2756 2757 if (phy == 0) 2758 msg->dest_dev = rmn_0; 2759 else if (phy == 1) 2760 msg->dest_dev = rmn_1; 2761 else 2762 msg->dest_dev = rmn_2; 2763 } 2764 2765 /** 2766 * ice_is_64b_phy_reg_e82x - Check if this is a 64bit PHY register 2767 * @low_addr: the low address to check 2768 * @high_addr: on return, contains the high address of the 64bit register 2769 * 2770 * Checks if the provided low address is one of the known 64bit PHY values 2771 * represented as two 32bit registers. If it is, return the appropriate high 2772 * register offset to use. 2773 */ 2774 static bool ice_is_64b_phy_reg_e82x(u16 low_addr, u16 *high_addr) 2775 { 2776 switch (low_addr) { 2777 case P_REG_PAR_PCS_TX_OFFSET_L: 2778 *high_addr = P_REG_PAR_PCS_TX_OFFSET_U; 2779 return true; 2780 case P_REG_PAR_PCS_RX_OFFSET_L: 2781 *high_addr = P_REG_PAR_PCS_RX_OFFSET_U; 2782 return true; 2783 case P_REG_PAR_TX_TIME_L: 2784 *high_addr = P_REG_PAR_TX_TIME_U; 2785 return true; 2786 case P_REG_PAR_RX_TIME_L: 2787 *high_addr = P_REG_PAR_RX_TIME_U; 2788 return true; 2789 case P_REG_TOTAL_TX_OFFSET_L: 2790 *high_addr = P_REG_TOTAL_TX_OFFSET_U; 2791 return true; 2792 case P_REG_TOTAL_RX_OFFSET_L: 2793 *high_addr = P_REG_TOTAL_RX_OFFSET_U; 2794 return true; 2795 case P_REG_UIX66_10G_40G_L: 2796 *high_addr = P_REG_UIX66_10G_40G_U; 2797 return true; 2798 case P_REG_UIX66_25G_100G_L: 2799 *high_addr = P_REG_UIX66_25G_100G_U; 2800 return true; 2801 case P_REG_TX_CAPTURE_L: 2802 *high_addr = P_REG_TX_CAPTURE_U; 2803 return true; 2804 case P_REG_RX_CAPTURE_L: 2805 *high_addr = P_REG_RX_CAPTURE_U; 2806 return true; 2807 case P_REG_TX_TIMER_INC_PRE_L: 2808 *high_addr = P_REG_TX_TIMER_INC_PRE_U; 2809 return true; 2810 case P_REG_RX_TIMER_INC_PRE_L: 2811 *high_addr = P_REG_RX_TIMER_INC_PRE_U; 2812 return true; 2813 default: 2814 return false; 2815 } 2816 } 2817 2818 /** 2819 * ice_is_40b_phy_reg_e82x - Check if this is a 40bit PHY register 2820 * @low_addr: the low address to check 2821 * @high_addr: on return, contains the high address of the 40bit value 2822 * 2823 * Checks if the provided low address is one of the known 40bit PHY values 2824 * split into two registers with the lower 8 bits in the low register and the 2825 * upper 32 bits in the high register. If it is, return the appropriate high 2826 * register offset to use. 2827 */ 2828 static bool ice_is_40b_phy_reg_e82x(u16 low_addr, u16 *high_addr) 2829 { 2830 switch (low_addr) { 2831 case P_REG_TIMETUS_L: 2832 *high_addr = P_REG_TIMETUS_U; 2833 return true; 2834 case P_REG_PAR_RX_TUS_L: 2835 *high_addr = P_REG_PAR_RX_TUS_U; 2836 return true; 2837 case P_REG_PAR_TX_TUS_L: 2838 *high_addr = P_REG_PAR_TX_TUS_U; 2839 return true; 2840 case P_REG_PCS_RX_TUS_L: 2841 *high_addr = P_REG_PCS_RX_TUS_U; 2842 return true; 2843 case P_REG_PCS_TX_TUS_L: 2844 *high_addr = P_REG_PCS_TX_TUS_U; 2845 return true; 2846 case P_REG_DESK_PAR_RX_TUS_L: 2847 *high_addr = P_REG_DESK_PAR_RX_TUS_U; 2848 return true; 2849 case P_REG_DESK_PAR_TX_TUS_L: 2850 *high_addr = P_REG_DESK_PAR_TX_TUS_U; 2851 return true; 2852 case P_REG_DESK_PCS_RX_TUS_L: 2853 *high_addr = P_REG_DESK_PCS_RX_TUS_U; 2854 return true; 2855 case P_REG_DESK_PCS_TX_TUS_L: 2856 *high_addr = P_REG_DESK_PCS_TX_TUS_U; 2857 return true; 2858 default: 2859 return false; 2860 } 2861 } 2862 2863 /** 2864 * ice_read_phy_reg_e82x - Read a PHY register 2865 * @hw: pointer to the HW struct 2866 * @port: PHY port to read from 2867 * @offset: PHY register offset to read 2868 * @val: on return, the contents read from the PHY 2869 * 2870 * Read a PHY register for the given port over the device sideband queue. 2871 */ 2872 static int 2873 ice_read_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 *val) 2874 { 2875 struct ice_sbq_msg_input msg = {0}; 2876 int err; 2877 2878 ice_fill_phy_msg_e82x(hw, &msg, port, offset); 2879 msg.opcode = ice_sbq_msg_rd; 2880 2881 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 2882 if (err) { 2883 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2884 err); 2885 return err; 2886 } 2887 2888 *val = msg.data; 2889 2890 return 0; 2891 } 2892 2893 /** 2894 * ice_read_64b_phy_reg_e82x - Read a 64bit value from PHY registers 2895 * @hw: pointer to the HW struct 2896 * @port: PHY port to read from 2897 * @low_addr: offset of the lower register to read from 2898 * @val: on return, the contents of the 64bit value from the PHY registers 2899 * 2900 * Reads the two registers associated with a 64bit value and returns it in the 2901 * val pointer. The offset always specifies the lower register offset to use. 2902 * The high offset is looked up. This function only operates on registers 2903 * known to be two parts of a 64bit value. 2904 */ 2905 static int 2906 ice_read_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val) 2907 { 2908 u32 low, high; 2909 u16 high_addr; 2910 int err; 2911 2912 /* Only operate on registers known to be split into two 32bit 2913 * registers. 2914 */ 2915 if (!ice_is_64b_phy_reg_e82x(low_addr, &high_addr)) { 2916 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n", 2917 low_addr); 2918 return -EINVAL; 2919 } 2920 2921 err = ice_read_phy_reg_e82x(hw, port, low_addr, &low); 2922 if (err) { 2923 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, err %d", 2924 low_addr, err); 2925 return err; 2926 } 2927 2928 err = ice_read_phy_reg_e82x(hw, port, high_addr, &high); 2929 if (err) { 2930 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, err %d", 2931 high_addr, err); 2932 return err; 2933 } 2934 2935 *val = (u64)high << 32 | low; 2936 2937 return 0; 2938 } 2939 2940 /** 2941 * ice_write_phy_reg_e82x - Write a PHY register 2942 * @hw: pointer to the HW struct 2943 * @port: PHY port to write to 2944 * @offset: PHY register offset to write 2945 * @val: The value to write to the register 2946 * 2947 * Write a PHY register for the given port over the device sideband queue. 2948 */ 2949 static int 2950 ice_write_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 offset, u32 val) 2951 { 2952 struct ice_sbq_msg_input msg = {0}; 2953 int err; 2954 2955 ice_fill_phy_msg_e82x(hw, &msg, port, offset); 2956 msg.opcode = ice_sbq_msg_wr; 2957 msg.data = val; 2958 2959 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 2960 if (err) { 2961 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2962 err); 2963 return err; 2964 } 2965 2966 return 0; 2967 } 2968 2969 /** 2970 * ice_write_40b_phy_reg_e82x - Write a 40b value to the PHY 2971 * @hw: pointer to the HW struct 2972 * @port: port to write to 2973 * @low_addr: offset of the low register 2974 * @val: 40b value to write 2975 * 2976 * Write the provided 40b value to the two associated registers by splitting 2977 * it up into two chunks, the lower 8 bits and the upper 32 bits. 2978 */ 2979 static int 2980 ice_write_40b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) 2981 { 2982 u32 low, high; 2983 u16 high_addr; 2984 int err; 2985 2986 /* Only operate on registers known to be split into a lower 8 bit 2987 * register and an upper 32 bit register. 2988 */ 2989 if (!ice_is_40b_phy_reg_e82x(low_addr, &high_addr)) { 2990 ice_debug(hw, ICE_DBG_PTP, "Invalid 40b register addr 0x%08x\n", 2991 low_addr); 2992 return -EINVAL; 2993 } 2994 low = FIELD_GET(P_REG_40B_LOW_M, val); 2995 high = (u32)(val >> P_REG_40B_HIGH_S); 2996 2997 err = ice_write_phy_reg_e82x(hw, port, low_addr, low); 2998 if (err) { 2999 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 3000 low_addr, err); 3001 return err; 3002 } 3003 3004 err = ice_write_phy_reg_e82x(hw, port, high_addr, high); 3005 if (err) { 3006 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 3007 high_addr, err); 3008 return err; 3009 } 3010 3011 return 0; 3012 } 3013 3014 /** 3015 * ice_write_64b_phy_reg_e82x - Write a 64bit value to PHY registers 3016 * @hw: pointer to the HW struct 3017 * @port: PHY port to read from 3018 * @low_addr: offset of the lower register to read from 3019 * @val: the contents of the 64bit value to write to PHY 3020 * 3021 * Write the 64bit value to the two associated 32bit PHY registers. The offset 3022 * is always specified as the lower register, and the high address is looked 3023 * up. This function only operates on registers known to be two parts of 3024 * a 64bit value. 3025 */ 3026 static int 3027 ice_write_64b_phy_reg_e82x(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) 3028 { 3029 u32 low, high; 3030 u16 high_addr; 3031 int err; 3032 3033 /* Only operate on registers known to be split into two 32bit 3034 * registers. 3035 */ 3036 if (!ice_is_64b_phy_reg_e82x(low_addr, &high_addr)) { 3037 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n", 3038 low_addr); 3039 return -EINVAL; 3040 } 3041 3042 low = lower_32_bits(val); 3043 high = upper_32_bits(val); 3044 3045 err = ice_write_phy_reg_e82x(hw, port, low_addr, low); 3046 if (err) { 3047 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 3048 low_addr, err); 3049 return err; 3050 } 3051 3052 err = ice_write_phy_reg_e82x(hw, port, high_addr, high); 3053 if (err) { 3054 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 3055 high_addr, err); 3056 return err; 3057 } 3058 3059 return 0; 3060 } 3061 3062 /** 3063 * ice_fill_quad_msg_e82x - Fill message data for quad register access 3064 * @hw: pointer to the HW struct 3065 * @msg: the PHY message buffer to fill in 3066 * @quad: the quad to access 3067 * @offset: the register offset 3068 * 3069 * Fill a message buffer for accessing a register in a quad shared between 3070 * multiple PHYs. 3071 * 3072 * Return: 3073 * * %0 - OK 3074 * * %-EINVAL - invalid quad number 3075 */ 3076 static int ice_fill_quad_msg_e82x(struct ice_hw *hw, 3077 struct ice_sbq_msg_input *msg, u8 quad, 3078 u16 offset) 3079 { 3080 u32 addr; 3081 3082 if (quad >= ICE_GET_QUAD_NUM(hw->ptp.num_lports)) 3083 return -EINVAL; 3084 3085 msg->dest_dev = rmn_0; 3086 3087 if (!(quad % ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy))) 3088 addr = Q_0_BASE + offset; 3089 else 3090 addr = Q_1_BASE + offset; 3091 3092 msg->msg_addr_low = lower_16_bits(addr); 3093 msg->msg_addr_high = upper_16_bits(addr); 3094 3095 return 0; 3096 } 3097 3098 /** 3099 * ice_read_quad_reg_e82x - Read a PHY quad register 3100 * @hw: pointer to the HW struct 3101 * @quad: quad to read from 3102 * @offset: quad register offset to read 3103 * @val: on return, the contents read from the quad 3104 * 3105 * Read a quad register over the device sideband queue. Quad registers are 3106 * shared between multiple PHYs. 3107 */ 3108 int 3109 ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val) 3110 { 3111 struct ice_sbq_msg_input msg = {0}; 3112 int err; 3113 3114 err = ice_fill_quad_msg_e82x(hw, &msg, quad, offset); 3115 if (err) 3116 return err; 3117 3118 msg.opcode = ice_sbq_msg_rd; 3119 3120 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 3121 if (err) { 3122 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 3123 err); 3124 return err; 3125 } 3126 3127 *val = msg.data; 3128 3129 return 0; 3130 } 3131 3132 /** 3133 * ice_write_quad_reg_e82x - Write a PHY quad register 3134 * @hw: pointer to the HW struct 3135 * @quad: quad to write to 3136 * @offset: quad register offset to write 3137 * @val: The value to write to the register 3138 * 3139 * Write a quad register over the device sideband queue. Quad registers are 3140 * shared between multiple PHYs. 3141 */ 3142 int 3143 ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val) 3144 { 3145 struct ice_sbq_msg_input msg = {0}; 3146 int err; 3147 3148 err = ice_fill_quad_msg_e82x(hw, &msg, quad, offset); 3149 if (err) 3150 return err; 3151 3152 msg.opcode = ice_sbq_msg_wr; 3153 msg.data = val; 3154 3155 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 3156 if (err) { 3157 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 3158 err); 3159 return err; 3160 } 3161 3162 return 0; 3163 } 3164 3165 /** 3166 * ice_read_phy_tstamp_e82x - Read a PHY timestamp out of the quad block 3167 * @hw: pointer to the HW struct 3168 * @quad: the quad to read from 3169 * @idx: the timestamp index to read 3170 * @tstamp: on return, the 40bit timestamp value 3171 * 3172 * Read a 40bit timestamp value out of the two associated registers in the 3173 * quad memory block that is shared between the internal PHYs of the E822 3174 * family of devices. 3175 */ 3176 static int 3177 ice_read_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp) 3178 { 3179 u16 lo_addr, hi_addr; 3180 u32 lo, hi; 3181 int err; 3182 3183 lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx); 3184 hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx); 3185 3186 err = ice_read_quad_reg_e82x(hw, quad, lo_addr, &lo); 3187 if (err) { 3188 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 3189 err); 3190 return err; 3191 } 3192 3193 err = ice_read_quad_reg_e82x(hw, quad, hi_addr, &hi); 3194 if (err) { 3195 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 3196 err); 3197 return err; 3198 } 3199 3200 /* For E822 based internal PHYs, the timestamp is reported with the 3201 * lower 8 bits in the low register, and the upper 32 bits in the high 3202 * register. 3203 */ 3204 *tstamp = FIELD_PREP(TS_PHY_HIGH_M, hi) | FIELD_PREP(TS_PHY_LOW_M, lo); 3205 3206 return 0; 3207 } 3208 3209 /** 3210 * ice_clear_phy_tstamp_e82x - Clear a timestamp from the quad block 3211 * @hw: pointer to the HW struct 3212 * @quad: the quad to read from 3213 * @idx: the timestamp index to reset 3214 * 3215 * Read the timestamp out of the quad to clear its timestamp status bit from 3216 * the PHY quad block that is shared between the internal PHYs of the E822 3217 * devices. 3218 * 3219 * Note that unlike E810, software cannot directly write to the quad memory 3220 * bank registers. E822 relies on the ice_get_phy_tx_tstamp_ready() function 3221 * to determine which timestamps are valid. Reading a timestamp auto-clears 3222 * the valid bit. 3223 * 3224 * To directly clear the contents of the timestamp block entirely, discarding 3225 * all timestamp data at once, software should instead use 3226 * ice_ptp_reset_ts_memory_quad_e82x(). 3227 * 3228 * This function should only be called on an idx whose bit is set according to 3229 * ice_get_phy_tx_tstamp_ready(). 3230 */ 3231 static int 3232 ice_clear_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx) 3233 { 3234 u64 unused_tstamp; 3235 int err; 3236 3237 err = ice_read_phy_tstamp_e82x(hw, quad, idx, &unused_tstamp); 3238 if (err) { 3239 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for quad %u, idx %u, err %d\n", 3240 quad, idx, err); 3241 return err; 3242 } 3243 3244 return 0; 3245 } 3246 3247 /** 3248 * ice_ptp_reset_ts_memory_quad_e82x - Clear all timestamps from the quad block 3249 * @hw: pointer to the HW struct 3250 * @quad: the quad to read from 3251 * 3252 * Clear all timestamps from the PHY quad block that is shared between the 3253 * internal PHYs on the E822 devices. 3254 */ 3255 void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad) 3256 { 3257 ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M); 3258 ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M); 3259 } 3260 3261 /** 3262 * ice_ptp_reset_ts_memory_e82x - Clear all timestamps from all quad blocks 3263 * @hw: pointer to the HW struct 3264 */ 3265 static void ice_ptp_reset_ts_memory_e82x(struct ice_hw *hw) 3266 { 3267 unsigned int quad; 3268 3269 for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports); quad++) 3270 ice_ptp_reset_ts_memory_quad_e82x(hw, quad); 3271 } 3272 3273 /** 3274 * ice_ptp_set_vernier_wl - Set the window length for vernier calibration 3275 * @hw: pointer to the HW struct 3276 * 3277 * Set the window length used for the vernier port calibration process. 3278 */ 3279 static int ice_ptp_set_vernier_wl(struct ice_hw *hw) 3280 { 3281 u8 port; 3282 3283 for (port = 0; port < hw->ptp.num_lports; port++) { 3284 int err; 3285 3286 err = ice_write_phy_reg_e82x(hw, port, P_REG_WL, 3287 PTP_VERNIER_WL); 3288 if (err) { 3289 ice_debug(hw, ICE_DBG_PTP, "Failed to set vernier window length for port %u, err %d\n", 3290 port, err); 3291 return err; 3292 } 3293 } 3294 3295 return 0; 3296 } 3297 3298 /** 3299 * ice_ptp_init_phc_e82x - Perform E822 specific PHC initialization 3300 * @hw: pointer to HW struct 3301 * 3302 * Perform PHC initialization steps specific to E822 devices. 3303 */ 3304 static int ice_ptp_init_phc_e82x(struct ice_hw *hw) 3305 { 3306 int err; 3307 u32 val; 3308 3309 /* Enable reading switch and PHY registers over the sideband queue */ 3310 #define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1) 3311 #define PF_SB_REM_DEV_CTL_PHY0 BIT(2) 3312 val = rd32(hw, PF_SB_REM_DEV_CTL); 3313 val |= (PF_SB_REM_DEV_CTL_SWITCH_READ | PF_SB_REM_DEV_CTL_PHY0); 3314 wr32(hw, PF_SB_REM_DEV_CTL, val); 3315 3316 /* Initialize the Clock Generation Unit */ 3317 err = ice_init_cgu_e82x(hw); 3318 if (err) 3319 return err; 3320 3321 /* Set window length for all the ports */ 3322 return ice_ptp_set_vernier_wl(hw); 3323 } 3324 3325 /** 3326 * ice_ptp_prep_phy_time_e82x - Prepare PHY port with initial time 3327 * @hw: pointer to the HW struct 3328 * @time: Time to initialize the PHY port clocks to 3329 * 3330 * Program the PHY port registers with a new initial time value. The port 3331 * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync 3332 * command. The time value is the upper 32 bits of the PHY timer, usually in 3333 * units of nominal nanoseconds. 3334 */ 3335 static int 3336 ice_ptp_prep_phy_time_e82x(struct ice_hw *hw, u32 time) 3337 { 3338 u64 phy_time; 3339 u8 port; 3340 int err; 3341 3342 /* The time represents the upper 32 bits of the PHY timer, so we need 3343 * to shift to account for this when programming. 3344 */ 3345 phy_time = (u64)time << 32; 3346 3347 for (port = 0; port < hw->ptp.num_lports; port++) { 3348 /* Tx case */ 3349 err = ice_write_64b_phy_reg_e82x(hw, port, 3350 P_REG_TX_TIMER_INC_PRE_L, 3351 phy_time); 3352 if (err) 3353 goto exit_err; 3354 3355 /* Rx case */ 3356 err = ice_write_64b_phy_reg_e82x(hw, port, 3357 P_REG_RX_TIMER_INC_PRE_L, 3358 phy_time); 3359 if (err) 3360 goto exit_err; 3361 } 3362 3363 return 0; 3364 3365 exit_err: 3366 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n", 3367 port, err); 3368 3369 return err; 3370 } 3371 3372 /** 3373 * ice_ptp_prep_port_adj_e82x - Prepare a single port for time adjust 3374 * @hw: pointer to HW struct 3375 * @port: Port number to be programmed 3376 * @time: time in cycles to adjust the port Tx and Rx clocks 3377 * 3378 * Program the port for an atomic adjustment by writing the Tx and Rx timer 3379 * registers. The atomic adjustment won't be completed until the driver issues 3380 * an ICE_PTP_ADJ_TIME command. 3381 * 3382 * Note that time is not in units of nanoseconds. It is in clock time 3383 * including the lower sub-nanosecond portion of the port timer. 3384 * 3385 * Negative adjustments are supported using 2s complement arithmetic. 3386 */ 3387 static int 3388 ice_ptp_prep_port_adj_e82x(struct ice_hw *hw, u8 port, s64 time) 3389 { 3390 u32 l_time, u_time; 3391 int err; 3392 3393 l_time = lower_32_bits(time); 3394 u_time = upper_32_bits(time); 3395 3396 /* Tx case */ 3397 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TIMER_INC_PRE_L, 3398 l_time); 3399 if (err) 3400 goto exit_err; 3401 3402 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TIMER_INC_PRE_U, 3403 u_time); 3404 if (err) 3405 goto exit_err; 3406 3407 /* Rx case */ 3408 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TIMER_INC_PRE_L, 3409 l_time); 3410 if (err) 3411 goto exit_err; 3412 3413 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TIMER_INC_PRE_U, 3414 u_time); 3415 if (err) 3416 goto exit_err; 3417 3418 return 0; 3419 3420 exit_err: 3421 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n", 3422 port, err); 3423 return err; 3424 } 3425 3426 /** 3427 * ice_ptp_prep_phy_adj_e82x - Prep PHY ports for a time adjustment 3428 * @hw: pointer to HW struct 3429 * @adj: adjustment in nanoseconds 3430 * 3431 * Prepare the PHY ports for an atomic time adjustment by programming the PHY 3432 * Tx and Rx port registers. The actual adjustment is completed by issuing an 3433 * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command. 3434 */ 3435 static int 3436 ice_ptp_prep_phy_adj_e82x(struct ice_hw *hw, s32 adj) 3437 { 3438 s64 cycles; 3439 u8 port; 3440 3441 /* The port clock supports adjustment of the sub-nanosecond portion of 3442 * the clock. We shift the provided adjustment in nanoseconds to 3443 * calculate the appropriate adjustment to program into the PHY ports. 3444 */ 3445 if (adj > 0) 3446 cycles = (s64)adj << 32; 3447 else 3448 cycles = -(((s64)-adj) << 32); 3449 3450 for (port = 0; port < hw->ptp.num_lports; port++) { 3451 int err; 3452 3453 err = ice_ptp_prep_port_adj_e82x(hw, port, cycles); 3454 if (err) 3455 return err; 3456 } 3457 3458 return 0; 3459 } 3460 3461 /** 3462 * ice_ptp_prep_phy_incval_e82x - Prepare PHY ports for time adjustment 3463 * @hw: pointer to HW struct 3464 * @incval: new increment value to prepare 3465 * 3466 * Prepare each of the PHY ports for a new increment value by programming the 3467 * port's TIMETUS registers. The new increment value will be updated after 3468 * issuing an ICE_PTP_INIT_INCVAL command. 3469 */ 3470 static int 3471 ice_ptp_prep_phy_incval_e82x(struct ice_hw *hw, u64 incval) 3472 { 3473 int err; 3474 u8 port; 3475 3476 for (port = 0; port < hw->ptp.num_lports; port++) { 3477 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L, 3478 incval); 3479 if (err) 3480 goto exit_err; 3481 } 3482 3483 return 0; 3484 3485 exit_err: 3486 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n", 3487 port, err); 3488 3489 return err; 3490 } 3491 3492 /** 3493 * ice_ptp_read_port_capture - Read a port's local time capture 3494 * @hw: pointer to HW struct 3495 * @port: Port number to read 3496 * @tx_ts: on return, the Tx port time capture 3497 * @rx_ts: on return, the Rx port time capture 3498 * 3499 * Read the port's Tx and Rx local time capture values. 3500 * 3501 * Note this has no equivalent for the E810 devices. 3502 */ 3503 static int 3504 ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts) 3505 { 3506 int err; 3507 3508 /* Tx case */ 3509 err = ice_read_64b_phy_reg_e82x(hw, port, P_REG_TX_CAPTURE_L, tx_ts); 3510 if (err) { 3511 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n", 3512 err); 3513 return err; 3514 } 3515 3516 ice_debug(hw, ICE_DBG_PTP, "tx_init = 0x%016llx\n", 3517 (unsigned long long)*tx_ts); 3518 3519 /* Rx case */ 3520 err = ice_read_64b_phy_reg_e82x(hw, port, P_REG_RX_CAPTURE_L, rx_ts); 3521 if (err) { 3522 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n", 3523 err); 3524 return err; 3525 } 3526 3527 ice_debug(hw, ICE_DBG_PTP, "rx_init = 0x%016llx\n", 3528 (unsigned long long)*rx_ts); 3529 3530 return 0; 3531 } 3532 3533 /** 3534 * ice_ptp_write_port_cmd_e82x - Prepare a single PHY port for a timer command 3535 * @hw: pointer to HW struct 3536 * @port: Port to which cmd has to be sent 3537 * @cmd: Command to be sent to the port 3538 * 3539 * Prepare the requested port for an upcoming timer sync command. 3540 * 3541 * Note there is no equivalent of this operation on E810, as that device 3542 * always handles all external PHYs internally. 3543 * 3544 * Return: 3545 * * %0 - success 3546 * * %other - failed to write to PHY 3547 */ 3548 static int ice_ptp_write_port_cmd_e82x(struct ice_hw *hw, u8 port, 3549 enum ice_ptp_tmr_cmd cmd) 3550 { 3551 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 3552 int err; 3553 3554 /* Tx case */ 3555 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_TMR_CMD, val); 3556 if (err) { 3557 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n", 3558 err); 3559 return err; 3560 } 3561 3562 /* Rx case */ 3563 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_TMR_CMD, 3564 val | TS_CMD_RX_TYPE); 3565 if (err) { 3566 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n", 3567 err); 3568 return err; 3569 } 3570 3571 return 0; 3572 } 3573 3574 /* E822 Vernier calibration functions 3575 * 3576 * The following functions are used as part of the vernier calibration of 3577 * a port. This calibration increases the precision of the timestamps on the 3578 * port. 3579 */ 3580 3581 /** 3582 * ice_phy_get_speed_and_fec_e82x - Get link speed and FEC based on serdes mode 3583 * @hw: pointer to HW struct 3584 * @port: the port to read from 3585 * @link_out: if non-NULL, holds link speed on success 3586 * @fec_out: if non-NULL, holds FEC algorithm on success 3587 * 3588 * Read the serdes data for the PHY port and extract the link speed and FEC 3589 * algorithm. 3590 */ 3591 static int 3592 ice_phy_get_speed_and_fec_e82x(struct ice_hw *hw, u8 port, 3593 enum ice_ptp_link_spd *link_out, 3594 enum ice_ptp_fec_mode *fec_out) 3595 { 3596 enum ice_ptp_link_spd link; 3597 enum ice_ptp_fec_mode fec; 3598 u32 serdes; 3599 int err; 3600 3601 err = ice_read_phy_reg_e82x(hw, port, P_REG_LINK_SPEED, &serdes); 3602 if (err) { 3603 ice_debug(hw, ICE_DBG_PTP, "Failed to read serdes info\n"); 3604 return err; 3605 } 3606 3607 /* Determine the FEC algorithm */ 3608 fec = (enum ice_ptp_fec_mode)P_REG_LINK_SPEED_FEC_MODE(serdes); 3609 3610 serdes &= P_REG_LINK_SPEED_SERDES_M; 3611 3612 /* Determine the link speed */ 3613 if (fec == ICE_PTP_FEC_MODE_RS_FEC) { 3614 switch (serdes) { 3615 case ICE_PTP_SERDES_25G: 3616 link = ICE_PTP_LNK_SPD_25G_RS; 3617 break; 3618 case ICE_PTP_SERDES_50G: 3619 link = ICE_PTP_LNK_SPD_50G_RS; 3620 break; 3621 case ICE_PTP_SERDES_100G: 3622 link = ICE_PTP_LNK_SPD_100G_RS; 3623 break; 3624 default: 3625 return -EIO; 3626 } 3627 } else { 3628 switch (serdes) { 3629 case ICE_PTP_SERDES_1G: 3630 link = ICE_PTP_LNK_SPD_1G; 3631 break; 3632 case ICE_PTP_SERDES_10G: 3633 link = ICE_PTP_LNK_SPD_10G; 3634 break; 3635 case ICE_PTP_SERDES_25G: 3636 link = ICE_PTP_LNK_SPD_25G; 3637 break; 3638 case ICE_PTP_SERDES_40G: 3639 link = ICE_PTP_LNK_SPD_40G; 3640 break; 3641 case ICE_PTP_SERDES_50G: 3642 link = ICE_PTP_LNK_SPD_50G; 3643 break; 3644 default: 3645 return -EIO; 3646 } 3647 } 3648 3649 if (link_out) 3650 *link_out = link; 3651 if (fec_out) 3652 *fec_out = fec; 3653 3654 return 0; 3655 } 3656 3657 /** 3658 * ice_phy_cfg_lane_e82x - Configure PHY quad for single/multi-lane timestamp 3659 * @hw: pointer to HW struct 3660 * @port: to configure the quad for 3661 */ 3662 static void ice_phy_cfg_lane_e82x(struct ice_hw *hw, u8 port) 3663 { 3664 enum ice_ptp_link_spd link_spd; 3665 int err; 3666 u32 val; 3667 u8 quad; 3668 3669 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, NULL); 3670 if (err) { 3671 ice_debug(hw, ICE_DBG_PTP, "Failed to get PHY link speed, err %d\n", 3672 err); 3673 return; 3674 } 3675 3676 quad = ICE_GET_QUAD_NUM(port); 3677 3678 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val); 3679 if (err) { 3680 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEM_GLB_CFG, err %d\n", 3681 err); 3682 return; 3683 } 3684 3685 if (link_spd >= ICE_PTP_LNK_SPD_40G) 3686 val &= ~Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M; 3687 else 3688 val |= Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M; 3689 3690 err = ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val); 3691 if (err) { 3692 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_MEM_GBL_CFG, err %d\n", 3693 err); 3694 return; 3695 } 3696 } 3697 3698 /** 3699 * ice_phy_cfg_uix_e82x - Configure Serdes UI to TU conversion for E822 3700 * @hw: pointer to the HW structure 3701 * @port: the port to configure 3702 * 3703 * Program the conversion ration of Serdes clock "unit intervals" (UIs) to PHC 3704 * hardware clock time units (TUs). That is, determine the number of TUs per 3705 * serdes unit interval, and program the UIX registers with this conversion. 3706 * 3707 * This conversion is used as part of the calibration process when determining 3708 * the additional error of a timestamp vs the real time of transmission or 3709 * receipt of the packet. 3710 * 3711 * Hardware uses the number of TUs per 66 UIs, written to the UIX registers 3712 * for the two main serdes clock rates, 10G/40G and 25G/100G serdes clocks. 3713 * 3714 * To calculate the conversion ratio, we use the following facts: 3715 * 3716 * a) the clock frequency in Hz (cycles per second) 3717 * b) the number of TUs per cycle (the increment value of the clock) 3718 * c) 1 second per 1 billion nanoseconds 3719 * d) the duration of 66 UIs in nanoseconds 3720 * 3721 * Given these facts, we can use the following table to work out what ratios 3722 * to multiply in order to get the number of TUs per 66 UIs: 3723 * 3724 * cycles | 1 second | incval (TUs) | nanoseconds 3725 * -------+--------------+--------------+------------- 3726 * second | 1 billion ns | cycle | 66 UIs 3727 * 3728 * To perform the multiplication using integers without too much loss of 3729 * precision, we can take use the following equation: 3730 * 3731 * (freq * incval * 6600 LINE_UI ) / ( 100 * 1 billion) 3732 * 3733 * We scale up to using 6600 UI instead of 66 in order to avoid fractional 3734 * nanosecond UIs (66 UI at 10G/40G is 6.4 ns) 3735 * 3736 * The increment value has a maximum expected range of about 34 bits, while 3737 * the frequency value is about 29 bits. Multiplying these values shouldn't 3738 * overflow the 64 bits. However, we must then further multiply them again by 3739 * the Serdes unit interval duration. To avoid overflow here, we split the 3740 * overall divide by 1e11 into a divide by 256 (shift down by 8 bits) and 3741 * a divide by 390,625,000. This does lose some precision, but avoids 3742 * miscalculation due to arithmetic overflow. 3743 */ 3744 static int ice_phy_cfg_uix_e82x(struct ice_hw *hw, u8 port) 3745 { 3746 u64 cur_freq, clk_incval, tu_per_sec, uix; 3747 int err; 3748 3749 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3750 clk_incval = ice_ptp_read_src_incval(hw); 3751 3752 /* Calculate TUs per second divided by 256 */ 3753 tu_per_sec = (cur_freq * clk_incval) >> 8; 3754 3755 #define LINE_UI_10G_40G 640 /* 6600 UIs is 640 nanoseconds at 10Gb/40Gb */ 3756 #define LINE_UI_25G_100G 256 /* 6600 UIs is 256 nanoseconds at 25Gb/100Gb */ 3757 3758 /* Program the 10Gb/40Gb conversion ratio */ 3759 uix = div_u64(tu_per_sec * LINE_UI_10G_40G, 390625000); 3760 3761 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_UIX66_10G_40G_L, 3762 uix); 3763 if (err) { 3764 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_10G_40G, err %d\n", 3765 err); 3766 return err; 3767 } 3768 3769 /* Program the 25Gb/100Gb conversion ratio */ 3770 uix = div_u64(tu_per_sec * LINE_UI_25G_100G, 390625000); 3771 3772 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_UIX66_25G_100G_L, 3773 uix); 3774 if (err) { 3775 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_25G_100G, err %d\n", 3776 err); 3777 return err; 3778 } 3779 3780 return 0; 3781 } 3782 3783 /** 3784 * ice_phy_cfg_parpcs_e82x - Configure TUs per PAR/PCS clock cycle 3785 * @hw: pointer to the HW struct 3786 * @port: port to configure 3787 * 3788 * Configure the number of TUs for the PAR and PCS clocks used as part of the 3789 * timestamp calibration process. This depends on the link speed, as the PHY 3790 * uses different markers depending on the speed. 3791 * 3792 * 1Gb/10Gb/25Gb: 3793 * - Tx/Rx PAR/PCS markers 3794 * 3795 * 25Gb RS: 3796 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers 3797 * 3798 * 40Gb/50Gb: 3799 * - Tx/Rx PAR/PCS markers 3800 * - Rx Deskew PAR/PCS markers 3801 * 3802 * 50G RS and 100GB RS: 3803 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers 3804 * - Rx Deskew PAR/PCS markers 3805 * - Tx PAR/PCS markers 3806 * 3807 * To calculate the conversion, we use the PHC clock frequency (cycles per 3808 * second), the increment value (TUs per cycle), and the related PHY clock 3809 * frequency to calculate the TUs per unit of the PHY link clock. The 3810 * following table shows how the units convert: 3811 * 3812 * cycles | TUs | second 3813 * -------+-------+-------- 3814 * second | cycle | cycles 3815 * 3816 * For each conversion register, look up the appropriate frequency from the 3817 * e822 PAR/PCS table and calculate the TUs per unit of that clock. Program 3818 * this to the appropriate register, preparing hardware to perform timestamp 3819 * calibration to calculate the total Tx or Rx offset to adjust the timestamp 3820 * in order to calibrate for the internal PHY delays. 3821 * 3822 * Note that the increment value ranges up to ~34 bits, and the clock 3823 * frequency is ~29 bits, so multiplying them together should fit within the 3824 * 64 bit arithmetic. 3825 */ 3826 static int ice_phy_cfg_parpcs_e82x(struct ice_hw *hw, u8 port) 3827 { 3828 u64 cur_freq, clk_incval, tu_per_sec, phy_tus; 3829 enum ice_ptp_link_spd link_spd; 3830 enum ice_ptp_fec_mode fec_mode; 3831 int err; 3832 3833 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode); 3834 if (err) 3835 return err; 3836 3837 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3838 clk_incval = ice_ptp_read_src_incval(hw); 3839 3840 /* Calculate TUs per cycle of the PHC clock */ 3841 tu_per_sec = cur_freq * clk_incval; 3842 3843 /* For each PHY conversion register, look up the appropriate link 3844 * speed frequency and determine the TUs per that clock's cycle time. 3845 * Split this into a high and low value and then program the 3846 * appropriate register. If that link speed does not use the 3847 * associated register, write zeros to clear it instead. 3848 */ 3849 3850 /* P_REG_PAR_TX_TUS */ 3851 if (e822_vernier[link_spd].tx_par_clk) 3852 phy_tus = div_u64(tu_per_sec, 3853 e822_vernier[link_spd].tx_par_clk); 3854 else 3855 phy_tus = 0; 3856 3857 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PAR_TX_TUS_L, 3858 phy_tus); 3859 if (err) 3860 return err; 3861 3862 /* P_REG_PAR_RX_TUS */ 3863 if (e822_vernier[link_spd].rx_par_clk) 3864 phy_tus = div_u64(tu_per_sec, 3865 e822_vernier[link_spd].rx_par_clk); 3866 else 3867 phy_tus = 0; 3868 3869 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PAR_RX_TUS_L, 3870 phy_tus); 3871 if (err) 3872 return err; 3873 3874 /* P_REG_PCS_TX_TUS */ 3875 if (e822_vernier[link_spd].tx_pcs_clk) 3876 phy_tus = div_u64(tu_per_sec, 3877 e822_vernier[link_spd].tx_pcs_clk); 3878 else 3879 phy_tus = 0; 3880 3881 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PCS_TX_TUS_L, 3882 phy_tus); 3883 if (err) 3884 return err; 3885 3886 /* P_REG_PCS_RX_TUS */ 3887 if (e822_vernier[link_spd].rx_pcs_clk) 3888 phy_tus = div_u64(tu_per_sec, 3889 e822_vernier[link_spd].rx_pcs_clk); 3890 else 3891 phy_tus = 0; 3892 3893 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_PCS_RX_TUS_L, 3894 phy_tus); 3895 if (err) 3896 return err; 3897 3898 /* P_REG_DESK_PAR_TX_TUS */ 3899 if (e822_vernier[link_spd].tx_desk_rsgb_par) 3900 phy_tus = div_u64(tu_per_sec, 3901 e822_vernier[link_spd].tx_desk_rsgb_par); 3902 else 3903 phy_tus = 0; 3904 3905 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PAR_TX_TUS_L, 3906 phy_tus); 3907 if (err) 3908 return err; 3909 3910 /* P_REG_DESK_PAR_RX_TUS */ 3911 if (e822_vernier[link_spd].rx_desk_rsgb_par) 3912 phy_tus = div_u64(tu_per_sec, 3913 e822_vernier[link_spd].rx_desk_rsgb_par); 3914 else 3915 phy_tus = 0; 3916 3917 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PAR_RX_TUS_L, 3918 phy_tus); 3919 if (err) 3920 return err; 3921 3922 /* P_REG_DESK_PCS_TX_TUS */ 3923 if (e822_vernier[link_spd].tx_desk_rsgb_pcs) 3924 phy_tus = div_u64(tu_per_sec, 3925 e822_vernier[link_spd].tx_desk_rsgb_pcs); 3926 else 3927 phy_tus = 0; 3928 3929 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PCS_TX_TUS_L, 3930 phy_tus); 3931 if (err) 3932 return err; 3933 3934 /* P_REG_DESK_PCS_RX_TUS */ 3935 if (e822_vernier[link_spd].rx_desk_rsgb_pcs) 3936 phy_tus = div_u64(tu_per_sec, 3937 e822_vernier[link_spd].rx_desk_rsgb_pcs); 3938 else 3939 phy_tus = 0; 3940 3941 return ice_write_40b_phy_reg_e82x(hw, port, P_REG_DESK_PCS_RX_TUS_L, 3942 phy_tus); 3943 } 3944 3945 /** 3946 * ice_calc_fixed_tx_offset_e82x - Calculated Fixed Tx offset for a port 3947 * @hw: pointer to the HW struct 3948 * @link_spd: the Link speed to calculate for 3949 * 3950 * Calculate the fixed offset due to known static latency data. 3951 */ 3952 static u64 3953 ice_calc_fixed_tx_offset_e82x(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) 3954 { 3955 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset; 3956 3957 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 3958 clk_incval = ice_ptp_read_src_incval(hw); 3959 3960 /* Calculate TUs per second */ 3961 tu_per_sec = cur_freq * clk_incval; 3962 3963 /* Calculate number of TUs to add for the fixed Tx latency. Since the 3964 * latency measurement is in 1/100th of a nanosecond, we need to 3965 * multiply by tu_per_sec and then divide by 1e11. This calculation 3966 * overflows 64 bit integer arithmetic, so break it up into two 3967 * divisions by 1e4 first then by 1e7. 3968 */ 3969 fixed_offset = div_u64(tu_per_sec, 10000); 3970 fixed_offset *= e822_vernier[link_spd].tx_fixed_delay; 3971 fixed_offset = div_u64(fixed_offset, 10000000); 3972 3973 return fixed_offset; 3974 } 3975 3976 /** 3977 * ice_phy_cfg_tx_offset_e82x - Configure total Tx timestamp offset 3978 * @hw: pointer to the HW struct 3979 * @port: the PHY port to configure 3980 * 3981 * Program the P_REG_TOTAL_TX_OFFSET register with the total number of TUs to 3982 * adjust Tx timestamps by. This is calculated by combining some known static 3983 * latency along with the Vernier offset computations done by hardware. 3984 * 3985 * This function will not return successfully until the Tx offset calculations 3986 * have been completed, which requires waiting until at least one packet has 3987 * been transmitted by the device. It is safe to call this function 3988 * periodically until calibration succeeds, as it will only program the offset 3989 * once. 3990 * 3991 * To avoid overflow, when calculating the offset based on the known static 3992 * latency values, we use measurements in 1/100th of a nanosecond, and divide 3993 * the TUs per second up front. This avoids overflow while allowing 3994 * calculation of the adjustment using integer arithmetic. 3995 * 3996 * Returns zero on success, -EBUSY if the hardware vernier offset 3997 * calibration has not completed, or another error code on failure. 3998 */ 3999 int ice_phy_cfg_tx_offset_e82x(struct ice_hw *hw, u8 port) 4000 { 4001 enum ice_ptp_link_spd link_spd; 4002 enum ice_ptp_fec_mode fec_mode; 4003 u64 total_offset, val; 4004 int err; 4005 u32 reg; 4006 4007 /* Nothing to do if we've already programmed the offset */ 4008 err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_OR, ®); 4009 if (err) { 4010 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OR for port %u, err %d\n", 4011 port, err); 4012 return err; 4013 } 4014 4015 if (reg) 4016 return 0; 4017 4018 err = ice_read_phy_reg_e82x(hw, port, P_REG_TX_OV_STATUS, ®); 4019 if (err) { 4020 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OV_STATUS for port %u, err %d\n", 4021 port, err); 4022 return err; 4023 } 4024 4025 if (!(reg & P_REG_TX_OV_STATUS_OV_M)) 4026 return -EBUSY; 4027 4028 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode); 4029 if (err) 4030 return err; 4031 4032 total_offset = ice_calc_fixed_tx_offset_e82x(hw, link_spd); 4033 4034 /* Read the first Vernier offset from the PHY register and add it to 4035 * the total offset. 4036 */ 4037 if (link_spd == ICE_PTP_LNK_SPD_1G || 4038 link_spd == ICE_PTP_LNK_SPD_10G || 4039 link_spd == ICE_PTP_LNK_SPD_25G || 4040 link_spd == ICE_PTP_LNK_SPD_25G_RS || 4041 link_spd == ICE_PTP_LNK_SPD_40G || 4042 link_spd == ICE_PTP_LNK_SPD_50G) { 4043 err = ice_read_64b_phy_reg_e82x(hw, port, 4044 P_REG_PAR_PCS_TX_OFFSET_L, 4045 &val); 4046 if (err) 4047 return err; 4048 4049 total_offset += val; 4050 } 4051 4052 /* For Tx, we only need to use the second Vernier offset for 4053 * multi-lane link speeds with RS-FEC. The lanes will always be 4054 * aligned. 4055 */ 4056 if (link_spd == ICE_PTP_LNK_SPD_50G_RS || 4057 link_spd == ICE_PTP_LNK_SPD_100G_RS) { 4058 err = ice_read_64b_phy_reg_e82x(hw, port, 4059 P_REG_PAR_TX_TIME_L, 4060 &val); 4061 if (err) 4062 return err; 4063 4064 total_offset += val; 4065 } 4066 4067 /* Now that the total offset has been calculated, program it to the 4068 * PHY and indicate that the Tx offset is ready. After this, 4069 * timestamps will be enabled. 4070 */ 4071 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_TOTAL_TX_OFFSET_L, 4072 total_offset); 4073 if (err) 4074 return err; 4075 4076 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 1); 4077 if (err) 4078 return err; 4079 4080 dev_info(ice_hw_to_dev(hw), "Port=%d Tx vernier offset calibration complete\n", 4081 port); 4082 4083 return 0; 4084 } 4085 4086 /** 4087 * ice_phy_calc_pmd_adj_e82x - Calculate PMD adjustment for Rx 4088 * @hw: pointer to the HW struct 4089 * @port: the PHY port to adjust for 4090 * @link_spd: the current link speed of the PHY 4091 * @fec_mode: the current FEC mode of the PHY 4092 * @pmd_adj: on return, the amount to adjust the Rx total offset by 4093 * 4094 * Calculates the adjustment to Rx timestamps due to PMD alignment in the PHY. 4095 * This varies by link speed and FEC mode. The value calculated accounts for 4096 * various delays caused when receiving a packet. 4097 */ 4098 static int 4099 ice_phy_calc_pmd_adj_e82x(struct ice_hw *hw, u8 port, 4100 enum ice_ptp_link_spd link_spd, 4101 enum ice_ptp_fec_mode fec_mode, u64 *pmd_adj) 4102 { 4103 u64 cur_freq, clk_incval, tu_per_sec, mult, adj; 4104 u8 pmd_align; 4105 u32 val; 4106 int err; 4107 4108 err = ice_read_phy_reg_e82x(hw, port, P_REG_PMD_ALIGNMENT, &val); 4109 if (err) { 4110 ice_debug(hw, ICE_DBG_PTP, "Failed to read PMD alignment, err %d\n", 4111 err); 4112 return err; 4113 } 4114 4115 pmd_align = (u8)val; 4116 4117 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 4118 clk_incval = ice_ptp_read_src_incval(hw); 4119 4120 /* Calculate TUs per second */ 4121 tu_per_sec = cur_freq * clk_incval; 4122 4123 /* The PMD alignment adjustment measurement depends on the link speed, 4124 * and whether FEC is enabled. For each link speed, the alignment 4125 * adjustment is calculated by dividing a value by the length of 4126 * a Time Unit in nanoseconds. 4127 * 4128 * 1G: align == 4 ? 10 * 0.8 : (align + 6 % 10) * 0.8 4129 * 10G: align == 65 ? 0 : (align * 0.1 * 32/33) 4130 * 10G w/FEC: align * 0.1 * 32/33 4131 * 25G: align == 65 ? 0 : (align * 0.4 * 32/33) 4132 * 25G w/FEC: align * 0.4 * 32/33 4133 * 40G: align == 65 ? 0 : (align * 0.1 * 32/33) 4134 * 40G w/FEC: align * 0.1 * 32/33 4135 * 50G: align == 65 ? 0 : (align * 0.4 * 32/33) 4136 * 50G w/FEC: align * 0.8 * 32/33 4137 * 4138 * For RS-FEC, if align is < 17 then we must also add 1.6 * 32/33. 4139 * 4140 * To allow for calculating this value using integer arithmetic, we 4141 * instead start with the number of TUs per second, (inverse of the 4142 * length of a Time Unit in nanoseconds), multiply by a value based 4143 * on the PMD alignment register, and then divide by the right value 4144 * calculated based on the table above. To avoid integer overflow this 4145 * division is broken up into a step of dividing by 125 first. 4146 */ 4147 if (link_spd == ICE_PTP_LNK_SPD_1G) { 4148 if (pmd_align == 4) 4149 mult = 10; 4150 else 4151 mult = (pmd_align + 6) % 10; 4152 } else if (link_spd == ICE_PTP_LNK_SPD_10G || 4153 link_spd == ICE_PTP_LNK_SPD_25G || 4154 link_spd == ICE_PTP_LNK_SPD_40G || 4155 link_spd == ICE_PTP_LNK_SPD_50G) { 4156 /* If Clause 74 FEC, always calculate PMD adjust */ 4157 if (pmd_align != 65 || fec_mode == ICE_PTP_FEC_MODE_CLAUSE74) 4158 mult = pmd_align; 4159 else 4160 mult = 0; 4161 } else if (link_spd == ICE_PTP_LNK_SPD_25G_RS || 4162 link_spd == ICE_PTP_LNK_SPD_50G_RS || 4163 link_spd == ICE_PTP_LNK_SPD_100G_RS) { 4164 if (pmd_align < 17) 4165 mult = pmd_align + 40; 4166 else 4167 mult = pmd_align; 4168 } else { 4169 ice_debug(hw, ICE_DBG_PTP, "Unknown link speed %d, skipping PMD adjustment\n", 4170 link_spd); 4171 mult = 0; 4172 } 4173 4174 /* In some cases, there's no need to adjust for the PMD alignment */ 4175 if (!mult) { 4176 *pmd_adj = 0; 4177 return 0; 4178 } 4179 4180 /* Calculate the adjustment by multiplying TUs per second by the 4181 * appropriate multiplier and divisor. To avoid overflow, we first 4182 * divide by 125, and then handle remaining divisor based on the link 4183 * speed pmd_adj_divisor value. 4184 */ 4185 adj = div_u64(tu_per_sec, 125); 4186 adj *= mult; 4187 adj = div_u64(adj, e822_vernier[link_spd].pmd_adj_divisor); 4188 4189 /* Finally, for 25G-RS and 50G-RS, a further adjustment for the Rx 4190 * cycle count is necessary. 4191 */ 4192 if (link_spd == ICE_PTP_LNK_SPD_25G_RS) { 4193 u64 cycle_adj; 4194 u8 rx_cycle; 4195 4196 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_40_TO_160_CNT, 4197 &val); 4198 if (err) { 4199 ice_debug(hw, ICE_DBG_PTP, "Failed to read 25G-RS Rx cycle count, err %d\n", 4200 err); 4201 return err; 4202 } 4203 4204 rx_cycle = val & P_REG_RX_40_TO_160_CNT_RXCYC_M; 4205 if (rx_cycle) { 4206 mult = (4 - rx_cycle) * 40; 4207 4208 cycle_adj = div_u64(tu_per_sec, 125); 4209 cycle_adj *= mult; 4210 cycle_adj = div_u64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor); 4211 4212 adj += cycle_adj; 4213 } 4214 } else if (link_spd == ICE_PTP_LNK_SPD_50G_RS) { 4215 u64 cycle_adj; 4216 u8 rx_cycle; 4217 4218 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_80_TO_160_CNT, 4219 &val); 4220 if (err) { 4221 ice_debug(hw, ICE_DBG_PTP, "Failed to read 50G-RS Rx cycle count, err %d\n", 4222 err); 4223 return err; 4224 } 4225 4226 rx_cycle = val & P_REG_RX_80_TO_160_CNT_RXCYC_M; 4227 if (rx_cycle) { 4228 mult = rx_cycle * 40; 4229 4230 cycle_adj = div_u64(tu_per_sec, 125); 4231 cycle_adj *= mult; 4232 cycle_adj = div_u64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor); 4233 4234 adj += cycle_adj; 4235 } 4236 } 4237 4238 /* Return the calculated adjustment */ 4239 *pmd_adj = adj; 4240 4241 return 0; 4242 } 4243 4244 /** 4245 * ice_calc_fixed_rx_offset_e82x - Calculated the fixed Rx offset for a port 4246 * @hw: pointer to HW struct 4247 * @link_spd: The Link speed to calculate for 4248 * 4249 * Determine the fixed Rx latency for a given link speed. 4250 */ 4251 static u64 4252 ice_calc_fixed_rx_offset_e82x(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) 4253 { 4254 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset; 4255 4256 cur_freq = ice_e82x_pll_freq(ice_e82x_time_ref(hw)); 4257 clk_incval = ice_ptp_read_src_incval(hw); 4258 4259 /* Calculate TUs per second */ 4260 tu_per_sec = cur_freq * clk_incval; 4261 4262 /* Calculate number of TUs to add for the fixed Rx latency. Since the 4263 * latency measurement is in 1/100th of a nanosecond, we need to 4264 * multiply by tu_per_sec and then divide by 1e11. This calculation 4265 * overflows 64 bit integer arithmetic, so break it up into two 4266 * divisions by 1e4 first then by 1e7. 4267 */ 4268 fixed_offset = div_u64(tu_per_sec, 10000); 4269 fixed_offset *= e822_vernier[link_spd].rx_fixed_delay; 4270 fixed_offset = div_u64(fixed_offset, 10000000); 4271 4272 return fixed_offset; 4273 } 4274 4275 /** 4276 * ice_phy_cfg_rx_offset_e82x - Configure total Rx timestamp offset 4277 * @hw: pointer to the HW struct 4278 * @port: the PHY port to configure 4279 * 4280 * Program the P_REG_TOTAL_RX_OFFSET register with the number of Time Units to 4281 * adjust Rx timestamps by. This combines calculations from the Vernier offset 4282 * measurements taken in hardware with some data about known fixed delay as 4283 * well as adjusting for multi-lane alignment delay. 4284 * 4285 * This function will not return successfully until the Rx offset calculations 4286 * have been completed, which requires waiting until at least one packet has 4287 * been received by the device. It is safe to call this function periodically 4288 * until calibration succeeds, as it will only program the offset once. 4289 * 4290 * This function must be called only after the offset registers are valid, 4291 * i.e. after the Vernier calibration wait has passed, to ensure that the PHY 4292 * has measured the offset. 4293 * 4294 * To avoid overflow, when calculating the offset based on the known static 4295 * latency values, we use measurements in 1/100th of a nanosecond, and divide 4296 * the TUs per second up front. This avoids overflow while allowing 4297 * calculation of the adjustment using integer arithmetic. 4298 * 4299 * Returns zero on success, -EBUSY if the hardware vernier offset 4300 * calibration has not completed, or another error code on failure. 4301 */ 4302 int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port) 4303 { 4304 enum ice_ptp_link_spd link_spd; 4305 enum ice_ptp_fec_mode fec_mode; 4306 u64 total_offset, pmd, val; 4307 int err; 4308 u32 reg; 4309 4310 /* Nothing to do if we've already programmed the offset */ 4311 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_OR, ®); 4312 if (err) { 4313 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OR for port %u, err %d\n", 4314 port, err); 4315 return err; 4316 } 4317 4318 if (reg) 4319 return 0; 4320 4321 err = ice_read_phy_reg_e82x(hw, port, P_REG_RX_OV_STATUS, ®); 4322 if (err) { 4323 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OV_STATUS for port %u, err %d\n", 4324 port, err); 4325 return err; 4326 } 4327 4328 if (!(reg & P_REG_RX_OV_STATUS_OV_M)) 4329 return -EBUSY; 4330 4331 err = ice_phy_get_speed_and_fec_e82x(hw, port, &link_spd, &fec_mode); 4332 if (err) 4333 return err; 4334 4335 total_offset = ice_calc_fixed_rx_offset_e82x(hw, link_spd); 4336 4337 /* Read the first Vernier offset from the PHY register and add it to 4338 * the total offset. 4339 */ 4340 err = ice_read_64b_phy_reg_e82x(hw, port, 4341 P_REG_PAR_PCS_RX_OFFSET_L, 4342 &val); 4343 if (err) 4344 return err; 4345 4346 total_offset += val; 4347 4348 /* For Rx, all multi-lane link speeds include a second Vernier 4349 * calibration, because the lanes might not be aligned. 4350 */ 4351 if (link_spd == ICE_PTP_LNK_SPD_40G || 4352 link_spd == ICE_PTP_LNK_SPD_50G || 4353 link_spd == ICE_PTP_LNK_SPD_50G_RS || 4354 link_spd == ICE_PTP_LNK_SPD_100G_RS) { 4355 err = ice_read_64b_phy_reg_e82x(hw, port, 4356 P_REG_PAR_RX_TIME_L, 4357 &val); 4358 if (err) 4359 return err; 4360 4361 total_offset += val; 4362 } 4363 4364 /* In addition, Rx must account for the PMD alignment */ 4365 err = ice_phy_calc_pmd_adj_e82x(hw, port, link_spd, fec_mode, &pmd); 4366 if (err) 4367 return err; 4368 4369 /* For RS-FEC, this adjustment adds delay, but for other modes, it 4370 * subtracts delay. 4371 */ 4372 if (fec_mode == ICE_PTP_FEC_MODE_RS_FEC) 4373 total_offset += pmd; 4374 else 4375 total_offset -= pmd; 4376 4377 /* Now that the total offset has been calculated, program it to the 4378 * PHY and indicate that the Rx offset is ready. After this, 4379 * timestamps will be enabled. 4380 */ 4381 err = ice_write_64b_phy_reg_e82x(hw, port, P_REG_TOTAL_RX_OFFSET_L, 4382 total_offset); 4383 if (err) 4384 return err; 4385 4386 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 1); 4387 if (err) 4388 return err; 4389 4390 dev_info(ice_hw_to_dev(hw), "Port=%d Rx vernier offset calibration complete\n", 4391 port); 4392 4393 return 0; 4394 } 4395 4396 /** 4397 * ice_ptp_clear_phy_offset_ready_e82x - Clear PHY TX_/RX_OFFSET_READY registers 4398 * @hw: pointer to the HW struct 4399 * 4400 * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted 4401 * and received timestamps as invalid. 4402 * 4403 * Return: 0 on success, other error codes when failed to write to PHY 4404 */ 4405 int ice_ptp_clear_phy_offset_ready_e82x(struct ice_hw *hw) 4406 { 4407 u8 port; 4408 4409 for (port = 0; port < hw->ptp.num_lports; port++) { 4410 int err; 4411 4412 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0); 4413 if (err) { 4414 dev_warn(ice_hw_to_dev(hw), 4415 "Failed to clear PHY TX_OFFSET_READY register\n"); 4416 return err; 4417 } 4418 4419 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0); 4420 if (err) { 4421 dev_warn(ice_hw_to_dev(hw), 4422 "Failed to clear PHY RX_OFFSET_READY register\n"); 4423 return err; 4424 } 4425 } 4426 4427 return 0; 4428 } 4429 4430 /** 4431 * ice_read_phy_and_phc_time_e82x - Simultaneously capture PHC and PHY time 4432 * @hw: pointer to the HW struct 4433 * @port: the PHY port to read 4434 * @phy_time: on return, the 64bit PHY timer value 4435 * @phc_time: on return, the lower 64bits of PHC time 4436 * 4437 * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY 4438 * and PHC timer values. 4439 */ 4440 static int 4441 ice_read_phy_and_phc_time_e82x(struct ice_hw *hw, u8 port, u64 *phy_time, 4442 u64 *phc_time) 4443 { 4444 u64 tx_time, rx_time; 4445 u32 zo, lo; 4446 u8 tmr_idx; 4447 int err; 4448 4449 tmr_idx = ice_get_ptp_src_clock_index(hw); 4450 4451 /* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */ 4452 ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME); 4453 4454 /* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */ 4455 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_READ_TIME); 4456 if (err) 4457 return err; 4458 4459 /* Issue the sync to start the ICE_PTP_READ_TIME capture */ 4460 ice_ptp_exec_tmr_cmd(hw); 4461 4462 /* Read the captured PHC time from the shadow time registers */ 4463 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx)); 4464 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx)); 4465 *phc_time = (u64)lo << 32 | zo; 4466 4467 /* Read the captured PHY time from the PHY shadow registers */ 4468 err = ice_ptp_read_port_capture(hw, port, &tx_time, &rx_time); 4469 if (err) 4470 return err; 4471 4472 /* If the PHY Tx and Rx timers don't match, log a warning message. 4473 * Note that this should not happen in normal circumstances since the 4474 * driver always programs them together. 4475 */ 4476 if (tx_time != rx_time) 4477 dev_warn(ice_hw_to_dev(hw), 4478 "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n", 4479 port, (unsigned long long)tx_time, 4480 (unsigned long long)rx_time); 4481 4482 *phy_time = tx_time; 4483 4484 return 0; 4485 } 4486 4487 /** 4488 * ice_sync_phy_timer_e82x - Synchronize the PHY timer with PHC timer 4489 * @hw: pointer to the HW struct 4490 * @port: the PHY port to synchronize 4491 * 4492 * Perform an adjustment to ensure that the PHY and PHC timers are in sync. 4493 * This is done by issuing a ICE_PTP_READ_TIME command which triggers a 4494 * simultaneous read of the PHY timer and PHC timer. Then we use the 4495 * difference to calculate an appropriate 2s complement addition to add 4496 * to the PHY timer in order to ensure it reads the same value as the 4497 * primary PHC timer. 4498 */ 4499 static int ice_sync_phy_timer_e82x(struct ice_hw *hw, u8 port) 4500 { 4501 u64 phc_time, phy_time, difference; 4502 int err; 4503 4504 if (!ice_ptp_lock(hw)) { 4505 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n"); 4506 return -EBUSY; 4507 } 4508 4509 err = ice_read_phy_and_phc_time_e82x(hw, port, &phy_time, &phc_time); 4510 if (err) 4511 goto err_unlock; 4512 4513 /* Calculate the amount required to add to the port time in order for 4514 * it to match the PHC time. 4515 * 4516 * Note that the port adjustment is done using 2s complement 4517 * arithmetic. This is convenient since it means that we can simply 4518 * calculate the difference between the PHC time and the port time, 4519 * and it will be interpreted correctly. 4520 */ 4521 difference = phc_time - phy_time; 4522 4523 err = ice_ptp_prep_port_adj_e82x(hw, port, (s64)difference); 4524 if (err) 4525 goto err_unlock; 4526 4527 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_ADJ_TIME); 4528 if (err) 4529 goto err_unlock; 4530 4531 /* Do not perform any action on the main timer */ 4532 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 4533 4534 /* Issue the sync to activate the time adjustment */ 4535 ice_ptp_exec_tmr_cmd(hw); 4536 4537 /* Re-capture the timer values to flush the command registers and 4538 * verify that the time was properly adjusted. 4539 */ 4540 err = ice_read_phy_and_phc_time_e82x(hw, port, &phy_time, &phc_time); 4541 if (err) 4542 goto err_unlock; 4543 4544 dev_info(ice_hw_to_dev(hw), 4545 "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n", 4546 port, (unsigned long long)phy_time, 4547 (unsigned long long)phc_time); 4548 4549 ice_ptp_unlock(hw); 4550 4551 return 0; 4552 4553 err_unlock: 4554 ice_ptp_unlock(hw); 4555 return err; 4556 } 4557 4558 /** 4559 * ice_stop_phy_timer_e82x - Stop the PHY clock timer 4560 * @hw: pointer to the HW struct 4561 * @port: the PHY port to stop 4562 * @soft_reset: if true, hold the SOFT_RESET bit of P_REG_PS 4563 * 4564 * Stop the clock of a PHY port. This must be done as part of the flow to 4565 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 4566 * initialized or when link speed changes. 4567 */ 4568 int 4569 ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset) 4570 { 4571 int err; 4572 u32 val; 4573 4574 err = ice_write_phy_reg_e82x(hw, port, P_REG_TX_OR, 0); 4575 if (err) 4576 return err; 4577 4578 err = ice_write_phy_reg_e82x(hw, port, P_REG_RX_OR, 0); 4579 if (err) 4580 return err; 4581 4582 err = ice_read_phy_reg_e82x(hw, port, P_REG_PS, &val); 4583 if (err) 4584 return err; 4585 4586 val &= ~P_REG_PS_START_M; 4587 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4588 if (err) 4589 return err; 4590 4591 val &= ~P_REG_PS_ENA_CLK_M; 4592 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4593 if (err) 4594 return err; 4595 4596 if (soft_reset) { 4597 val |= P_REG_PS_SFT_RESET_M; 4598 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4599 if (err) 4600 return err; 4601 } 4602 4603 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port); 4604 4605 return 0; 4606 } 4607 4608 /** 4609 * ice_start_phy_timer_e82x - Start the PHY clock timer 4610 * @hw: pointer to the HW struct 4611 * @port: the PHY port to start 4612 * 4613 * Start the clock of a PHY port. This must be done as part of the flow to 4614 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 4615 * initialized or when link speed changes. 4616 * 4617 * Hardware will take Vernier measurements on Tx or Rx of packets. 4618 */ 4619 int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port) 4620 { 4621 u32 lo, hi, val; 4622 u64 incval; 4623 u8 tmr_idx; 4624 int err; 4625 4626 tmr_idx = ice_get_ptp_src_clock_index(hw); 4627 4628 err = ice_stop_phy_timer_e82x(hw, port, false); 4629 if (err) 4630 return err; 4631 4632 ice_phy_cfg_lane_e82x(hw, port); 4633 4634 err = ice_phy_cfg_uix_e82x(hw, port); 4635 if (err) 4636 return err; 4637 4638 err = ice_phy_cfg_parpcs_e82x(hw, port); 4639 if (err) 4640 return err; 4641 4642 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 4643 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 4644 incval = (u64)hi << 32 | lo; 4645 4646 err = ice_write_40b_phy_reg_e82x(hw, port, P_REG_TIMETUS_L, incval); 4647 if (err) 4648 return err; 4649 4650 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL); 4651 if (err) 4652 return err; 4653 4654 /* Do not perform any action on the main timer */ 4655 ice_ptp_src_cmd(hw, ICE_PTP_NOP); 4656 4657 ice_ptp_exec_tmr_cmd(hw); 4658 4659 err = ice_read_phy_reg_e82x(hw, port, P_REG_PS, &val); 4660 if (err) 4661 return err; 4662 4663 val |= P_REG_PS_SFT_RESET_M; 4664 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4665 if (err) 4666 return err; 4667 4668 val |= P_REG_PS_START_M; 4669 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4670 if (err) 4671 return err; 4672 4673 val &= ~P_REG_PS_SFT_RESET_M; 4674 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4675 if (err) 4676 return err; 4677 4678 err = ice_ptp_one_port_cmd(hw, port, ICE_PTP_INIT_INCVAL); 4679 if (err) 4680 return err; 4681 4682 ice_ptp_exec_tmr_cmd(hw); 4683 4684 val |= P_REG_PS_ENA_CLK_M; 4685 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4686 if (err) 4687 return err; 4688 4689 val |= P_REG_PS_LOAD_OFFSET_M; 4690 err = ice_write_phy_reg_e82x(hw, port, P_REG_PS, val); 4691 if (err) 4692 return err; 4693 4694 ice_ptp_exec_tmr_cmd(hw); 4695 4696 err = ice_sync_phy_timer_e82x(hw, port); 4697 if (err) 4698 return err; 4699 4700 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port); 4701 4702 return 0; 4703 } 4704 4705 /** 4706 * ice_get_phy_tx_tstamp_ready_e82x - Read Tx memory status register 4707 * @hw: pointer to the HW struct 4708 * @quad: the timestamp quad to read from 4709 * @tstamp_ready: contents of the Tx memory status register 4710 * 4711 * Read the Q_REG_TX_MEMORY_STATUS register indicating which timestamps in 4712 * the PHY are ready. A set bit means the corresponding timestamp is valid and 4713 * ready to be captured from the PHY timestamp block. 4714 */ 4715 static int 4716 ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw *hw, u8 quad, u64 *tstamp_ready) 4717 { 4718 u32 hi, lo; 4719 int err; 4720 4721 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_U, &hi); 4722 if (err) { 4723 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_U for quad %u, err %d\n", 4724 quad, err); 4725 return err; 4726 } 4727 4728 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_L, &lo); 4729 if (err) { 4730 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_L for quad %u, err %d\n", 4731 quad, err); 4732 return err; 4733 } 4734 4735 *tstamp_ready = (u64)hi << 32 | (u64)lo; 4736 4737 return 0; 4738 } 4739 4740 /** 4741 * ice_phy_cfg_intr_e82x - Configure TX timestamp interrupt 4742 * @hw: pointer to the HW struct 4743 * @quad: the timestamp quad 4744 * @ena: enable or disable interrupt 4745 * @threshold: interrupt threshold 4746 * 4747 * Configure TX timestamp interrupt for the specified quad 4748 * 4749 * Return: 0 on success, other error codes when failed to read/write quad 4750 */ 4751 4752 int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold) 4753 { 4754 int err; 4755 u32 val; 4756 4757 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val); 4758 if (err) 4759 return err; 4760 4761 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M; 4762 if (ena) { 4763 val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M; 4764 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M; 4765 val |= FIELD_PREP(Q_REG_TX_MEM_GBL_CFG_INTR_THR_M, threshold); 4766 } 4767 4768 return ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val); 4769 } 4770 4771 /** 4772 * ice_ptp_init_phy_e82x - initialize PHY parameters 4773 * @ptp: pointer to the PTP HW struct 4774 */ 4775 static void ice_ptp_init_phy_e82x(struct ice_ptp_hw *ptp) 4776 { 4777 ptp->phy_model = ICE_PHY_E82X; 4778 ptp->num_lports = 8; 4779 ptp->ports_per_phy = 8; 4780 } 4781 4782 /* E810 functions 4783 * 4784 * The following functions operate on the E810 series devices which use 4785 * a separate external PHY. 4786 */ 4787 4788 /** 4789 * ice_read_phy_reg_e810 - Read register from external PHY on E810 4790 * @hw: pointer to the HW struct 4791 * @addr: the address to read from 4792 * @val: On return, the value read from the PHY 4793 * 4794 * Read a register from the external PHY on the E810 device. 4795 */ 4796 static int ice_read_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 *val) 4797 { 4798 struct ice_sbq_msg_input msg = {0}; 4799 int err; 4800 4801 msg.msg_addr_low = lower_16_bits(addr); 4802 msg.msg_addr_high = upper_16_bits(addr); 4803 msg.opcode = ice_sbq_msg_rd; 4804 msg.dest_dev = rmn_0; 4805 4806 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 4807 if (err) { 4808 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 4809 err); 4810 return err; 4811 } 4812 4813 *val = msg.data; 4814 4815 return 0; 4816 } 4817 4818 /** 4819 * ice_write_phy_reg_e810 - Write register on external PHY on E810 4820 * @hw: pointer to the HW struct 4821 * @addr: the address to writem to 4822 * @val: the value to write to the PHY 4823 * 4824 * Write a value to a register of the external PHY on the E810 device. 4825 */ 4826 static int ice_write_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 val) 4827 { 4828 struct ice_sbq_msg_input msg = {0}; 4829 int err; 4830 4831 msg.msg_addr_low = lower_16_bits(addr); 4832 msg.msg_addr_high = upper_16_bits(addr); 4833 msg.opcode = ice_sbq_msg_wr; 4834 msg.dest_dev = rmn_0; 4835 msg.data = val; 4836 4837 err = ice_sbq_rw_reg(hw, &msg, ICE_AQ_FLAG_RD); 4838 if (err) { 4839 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 4840 err); 4841 return err; 4842 } 4843 4844 return 0; 4845 } 4846 4847 /** 4848 * ice_read_phy_tstamp_ll_e810 - Read a PHY timestamp registers through the FW 4849 * @hw: pointer to the HW struct 4850 * @idx: the timestamp index to read 4851 * @hi: 8 bit timestamp high value 4852 * @lo: 32 bit timestamp low value 4853 * 4854 * Read a 8bit timestamp high value and 32 bit timestamp low value out of the 4855 * timestamp block of the external PHY on the E810 device using the low latency 4856 * timestamp read. 4857 */ 4858 static int 4859 ice_read_phy_tstamp_ll_e810(struct ice_hw *hw, u8 idx, u8 *hi, u32 *lo) 4860 { 4861 u32 val; 4862 u8 i; 4863 4864 /* Write TS index to read to the PF register so the FW can read it */ 4865 val = FIELD_PREP(TS_LL_READ_TS_IDX, idx) | TS_LL_READ_TS; 4866 wr32(hw, PF_SB_ATQBAL, val); 4867 4868 /* Read the register repeatedly until the FW provides us the TS */ 4869 for (i = TS_LL_READ_RETRIES; i > 0; i--) { 4870 val = rd32(hw, PF_SB_ATQBAL); 4871 4872 /* When the bit is cleared, the TS is ready in the register */ 4873 if (!(FIELD_GET(TS_LL_READ_TS, val))) { 4874 /* High 8 bit value of the TS is on the bits 16:23 */ 4875 *hi = FIELD_GET(TS_LL_READ_TS_HIGH, val); 4876 4877 /* Read the low 32 bit value and set the TS valid bit */ 4878 *lo = rd32(hw, PF_SB_ATQBAH) | TS_VALID; 4879 return 0; 4880 } 4881 4882 udelay(10); 4883 } 4884 4885 /* FW failed to provide the TS in time */ 4886 ice_debug(hw, ICE_DBG_PTP, "Failed to read PTP timestamp using low latency read\n"); 4887 return -EINVAL; 4888 } 4889 4890 /** 4891 * ice_read_phy_tstamp_sbq_e810 - Read a PHY timestamp registers through the sbq 4892 * @hw: pointer to the HW struct 4893 * @lport: the lport to read from 4894 * @idx: the timestamp index to read 4895 * @hi: 8 bit timestamp high value 4896 * @lo: 32 bit timestamp low value 4897 * 4898 * Read a 8bit timestamp high value and 32 bit timestamp low value out of the 4899 * timestamp block of the external PHY on the E810 device using sideband queue. 4900 */ 4901 static int 4902 ice_read_phy_tstamp_sbq_e810(struct ice_hw *hw, u8 lport, u8 idx, u8 *hi, 4903 u32 *lo) 4904 { 4905 u32 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); 4906 u32 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); 4907 u32 lo_val, hi_val; 4908 int err; 4909 4910 err = ice_read_phy_reg_e810(hw, lo_addr, &lo_val); 4911 if (err) { 4912 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 4913 err); 4914 return err; 4915 } 4916 4917 err = ice_read_phy_reg_e810(hw, hi_addr, &hi_val); 4918 if (err) { 4919 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 4920 err); 4921 return err; 4922 } 4923 4924 *lo = lo_val; 4925 *hi = (u8)hi_val; 4926 4927 return 0; 4928 } 4929 4930 /** 4931 * ice_read_phy_tstamp_e810 - Read a PHY timestamp out of the external PHY 4932 * @hw: pointer to the HW struct 4933 * @lport: the lport to read from 4934 * @idx: the timestamp index to read 4935 * @tstamp: on return, the 40bit timestamp value 4936 * 4937 * Read a 40bit timestamp value out of the timestamp block of the external PHY 4938 * on the E810 device. 4939 */ 4940 static int 4941 ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) 4942 { 4943 u32 lo = 0; 4944 u8 hi = 0; 4945 int err; 4946 4947 if (hw->dev_caps.ts_dev_info.ts_ll_read) 4948 err = ice_read_phy_tstamp_ll_e810(hw, idx, &hi, &lo); 4949 else 4950 err = ice_read_phy_tstamp_sbq_e810(hw, lport, idx, &hi, &lo); 4951 4952 if (err) 4953 return err; 4954 4955 /* For E810 devices, the timestamp is reported with the lower 32 bits 4956 * in the low register, and the upper 8 bits in the high register. 4957 */ 4958 *tstamp = ((u64)hi) << TS_HIGH_S | ((u64)lo & TS_LOW_M); 4959 4960 return 0; 4961 } 4962 4963 /** 4964 * ice_clear_phy_tstamp_e810 - Clear a timestamp from the external PHY 4965 * @hw: pointer to the HW struct 4966 * @lport: the lport to read from 4967 * @idx: the timestamp index to reset 4968 * 4969 * Read the timestamp and then forcibly overwrite its value to clear the valid 4970 * bit from the timestamp block of the external PHY on the E810 device. 4971 * 4972 * This function should only be called on an idx whose bit is set according to 4973 * ice_get_phy_tx_tstamp_ready(). 4974 */ 4975 static int ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx) 4976 { 4977 u32 lo_addr, hi_addr; 4978 u64 unused_tstamp; 4979 int err; 4980 4981 err = ice_read_phy_tstamp_e810(hw, lport, idx, &unused_tstamp); 4982 if (err) { 4983 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for lport %u, idx %u, err %d\n", 4984 lport, idx, err); 4985 return err; 4986 } 4987 4988 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); 4989 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); 4990 4991 err = ice_write_phy_reg_e810(hw, lo_addr, 0); 4992 if (err) { 4993 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register for lport %u, idx %u, err %d\n", 4994 lport, idx, err); 4995 return err; 4996 } 4997 4998 err = ice_write_phy_reg_e810(hw, hi_addr, 0); 4999 if (err) { 5000 ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register for lport %u, idx %u, err %d\n", 5001 lport, idx, err); 5002 return err; 5003 } 5004 5005 return 0; 5006 } 5007 5008 /** 5009 * ice_ptp_init_phc_e810 - Perform E810 specific PHC initialization 5010 * @hw: pointer to HW struct 5011 * 5012 * Perform E810-specific PTP hardware clock initialization steps. 5013 * 5014 * Return: 0 on success, other error codes when failed to initialize TimeSync 5015 */ 5016 static int ice_ptp_init_phc_e810(struct ice_hw *hw) 5017 { 5018 u8 tmr_idx; 5019 int err; 5020 5021 /* Ensure synchronization delay is zero */ 5022 wr32(hw, GLTSYN_SYNC_DLAY, 0); 5023 5024 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5025 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_ENA(tmr_idx), 5026 GLTSYN_ENA_TSYN_ENA_M); 5027 if (err) 5028 ice_debug(hw, ICE_DBG_PTP, "PTP failed in ena_phy_time_syn %d\n", 5029 err); 5030 5031 return err; 5032 } 5033 5034 /** 5035 * ice_ptp_prep_phy_time_e810 - Prepare PHY port with initial time 5036 * @hw: Board private structure 5037 * @time: Time to initialize the PHY port clock to 5038 * 5039 * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the 5040 * initial clock time. The time will not actually be programmed until the 5041 * driver issues an ICE_PTP_INIT_TIME command. 5042 * 5043 * The time value is the upper 32 bits of the PHY timer, usually in units of 5044 * nominal nanoseconds. 5045 */ 5046 static int ice_ptp_prep_phy_time_e810(struct ice_hw *hw, u32 time) 5047 { 5048 u8 tmr_idx; 5049 int err; 5050 5051 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5052 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_0(tmr_idx), 0); 5053 if (err) { 5054 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_0, err %d\n", 5055 err); 5056 return err; 5057 } 5058 5059 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_L(tmr_idx), time); 5060 if (err) { 5061 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_L, err %d\n", 5062 err); 5063 return err; 5064 } 5065 5066 return 0; 5067 } 5068 5069 /** 5070 * ice_ptp_prep_phy_adj_e810 - Prep PHY port for a time adjustment 5071 * @hw: pointer to HW struct 5072 * @adj: adjustment value to program 5073 * 5074 * Prepare the PHY port for an atomic adjustment by programming the PHY 5075 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual adjustment 5076 * is completed by issuing an ICE_PTP_ADJ_TIME sync command. 5077 * 5078 * The adjustment value only contains the portion used for the upper 32bits of 5079 * the PHY timer, usually in units of nominal nanoseconds. Negative 5080 * adjustments are supported using 2s complement arithmetic. 5081 */ 5082 static int ice_ptp_prep_phy_adj_e810(struct ice_hw *hw, s32 adj) 5083 { 5084 u8 tmr_idx; 5085 int err; 5086 5087 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5088 5089 /* Adjustments are represented as signed 2's complement values in 5090 * nanoseconds. Sub-nanosecond adjustment is not supported. 5091 */ 5092 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), 0); 5093 if (err) { 5094 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_L, err %d\n", 5095 err); 5096 return err; 5097 } 5098 5099 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), adj); 5100 if (err) { 5101 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_H, err %d\n", 5102 err); 5103 return err; 5104 } 5105 5106 return 0; 5107 } 5108 5109 /** 5110 * ice_ptp_prep_phy_incval_e810 - Prep PHY port increment value change 5111 * @hw: pointer to HW struct 5112 * @incval: The new 40bit increment value to prepare 5113 * 5114 * Prepare the PHY port for a new increment value by programming the PHY 5115 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual change is 5116 * completed by issuing an ICE_PTP_INIT_INCVAL command. 5117 */ 5118 static int ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval) 5119 { 5120 u32 high, low; 5121 u8 tmr_idx; 5122 int err; 5123 5124 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5125 low = lower_32_bits(incval); 5126 high = upper_32_bits(incval); 5127 5128 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), low); 5129 if (err) { 5130 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval to PHY SHADJ_L, err %d\n", 5131 err); 5132 return err; 5133 } 5134 5135 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), high); 5136 if (err) { 5137 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval PHY SHADJ_H, err %d\n", 5138 err); 5139 return err; 5140 } 5141 5142 return 0; 5143 } 5144 5145 /** 5146 * ice_ptp_port_cmd_e810 - Prepare all external PHYs for a timer command 5147 * @hw: pointer to HW struct 5148 * @cmd: Command to be sent to the port 5149 * 5150 * Prepare the external PHYs connected to this device for a timer sync 5151 * command. 5152 */ 5153 static int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 5154 { 5155 u32 val = ice_ptp_tmr_cmd_to_port_reg(hw, cmd); 5156 5157 return ice_write_phy_reg_e810(hw, E810_ETH_GLTSYN_CMD, val); 5158 } 5159 5160 /** 5161 * ice_get_phy_tx_tstamp_ready_e810 - Read Tx memory status register 5162 * @hw: pointer to the HW struct 5163 * @port: the PHY port to read 5164 * @tstamp_ready: contents of the Tx memory status register 5165 * 5166 * E810 devices do not use a Tx memory status register. Instead simply 5167 * indicate that all timestamps are currently ready. 5168 */ 5169 static int 5170 ice_get_phy_tx_tstamp_ready_e810(struct ice_hw *hw, u8 port, u64 *tstamp_ready) 5171 { 5172 *tstamp_ready = 0xFFFFFFFFFFFFFFFF; 5173 return 0; 5174 } 5175 5176 /* E810 SMA functions 5177 * 5178 * The following functions operate specifically on E810 hardware and are used 5179 * to access the extended GPIOs available. 5180 */ 5181 5182 /** 5183 * ice_get_pca9575_handle 5184 * @hw: pointer to the hw struct 5185 * @pca9575_handle: GPIO controller's handle 5186 * 5187 * Find and return the GPIO controller's handle in the netlist. 5188 * When found - the value will be cached in the hw structure and following calls 5189 * will return cached value 5190 */ 5191 static int 5192 ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) 5193 { 5194 struct ice_aqc_get_link_topo *cmd; 5195 struct ice_aq_desc desc; 5196 int status; 5197 u8 idx; 5198 5199 /* If handle was read previously return cached value */ 5200 if (hw->io_expander_handle) { 5201 *pca9575_handle = hw->io_expander_handle; 5202 return 0; 5203 } 5204 5205 /* If handle was not detected read it from the netlist */ 5206 cmd = &desc.params.get_link_topo; 5207 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 5208 5209 /* Set node type to GPIO controller */ 5210 cmd->addr.topo_params.node_type_ctx = 5211 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & 5212 ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL); 5213 5214 #define SW_PCA9575_SFP_TOPO_IDX 2 5215 #define SW_PCA9575_QSFP_TOPO_IDX 1 5216 5217 /* Check if the SW IO expander controlling SMA exists in the netlist. */ 5218 if (hw->device_id == ICE_DEV_ID_E810C_SFP) 5219 idx = SW_PCA9575_SFP_TOPO_IDX; 5220 else if (hw->device_id == ICE_DEV_ID_E810C_QSFP) 5221 idx = SW_PCA9575_QSFP_TOPO_IDX; 5222 else 5223 return -EOPNOTSUPP; 5224 5225 cmd->addr.topo_params.index = idx; 5226 5227 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 5228 if (status) 5229 return -EOPNOTSUPP; 5230 5231 /* Verify if we found the right IO expander type */ 5232 if (desc.params.get_link_topo.node_part_num != 5233 ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575) 5234 return -EOPNOTSUPP; 5235 5236 /* If present save the handle and return it */ 5237 hw->io_expander_handle = 5238 le16_to_cpu(desc.params.get_link_topo.addr.handle); 5239 *pca9575_handle = hw->io_expander_handle; 5240 5241 return 0; 5242 } 5243 5244 /** 5245 * ice_read_sma_ctrl 5246 * @hw: pointer to the hw struct 5247 * @data: pointer to data to be read from the GPIO controller 5248 * 5249 * Read the SMA controller state. It is connected to pins 3-7 of Port 1 of the 5250 * PCA9575 expander, so only bits 3-7 in data are valid. 5251 */ 5252 int ice_read_sma_ctrl(struct ice_hw *hw, u8 *data) 5253 { 5254 int status; 5255 u16 handle; 5256 u8 i; 5257 5258 status = ice_get_pca9575_handle(hw, &handle); 5259 if (status) 5260 return status; 5261 5262 *data = 0; 5263 5264 for (i = ICE_SMA_MIN_BIT; i <= ICE_SMA_MAX_BIT; i++) { 5265 bool pin; 5266 5267 status = ice_aq_get_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET, 5268 &pin, NULL); 5269 if (status) 5270 break; 5271 *data |= (u8)(!pin) << i; 5272 } 5273 5274 return status; 5275 } 5276 5277 /** 5278 * ice_write_sma_ctrl 5279 * @hw: pointer to the hw struct 5280 * @data: data to be written to the GPIO controller 5281 * 5282 * Write the data to the SMA controller. It is connected to pins 3-7 of Port 1 5283 * of the PCA9575 expander, so only bits 3-7 in data are valid. 5284 */ 5285 int ice_write_sma_ctrl(struct ice_hw *hw, u8 data) 5286 { 5287 int status; 5288 u16 handle; 5289 u8 i; 5290 5291 status = ice_get_pca9575_handle(hw, &handle); 5292 if (status) 5293 return status; 5294 5295 for (i = ICE_SMA_MIN_BIT; i <= ICE_SMA_MAX_BIT; i++) { 5296 bool pin; 5297 5298 pin = !(data & (1 << i)); 5299 status = ice_aq_set_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET, 5300 pin, NULL); 5301 if (status) 5302 break; 5303 } 5304 5305 return status; 5306 } 5307 5308 /** 5309 * ice_read_pca9575_reg 5310 * @hw: pointer to the hw struct 5311 * @offset: GPIO controller register offset 5312 * @data: pointer to data to be read from the GPIO controller 5313 * 5314 * Read the register from the GPIO controller 5315 */ 5316 int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data) 5317 { 5318 struct ice_aqc_link_topo_addr link_topo; 5319 __le16 addr; 5320 u16 handle; 5321 int err; 5322 5323 memset(&link_topo, 0, sizeof(link_topo)); 5324 5325 err = ice_get_pca9575_handle(hw, &handle); 5326 if (err) 5327 return err; 5328 5329 link_topo.handle = cpu_to_le16(handle); 5330 link_topo.topo_params.node_type_ctx = 5331 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, 5332 ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED); 5333 5334 addr = cpu_to_le16((u16)offset); 5335 5336 return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL); 5337 } 5338 5339 /** 5340 * ice_ptp_read_sdp_ac - read SDP available connections section from NVM 5341 * @hw: pointer to the HW struct 5342 * @entries: returns the SDP available connections section from NVM 5343 * @num_entries: returns the number of valid entries 5344 * 5345 * Return: 0 on success, negative error code if NVM read failed or section does 5346 * not exist or is corrupted 5347 */ 5348 int ice_ptp_read_sdp_ac(struct ice_hw *hw, __le16 *entries, uint *num_entries) 5349 { 5350 __le16 data; 5351 u32 offset; 5352 int err; 5353 5354 err = ice_acquire_nvm(hw, ICE_RES_READ); 5355 if (err) 5356 goto exit; 5357 5358 /* Read the offset of SDP_AC */ 5359 offset = ICE_AQC_NVM_SDP_AC_PTR_OFFSET; 5360 err = ice_aq_read_nvm(hw, 0, offset, sizeof(data), &data, false, true, 5361 NULL); 5362 if (err) 5363 goto exit; 5364 5365 /* Check if section exist */ 5366 offset = FIELD_GET(ICE_AQC_NVM_SDP_AC_PTR_M, le16_to_cpu(data)); 5367 if (offset == ICE_AQC_NVM_SDP_AC_PTR_INVAL) { 5368 err = -EINVAL; 5369 goto exit; 5370 } 5371 5372 if (offset & ICE_AQC_NVM_SDP_AC_PTR_TYPE_M) { 5373 offset &= ICE_AQC_NVM_SDP_AC_PTR_M; 5374 offset *= ICE_AQC_NVM_SECTOR_UNIT; 5375 } else { 5376 offset *= sizeof(data); 5377 } 5378 5379 /* Skip reading section length and read the number of valid entries */ 5380 offset += sizeof(data); 5381 err = ice_aq_read_nvm(hw, 0, offset, sizeof(data), &data, false, true, 5382 NULL); 5383 if (err) 5384 goto exit; 5385 *num_entries = le16_to_cpu(data); 5386 5387 /* Read SDP configuration section */ 5388 offset += sizeof(data); 5389 err = ice_aq_read_nvm(hw, 0, offset, *num_entries * sizeof(data), 5390 entries, false, true, NULL); 5391 5392 exit: 5393 if (err) 5394 dev_dbg(ice_hw_to_dev(hw), "Failed to configure SDP connection section\n"); 5395 ice_release_nvm(hw); 5396 return err; 5397 } 5398 5399 /** 5400 * ice_ptp_init_phy_e810 - initialize PHY parameters 5401 * @ptp: pointer to the PTP HW struct 5402 */ 5403 static void ice_ptp_init_phy_e810(struct ice_ptp_hw *ptp) 5404 { 5405 ptp->phy_model = ICE_PHY_E810; 5406 ptp->num_lports = 8; 5407 ptp->ports_per_phy = 4; 5408 } 5409 5410 /* Device agnostic functions 5411 * 5412 * The following functions implement shared behavior common to both E822 and 5413 * E810 devices, possibly calling a device specific implementation where 5414 * necessary. 5415 */ 5416 5417 /** 5418 * ice_ptp_lock - Acquire PTP global semaphore register lock 5419 * @hw: pointer to the HW struct 5420 * 5421 * Acquire the global PTP hardware semaphore lock. Returns true if the lock 5422 * was acquired, false otherwise. 5423 * 5424 * The PFTSYN_SEM register sets the busy bit on read, returning the previous 5425 * value. If software sees the busy bit cleared, this means that this function 5426 * acquired the lock (and the busy bit is now set). If software sees the busy 5427 * bit set, it means that another function acquired the lock. 5428 * 5429 * Software must clear the busy bit with a write to release the lock for other 5430 * functions when done. 5431 */ 5432 bool ice_ptp_lock(struct ice_hw *hw) 5433 { 5434 u32 hw_lock; 5435 int i; 5436 5437 #define MAX_TRIES 15 5438 5439 for (i = 0; i < MAX_TRIES; i++) { 5440 hw_lock = rd32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id)); 5441 hw_lock = hw_lock & PFTSYN_SEM_BUSY_M; 5442 if (hw_lock) { 5443 /* Somebody is holding the lock */ 5444 usleep_range(5000, 6000); 5445 continue; 5446 } 5447 5448 break; 5449 } 5450 5451 return !hw_lock; 5452 } 5453 5454 /** 5455 * ice_ptp_unlock - Release PTP global semaphore register lock 5456 * @hw: pointer to the HW struct 5457 * 5458 * Release the global PTP hardware semaphore lock. This is done by writing to 5459 * the PFTSYN_SEM register. 5460 */ 5461 void ice_ptp_unlock(struct ice_hw *hw) 5462 { 5463 wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0); 5464 } 5465 5466 /** 5467 * ice_ptp_init_hw - Initialize hw based on device type 5468 * @hw: pointer to the HW structure 5469 * 5470 * Determine the PHY model for the device, and initialize hw 5471 * for use by other functions. 5472 */ 5473 void ice_ptp_init_hw(struct ice_hw *hw) 5474 { 5475 struct ice_ptp_hw *ptp = &hw->ptp; 5476 5477 if (ice_is_e822(hw) || ice_is_e823(hw)) 5478 ice_ptp_init_phy_e82x(ptp); 5479 else if (ice_is_e810(hw)) 5480 ice_ptp_init_phy_e810(ptp); 5481 else if (ice_is_e825c(hw)) 5482 ice_ptp_init_phy_e825c(hw); 5483 else 5484 ptp->phy_model = ICE_PHY_UNSUP; 5485 } 5486 5487 /** 5488 * ice_ptp_write_port_cmd - Prepare a single PHY port for a timer command 5489 * @hw: pointer to HW struct 5490 * @port: Port to which cmd has to be sent 5491 * @cmd: Command to be sent to the port 5492 * 5493 * Prepare one port for the upcoming timer sync command. Do not use this for 5494 * programming only a single port, instead use ice_ptp_one_port_cmd() to 5495 * ensure non-modified ports get properly initialized to ICE_PTP_NOP. 5496 * 5497 * Return: 5498 * * %0 - success 5499 * %-EBUSY - PHY type not supported 5500 * * %other - failed to write port command 5501 */ 5502 static int ice_ptp_write_port_cmd(struct ice_hw *hw, u8 port, 5503 enum ice_ptp_tmr_cmd cmd) 5504 { 5505 switch (ice_get_phy_model(hw)) { 5506 case ICE_PHY_ETH56G: 5507 return ice_ptp_write_port_cmd_eth56g(hw, port, cmd); 5508 case ICE_PHY_E82X: 5509 return ice_ptp_write_port_cmd_e82x(hw, port, cmd); 5510 default: 5511 return -EOPNOTSUPP; 5512 } 5513 } 5514 5515 /** 5516 * ice_ptp_one_port_cmd - Program one PHY port for a timer command 5517 * @hw: pointer to HW struct 5518 * @configured_port: the port that should execute the command 5519 * @configured_cmd: the command to be executed on the configured port 5520 * 5521 * Prepare one port for executing a timer command, while preparing all other 5522 * ports to ICE_PTP_NOP. This allows executing a command on a single port 5523 * while ensuring all other ports do not execute stale commands. 5524 * 5525 * Return: 5526 * * %0 - success 5527 * * %other - failed to write port command 5528 */ 5529 int ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port, 5530 enum ice_ptp_tmr_cmd configured_cmd) 5531 { 5532 u32 port; 5533 5534 for (port = 0; port < hw->ptp.num_lports; port++) { 5535 int err; 5536 5537 /* Program the configured port with the configured command, 5538 * program all other ports with ICE_PTP_NOP. 5539 */ 5540 if (port == configured_port) 5541 err = ice_ptp_write_port_cmd(hw, port, configured_cmd); 5542 else 5543 err = ice_ptp_write_port_cmd(hw, port, ICE_PTP_NOP); 5544 5545 if (err) 5546 return err; 5547 } 5548 5549 return 0; 5550 } 5551 5552 /** 5553 * ice_ptp_port_cmd - Prepare PHY ports for a timer sync command 5554 * @hw: pointer to HW struct 5555 * @cmd: the timer command to setup 5556 * 5557 * Prepare all PHY ports on this device for the requested timer command. For 5558 * some families this can be done in one shot, but for other families each 5559 * port must be configured individually. 5560 * 5561 * Return: 5562 * * %0 - success 5563 * * %other - failed to write port command 5564 */ 5565 static int ice_ptp_port_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 5566 { 5567 u32 port; 5568 5569 /* PHY models which can program all ports simultaneously */ 5570 switch (ice_get_phy_model(hw)) { 5571 case ICE_PHY_E810: 5572 return ice_ptp_port_cmd_e810(hw, cmd); 5573 default: 5574 break; 5575 } 5576 5577 /* PHY models which require programming each port separately */ 5578 for (port = 0; port < hw->ptp.num_lports; port++) { 5579 int err; 5580 5581 err = ice_ptp_write_port_cmd(hw, port, cmd); 5582 if (err) 5583 return err; 5584 } 5585 5586 return 0; 5587 } 5588 5589 /** 5590 * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command 5591 * @hw: pointer to HW struct 5592 * @cmd: the command to issue 5593 * 5594 * Prepare the source timer and PHY timers and then trigger the requested 5595 * command. This causes the shadow registers previously written in preparation 5596 * for the command to be synchronously applied to both the source and PHY 5597 * timers. 5598 */ 5599 static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 5600 { 5601 int err; 5602 5603 /* First, prepare the source timer */ 5604 ice_ptp_src_cmd(hw, cmd); 5605 5606 /* Next, prepare the ports */ 5607 err = ice_ptp_port_cmd(hw, cmd); 5608 if (err) { 5609 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for timer command %u, err %d\n", 5610 cmd, err); 5611 return err; 5612 } 5613 5614 /* Write the sync command register to drive both source and PHY timer 5615 * commands synchronously 5616 */ 5617 ice_ptp_exec_tmr_cmd(hw); 5618 5619 return 0; 5620 } 5621 5622 /** 5623 * ice_ptp_init_time - Initialize device time to provided value 5624 * @hw: pointer to HW struct 5625 * @time: 64bits of time (GLTSYN_TIME_L and GLTSYN_TIME_H) 5626 * 5627 * Initialize the device to the specified time provided. This requires a three 5628 * step process: 5629 * 5630 * 1) write the new init time to the source timer shadow registers 5631 * 2) write the new init time to the PHY timer shadow registers 5632 * 3) issue an init_time timer command to synchronously switch both the source 5633 * and port timers to the new init time value at the next clock cycle. 5634 */ 5635 int ice_ptp_init_time(struct ice_hw *hw, u64 time) 5636 { 5637 u8 tmr_idx; 5638 int err; 5639 5640 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5641 5642 /* Source timers */ 5643 wr32(hw, GLTSYN_SHTIME_L(tmr_idx), lower_32_bits(time)); 5644 wr32(hw, GLTSYN_SHTIME_H(tmr_idx), upper_32_bits(time)); 5645 wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0); 5646 5647 /* PHY timers */ 5648 /* Fill Rx and Tx ports and send msg to PHY */ 5649 switch (ice_get_phy_model(hw)) { 5650 case ICE_PHY_ETH56G: 5651 err = ice_ptp_prep_phy_time_eth56g(hw, 5652 (u32)(time & 0xFFFFFFFF)); 5653 break; 5654 case ICE_PHY_E810: 5655 err = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF); 5656 break; 5657 case ICE_PHY_E82X: 5658 err = ice_ptp_prep_phy_time_e82x(hw, time & 0xFFFFFFFF); 5659 break; 5660 default: 5661 err = -EOPNOTSUPP; 5662 } 5663 5664 if (err) 5665 return err; 5666 5667 return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_TIME); 5668 } 5669 5670 /** 5671 * ice_ptp_write_incval - Program PHC with new increment value 5672 * @hw: pointer to HW struct 5673 * @incval: Source timer increment value per clock cycle 5674 * 5675 * Program the PHC with a new increment value. This requires a three-step 5676 * process: 5677 * 5678 * 1) Write the increment value to the source timer shadow registers 5679 * 2) Write the increment value to the PHY timer shadow registers 5680 * 3) Issue an ICE_PTP_INIT_INCVAL timer command to synchronously switch both 5681 * the source and port timers to the new increment value at the next clock 5682 * cycle. 5683 */ 5684 int ice_ptp_write_incval(struct ice_hw *hw, u64 incval) 5685 { 5686 u8 tmr_idx; 5687 int err; 5688 5689 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5690 5691 /* Shadow Adjust */ 5692 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), lower_32_bits(incval)); 5693 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), upper_32_bits(incval)); 5694 5695 switch (ice_get_phy_model(hw)) { 5696 case ICE_PHY_ETH56G: 5697 err = ice_ptp_prep_phy_incval_eth56g(hw, incval); 5698 break; 5699 case ICE_PHY_E810: 5700 err = ice_ptp_prep_phy_incval_e810(hw, incval); 5701 break; 5702 case ICE_PHY_E82X: 5703 err = ice_ptp_prep_phy_incval_e82x(hw, incval); 5704 break; 5705 default: 5706 err = -EOPNOTSUPP; 5707 } 5708 5709 if (err) 5710 return err; 5711 5712 return ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_INCVAL); 5713 } 5714 5715 /** 5716 * ice_ptp_write_incval_locked - Program new incval while holding semaphore 5717 * @hw: pointer to HW struct 5718 * @incval: Source timer increment value per clock cycle 5719 * 5720 * Program a new PHC incval while holding the PTP semaphore. 5721 */ 5722 int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval) 5723 { 5724 int err; 5725 5726 if (!ice_ptp_lock(hw)) 5727 return -EBUSY; 5728 5729 err = ice_ptp_write_incval(hw, incval); 5730 5731 ice_ptp_unlock(hw); 5732 5733 return err; 5734 } 5735 5736 /** 5737 * ice_ptp_adj_clock - Adjust PHC clock time atomically 5738 * @hw: pointer to HW struct 5739 * @adj: Adjustment in nanoseconds 5740 * 5741 * Perform an atomic adjustment of the PHC time by the specified number of 5742 * nanoseconds. This requires a three-step process: 5743 * 5744 * 1) Write the adjustment to the source timer shadow registers 5745 * 2) Write the adjustment to the PHY timer shadow registers 5746 * 3) Issue an ICE_PTP_ADJ_TIME timer command to synchronously apply the 5747 * adjustment to both the source and port timers at the next clock cycle. 5748 */ 5749 int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj) 5750 { 5751 u8 tmr_idx; 5752 int err; 5753 5754 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5755 5756 /* Write the desired clock adjustment into the GLTSYN_SHADJ register. 5757 * For an ICE_PTP_ADJ_TIME command, this set of registers represents 5758 * the value to add to the clock time. It supports subtraction by 5759 * interpreting the value as a 2's complement integer. 5760 */ 5761 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0); 5762 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj); 5763 5764 switch (ice_get_phy_model(hw)) { 5765 case ICE_PHY_ETH56G: 5766 err = ice_ptp_prep_phy_adj_eth56g(hw, adj); 5767 break; 5768 case ICE_PHY_E810: 5769 err = ice_ptp_prep_phy_adj_e810(hw, adj); 5770 break; 5771 case ICE_PHY_E82X: 5772 err = ice_ptp_prep_phy_adj_e82x(hw, adj); 5773 break; 5774 default: 5775 err = -EOPNOTSUPP; 5776 } 5777 5778 if (err) 5779 return err; 5780 5781 return ice_ptp_tmr_cmd(hw, ICE_PTP_ADJ_TIME); 5782 } 5783 5784 /** 5785 * ice_read_phy_tstamp - Read a PHY timestamp from the timestamo block 5786 * @hw: pointer to the HW struct 5787 * @block: the block to read from 5788 * @idx: the timestamp index to read 5789 * @tstamp: on return, the 40bit timestamp value 5790 * 5791 * Read a 40bit timestamp value out of the timestamp block. For E822 devices, 5792 * the block is the quad to read from. For E810 devices, the block is the 5793 * logical port to read from. 5794 */ 5795 int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp) 5796 { 5797 switch (ice_get_phy_model(hw)) { 5798 case ICE_PHY_ETH56G: 5799 return ice_read_ptp_tstamp_eth56g(hw, block, idx, tstamp); 5800 case ICE_PHY_E810: 5801 return ice_read_phy_tstamp_e810(hw, block, idx, tstamp); 5802 case ICE_PHY_E82X: 5803 return ice_read_phy_tstamp_e82x(hw, block, idx, tstamp); 5804 default: 5805 return -EOPNOTSUPP; 5806 } 5807 } 5808 5809 /** 5810 * ice_clear_phy_tstamp - Clear a timestamp from the timestamp block 5811 * @hw: pointer to the HW struct 5812 * @block: the block to read from 5813 * @idx: the timestamp index to reset 5814 * 5815 * Clear a timestamp from the timestamp block, discarding its value without 5816 * returning it. This resets the memory status bit for the timestamp index 5817 * allowing it to be reused for another timestamp in the future. 5818 * 5819 * For E822 devices, the block number is the PHY quad to clear from. For E810 5820 * devices, the block number is the logical port to clear from. 5821 * 5822 * This function must only be called on a timestamp index whose valid bit is 5823 * set according to ice_get_phy_tx_tstamp_ready(). 5824 */ 5825 int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx) 5826 { 5827 switch (ice_get_phy_model(hw)) { 5828 case ICE_PHY_ETH56G: 5829 return ice_clear_ptp_tstamp_eth56g(hw, block, idx); 5830 case ICE_PHY_E810: 5831 return ice_clear_phy_tstamp_e810(hw, block, idx); 5832 case ICE_PHY_E82X: 5833 return ice_clear_phy_tstamp_e82x(hw, block, idx); 5834 default: 5835 return -EOPNOTSUPP; 5836 } 5837 } 5838 5839 /** 5840 * ice_get_pf_c827_idx - find and return the C827 index for the current pf 5841 * @hw: pointer to the hw struct 5842 * @idx: index of the found C827 PHY 5843 * Return: 5844 * * 0 - success 5845 * * negative - failure 5846 */ 5847 static int ice_get_pf_c827_idx(struct ice_hw *hw, u8 *idx) 5848 { 5849 struct ice_aqc_get_link_topo cmd; 5850 u8 node_part_number; 5851 u16 node_handle; 5852 int status; 5853 u8 ctx; 5854 5855 if (hw->mac_type != ICE_MAC_E810) 5856 return -ENODEV; 5857 5858 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) { 5859 *idx = C827_0; 5860 return 0; 5861 } 5862 5863 memset(&cmd, 0, sizeof(cmd)); 5864 5865 ctx = ICE_AQC_LINK_TOPO_NODE_TYPE_PHY << ICE_AQC_LINK_TOPO_NODE_TYPE_S; 5866 ctx |= ICE_AQC_LINK_TOPO_NODE_CTX_PORT << ICE_AQC_LINK_TOPO_NODE_CTX_S; 5867 cmd.addr.topo_params.node_type_ctx = ctx; 5868 5869 status = ice_aq_get_netlist_node(hw, &cmd, &node_part_number, 5870 &node_handle); 5871 if (status || node_part_number != ICE_AQC_GET_LINK_TOPO_NODE_NR_C827) 5872 return -ENOENT; 5873 5874 if (node_handle == E810C_QSFP_C827_0_HANDLE) 5875 *idx = C827_0; 5876 else if (node_handle == E810C_QSFP_C827_1_HANDLE) 5877 *idx = C827_1; 5878 else 5879 return -EIO; 5880 5881 return 0; 5882 } 5883 5884 /** 5885 * ice_ptp_reset_ts_memory - Reset timestamp memory for all blocks 5886 * @hw: pointer to the HW struct 5887 */ 5888 void ice_ptp_reset_ts_memory(struct ice_hw *hw) 5889 { 5890 switch (ice_get_phy_model(hw)) { 5891 case ICE_PHY_ETH56G: 5892 ice_ptp_reset_ts_memory_eth56g(hw); 5893 break; 5894 case ICE_PHY_E82X: 5895 ice_ptp_reset_ts_memory_e82x(hw); 5896 break; 5897 case ICE_PHY_E810: 5898 default: 5899 return; 5900 } 5901 } 5902 5903 /** 5904 * ice_ptp_init_phc - Initialize PTP hardware clock 5905 * @hw: pointer to the HW struct 5906 * 5907 * Perform the steps required to initialize the PTP hardware clock. 5908 */ 5909 int ice_ptp_init_phc(struct ice_hw *hw) 5910 { 5911 u8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned; 5912 5913 /* Enable source clocks */ 5914 wr32(hw, GLTSYN_ENA(src_idx), GLTSYN_ENA_TSYN_ENA_M); 5915 5916 /* Clear event err indications for auxiliary pins */ 5917 (void)rd32(hw, GLTSYN_STAT(src_idx)); 5918 5919 switch (ice_get_phy_model(hw)) { 5920 case ICE_PHY_ETH56G: 5921 return ice_ptp_init_phc_eth56g(hw); 5922 case ICE_PHY_E810: 5923 return ice_ptp_init_phc_e810(hw); 5924 case ICE_PHY_E82X: 5925 return ice_ptp_init_phc_e82x(hw); 5926 default: 5927 return -EOPNOTSUPP; 5928 } 5929 } 5930 5931 /** 5932 * ice_get_phy_tx_tstamp_ready - Read PHY Tx memory status indication 5933 * @hw: pointer to the HW struct 5934 * @block: the timestamp block to check 5935 * @tstamp_ready: storage for the PHY Tx memory status information 5936 * 5937 * Check the PHY for Tx timestamp memory status. This reports a 64 bit value 5938 * which indicates which timestamps in the block may be captured. A set bit 5939 * means the timestamp can be read. An unset bit means the timestamp is not 5940 * ready and software should avoid reading the register. 5941 */ 5942 int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready) 5943 { 5944 switch (ice_get_phy_model(hw)) { 5945 case ICE_PHY_ETH56G: 5946 return ice_get_phy_tx_tstamp_ready_eth56g(hw, block, 5947 tstamp_ready); 5948 case ICE_PHY_E810: 5949 return ice_get_phy_tx_tstamp_ready_e810(hw, block, 5950 tstamp_ready); 5951 case ICE_PHY_E82X: 5952 return ice_get_phy_tx_tstamp_ready_e82x(hw, block, 5953 tstamp_ready); 5954 break; 5955 default: 5956 return -EOPNOTSUPP; 5957 } 5958 } 5959 5960 /** 5961 * ice_cgu_get_pin_desc_e823 - get pin description array 5962 * @hw: pointer to the hw struct 5963 * @input: if request is done against input or output pin 5964 * @size: number of inputs/outputs 5965 * 5966 * Return: pointer to pin description array associated to given hw. 5967 */ 5968 static const struct ice_cgu_pin_desc * 5969 ice_cgu_get_pin_desc_e823(struct ice_hw *hw, bool input, int *size) 5970 { 5971 static const struct ice_cgu_pin_desc *t; 5972 5973 if (hw->cgu_part_number == 5974 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032) { 5975 if (input) { 5976 t = ice_e823_zl_cgu_inputs; 5977 *size = ARRAY_SIZE(ice_e823_zl_cgu_inputs); 5978 } else { 5979 t = ice_e823_zl_cgu_outputs; 5980 *size = ARRAY_SIZE(ice_e823_zl_cgu_outputs); 5981 } 5982 } else if (hw->cgu_part_number == 5983 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384) { 5984 if (input) { 5985 t = ice_e823_si_cgu_inputs; 5986 *size = ARRAY_SIZE(ice_e823_si_cgu_inputs); 5987 } else { 5988 t = ice_e823_si_cgu_outputs; 5989 *size = ARRAY_SIZE(ice_e823_si_cgu_outputs); 5990 } 5991 } else { 5992 t = NULL; 5993 *size = 0; 5994 } 5995 5996 return t; 5997 } 5998 5999 /** 6000 * ice_cgu_get_pin_desc - get pin description array 6001 * @hw: pointer to the hw struct 6002 * @input: if request is done against input or output pins 6003 * @size: size of array returned by function 6004 * 6005 * Return: pointer to pin description array associated to given hw. 6006 */ 6007 static const struct ice_cgu_pin_desc * 6008 ice_cgu_get_pin_desc(struct ice_hw *hw, bool input, int *size) 6009 { 6010 const struct ice_cgu_pin_desc *t = NULL; 6011 6012 switch (hw->device_id) { 6013 case ICE_DEV_ID_E810C_SFP: 6014 if (input) { 6015 t = ice_e810t_sfp_cgu_inputs; 6016 *size = ARRAY_SIZE(ice_e810t_sfp_cgu_inputs); 6017 } else { 6018 t = ice_e810t_sfp_cgu_outputs; 6019 *size = ARRAY_SIZE(ice_e810t_sfp_cgu_outputs); 6020 } 6021 break; 6022 case ICE_DEV_ID_E810C_QSFP: 6023 if (input) { 6024 t = ice_e810t_qsfp_cgu_inputs; 6025 *size = ARRAY_SIZE(ice_e810t_qsfp_cgu_inputs); 6026 } else { 6027 t = ice_e810t_qsfp_cgu_outputs; 6028 *size = ARRAY_SIZE(ice_e810t_qsfp_cgu_outputs); 6029 } 6030 break; 6031 case ICE_DEV_ID_E823L_10G_BASE_T: 6032 case ICE_DEV_ID_E823L_1GBE: 6033 case ICE_DEV_ID_E823L_BACKPLANE: 6034 case ICE_DEV_ID_E823L_QSFP: 6035 case ICE_DEV_ID_E823L_SFP: 6036 case ICE_DEV_ID_E823C_10G_BASE_T: 6037 case ICE_DEV_ID_E823C_BACKPLANE: 6038 case ICE_DEV_ID_E823C_QSFP: 6039 case ICE_DEV_ID_E823C_SFP: 6040 case ICE_DEV_ID_E823C_SGMII: 6041 t = ice_cgu_get_pin_desc_e823(hw, input, size); 6042 break; 6043 default: 6044 break; 6045 } 6046 6047 return t; 6048 } 6049 6050 /** 6051 * ice_cgu_get_pin_type - get pin's type 6052 * @hw: pointer to the hw struct 6053 * @pin: pin index 6054 * @input: if request is done against input or output pin 6055 * 6056 * Return: type of a pin. 6057 */ 6058 enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool input) 6059 { 6060 const struct ice_cgu_pin_desc *t; 6061 int t_size; 6062 6063 t = ice_cgu_get_pin_desc(hw, input, &t_size); 6064 6065 if (!t) 6066 return 0; 6067 6068 if (pin >= t_size) 6069 return 0; 6070 6071 return t[pin].type; 6072 } 6073 6074 /** 6075 * ice_cgu_get_pin_freq_supp - get pin's supported frequency 6076 * @hw: pointer to the hw struct 6077 * @pin: pin index 6078 * @input: if request is done against input or output pin 6079 * @num: output number of supported frequencies 6080 * 6081 * Get frequency supported number and array of supported frequencies. 6082 * 6083 * Return: array of supported frequencies for given pin. 6084 */ 6085 struct dpll_pin_frequency * 6086 ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num) 6087 { 6088 const struct ice_cgu_pin_desc *t; 6089 int t_size; 6090 6091 *num = 0; 6092 t = ice_cgu_get_pin_desc(hw, input, &t_size); 6093 if (!t) 6094 return NULL; 6095 if (pin >= t_size) 6096 return NULL; 6097 *num = t[pin].freq_supp_num; 6098 6099 return t[pin].freq_supp; 6100 } 6101 6102 /** 6103 * ice_cgu_get_pin_name - get pin's name 6104 * @hw: pointer to the hw struct 6105 * @pin: pin index 6106 * @input: if request is done against input or output pin 6107 * 6108 * Return: 6109 * * null terminated char array with name 6110 * * NULL in case of failure 6111 */ 6112 const char *ice_cgu_get_pin_name(struct ice_hw *hw, u8 pin, bool input) 6113 { 6114 const struct ice_cgu_pin_desc *t; 6115 int t_size; 6116 6117 t = ice_cgu_get_pin_desc(hw, input, &t_size); 6118 6119 if (!t) 6120 return NULL; 6121 6122 if (pin >= t_size) 6123 return NULL; 6124 6125 return t[pin].name; 6126 } 6127 6128 /** 6129 * ice_get_cgu_state - get the state of the DPLL 6130 * @hw: pointer to the hw struct 6131 * @dpll_idx: Index of internal DPLL unit 6132 * @last_dpll_state: last known state of DPLL 6133 * @pin: pointer to a buffer for returning currently active pin 6134 * @ref_state: reference clock state 6135 * @eec_mode: eec mode of the DPLL 6136 * @phase_offset: pointer to a buffer for returning phase offset 6137 * @dpll_state: state of the DPLL (output) 6138 * 6139 * This function will read the state of the DPLL(dpll_idx). Non-null 6140 * 'pin', 'ref_state', 'eec_mode' and 'phase_offset' parameters are used to 6141 * retrieve currently active pin, state, mode and phase_offset respectively. 6142 * 6143 * Return: state of the DPLL 6144 */ 6145 int ice_get_cgu_state(struct ice_hw *hw, u8 dpll_idx, 6146 enum dpll_lock_status last_dpll_state, u8 *pin, 6147 u8 *ref_state, u8 *eec_mode, s64 *phase_offset, 6148 enum dpll_lock_status *dpll_state) 6149 { 6150 u8 hw_ref_state, hw_dpll_state, hw_eec_mode, hw_config; 6151 s64 hw_phase_offset; 6152 int status; 6153 6154 status = ice_aq_get_cgu_dpll_status(hw, dpll_idx, &hw_ref_state, 6155 &hw_dpll_state, &hw_config, 6156 &hw_phase_offset, &hw_eec_mode); 6157 if (status) 6158 return status; 6159 6160 if (pin) 6161 /* current ref pin in dpll_state_refsel_status_X register */ 6162 *pin = hw_config & ICE_AQC_GET_CGU_DPLL_CONFIG_CLK_REF_SEL; 6163 if (phase_offset) 6164 *phase_offset = hw_phase_offset; 6165 if (ref_state) 6166 *ref_state = hw_ref_state; 6167 if (eec_mode) 6168 *eec_mode = hw_eec_mode; 6169 if (!dpll_state) 6170 return 0; 6171 6172 /* According to ZL DPLL documentation, once state reach LOCKED_HO_ACQ 6173 * it would never return to FREERUN. This aligns to ITU-T G.781 6174 * Recommendation. We cannot report HOLDOVER as HO memory is cleared 6175 * while switching to another reference. 6176 * Only for situations where previous state was either: "LOCKED without 6177 * HO_ACQ" or "HOLDOVER" we actually back to FREERUN. 6178 */ 6179 if (hw_dpll_state & ICE_AQC_GET_CGU_DPLL_STATUS_STATE_LOCK) { 6180 if (hw_dpll_state & ICE_AQC_GET_CGU_DPLL_STATUS_STATE_HO_READY) 6181 *dpll_state = DPLL_LOCK_STATUS_LOCKED_HO_ACQ; 6182 else 6183 *dpll_state = DPLL_LOCK_STATUS_LOCKED; 6184 } else if (last_dpll_state == DPLL_LOCK_STATUS_LOCKED_HO_ACQ || 6185 last_dpll_state == DPLL_LOCK_STATUS_HOLDOVER) { 6186 *dpll_state = DPLL_LOCK_STATUS_HOLDOVER; 6187 } else { 6188 *dpll_state = DPLL_LOCK_STATUS_UNLOCKED; 6189 } 6190 6191 return 0; 6192 } 6193 6194 /** 6195 * ice_get_cgu_rclk_pin_info - get info on available recovered clock pins 6196 * @hw: pointer to the hw struct 6197 * @base_idx: returns index of first recovered clock pin on device 6198 * @pin_num: returns number of recovered clock pins available on device 6199 * 6200 * Based on hw provide caller info about recovery clock pins available on the 6201 * board. 6202 * 6203 * Return: 6204 * * 0 - success, information is valid 6205 * * negative - failure, information is not valid 6206 */ 6207 int ice_get_cgu_rclk_pin_info(struct ice_hw *hw, u8 *base_idx, u8 *pin_num) 6208 { 6209 u8 phy_idx; 6210 int ret; 6211 6212 switch (hw->device_id) { 6213 case ICE_DEV_ID_E810C_SFP: 6214 case ICE_DEV_ID_E810C_QSFP: 6215 6216 ret = ice_get_pf_c827_idx(hw, &phy_idx); 6217 if (ret) 6218 return ret; 6219 *base_idx = E810T_CGU_INPUT_C827(phy_idx, ICE_RCLKA_PIN); 6220 *pin_num = ICE_E810_RCLK_PINS_NUM; 6221 ret = 0; 6222 break; 6223 case ICE_DEV_ID_E823L_10G_BASE_T: 6224 case ICE_DEV_ID_E823L_1GBE: 6225 case ICE_DEV_ID_E823L_BACKPLANE: 6226 case ICE_DEV_ID_E823L_QSFP: 6227 case ICE_DEV_ID_E823L_SFP: 6228 case ICE_DEV_ID_E823C_10G_BASE_T: 6229 case ICE_DEV_ID_E823C_BACKPLANE: 6230 case ICE_DEV_ID_E823C_QSFP: 6231 case ICE_DEV_ID_E823C_SFP: 6232 case ICE_DEV_ID_E823C_SGMII: 6233 *pin_num = ICE_E82X_RCLK_PINS_NUM; 6234 ret = 0; 6235 if (hw->cgu_part_number == 6236 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032) 6237 *base_idx = ZL_REF1P; 6238 else if (hw->cgu_part_number == 6239 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384) 6240 *base_idx = SI_REF1P; 6241 else 6242 ret = -ENODEV; 6243 6244 break; 6245 default: 6246 ret = -ENODEV; 6247 break; 6248 } 6249 6250 return ret; 6251 } 6252 6253 /** 6254 * ice_cgu_get_output_pin_state_caps - get output pin state capabilities 6255 * @hw: pointer to the hw struct 6256 * @pin_id: id of a pin 6257 * @caps: capabilities to modify 6258 * 6259 * Return: 6260 * * 0 - success, state capabilities were modified 6261 * * negative - failure, capabilities were not modified 6262 */ 6263 int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw, u8 pin_id, 6264 unsigned long *caps) 6265 { 6266 bool can_change = true; 6267 6268 switch (hw->device_id) { 6269 case ICE_DEV_ID_E810C_SFP: 6270 if (pin_id == ZL_OUT2 || pin_id == ZL_OUT3) 6271 can_change = false; 6272 break; 6273 case ICE_DEV_ID_E810C_QSFP: 6274 if (pin_id == ZL_OUT2 || pin_id == ZL_OUT3 || pin_id == ZL_OUT4) 6275 can_change = false; 6276 break; 6277 case ICE_DEV_ID_E823L_10G_BASE_T: 6278 case ICE_DEV_ID_E823L_1GBE: 6279 case ICE_DEV_ID_E823L_BACKPLANE: 6280 case ICE_DEV_ID_E823L_QSFP: 6281 case ICE_DEV_ID_E823L_SFP: 6282 case ICE_DEV_ID_E823C_10G_BASE_T: 6283 case ICE_DEV_ID_E823C_BACKPLANE: 6284 case ICE_DEV_ID_E823C_QSFP: 6285 case ICE_DEV_ID_E823C_SFP: 6286 case ICE_DEV_ID_E823C_SGMII: 6287 if (hw->cgu_part_number == 6288 ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032 && 6289 pin_id == ZL_OUT2) 6290 can_change = false; 6291 else if (hw->cgu_part_number == 6292 ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384 && 6293 pin_id == SI_OUT1) 6294 can_change = false; 6295 break; 6296 default: 6297 return -EINVAL; 6298 } 6299 if (can_change) 6300 *caps |= DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE; 6301 else 6302 *caps &= ~DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE; 6303 6304 return 0; 6305 } 6306