1a4511307SFan Gong /* SPDX-License-Identifier: GPL-2.0 */ 2a4511307SFan Gong /* Copyright (c) Huawei Technologies Co., Ltd. 2025. All rights reserved. */ 3a4511307SFan Gong 4a4511307SFan Gong #ifndef _HINIC3_CSR_H_ 5a4511307SFan Gong #define _HINIC3_CSR_H_ 6a4511307SFan Gong 7a4511307SFan Gong #define HINIC3_CFG_REGS_FLAG 0x40000000 8a4511307SFan Gong #define HINIC3_REGS_FLAG_MASK 0x3FFFFFFF 9a4511307SFan Gong 10a4511307SFan Gong #define HINIC3_VF_CFG_REG_OFFSET 0x2000 11a4511307SFan Gong 12a4511307SFan Gong /* HW interface registers */ 13a4511307SFan Gong #define HINIC3_CSR_FUNC_ATTR0_ADDR (HINIC3_CFG_REGS_FLAG + 0x0) 14a4511307SFan Gong #define HINIC3_CSR_FUNC_ATTR1_ADDR (HINIC3_CFG_REGS_FLAG + 0x4) 15a4511307SFan Gong #define HINIC3_CSR_FUNC_ATTR2_ADDR (HINIC3_CFG_REGS_FLAG + 0x8) 16a4511307SFan Gong #define HINIC3_CSR_FUNC_ATTR3_ADDR (HINIC3_CFG_REGS_FLAG + 0xC) 17a4511307SFan Gong #define HINIC3_CSR_FUNC_ATTR4_ADDR (HINIC3_CFG_REGS_FLAG + 0x10) 18a4511307SFan Gong #define HINIC3_CSR_FUNC_ATTR5_ADDR (HINIC3_CFG_REGS_FLAG + 0x14) 19a4511307SFan Gong #define HINIC3_CSR_FUNC_ATTR6_ADDR (HINIC3_CFG_REGS_FLAG + 0x18) 20a4511307SFan Gong 21a4511307SFan Gong #define HINIC3_FUNC_CSR_MAILBOX_DATA_OFF 0x80 22a4511307SFan Gong #define HINIC3_FUNC_CSR_MAILBOX_CONTROL_OFF (HINIC3_CFG_REGS_FLAG + 0x0100) 23a4511307SFan Gong #define HINIC3_FUNC_CSR_MAILBOX_INT_OFF (HINIC3_CFG_REGS_FLAG + 0x0104) 24a4511307SFan Gong #define HINIC3_FUNC_CSR_MAILBOX_RESULT_H_OFF (HINIC3_CFG_REGS_FLAG + 0x0108) 25a4511307SFan Gong #define HINIC3_FUNC_CSR_MAILBOX_RESULT_L_OFF (HINIC3_CFG_REGS_FLAG + 0x010C) 26a4511307SFan Gong 27a4511307SFan Gong #define HINIC3_CSR_DMA_ATTR_TBL_ADDR (HINIC3_CFG_REGS_FLAG + 0x380) 28a4511307SFan Gong #define HINIC3_CSR_DMA_ATTR_INDIR_IDX_ADDR (HINIC3_CFG_REGS_FLAG + 0x390) 29a4511307SFan Gong 30a4511307SFan Gong /* MSI-X registers */ 31a4511307SFan Gong #define HINIC3_CSR_FUNC_MSI_CLR_WR_ADDR (HINIC3_CFG_REGS_FLAG + 0x58) 32a4511307SFan Gong 33a4511307SFan Gong #define HINIC3_MSI_CLR_INDIR_RESEND_TIMER_CLR_MASK BIT(0) 34a4511307SFan Gong #define HINIC3_MSI_CLR_INDIR_INT_MSK_SET_MASK BIT(1) 35a4511307SFan Gong #define HINIC3_MSI_CLR_INDIR_INT_MSK_CLR_MASK BIT(2) 36a4511307SFan Gong #define HINIC3_MSI_CLR_INDIR_AUTO_MSK_SET_MASK BIT(3) 37a4511307SFan Gong #define HINIC3_MSI_CLR_INDIR_AUTO_MSK_CLR_MASK BIT(4) 38a4511307SFan Gong #define HINIC3_MSI_CLR_INDIR_SIMPLE_INDIR_IDX_MASK GENMASK(31, 22) 39a4511307SFan Gong #define HINIC3_MSI_CLR_INDIR_SET(val, member) \ 40a4511307SFan Gong FIELD_PREP(HINIC3_MSI_CLR_INDIR_##member##_MASK, val) 41a4511307SFan Gong 42a4511307SFan Gong /* EQ registers */ 43a4511307SFan Gong #define HINIC3_AEQ_INDIR_IDX_ADDR (HINIC3_CFG_REGS_FLAG + 0x210) 44*c4bbfd9bSFan Gong #define HINIC3_CEQ_INDIR_IDX_ADDR (HINIC3_CFG_REGS_FLAG + 0x290) 45a4511307SFan Gong 46a4511307SFan Gong #define HINIC3_EQ_INDIR_IDX_ADDR(type) \ 47*c4bbfd9bSFan Gong ((type == HINIC3_AEQ) ? HINIC3_AEQ_INDIR_IDX_ADDR : \ 48*c4bbfd9bSFan Gong HINIC3_CEQ_INDIR_IDX_ADDR) 49a4511307SFan Gong 50a4511307SFan Gong #define HINIC3_AEQ_MTT_OFF_BASE_ADDR (HINIC3_CFG_REGS_FLAG + 0x240) 51*c4bbfd9bSFan Gong #define HINIC3_CEQ_MTT_OFF_BASE_ADDR (HINIC3_CFG_REGS_FLAG + 0x2C0) 52a4511307SFan Gong 53a4511307SFan Gong #define HINIC3_CSR_EQ_PAGE_OFF_STRIDE 8 54a4511307SFan Gong 55a4511307SFan Gong #define HINIC3_AEQ_HI_PHYS_ADDR_REG(pg_num) \ 56a4511307SFan Gong (HINIC3_AEQ_MTT_OFF_BASE_ADDR + (pg_num) * \ 57a4511307SFan Gong HINIC3_CSR_EQ_PAGE_OFF_STRIDE) 58a4511307SFan Gong 59a4511307SFan Gong #define HINIC3_AEQ_LO_PHYS_ADDR_REG(pg_num) \ 60a4511307SFan Gong (HINIC3_AEQ_MTT_OFF_BASE_ADDR + (pg_num) * \ 61a4511307SFan Gong HINIC3_CSR_EQ_PAGE_OFF_STRIDE + 4) 62a4511307SFan Gong 63*c4bbfd9bSFan Gong #define HINIC3_CEQ_HI_PHYS_ADDR_REG(pg_num) \ 64*c4bbfd9bSFan Gong (HINIC3_CEQ_MTT_OFF_BASE_ADDR + (pg_num) * \ 65*c4bbfd9bSFan Gong HINIC3_CSR_EQ_PAGE_OFF_STRIDE) 66*c4bbfd9bSFan Gong 67*c4bbfd9bSFan Gong #define HINIC3_CEQ_LO_PHYS_ADDR_REG(pg_num) \ 68*c4bbfd9bSFan Gong (HINIC3_CEQ_MTT_OFF_BASE_ADDR + (pg_num) * \ 69*c4bbfd9bSFan Gong HINIC3_CSR_EQ_PAGE_OFF_STRIDE + 4) 70*c4bbfd9bSFan Gong 71a4511307SFan Gong #define HINIC3_CSR_AEQ_CTRL_0_ADDR (HINIC3_CFG_REGS_FLAG + 0x200) 72a4511307SFan Gong #define HINIC3_CSR_AEQ_CTRL_1_ADDR (HINIC3_CFG_REGS_FLAG + 0x204) 73a4511307SFan Gong #define HINIC3_CSR_AEQ_PROD_IDX_ADDR (HINIC3_CFG_REGS_FLAG + 0x20C) 74a4511307SFan Gong #define HINIC3_CSR_AEQ_CI_SIMPLE_INDIR_ADDR (HINIC3_CFG_REGS_FLAG + 0x50) 75a4511307SFan Gong 76*c4bbfd9bSFan Gong #define HINIC3_CSR_CEQ_PROD_IDX_ADDR (HINIC3_CFG_REGS_FLAG + 0x28c) 77*c4bbfd9bSFan Gong #define HINIC3_CSR_CEQ_CI_SIMPLE_INDIR_ADDR (HINIC3_CFG_REGS_FLAG + 0x54) 78*c4bbfd9bSFan Gong 79a4511307SFan Gong #endif 80